github.com/shogo82148/std@v1.22.1-0.20240327122250-4e474527810c/cmd/internal/obj/ppc64/a.out.go (about) 1 // cmd/9c/9.out.h from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import "github.com/shogo82148/std/cmd/internal/obj" 33 34 /* 35 * powerpc 64 36 */ 37 const ( 38 NSNAME = 8 39 NSYM = 50 40 NREG = 32 41 NFREG = 32 42 ) 43 44 const ( 45 /* RBasePPC64 = 4096 */ 46 /* R0=4096 ... R31=4127 */ 47 REG_R0 = obj.RBasePPC64 + iota 48 REG_R1 49 REG_R2 50 REG_R3 51 REG_R4 52 REG_R5 53 REG_R6 54 REG_R7 55 REG_R8 56 REG_R9 57 REG_R10 58 REG_R11 59 REG_R12 60 REG_R13 61 REG_R14 62 REG_R15 63 REG_R16 64 REG_R17 65 REG_R18 66 REG_R19 67 REG_R20 68 REG_R21 69 REG_R22 70 REG_R23 71 REG_R24 72 REG_R25 73 REG_R26 74 REG_R27 75 REG_R28 76 REG_R29 77 REG_R30 78 REG_R31 79 80 // CR bits. Use Book 1, chapter 2 naming for bits. Keep aligned to 32 81 REG_CR0LT 82 REG_CR0GT 83 REG_CR0EQ 84 REG_CR0SO 85 REG_CR1LT 86 REG_CR1GT 87 REG_CR1EQ 88 REG_CR1SO 89 REG_CR2LT 90 REG_CR2GT 91 REG_CR2EQ 92 REG_CR2SO 93 REG_CR3LT 94 REG_CR3GT 95 REG_CR3EQ 96 REG_CR3SO 97 REG_CR4LT 98 REG_CR4GT 99 REG_CR4EQ 100 REG_CR4SO 101 REG_CR5LT 102 REG_CR5GT 103 REG_CR5EQ 104 REG_CR5SO 105 REG_CR6LT 106 REG_CR6GT 107 REG_CR6EQ 108 REG_CR6SO 109 REG_CR7LT 110 REG_CR7GT 111 REG_CR7EQ 112 REG_CR7SO 113 114 /* Align FPR and VSR vectors such that when masked with 0x3F they produce 115 an equivalent VSX register. */ 116 /* F0=4160 ... F31=4191 */ 117 REG_F0 118 REG_F1 119 REG_F2 120 REG_F3 121 REG_F4 122 REG_F5 123 REG_F6 124 REG_F7 125 REG_F8 126 REG_F9 127 REG_F10 128 REG_F11 129 REG_F12 130 REG_F13 131 REG_F14 132 REG_F15 133 REG_F16 134 REG_F17 135 REG_F18 136 REG_F19 137 REG_F20 138 REG_F21 139 REG_F22 140 REG_F23 141 REG_F24 142 REG_F25 143 REG_F26 144 REG_F27 145 REG_F28 146 REG_F29 147 REG_F30 148 REG_F31 149 150 /* V0=4192 ... V31=4223 */ 151 REG_V0 152 REG_V1 153 REG_V2 154 REG_V3 155 REG_V4 156 REG_V5 157 REG_V6 158 REG_V7 159 REG_V8 160 REG_V9 161 REG_V10 162 REG_V11 163 REG_V12 164 REG_V13 165 REG_V14 166 REG_V15 167 REG_V16 168 REG_V17 169 REG_V18 170 REG_V19 171 REG_V20 172 REG_V21 173 REG_V22 174 REG_V23 175 REG_V24 176 REG_V25 177 REG_V26 178 REG_V27 179 REG_V28 180 REG_V29 181 REG_V30 182 REG_V31 183 184 /* VS0=4224 ... VS63=4287 */ 185 REG_VS0 186 REG_VS1 187 REG_VS2 188 REG_VS3 189 REG_VS4 190 REG_VS5 191 REG_VS6 192 REG_VS7 193 REG_VS8 194 REG_VS9 195 REG_VS10 196 REG_VS11 197 REG_VS12 198 REG_VS13 199 REG_VS14 200 REG_VS15 201 REG_VS16 202 REG_VS17 203 REG_VS18 204 REG_VS19 205 REG_VS20 206 REG_VS21 207 REG_VS22 208 REG_VS23 209 REG_VS24 210 REG_VS25 211 REG_VS26 212 REG_VS27 213 REG_VS28 214 REG_VS29 215 REG_VS30 216 REG_VS31 217 REG_VS32 218 REG_VS33 219 REG_VS34 220 REG_VS35 221 REG_VS36 222 REG_VS37 223 REG_VS38 224 REG_VS39 225 REG_VS40 226 REG_VS41 227 REG_VS42 228 REG_VS43 229 REG_VS44 230 REG_VS45 231 REG_VS46 232 REG_VS47 233 REG_VS48 234 REG_VS49 235 REG_VS50 236 REG_VS51 237 REG_VS52 238 REG_VS53 239 REG_VS54 240 REG_VS55 241 REG_VS56 242 REG_VS57 243 REG_VS58 244 REG_VS59 245 REG_VS60 246 REG_VS61 247 REG_VS62 248 REG_VS63 249 250 REG_CR0 251 REG_CR1 252 REG_CR2 253 REG_CR3 254 REG_CR4 255 REG_CR5 256 REG_CR6 257 REG_CR7 258 259 // MMA accumulator registers, these shadow VSR 0-31 260 // e.g MMAx shadows VSRx*4-VSRx*4+3 or 261 // MMA0 shadows VSR0-VSR3 262 REG_A0 263 REG_A1 264 REG_A2 265 REG_A3 266 REG_A4 267 REG_A5 268 REG_A6 269 REG_A7 270 271 REG_MSR 272 REG_FPSCR 273 REG_CR 274 275 REG_SPECIAL = REG_CR0 276 277 REG_CRBIT0 = REG_CR0LT 278 279 REG_SPR0 = obj.RBasePPC64 + 1024 280 281 REG_XER = REG_SPR0 + 1 282 REG_LR = REG_SPR0 + 8 283 REG_CTR = REG_SPR0 + 9 284 285 REGZERO = REG_R0 286 REGSP = REG_R1 287 REGSB = REG_R2 288 REGRET = REG_R3 289 REGARG = -1 290 REGRT1 = REG_R20 291 REGRT2 = REG_R21 292 REGMIN = REG_R7 293 REGCTXT = REG_R11 294 REGTLS = REG_R13 295 REGMAX = REG_R27 296 REGEXT = REG_R30 297 REGG = REG_R30 298 REGTMP = REG_R31 299 FREGRET = REG_F0 300 FREGMIN = REG_F17 301 FREGMAX = REG_F26 302 FREGEXT = REG_F26 303 ) 304 305 // OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI 306 // https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture 307 var PPC64DWARFRegisters = map[int16]int16{} 308 309 /* 310 * GENERAL: 311 * 312 * compiler allocates R3 up as temps 313 * compiler allocates register variables R7-R27 314 * compiler allocates external registers R30 down 315 * 316 * compiler allocates register variables F17-F26 317 * compiler allocates external registers F26 down 318 */ 319 const ( 320 BIG = 32768 - 8 321 ) 322 323 const ( 324 /* mark flags */ 325 LABEL = 1 << 0 326 LEAF = 1 << 1 327 FLOAT = 1 << 2 328 BRANCH = 1 << 3 329 LOAD = 1 << 4 330 FCMP = 1 << 5 331 SYNC = 1 << 6 332 LIST = 1 << 7 333 FOLL = 1 << 8 334 NOSCHED = 1 << 9 335 PFX_X64B = 1 << 10 336 ) 337 338 const ( 339 BI_CR0 = 0 340 BI_CR1 = 4 341 BI_CR2 = 8 342 BI_CR3 = 12 343 BI_CR4 = 16 344 BI_CR5 = 20 345 BI_CR6 = 24 346 BI_CR7 = 28 347 BI_LT = 0 348 BI_GT = 1 349 BI_EQ = 2 350 BI_FU = 3 351 ) 352 353 const ( 354 BO_ALWAYS = 20 355 BO_BCTR = 16 356 BO_NOTBCTR = 18 357 BO_BCR = 12 358 BO_BCRBCTR = 8 359 BO_NOTBCR = 4 360 ) 361 362 const ( 363 C_COND_LT = iota 364 C_COND_GT 365 C_COND_EQ 366 C_COND_SO 367 ) 368 369 const ( 370 C_NONE = iota 371 C_REGP 372 C_REG 373 C_FREGP 374 C_FREG 375 C_VREG 376 C_VSREGP 377 C_VSREG 378 C_CREG 379 C_CRBIT 380 C_SPR 381 C_AREG 382 C_ZCON 383 C_U1CON 384 C_U2CON 385 C_U3CON 386 C_U4CON 387 C_U5CON 388 C_U8CON 389 C_U15CON 390 C_S16CON 391 C_U16CON 392 C_16CON 393 C_U31CON 394 C_S32CON 395 C_U32CON 396 C_32CON 397 C_S34CON 398 C_64CON 399 C_SACON 400 C_LACON 401 C_DACON 402 C_BRA 403 C_BRAPIC 404 C_ZOREG 405 C_SOREG 406 C_LOREG 407 C_XOREG 408 C_FPSCR 409 C_LR 410 C_CTR 411 C_ANY 412 C_GOK 413 C_ADDR 414 C_TLS_LE 415 C_TLS_IE 416 C_TEXTSIZE 417 418 C_NCLASS 419 ) 420 421 const ( 422 AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota 423 AADDCC 424 AADDIS 425 AADDV 426 AADDVCC 427 AADDC 428 AADDCCC 429 AADDCV 430 AADDCVCC 431 AADDME 432 AADDMECC 433 AADDMEVCC 434 AADDMEV 435 AADDE 436 AADDECC 437 AADDEVCC 438 AADDEV 439 AADDZE 440 AADDZECC 441 AADDZEVCC 442 AADDZEV 443 AADDEX 444 AAND 445 AANDCC 446 AANDN 447 AANDNCC 448 AANDISCC 449 ABC 450 ABCL 451 ABEQ 452 ABGE 453 ABGT 454 ABLE 455 ABLT 456 ABNE 457 ABVC 458 ABVS 459 ABDNZ 460 ABDZ 461 ACMP 462 ACMPU 463 ACMPEQB 464 ACNTLZW 465 ACNTLZWCC 466 ACRAND 467 ACRANDN 468 ACREQV 469 ACRNAND 470 ACRNOR 471 ACROR 472 ACRORN 473 ACRXOR 474 ADIVW 475 ADIVWCC 476 ADIVWVCC 477 ADIVWV 478 ADIVWU 479 ADIVWUCC 480 ADIVWUVCC 481 ADIVWUV 482 AMODUD 483 AMODUW 484 AMODSD 485 AMODSW 486 AEQV 487 AEQVCC 488 AEXTSB 489 AEXTSBCC 490 AEXTSH 491 AEXTSHCC 492 AFABS 493 AFABSCC 494 AFADD 495 AFADDCC 496 AFADDS 497 AFADDSCC 498 AFCMPO 499 AFCMPU 500 AFCTIW 501 AFCTIWCC 502 AFCTIWZ 503 AFCTIWZCC 504 AFDIV 505 AFDIVCC 506 AFDIVS 507 AFDIVSCC 508 AFMADD 509 AFMADDCC 510 AFMADDS 511 AFMADDSCC 512 AFMOVD 513 AFMOVDCC 514 AFMOVDU 515 AFMOVS 516 AFMOVSU 517 AFMOVSX 518 AFMOVSZ 519 AFMSUB 520 AFMSUBCC 521 AFMSUBS 522 AFMSUBSCC 523 AFMUL 524 AFMULCC 525 AFMULS 526 AFMULSCC 527 AFNABS 528 AFNABSCC 529 AFNEG 530 AFNEGCC 531 AFNMADD 532 AFNMADDCC 533 AFNMADDS 534 AFNMADDSCC 535 AFNMSUB 536 AFNMSUBCC 537 AFNMSUBS 538 AFNMSUBSCC 539 AFRSP 540 AFRSPCC 541 AFSUB 542 AFSUBCC 543 AFSUBS 544 AFSUBSCC 545 AISEL 546 AMOVMW 547 ALBAR 548 ALHAR 549 ALSW 550 ALWAR 551 ALWSYNC 552 AMOVDBR 553 AMOVWBR 554 AMOVB 555 AMOVBU 556 AMOVBZ 557 AMOVBZU 558 AMOVH 559 AMOVHBR 560 AMOVHU 561 AMOVHZ 562 AMOVHZU 563 AMOVW 564 AMOVWU 565 AMOVFL 566 AMOVCRFS 567 AMTFSB0 568 AMTFSB0CC 569 AMTFSB1 570 AMTFSB1CC 571 AMULHW 572 AMULHWCC 573 AMULHWU 574 AMULHWUCC 575 AMULLW 576 AMULLWCC 577 AMULLWVCC 578 AMULLWV 579 ANAND 580 ANANDCC 581 ANEG 582 ANEGCC 583 ANEGVCC 584 ANEGV 585 ANOR 586 ANORCC 587 AOR 588 AORCC 589 AORN 590 AORNCC 591 AORIS 592 AREM 593 AREMU 594 ARFI 595 ARLWMI 596 ARLWMICC 597 ARLWNM 598 ARLWNMCC 599 ACLRLSLWI 600 ASLW 601 ASLWCC 602 ASRW 603 ASRAW 604 ASRAWCC 605 ASRWCC 606 ASTBCCC 607 ASTHCCC 608 ASTSW 609 ASTWCCC 610 ASUB 611 ASUBCC 612 ASUBVCC 613 ASUBC 614 ASUBCCC 615 ASUBCV 616 ASUBCVCC 617 ASUBME 618 ASUBMECC 619 ASUBMEVCC 620 ASUBMEV 621 ASUBV 622 ASUBE 623 ASUBECC 624 ASUBEV 625 ASUBEVCC 626 ASUBZE 627 ASUBZECC 628 ASUBZEVCC 629 ASUBZEV 630 ASYNC 631 AXOR 632 AXORCC 633 AXORIS 634 635 ADCBF 636 ADCBI 637 ADCBST 638 ADCBT 639 ADCBTST 640 ADCBZ 641 AEIEIO 642 AICBI 643 AISYNC 644 APTESYNC 645 ATLBIE 646 ATLBIEL 647 ATLBSYNC 648 ATW 649 650 ASYSCALL 651 AWORD 652 653 ARFCI 654 655 AFCPSGN 656 AFCPSGNCC 657 /* optional on 32-bit */ 658 AFRES 659 AFRESCC 660 AFRIM 661 AFRIMCC 662 AFRIP 663 AFRIPCC 664 AFRIZ 665 AFRIZCC 666 AFRIN 667 AFRINCC 668 AFRSQRTE 669 AFRSQRTECC 670 AFSEL 671 AFSELCC 672 AFSQRT 673 AFSQRTCC 674 AFSQRTS 675 AFSQRTSCC 676 677 ACNTLZD 678 ACNTLZDCC 679 ACMPW 680 ACMPWU 681 ACMPB 682 AFTDIV 683 AFTSQRT 684 ADIVD 685 ADIVDCC 686 ADIVDE 687 ADIVDECC 688 ADIVDEU 689 ADIVDEUCC 690 ADIVDVCC 691 ADIVDV 692 ADIVDU 693 ADIVDUCC 694 ADIVDUVCC 695 ADIVDUV 696 AEXTSW 697 AEXTSWCC 698 /* AFCFIW; AFCFIWCC */ 699 AFCFID 700 AFCFIDCC 701 AFCFIDU 702 AFCFIDUCC 703 AFCFIDS 704 AFCFIDSCC 705 AFCTID 706 AFCTIDCC 707 AFCTIDZ 708 AFCTIDZCC 709 ALDAR 710 AMOVD 711 AMOVDU 712 AMOVWZ 713 AMOVWZU 714 AMULHD 715 AMULHDCC 716 AMULHDU 717 AMULHDUCC 718 AMULLD 719 AMULLDCC 720 AMULLDVCC 721 AMULLDV 722 ARFID 723 ARLDMI 724 ARLDMICC 725 ARLDIMI 726 ARLDIMICC 727 ARLDC 728 ARLDCCC 729 ARLDCR 730 ARLDCRCC 731 ARLDICR 732 ARLDICRCC 733 ARLDCL 734 ARLDCLCC 735 ARLDICL 736 ARLDICLCC 737 ARLDIC 738 ARLDICCC 739 ACLRLSLDI 740 AROTL 741 AROTLW 742 ASLBIA 743 ASLBIE 744 ASLBMFEE 745 ASLBMFEV 746 ASLBMTE 747 ASLD 748 ASLDCC 749 ASRD 750 ASRAD 751 ASRADCC 752 ASRDCC 753 AEXTSWSLI 754 AEXTSWSLICC 755 ASTDCCC 756 ATD 757 ASETB 758 759 /* 64-bit pseudo operation */ 760 ADWORD 761 AREMD 762 AREMDU 763 764 /* more 64-bit operations */ 765 AHRFID 766 APOPCNTD 767 APOPCNTW 768 APOPCNTB 769 ACNTTZW 770 ACNTTZWCC 771 ACNTTZD 772 ACNTTZDCC 773 ACOPY 774 APASTECC 775 ADARN 776 AMADDHD 777 AMADDHDU 778 AMADDLD 779 780 /* Vector */ 781 ALVEBX 782 ALVEHX 783 ALVEWX 784 ALVX 785 ALVXL 786 ALVSL 787 ALVSR 788 ASTVEBX 789 ASTVEHX 790 ASTVEWX 791 ASTVX 792 ASTVXL 793 AVAND 794 AVANDC 795 AVNAND 796 AVOR 797 AVORC 798 AVNOR 799 AVXOR 800 AVEQV 801 AVADDUM 802 AVADDUBM 803 AVADDUHM 804 AVADDUWM 805 AVADDUDM 806 AVADDUQM 807 AVADDCU 808 AVADDCUQ 809 AVADDCUW 810 AVADDUS 811 AVADDUBS 812 AVADDUHS 813 AVADDUWS 814 AVADDSS 815 AVADDSBS 816 AVADDSHS 817 AVADDSWS 818 AVADDE 819 AVADDEUQM 820 AVADDECUQ 821 AVSUBUM 822 AVSUBUBM 823 AVSUBUHM 824 AVSUBUWM 825 AVSUBUDM 826 AVSUBUQM 827 AVSUBCU 828 AVSUBCUQ 829 AVSUBCUW 830 AVSUBUS 831 AVSUBUBS 832 AVSUBUHS 833 AVSUBUWS 834 AVSUBSS 835 AVSUBSBS 836 AVSUBSHS 837 AVSUBSWS 838 AVSUBE 839 AVSUBEUQM 840 AVSUBECUQ 841 AVMULESB 842 AVMULOSB 843 AVMULEUB 844 AVMULOUB 845 AVMULESH 846 AVMULOSH 847 AVMULEUH 848 AVMULOUH 849 AVMULESW 850 AVMULOSW 851 AVMULEUW 852 AVMULOUW 853 AVMULUWM 854 AVPMSUM 855 AVPMSUMB 856 AVPMSUMH 857 AVPMSUMW 858 AVPMSUMD 859 AVMSUMUDM 860 AVR 861 AVRLB 862 AVRLH 863 AVRLW 864 AVRLD 865 AVS 866 AVSLB 867 AVSLH 868 AVSLW 869 AVSL 870 AVSLO 871 AVSRB 872 AVSRH 873 AVSRW 874 AVSR 875 AVSRO 876 AVSLD 877 AVSRD 878 AVSA 879 AVSRAB 880 AVSRAH 881 AVSRAW 882 AVSRAD 883 AVSOI 884 AVSLDOI 885 AVCLZ 886 AVCLZB 887 AVCLZH 888 AVCLZW 889 AVCLZD 890 AVPOPCNT 891 AVPOPCNTB 892 AVPOPCNTH 893 AVPOPCNTW 894 AVPOPCNTD 895 AVCMPEQ 896 AVCMPEQUB 897 AVCMPEQUBCC 898 AVCMPEQUH 899 AVCMPEQUHCC 900 AVCMPEQUW 901 AVCMPEQUWCC 902 AVCMPEQUD 903 AVCMPEQUDCC 904 AVCMPGT 905 AVCMPGTUB 906 AVCMPGTUBCC 907 AVCMPGTUH 908 AVCMPGTUHCC 909 AVCMPGTUW 910 AVCMPGTUWCC 911 AVCMPGTUD 912 AVCMPGTUDCC 913 AVCMPGTSB 914 AVCMPGTSBCC 915 AVCMPGTSH 916 AVCMPGTSHCC 917 AVCMPGTSW 918 AVCMPGTSWCC 919 AVCMPGTSD 920 AVCMPGTSDCC 921 AVCMPNEZB 922 AVCMPNEZBCC 923 AVCMPNEB 924 AVCMPNEBCC 925 AVCMPNEH 926 AVCMPNEHCC 927 AVCMPNEW 928 AVCMPNEWCC 929 AVPERM 930 AVPERMXOR 931 AVPERMR 932 AVBPERMQ 933 AVBPERMD 934 AVSEL 935 AVSPLTB 936 AVSPLTH 937 AVSPLTW 938 AVSPLTISB 939 AVSPLTISH 940 AVSPLTISW 941 AVCIPH 942 AVCIPHER 943 AVCIPHERLAST 944 AVNCIPH 945 AVNCIPHER 946 AVNCIPHERLAST 947 AVSBOX 948 AVSHASIGMA 949 AVSHASIGMAW 950 AVSHASIGMAD 951 AVMRGEW 952 AVMRGOW 953 AVCLZLSBB 954 AVCTZLSBB 955 956 /* VSX */ 957 ALXV 958 ALXVL 959 ALXVLL 960 ALXVD2X 961 ALXVW4X 962 ALXVH8X 963 ALXVB16X 964 ALXVX 965 ALXVDSX 966 ASTXV 967 ASTXVL 968 ASTXVLL 969 ASTXVD2X 970 ASTXVW4X 971 ASTXVH8X 972 ASTXVB16X 973 ASTXVX 974 ALXSDX 975 ASTXSDX 976 ALXSIWAX 977 ALXSIWZX 978 ASTXSIWX 979 AMFVSRD 980 AMFFPRD 981 AMFVRD 982 AMFVSRWZ 983 AMFVSRLD 984 AMTVSRD 985 AMTFPRD 986 AMTVRD 987 AMTVSRWA 988 AMTVSRWZ 989 AMTVSRDD 990 AMTVSRWS 991 AXXLAND 992 AXXLANDC 993 AXXLEQV 994 AXXLNAND 995 AXXLOR 996 AXXLORC 997 AXXLNOR 998 AXXLORQ 999 AXXLXOR 1000 AXXSEL 1001 AXXMRGHW 1002 AXXMRGLW 1003 AXXSPLTW 1004 AXXSPLTIB 1005 AXXPERM 1006 AXXPERMDI 1007 AXXSLDWI 1008 AXXBRQ 1009 AXXBRD 1010 AXXBRW 1011 AXXBRH 1012 AXSCVDPSP 1013 AXSCVSPDP 1014 AXSCVDPSPN 1015 AXSCVSPDPN 1016 AXVCVDPSP 1017 AXVCVSPDP 1018 AXSCVDPSXDS 1019 AXSCVDPSXWS 1020 AXSCVDPUXDS 1021 AXSCVDPUXWS 1022 AXSCVSXDDP 1023 AXSCVUXDDP 1024 AXSCVSXDSP 1025 AXSCVUXDSP 1026 AXVCVDPSXDS 1027 AXVCVDPSXWS 1028 AXVCVDPUXDS 1029 AXVCVDPUXWS 1030 AXVCVSPSXDS 1031 AXVCVSPSXWS 1032 AXVCVSPUXDS 1033 AXVCVSPUXWS 1034 AXVCVSXDDP 1035 AXVCVSXWDP 1036 AXVCVUXDDP 1037 AXVCVUXWDP 1038 AXVCVSXDSP 1039 AXVCVSXWSP 1040 AXVCVUXDSP 1041 AXVCVUXWSP 1042 ALASTAOUT 1043 1044 // aliases 1045 ABR = obj.AJMP 1046 ABL = obj.ACALL 1047 ALAST = ALASTGEN 1048 )