github.com/shogo82148/std@v1.22.1-0.20240327122250-4e474527810c/cmd/internal/obj/riscv/cpu.go (about) 1 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 2 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 3 // Portions Copyright © 1997-1999 Vita Nuova Limited 4 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 5 // Portions Copyright © 2004,2006 Bruce Ellis 6 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 7 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 8 // Portions Copyright © 2009 The Go Authors. All rights reserved. 9 // Portions Copyright © 2019 The Go Authors. All rights reserved. 10 // 11 // Permission is hereby granted, free of charge, to any person obtaining a copy 12 // of this software and associated documentation files (the "Software"), to deal 13 // in the Software without restriction, including without limitation the rights 14 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 15 // copies of the Software, and to permit persons to whom the Software is 16 // furnished to do so, subject to the following conditions: 17 // 18 // The above copyright notice and this permission notice shall be included in 19 // all copies or substantial portions of the Software. 20 // 21 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 24 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 25 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 26 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 27 // THE SOFTWARE. 28 29 package riscv 30 31 import ( 32 "github.com/shogo82148/std/cmd/internal/obj" 33 ) 34 35 const ( 36 // Base register numberings. 37 REG_X0 = obj.RBaseRISCV + iota 38 REG_X1 39 REG_X2 40 REG_X3 41 REG_X4 42 REG_X5 43 REG_X6 44 REG_X7 45 REG_X8 46 REG_X9 47 REG_X10 48 REG_X11 49 REG_X12 50 REG_X13 51 REG_X14 52 REG_X15 53 REG_X16 54 REG_X17 55 REG_X18 56 REG_X19 57 REG_X20 58 REG_X21 59 REG_X22 60 REG_X23 61 REG_X24 62 REG_X25 63 REG_X26 64 REG_X27 65 REG_X28 66 REG_X29 67 REG_X30 68 REG_X31 69 70 // FP register numberings. 71 REG_F0 72 REG_F1 73 REG_F2 74 REG_F3 75 REG_F4 76 REG_F5 77 REG_F6 78 REG_F7 79 REG_F8 80 REG_F9 81 REG_F10 82 REG_F11 83 REG_F12 84 REG_F13 85 REG_F14 86 REG_F15 87 REG_F16 88 REG_F17 89 REG_F18 90 REG_F19 91 REG_F20 92 REG_F21 93 REG_F22 94 REG_F23 95 REG_F24 96 REG_F25 97 REG_F26 98 REG_F27 99 REG_F28 100 REG_F29 101 REG_F30 102 REG_F31 103 104 // This marks the end of the register numbering. 105 REG_END 106 107 // General registers reassigned to ABI names. 108 REG_ZERO = REG_X0 109 REG_RA = REG_X1 110 REG_SP = REG_X2 111 REG_GP = REG_X3 112 REG_TP = REG_X4 113 REG_T0 = REG_X5 114 REG_T1 = REG_X6 115 REG_T2 = REG_X7 116 REG_S0 = REG_X8 117 REG_S1 = REG_X9 118 REG_A0 = REG_X10 119 REG_A1 = REG_X11 120 REG_A2 = REG_X12 121 REG_A3 = REG_X13 122 REG_A4 = REG_X14 123 REG_A5 = REG_X15 124 REG_A6 = REG_X16 125 REG_A7 = REG_X17 126 REG_S2 = REG_X18 127 REG_S3 = REG_X19 128 REG_S4 = REG_X20 129 REG_S5 = REG_X21 130 REG_S6 = REG_X22 131 REG_S7 = REG_X23 132 REG_S8 = REG_X24 133 REG_S9 = REG_X25 134 REG_S10 = REG_X26 135 REG_S11 = REG_X27 136 REG_T3 = REG_X28 137 REG_T4 = REG_X29 138 REG_T5 = REG_X30 139 REG_T6 = REG_X31 140 141 // Go runtime register names. 142 REG_CTXT = REG_S10 143 REG_G = REG_S11 144 REG_LR = REG_RA 145 REG_TMP = REG_T6 146 147 // ABI names for floating point registers. 148 REG_FT0 = REG_F0 149 REG_FT1 = REG_F1 150 REG_FT2 = REG_F2 151 REG_FT3 = REG_F3 152 REG_FT4 = REG_F4 153 REG_FT5 = REG_F5 154 REG_FT6 = REG_F6 155 REG_FT7 = REG_F7 156 REG_FS0 = REG_F8 157 REG_FS1 = REG_F9 158 REG_FA0 = REG_F10 159 REG_FA1 = REG_F11 160 REG_FA2 = REG_F12 161 REG_FA3 = REG_F13 162 REG_FA4 = REG_F14 163 REG_FA5 = REG_F15 164 REG_FA6 = REG_F16 165 REG_FA7 = REG_F17 166 REG_FS2 = REG_F18 167 REG_FS3 = REG_F19 168 REG_FS4 = REG_F20 169 REG_FS5 = REG_F21 170 REG_FS6 = REG_F22 171 REG_FS7 = REG_F23 172 REG_FS8 = REG_F24 173 REG_FS9 = REG_F25 174 REG_FS10 = REG_F26 175 REG_FS11 = REG_F27 176 REG_FT8 = REG_F28 177 REG_FT9 = REG_F29 178 REG_FT10 = REG_F30 179 REG_FT11 = REG_F31 180 181 // Names generated by the SSA compiler. 182 REGSP = REG_SP 183 REGG = REG_G 184 ) 185 186 // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers 187 var RISCV64DWARFRegisters = map[int16]int16{ 188 189 REG_X0: 0, 190 REG_X1: 1, 191 REG_X2: 2, 192 REG_X3: 3, 193 REG_X4: 4, 194 REG_X5: 5, 195 REG_X6: 6, 196 REG_X7: 7, 197 REG_X8: 8, 198 REG_X9: 9, 199 REG_X10: 10, 200 REG_X11: 11, 201 REG_X12: 12, 202 REG_X13: 13, 203 REG_X14: 14, 204 REG_X15: 15, 205 REG_X16: 16, 206 REG_X17: 17, 207 REG_X18: 18, 208 REG_X19: 19, 209 REG_X20: 20, 210 REG_X21: 21, 211 REG_X22: 22, 212 REG_X23: 23, 213 REG_X24: 24, 214 REG_X25: 25, 215 REG_X26: 26, 216 REG_X27: 27, 217 REG_X28: 28, 218 REG_X29: 29, 219 REG_X30: 30, 220 REG_X31: 31, 221 222 REG_F0: 32, 223 REG_F1: 33, 224 REG_F2: 34, 225 REG_F3: 35, 226 REG_F4: 36, 227 REG_F5: 37, 228 REG_F6: 38, 229 REG_F7: 39, 230 REG_F8: 40, 231 REG_F9: 41, 232 REG_F10: 42, 233 REG_F11: 43, 234 REG_F12: 44, 235 REG_F13: 45, 236 REG_F14: 46, 237 REG_F15: 47, 238 REG_F16: 48, 239 REG_F17: 49, 240 REG_F18: 50, 241 REG_F19: 51, 242 REG_F20: 52, 243 REG_F21: 53, 244 REG_F22: 54, 245 REG_F23: 55, 246 REG_F24: 56, 247 REG_F25: 57, 248 REG_F26: 58, 249 REG_F27: 59, 250 REG_F28: 60, 251 REG_F29: 61, 252 REG_F30: 62, 253 REG_F31: 63, 254 } 255 256 // Prog.Mark flags. 257 const ( 258 // USES_REG_TMP indicates that a machine instruction generated from the 259 // corresponding *obj.Prog uses the temporary register. 260 USES_REG_TMP = 1 << iota 261 262 // NEED_JAL_RELOC is set on JAL instructions to indicate that a 263 // R_RISCV_JAL relocation is needed. 264 NEED_JAL_RELOC 265 266 // NEED_CALL_RELOC is set on an AUIPC instruction to indicate that it 267 // is the first instruction in an AUIPC + JAL pair that needs a 268 // R_RISCV_CALL relocation. 269 NEED_CALL_RELOC 270 271 // NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that 272 // it is the first instruction in an AUIPC + I-type pair that needs a 273 // R_RISCV_PCREL_ITYPE relocation. 274 NEED_PCREL_ITYPE_RELOC 275 276 // NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that 277 // it is the first instruction in an AUIPC + S-type pair that needs a 278 // R_RISCV_PCREL_STYPE relocation. 279 NEED_PCREL_STYPE_RELOC 280 ) 281 282 // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files 283 // at https://github.com/riscv/riscv-opcodes. 284 // 285 // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. 286 // 287 // See also "The RISC-V Instruction Set Manual" at https://riscv.org/specifications/. 288 // 289 // If you modify this table, you MUST run 'go generate' to regenerate anames.go! 290 const ( 291 292 // 2.4: Integer Computational Instructions 293 AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota 294 ASLTI 295 ASLTIU 296 AANDI 297 AORI 298 AXORI 299 ASLLI 300 ASRLI 301 ASRAI 302 ALUI 303 AAUIPC 304 AADD 305 ASLT 306 ASLTU 307 AAND 308 AOR 309 AXOR 310 ASLL 311 ASRL 312 ASUB 313 ASRA 314 315 // 2.5: Control Transfer Instructions 316 AJAL 317 AJALR 318 ABEQ 319 ABNE 320 ABLT 321 ABLTU 322 ABGE 323 ABGEU 324 325 // 2.6: Load and Store Instructions 326 ALW 327 ALWU 328 ALH 329 ALHU 330 ALB 331 ALBU 332 ASW 333 ASH 334 ASB 335 336 // 2.7: Memory Ordering Instructions 337 AFENCE 338 AFENCETSO 339 APAUSE 340 341 // 5.2: Integer Computational Instructions (RV64I) 342 AADDIW 343 ASLLIW 344 ASRLIW 345 ASRAIW 346 AADDW 347 ASLLW 348 ASRLW 349 ASUBW 350 ASRAW 351 352 // 5.3: Load and Store Instructions (RV64I) 353 ALD 354 ASD 355 356 // 7.1: Multiplication Operations 357 AMUL 358 AMULH 359 AMULHU 360 AMULHSU 361 AMULW 362 ADIV 363 ADIVU 364 AREM 365 AREMU 366 ADIVW 367 ADIVUW 368 AREMW 369 AREMUW 370 371 // 8.2: Load-Reserved/Store-Conditional Instructions 372 ALRD 373 ASCD 374 ALRW 375 ASCW 376 377 // 8.3: Atomic Memory Operations 378 AAMOSWAPD 379 AAMOADDD 380 AAMOANDD 381 AAMOORD 382 AAMOXORD 383 AAMOMAXD 384 AAMOMAXUD 385 AAMOMIND 386 AAMOMINUD 387 AAMOSWAPW 388 AAMOADDW 389 AAMOANDW 390 AAMOORW 391 AAMOXORW 392 AAMOMAXW 393 AAMOMAXUW 394 AAMOMINW 395 AAMOMINUW 396 397 // 10.1: Base Counters and Timers 398 ARDCYCLE 399 ARDCYCLEH 400 ARDTIME 401 ARDTIMEH 402 ARDINSTRET 403 ARDINSTRETH 404 405 // 11.2: Floating-Point Control and Status Register 406 AFRCSR 407 AFSCSR 408 AFRRM 409 AFSRM 410 AFRFLAGS 411 AFSFLAGS 412 AFSRMI 413 AFSFLAGSI 414 415 // 11.5: Single-Precision Load and Store Instructions 416 AFLW 417 AFSW 418 419 // 11.6: Single-Precision Floating-Point Computational Instructions 420 AFADDS 421 AFSUBS 422 AFMULS 423 AFDIVS 424 AFMINS 425 AFMAXS 426 AFSQRTS 427 AFMADDS 428 AFMSUBS 429 AFNMADDS 430 AFNMSUBS 431 432 // 11.7: Single-Precision Floating-Point Conversion and Move Instructions 433 AFCVTWS 434 AFCVTLS 435 AFCVTSW 436 AFCVTSL 437 AFCVTWUS 438 AFCVTLUS 439 AFCVTSWU 440 AFCVTSLU 441 AFSGNJS 442 AFSGNJNS 443 AFSGNJXS 444 AFMVXS 445 AFMVSX 446 AFMVXW 447 AFMVWX 448 449 // 11.8: Single-Precision Floating-Point Compare Instructions 450 AFEQS 451 AFLTS 452 AFLES 453 454 // 11.9: Single-Precision Floating-Point Classify Instruction 455 AFCLASSS 456 457 // 12.3: Double-Precision Load and Store Instructions 458 AFLD 459 AFSD 460 461 // 12.4: Double-Precision Floating-Point Computational Instructions 462 AFADDD 463 AFSUBD 464 AFMULD 465 AFDIVD 466 AFMIND 467 AFMAXD 468 AFSQRTD 469 AFMADDD 470 AFMSUBD 471 AFNMADDD 472 AFNMSUBD 473 474 // 12.5: Double-Precision Floating-Point Conversion and Move Instructions 475 AFCVTWD 476 AFCVTLD 477 AFCVTDW 478 AFCVTDL 479 AFCVTWUD 480 AFCVTLUD 481 AFCVTDWU 482 AFCVTDLU 483 AFCVTSD 484 AFCVTDS 485 AFSGNJD 486 AFSGNJND 487 AFSGNJXD 488 AFMVXD 489 AFMVDX 490 491 // 12.6: Double-Precision Floating-Point Compare Instructions 492 AFEQD 493 AFLTD 494 AFLED 495 496 // 12.7: Double-Precision Floating-Point Classify Instruction 497 AFCLASSD 498 499 // 13.1 Quad-Precision Load and Store Instructions 500 AFLQ 501 AFSQ 502 503 // 13.2: Quad-Precision Computational Instructions 504 AFADDQ 505 AFSUBQ 506 AFMULQ 507 AFDIVQ 508 AFMINQ 509 AFMAXQ 510 AFSQRTQ 511 AFMADDQ 512 AFMSUBQ 513 AFNMADDQ 514 AFNMSUBQ 515 516 // 13.3 Quad-Precision Convert and Move Instructions 517 AFCVTWQ 518 AFCVTLQ 519 AFCVTSQ 520 AFCVTDQ 521 AFCVTQW 522 AFCVTQL 523 AFCVTQS 524 AFCVTQD 525 AFCVTWUQ 526 AFCVTLUQ 527 AFCVTQWU 528 AFCVTQLU 529 AFSGNJQ 530 AFSGNJNQ 531 AFSGNJXQ 532 533 // 13.4 Quad-Precision Floating-Point Compare Instructions 534 AFEQQ 535 AFLEQ 536 AFLTQ 537 538 // 13.5 Quad-Precision Floating-Point Classify Instruction 539 AFCLASSQ 540 541 // 3.1.9: Instructions to Access CSRs 542 ACSRRW 543 ACSRRS 544 ACSRRC 545 ACSRRWI 546 ACSRRSI 547 ACSRRCI 548 549 // 3.2.1: Environment Call and Breakpoint 550 AECALL 551 ASCALL 552 AEBREAK 553 ASBREAK 554 555 // 3.2.2: Trap-Return Instructions 556 AMRET 557 ASRET 558 ADRET 559 560 // 3.2.3: Wait for Interrupt 561 AWFI 562 563 // 4.2.1: Supervisor Memory-Management Fence Instruction 564 ASFENCEVMA 565 566 // 1.1: Address Generation Instructions (Zba) 567 AADDUW 568 ASH1ADD 569 ASH1ADDUW 570 ASH2ADD 571 ASH2ADDUW 572 ASH3ADD 573 ASH3ADDUW 574 ASLLIUW 575 576 // 1.2: Basic Bit Manipulation (Zbb) 577 AANDN 578 AORN 579 AXNOR 580 ACLZ 581 ACLZW 582 ACTZ 583 ACTZW 584 ACPOP 585 ACPOPW 586 AMAX 587 AMAXU 588 AMIN 589 AMINU 590 ASEXTB 591 ASEXTH 592 AZEXTH 593 594 // 1.3: Bitwise Rotation (Zbb) 595 AROL 596 AROLW 597 AROR 598 ARORI 599 ARORIW 600 ARORW 601 AORCB 602 AREV8 603 604 // 1.5: Single-bit Instructions (Zbs) 605 ABCLR 606 ABCLRI 607 ABEXT 608 ABEXTI 609 ABINV 610 ABINVI 611 ABSET 612 ABSETI 613 614 // The escape hatch. Inserts a single 32-bit word. 615 AWORD 616 617 // Pseudo-instructions. These get translated by the assembler into other 618 // instructions, based on their operands. 619 ABEQZ 620 ABGEZ 621 ABGT 622 ABGTU 623 ABGTZ 624 ABLE 625 ABLEU 626 ABLEZ 627 ABLTZ 628 ABNEZ 629 AFABSD 630 AFABSS 631 AFNEGD 632 AFNEGS 633 AFNED 634 AFNES 635 AMOV 636 AMOVB 637 AMOVBU 638 AMOVF 639 AMOVD 640 AMOVH 641 AMOVHU 642 AMOVW 643 AMOVWU 644 ANEG 645 ANEGW 646 ANOT 647 ASEQZ 648 ASNEZ 649 650 // End marker 651 ALAST 652 ) 653 654 const ( 655 RM_RNE uint8 = iota 656 RM_RTZ 657 RM_RDN 658 RM_RUP 659 RM_RMM 660 ) 661 662 // Instruction encoding masks. 663 const ( 664 // BTypeImmMask is a mask including only the immediate portion of 665 // B-type instructions. 666 BTypeImmMask = 0xfe000f80 667 668 // CBTypeImmMask is a mask including only the immediate portion of 669 // CB-type instructions. 670 CBTypeImmMask = 0x1c7c 671 672 // CJTypeImmMask is a mask including only the immediate portion of 673 // CJ-type instructions. 674 CJTypeImmMask = 0x1f7c 675 676 // ITypeImmMask is a mask including only the immediate portion of 677 // I-type instructions. 678 ITypeImmMask = 0xfff00000 679 680 // JTypeImmMask is a mask including only the immediate portion of 681 // J-type instructions. 682 JTypeImmMask = 0xfffff000 683 684 // STypeImmMask is a mask including only the immediate portion of 685 // S-type instructions. 686 STypeImmMask = 0xfe000f80 687 688 // UTypeImmMask is a mask including only the immediate portion of 689 // U-type instructions. 690 UTypeImmMask = 0xfffff000 691 )