github.com/slayercat/go@v0.0.0-20170428012452-c51559813f61/src/cmd/compile/internal/ssa/opGen.go (about) 1 // Code generated from gen/*Ops.go; DO NOT EDIT. 2 3 package ssa 4 5 import ( 6 "cmd/internal/obj" 7 "cmd/internal/obj/arm" 8 "cmd/internal/obj/arm64" 9 "cmd/internal/obj/mips" 10 "cmd/internal/obj/ppc64" 11 "cmd/internal/obj/s390x" 12 "cmd/internal/obj/x86" 13 ) 14 15 const ( 16 BlockInvalid BlockKind = iota 17 18 Block386EQ 19 Block386NE 20 Block386LT 21 Block386LE 22 Block386GT 23 Block386GE 24 Block386ULT 25 Block386ULE 26 Block386UGT 27 Block386UGE 28 Block386EQF 29 Block386NEF 30 Block386ORD 31 Block386NAN 32 33 BlockAMD64EQ 34 BlockAMD64NE 35 BlockAMD64LT 36 BlockAMD64LE 37 BlockAMD64GT 38 BlockAMD64GE 39 BlockAMD64ULT 40 BlockAMD64ULE 41 BlockAMD64UGT 42 BlockAMD64UGE 43 BlockAMD64EQF 44 BlockAMD64NEF 45 BlockAMD64ORD 46 BlockAMD64NAN 47 48 BlockARMEQ 49 BlockARMNE 50 BlockARMLT 51 BlockARMLE 52 BlockARMGT 53 BlockARMGE 54 BlockARMULT 55 BlockARMULE 56 BlockARMUGT 57 BlockARMUGE 58 59 BlockARM64EQ 60 BlockARM64NE 61 BlockARM64LT 62 BlockARM64LE 63 BlockARM64GT 64 BlockARM64GE 65 BlockARM64ULT 66 BlockARM64ULE 67 BlockARM64UGT 68 BlockARM64UGE 69 BlockARM64Z 70 BlockARM64NZ 71 BlockARM64ZW 72 BlockARM64NZW 73 74 BlockMIPSEQ 75 BlockMIPSNE 76 BlockMIPSLTZ 77 BlockMIPSLEZ 78 BlockMIPSGTZ 79 BlockMIPSGEZ 80 BlockMIPSFPT 81 BlockMIPSFPF 82 83 BlockMIPS64EQ 84 BlockMIPS64NE 85 BlockMIPS64LTZ 86 BlockMIPS64LEZ 87 BlockMIPS64GTZ 88 BlockMIPS64GEZ 89 BlockMIPS64FPT 90 BlockMIPS64FPF 91 92 BlockPPC64EQ 93 BlockPPC64NE 94 BlockPPC64LT 95 BlockPPC64LE 96 BlockPPC64GT 97 BlockPPC64GE 98 BlockPPC64FLT 99 BlockPPC64FLE 100 BlockPPC64FGT 101 BlockPPC64FGE 102 103 BlockS390XEQ 104 BlockS390XNE 105 BlockS390XLT 106 BlockS390XLE 107 BlockS390XGT 108 BlockS390XGE 109 BlockS390XGTF 110 BlockS390XGEF 111 112 BlockPlain 113 BlockIf 114 BlockDefer 115 BlockRet 116 BlockRetJmp 117 BlockExit 118 BlockFirst 119 ) 120 121 var blockString = [...]string{ 122 BlockInvalid: "BlockInvalid", 123 124 Block386EQ: "EQ", 125 Block386NE: "NE", 126 Block386LT: "LT", 127 Block386LE: "LE", 128 Block386GT: "GT", 129 Block386GE: "GE", 130 Block386ULT: "ULT", 131 Block386ULE: "ULE", 132 Block386UGT: "UGT", 133 Block386UGE: "UGE", 134 Block386EQF: "EQF", 135 Block386NEF: "NEF", 136 Block386ORD: "ORD", 137 Block386NAN: "NAN", 138 139 BlockAMD64EQ: "EQ", 140 BlockAMD64NE: "NE", 141 BlockAMD64LT: "LT", 142 BlockAMD64LE: "LE", 143 BlockAMD64GT: "GT", 144 BlockAMD64GE: "GE", 145 BlockAMD64ULT: "ULT", 146 BlockAMD64ULE: "ULE", 147 BlockAMD64UGT: "UGT", 148 BlockAMD64UGE: "UGE", 149 BlockAMD64EQF: "EQF", 150 BlockAMD64NEF: "NEF", 151 BlockAMD64ORD: "ORD", 152 BlockAMD64NAN: "NAN", 153 154 BlockARMEQ: "EQ", 155 BlockARMNE: "NE", 156 BlockARMLT: "LT", 157 BlockARMLE: "LE", 158 BlockARMGT: "GT", 159 BlockARMGE: "GE", 160 BlockARMULT: "ULT", 161 BlockARMULE: "ULE", 162 BlockARMUGT: "UGT", 163 BlockARMUGE: "UGE", 164 165 BlockARM64EQ: "EQ", 166 BlockARM64NE: "NE", 167 BlockARM64LT: "LT", 168 BlockARM64LE: "LE", 169 BlockARM64GT: "GT", 170 BlockARM64GE: "GE", 171 BlockARM64ULT: "ULT", 172 BlockARM64ULE: "ULE", 173 BlockARM64UGT: "UGT", 174 BlockARM64UGE: "UGE", 175 BlockARM64Z: "Z", 176 BlockARM64NZ: "NZ", 177 BlockARM64ZW: "ZW", 178 BlockARM64NZW: "NZW", 179 180 BlockMIPSEQ: "EQ", 181 BlockMIPSNE: "NE", 182 BlockMIPSLTZ: "LTZ", 183 BlockMIPSLEZ: "LEZ", 184 BlockMIPSGTZ: "GTZ", 185 BlockMIPSGEZ: "GEZ", 186 BlockMIPSFPT: "FPT", 187 BlockMIPSFPF: "FPF", 188 189 BlockMIPS64EQ: "EQ", 190 BlockMIPS64NE: "NE", 191 BlockMIPS64LTZ: "LTZ", 192 BlockMIPS64LEZ: "LEZ", 193 BlockMIPS64GTZ: "GTZ", 194 BlockMIPS64GEZ: "GEZ", 195 BlockMIPS64FPT: "FPT", 196 BlockMIPS64FPF: "FPF", 197 198 BlockPPC64EQ: "EQ", 199 BlockPPC64NE: "NE", 200 BlockPPC64LT: "LT", 201 BlockPPC64LE: "LE", 202 BlockPPC64GT: "GT", 203 BlockPPC64GE: "GE", 204 BlockPPC64FLT: "FLT", 205 BlockPPC64FLE: "FLE", 206 BlockPPC64FGT: "FGT", 207 BlockPPC64FGE: "FGE", 208 209 BlockS390XEQ: "EQ", 210 BlockS390XNE: "NE", 211 BlockS390XLT: "LT", 212 BlockS390XLE: "LE", 213 BlockS390XGT: "GT", 214 BlockS390XGE: "GE", 215 BlockS390XGTF: "GTF", 216 BlockS390XGEF: "GEF", 217 218 BlockPlain: "Plain", 219 BlockIf: "If", 220 BlockDefer: "Defer", 221 BlockRet: "Ret", 222 BlockRetJmp: "RetJmp", 223 BlockExit: "Exit", 224 BlockFirst: "First", 225 } 226 227 func (k BlockKind) String() string { return blockString[k] } 228 229 const ( 230 OpInvalid Op = iota 231 232 Op386ADDSS 233 Op386ADDSD 234 Op386SUBSS 235 Op386SUBSD 236 Op386MULSS 237 Op386MULSD 238 Op386DIVSS 239 Op386DIVSD 240 Op386MOVSSload 241 Op386MOVSDload 242 Op386MOVSSconst 243 Op386MOVSDconst 244 Op386MOVSSloadidx1 245 Op386MOVSSloadidx4 246 Op386MOVSDloadidx1 247 Op386MOVSDloadidx8 248 Op386MOVSSstore 249 Op386MOVSDstore 250 Op386MOVSSstoreidx1 251 Op386MOVSSstoreidx4 252 Op386MOVSDstoreidx1 253 Op386MOVSDstoreidx8 254 Op386ADDL 255 Op386ADDLconst 256 Op386ADDLcarry 257 Op386ADDLconstcarry 258 Op386ADCL 259 Op386ADCLconst 260 Op386SUBL 261 Op386SUBLconst 262 Op386SUBLcarry 263 Op386SUBLconstcarry 264 Op386SBBL 265 Op386SBBLconst 266 Op386MULL 267 Op386MULLconst 268 Op386HMULL 269 Op386HMULLU 270 Op386MULLQU 271 Op386AVGLU 272 Op386DIVL 273 Op386DIVW 274 Op386DIVLU 275 Op386DIVWU 276 Op386MODL 277 Op386MODW 278 Op386MODLU 279 Op386MODWU 280 Op386ANDL 281 Op386ANDLconst 282 Op386ORL 283 Op386ORLconst 284 Op386XORL 285 Op386XORLconst 286 Op386CMPL 287 Op386CMPW 288 Op386CMPB 289 Op386CMPLconst 290 Op386CMPWconst 291 Op386CMPBconst 292 Op386UCOMISS 293 Op386UCOMISD 294 Op386TESTL 295 Op386TESTW 296 Op386TESTB 297 Op386TESTLconst 298 Op386TESTWconst 299 Op386TESTBconst 300 Op386SHLL 301 Op386SHLLconst 302 Op386SHRL 303 Op386SHRW 304 Op386SHRB 305 Op386SHRLconst 306 Op386SHRWconst 307 Op386SHRBconst 308 Op386SARL 309 Op386SARW 310 Op386SARB 311 Op386SARLconst 312 Op386SARWconst 313 Op386SARBconst 314 Op386ROLLconst 315 Op386ROLWconst 316 Op386ROLBconst 317 Op386NEGL 318 Op386NOTL 319 Op386BSFL 320 Op386BSFW 321 Op386BSRL 322 Op386BSRW 323 Op386BSWAPL 324 Op386SQRTSD 325 Op386SBBLcarrymask 326 Op386SETEQ 327 Op386SETNE 328 Op386SETL 329 Op386SETLE 330 Op386SETG 331 Op386SETGE 332 Op386SETB 333 Op386SETBE 334 Op386SETA 335 Op386SETAE 336 Op386SETEQF 337 Op386SETNEF 338 Op386SETORD 339 Op386SETNAN 340 Op386SETGF 341 Op386SETGEF 342 Op386MOVBLSX 343 Op386MOVBLZX 344 Op386MOVWLSX 345 Op386MOVWLZX 346 Op386MOVLconst 347 Op386CVTTSD2SL 348 Op386CVTTSS2SL 349 Op386CVTSL2SS 350 Op386CVTSL2SD 351 Op386CVTSD2SS 352 Op386CVTSS2SD 353 Op386PXOR 354 Op386LEAL 355 Op386LEAL1 356 Op386LEAL2 357 Op386LEAL4 358 Op386LEAL8 359 Op386MOVBload 360 Op386MOVBLSXload 361 Op386MOVWload 362 Op386MOVWLSXload 363 Op386MOVLload 364 Op386MOVBstore 365 Op386MOVWstore 366 Op386MOVLstore 367 Op386MOVBloadidx1 368 Op386MOVWloadidx1 369 Op386MOVWloadidx2 370 Op386MOVLloadidx1 371 Op386MOVLloadidx4 372 Op386MOVBstoreidx1 373 Op386MOVWstoreidx1 374 Op386MOVWstoreidx2 375 Op386MOVLstoreidx1 376 Op386MOVLstoreidx4 377 Op386MOVBstoreconst 378 Op386MOVWstoreconst 379 Op386MOVLstoreconst 380 Op386MOVBstoreconstidx1 381 Op386MOVWstoreconstidx1 382 Op386MOVWstoreconstidx2 383 Op386MOVLstoreconstidx1 384 Op386MOVLstoreconstidx4 385 Op386DUFFZERO 386 Op386REPSTOSL 387 Op386CALLstatic 388 Op386CALLclosure 389 Op386CALLinter 390 Op386DUFFCOPY 391 Op386REPMOVSL 392 Op386InvertFlags 393 Op386LoweredGetG 394 Op386LoweredGetClosurePtr 395 Op386LoweredNilCheck 396 Op386MOVLconvert 397 Op386FlagEQ 398 Op386FlagLT_ULT 399 Op386FlagLT_UGT 400 Op386FlagGT_UGT 401 Op386FlagGT_ULT 402 Op386FCHS 403 Op386MOVSSconst1 404 Op386MOVSDconst1 405 Op386MOVSSconst2 406 Op386MOVSDconst2 407 408 OpAMD64ADDSS 409 OpAMD64ADDSD 410 OpAMD64SUBSS 411 OpAMD64SUBSD 412 OpAMD64MULSS 413 OpAMD64MULSD 414 OpAMD64DIVSS 415 OpAMD64DIVSD 416 OpAMD64MOVSSload 417 OpAMD64MOVSDload 418 OpAMD64MOVSSconst 419 OpAMD64MOVSDconst 420 OpAMD64MOVSSloadidx1 421 OpAMD64MOVSSloadidx4 422 OpAMD64MOVSDloadidx1 423 OpAMD64MOVSDloadidx8 424 OpAMD64MOVSSstore 425 OpAMD64MOVSDstore 426 OpAMD64MOVSSstoreidx1 427 OpAMD64MOVSSstoreidx4 428 OpAMD64MOVSDstoreidx1 429 OpAMD64MOVSDstoreidx8 430 OpAMD64ADDSDmem 431 OpAMD64ADDSSmem 432 OpAMD64SUBSSmem 433 OpAMD64SUBSDmem 434 OpAMD64MULSSmem 435 OpAMD64MULSDmem 436 OpAMD64ADDQ 437 OpAMD64ADDL 438 OpAMD64ADDQconst 439 OpAMD64ADDLconst 440 OpAMD64SUBQ 441 OpAMD64SUBL 442 OpAMD64SUBQconst 443 OpAMD64SUBLconst 444 OpAMD64MULQ 445 OpAMD64MULL 446 OpAMD64MULQconst 447 OpAMD64MULLconst 448 OpAMD64HMULQ 449 OpAMD64HMULL 450 OpAMD64HMULQU 451 OpAMD64HMULLU 452 OpAMD64AVGQU 453 OpAMD64DIVQ 454 OpAMD64DIVL 455 OpAMD64DIVW 456 OpAMD64DIVQU 457 OpAMD64DIVLU 458 OpAMD64DIVWU 459 OpAMD64MULQU2 460 OpAMD64DIVQU2 461 OpAMD64ANDQ 462 OpAMD64ANDL 463 OpAMD64ANDQconst 464 OpAMD64ANDLconst 465 OpAMD64ORQ 466 OpAMD64ORL 467 OpAMD64ORQconst 468 OpAMD64ORLconst 469 OpAMD64XORQ 470 OpAMD64XORL 471 OpAMD64XORQconst 472 OpAMD64XORLconst 473 OpAMD64CMPQ 474 OpAMD64CMPL 475 OpAMD64CMPW 476 OpAMD64CMPB 477 OpAMD64CMPQconst 478 OpAMD64CMPLconst 479 OpAMD64CMPWconst 480 OpAMD64CMPBconst 481 OpAMD64UCOMISS 482 OpAMD64UCOMISD 483 OpAMD64BTL 484 OpAMD64BTQ 485 OpAMD64BTLconst 486 OpAMD64BTQconst 487 OpAMD64TESTQ 488 OpAMD64TESTL 489 OpAMD64TESTW 490 OpAMD64TESTB 491 OpAMD64TESTQconst 492 OpAMD64TESTLconst 493 OpAMD64TESTWconst 494 OpAMD64TESTBconst 495 OpAMD64SHLQ 496 OpAMD64SHLL 497 OpAMD64SHLQconst 498 OpAMD64SHLLconst 499 OpAMD64SHRQ 500 OpAMD64SHRL 501 OpAMD64SHRW 502 OpAMD64SHRB 503 OpAMD64SHRQconst 504 OpAMD64SHRLconst 505 OpAMD64SHRWconst 506 OpAMD64SHRBconst 507 OpAMD64SARQ 508 OpAMD64SARL 509 OpAMD64SARW 510 OpAMD64SARB 511 OpAMD64SARQconst 512 OpAMD64SARLconst 513 OpAMD64SARWconst 514 OpAMD64SARBconst 515 OpAMD64ROLQ 516 OpAMD64ROLL 517 OpAMD64ROLW 518 OpAMD64ROLB 519 OpAMD64RORQ 520 OpAMD64RORL 521 OpAMD64RORW 522 OpAMD64RORB 523 OpAMD64ROLQconst 524 OpAMD64ROLLconst 525 OpAMD64ROLWconst 526 OpAMD64ROLBconst 527 OpAMD64ADDLmem 528 OpAMD64ADDQmem 529 OpAMD64SUBQmem 530 OpAMD64SUBLmem 531 OpAMD64ANDLmem 532 OpAMD64ANDQmem 533 OpAMD64ORQmem 534 OpAMD64ORLmem 535 OpAMD64XORQmem 536 OpAMD64XORLmem 537 OpAMD64NEGQ 538 OpAMD64NEGL 539 OpAMD64NOTQ 540 OpAMD64NOTL 541 OpAMD64BSFQ 542 OpAMD64BSFL 543 OpAMD64BSRQ 544 OpAMD64BSRL 545 OpAMD64CMOVQEQ 546 OpAMD64CMOVLEQ 547 OpAMD64BSWAPQ 548 OpAMD64BSWAPL 549 OpAMD64POPCNTQ 550 OpAMD64POPCNTL 551 OpAMD64SQRTSD 552 OpAMD64SBBQcarrymask 553 OpAMD64SBBLcarrymask 554 OpAMD64SETEQ 555 OpAMD64SETNE 556 OpAMD64SETL 557 OpAMD64SETLE 558 OpAMD64SETG 559 OpAMD64SETGE 560 OpAMD64SETB 561 OpAMD64SETBE 562 OpAMD64SETA 563 OpAMD64SETAE 564 OpAMD64SETEQF 565 OpAMD64SETNEF 566 OpAMD64SETORD 567 OpAMD64SETNAN 568 OpAMD64SETGF 569 OpAMD64SETGEF 570 OpAMD64MOVBQSX 571 OpAMD64MOVBQZX 572 OpAMD64MOVWQSX 573 OpAMD64MOVWQZX 574 OpAMD64MOVLQSX 575 OpAMD64MOVLQZX 576 OpAMD64MOVLconst 577 OpAMD64MOVQconst 578 OpAMD64CVTTSD2SL 579 OpAMD64CVTTSD2SQ 580 OpAMD64CVTTSS2SL 581 OpAMD64CVTTSS2SQ 582 OpAMD64CVTSL2SS 583 OpAMD64CVTSL2SD 584 OpAMD64CVTSQ2SS 585 OpAMD64CVTSQ2SD 586 OpAMD64CVTSD2SS 587 OpAMD64CVTSS2SD 588 OpAMD64PXOR 589 OpAMD64LEAQ 590 OpAMD64LEAQ1 591 OpAMD64LEAQ2 592 OpAMD64LEAQ4 593 OpAMD64LEAQ8 594 OpAMD64LEAL 595 OpAMD64MOVBload 596 OpAMD64MOVBQSXload 597 OpAMD64MOVWload 598 OpAMD64MOVWQSXload 599 OpAMD64MOVLload 600 OpAMD64MOVLQSXload 601 OpAMD64MOVQload 602 OpAMD64MOVBstore 603 OpAMD64MOVWstore 604 OpAMD64MOVLstore 605 OpAMD64MOVQstore 606 OpAMD64MOVOload 607 OpAMD64MOVOstore 608 OpAMD64MOVBloadidx1 609 OpAMD64MOVWloadidx1 610 OpAMD64MOVWloadidx2 611 OpAMD64MOVLloadidx1 612 OpAMD64MOVLloadidx4 613 OpAMD64MOVQloadidx1 614 OpAMD64MOVQloadidx8 615 OpAMD64MOVBstoreidx1 616 OpAMD64MOVWstoreidx1 617 OpAMD64MOVWstoreidx2 618 OpAMD64MOVLstoreidx1 619 OpAMD64MOVLstoreidx4 620 OpAMD64MOVQstoreidx1 621 OpAMD64MOVQstoreidx8 622 OpAMD64MOVBstoreconst 623 OpAMD64MOVWstoreconst 624 OpAMD64MOVLstoreconst 625 OpAMD64MOVQstoreconst 626 OpAMD64MOVBstoreconstidx1 627 OpAMD64MOVWstoreconstidx1 628 OpAMD64MOVWstoreconstidx2 629 OpAMD64MOVLstoreconstidx1 630 OpAMD64MOVLstoreconstidx4 631 OpAMD64MOVQstoreconstidx1 632 OpAMD64MOVQstoreconstidx8 633 OpAMD64DUFFZERO 634 OpAMD64MOVOconst 635 OpAMD64REPSTOSQ 636 OpAMD64CALLstatic 637 OpAMD64CALLclosure 638 OpAMD64CALLinter 639 OpAMD64DUFFCOPY 640 OpAMD64REPMOVSQ 641 OpAMD64InvertFlags 642 OpAMD64LoweredGetG 643 OpAMD64LoweredGetClosurePtr 644 OpAMD64LoweredNilCheck 645 OpAMD64MOVQconvert 646 OpAMD64MOVLconvert 647 OpAMD64FlagEQ 648 OpAMD64FlagLT_ULT 649 OpAMD64FlagLT_UGT 650 OpAMD64FlagGT_UGT 651 OpAMD64FlagGT_ULT 652 OpAMD64MOVLatomicload 653 OpAMD64MOVQatomicload 654 OpAMD64XCHGL 655 OpAMD64XCHGQ 656 OpAMD64XADDLlock 657 OpAMD64XADDQlock 658 OpAMD64AddTupleFirst32 659 OpAMD64AddTupleFirst64 660 OpAMD64CMPXCHGLlock 661 OpAMD64CMPXCHGQlock 662 OpAMD64ANDBlock 663 OpAMD64ORBlock 664 665 OpARMADD 666 OpARMADDconst 667 OpARMSUB 668 OpARMSUBconst 669 OpARMRSB 670 OpARMRSBconst 671 OpARMMUL 672 OpARMHMUL 673 OpARMHMULU 674 OpARMCALLudiv 675 OpARMADDS 676 OpARMADDSconst 677 OpARMADC 678 OpARMADCconst 679 OpARMSUBS 680 OpARMSUBSconst 681 OpARMRSBSconst 682 OpARMSBC 683 OpARMSBCconst 684 OpARMRSCconst 685 OpARMMULLU 686 OpARMMULA 687 OpARMADDF 688 OpARMADDD 689 OpARMSUBF 690 OpARMSUBD 691 OpARMMULF 692 OpARMMULD 693 OpARMDIVF 694 OpARMDIVD 695 OpARMAND 696 OpARMANDconst 697 OpARMOR 698 OpARMORconst 699 OpARMXOR 700 OpARMXORconst 701 OpARMBIC 702 OpARMBICconst 703 OpARMMVN 704 OpARMNEGF 705 OpARMNEGD 706 OpARMSQRTD 707 OpARMCLZ 708 OpARMREV 709 OpARMRBIT 710 OpARMSLL 711 OpARMSLLconst 712 OpARMSRL 713 OpARMSRLconst 714 OpARMSRA 715 OpARMSRAconst 716 OpARMSRRconst 717 OpARMADDshiftLL 718 OpARMADDshiftRL 719 OpARMADDshiftRA 720 OpARMSUBshiftLL 721 OpARMSUBshiftRL 722 OpARMSUBshiftRA 723 OpARMRSBshiftLL 724 OpARMRSBshiftRL 725 OpARMRSBshiftRA 726 OpARMANDshiftLL 727 OpARMANDshiftRL 728 OpARMANDshiftRA 729 OpARMORshiftLL 730 OpARMORshiftRL 731 OpARMORshiftRA 732 OpARMXORshiftLL 733 OpARMXORshiftRL 734 OpARMXORshiftRA 735 OpARMXORshiftRR 736 OpARMBICshiftLL 737 OpARMBICshiftRL 738 OpARMBICshiftRA 739 OpARMMVNshiftLL 740 OpARMMVNshiftRL 741 OpARMMVNshiftRA 742 OpARMADCshiftLL 743 OpARMADCshiftRL 744 OpARMADCshiftRA 745 OpARMSBCshiftLL 746 OpARMSBCshiftRL 747 OpARMSBCshiftRA 748 OpARMRSCshiftLL 749 OpARMRSCshiftRL 750 OpARMRSCshiftRA 751 OpARMADDSshiftLL 752 OpARMADDSshiftRL 753 OpARMADDSshiftRA 754 OpARMSUBSshiftLL 755 OpARMSUBSshiftRL 756 OpARMSUBSshiftRA 757 OpARMRSBSshiftLL 758 OpARMRSBSshiftRL 759 OpARMRSBSshiftRA 760 OpARMADDshiftLLreg 761 OpARMADDshiftRLreg 762 OpARMADDshiftRAreg 763 OpARMSUBshiftLLreg 764 OpARMSUBshiftRLreg 765 OpARMSUBshiftRAreg 766 OpARMRSBshiftLLreg 767 OpARMRSBshiftRLreg 768 OpARMRSBshiftRAreg 769 OpARMANDshiftLLreg 770 OpARMANDshiftRLreg 771 OpARMANDshiftRAreg 772 OpARMORshiftLLreg 773 OpARMORshiftRLreg 774 OpARMORshiftRAreg 775 OpARMXORshiftLLreg 776 OpARMXORshiftRLreg 777 OpARMXORshiftRAreg 778 OpARMBICshiftLLreg 779 OpARMBICshiftRLreg 780 OpARMBICshiftRAreg 781 OpARMMVNshiftLLreg 782 OpARMMVNshiftRLreg 783 OpARMMVNshiftRAreg 784 OpARMADCshiftLLreg 785 OpARMADCshiftRLreg 786 OpARMADCshiftRAreg 787 OpARMSBCshiftLLreg 788 OpARMSBCshiftRLreg 789 OpARMSBCshiftRAreg 790 OpARMRSCshiftLLreg 791 OpARMRSCshiftRLreg 792 OpARMRSCshiftRAreg 793 OpARMADDSshiftLLreg 794 OpARMADDSshiftRLreg 795 OpARMADDSshiftRAreg 796 OpARMSUBSshiftLLreg 797 OpARMSUBSshiftRLreg 798 OpARMSUBSshiftRAreg 799 OpARMRSBSshiftLLreg 800 OpARMRSBSshiftRLreg 801 OpARMRSBSshiftRAreg 802 OpARMCMP 803 OpARMCMPconst 804 OpARMCMN 805 OpARMCMNconst 806 OpARMTST 807 OpARMTSTconst 808 OpARMTEQ 809 OpARMTEQconst 810 OpARMCMPF 811 OpARMCMPD 812 OpARMCMPshiftLL 813 OpARMCMPshiftRL 814 OpARMCMPshiftRA 815 OpARMCMPshiftLLreg 816 OpARMCMPshiftRLreg 817 OpARMCMPshiftRAreg 818 OpARMCMPF0 819 OpARMCMPD0 820 OpARMMOVWconst 821 OpARMMOVFconst 822 OpARMMOVDconst 823 OpARMMOVWaddr 824 OpARMMOVBload 825 OpARMMOVBUload 826 OpARMMOVHload 827 OpARMMOVHUload 828 OpARMMOVWload 829 OpARMMOVFload 830 OpARMMOVDload 831 OpARMMOVBstore 832 OpARMMOVHstore 833 OpARMMOVWstore 834 OpARMMOVFstore 835 OpARMMOVDstore 836 OpARMMOVWloadidx 837 OpARMMOVWloadshiftLL 838 OpARMMOVWloadshiftRL 839 OpARMMOVWloadshiftRA 840 OpARMMOVWstoreidx 841 OpARMMOVWstoreshiftLL 842 OpARMMOVWstoreshiftRL 843 OpARMMOVWstoreshiftRA 844 OpARMMOVBreg 845 OpARMMOVBUreg 846 OpARMMOVHreg 847 OpARMMOVHUreg 848 OpARMMOVWreg 849 OpARMMOVWnop 850 OpARMMOVWF 851 OpARMMOVWD 852 OpARMMOVWUF 853 OpARMMOVWUD 854 OpARMMOVFW 855 OpARMMOVDW 856 OpARMMOVFWU 857 OpARMMOVDWU 858 OpARMMOVFD 859 OpARMMOVDF 860 OpARMCMOVWHSconst 861 OpARMCMOVWLSconst 862 OpARMSRAcond 863 OpARMCALLstatic 864 OpARMCALLclosure 865 OpARMCALLinter 866 OpARMLoweredNilCheck 867 OpARMEqual 868 OpARMNotEqual 869 OpARMLessThan 870 OpARMLessEqual 871 OpARMGreaterThan 872 OpARMGreaterEqual 873 OpARMLessThanU 874 OpARMLessEqualU 875 OpARMGreaterThanU 876 OpARMGreaterEqualU 877 OpARMDUFFZERO 878 OpARMDUFFCOPY 879 OpARMLoweredZero 880 OpARMLoweredMove 881 OpARMLoweredGetClosurePtr 882 OpARMMOVWconvert 883 OpARMFlagEQ 884 OpARMFlagLT_ULT 885 OpARMFlagLT_UGT 886 OpARMFlagGT_UGT 887 OpARMFlagGT_ULT 888 OpARMInvertFlags 889 890 OpARM64ADD 891 OpARM64ADDconst 892 OpARM64SUB 893 OpARM64SUBconst 894 OpARM64MUL 895 OpARM64MULW 896 OpARM64MULH 897 OpARM64UMULH 898 OpARM64MULL 899 OpARM64UMULL 900 OpARM64DIV 901 OpARM64UDIV 902 OpARM64DIVW 903 OpARM64UDIVW 904 OpARM64MOD 905 OpARM64UMOD 906 OpARM64MODW 907 OpARM64UMODW 908 OpARM64FADDS 909 OpARM64FADDD 910 OpARM64FSUBS 911 OpARM64FSUBD 912 OpARM64FMULS 913 OpARM64FMULD 914 OpARM64FDIVS 915 OpARM64FDIVD 916 OpARM64AND 917 OpARM64ANDconst 918 OpARM64OR 919 OpARM64ORconst 920 OpARM64XOR 921 OpARM64XORconst 922 OpARM64BIC 923 OpARM64BICconst 924 OpARM64MVN 925 OpARM64NEG 926 OpARM64FNEGS 927 OpARM64FNEGD 928 OpARM64FSQRTD 929 OpARM64REV 930 OpARM64REVW 931 OpARM64REV16W 932 OpARM64RBIT 933 OpARM64RBITW 934 OpARM64CLZ 935 OpARM64CLZW 936 OpARM64SLL 937 OpARM64SLLconst 938 OpARM64SRL 939 OpARM64SRLconst 940 OpARM64SRA 941 OpARM64SRAconst 942 OpARM64RORconst 943 OpARM64RORWconst 944 OpARM64CMP 945 OpARM64CMPconst 946 OpARM64CMPW 947 OpARM64CMPWconst 948 OpARM64CMN 949 OpARM64CMNconst 950 OpARM64CMNW 951 OpARM64CMNWconst 952 OpARM64FCMPS 953 OpARM64FCMPD 954 OpARM64ADDshiftLL 955 OpARM64ADDshiftRL 956 OpARM64ADDshiftRA 957 OpARM64SUBshiftLL 958 OpARM64SUBshiftRL 959 OpARM64SUBshiftRA 960 OpARM64ANDshiftLL 961 OpARM64ANDshiftRL 962 OpARM64ANDshiftRA 963 OpARM64ORshiftLL 964 OpARM64ORshiftRL 965 OpARM64ORshiftRA 966 OpARM64XORshiftLL 967 OpARM64XORshiftRL 968 OpARM64XORshiftRA 969 OpARM64BICshiftLL 970 OpARM64BICshiftRL 971 OpARM64BICshiftRA 972 OpARM64CMPshiftLL 973 OpARM64CMPshiftRL 974 OpARM64CMPshiftRA 975 OpARM64MOVDconst 976 OpARM64FMOVSconst 977 OpARM64FMOVDconst 978 OpARM64MOVDaddr 979 OpARM64MOVBload 980 OpARM64MOVBUload 981 OpARM64MOVHload 982 OpARM64MOVHUload 983 OpARM64MOVWload 984 OpARM64MOVWUload 985 OpARM64MOVDload 986 OpARM64FMOVSload 987 OpARM64FMOVDload 988 OpARM64MOVBstore 989 OpARM64MOVHstore 990 OpARM64MOVWstore 991 OpARM64MOVDstore 992 OpARM64FMOVSstore 993 OpARM64FMOVDstore 994 OpARM64MOVBstorezero 995 OpARM64MOVHstorezero 996 OpARM64MOVWstorezero 997 OpARM64MOVDstorezero 998 OpARM64MOVBreg 999 OpARM64MOVBUreg 1000 OpARM64MOVHreg 1001 OpARM64MOVHUreg 1002 OpARM64MOVWreg 1003 OpARM64MOVWUreg 1004 OpARM64MOVDreg 1005 OpARM64MOVDnop 1006 OpARM64SCVTFWS 1007 OpARM64SCVTFWD 1008 OpARM64UCVTFWS 1009 OpARM64UCVTFWD 1010 OpARM64SCVTFS 1011 OpARM64SCVTFD 1012 OpARM64UCVTFS 1013 OpARM64UCVTFD 1014 OpARM64FCVTZSSW 1015 OpARM64FCVTZSDW 1016 OpARM64FCVTZUSW 1017 OpARM64FCVTZUDW 1018 OpARM64FCVTZSS 1019 OpARM64FCVTZSD 1020 OpARM64FCVTZUS 1021 OpARM64FCVTZUD 1022 OpARM64FCVTSD 1023 OpARM64FCVTDS 1024 OpARM64CSELULT 1025 OpARM64CSELULT0 1026 OpARM64CALLstatic 1027 OpARM64CALLclosure 1028 OpARM64CALLinter 1029 OpARM64LoweredNilCheck 1030 OpARM64Equal 1031 OpARM64NotEqual 1032 OpARM64LessThan 1033 OpARM64LessEqual 1034 OpARM64GreaterThan 1035 OpARM64GreaterEqual 1036 OpARM64LessThanU 1037 OpARM64LessEqualU 1038 OpARM64GreaterThanU 1039 OpARM64GreaterEqualU 1040 OpARM64DUFFZERO 1041 OpARM64LoweredZero 1042 OpARM64DUFFCOPY 1043 OpARM64LoweredMove 1044 OpARM64LoweredGetClosurePtr 1045 OpARM64MOVDconvert 1046 OpARM64FlagEQ 1047 OpARM64FlagLT_ULT 1048 OpARM64FlagLT_UGT 1049 OpARM64FlagGT_UGT 1050 OpARM64FlagGT_ULT 1051 OpARM64InvertFlags 1052 OpARM64LDAR 1053 OpARM64LDARW 1054 OpARM64STLR 1055 OpARM64STLRW 1056 OpARM64LoweredAtomicExchange64 1057 OpARM64LoweredAtomicExchange32 1058 OpARM64LoweredAtomicAdd64 1059 OpARM64LoweredAtomicAdd32 1060 OpARM64LoweredAtomicCas64 1061 OpARM64LoweredAtomicCas32 1062 OpARM64LoweredAtomicAnd8 1063 OpARM64LoweredAtomicOr8 1064 1065 OpMIPSADD 1066 OpMIPSADDconst 1067 OpMIPSSUB 1068 OpMIPSSUBconst 1069 OpMIPSMUL 1070 OpMIPSMULT 1071 OpMIPSMULTU 1072 OpMIPSDIV 1073 OpMIPSDIVU 1074 OpMIPSADDF 1075 OpMIPSADDD 1076 OpMIPSSUBF 1077 OpMIPSSUBD 1078 OpMIPSMULF 1079 OpMIPSMULD 1080 OpMIPSDIVF 1081 OpMIPSDIVD 1082 OpMIPSAND 1083 OpMIPSANDconst 1084 OpMIPSOR 1085 OpMIPSORconst 1086 OpMIPSXOR 1087 OpMIPSXORconst 1088 OpMIPSNOR 1089 OpMIPSNORconst 1090 OpMIPSNEG 1091 OpMIPSNEGF 1092 OpMIPSNEGD 1093 OpMIPSSQRTD 1094 OpMIPSSLL 1095 OpMIPSSLLconst 1096 OpMIPSSRL 1097 OpMIPSSRLconst 1098 OpMIPSSRA 1099 OpMIPSSRAconst 1100 OpMIPSCLZ 1101 OpMIPSSGT 1102 OpMIPSSGTconst 1103 OpMIPSSGTzero 1104 OpMIPSSGTU 1105 OpMIPSSGTUconst 1106 OpMIPSSGTUzero 1107 OpMIPSCMPEQF 1108 OpMIPSCMPEQD 1109 OpMIPSCMPGEF 1110 OpMIPSCMPGED 1111 OpMIPSCMPGTF 1112 OpMIPSCMPGTD 1113 OpMIPSMOVWconst 1114 OpMIPSMOVFconst 1115 OpMIPSMOVDconst 1116 OpMIPSMOVWaddr 1117 OpMIPSMOVBload 1118 OpMIPSMOVBUload 1119 OpMIPSMOVHload 1120 OpMIPSMOVHUload 1121 OpMIPSMOVWload 1122 OpMIPSMOVFload 1123 OpMIPSMOVDload 1124 OpMIPSMOVBstore 1125 OpMIPSMOVHstore 1126 OpMIPSMOVWstore 1127 OpMIPSMOVFstore 1128 OpMIPSMOVDstore 1129 OpMIPSMOVBstorezero 1130 OpMIPSMOVHstorezero 1131 OpMIPSMOVWstorezero 1132 OpMIPSMOVBreg 1133 OpMIPSMOVBUreg 1134 OpMIPSMOVHreg 1135 OpMIPSMOVHUreg 1136 OpMIPSMOVWreg 1137 OpMIPSMOVWnop 1138 OpMIPSCMOVZ 1139 OpMIPSCMOVZzero 1140 OpMIPSMOVWF 1141 OpMIPSMOVWD 1142 OpMIPSTRUNCFW 1143 OpMIPSTRUNCDW 1144 OpMIPSMOVFD 1145 OpMIPSMOVDF 1146 OpMIPSCALLstatic 1147 OpMIPSCALLclosure 1148 OpMIPSCALLinter 1149 OpMIPSLoweredAtomicLoad 1150 OpMIPSLoweredAtomicStore 1151 OpMIPSLoweredAtomicStorezero 1152 OpMIPSLoweredAtomicExchange 1153 OpMIPSLoweredAtomicAdd 1154 OpMIPSLoweredAtomicAddconst 1155 OpMIPSLoweredAtomicCas 1156 OpMIPSLoweredAtomicAnd 1157 OpMIPSLoweredAtomicOr 1158 OpMIPSLoweredZero 1159 OpMIPSLoweredMove 1160 OpMIPSLoweredNilCheck 1161 OpMIPSFPFlagTrue 1162 OpMIPSFPFlagFalse 1163 OpMIPSLoweredGetClosurePtr 1164 OpMIPSMOVWconvert 1165 1166 OpMIPS64ADDV 1167 OpMIPS64ADDVconst 1168 OpMIPS64SUBV 1169 OpMIPS64SUBVconst 1170 OpMIPS64MULV 1171 OpMIPS64MULVU 1172 OpMIPS64DIVV 1173 OpMIPS64DIVVU 1174 OpMIPS64ADDF 1175 OpMIPS64ADDD 1176 OpMIPS64SUBF 1177 OpMIPS64SUBD 1178 OpMIPS64MULF 1179 OpMIPS64MULD 1180 OpMIPS64DIVF 1181 OpMIPS64DIVD 1182 OpMIPS64AND 1183 OpMIPS64ANDconst 1184 OpMIPS64OR 1185 OpMIPS64ORconst 1186 OpMIPS64XOR 1187 OpMIPS64XORconst 1188 OpMIPS64NOR 1189 OpMIPS64NORconst 1190 OpMIPS64NEGV 1191 OpMIPS64NEGF 1192 OpMIPS64NEGD 1193 OpMIPS64SLLV 1194 OpMIPS64SLLVconst 1195 OpMIPS64SRLV 1196 OpMIPS64SRLVconst 1197 OpMIPS64SRAV 1198 OpMIPS64SRAVconst 1199 OpMIPS64SGT 1200 OpMIPS64SGTconst 1201 OpMIPS64SGTU 1202 OpMIPS64SGTUconst 1203 OpMIPS64CMPEQF 1204 OpMIPS64CMPEQD 1205 OpMIPS64CMPGEF 1206 OpMIPS64CMPGED 1207 OpMIPS64CMPGTF 1208 OpMIPS64CMPGTD 1209 OpMIPS64MOVVconst 1210 OpMIPS64MOVFconst 1211 OpMIPS64MOVDconst 1212 OpMIPS64MOVVaddr 1213 OpMIPS64MOVBload 1214 OpMIPS64MOVBUload 1215 OpMIPS64MOVHload 1216 OpMIPS64MOVHUload 1217 OpMIPS64MOVWload 1218 OpMIPS64MOVWUload 1219 OpMIPS64MOVVload 1220 OpMIPS64MOVFload 1221 OpMIPS64MOVDload 1222 OpMIPS64MOVBstore 1223 OpMIPS64MOVHstore 1224 OpMIPS64MOVWstore 1225 OpMIPS64MOVVstore 1226 OpMIPS64MOVFstore 1227 OpMIPS64MOVDstore 1228 OpMIPS64MOVBstorezero 1229 OpMIPS64MOVHstorezero 1230 OpMIPS64MOVWstorezero 1231 OpMIPS64MOVVstorezero 1232 OpMIPS64MOVBreg 1233 OpMIPS64MOVBUreg 1234 OpMIPS64MOVHreg 1235 OpMIPS64MOVHUreg 1236 OpMIPS64MOVWreg 1237 OpMIPS64MOVWUreg 1238 OpMIPS64MOVVreg 1239 OpMIPS64MOVVnop 1240 OpMIPS64MOVWF 1241 OpMIPS64MOVWD 1242 OpMIPS64MOVVF 1243 OpMIPS64MOVVD 1244 OpMIPS64TRUNCFW 1245 OpMIPS64TRUNCDW 1246 OpMIPS64TRUNCFV 1247 OpMIPS64TRUNCDV 1248 OpMIPS64MOVFD 1249 OpMIPS64MOVDF 1250 OpMIPS64CALLstatic 1251 OpMIPS64CALLclosure 1252 OpMIPS64CALLinter 1253 OpMIPS64DUFFZERO 1254 OpMIPS64LoweredZero 1255 OpMIPS64LoweredMove 1256 OpMIPS64LoweredNilCheck 1257 OpMIPS64FPFlagTrue 1258 OpMIPS64FPFlagFalse 1259 OpMIPS64LoweredGetClosurePtr 1260 OpMIPS64MOVVconvert 1261 1262 OpPPC64ADD 1263 OpPPC64ADDconst 1264 OpPPC64FADD 1265 OpPPC64FADDS 1266 OpPPC64SUB 1267 OpPPC64FSUB 1268 OpPPC64FSUBS 1269 OpPPC64MULLD 1270 OpPPC64MULLW 1271 OpPPC64MULHD 1272 OpPPC64MULHW 1273 OpPPC64MULHDU 1274 OpPPC64MULHWU 1275 OpPPC64FMUL 1276 OpPPC64FMULS 1277 OpPPC64FMADD 1278 OpPPC64FMADDS 1279 OpPPC64FMSUB 1280 OpPPC64FMSUBS 1281 OpPPC64SRAD 1282 OpPPC64SRAW 1283 OpPPC64SRD 1284 OpPPC64SRW 1285 OpPPC64SLD 1286 OpPPC64SLW 1287 OpPPC64ADDconstForCarry 1288 OpPPC64MaskIfNotCarry 1289 OpPPC64SRADconst 1290 OpPPC64SRAWconst 1291 OpPPC64SRDconst 1292 OpPPC64SRWconst 1293 OpPPC64SLDconst 1294 OpPPC64SLWconst 1295 OpPPC64ROTLconst 1296 OpPPC64ROTLWconst 1297 OpPPC64FDIV 1298 OpPPC64FDIVS 1299 OpPPC64DIVD 1300 OpPPC64DIVW 1301 OpPPC64DIVDU 1302 OpPPC64DIVWU 1303 OpPPC64FCTIDZ 1304 OpPPC64FCTIWZ 1305 OpPPC64FCFID 1306 OpPPC64FRSP 1307 OpPPC64Xf2i64 1308 OpPPC64Xi2f64 1309 OpPPC64AND 1310 OpPPC64ANDN 1311 OpPPC64OR 1312 OpPPC64ORN 1313 OpPPC64NOR 1314 OpPPC64XOR 1315 OpPPC64EQV 1316 OpPPC64NEG 1317 OpPPC64FNEG 1318 OpPPC64FSQRT 1319 OpPPC64FSQRTS 1320 OpPPC64ORconst 1321 OpPPC64XORconst 1322 OpPPC64ANDconst 1323 OpPPC64ANDCCconst 1324 OpPPC64MOVBreg 1325 OpPPC64MOVBZreg 1326 OpPPC64MOVHreg 1327 OpPPC64MOVHZreg 1328 OpPPC64MOVWreg 1329 OpPPC64MOVWZreg 1330 OpPPC64MOVBZload 1331 OpPPC64MOVHload 1332 OpPPC64MOVHZload 1333 OpPPC64MOVWload 1334 OpPPC64MOVWZload 1335 OpPPC64MOVDload 1336 OpPPC64FMOVDload 1337 OpPPC64FMOVSload 1338 OpPPC64MOVBstore 1339 OpPPC64MOVHstore 1340 OpPPC64MOVWstore 1341 OpPPC64MOVDstore 1342 OpPPC64FMOVDstore 1343 OpPPC64FMOVSstore 1344 OpPPC64MOVBstorezero 1345 OpPPC64MOVHstorezero 1346 OpPPC64MOVWstorezero 1347 OpPPC64MOVDstorezero 1348 OpPPC64MOVDaddr 1349 OpPPC64MOVDconst 1350 OpPPC64FMOVDconst 1351 OpPPC64FMOVSconst 1352 OpPPC64FCMPU 1353 OpPPC64CMP 1354 OpPPC64CMPU 1355 OpPPC64CMPW 1356 OpPPC64CMPWU 1357 OpPPC64CMPconst 1358 OpPPC64CMPUconst 1359 OpPPC64CMPWconst 1360 OpPPC64CMPWUconst 1361 OpPPC64Equal 1362 OpPPC64NotEqual 1363 OpPPC64LessThan 1364 OpPPC64FLessThan 1365 OpPPC64LessEqual 1366 OpPPC64FLessEqual 1367 OpPPC64GreaterThan 1368 OpPPC64FGreaterThan 1369 OpPPC64GreaterEqual 1370 OpPPC64FGreaterEqual 1371 OpPPC64LoweredGetClosurePtr 1372 OpPPC64LoweredNilCheck 1373 OpPPC64LoweredRound32F 1374 OpPPC64LoweredRound64F 1375 OpPPC64MOVDconvert 1376 OpPPC64CALLstatic 1377 OpPPC64CALLclosure 1378 OpPPC64CALLinter 1379 OpPPC64LoweredZero 1380 OpPPC64LoweredMove 1381 OpPPC64LoweredAtomicStore32 1382 OpPPC64LoweredAtomicStore64 1383 OpPPC64LoweredAtomicLoad32 1384 OpPPC64LoweredAtomicLoad64 1385 OpPPC64LoweredAtomicLoadPtr 1386 OpPPC64LoweredAtomicAdd32 1387 OpPPC64LoweredAtomicAdd64 1388 OpPPC64LoweredAtomicExchange32 1389 OpPPC64LoweredAtomicExchange64 1390 OpPPC64LoweredAtomicCas64 1391 OpPPC64LoweredAtomicCas32 1392 OpPPC64LoweredAtomicAnd8 1393 OpPPC64LoweredAtomicOr8 1394 OpPPC64InvertFlags 1395 OpPPC64FlagEQ 1396 OpPPC64FlagLT 1397 OpPPC64FlagGT 1398 1399 OpS390XFADDS 1400 OpS390XFADD 1401 OpS390XFSUBS 1402 OpS390XFSUB 1403 OpS390XFMULS 1404 OpS390XFMUL 1405 OpS390XFDIVS 1406 OpS390XFDIV 1407 OpS390XFNEGS 1408 OpS390XFNEG 1409 OpS390XFMADDS 1410 OpS390XFMADD 1411 OpS390XFMSUBS 1412 OpS390XFMSUB 1413 OpS390XFMOVSload 1414 OpS390XFMOVDload 1415 OpS390XFMOVSconst 1416 OpS390XFMOVDconst 1417 OpS390XFMOVSloadidx 1418 OpS390XFMOVDloadidx 1419 OpS390XFMOVSstore 1420 OpS390XFMOVDstore 1421 OpS390XFMOVSstoreidx 1422 OpS390XFMOVDstoreidx 1423 OpS390XADD 1424 OpS390XADDW 1425 OpS390XADDconst 1426 OpS390XADDWconst 1427 OpS390XADDload 1428 OpS390XADDWload 1429 OpS390XSUB 1430 OpS390XSUBW 1431 OpS390XSUBconst 1432 OpS390XSUBWconst 1433 OpS390XSUBload 1434 OpS390XSUBWload 1435 OpS390XMULLD 1436 OpS390XMULLW 1437 OpS390XMULLDconst 1438 OpS390XMULLWconst 1439 OpS390XMULLDload 1440 OpS390XMULLWload 1441 OpS390XMULHD 1442 OpS390XMULHDU 1443 OpS390XDIVD 1444 OpS390XDIVW 1445 OpS390XDIVDU 1446 OpS390XDIVWU 1447 OpS390XMODD 1448 OpS390XMODW 1449 OpS390XMODDU 1450 OpS390XMODWU 1451 OpS390XAND 1452 OpS390XANDW 1453 OpS390XANDconst 1454 OpS390XANDWconst 1455 OpS390XANDload 1456 OpS390XANDWload 1457 OpS390XOR 1458 OpS390XORW 1459 OpS390XORconst 1460 OpS390XORWconst 1461 OpS390XORload 1462 OpS390XORWload 1463 OpS390XXOR 1464 OpS390XXORW 1465 OpS390XXORconst 1466 OpS390XXORWconst 1467 OpS390XXORload 1468 OpS390XXORWload 1469 OpS390XCMP 1470 OpS390XCMPW 1471 OpS390XCMPU 1472 OpS390XCMPWU 1473 OpS390XCMPconst 1474 OpS390XCMPWconst 1475 OpS390XCMPUconst 1476 OpS390XCMPWUconst 1477 OpS390XFCMPS 1478 OpS390XFCMP 1479 OpS390XSLD 1480 OpS390XSLW 1481 OpS390XSLDconst 1482 OpS390XSLWconst 1483 OpS390XSRD 1484 OpS390XSRW 1485 OpS390XSRDconst 1486 OpS390XSRWconst 1487 OpS390XSRAD 1488 OpS390XSRAW 1489 OpS390XSRADconst 1490 OpS390XSRAWconst 1491 OpS390XRLLGconst 1492 OpS390XRLLconst 1493 OpS390XNEG 1494 OpS390XNEGW 1495 OpS390XNOT 1496 OpS390XNOTW 1497 OpS390XFSQRT 1498 OpS390XSUBEcarrymask 1499 OpS390XSUBEWcarrymask 1500 OpS390XMOVDEQ 1501 OpS390XMOVDNE 1502 OpS390XMOVDLT 1503 OpS390XMOVDLE 1504 OpS390XMOVDGT 1505 OpS390XMOVDGE 1506 OpS390XMOVDGTnoinv 1507 OpS390XMOVDGEnoinv 1508 OpS390XMOVBreg 1509 OpS390XMOVBZreg 1510 OpS390XMOVHreg 1511 OpS390XMOVHZreg 1512 OpS390XMOVWreg 1513 OpS390XMOVWZreg 1514 OpS390XMOVDreg 1515 OpS390XMOVDnop 1516 OpS390XMOVDconst 1517 OpS390XCFDBRA 1518 OpS390XCGDBRA 1519 OpS390XCFEBRA 1520 OpS390XCGEBRA 1521 OpS390XCEFBRA 1522 OpS390XCDFBRA 1523 OpS390XCEGBRA 1524 OpS390XCDGBRA 1525 OpS390XLEDBR 1526 OpS390XLDEBR 1527 OpS390XMOVDaddr 1528 OpS390XMOVDaddridx 1529 OpS390XMOVBZload 1530 OpS390XMOVBload 1531 OpS390XMOVHZload 1532 OpS390XMOVHload 1533 OpS390XMOVWZload 1534 OpS390XMOVWload 1535 OpS390XMOVDload 1536 OpS390XMOVWBR 1537 OpS390XMOVDBR 1538 OpS390XMOVHBRload 1539 OpS390XMOVWBRload 1540 OpS390XMOVDBRload 1541 OpS390XMOVBstore 1542 OpS390XMOVHstore 1543 OpS390XMOVWstore 1544 OpS390XMOVDstore 1545 OpS390XMOVHBRstore 1546 OpS390XMOVWBRstore 1547 OpS390XMOVDBRstore 1548 OpS390XMVC 1549 OpS390XMOVBZloadidx 1550 OpS390XMOVHZloadidx 1551 OpS390XMOVWZloadidx 1552 OpS390XMOVDloadidx 1553 OpS390XMOVHBRloadidx 1554 OpS390XMOVWBRloadidx 1555 OpS390XMOVDBRloadidx 1556 OpS390XMOVBstoreidx 1557 OpS390XMOVHstoreidx 1558 OpS390XMOVWstoreidx 1559 OpS390XMOVDstoreidx 1560 OpS390XMOVHBRstoreidx 1561 OpS390XMOVWBRstoreidx 1562 OpS390XMOVDBRstoreidx 1563 OpS390XMOVBstoreconst 1564 OpS390XMOVHstoreconst 1565 OpS390XMOVWstoreconst 1566 OpS390XMOVDstoreconst 1567 OpS390XCLEAR 1568 OpS390XCALLstatic 1569 OpS390XCALLclosure 1570 OpS390XCALLinter 1571 OpS390XInvertFlags 1572 OpS390XLoweredGetG 1573 OpS390XLoweredGetClosurePtr 1574 OpS390XLoweredNilCheck 1575 OpS390XLoweredRound32F 1576 OpS390XLoweredRound64F 1577 OpS390XMOVDconvert 1578 OpS390XFlagEQ 1579 OpS390XFlagLT 1580 OpS390XFlagGT 1581 OpS390XMOVWZatomicload 1582 OpS390XMOVDatomicload 1583 OpS390XMOVWatomicstore 1584 OpS390XMOVDatomicstore 1585 OpS390XLAA 1586 OpS390XLAAG 1587 OpS390XAddTupleFirst32 1588 OpS390XAddTupleFirst64 1589 OpS390XLoweredAtomicCas32 1590 OpS390XLoweredAtomicCas64 1591 OpS390XLoweredAtomicExchange32 1592 OpS390XLoweredAtomicExchange64 1593 OpS390XFLOGR 1594 OpS390XSTMG2 1595 OpS390XSTMG3 1596 OpS390XSTMG4 1597 OpS390XSTM2 1598 OpS390XSTM3 1599 OpS390XSTM4 1600 OpS390XLoweredMove 1601 OpS390XLoweredZero 1602 1603 OpAdd8 1604 OpAdd16 1605 OpAdd32 1606 OpAdd64 1607 OpAddPtr 1608 OpAdd32F 1609 OpAdd64F 1610 OpSub8 1611 OpSub16 1612 OpSub32 1613 OpSub64 1614 OpSubPtr 1615 OpSub32F 1616 OpSub64F 1617 OpMul8 1618 OpMul16 1619 OpMul32 1620 OpMul64 1621 OpMul32F 1622 OpMul64F 1623 OpDiv32F 1624 OpDiv64F 1625 OpHmul32 1626 OpHmul32u 1627 OpHmul64 1628 OpHmul64u 1629 OpMul32uhilo 1630 OpMul64uhilo 1631 OpAvg32u 1632 OpAvg64u 1633 OpDiv8 1634 OpDiv8u 1635 OpDiv16 1636 OpDiv16u 1637 OpDiv32 1638 OpDiv32u 1639 OpDiv64 1640 OpDiv64u 1641 OpDiv128u 1642 OpMod8 1643 OpMod8u 1644 OpMod16 1645 OpMod16u 1646 OpMod32 1647 OpMod32u 1648 OpMod64 1649 OpMod64u 1650 OpAnd8 1651 OpAnd16 1652 OpAnd32 1653 OpAnd64 1654 OpOr8 1655 OpOr16 1656 OpOr32 1657 OpOr64 1658 OpXor8 1659 OpXor16 1660 OpXor32 1661 OpXor64 1662 OpLsh8x8 1663 OpLsh8x16 1664 OpLsh8x32 1665 OpLsh8x64 1666 OpLsh16x8 1667 OpLsh16x16 1668 OpLsh16x32 1669 OpLsh16x64 1670 OpLsh32x8 1671 OpLsh32x16 1672 OpLsh32x32 1673 OpLsh32x64 1674 OpLsh64x8 1675 OpLsh64x16 1676 OpLsh64x32 1677 OpLsh64x64 1678 OpRsh8x8 1679 OpRsh8x16 1680 OpRsh8x32 1681 OpRsh8x64 1682 OpRsh16x8 1683 OpRsh16x16 1684 OpRsh16x32 1685 OpRsh16x64 1686 OpRsh32x8 1687 OpRsh32x16 1688 OpRsh32x32 1689 OpRsh32x64 1690 OpRsh64x8 1691 OpRsh64x16 1692 OpRsh64x32 1693 OpRsh64x64 1694 OpRsh8Ux8 1695 OpRsh8Ux16 1696 OpRsh8Ux32 1697 OpRsh8Ux64 1698 OpRsh16Ux8 1699 OpRsh16Ux16 1700 OpRsh16Ux32 1701 OpRsh16Ux64 1702 OpRsh32Ux8 1703 OpRsh32Ux16 1704 OpRsh32Ux32 1705 OpRsh32Ux64 1706 OpRsh64Ux8 1707 OpRsh64Ux16 1708 OpRsh64Ux32 1709 OpRsh64Ux64 1710 OpEq8 1711 OpEq16 1712 OpEq32 1713 OpEq64 1714 OpEqPtr 1715 OpEqInter 1716 OpEqSlice 1717 OpEq32F 1718 OpEq64F 1719 OpNeq8 1720 OpNeq16 1721 OpNeq32 1722 OpNeq64 1723 OpNeqPtr 1724 OpNeqInter 1725 OpNeqSlice 1726 OpNeq32F 1727 OpNeq64F 1728 OpLess8 1729 OpLess8U 1730 OpLess16 1731 OpLess16U 1732 OpLess32 1733 OpLess32U 1734 OpLess64 1735 OpLess64U 1736 OpLess32F 1737 OpLess64F 1738 OpLeq8 1739 OpLeq8U 1740 OpLeq16 1741 OpLeq16U 1742 OpLeq32 1743 OpLeq32U 1744 OpLeq64 1745 OpLeq64U 1746 OpLeq32F 1747 OpLeq64F 1748 OpGreater8 1749 OpGreater8U 1750 OpGreater16 1751 OpGreater16U 1752 OpGreater32 1753 OpGreater32U 1754 OpGreater64 1755 OpGreater64U 1756 OpGreater32F 1757 OpGreater64F 1758 OpGeq8 1759 OpGeq8U 1760 OpGeq16 1761 OpGeq16U 1762 OpGeq32 1763 OpGeq32U 1764 OpGeq64 1765 OpGeq64U 1766 OpGeq32F 1767 OpGeq64F 1768 OpAndB 1769 OpOrB 1770 OpEqB 1771 OpNeqB 1772 OpNot 1773 OpNeg8 1774 OpNeg16 1775 OpNeg32 1776 OpNeg64 1777 OpNeg32F 1778 OpNeg64F 1779 OpCom8 1780 OpCom16 1781 OpCom32 1782 OpCom64 1783 OpCtz32 1784 OpCtz64 1785 OpBitLen32 1786 OpBitLen64 1787 OpBswap32 1788 OpBswap64 1789 OpBitRev8 1790 OpBitRev16 1791 OpBitRev32 1792 OpBitRev64 1793 OpPopCount8 1794 OpPopCount16 1795 OpPopCount32 1796 OpPopCount64 1797 OpSqrt 1798 OpPhi 1799 OpCopy 1800 OpConvert 1801 OpConstBool 1802 OpConstString 1803 OpConstNil 1804 OpConst8 1805 OpConst16 1806 OpConst32 1807 OpConst64 1808 OpConst32F 1809 OpConst64F 1810 OpConstInterface 1811 OpConstSlice 1812 OpInitMem 1813 OpArg 1814 OpAddr 1815 OpSP 1816 OpSB 1817 OpLoad 1818 OpStore 1819 OpMove 1820 OpZero 1821 OpStoreWB 1822 OpMoveWB 1823 OpZeroWB 1824 OpClosureCall 1825 OpStaticCall 1826 OpInterCall 1827 OpSignExt8to16 1828 OpSignExt8to32 1829 OpSignExt8to64 1830 OpSignExt16to32 1831 OpSignExt16to64 1832 OpSignExt32to64 1833 OpZeroExt8to16 1834 OpZeroExt8to32 1835 OpZeroExt8to64 1836 OpZeroExt16to32 1837 OpZeroExt16to64 1838 OpZeroExt32to64 1839 OpTrunc16to8 1840 OpTrunc32to8 1841 OpTrunc32to16 1842 OpTrunc64to8 1843 OpTrunc64to16 1844 OpTrunc64to32 1845 OpCvt32to32F 1846 OpCvt32to64F 1847 OpCvt64to32F 1848 OpCvt64to64F 1849 OpCvt32Fto32 1850 OpCvt32Fto64 1851 OpCvt64Fto32 1852 OpCvt64Fto64 1853 OpCvt32Fto64F 1854 OpCvt64Fto32F 1855 OpRound32F 1856 OpRound64F 1857 OpIsNonNil 1858 OpIsInBounds 1859 OpIsSliceInBounds 1860 OpNilCheck 1861 OpGetG 1862 OpGetClosurePtr 1863 OpPtrIndex 1864 OpOffPtr 1865 OpSliceMake 1866 OpSlicePtr 1867 OpSliceLen 1868 OpSliceCap 1869 OpComplexMake 1870 OpComplexReal 1871 OpComplexImag 1872 OpStringMake 1873 OpStringPtr 1874 OpStringLen 1875 OpIMake 1876 OpITab 1877 OpIData 1878 OpStructMake0 1879 OpStructMake1 1880 OpStructMake2 1881 OpStructMake3 1882 OpStructMake4 1883 OpStructSelect 1884 OpArrayMake0 1885 OpArrayMake1 1886 OpArraySelect 1887 OpStoreReg 1888 OpLoadReg 1889 OpFwdRef 1890 OpUnknown 1891 OpVarDef 1892 OpVarKill 1893 OpVarLive 1894 OpKeepAlive 1895 OpInt64Make 1896 OpInt64Hi 1897 OpInt64Lo 1898 OpAdd32carry 1899 OpAdd32withcarry 1900 OpSub32carry 1901 OpSub32withcarry 1902 OpSignmask 1903 OpZeromask 1904 OpSlicemask 1905 OpCvt32Uto32F 1906 OpCvt32Uto64F 1907 OpCvt32Fto32U 1908 OpCvt64Fto32U 1909 OpCvt64Uto32F 1910 OpCvt64Uto64F 1911 OpCvt32Fto64U 1912 OpCvt64Fto64U 1913 OpSelect0 1914 OpSelect1 1915 OpAtomicLoad32 1916 OpAtomicLoad64 1917 OpAtomicLoadPtr 1918 OpAtomicStore32 1919 OpAtomicStore64 1920 OpAtomicStorePtrNoWB 1921 OpAtomicExchange32 1922 OpAtomicExchange64 1923 OpAtomicAdd32 1924 OpAtomicAdd64 1925 OpAtomicCompareAndSwap32 1926 OpAtomicCompareAndSwap64 1927 OpAtomicAnd8 1928 OpAtomicOr8 1929 OpClobber 1930 ) 1931 1932 var opcodeTable = [...]opInfo{ 1933 {name: "OpInvalid"}, 1934 1935 { 1936 name: "ADDSS", 1937 argLen: 2, 1938 commutative: true, 1939 resultInArg0: true, 1940 usesScratch: true, 1941 asm: x86.AADDSS, 1942 reg: regInfo{ 1943 inputs: []inputInfo{ 1944 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1945 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1946 }, 1947 outputs: []outputInfo{ 1948 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1949 }, 1950 }, 1951 }, 1952 { 1953 name: "ADDSD", 1954 argLen: 2, 1955 commutative: true, 1956 resultInArg0: true, 1957 asm: x86.AADDSD, 1958 reg: regInfo{ 1959 inputs: []inputInfo{ 1960 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1961 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1962 }, 1963 outputs: []outputInfo{ 1964 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1965 }, 1966 }, 1967 }, 1968 { 1969 name: "SUBSS", 1970 argLen: 2, 1971 resultInArg0: true, 1972 usesScratch: true, 1973 asm: x86.ASUBSS, 1974 reg: regInfo{ 1975 inputs: []inputInfo{ 1976 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1977 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1978 }, 1979 outputs: []outputInfo{ 1980 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1981 }, 1982 }, 1983 }, 1984 { 1985 name: "SUBSD", 1986 argLen: 2, 1987 resultInArg0: true, 1988 asm: x86.ASUBSD, 1989 reg: regInfo{ 1990 inputs: []inputInfo{ 1991 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1992 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1993 }, 1994 outputs: []outputInfo{ 1995 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1996 }, 1997 }, 1998 }, 1999 { 2000 name: "MULSS", 2001 argLen: 2, 2002 commutative: true, 2003 resultInArg0: true, 2004 usesScratch: true, 2005 asm: x86.AMULSS, 2006 reg: regInfo{ 2007 inputs: []inputInfo{ 2008 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2009 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2010 }, 2011 outputs: []outputInfo{ 2012 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2013 }, 2014 }, 2015 }, 2016 { 2017 name: "MULSD", 2018 argLen: 2, 2019 commutative: true, 2020 resultInArg0: true, 2021 asm: x86.AMULSD, 2022 reg: regInfo{ 2023 inputs: []inputInfo{ 2024 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2025 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2026 }, 2027 outputs: []outputInfo{ 2028 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2029 }, 2030 }, 2031 }, 2032 { 2033 name: "DIVSS", 2034 argLen: 2, 2035 resultInArg0: true, 2036 usesScratch: true, 2037 asm: x86.ADIVSS, 2038 reg: regInfo{ 2039 inputs: []inputInfo{ 2040 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2041 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2042 }, 2043 outputs: []outputInfo{ 2044 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2045 }, 2046 }, 2047 }, 2048 { 2049 name: "DIVSD", 2050 argLen: 2, 2051 resultInArg0: true, 2052 asm: x86.ADIVSD, 2053 reg: regInfo{ 2054 inputs: []inputInfo{ 2055 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2056 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2057 }, 2058 outputs: []outputInfo{ 2059 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2060 }, 2061 }, 2062 }, 2063 { 2064 name: "MOVSSload", 2065 auxType: auxSymOff, 2066 argLen: 2, 2067 faultOnNilArg0: true, 2068 symEffect: SymRead, 2069 asm: x86.AMOVSS, 2070 reg: regInfo{ 2071 inputs: []inputInfo{ 2072 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2073 }, 2074 outputs: []outputInfo{ 2075 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2076 }, 2077 }, 2078 }, 2079 { 2080 name: "MOVSDload", 2081 auxType: auxSymOff, 2082 argLen: 2, 2083 faultOnNilArg0: true, 2084 symEffect: SymRead, 2085 asm: x86.AMOVSD, 2086 reg: regInfo{ 2087 inputs: []inputInfo{ 2088 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2089 }, 2090 outputs: []outputInfo{ 2091 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2092 }, 2093 }, 2094 }, 2095 { 2096 name: "MOVSSconst", 2097 auxType: auxFloat32, 2098 argLen: 0, 2099 rematerializeable: true, 2100 asm: x86.AMOVSS, 2101 reg: regInfo{ 2102 outputs: []outputInfo{ 2103 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2104 }, 2105 }, 2106 }, 2107 { 2108 name: "MOVSDconst", 2109 auxType: auxFloat64, 2110 argLen: 0, 2111 rematerializeable: true, 2112 asm: x86.AMOVSD, 2113 reg: regInfo{ 2114 outputs: []outputInfo{ 2115 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2116 }, 2117 }, 2118 }, 2119 { 2120 name: "MOVSSloadidx1", 2121 auxType: auxSymOff, 2122 argLen: 3, 2123 symEffect: SymRead, 2124 asm: x86.AMOVSS, 2125 reg: regInfo{ 2126 inputs: []inputInfo{ 2127 {1, 255}, // AX CX DX BX SP BP SI DI 2128 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2129 }, 2130 outputs: []outputInfo{ 2131 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2132 }, 2133 }, 2134 }, 2135 { 2136 name: "MOVSSloadidx4", 2137 auxType: auxSymOff, 2138 argLen: 3, 2139 symEffect: SymRead, 2140 asm: x86.AMOVSS, 2141 reg: regInfo{ 2142 inputs: []inputInfo{ 2143 {1, 255}, // AX CX DX BX SP BP SI DI 2144 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2145 }, 2146 outputs: []outputInfo{ 2147 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2148 }, 2149 }, 2150 }, 2151 { 2152 name: "MOVSDloadidx1", 2153 auxType: auxSymOff, 2154 argLen: 3, 2155 symEffect: SymRead, 2156 asm: x86.AMOVSD, 2157 reg: regInfo{ 2158 inputs: []inputInfo{ 2159 {1, 255}, // AX CX DX BX SP BP SI DI 2160 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2161 }, 2162 outputs: []outputInfo{ 2163 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2164 }, 2165 }, 2166 }, 2167 { 2168 name: "MOVSDloadidx8", 2169 auxType: auxSymOff, 2170 argLen: 3, 2171 symEffect: SymRead, 2172 asm: x86.AMOVSD, 2173 reg: regInfo{ 2174 inputs: []inputInfo{ 2175 {1, 255}, // AX CX DX BX SP BP SI DI 2176 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2177 }, 2178 outputs: []outputInfo{ 2179 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2180 }, 2181 }, 2182 }, 2183 { 2184 name: "MOVSSstore", 2185 auxType: auxSymOff, 2186 argLen: 3, 2187 faultOnNilArg0: true, 2188 symEffect: SymWrite, 2189 asm: x86.AMOVSS, 2190 reg: regInfo{ 2191 inputs: []inputInfo{ 2192 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2193 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2194 }, 2195 }, 2196 }, 2197 { 2198 name: "MOVSDstore", 2199 auxType: auxSymOff, 2200 argLen: 3, 2201 faultOnNilArg0: true, 2202 symEffect: SymWrite, 2203 asm: x86.AMOVSD, 2204 reg: regInfo{ 2205 inputs: []inputInfo{ 2206 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2207 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2208 }, 2209 }, 2210 }, 2211 { 2212 name: "MOVSSstoreidx1", 2213 auxType: auxSymOff, 2214 argLen: 4, 2215 symEffect: SymWrite, 2216 asm: x86.AMOVSS, 2217 reg: regInfo{ 2218 inputs: []inputInfo{ 2219 {1, 255}, // AX CX DX BX SP BP SI DI 2220 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2221 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2222 }, 2223 }, 2224 }, 2225 { 2226 name: "MOVSSstoreidx4", 2227 auxType: auxSymOff, 2228 argLen: 4, 2229 symEffect: SymWrite, 2230 asm: x86.AMOVSS, 2231 reg: regInfo{ 2232 inputs: []inputInfo{ 2233 {1, 255}, // AX CX DX BX SP BP SI DI 2234 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2235 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2236 }, 2237 }, 2238 }, 2239 { 2240 name: "MOVSDstoreidx1", 2241 auxType: auxSymOff, 2242 argLen: 4, 2243 symEffect: SymWrite, 2244 asm: x86.AMOVSD, 2245 reg: regInfo{ 2246 inputs: []inputInfo{ 2247 {1, 255}, // AX CX DX BX SP BP SI DI 2248 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2249 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2250 }, 2251 }, 2252 }, 2253 { 2254 name: "MOVSDstoreidx8", 2255 auxType: auxSymOff, 2256 argLen: 4, 2257 symEffect: SymWrite, 2258 asm: x86.AMOVSD, 2259 reg: regInfo{ 2260 inputs: []inputInfo{ 2261 {1, 255}, // AX CX DX BX SP BP SI DI 2262 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2263 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2264 }, 2265 }, 2266 }, 2267 { 2268 name: "ADDL", 2269 argLen: 2, 2270 commutative: true, 2271 clobberFlags: true, 2272 asm: x86.AADDL, 2273 reg: regInfo{ 2274 inputs: []inputInfo{ 2275 {1, 239}, // AX CX DX BX BP SI DI 2276 {0, 255}, // AX CX DX BX SP BP SI DI 2277 }, 2278 outputs: []outputInfo{ 2279 {0, 239}, // AX CX DX BX BP SI DI 2280 }, 2281 }, 2282 }, 2283 { 2284 name: "ADDLconst", 2285 auxType: auxInt32, 2286 argLen: 1, 2287 clobberFlags: true, 2288 asm: x86.AADDL, 2289 reg: regInfo{ 2290 inputs: []inputInfo{ 2291 {0, 255}, // AX CX DX BX SP BP SI DI 2292 }, 2293 outputs: []outputInfo{ 2294 {0, 239}, // AX CX DX BX BP SI DI 2295 }, 2296 }, 2297 }, 2298 { 2299 name: "ADDLcarry", 2300 argLen: 2, 2301 commutative: true, 2302 resultInArg0: true, 2303 asm: x86.AADDL, 2304 reg: regInfo{ 2305 inputs: []inputInfo{ 2306 {0, 239}, // AX CX DX BX BP SI DI 2307 {1, 239}, // AX CX DX BX BP SI DI 2308 }, 2309 outputs: []outputInfo{ 2310 {1, 0}, 2311 {0, 239}, // AX CX DX BX BP SI DI 2312 }, 2313 }, 2314 }, 2315 { 2316 name: "ADDLconstcarry", 2317 auxType: auxInt32, 2318 argLen: 1, 2319 resultInArg0: true, 2320 asm: x86.AADDL, 2321 reg: regInfo{ 2322 inputs: []inputInfo{ 2323 {0, 239}, // AX CX DX BX BP SI DI 2324 }, 2325 outputs: []outputInfo{ 2326 {1, 0}, 2327 {0, 239}, // AX CX DX BX BP SI DI 2328 }, 2329 }, 2330 }, 2331 { 2332 name: "ADCL", 2333 argLen: 3, 2334 commutative: true, 2335 resultInArg0: true, 2336 clobberFlags: true, 2337 asm: x86.AADCL, 2338 reg: regInfo{ 2339 inputs: []inputInfo{ 2340 {0, 239}, // AX CX DX BX BP SI DI 2341 {1, 239}, // AX CX DX BX BP SI DI 2342 }, 2343 outputs: []outputInfo{ 2344 {0, 239}, // AX CX DX BX BP SI DI 2345 }, 2346 }, 2347 }, 2348 { 2349 name: "ADCLconst", 2350 auxType: auxInt32, 2351 argLen: 2, 2352 resultInArg0: true, 2353 clobberFlags: true, 2354 asm: x86.AADCL, 2355 reg: regInfo{ 2356 inputs: []inputInfo{ 2357 {0, 239}, // AX CX DX BX BP SI DI 2358 }, 2359 outputs: []outputInfo{ 2360 {0, 239}, // AX CX DX BX BP SI DI 2361 }, 2362 }, 2363 }, 2364 { 2365 name: "SUBL", 2366 argLen: 2, 2367 resultInArg0: true, 2368 clobberFlags: true, 2369 asm: x86.ASUBL, 2370 reg: regInfo{ 2371 inputs: []inputInfo{ 2372 {0, 239}, // AX CX DX BX BP SI DI 2373 {1, 239}, // AX CX DX BX BP SI DI 2374 }, 2375 outputs: []outputInfo{ 2376 {0, 239}, // AX CX DX BX BP SI DI 2377 }, 2378 }, 2379 }, 2380 { 2381 name: "SUBLconst", 2382 auxType: auxInt32, 2383 argLen: 1, 2384 resultInArg0: true, 2385 clobberFlags: true, 2386 asm: x86.ASUBL, 2387 reg: regInfo{ 2388 inputs: []inputInfo{ 2389 {0, 239}, // AX CX DX BX BP SI DI 2390 }, 2391 outputs: []outputInfo{ 2392 {0, 239}, // AX CX DX BX BP SI DI 2393 }, 2394 }, 2395 }, 2396 { 2397 name: "SUBLcarry", 2398 argLen: 2, 2399 resultInArg0: true, 2400 asm: x86.ASUBL, 2401 reg: regInfo{ 2402 inputs: []inputInfo{ 2403 {0, 239}, // AX CX DX BX BP SI DI 2404 {1, 239}, // AX CX DX BX BP SI DI 2405 }, 2406 outputs: []outputInfo{ 2407 {1, 0}, 2408 {0, 239}, // AX CX DX BX BP SI DI 2409 }, 2410 }, 2411 }, 2412 { 2413 name: "SUBLconstcarry", 2414 auxType: auxInt32, 2415 argLen: 1, 2416 resultInArg0: true, 2417 asm: x86.ASUBL, 2418 reg: regInfo{ 2419 inputs: []inputInfo{ 2420 {0, 239}, // AX CX DX BX BP SI DI 2421 }, 2422 outputs: []outputInfo{ 2423 {1, 0}, 2424 {0, 239}, // AX CX DX BX BP SI DI 2425 }, 2426 }, 2427 }, 2428 { 2429 name: "SBBL", 2430 argLen: 3, 2431 resultInArg0: true, 2432 clobberFlags: true, 2433 asm: x86.ASBBL, 2434 reg: regInfo{ 2435 inputs: []inputInfo{ 2436 {0, 239}, // AX CX DX BX BP SI DI 2437 {1, 239}, // AX CX DX BX BP SI DI 2438 }, 2439 outputs: []outputInfo{ 2440 {0, 239}, // AX CX DX BX BP SI DI 2441 }, 2442 }, 2443 }, 2444 { 2445 name: "SBBLconst", 2446 auxType: auxInt32, 2447 argLen: 2, 2448 resultInArg0: true, 2449 clobberFlags: true, 2450 asm: x86.ASBBL, 2451 reg: regInfo{ 2452 inputs: []inputInfo{ 2453 {0, 239}, // AX CX DX BX BP SI DI 2454 }, 2455 outputs: []outputInfo{ 2456 {0, 239}, // AX CX DX BX BP SI DI 2457 }, 2458 }, 2459 }, 2460 { 2461 name: "MULL", 2462 argLen: 2, 2463 commutative: true, 2464 resultInArg0: true, 2465 clobberFlags: true, 2466 asm: x86.AIMULL, 2467 reg: regInfo{ 2468 inputs: []inputInfo{ 2469 {0, 239}, // AX CX DX BX BP SI DI 2470 {1, 239}, // AX CX DX BX BP SI DI 2471 }, 2472 outputs: []outputInfo{ 2473 {0, 239}, // AX CX DX BX BP SI DI 2474 }, 2475 }, 2476 }, 2477 { 2478 name: "MULLconst", 2479 auxType: auxInt32, 2480 argLen: 1, 2481 resultInArg0: true, 2482 clobberFlags: true, 2483 asm: x86.AIMULL, 2484 reg: regInfo{ 2485 inputs: []inputInfo{ 2486 {0, 239}, // AX CX DX BX BP SI DI 2487 }, 2488 outputs: []outputInfo{ 2489 {0, 239}, // AX CX DX BX BP SI DI 2490 }, 2491 }, 2492 }, 2493 { 2494 name: "HMULL", 2495 argLen: 2, 2496 commutative: true, 2497 clobberFlags: true, 2498 asm: x86.AIMULL, 2499 reg: regInfo{ 2500 inputs: []inputInfo{ 2501 {0, 1}, // AX 2502 {1, 255}, // AX CX DX BX SP BP SI DI 2503 }, 2504 clobbers: 1, // AX 2505 outputs: []outputInfo{ 2506 {0, 4}, // DX 2507 }, 2508 }, 2509 }, 2510 { 2511 name: "HMULLU", 2512 argLen: 2, 2513 commutative: true, 2514 clobberFlags: true, 2515 asm: x86.AMULL, 2516 reg: regInfo{ 2517 inputs: []inputInfo{ 2518 {0, 1}, // AX 2519 {1, 255}, // AX CX DX BX SP BP SI DI 2520 }, 2521 clobbers: 1, // AX 2522 outputs: []outputInfo{ 2523 {0, 4}, // DX 2524 }, 2525 }, 2526 }, 2527 { 2528 name: "MULLQU", 2529 argLen: 2, 2530 commutative: true, 2531 clobberFlags: true, 2532 asm: x86.AMULL, 2533 reg: regInfo{ 2534 inputs: []inputInfo{ 2535 {0, 1}, // AX 2536 {1, 255}, // AX CX DX BX SP BP SI DI 2537 }, 2538 outputs: []outputInfo{ 2539 {0, 4}, // DX 2540 {1, 1}, // AX 2541 }, 2542 }, 2543 }, 2544 { 2545 name: "AVGLU", 2546 argLen: 2, 2547 commutative: true, 2548 resultInArg0: true, 2549 clobberFlags: true, 2550 reg: regInfo{ 2551 inputs: []inputInfo{ 2552 {0, 239}, // AX CX DX BX BP SI DI 2553 {1, 239}, // AX CX DX BX BP SI DI 2554 }, 2555 outputs: []outputInfo{ 2556 {0, 239}, // AX CX DX BX BP SI DI 2557 }, 2558 }, 2559 }, 2560 { 2561 name: "DIVL", 2562 argLen: 2, 2563 clobberFlags: true, 2564 asm: x86.AIDIVL, 2565 reg: regInfo{ 2566 inputs: []inputInfo{ 2567 {0, 1}, // AX 2568 {1, 251}, // AX CX BX SP BP SI DI 2569 }, 2570 clobbers: 4, // DX 2571 outputs: []outputInfo{ 2572 {0, 1}, // AX 2573 }, 2574 }, 2575 }, 2576 { 2577 name: "DIVW", 2578 argLen: 2, 2579 clobberFlags: true, 2580 asm: x86.AIDIVW, 2581 reg: regInfo{ 2582 inputs: []inputInfo{ 2583 {0, 1}, // AX 2584 {1, 251}, // AX CX BX SP BP SI DI 2585 }, 2586 clobbers: 4, // DX 2587 outputs: []outputInfo{ 2588 {0, 1}, // AX 2589 }, 2590 }, 2591 }, 2592 { 2593 name: "DIVLU", 2594 argLen: 2, 2595 clobberFlags: true, 2596 asm: x86.ADIVL, 2597 reg: regInfo{ 2598 inputs: []inputInfo{ 2599 {0, 1}, // AX 2600 {1, 251}, // AX CX BX SP BP SI DI 2601 }, 2602 clobbers: 4, // DX 2603 outputs: []outputInfo{ 2604 {0, 1}, // AX 2605 }, 2606 }, 2607 }, 2608 { 2609 name: "DIVWU", 2610 argLen: 2, 2611 clobberFlags: true, 2612 asm: x86.ADIVW, 2613 reg: regInfo{ 2614 inputs: []inputInfo{ 2615 {0, 1}, // AX 2616 {1, 251}, // AX CX BX SP BP SI DI 2617 }, 2618 clobbers: 4, // DX 2619 outputs: []outputInfo{ 2620 {0, 1}, // AX 2621 }, 2622 }, 2623 }, 2624 { 2625 name: "MODL", 2626 argLen: 2, 2627 clobberFlags: true, 2628 asm: x86.AIDIVL, 2629 reg: regInfo{ 2630 inputs: []inputInfo{ 2631 {0, 1}, // AX 2632 {1, 251}, // AX CX BX SP BP SI DI 2633 }, 2634 clobbers: 1, // AX 2635 outputs: []outputInfo{ 2636 {0, 4}, // DX 2637 }, 2638 }, 2639 }, 2640 { 2641 name: "MODW", 2642 argLen: 2, 2643 clobberFlags: true, 2644 asm: x86.AIDIVW, 2645 reg: regInfo{ 2646 inputs: []inputInfo{ 2647 {0, 1}, // AX 2648 {1, 251}, // AX CX BX SP BP SI DI 2649 }, 2650 clobbers: 1, // AX 2651 outputs: []outputInfo{ 2652 {0, 4}, // DX 2653 }, 2654 }, 2655 }, 2656 { 2657 name: "MODLU", 2658 argLen: 2, 2659 clobberFlags: true, 2660 asm: x86.ADIVL, 2661 reg: regInfo{ 2662 inputs: []inputInfo{ 2663 {0, 1}, // AX 2664 {1, 251}, // AX CX BX SP BP SI DI 2665 }, 2666 clobbers: 1, // AX 2667 outputs: []outputInfo{ 2668 {0, 4}, // DX 2669 }, 2670 }, 2671 }, 2672 { 2673 name: "MODWU", 2674 argLen: 2, 2675 clobberFlags: true, 2676 asm: x86.ADIVW, 2677 reg: regInfo{ 2678 inputs: []inputInfo{ 2679 {0, 1}, // AX 2680 {1, 251}, // AX CX BX SP BP SI DI 2681 }, 2682 clobbers: 1, // AX 2683 outputs: []outputInfo{ 2684 {0, 4}, // DX 2685 }, 2686 }, 2687 }, 2688 { 2689 name: "ANDL", 2690 argLen: 2, 2691 commutative: true, 2692 resultInArg0: true, 2693 clobberFlags: true, 2694 asm: x86.AANDL, 2695 reg: regInfo{ 2696 inputs: []inputInfo{ 2697 {0, 239}, // AX CX DX BX BP SI DI 2698 {1, 239}, // AX CX DX BX BP SI DI 2699 }, 2700 outputs: []outputInfo{ 2701 {0, 239}, // AX CX DX BX BP SI DI 2702 }, 2703 }, 2704 }, 2705 { 2706 name: "ANDLconst", 2707 auxType: auxInt32, 2708 argLen: 1, 2709 resultInArg0: true, 2710 clobberFlags: true, 2711 asm: x86.AANDL, 2712 reg: regInfo{ 2713 inputs: []inputInfo{ 2714 {0, 239}, // AX CX DX BX BP SI DI 2715 }, 2716 outputs: []outputInfo{ 2717 {0, 239}, // AX CX DX BX BP SI DI 2718 }, 2719 }, 2720 }, 2721 { 2722 name: "ORL", 2723 argLen: 2, 2724 commutative: true, 2725 resultInArg0: true, 2726 clobberFlags: true, 2727 asm: x86.AORL, 2728 reg: regInfo{ 2729 inputs: []inputInfo{ 2730 {0, 239}, // AX CX DX BX BP SI DI 2731 {1, 239}, // AX CX DX BX BP SI DI 2732 }, 2733 outputs: []outputInfo{ 2734 {0, 239}, // AX CX DX BX BP SI DI 2735 }, 2736 }, 2737 }, 2738 { 2739 name: "ORLconst", 2740 auxType: auxInt32, 2741 argLen: 1, 2742 resultInArg0: true, 2743 clobberFlags: true, 2744 asm: x86.AORL, 2745 reg: regInfo{ 2746 inputs: []inputInfo{ 2747 {0, 239}, // AX CX DX BX BP SI DI 2748 }, 2749 outputs: []outputInfo{ 2750 {0, 239}, // AX CX DX BX BP SI DI 2751 }, 2752 }, 2753 }, 2754 { 2755 name: "XORL", 2756 argLen: 2, 2757 commutative: true, 2758 resultInArg0: true, 2759 clobberFlags: true, 2760 asm: x86.AXORL, 2761 reg: regInfo{ 2762 inputs: []inputInfo{ 2763 {0, 239}, // AX CX DX BX BP SI DI 2764 {1, 239}, // AX CX DX BX BP SI DI 2765 }, 2766 outputs: []outputInfo{ 2767 {0, 239}, // AX CX DX BX BP SI DI 2768 }, 2769 }, 2770 }, 2771 { 2772 name: "XORLconst", 2773 auxType: auxInt32, 2774 argLen: 1, 2775 resultInArg0: true, 2776 clobberFlags: true, 2777 asm: x86.AXORL, 2778 reg: regInfo{ 2779 inputs: []inputInfo{ 2780 {0, 239}, // AX CX DX BX BP SI DI 2781 }, 2782 outputs: []outputInfo{ 2783 {0, 239}, // AX CX DX BX BP SI DI 2784 }, 2785 }, 2786 }, 2787 { 2788 name: "CMPL", 2789 argLen: 2, 2790 asm: x86.ACMPL, 2791 reg: regInfo{ 2792 inputs: []inputInfo{ 2793 {0, 255}, // AX CX DX BX SP BP SI DI 2794 {1, 255}, // AX CX DX BX SP BP SI DI 2795 }, 2796 }, 2797 }, 2798 { 2799 name: "CMPW", 2800 argLen: 2, 2801 asm: x86.ACMPW, 2802 reg: regInfo{ 2803 inputs: []inputInfo{ 2804 {0, 255}, // AX CX DX BX SP BP SI DI 2805 {1, 255}, // AX CX DX BX SP BP SI DI 2806 }, 2807 }, 2808 }, 2809 { 2810 name: "CMPB", 2811 argLen: 2, 2812 asm: x86.ACMPB, 2813 reg: regInfo{ 2814 inputs: []inputInfo{ 2815 {0, 255}, // AX CX DX BX SP BP SI DI 2816 {1, 255}, // AX CX DX BX SP BP SI DI 2817 }, 2818 }, 2819 }, 2820 { 2821 name: "CMPLconst", 2822 auxType: auxInt32, 2823 argLen: 1, 2824 asm: x86.ACMPL, 2825 reg: regInfo{ 2826 inputs: []inputInfo{ 2827 {0, 255}, // AX CX DX BX SP BP SI DI 2828 }, 2829 }, 2830 }, 2831 { 2832 name: "CMPWconst", 2833 auxType: auxInt16, 2834 argLen: 1, 2835 asm: x86.ACMPW, 2836 reg: regInfo{ 2837 inputs: []inputInfo{ 2838 {0, 255}, // AX CX DX BX SP BP SI DI 2839 }, 2840 }, 2841 }, 2842 { 2843 name: "CMPBconst", 2844 auxType: auxInt8, 2845 argLen: 1, 2846 asm: x86.ACMPB, 2847 reg: regInfo{ 2848 inputs: []inputInfo{ 2849 {0, 255}, // AX CX DX BX SP BP SI DI 2850 }, 2851 }, 2852 }, 2853 { 2854 name: "UCOMISS", 2855 argLen: 2, 2856 usesScratch: true, 2857 asm: x86.AUCOMISS, 2858 reg: regInfo{ 2859 inputs: []inputInfo{ 2860 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2861 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2862 }, 2863 }, 2864 }, 2865 { 2866 name: "UCOMISD", 2867 argLen: 2, 2868 usesScratch: true, 2869 asm: x86.AUCOMISD, 2870 reg: regInfo{ 2871 inputs: []inputInfo{ 2872 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2873 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2874 }, 2875 }, 2876 }, 2877 { 2878 name: "TESTL", 2879 argLen: 2, 2880 commutative: true, 2881 asm: x86.ATESTL, 2882 reg: regInfo{ 2883 inputs: []inputInfo{ 2884 {0, 255}, // AX CX DX BX SP BP SI DI 2885 {1, 255}, // AX CX DX BX SP BP SI DI 2886 }, 2887 }, 2888 }, 2889 { 2890 name: "TESTW", 2891 argLen: 2, 2892 commutative: true, 2893 asm: x86.ATESTW, 2894 reg: regInfo{ 2895 inputs: []inputInfo{ 2896 {0, 255}, // AX CX DX BX SP BP SI DI 2897 {1, 255}, // AX CX DX BX SP BP SI DI 2898 }, 2899 }, 2900 }, 2901 { 2902 name: "TESTB", 2903 argLen: 2, 2904 commutative: true, 2905 asm: x86.ATESTB, 2906 reg: regInfo{ 2907 inputs: []inputInfo{ 2908 {0, 255}, // AX CX DX BX SP BP SI DI 2909 {1, 255}, // AX CX DX BX SP BP SI DI 2910 }, 2911 }, 2912 }, 2913 { 2914 name: "TESTLconst", 2915 auxType: auxInt32, 2916 argLen: 1, 2917 asm: x86.ATESTL, 2918 reg: regInfo{ 2919 inputs: []inputInfo{ 2920 {0, 255}, // AX CX DX BX SP BP SI DI 2921 }, 2922 }, 2923 }, 2924 { 2925 name: "TESTWconst", 2926 auxType: auxInt16, 2927 argLen: 1, 2928 asm: x86.ATESTW, 2929 reg: regInfo{ 2930 inputs: []inputInfo{ 2931 {0, 255}, // AX CX DX BX SP BP SI DI 2932 }, 2933 }, 2934 }, 2935 { 2936 name: "TESTBconst", 2937 auxType: auxInt8, 2938 argLen: 1, 2939 asm: x86.ATESTB, 2940 reg: regInfo{ 2941 inputs: []inputInfo{ 2942 {0, 255}, // AX CX DX BX SP BP SI DI 2943 }, 2944 }, 2945 }, 2946 { 2947 name: "SHLL", 2948 argLen: 2, 2949 resultInArg0: true, 2950 clobberFlags: true, 2951 asm: x86.ASHLL, 2952 reg: regInfo{ 2953 inputs: []inputInfo{ 2954 {1, 2}, // CX 2955 {0, 239}, // AX CX DX BX BP SI DI 2956 }, 2957 outputs: []outputInfo{ 2958 {0, 239}, // AX CX DX BX BP SI DI 2959 }, 2960 }, 2961 }, 2962 { 2963 name: "SHLLconst", 2964 auxType: auxInt32, 2965 argLen: 1, 2966 resultInArg0: true, 2967 clobberFlags: true, 2968 asm: x86.ASHLL, 2969 reg: regInfo{ 2970 inputs: []inputInfo{ 2971 {0, 239}, // AX CX DX BX BP SI DI 2972 }, 2973 outputs: []outputInfo{ 2974 {0, 239}, // AX CX DX BX BP SI DI 2975 }, 2976 }, 2977 }, 2978 { 2979 name: "SHRL", 2980 argLen: 2, 2981 resultInArg0: true, 2982 clobberFlags: true, 2983 asm: x86.ASHRL, 2984 reg: regInfo{ 2985 inputs: []inputInfo{ 2986 {1, 2}, // CX 2987 {0, 239}, // AX CX DX BX BP SI DI 2988 }, 2989 outputs: []outputInfo{ 2990 {0, 239}, // AX CX DX BX BP SI DI 2991 }, 2992 }, 2993 }, 2994 { 2995 name: "SHRW", 2996 argLen: 2, 2997 resultInArg0: true, 2998 clobberFlags: true, 2999 asm: x86.ASHRW, 3000 reg: regInfo{ 3001 inputs: []inputInfo{ 3002 {1, 2}, // CX 3003 {0, 239}, // AX CX DX BX BP SI DI 3004 }, 3005 outputs: []outputInfo{ 3006 {0, 239}, // AX CX DX BX BP SI DI 3007 }, 3008 }, 3009 }, 3010 { 3011 name: "SHRB", 3012 argLen: 2, 3013 resultInArg0: true, 3014 clobberFlags: true, 3015 asm: x86.ASHRB, 3016 reg: regInfo{ 3017 inputs: []inputInfo{ 3018 {1, 2}, // CX 3019 {0, 239}, // AX CX DX BX BP SI DI 3020 }, 3021 outputs: []outputInfo{ 3022 {0, 239}, // AX CX DX BX BP SI DI 3023 }, 3024 }, 3025 }, 3026 { 3027 name: "SHRLconst", 3028 auxType: auxInt32, 3029 argLen: 1, 3030 resultInArg0: true, 3031 clobberFlags: true, 3032 asm: x86.ASHRL, 3033 reg: regInfo{ 3034 inputs: []inputInfo{ 3035 {0, 239}, // AX CX DX BX BP SI DI 3036 }, 3037 outputs: []outputInfo{ 3038 {0, 239}, // AX CX DX BX BP SI DI 3039 }, 3040 }, 3041 }, 3042 { 3043 name: "SHRWconst", 3044 auxType: auxInt16, 3045 argLen: 1, 3046 resultInArg0: true, 3047 clobberFlags: true, 3048 asm: x86.ASHRW, 3049 reg: regInfo{ 3050 inputs: []inputInfo{ 3051 {0, 239}, // AX CX DX BX BP SI DI 3052 }, 3053 outputs: []outputInfo{ 3054 {0, 239}, // AX CX DX BX BP SI DI 3055 }, 3056 }, 3057 }, 3058 { 3059 name: "SHRBconst", 3060 auxType: auxInt8, 3061 argLen: 1, 3062 resultInArg0: true, 3063 clobberFlags: true, 3064 asm: x86.ASHRB, 3065 reg: regInfo{ 3066 inputs: []inputInfo{ 3067 {0, 239}, // AX CX DX BX BP SI DI 3068 }, 3069 outputs: []outputInfo{ 3070 {0, 239}, // AX CX DX BX BP SI DI 3071 }, 3072 }, 3073 }, 3074 { 3075 name: "SARL", 3076 argLen: 2, 3077 resultInArg0: true, 3078 clobberFlags: true, 3079 asm: x86.ASARL, 3080 reg: regInfo{ 3081 inputs: []inputInfo{ 3082 {1, 2}, // CX 3083 {0, 239}, // AX CX DX BX BP SI DI 3084 }, 3085 outputs: []outputInfo{ 3086 {0, 239}, // AX CX DX BX BP SI DI 3087 }, 3088 }, 3089 }, 3090 { 3091 name: "SARW", 3092 argLen: 2, 3093 resultInArg0: true, 3094 clobberFlags: true, 3095 asm: x86.ASARW, 3096 reg: regInfo{ 3097 inputs: []inputInfo{ 3098 {1, 2}, // CX 3099 {0, 239}, // AX CX DX BX BP SI DI 3100 }, 3101 outputs: []outputInfo{ 3102 {0, 239}, // AX CX DX BX BP SI DI 3103 }, 3104 }, 3105 }, 3106 { 3107 name: "SARB", 3108 argLen: 2, 3109 resultInArg0: true, 3110 clobberFlags: true, 3111 asm: x86.ASARB, 3112 reg: regInfo{ 3113 inputs: []inputInfo{ 3114 {1, 2}, // CX 3115 {0, 239}, // AX CX DX BX BP SI DI 3116 }, 3117 outputs: []outputInfo{ 3118 {0, 239}, // AX CX DX BX BP SI DI 3119 }, 3120 }, 3121 }, 3122 { 3123 name: "SARLconst", 3124 auxType: auxInt32, 3125 argLen: 1, 3126 resultInArg0: true, 3127 clobberFlags: true, 3128 asm: x86.ASARL, 3129 reg: regInfo{ 3130 inputs: []inputInfo{ 3131 {0, 239}, // AX CX DX BX BP SI DI 3132 }, 3133 outputs: []outputInfo{ 3134 {0, 239}, // AX CX DX BX BP SI DI 3135 }, 3136 }, 3137 }, 3138 { 3139 name: "SARWconst", 3140 auxType: auxInt16, 3141 argLen: 1, 3142 resultInArg0: true, 3143 clobberFlags: true, 3144 asm: x86.ASARW, 3145 reg: regInfo{ 3146 inputs: []inputInfo{ 3147 {0, 239}, // AX CX DX BX BP SI DI 3148 }, 3149 outputs: []outputInfo{ 3150 {0, 239}, // AX CX DX BX BP SI DI 3151 }, 3152 }, 3153 }, 3154 { 3155 name: "SARBconst", 3156 auxType: auxInt8, 3157 argLen: 1, 3158 resultInArg0: true, 3159 clobberFlags: true, 3160 asm: x86.ASARB, 3161 reg: regInfo{ 3162 inputs: []inputInfo{ 3163 {0, 239}, // AX CX DX BX BP SI DI 3164 }, 3165 outputs: []outputInfo{ 3166 {0, 239}, // AX CX DX BX BP SI DI 3167 }, 3168 }, 3169 }, 3170 { 3171 name: "ROLLconst", 3172 auxType: auxInt32, 3173 argLen: 1, 3174 resultInArg0: true, 3175 clobberFlags: true, 3176 asm: x86.AROLL, 3177 reg: regInfo{ 3178 inputs: []inputInfo{ 3179 {0, 239}, // AX CX DX BX BP SI DI 3180 }, 3181 outputs: []outputInfo{ 3182 {0, 239}, // AX CX DX BX BP SI DI 3183 }, 3184 }, 3185 }, 3186 { 3187 name: "ROLWconst", 3188 auxType: auxInt16, 3189 argLen: 1, 3190 resultInArg0: true, 3191 clobberFlags: true, 3192 asm: x86.AROLW, 3193 reg: regInfo{ 3194 inputs: []inputInfo{ 3195 {0, 239}, // AX CX DX BX BP SI DI 3196 }, 3197 outputs: []outputInfo{ 3198 {0, 239}, // AX CX DX BX BP SI DI 3199 }, 3200 }, 3201 }, 3202 { 3203 name: "ROLBconst", 3204 auxType: auxInt8, 3205 argLen: 1, 3206 resultInArg0: true, 3207 clobberFlags: true, 3208 asm: x86.AROLB, 3209 reg: regInfo{ 3210 inputs: []inputInfo{ 3211 {0, 239}, // AX CX DX BX BP SI DI 3212 }, 3213 outputs: []outputInfo{ 3214 {0, 239}, // AX CX DX BX BP SI DI 3215 }, 3216 }, 3217 }, 3218 { 3219 name: "NEGL", 3220 argLen: 1, 3221 resultInArg0: true, 3222 clobberFlags: true, 3223 asm: x86.ANEGL, 3224 reg: regInfo{ 3225 inputs: []inputInfo{ 3226 {0, 239}, // AX CX DX BX BP SI DI 3227 }, 3228 outputs: []outputInfo{ 3229 {0, 239}, // AX CX DX BX BP SI DI 3230 }, 3231 }, 3232 }, 3233 { 3234 name: "NOTL", 3235 argLen: 1, 3236 resultInArg0: true, 3237 clobberFlags: true, 3238 asm: x86.ANOTL, 3239 reg: regInfo{ 3240 inputs: []inputInfo{ 3241 {0, 239}, // AX CX DX BX BP SI DI 3242 }, 3243 outputs: []outputInfo{ 3244 {0, 239}, // AX CX DX BX BP SI DI 3245 }, 3246 }, 3247 }, 3248 { 3249 name: "BSFL", 3250 argLen: 1, 3251 clobberFlags: true, 3252 asm: x86.ABSFL, 3253 reg: regInfo{ 3254 inputs: []inputInfo{ 3255 {0, 239}, // AX CX DX BX BP SI DI 3256 }, 3257 outputs: []outputInfo{ 3258 {0, 239}, // AX CX DX BX BP SI DI 3259 }, 3260 }, 3261 }, 3262 { 3263 name: "BSFW", 3264 argLen: 1, 3265 clobberFlags: true, 3266 asm: x86.ABSFW, 3267 reg: regInfo{ 3268 inputs: []inputInfo{ 3269 {0, 239}, // AX CX DX BX BP SI DI 3270 }, 3271 outputs: []outputInfo{ 3272 {0, 239}, // AX CX DX BX BP SI DI 3273 }, 3274 }, 3275 }, 3276 { 3277 name: "BSRL", 3278 argLen: 1, 3279 clobberFlags: true, 3280 asm: x86.ABSRL, 3281 reg: regInfo{ 3282 inputs: []inputInfo{ 3283 {0, 239}, // AX CX DX BX BP SI DI 3284 }, 3285 outputs: []outputInfo{ 3286 {0, 239}, // AX CX DX BX BP SI DI 3287 }, 3288 }, 3289 }, 3290 { 3291 name: "BSRW", 3292 argLen: 1, 3293 clobberFlags: true, 3294 asm: x86.ABSRW, 3295 reg: regInfo{ 3296 inputs: []inputInfo{ 3297 {0, 239}, // AX CX DX BX BP SI DI 3298 }, 3299 outputs: []outputInfo{ 3300 {0, 239}, // AX CX DX BX BP SI DI 3301 }, 3302 }, 3303 }, 3304 { 3305 name: "BSWAPL", 3306 argLen: 1, 3307 resultInArg0: true, 3308 clobberFlags: true, 3309 asm: x86.ABSWAPL, 3310 reg: regInfo{ 3311 inputs: []inputInfo{ 3312 {0, 239}, // AX CX DX BX BP SI DI 3313 }, 3314 outputs: []outputInfo{ 3315 {0, 239}, // AX CX DX BX BP SI DI 3316 }, 3317 }, 3318 }, 3319 { 3320 name: "SQRTSD", 3321 argLen: 1, 3322 asm: x86.ASQRTSD, 3323 reg: regInfo{ 3324 inputs: []inputInfo{ 3325 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3326 }, 3327 outputs: []outputInfo{ 3328 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3329 }, 3330 }, 3331 }, 3332 { 3333 name: "SBBLcarrymask", 3334 argLen: 1, 3335 asm: x86.ASBBL, 3336 reg: regInfo{ 3337 outputs: []outputInfo{ 3338 {0, 239}, // AX CX DX BX BP SI DI 3339 }, 3340 }, 3341 }, 3342 { 3343 name: "SETEQ", 3344 argLen: 1, 3345 asm: x86.ASETEQ, 3346 reg: regInfo{ 3347 outputs: []outputInfo{ 3348 {0, 239}, // AX CX DX BX BP SI DI 3349 }, 3350 }, 3351 }, 3352 { 3353 name: "SETNE", 3354 argLen: 1, 3355 asm: x86.ASETNE, 3356 reg: regInfo{ 3357 outputs: []outputInfo{ 3358 {0, 239}, // AX CX DX BX BP SI DI 3359 }, 3360 }, 3361 }, 3362 { 3363 name: "SETL", 3364 argLen: 1, 3365 asm: x86.ASETLT, 3366 reg: regInfo{ 3367 outputs: []outputInfo{ 3368 {0, 239}, // AX CX DX BX BP SI DI 3369 }, 3370 }, 3371 }, 3372 { 3373 name: "SETLE", 3374 argLen: 1, 3375 asm: x86.ASETLE, 3376 reg: regInfo{ 3377 outputs: []outputInfo{ 3378 {0, 239}, // AX CX DX BX BP SI DI 3379 }, 3380 }, 3381 }, 3382 { 3383 name: "SETG", 3384 argLen: 1, 3385 asm: x86.ASETGT, 3386 reg: regInfo{ 3387 outputs: []outputInfo{ 3388 {0, 239}, // AX CX DX BX BP SI DI 3389 }, 3390 }, 3391 }, 3392 { 3393 name: "SETGE", 3394 argLen: 1, 3395 asm: x86.ASETGE, 3396 reg: regInfo{ 3397 outputs: []outputInfo{ 3398 {0, 239}, // AX CX DX BX BP SI DI 3399 }, 3400 }, 3401 }, 3402 { 3403 name: "SETB", 3404 argLen: 1, 3405 asm: x86.ASETCS, 3406 reg: regInfo{ 3407 outputs: []outputInfo{ 3408 {0, 239}, // AX CX DX BX BP SI DI 3409 }, 3410 }, 3411 }, 3412 { 3413 name: "SETBE", 3414 argLen: 1, 3415 asm: x86.ASETLS, 3416 reg: regInfo{ 3417 outputs: []outputInfo{ 3418 {0, 239}, // AX CX DX BX BP SI DI 3419 }, 3420 }, 3421 }, 3422 { 3423 name: "SETA", 3424 argLen: 1, 3425 asm: x86.ASETHI, 3426 reg: regInfo{ 3427 outputs: []outputInfo{ 3428 {0, 239}, // AX CX DX BX BP SI DI 3429 }, 3430 }, 3431 }, 3432 { 3433 name: "SETAE", 3434 argLen: 1, 3435 asm: x86.ASETCC, 3436 reg: regInfo{ 3437 outputs: []outputInfo{ 3438 {0, 239}, // AX CX DX BX BP SI DI 3439 }, 3440 }, 3441 }, 3442 { 3443 name: "SETEQF", 3444 argLen: 1, 3445 clobberFlags: true, 3446 asm: x86.ASETEQ, 3447 reg: regInfo{ 3448 clobbers: 1, // AX 3449 outputs: []outputInfo{ 3450 {0, 238}, // CX DX BX BP SI DI 3451 }, 3452 }, 3453 }, 3454 { 3455 name: "SETNEF", 3456 argLen: 1, 3457 clobberFlags: true, 3458 asm: x86.ASETNE, 3459 reg: regInfo{ 3460 clobbers: 1, // AX 3461 outputs: []outputInfo{ 3462 {0, 238}, // CX DX BX BP SI DI 3463 }, 3464 }, 3465 }, 3466 { 3467 name: "SETORD", 3468 argLen: 1, 3469 asm: x86.ASETPC, 3470 reg: regInfo{ 3471 outputs: []outputInfo{ 3472 {0, 239}, // AX CX DX BX BP SI DI 3473 }, 3474 }, 3475 }, 3476 { 3477 name: "SETNAN", 3478 argLen: 1, 3479 asm: x86.ASETPS, 3480 reg: regInfo{ 3481 outputs: []outputInfo{ 3482 {0, 239}, // AX CX DX BX BP SI DI 3483 }, 3484 }, 3485 }, 3486 { 3487 name: "SETGF", 3488 argLen: 1, 3489 asm: x86.ASETHI, 3490 reg: regInfo{ 3491 outputs: []outputInfo{ 3492 {0, 239}, // AX CX DX BX BP SI DI 3493 }, 3494 }, 3495 }, 3496 { 3497 name: "SETGEF", 3498 argLen: 1, 3499 asm: x86.ASETCC, 3500 reg: regInfo{ 3501 outputs: []outputInfo{ 3502 {0, 239}, // AX CX DX BX BP SI DI 3503 }, 3504 }, 3505 }, 3506 { 3507 name: "MOVBLSX", 3508 argLen: 1, 3509 asm: x86.AMOVBLSX, 3510 reg: regInfo{ 3511 inputs: []inputInfo{ 3512 {0, 239}, // AX CX DX BX BP SI DI 3513 }, 3514 outputs: []outputInfo{ 3515 {0, 239}, // AX CX DX BX BP SI DI 3516 }, 3517 }, 3518 }, 3519 { 3520 name: "MOVBLZX", 3521 argLen: 1, 3522 asm: x86.AMOVBLZX, 3523 reg: regInfo{ 3524 inputs: []inputInfo{ 3525 {0, 239}, // AX CX DX BX BP SI DI 3526 }, 3527 outputs: []outputInfo{ 3528 {0, 239}, // AX CX DX BX BP SI DI 3529 }, 3530 }, 3531 }, 3532 { 3533 name: "MOVWLSX", 3534 argLen: 1, 3535 asm: x86.AMOVWLSX, 3536 reg: regInfo{ 3537 inputs: []inputInfo{ 3538 {0, 239}, // AX CX DX BX BP SI DI 3539 }, 3540 outputs: []outputInfo{ 3541 {0, 239}, // AX CX DX BX BP SI DI 3542 }, 3543 }, 3544 }, 3545 { 3546 name: "MOVWLZX", 3547 argLen: 1, 3548 asm: x86.AMOVWLZX, 3549 reg: regInfo{ 3550 inputs: []inputInfo{ 3551 {0, 239}, // AX CX DX BX BP SI DI 3552 }, 3553 outputs: []outputInfo{ 3554 {0, 239}, // AX CX DX BX BP SI DI 3555 }, 3556 }, 3557 }, 3558 { 3559 name: "MOVLconst", 3560 auxType: auxInt32, 3561 argLen: 0, 3562 rematerializeable: true, 3563 asm: x86.AMOVL, 3564 reg: regInfo{ 3565 outputs: []outputInfo{ 3566 {0, 239}, // AX CX DX BX BP SI DI 3567 }, 3568 }, 3569 }, 3570 { 3571 name: "CVTTSD2SL", 3572 argLen: 1, 3573 usesScratch: true, 3574 asm: x86.ACVTTSD2SL, 3575 reg: regInfo{ 3576 inputs: []inputInfo{ 3577 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3578 }, 3579 outputs: []outputInfo{ 3580 {0, 239}, // AX CX DX BX BP SI DI 3581 }, 3582 }, 3583 }, 3584 { 3585 name: "CVTTSS2SL", 3586 argLen: 1, 3587 usesScratch: true, 3588 asm: x86.ACVTTSS2SL, 3589 reg: regInfo{ 3590 inputs: []inputInfo{ 3591 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3592 }, 3593 outputs: []outputInfo{ 3594 {0, 239}, // AX CX DX BX BP SI DI 3595 }, 3596 }, 3597 }, 3598 { 3599 name: "CVTSL2SS", 3600 argLen: 1, 3601 usesScratch: true, 3602 asm: x86.ACVTSL2SS, 3603 reg: regInfo{ 3604 inputs: []inputInfo{ 3605 {0, 239}, // AX CX DX BX BP SI DI 3606 }, 3607 outputs: []outputInfo{ 3608 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3609 }, 3610 }, 3611 }, 3612 { 3613 name: "CVTSL2SD", 3614 argLen: 1, 3615 usesScratch: true, 3616 asm: x86.ACVTSL2SD, 3617 reg: regInfo{ 3618 inputs: []inputInfo{ 3619 {0, 239}, // AX CX DX BX BP SI DI 3620 }, 3621 outputs: []outputInfo{ 3622 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3623 }, 3624 }, 3625 }, 3626 { 3627 name: "CVTSD2SS", 3628 argLen: 1, 3629 usesScratch: true, 3630 asm: x86.ACVTSD2SS, 3631 reg: regInfo{ 3632 inputs: []inputInfo{ 3633 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3634 }, 3635 outputs: []outputInfo{ 3636 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3637 }, 3638 }, 3639 }, 3640 { 3641 name: "CVTSS2SD", 3642 argLen: 1, 3643 asm: x86.ACVTSS2SD, 3644 reg: regInfo{ 3645 inputs: []inputInfo{ 3646 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3647 }, 3648 outputs: []outputInfo{ 3649 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3650 }, 3651 }, 3652 }, 3653 { 3654 name: "PXOR", 3655 argLen: 2, 3656 commutative: true, 3657 resultInArg0: true, 3658 asm: x86.APXOR, 3659 reg: regInfo{ 3660 inputs: []inputInfo{ 3661 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3662 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3663 }, 3664 outputs: []outputInfo{ 3665 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3666 }, 3667 }, 3668 }, 3669 { 3670 name: "LEAL", 3671 auxType: auxSymOff, 3672 argLen: 1, 3673 rematerializeable: true, 3674 symEffect: SymAddr, 3675 reg: regInfo{ 3676 inputs: []inputInfo{ 3677 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3678 }, 3679 outputs: []outputInfo{ 3680 {0, 239}, // AX CX DX BX BP SI DI 3681 }, 3682 }, 3683 }, 3684 { 3685 name: "LEAL1", 3686 auxType: auxSymOff, 3687 argLen: 2, 3688 commutative: true, 3689 symEffect: SymAddr, 3690 reg: regInfo{ 3691 inputs: []inputInfo{ 3692 {1, 255}, // AX CX DX BX SP BP SI DI 3693 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3694 }, 3695 outputs: []outputInfo{ 3696 {0, 239}, // AX CX DX BX BP SI DI 3697 }, 3698 }, 3699 }, 3700 { 3701 name: "LEAL2", 3702 auxType: auxSymOff, 3703 argLen: 2, 3704 symEffect: SymAddr, 3705 reg: regInfo{ 3706 inputs: []inputInfo{ 3707 {1, 255}, // AX CX DX BX SP BP SI DI 3708 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3709 }, 3710 outputs: []outputInfo{ 3711 {0, 239}, // AX CX DX BX BP SI DI 3712 }, 3713 }, 3714 }, 3715 { 3716 name: "LEAL4", 3717 auxType: auxSymOff, 3718 argLen: 2, 3719 symEffect: SymAddr, 3720 reg: regInfo{ 3721 inputs: []inputInfo{ 3722 {1, 255}, // AX CX DX BX SP BP SI DI 3723 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3724 }, 3725 outputs: []outputInfo{ 3726 {0, 239}, // AX CX DX BX BP SI DI 3727 }, 3728 }, 3729 }, 3730 { 3731 name: "LEAL8", 3732 auxType: auxSymOff, 3733 argLen: 2, 3734 symEffect: SymAddr, 3735 reg: regInfo{ 3736 inputs: []inputInfo{ 3737 {1, 255}, // AX CX DX BX SP BP SI DI 3738 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3739 }, 3740 outputs: []outputInfo{ 3741 {0, 239}, // AX CX DX BX BP SI DI 3742 }, 3743 }, 3744 }, 3745 { 3746 name: "MOVBload", 3747 auxType: auxSymOff, 3748 argLen: 2, 3749 faultOnNilArg0: true, 3750 symEffect: SymRead, 3751 asm: x86.AMOVBLZX, 3752 reg: regInfo{ 3753 inputs: []inputInfo{ 3754 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3755 }, 3756 outputs: []outputInfo{ 3757 {0, 239}, // AX CX DX BX BP SI DI 3758 }, 3759 }, 3760 }, 3761 { 3762 name: "MOVBLSXload", 3763 auxType: auxSymOff, 3764 argLen: 2, 3765 faultOnNilArg0: true, 3766 symEffect: SymRead, 3767 asm: x86.AMOVBLSX, 3768 reg: regInfo{ 3769 inputs: []inputInfo{ 3770 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3771 }, 3772 outputs: []outputInfo{ 3773 {0, 239}, // AX CX DX BX BP SI DI 3774 }, 3775 }, 3776 }, 3777 { 3778 name: "MOVWload", 3779 auxType: auxSymOff, 3780 argLen: 2, 3781 faultOnNilArg0: true, 3782 symEffect: SymRead, 3783 asm: x86.AMOVWLZX, 3784 reg: regInfo{ 3785 inputs: []inputInfo{ 3786 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3787 }, 3788 outputs: []outputInfo{ 3789 {0, 239}, // AX CX DX BX BP SI DI 3790 }, 3791 }, 3792 }, 3793 { 3794 name: "MOVWLSXload", 3795 auxType: auxSymOff, 3796 argLen: 2, 3797 faultOnNilArg0: true, 3798 symEffect: SymRead, 3799 asm: x86.AMOVWLSX, 3800 reg: regInfo{ 3801 inputs: []inputInfo{ 3802 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3803 }, 3804 outputs: []outputInfo{ 3805 {0, 239}, // AX CX DX BX BP SI DI 3806 }, 3807 }, 3808 }, 3809 { 3810 name: "MOVLload", 3811 auxType: auxSymOff, 3812 argLen: 2, 3813 faultOnNilArg0: true, 3814 symEffect: SymRead, 3815 asm: x86.AMOVL, 3816 reg: regInfo{ 3817 inputs: []inputInfo{ 3818 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3819 }, 3820 outputs: []outputInfo{ 3821 {0, 239}, // AX CX DX BX BP SI DI 3822 }, 3823 }, 3824 }, 3825 { 3826 name: "MOVBstore", 3827 auxType: auxSymOff, 3828 argLen: 3, 3829 faultOnNilArg0: true, 3830 symEffect: SymWrite, 3831 asm: x86.AMOVB, 3832 reg: regInfo{ 3833 inputs: []inputInfo{ 3834 {1, 255}, // AX CX DX BX SP BP SI DI 3835 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3836 }, 3837 }, 3838 }, 3839 { 3840 name: "MOVWstore", 3841 auxType: auxSymOff, 3842 argLen: 3, 3843 faultOnNilArg0: true, 3844 symEffect: SymWrite, 3845 asm: x86.AMOVW, 3846 reg: regInfo{ 3847 inputs: []inputInfo{ 3848 {1, 255}, // AX CX DX BX SP BP SI DI 3849 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3850 }, 3851 }, 3852 }, 3853 { 3854 name: "MOVLstore", 3855 auxType: auxSymOff, 3856 argLen: 3, 3857 faultOnNilArg0: true, 3858 symEffect: SymWrite, 3859 asm: x86.AMOVL, 3860 reg: regInfo{ 3861 inputs: []inputInfo{ 3862 {1, 255}, // AX CX DX BX SP BP SI DI 3863 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3864 }, 3865 }, 3866 }, 3867 { 3868 name: "MOVBloadidx1", 3869 auxType: auxSymOff, 3870 argLen: 3, 3871 commutative: true, 3872 symEffect: SymRead, 3873 asm: x86.AMOVBLZX, 3874 reg: regInfo{ 3875 inputs: []inputInfo{ 3876 {1, 255}, // AX CX DX BX SP BP SI DI 3877 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3878 }, 3879 outputs: []outputInfo{ 3880 {0, 239}, // AX CX DX BX BP SI DI 3881 }, 3882 }, 3883 }, 3884 { 3885 name: "MOVWloadidx1", 3886 auxType: auxSymOff, 3887 argLen: 3, 3888 commutative: true, 3889 symEffect: SymRead, 3890 asm: x86.AMOVWLZX, 3891 reg: regInfo{ 3892 inputs: []inputInfo{ 3893 {1, 255}, // AX CX DX BX SP BP SI DI 3894 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3895 }, 3896 outputs: []outputInfo{ 3897 {0, 239}, // AX CX DX BX BP SI DI 3898 }, 3899 }, 3900 }, 3901 { 3902 name: "MOVWloadidx2", 3903 auxType: auxSymOff, 3904 argLen: 3, 3905 symEffect: SymRead, 3906 asm: x86.AMOVWLZX, 3907 reg: regInfo{ 3908 inputs: []inputInfo{ 3909 {1, 255}, // AX CX DX BX SP BP SI DI 3910 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3911 }, 3912 outputs: []outputInfo{ 3913 {0, 239}, // AX CX DX BX BP SI DI 3914 }, 3915 }, 3916 }, 3917 { 3918 name: "MOVLloadidx1", 3919 auxType: auxSymOff, 3920 argLen: 3, 3921 commutative: true, 3922 symEffect: SymRead, 3923 asm: x86.AMOVL, 3924 reg: regInfo{ 3925 inputs: []inputInfo{ 3926 {1, 255}, // AX CX DX BX SP BP SI DI 3927 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3928 }, 3929 outputs: []outputInfo{ 3930 {0, 239}, // AX CX DX BX BP SI DI 3931 }, 3932 }, 3933 }, 3934 { 3935 name: "MOVLloadidx4", 3936 auxType: auxSymOff, 3937 argLen: 3, 3938 symEffect: SymRead, 3939 asm: x86.AMOVL, 3940 reg: regInfo{ 3941 inputs: []inputInfo{ 3942 {1, 255}, // AX CX DX BX SP BP SI DI 3943 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3944 }, 3945 outputs: []outputInfo{ 3946 {0, 239}, // AX CX DX BX BP SI DI 3947 }, 3948 }, 3949 }, 3950 { 3951 name: "MOVBstoreidx1", 3952 auxType: auxSymOff, 3953 argLen: 4, 3954 commutative: true, 3955 symEffect: SymWrite, 3956 asm: x86.AMOVB, 3957 reg: regInfo{ 3958 inputs: []inputInfo{ 3959 {1, 255}, // AX CX DX BX SP BP SI DI 3960 {2, 255}, // AX CX DX BX SP BP SI DI 3961 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3962 }, 3963 }, 3964 }, 3965 { 3966 name: "MOVWstoreidx1", 3967 auxType: auxSymOff, 3968 argLen: 4, 3969 commutative: true, 3970 symEffect: SymWrite, 3971 asm: x86.AMOVW, 3972 reg: regInfo{ 3973 inputs: []inputInfo{ 3974 {1, 255}, // AX CX DX BX SP BP SI DI 3975 {2, 255}, // AX CX DX BX SP BP SI DI 3976 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3977 }, 3978 }, 3979 }, 3980 { 3981 name: "MOVWstoreidx2", 3982 auxType: auxSymOff, 3983 argLen: 4, 3984 symEffect: SymWrite, 3985 asm: x86.AMOVW, 3986 reg: regInfo{ 3987 inputs: []inputInfo{ 3988 {1, 255}, // AX CX DX BX SP BP SI DI 3989 {2, 255}, // AX CX DX BX SP BP SI DI 3990 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3991 }, 3992 }, 3993 }, 3994 { 3995 name: "MOVLstoreidx1", 3996 auxType: auxSymOff, 3997 argLen: 4, 3998 commutative: true, 3999 symEffect: SymWrite, 4000 asm: x86.AMOVL, 4001 reg: regInfo{ 4002 inputs: []inputInfo{ 4003 {1, 255}, // AX CX DX BX SP BP SI DI 4004 {2, 255}, // AX CX DX BX SP BP SI DI 4005 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4006 }, 4007 }, 4008 }, 4009 { 4010 name: "MOVLstoreidx4", 4011 auxType: auxSymOff, 4012 argLen: 4, 4013 symEffect: SymWrite, 4014 asm: x86.AMOVL, 4015 reg: regInfo{ 4016 inputs: []inputInfo{ 4017 {1, 255}, // AX CX DX BX SP BP SI DI 4018 {2, 255}, // AX CX DX BX SP BP SI DI 4019 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4020 }, 4021 }, 4022 }, 4023 { 4024 name: "MOVBstoreconst", 4025 auxType: auxSymValAndOff, 4026 argLen: 2, 4027 faultOnNilArg0: true, 4028 symEffect: SymWrite, 4029 asm: x86.AMOVB, 4030 reg: regInfo{ 4031 inputs: []inputInfo{ 4032 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4033 }, 4034 }, 4035 }, 4036 { 4037 name: "MOVWstoreconst", 4038 auxType: auxSymValAndOff, 4039 argLen: 2, 4040 faultOnNilArg0: true, 4041 symEffect: SymWrite, 4042 asm: x86.AMOVW, 4043 reg: regInfo{ 4044 inputs: []inputInfo{ 4045 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4046 }, 4047 }, 4048 }, 4049 { 4050 name: "MOVLstoreconst", 4051 auxType: auxSymValAndOff, 4052 argLen: 2, 4053 faultOnNilArg0: true, 4054 symEffect: SymWrite, 4055 asm: x86.AMOVL, 4056 reg: regInfo{ 4057 inputs: []inputInfo{ 4058 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4059 }, 4060 }, 4061 }, 4062 { 4063 name: "MOVBstoreconstidx1", 4064 auxType: auxSymValAndOff, 4065 argLen: 3, 4066 symEffect: SymWrite, 4067 asm: x86.AMOVB, 4068 reg: regInfo{ 4069 inputs: []inputInfo{ 4070 {1, 255}, // AX CX DX BX SP BP SI DI 4071 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4072 }, 4073 }, 4074 }, 4075 { 4076 name: "MOVWstoreconstidx1", 4077 auxType: auxSymValAndOff, 4078 argLen: 3, 4079 symEffect: SymWrite, 4080 asm: x86.AMOVW, 4081 reg: regInfo{ 4082 inputs: []inputInfo{ 4083 {1, 255}, // AX CX DX BX SP BP SI DI 4084 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4085 }, 4086 }, 4087 }, 4088 { 4089 name: "MOVWstoreconstidx2", 4090 auxType: auxSymValAndOff, 4091 argLen: 3, 4092 symEffect: SymWrite, 4093 asm: x86.AMOVW, 4094 reg: regInfo{ 4095 inputs: []inputInfo{ 4096 {1, 255}, // AX CX DX BX SP BP SI DI 4097 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4098 }, 4099 }, 4100 }, 4101 { 4102 name: "MOVLstoreconstidx1", 4103 auxType: auxSymValAndOff, 4104 argLen: 3, 4105 symEffect: SymWrite, 4106 asm: x86.AMOVL, 4107 reg: regInfo{ 4108 inputs: []inputInfo{ 4109 {1, 255}, // AX CX DX BX SP BP SI DI 4110 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4111 }, 4112 }, 4113 }, 4114 { 4115 name: "MOVLstoreconstidx4", 4116 auxType: auxSymValAndOff, 4117 argLen: 3, 4118 symEffect: SymWrite, 4119 asm: x86.AMOVL, 4120 reg: regInfo{ 4121 inputs: []inputInfo{ 4122 {1, 255}, // AX CX DX BX SP BP SI DI 4123 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4124 }, 4125 }, 4126 }, 4127 { 4128 name: "DUFFZERO", 4129 auxType: auxInt64, 4130 argLen: 3, 4131 faultOnNilArg0: true, 4132 reg: regInfo{ 4133 inputs: []inputInfo{ 4134 {0, 128}, // DI 4135 {1, 1}, // AX 4136 }, 4137 clobbers: 130, // CX DI 4138 }, 4139 }, 4140 { 4141 name: "REPSTOSL", 4142 argLen: 4, 4143 faultOnNilArg0: true, 4144 reg: regInfo{ 4145 inputs: []inputInfo{ 4146 {0, 128}, // DI 4147 {1, 2}, // CX 4148 {2, 1}, // AX 4149 }, 4150 clobbers: 130, // CX DI 4151 }, 4152 }, 4153 { 4154 name: "CALLstatic", 4155 auxType: auxSymOff, 4156 argLen: 1, 4157 clobberFlags: true, 4158 call: true, 4159 symEffect: SymNone, 4160 reg: regInfo{ 4161 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4162 }, 4163 }, 4164 { 4165 name: "CALLclosure", 4166 auxType: auxInt64, 4167 argLen: 3, 4168 clobberFlags: true, 4169 call: true, 4170 reg: regInfo{ 4171 inputs: []inputInfo{ 4172 {1, 4}, // DX 4173 {0, 255}, // AX CX DX BX SP BP SI DI 4174 }, 4175 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4176 }, 4177 }, 4178 { 4179 name: "CALLinter", 4180 auxType: auxInt64, 4181 argLen: 2, 4182 clobberFlags: true, 4183 call: true, 4184 reg: regInfo{ 4185 inputs: []inputInfo{ 4186 {0, 239}, // AX CX DX BX BP SI DI 4187 }, 4188 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4189 }, 4190 }, 4191 { 4192 name: "DUFFCOPY", 4193 auxType: auxInt64, 4194 argLen: 3, 4195 clobberFlags: true, 4196 faultOnNilArg0: true, 4197 faultOnNilArg1: true, 4198 reg: regInfo{ 4199 inputs: []inputInfo{ 4200 {0, 128}, // DI 4201 {1, 64}, // SI 4202 }, 4203 clobbers: 194, // CX SI DI 4204 }, 4205 }, 4206 { 4207 name: "REPMOVSL", 4208 argLen: 4, 4209 faultOnNilArg0: true, 4210 faultOnNilArg1: true, 4211 reg: regInfo{ 4212 inputs: []inputInfo{ 4213 {0, 128}, // DI 4214 {1, 64}, // SI 4215 {2, 2}, // CX 4216 }, 4217 clobbers: 194, // CX SI DI 4218 }, 4219 }, 4220 { 4221 name: "InvertFlags", 4222 argLen: 1, 4223 reg: regInfo{}, 4224 }, 4225 { 4226 name: "LoweredGetG", 4227 argLen: 1, 4228 reg: regInfo{ 4229 outputs: []outputInfo{ 4230 {0, 239}, // AX CX DX BX BP SI DI 4231 }, 4232 }, 4233 }, 4234 { 4235 name: "LoweredGetClosurePtr", 4236 argLen: 0, 4237 reg: regInfo{ 4238 outputs: []outputInfo{ 4239 {0, 4}, // DX 4240 }, 4241 }, 4242 }, 4243 { 4244 name: "LoweredNilCheck", 4245 argLen: 2, 4246 clobberFlags: true, 4247 nilCheck: true, 4248 faultOnNilArg0: true, 4249 reg: regInfo{ 4250 inputs: []inputInfo{ 4251 {0, 255}, // AX CX DX BX SP BP SI DI 4252 }, 4253 }, 4254 }, 4255 { 4256 name: "MOVLconvert", 4257 argLen: 2, 4258 asm: x86.AMOVL, 4259 reg: regInfo{ 4260 inputs: []inputInfo{ 4261 {0, 239}, // AX CX DX BX BP SI DI 4262 }, 4263 outputs: []outputInfo{ 4264 {0, 239}, // AX CX DX BX BP SI DI 4265 }, 4266 }, 4267 }, 4268 { 4269 name: "FlagEQ", 4270 argLen: 0, 4271 reg: regInfo{}, 4272 }, 4273 { 4274 name: "FlagLT_ULT", 4275 argLen: 0, 4276 reg: regInfo{}, 4277 }, 4278 { 4279 name: "FlagLT_UGT", 4280 argLen: 0, 4281 reg: regInfo{}, 4282 }, 4283 { 4284 name: "FlagGT_UGT", 4285 argLen: 0, 4286 reg: regInfo{}, 4287 }, 4288 { 4289 name: "FlagGT_ULT", 4290 argLen: 0, 4291 reg: regInfo{}, 4292 }, 4293 { 4294 name: "FCHS", 4295 argLen: 1, 4296 reg: regInfo{ 4297 inputs: []inputInfo{ 4298 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4299 }, 4300 outputs: []outputInfo{ 4301 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4302 }, 4303 }, 4304 }, 4305 { 4306 name: "MOVSSconst1", 4307 auxType: auxFloat32, 4308 argLen: 0, 4309 reg: regInfo{ 4310 outputs: []outputInfo{ 4311 {0, 239}, // AX CX DX BX BP SI DI 4312 }, 4313 }, 4314 }, 4315 { 4316 name: "MOVSDconst1", 4317 auxType: auxFloat64, 4318 argLen: 0, 4319 reg: regInfo{ 4320 outputs: []outputInfo{ 4321 {0, 239}, // AX CX DX BX BP SI DI 4322 }, 4323 }, 4324 }, 4325 { 4326 name: "MOVSSconst2", 4327 argLen: 1, 4328 asm: x86.AMOVSS, 4329 reg: regInfo{ 4330 inputs: []inputInfo{ 4331 {0, 239}, // AX CX DX BX BP SI DI 4332 }, 4333 outputs: []outputInfo{ 4334 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4335 }, 4336 }, 4337 }, 4338 { 4339 name: "MOVSDconst2", 4340 argLen: 1, 4341 asm: x86.AMOVSD, 4342 reg: regInfo{ 4343 inputs: []inputInfo{ 4344 {0, 239}, // AX CX DX BX BP SI DI 4345 }, 4346 outputs: []outputInfo{ 4347 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4348 }, 4349 }, 4350 }, 4351 4352 { 4353 name: "ADDSS", 4354 argLen: 2, 4355 commutative: true, 4356 resultInArg0: true, 4357 asm: x86.AADDSS, 4358 reg: regInfo{ 4359 inputs: []inputInfo{ 4360 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4361 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4362 }, 4363 outputs: []outputInfo{ 4364 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4365 }, 4366 }, 4367 }, 4368 { 4369 name: "ADDSD", 4370 argLen: 2, 4371 commutative: true, 4372 resultInArg0: true, 4373 asm: x86.AADDSD, 4374 reg: regInfo{ 4375 inputs: []inputInfo{ 4376 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4377 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4378 }, 4379 outputs: []outputInfo{ 4380 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4381 }, 4382 }, 4383 }, 4384 { 4385 name: "SUBSS", 4386 argLen: 2, 4387 resultInArg0: true, 4388 asm: x86.ASUBSS, 4389 reg: regInfo{ 4390 inputs: []inputInfo{ 4391 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4392 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4393 }, 4394 outputs: []outputInfo{ 4395 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4396 }, 4397 }, 4398 }, 4399 { 4400 name: "SUBSD", 4401 argLen: 2, 4402 resultInArg0: true, 4403 asm: x86.ASUBSD, 4404 reg: regInfo{ 4405 inputs: []inputInfo{ 4406 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4407 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4408 }, 4409 outputs: []outputInfo{ 4410 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4411 }, 4412 }, 4413 }, 4414 { 4415 name: "MULSS", 4416 argLen: 2, 4417 commutative: true, 4418 resultInArg0: true, 4419 asm: x86.AMULSS, 4420 reg: regInfo{ 4421 inputs: []inputInfo{ 4422 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4423 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4424 }, 4425 outputs: []outputInfo{ 4426 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4427 }, 4428 }, 4429 }, 4430 { 4431 name: "MULSD", 4432 argLen: 2, 4433 commutative: true, 4434 resultInArg0: true, 4435 asm: x86.AMULSD, 4436 reg: regInfo{ 4437 inputs: []inputInfo{ 4438 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4439 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4440 }, 4441 outputs: []outputInfo{ 4442 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4443 }, 4444 }, 4445 }, 4446 { 4447 name: "DIVSS", 4448 argLen: 2, 4449 resultInArg0: true, 4450 asm: x86.ADIVSS, 4451 reg: regInfo{ 4452 inputs: []inputInfo{ 4453 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4454 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4455 }, 4456 outputs: []outputInfo{ 4457 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4458 }, 4459 }, 4460 }, 4461 { 4462 name: "DIVSD", 4463 argLen: 2, 4464 resultInArg0: true, 4465 asm: x86.ADIVSD, 4466 reg: regInfo{ 4467 inputs: []inputInfo{ 4468 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4469 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4470 }, 4471 outputs: []outputInfo{ 4472 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4473 }, 4474 }, 4475 }, 4476 { 4477 name: "MOVSSload", 4478 auxType: auxSymOff, 4479 argLen: 2, 4480 faultOnNilArg0: true, 4481 symEffect: SymRead, 4482 asm: x86.AMOVSS, 4483 reg: regInfo{ 4484 inputs: []inputInfo{ 4485 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4486 }, 4487 outputs: []outputInfo{ 4488 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4489 }, 4490 }, 4491 }, 4492 { 4493 name: "MOVSDload", 4494 auxType: auxSymOff, 4495 argLen: 2, 4496 faultOnNilArg0: true, 4497 symEffect: SymRead, 4498 asm: x86.AMOVSD, 4499 reg: regInfo{ 4500 inputs: []inputInfo{ 4501 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4502 }, 4503 outputs: []outputInfo{ 4504 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4505 }, 4506 }, 4507 }, 4508 { 4509 name: "MOVSSconst", 4510 auxType: auxFloat32, 4511 argLen: 0, 4512 rematerializeable: true, 4513 asm: x86.AMOVSS, 4514 reg: regInfo{ 4515 outputs: []outputInfo{ 4516 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4517 }, 4518 }, 4519 }, 4520 { 4521 name: "MOVSDconst", 4522 auxType: auxFloat64, 4523 argLen: 0, 4524 rematerializeable: true, 4525 asm: x86.AMOVSD, 4526 reg: regInfo{ 4527 outputs: []outputInfo{ 4528 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4529 }, 4530 }, 4531 }, 4532 { 4533 name: "MOVSSloadidx1", 4534 auxType: auxSymOff, 4535 argLen: 3, 4536 symEffect: SymRead, 4537 asm: x86.AMOVSS, 4538 reg: regInfo{ 4539 inputs: []inputInfo{ 4540 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4541 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4542 }, 4543 outputs: []outputInfo{ 4544 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4545 }, 4546 }, 4547 }, 4548 { 4549 name: "MOVSSloadidx4", 4550 auxType: auxSymOff, 4551 argLen: 3, 4552 symEffect: SymRead, 4553 asm: x86.AMOVSS, 4554 reg: regInfo{ 4555 inputs: []inputInfo{ 4556 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4557 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4558 }, 4559 outputs: []outputInfo{ 4560 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4561 }, 4562 }, 4563 }, 4564 { 4565 name: "MOVSDloadidx1", 4566 auxType: auxSymOff, 4567 argLen: 3, 4568 symEffect: SymRead, 4569 asm: x86.AMOVSD, 4570 reg: regInfo{ 4571 inputs: []inputInfo{ 4572 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4573 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4574 }, 4575 outputs: []outputInfo{ 4576 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4577 }, 4578 }, 4579 }, 4580 { 4581 name: "MOVSDloadidx8", 4582 auxType: auxSymOff, 4583 argLen: 3, 4584 symEffect: SymRead, 4585 asm: x86.AMOVSD, 4586 reg: regInfo{ 4587 inputs: []inputInfo{ 4588 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4589 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4590 }, 4591 outputs: []outputInfo{ 4592 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4593 }, 4594 }, 4595 }, 4596 { 4597 name: "MOVSSstore", 4598 auxType: auxSymOff, 4599 argLen: 3, 4600 faultOnNilArg0: true, 4601 symEffect: SymWrite, 4602 asm: x86.AMOVSS, 4603 reg: regInfo{ 4604 inputs: []inputInfo{ 4605 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4606 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4607 }, 4608 }, 4609 }, 4610 { 4611 name: "MOVSDstore", 4612 auxType: auxSymOff, 4613 argLen: 3, 4614 faultOnNilArg0: true, 4615 symEffect: SymWrite, 4616 asm: x86.AMOVSD, 4617 reg: regInfo{ 4618 inputs: []inputInfo{ 4619 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4620 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4621 }, 4622 }, 4623 }, 4624 { 4625 name: "MOVSSstoreidx1", 4626 auxType: auxSymOff, 4627 argLen: 4, 4628 symEffect: SymWrite, 4629 asm: x86.AMOVSS, 4630 reg: regInfo{ 4631 inputs: []inputInfo{ 4632 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4633 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4634 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4635 }, 4636 }, 4637 }, 4638 { 4639 name: "MOVSSstoreidx4", 4640 auxType: auxSymOff, 4641 argLen: 4, 4642 symEffect: SymWrite, 4643 asm: x86.AMOVSS, 4644 reg: regInfo{ 4645 inputs: []inputInfo{ 4646 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4647 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4648 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4649 }, 4650 }, 4651 }, 4652 { 4653 name: "MOVSDstoreidx1", 4654 auxType: auxSymOff, 4655 argLen: 4, 4656 symEffect: SymWrite, 4657 asm: x86.AMOVSD, 4658 reg: regInfo{ 4659 inputs: []inputInfo{ 4660 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4661 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4662 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4663 }, 4664 }, 4665 }, 4666 { 4667 name: "MOVSDstoreidx8", 4668 auxType: auxSymOff, 4669 argLen: 4, 4670 symEffect: SymWrite, 4671 asm: x86.AMOVSD, 4672 reg: regInfo{ 4673 inputs: []inputInfo{ 4674 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4675 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4676 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4677 }, 4678 }, 4679 }, 4680 { 4681 name: "ADDSDmem", 4682 auxType: auxSymOff, 4683 argLen: 3, 4684 resultInArg0: true, 4685 faultOnNilArg1: true, 4686 symEffect: SymRead, 4687 asm: x86.AADDSD, 4688 reg: regInfo{ 4689 inputs: []inputInfo{ 4690 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4691 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4692 }, 4693 outputs: []outputInfo{ 4694 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4695 }, 4696 }, 4697 }, 4698 { 4699 name: "ADDSSmem", 4700 auxType: auxSymOff, 4701 argLen: 3, 4702 resultInArg0: true, 4703 faultOnNilArg1: true, 4704 symEffect: SymRead, 4705 asm: x86.AADDSS, 4706 reg: regInfo{ 4707 inputs: []inputInfo{ 4708 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4709 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4710 }, 4711 outputs: []outputInfo{ 4712 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4713 }, 4714 }, 4715 }, 4716 { 4717 name: "SUBSSmem", 4718 auxType: auxSymOff, 4719 argLen: 3, 4720 resultInArg0: true, 4721 faultOnNilArg1: true, 4722 symEffect: SymRead, 4723 asm: x86.ASUBSS, 4724 reg: regInfo{ 4725 inputs: []inputInfo{ 4726 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4727 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4728 }, 4729 outputs: []outputInfo{ 4730 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4731 }, 4732 }, 4733 }, 4734 { 4735 name: "SUBSDmem", 4736 auxType: auxSymOff, 4737 argLen: 3, 4738 resultInArg0: true, 4739 faultOnNilArg1: true, 4740 symEffect: SymRead, 4741 asm: x86.ASUBSD, 4742 reg: regInfo{ 4743 inputs: []inputInfo{ 4744 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4745 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4746 }, 4747 outputs: []outputInfo{ 4748 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4749 }, 4750 }, 4751 }, 4752 { 4753 name: "MULSSmem", 4754 auxType: auxSymOff, 4755 argLen: 3, 4756 resultInArg0: true, 4757 faultOnNilArg1: true, 4758 symEffect: SymRead, 4759 asm: x86.AMULSS, 4760 reg: regInfo{ 4761 inputs: []inputInfo{ 4762 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4763 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4764 }, 4765 outputs: []outputInfo{ 4766 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4767 }, 4768 }, 4769 }, 4770 { 4771 name: "MULSDmem", 4772 auxType: auxSymOff, 4773 argLen: 3, 4774 resultInArg0: true, 4775 faultOnNilArg1: true, 4776 symEffect: SymRead, 4777 asm: x86.AMULSD, 4778 reg: regInfo{ 4779 inputs: []inputInfo{ 4780 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4781 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4782 }, 4783 outputs: []outputInfo{ 4784 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4785 }, 4786 }, 4787 }, 4788 { 4789 name: "ADDQ", 4790 argLen: 2, 4791 commutative: true, 4792 clobberFlags: true, 4793 asm: x86.AADDQ, 4794 reg: regInfo{ 4795 inputs: []inputInfo{ 4796 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4797 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4798 }, 4799 outputs: []outputInfo{ 4800 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4801 }, 4802 }, 4803 }, 4804 { 4805 name: "ADDL", 4806 argLen: 2, 4807 commutative: true, 4808 clobberFlags: true, 4809 asm: x86.AADDL, 4810 reg: regInfo{ 4811 inputs: []inputInfo{ 4812 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4813 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4814 }, 4815 outputs: []outputInfo{ 4816 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4817 }, 4818 }, 4819 }, 4820 { 4821 name: "ADDQconst", 4822 auxType: auxInt64, 4823 argLen: 1, 4824 clobberFlags: true, 4825 asm: x86.AADDQ, 4826 reg: regInfo{ 4827 inputs: []inputInfo{ 4828 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4829 }, 4830 outputs: []outputInfo{ 4831 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4832 }, 4833 }, 4834 }, 4835 { 4836 name: "ADDLconst", 4837 auxType: auxInt32, 4838 argLen: 1, 4839 clobberFlags: true, 4840 asm: x86.AADDL, 4841 reg: regInfo{ 4842 inputs: []inputInfo{ 4843 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4844 }, 4845 outputs: []outputInfo{ 4846 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4847 }, 4848 }, 4849 }, 4850 { 4851 name: "SUBQ", 4852 argLen: 2, 4853 resultInArg0: true, 4854 clobberFlags: true, 4855 asm: x86.ASUBQ, 4856 reg: regInfo{ 4857 inputs: []inputInfo{ 4858 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4859 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4860 }, 4861 outputs: []outputInfo{ 4862 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4863 }, 4864 }, 4865 }, 4866 { 4867 name: "SUBL", 4868 argLen: 2, 4869 resultInArg0: true, 4870 clobberFlags: true, 4871 asm: x86.ASUBL, 4872 reg: regInfo{ 4873 inputs: []inputInfo{ 4874 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4875 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4876 }, 4877 outputs: []outputInfo{ 4878 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4879 }, 4880 }, 4881 }, 4882 { 4883 name: "SUBQconst", 4884 auxType: auxInt64, 4885 argLen: 1, 4886 resultInArg0: true, 4887 clobberFlags: true, 4888 asm: x86.ASUBQ, 4889 reg: regInfo{ 4890 inputs: []inputInfo{ 4891 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4892 }, 4893 outputs: []outputInfo{ 4894 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4895 }, 4896 }, 4897 }, 4898 { 4899 name: "SUBLconst", 4900 auxType: auxInt32, 4901 argLen: 1, 4902 resultInArg0: true, 4903 clobberFlags: true, 4904 asm: x86.ASUBL, 4905 reg: regInfo{ 4906 inputs: []inputInfo{ 4907 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4908 }, 4909 outputs: []outputInfo{ 4910 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4911 }, 4912 }, 4913 }, 4914 { 4915 name: "MULQ", 4916 argLen: 2, 4917 commutative: true, 4918 resultInArg0: true, 4919 clobberFlags: true, 4920 asm: x86.AIMULQ, 4921 reg: regInfo{ 4922 inputs: []inputInfo{ 4923 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4924 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4925 }, 4926 outputs: []outputInfo{ 4927 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4928 }, 4929 }, 4930 }, 4931 { 4932 name: "MULL", 4933 argLen: 2, 4934 commutative: true, 4935 resultInArg0: true, 4936 clobberFlags: true, 4937 asm: x86.AIMULL, 4938 reg: regInfo{ 4939 inputs: []inputInfo{ 4940 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4941 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4942 }, 4943 outputs: []outputInfo{ 4944 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4945 }, 4946 }, 4947 }, 4948 { 4949 name: "MULQconst", 4950 auxType: auxInt64, 4951 argLen: 1, 4952 resultInArg0: true, 4953 clobberFlags: true, 4954 asm: x86.AIMULQ, 4955 reg: regInfo{ 4956 inputs: []inputInfo{ 4957 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4958 }, 4959 outputs: []outputInfo{ 4960 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4961 }, 4962 }, 4963 }, 4964 { 4965 name: "MULLconst", 4966 auxType: auxInt32, 4967 argLen: 1, 4968 resultInArg0: true, 4969 clobberFlags: true, 4970 asm: x86.AIMULL, 4971 reg: regInfo{ 4972 inputs: []inputInfo{ 4973 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4974 }, 4975 outputs: []outputInfo{ 4976 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4977 }, 4978 }, 4979 }, 4980 { 4981 name: "HMULQ", 4982 argLen: 2, 4983 commutative: true, 4984 clobberFlags: true, 4985 asm: x86.AIMULQ, 4986 reg: regInfo{ 4987 inputs: []inputInfo{ 4988 {0, 1}, // AX 4989 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4990 }, 4991 clobbers: 1, // AX 4992 outputs: []outputInfo{ 4993 {0, 4}, // DX 4994 }, 4995 }, 4996 }, 4997 { 4998 name: "HMULL", 4999 argLen: 2, 5000 commutative: true, 5001 clobberFlags: true, 5002 asm: x86.AIMULL, 5003 reg: regInfo{ 5004 inputs: []inputInfo{ 5005 {0, 1}, // AX 5006 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5007 }, 5008 clobbers: 1, // AX 5009 outputs: []outputInfo{ 5010 {0, 4}, // DX 5011 }, 5012 }, 5013 }, 5014 { 5015 name: "HMULQU", 5016 argLen: 2, 5017 commutative: true, 5018 clobberFlags: true, 5019 asm: x86.AMULQ, 5020 reg: regInfo{ 5021 inputs: []inputInfo{ 5022 {0, 1}, // AX 5023 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5024 }, 5025 clobbers: 1, // AX 5026 outputs: []outputInfo{ 5027 {0, 4}, // DX 5028 }, 5029 }, 5030 }, 5031 { 5032 name: "HMULLU", 5033 argLen: 2, 5034 commutative: true, 5035 clobberFlags: true, 5036 asm: x86.AMULL, 5037 reg: regInfo{ 5038 inputs: []inputInfo{ 5039 {0, 1}, // AX 5040 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5041 }, 5042 clobbers: 1, // AX 5043 outputs: []outputInfo{ 5044 {0, 4}, // DX 5045 }, 5046 }, 5047 }, 5048 { 5049 name: "AVGQU", 5050 argLen: 2, 5051 commutative: true, 5052 resultInArg0: true, 5053 clobberFlags: true, 5054 reg: regInfo{ 5055 inputs: []inputInfo{ 5056 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5057 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5058 }, 5059 outputs: []outputInfo{ 5060 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5061 }, 5062 }, 5063 }, 5064 { 5065 name: "DIVQ", 5066 argLen: 2, 5067 clobberFlags: true, 5068 asm: x86.AIDIVQ, 5069 reg: regInfo{ 5070 inputs: []inputInfo{ 5071 {0, 1}, // AX 5072 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5073 }, 5074 outputs: []outputInfo{ 5075 {0, 1}, // AX 5076 {1, 4}, // DX 5077 }, 5078 }, 5079 }, 5080 { 5081 name: "DIVL", 5082 argLen: 2, 5083 clobberFlags: true, 5084 asm: x86.AIDIVL, 5085 reg: regInfo{ 5086 inputs: []inputInfo{ 5087 {0, 1}, // AX 5088 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5089 }, 5090 outputs: []outputInfo{ 5091 {0, 1}, // AX 5092 {1, 4}, // DX 5093 }, 5094 }, 5095 }, 5096 { 5097 name: "DIVW", 5098 argLen: 2, 5099 clobberFlags: true, 5100 asm: x86.AIDIVW, 5101 reg: regInfo{ 5102 inputs: []inputInfo{ 5103 {0, 1}, // AX 5104 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5105 }, 5106 outputs: []outputInfo{ 5107 {0, 1}, // AX 5108 {1, 4}, // DX 5109 }, 5110 }, 5111 }, 5112 { 5113 name: "DIVQU", 5114 argLen: 2, 5115 clobberFlags: true, 5116 asm: x86.ADIVQ, 5117 reg: regInfo{ 5118 inputs: []inputInfo{ 5119 {0, 1}, // AX 5120 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5121 }, 5122 outputs: []outputInfo{ 5123 {0, 1}, // AX 5124 {1, 4}, // DX 5125 }, 5126 }, 5127 }, 5128 { 5129 name: "DIVLU", 5130 argLen: 2, 5131 clobberFlags: true, 5132 asm: x86.ADIVL, 5133 reg: regInfo{ 5134 inputs: []inputInfo{ 5135 {0, 1}, // AX 5136 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5137 }, 5138 outputs: []outputInfo{ 5139 {0, 1}, // AX 5140 {1, 4}, // DX 5141 }, 5142 }, 5143 }, 5144 { 5145 name: "DIVWU", 5146 argLen: 2, 5147 clobberFlags: true, 5148 asm: x86.ADIVW, 5149 reg: regInfo{ 5150 inputs: []inputInfo{ 5151 {0, 1}, // AX 5152 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5153 }, 5154 outputs: []outputInfo{ 5155 {0, 1}, // AX 5156 {1, 4}, // DX 5157 }, 5158 }, 5159 }, 5160 { 5161 name: "MULQU2", 5162 argLen: 2, 5163 commutative: true, 5164 clobberFlags: true, 5165 asm: x86.AMULQ, 5166 reg: regInfo{ 5167 inputs: []inputInfo{ 5168 {0, 1}, // AX 5169 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5170 }, 5171 outputs: []outputInfo{ 5172 {0, 4}, // DX 5173 {1, 1}, // AX 5174 }, 5175 }, 5176 }, 5177 { 5178 name: "DIVQU2", 5179 argLen: 3, 5180 clobberFlags: true, 5181 asm: x86.ADIVQ, 5182 reg: regInfo{ 5183 inputs: []inputInfo{ 5184 {0, 4}, // DX 5185 {1, 1}, // AX 5186 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5187 }, 5188 outputs: []outputInfo{ 5189 {0, 1}, // AX 5190 {1, 4}, // DX 5191 }, 5192 }, 5193 }, 5194 { 5195 name: "ANDQ", 5196 argLen: 2, 5197 commutative: true, 5198 resultInArg0: true, 5199 clobberFlags: true, 5200 asm: x86.AANDQ, 5201 reg: regInfo{ 5202 inputs: []inputInfo{ 5203 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5204 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5205 }, 5206 outputs: []outputInfo{ 5207 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5208 }, 5209 }, 5210 }, 5211 { 5212 name: "ANDL", 5213 argLen: 2, 5214 commutative: true, 5215 resultInArg0: true, 5216 clobberFlags: true, 5217 asm: x86.AANDL, 5218 reg: regInfo{ 5219 inputs: []inputInfo{ 5220 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5221 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5222 }, 5223 outputs: []outputInfo{ 5224 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5225 }, 5226 }, 5227 }, 5228 { 5229 name: "ANDQconst", 5230 auxType: auxInt64, 5231 argLen: 1, 5232 resultInArg0: true, 5233 clobberFlags: true, 5234 asm: x86.AANDQ, 5235 reg: regInfo{ 5236 inputs: []inputInfo{ 5237 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5238 }, 5239 outputs: []outputInfo{ 5240 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5241 }, 5242 }, 5243 }, 5244 { 5245 name: "ANDLconst", 5246 auxType: auxInt32, 5247 argLen: 1, 5248 resultInArg0: true, 5249 clobberFlags: true, 5250 asm: x86.AANDL, 5251 reg: regInfo{ 5252 inputs: []inputInfo{ 5253 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5254 }, 5255 outputs: []outputInfo{ 5256 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5257 }, 5258 }, 5259 }, 5260 { 5261 name: "ORQ", 5262 argLen: 2, 5263 commutative: true, 5264 resultInArg0: true, 5265 clobberFlags: true, 5266 asm: x86.AORQ, 5267 reg: regInfo{ 5268 inputs: []inputInfo{ 5269 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5270 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5271 }, 5272 outputs: []outputInfo{ 5273 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5274 }, 5275 }, 5276 }, 5277 { 5278 name: "ORL", 5279 argLen: 2, 5280 commutative: true, 5281 resultInArg0: true, 5282 clobberFlags: true, 5283 asm: x86.AORL, 5284 reg: regInfo{ 5285 inputs: []inputInfo{ 5286 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5287 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5288 }, 5289 outputs: []outputInfo{ 5290 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5291 }, 5292 }, 5293 }, 5294 { 5295 name: "ORQconst", 5296 auxType: auxInt64, 5297 argLen: 1, 5298 resultInArg0: true, 5299 clobberFlags: true, 5300 asm: x86.AORQ, 5301 reg: regInfo{ 5302 inputs: []inputInfo{ 5303 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5304 }, 5305 outputs: []outputInfo{ 5306 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5307 }, 5308 }, 5309 }, 5310 { 5311 name: "ORLconst", 5312 auxType: auxInt32, 5313 argLen: 1, 5314 resultInArg0: true, 5315 clobberFlags: true, 5316 asm: x86.AORL, 5317 reg: regInfo{ 5318 inputs: []inputInfo{ 5319 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5320 }, 5321 outputs: []outputInfo{ 5322 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5323 }, 5324 }, 5325 }, 5326 { 5327 name: "XORQ", 5328 argLen: 2, 5329 commutative: true, 5330 resultInArg0: true, 5331 clobberFlags: true, 5332 asm: x86.AXORQ, 5333 reg: regInfo{ 5334 inputs: []inputInfo{ 5335 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5336 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5337 }, 5338 outputs: []outputInfo{ 5339 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5340 }, 5341 }, 5342 }, 5343 { 5344 name: "XORL", 5345 argLen: 2, 5346 commutative: true, 5347 resultInArg0: true, 5348 clobberFlags: true, 5349 asm: x86.AXORL, 5350 reg: regInfo{ 5351 inputs: []inputInfo{ 5352 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5353 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5354 }, 5355 outputs: []outputInfo{ 5356 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5357 }, 5358 }, 5359 }, 5360 { 5361 name: "XORQconst", 5362 auxType: auxInt64, 5363 argLen: 1, 5364 resultInArg0: true, 5365 clobberFlags: true, 5366 asm: x86.AXORQ, 5367 reg: regInfo{ 5368 inputs: []inputInfo{ 5369 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5370 }, 5371 outputs: []outputInfo{ 5372 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5373 }, 5374 }, 5375 }, 5376 { 5377 name: "XORLconst", 5378 auxType: auxInt32, 5379 argLen: 1, 5380 resultInArg0: true, 5381 clobberFlags: true, 5382 asm: x86.AXORL, 5383 reg: regInfo{ 5384 inputs: []inputInfo{ 5385 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5386 }, 5387 outputs: []outputInfo{ 5388 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5389 }, 5390 }, 5391 }, 5392 { 5393 name: "CMPQ", 5394 argLen: 2, 5395 asm: x86.ACMPQ, 5396 reg: regInfo{ 5397 inputs: []inputInfo{ 5398 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5399 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5400 }, 5401 }, 5402 }, 5403 { 5404 name: "CMPL", 5405 argLen: 2, 5406 asm: x86.ACMPL, 5407 reg: regInfo{ 5408 inputs: []inputInfo{ 5409 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5410 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5411 }, 5412 }, 5413 }, 5414 { 5415 name: "CMPW", 5416 argLen: 2, 5417 asm: x86.ACMPW, 5418 reg: regInfo{ 5419 inputs: []inputInfo{ 5420 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5421 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5422 }, 5423 }, 5424 }, 5425 { 5426 name: "CMPB", 5427 argLen: 2, 5428 asm: x86.ACMPB, 5429 reg: regInfo{ 5430 inputs: []inputInfo{ 5431 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5432 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5433 }, 5434 }, 5435 }, 5436 { 5437 name: "CMPQconst", 5438 auxType: auxInt64, 5439 argLen: 1, 5440 asm: x86.ACMPQ, 5441 reg: regInfo{ 5442 inputs: []inputInfo{ 5443 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5444 }, 5445 }, 5446 }, 5447 { 5448 name: "CMPLconst", 5449 auxType: auxInt32, 5450 argLen: 1, 5451 asm: x86.ACMPL, 5452 reg: regInfo{ 5453 inputs: []inputInfo{ 5454 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5455 }, 5456 }, 5457 }, 5458 { 5459 name: "CMPWconst", 5460 auxType: auxInt16, 5461 argLen: 1, 5462 asm: x86.ACMPW, 5463 reg: regInfo{ 5464 inputs: []inputInfo{ 5465 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5466 }, 5467 }, 5468 }, 5469 { 5470 name: "CMPBconst", 5471 auxType: auxInt8, 5472 argLen: 1, 5473 asm: x86.ACMPB, 5474 reg: regInfo{ 5475 inputs: []inputInfo{ 5476 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5477 }, 5478 }, 5479 }, 5480 { 5481 name: "UCOMISS", 5482 argLen: 2, 5483 asm: x86.AUCOMISS, 5484 reg: regInfo{ 5485 inputs: []inputInfo{ 5486 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5487 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5488 }, 5489 }, 5490 }, 5491 { 5492 name: "UCOMISD", 5493 argLen: 2, 5494 asm: x86.AUCOMISD, 5495 reg: regInfo{ 5496 inputs: []inputInfo{ 5497 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5498 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5499 }, 5500 }, 5501 }, 5502 { 5503 name: "BTL", 5504 argLen: 2, 5505 asm: x86.ABTL, 5506 reg: regInfo{ 5507 inputs: []inputInfo{ 5508 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5509 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5510 }, 5511 }, 5512 }, 5513 { 5514 name: "BTQ", 5515 argLen: 2, 5516 asm: x86.ABTQ, 5517 reg: regInfo{ 5518 inputs: []inputInfo{ 5519 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5520 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5521 }, 5522 }, 5523 }, 5524 { 5525 name: "BTLconst", 5526 auxType: auxInt8, 5527 argLen: 1, 5528 asm: x86.ABTL, 5529 reg: regInfo{ 5530 inputs: []inputInfo{ 5531 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5532 }, 5533 }, 5534 }, 5535 { 5536 name: "BTQconst", 5537 auxType: auxInt8, 5538 argLen: 1, 5539 asm: x86.ABTQ, 5540 reg: regInfo{ 5541 inputs: []inputInfo{ 5542 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5543 }, 5544 }, 5545 }, 5546 { 5547 name: "TESTQ", 5548 argLen: 2, 5549 commutative: true, 5550 asm: x86.ATESTQ, 5551 reg: regInfo{ 5552 inputs: []inputInfo{ 5553 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5554 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5555 }, 5556 }, 5557 }, 5558 { 5559 name: "TESTL", 5560 argLen: 2, 5561 commutative: true, 5562 asm: x86.ATESTL, 5563 reg: regInfo{ 5564 inputs: []inputInfo{ 5565 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5566 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5567 }, 5568 }, 5569 }, 5570 { 5571 name: "TESTW", 5572 argLen: 2, 5573 commutative: true, 5574 asm: x86.ATESTW, 5575 reg: regInfo{ 5576 inputs: []inputInfo{ 5577 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5578 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5579 }, 5580 }, 5581 }, 5582 { 5583 name: "TESTB", 5584 argLen: 2, 5585 commutative: true, 5586 asm: x86.ATESTB, 5587 reg: regInfo{ 5588 inputs: []inputInfo{ 5589 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5590 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5591 }, 5592 }, 5593 }, 5594 { 5595 name: "TESTQconst", 5596 auxType: auxInt64, 5597 argLen: 1, 5598 asm: x86.ATESTQ, 5599 reg: regInfo{ 5600 inputs: []inputInfo{ 5601 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5602 }, 5603 }, 5604 }, 5605 { 5606 name: "TESTLconst", 5607 auxType: auxInt32, 5608 argLen: 1, 5609 asm: x86.ATESTL, 5610 reg: regInfo{ 5611 inputs: []inputInfo{ 5612 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5613 }, 5614 }, 5615 }, 5616 { 5617 name: "TESTWconst", 5618 auxType: auxInt16, 5619 argLen: 1, 5620 asm: x86.ATESTW, 5621 reg: regInfo{ 5622 inputs: []inputInfo{ 5623 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5624 }, 5625 }, 5626 }, 5627 { 5628 name: "TESTBconst", 5629 auxType: auxInt8, 5630 argLen: 1, 5631 asm: x86.ATESTB, 5632 reg: regInfo{ 5633 inputs: []inputInfo{ 5634 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5635 }, 5636 }, 5637 }, 5638 { 5639 name: "SHLQ", 5640 argLen: 2, 5641 resultInArg0: true, 5642 clobberFlags: true, 5643 asm: x86.ASHLQ, 5644 reg: regInfo{ 5645 inputs: []inputInfo{ 5646 {1, 2}, // CX 5647 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5648 }, 5649 outputs: []outputInfo{ 5650 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5651 }, 5652 }, 5653 }, 5654 { 5655 name: "SHLL", 5656 argLen: 2, 5657 resultInArg0: true, 5658 clobberFlags: true, 5659 asm: x86.ASHLL, 5660 reg: regInfo{ 5661 inputs: []inputInfo{ 5662 {1, 2}, // CX 5663 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5664 }, 5665 outputs: []outputInfo{ 5666 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5667 }, 5668 }, 5669 }, 5670 { 5671 name: "SHLQconst", 5672 auxType: auxInt8, 5673 argLen: 1, 5674 resultInArg0: true, 5675 clobberFlags: true, 5676 asm: x86.ASHLQ, 5677 reg: regInfo{ 5678 inputs: []inputInfo{ 5679 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5680 }, 5681 outputs: []outputInfo{ 5682 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5683 }, 5684 }, 5685 }, 5686 { 5687 name: "SHLLconst", 5688 auxType: auxInt8, 5689 argLen: 1, 5690 resultInArg0: true, 5691 clobberFlags: true, 5692 asm: x86.ASHLL, 5693 reg: regInfo{ 5694 inputs: []inputInfo{ 5695 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5696 }, 5697 outputs: []outputInfo{ 5698 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5699 }, 5700 }, 5701 }, 5702 { 5703 name: "SHRQ", 5704 argLen: 2, 5705 resultInArg0: true, 5706 clobberFlags: true, 5707 asm: x86.ASHRQ, 5708 reg: regInfo{ 5709 inputs: []inputInfo{ 5710 {1, 2}, // CX 5711 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5712 }, 5713 outputs: []outputInfo{ 5714 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5715 }, 5716 }, 5717 }, 5718 { 5719 name: "SHRL", 5720 argLen: 2, 5721 resultInArg0: true, 5722 clobberFlags: true, 5723 asm: x86.ASHRL, 5724 reg: regInfo{ 5725 inputs: []inputInfo{ 5726 {1, 2}, // CX 5727 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5728 }, 5729 outputs: []outputInfo{ 5730 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5731 }, 5732 }, 5733 }, 5734 { 5735 name: "SHRW", 5736 argLen: 2, 5737 resultInArg0: true, 5738 clobberFlags: true, 5739 asm: x86.ASHRW, 5740 reg: regInfo{ 5741 inputs: []inputInfo{ 5742 {1, 2}, // CX 5743 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5744 }, 5745 outputs: []outputInfo{ 5746 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5747 }, 5748 }, 5749 }, 5750 { 5751 name: "SHRB", 5752 argLen: 2, 5753 resultInArg0: true, 5754 clobberFlags: true, 5755 asm: x86.ASHRB, 5756 reg: regInfo{ 5757 inputs: []inputInfo{ 5758 {1, 2}, // CX 5759 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5760 }, 5761 outputs: []outputInfo{ 5762 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5763 }, 5764 }, 5765 }, 5766 { 5767 name: "SHRQconst", 5768 auxType: auxInt8, 5769 argLen: 1, 5770 resultInArg0: true, 5771 clobberFlags: true, 5772 asm: x86.ASHRQ, 5773 reg: regInfo{ 5774 inputs: []inputInfo{ 5775 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5776 }, 5777 outputs: []outputInfo{ 5778 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5779 }, 5780 }, 5781 }, 5782 { 5783 name: "SHRLconst", 5784 auxType: auxInt8, 5785 argLen: 1, 5786 resultInArg0: true, 5787 clobberFlags: true, 5788 asm: x86.ASHRL, 5789 reg: regInfo{ 5790 inputs: []inputInfo{ 5791 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5792 }, 5793 outputs: []outputInfo{ 5794 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5795 }, 5796 }, 5797 }, 5798 { 5799 name: "SHRWconst", 5800 auxType: auxInt8, 5801 argLen: 1, 5802 resultInArg0: true, 5803 clobberFlags: true, 5804 asm: x86.ASHRW, 5805 reg: regInfo{ 5806 inputs: []inputInfo{ 5807 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5808 }, 5809 outputs: []outputInfo{ 5810 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5811 }, 5812 }, 5813 }, 5814 { 5815 name: "SHRBconst", 5816 auxType: auxInt8, 5817 argLen: 1, 5818 resultInArg0: true, 5819 clobberFlags: true, 5820 asm: x86.ASHRB, 5821 reg: regInfo{ 5822 inputs: []inputInfo{ 5823 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5824 }, 5825 outputs: []outputInfo{ 5826 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5827 }, 5828 }, 5829 }, 5830 { 5831 name: "SARQ", 5832 argLen: 2, 5833 resultInArg0: true, 5834 clobberFlags: true, 5835 asm: x86.ASARQ, 5836 reg: regInfo{ 5837 inputs: []inputInfo{ 5838 {1, 2}, // CX 5839 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5840 }, 5841 outputs: []outputInfo{ 5842 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5843 }, 5844 }, 5845 }, 5846 { 5847 name: "SARL", 5848 argLen: 2, 5849 resultInArg0: true, 5850 clobberFlags: true, 5851 asm: x86.ASARL, 5852 reg: regInfo{ 5853 inputs: []inputInfo{ 5854 {1, 2}, // CX 5855 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5856 }, 5857 outputs: []outputInfo{ 5858 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5859 }, 5860 }, 5861 }, 5862 { 5863 name: "SARW", 5864 argLen: 2, 5865 resultInArg0: true, 5866 clobberFlags: true, 5867 asm: x86.ASARW, 5868 reg: regInfo{ 5869 inputs: []inputInfo{ 5870 {1, 2}, // CX 5871 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5872 }, 5873 outputs: []outputInfo{ 5874 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5875 }, 5876 }, 5877 }, 5878 { 5879 name: "SARB", 5880 argLen: 2, 5881 resultInArg0: true, 5882 clobberFlags: true, 5883 asm: x86.ASARB, 5884 reg: regInfo{ 5885 inputs: []inputInfo{ 5886 {1, 2}, // CX 5887 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5888 }, 5889 outputs: []outputInfo{ 5890 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5891 }, 5892 }, 5893 }, 5894 { 5895 name: "SARQconst", 5896 auxType: auxInt8, 5897 argLen: 1, 5898 resultInArg0: true, 5899 clobberFlags: true, 5900 asm: x86.ASARQ, 5901 reg: regInfo{ 5902 inputs: []inputInfo{ 5903 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5904 }, 5905 outputs: []outputInfo{ 5906 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5907 }, 5908 }, 5909 }, 5910 { 5911 name: "SARLconst", 5912 auxType: auxInt8, 5913 argLen: 1, 5914 resultInArg0: true, 5915 clobberFlags: true, 5916 asm: x86.ASARL, 5917 reg: regInfo{ 5918 inputs: []inputInfo{ 5919 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5920 }, 5921 outputs: []outputInfo{ 5922 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5923 }, 5924 }, 5925 }, 5926 { 5927 name: "SARWconst", 5928 auxType: auxInt8, 5929 argLen: 1, 5930 resultInArg0: true, 5931 clobberFlags: true, 5932 asm: x86.ASARW, 5933 reg: regInfo{ 5934 inputs: []inputInfo{ 5935 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5936 }, 5937 outputs: []outputInfo{ 5938 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5939 }, 5940 }, 5941 }, 5942 { 5943 name: "SARBconst", 5944 auxType: auxInt8, 5945 argLen: 1, 5946 resultInArg0: true, 5947 clobberFlags: true, 5948 asm: x86.ASARB, 5949 reg: regInfo{ 5950 inputs: []inputInfo{ 5951 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5952 }, 5953 outputs: []outputInfo{ 5954 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5955 }, 5956 }, 5957 }, 5958 { 5959 name: "ROLQ", 5960 argLen: 2, 5961 resultInArg0: true, 5962 clobberFlags: true, 5963 asm: x86.AROLQ, 5964 reg: regInfo{ 5965 inputs: []inputInfo{ 5966 {1, 2}, // CX 5967 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5968 }, 5969 outputs: []outputInfo{ 5970 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5971 }, 5972 }, 5973 }, 5974 { 5975 name: "ROLL", 5976 argLen: 2, 5977 resultInArg0: true, 5978 clobberFlags: true, 5979 asm: x86.AROLL, 5980 reg: regInfo{ 5981 inputs: []inputInfo{ 5982 {1, 2}, // CX 5983 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5984 }, 5985 outputs: []outputInfo{ 5986 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5987 }, 5988 }, 5989 }, 5990 { 5991 name: "ROLW", 5992 argLen: 2, 5993 resultInArg0: true, 5994 clobberFlags: true, 5995 asm: x86.AROLW, 5996 reg: regInfo{ 5997 inputs: []inputInfo{ 5998 {1, 2}, // CX 5999 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6000 }, 6001 outputs: []outputInfo{ 6002 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6003 }, 6004 }, 6005 }, 6006 { 6007 name: "ROLB", 6008 argLen: 2, 6009 resultInArg0: true, 6010 clobberFlags: true, 6011 asm: x86.AROLB, 6012 reg: regInfo{ 6013 inputs: []inputInfo{ 6014 {1, 2}, // CX 6015 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6016 }, 6017 outputs: []outputInfo{ 6018 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6019 }, 6020 }, 6021 }, 6022 { 6023 name: "RORQ", 6024 argLen: 2, 6025 resultInArg0: true, 6026 clobberFlags: true, 6027 asm: x86.ARORQ, 6028 reg: regInfo{ 6029 inputs: []inputInfo{ 6030 {1, 2}, // CX 6031 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6032 }, 6033 outputs: []outputInfo{ 6034 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6035 }, 6036 }, 6037 }, 6038 { 6039 name: "RORL", 6040 argLen: 2, 6041 resultInArg0: true, 6042 clobberFlags: true, 6043 asm: x86.ARORL, 6044 reg: regInfo{ 6045 inputs: []inputInfo{ 6046 {1, 2}, // CX 6047 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6048 }, 6049 outputs: []outputInfo{ 6050 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6051 }, 6052 }, 6053 }, 6054 { 6055 name: "RORW", 6056 argLen: 2, 6057 resultInArg0: true, 6058 clobberFlags: true, 6059 asm: x86.ARORW, 6060 reg: regInfo{ 6061 inputs: []inputInfo{ 6062 {1, 2}, // CX 6063 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6064 }, 6065 outputs: []outputInfo{ 6066 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6067 }, 6068 }, 6069 }, 6070 { 6071 name: "RORB", 6072 argLen: 2, 6073 resultInArg0: true, 6074 clobberFlags: true, 6075 asm: x86.ARORB, 6076 reg: regInfo{ 6077 inputs: []inputInfo{ 6078 {1, 2}, // CX 6079 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6080 }, 6081 outputs: []outputInfo{ 6082 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6083 }, 6084 }, 6085 }, 6086 { 6087 name: "ROLQconst", 6088 auxType: auxInt8, 6089 argLen: 1, 6090 resultInArg0: true, 6091 clobberFlags: true, 6092 asm: x86.AROLQ, 6093 reg: regInfo{ 6094 inputs: []inputInfo{ 6095 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6096 }, 6097 outputs: []outputInfo{ 6098 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6099 }, 6100 }, 6101 }, 6102 { 6103 name: "ROLLconst", 6104 auxType: auxInt8, 6105 argLen: 1, 6106 resultInArg0: true, 6107 clobberFlags: true, 6108 asm: x86.AROLL, 6109 reg: regInfo{ 6110 inputs: []inputInfo{ 6111 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6112 }, 6113 outputs: []outputInfo{ 6114 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6115 }, 6116 }, 6117 }, 6118 { 6119 name: "ROLWconst", 6120 auxType: auxInt8, 6121 argLen: 1, 6122 resultInArg0: true, 6123 clobberFlags: true, 6124 asm: x86.AROLW, 6125 reg: regInfo{ 6126 inputs: []inputInfo{ 6127 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6128 }, 6129 outputs: []outputInfo{ 6130 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6131 }, 6132 }, 6133 }, 6134 { 6135 name: "ROLBconst", 6136 auxType: auxInt8, 6137 argLen: 1, 6138 resultInArg0: true, 6139 clobberFlags: true, 6140 asm: x86.AROLB, 6141 reg: regInfo{ 6142 inputs: []inputInfo{ 6143 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6144 }, 6145 outputs: []outputInfo{ 6146 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6147 }, 6148 }, 6149 }, 6150 { 6151 name: "ADDLmem", 6152 auxType: auxSymOff, 6153 argLen: 3, 6154 resultInArg0: true, 6155 clobberFlags: true, 6156 faultOnNilArg1: true, 6157 symEffect: SymRead, 6158 asm: x86.AADDL, 6159 reg: regInfo{ 6160 inputs: []inputInfo{ 6161 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6162 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6163 }, 6164 outputs: []outputInfo{ 6165 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6166 }, 6167 }, 6168 }, 6169 { 6170 name: "ADDQmem", 6171 auxType: auxSymOff, 6172 argLen: 3, 6173 resultInArg0: true, 6174 clobberFlags: true, 6175 faultOnNilArg1: true, 6176 symEffect: SymRead, 6177 asm: x86.AADDQ, 6178 reg: regInfo{ 6179 inputs: []inputInfo{ 6180 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6181 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6182 }, 6183 outputs: []outputInfo{ 6184 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6185 }, 6186 }, 6187 }, 6188 { 6189 name: "SUBQmem", 6190 auxType: auxSymOff, 6191 argLen: 3, 6192 resultInArg0: true, 6193 clobberFlags: true, 6194 faultOnNilArg1: true, 6195 symEffect: SymRead, 6196 asm: x86.ASUBQ, 6197 reg: regInfo{ 6198 inputs: []inputInfo{ 6199 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6200 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6201 }, 6202 outputs: []outputInfo{ 6203 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6204 }, 6205 }, 6206 }, 6207 { 6208 name: "SUBLmem", 6209 auxType: auxSymOff, 6210 argLen: 3, 6211 resultInArg0: true, 6212 clobberFlags: true, 6213 faultOnNilArg1: true, 6214 symEffect: SymRead, 6215 asm: x86.ASUBL, 6216 reg: regInfo{ 6217 inputs: []inputInfo{ 6218 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6219 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6220 }, 6221 outputs: []outputInfo{ 6222 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6223 }, 6224 }, 6225 }, 6226 { 6227 name: "ANDLmem", 6228 auxType: auxSymOff, 6229 argLen: 3, 6230 resultInArg0: true, 6231 clobberFlags: true, 6232 faultOnNilArg1: true, 6233 symEffect: SymRead, 6234 asm: x86.AANDL, 6235 reg: regInfo{ 6236 inputs: []inputInfo{ 6237 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6238 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6239 }, 6240 outputs: []outputInfo{ 6241 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6242 }, 6243 }, 6244 }, 6245 { 6246 name: "ANDQmem", 6247 auxType: auxSymOff, 6248 argLen: 3, 6249 resultInArg0: true, 6250 clobberFlags: true, 6251 faultOnNilArg1: true, 6252 symEffect: SymRead, 6253 asm: x86.AANDQ, 6254 reg: regInfo{ 6255 inputs: []inputInfo{ 6256 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6257 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6258 }, 6259 outputs: []outputInfo{ 6260 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6261 }, 6262 }, 6263 }, 6264 { 6265 name: "ORQmem", 6266 auxType: auxSymOff, 6267 argLen: 3, 6268 resultInArg0: true, 6269 clobberFlags: true, 6270 faultOnNilArg1: true, 6271 symEffect: SymRead, 6272 asm: x86.AORQ, 6273 reg: regInfo{ 6274 inputs: []inputInfo{ 6275 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6276 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6277 }, 6278 outputs: []outputInfo{ 6279 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6280 }, 6281 }, 6282 }, 6283 { 6284 name: "ORLmem", 6285 auxType: auxSymOff, 6286 argLen: 3, 6287 resultInArg0: true, 6288 clobberFlags: true, 6289 faultOnNilArg1: true, 6290 symEffect: SymRead, 6291 asm: x86.AORL, 6292 reg: regInfo{ 6293 inputs: []inputInfo{ 6294 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6295 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6296 }, 6297 outputs: []outputInfo{ 6298 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6299 }, 6300 }, 6301 }, 6302 { 6303 name: "XORQmem", 6304 auxType: auxSymOff, 6305 argLen: 3, 6306 resultInArg0: true, 6307 clobberFlags: true, 6308 faultOnNilArg1: true, 6309 symEffect: SymRead, 6310 asm: x86.AXORQ, 6311 reg: regInfo{ 6312 inputs: []inputInfo{ 6313 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6314 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6315 }, 6316 outputs: []outputInfo{ 6317 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6318 }, 6319 }, 6320 }, 6321 { 6322 name: "XORLmem", 6323 auxType: auxSymOff, 6324 argLen: 3, 6325 resultInArg0: true, 6326 clobberFlags: true, 6327 faultOnNilArg1: true, 6328 symEffect: SymRead, 6329 asm: x86.AXORL, 6330 reg: regInfo{ 6331 inputs: []inputInfo{ 6332 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6333 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6334 }, 6335 outputs: []outputInfo{ 6336 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6337 }, 6338 }, 6339 }, 6340 { 6341 name: "NEGQ", 6342 argLen: 1, 6343 resultInArg0: true, 6344 clobberFlags: true, 6345 asm: x86.ANEGQ, 6346 reg: regInfo{ 6347 inputs: []inputInfo{ 6348 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6349 }, 6350 outputs: []outputInfo{ 6351 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6352 }, 6353 }, 6354 }, 6355 { 6356 name: "NEGL", 6357 argLen: 1, 6358 resultInArg0: true, 6359 clobberFlags: true, 6360 asm: x86.ANEGL, 6361 reg: regInfo{ 6362 inputs: []inputInfo{ 6363 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6364 }, 6365 outputs: []outputInfo{ 6366 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6367 }, 6368 }, 6369 }, 6370 { 6371 name: "NOTQ", 6372 argLen: 1, 6373 resultInArg0: true, 6374 clobberFlags: true, 6375 asm: x86.ANOTQ, 6376 reg: regInfo{ 6377 inputs: []inputInfo{ 6378 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6379 }, 6380 outputs: []outputInfo{ 6381 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6382 }, 6383 }, 6384 }, 6385 { 6386 name: "NOTL", 6387 argLen: 1, 6388 resultInArg0: true, 6389 clobberFlags: true, 6390 asm: x86.ANOTL, 6391 reg: regInfo{ 6392 inputs: []inputInfo{ 6393 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6394 }, 6395 outputs: []outputInfo{ 6396 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6397 }, 6398 }, 6399 }, 6400 { 6401 name: "BSFQ", 6402 argLen: 1, 6403 asm: x86.ABSFQ, 6404 reg: regInfo{ 6405 inputs: []inputInfo{ 6406 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6407 }, 6408 outputs: []outputInfo{ 6409 {1, 0}, 6410 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6411 }, 6412 }, 6413 }, 6414 { 6415 name: "BSFL", 6416 argLen: 1, 6417 asm: x86.ABSFL, 6418 reg: regInfo{ 6419 inputs: []inputInfo{ 6420 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6421 }, 6422 outputs: []outputInfo{ 6423 {1, 0}, 6424 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6425 }, 6426 }, 6427 }, 6428 { 6429 name: "BSRQ", 6430 argLen: 1, 6431 asm: x86.ABSRQ, 6432 reg: regInfo{ 6433 inputs: []inputInfo{ 6434 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6435 }, 6436 outputs: []outputInfo{ 6437 {1, 0}, 6438 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6439 }, 6440 }, 6441 }, 6442 { 6443 name: "BSRL", 6444 argLen: 1, 6445 asm: x86.ABSRL, 6446 reg: regInfo{ 6447 inputs: []inputInfo{ 6448 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6449 }, 6450 outputs: []outputInfo{ 6451 {1, 0}, 6452 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6453 }, 6454 }, 6455 }, 6456 { 6457 name: "CMOVQEQ", 6458 argLen: 3, 6459 resultInArg0: true, 6460 asm: x86.ACMOVQEQ, 6461 reg: regInfo{ 6462 inputs: []inputInfo{ 6463 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6464 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6465 }, 6466 outputs: []outputInfo{ 6467 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6468 }, 6469 }, 6470 }, 6471 { 6472 name: "CMOVLEQ", 6473 argLen: 3, 6474 resultInArg0: true, 6475 asm: x86.ACMOVLEQ, 6476 reg: regInfo{ 6477 inputs: []inputInfo{ 6478 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6479 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6480 }, 6481 outputs: []outputInfo{ 6482 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6483 }, 6484 }, 6485 }, 6486 { 6487 name: "BSWAPQ", 6488 argLen: 1, 6489 resultInArg0: true, 6490 clobberFlags: true, 6491 asm: x86.ABSWAPQ, 6492 reg: regInfo{ 6493 inputs: []inputInfo{ 6494 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6495 }, 6496 outputs: []outputInfo{ 6497 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6498 }, 6499 }, 6500 }, 6501 { 6502 name: "BSWAPL", 6503 argLen: 1, 6504 resultInArg0: true, 6505 clobberFlags: true, 6506 asm: x86.ABSWAPL, 6507 reg: regInfo{ 6508 inputs: []inputInfo{ 6509 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6510 }, 6511 outputs: []outputInfo{ 6512 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6513 }, 6514 }, 6515 }, 6516 { 6517 name: "POPCNTQ", 6518 argLen: 1, 6519 clobberFlags: true, 6520 asm: x86.APOPCNTQ, 6521 reg: regInfo{ 6522 inputs: []inputInfo{ 6523 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6524 }, 6525 outputs: []outputInfo{ 6526 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6527 }, 6528 }, 6529 }, 6530 { 6531 name: "POPCNTL", 6532 argLen: 1, 6533 clobberFlags: true, 6534 asm: x86.APOPCNTL, 6535 reg: regInfo{ 6536 inputs: []inputInfo{ 6537 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6538 }, 6539 outputs: []outputInfo{ 6540 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6541 }, 6542 }, 6543 }, 6544 { 6545 name: "SQRTSD", 6546 argLen: 1, 6547 asm: x86.ASQRTSD, 6548 reg: regInfo{ 6549 inputs: []inputInfo{ 6550 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6551 }, 6552 outputs: []outputInfo{ 6553 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6554 }, 6555 }, 6556 }, 6557 { 6558 name: "SBBQcarrymask", 6559 argLen: 1, 6560 asm: x86.ASBBQ, 6561 reg: regInfo{ 6562 outputs: []outputInfo{ 6563 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6564 }, 6565 }, 6566 }, 6567 { 6568 name: "SBBLcarrymask", 6569 argLen: 1, 6570 asm: x86.ASBBL, 6571 reg: regInfo{ 6572 outputs: []outputInfo{ 6573 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6574 }, 6575 }, 6576 }, 6577 { 6578 name: "SETEQ", 6579 argLen: 1, 6580 asm: x86.ASETEQ, 6581 reg: regInfo{ 6582 outputs: []outputInfo{ 6583 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6584 }, 6585 }, 6586 }, 6587 { 6588 name: "SETNE", 6589 argLen: 1, 6590 asm: x86.ASETNE, 6591 reg: regInfo{ 6592 outputs: []outputInfo{ 6593 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6594 }, 6595 }, 6596 }, 6597 { 6598 name: "SETL", 6599 argLen: 1, 6600 asm: x86.ASETLT, 6601 reg: regInfo{ 6602 outputs: []outputInfo{ 6603 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6604 }, 6605 }, 6606 }, 6607 { 6608 name: "SETLE", 6609 argLen: 1, 6610 asm: x86.ASETLE, 6611 reg: regInfo{ 6612 outputs: []outputInfo{ 6613 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6614 }, 6615 }, 6616 }, 6617 { 6618 name: "SETG", 6619 argLen: 1, 6620 asm: x86.ASETGT, 6621 reg: regInfo{ 6622 outputs: []outputInfo{ 6623 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6624 }, 6625 }, 6626 }, 6627 { 6628 name: "SETGE", 6629 argLen: 1, 6630 asm: x86.ASETGE, 6631 reg: regInfo{ 6632 outputs: []outputInfo{ 6633 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6634 }, 6635 }, 6636 }, 6637 { 6638 name: "SETB", 6639 argLen: 1, 6640 asm: x86.ASETCS, 6641 reg: regInfo{ 6642 outputs: []outputInfo{ 6643 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6644 }, 6645 }, 6646 }, 6647 { 6648 name: "SETBE", 6649 argLen: 1, 6650 asm: x86.ASETLS, 6651 reg: regInfo{ 6652 outputs: []outputInfo{ 6653 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6654 }, 6655 }, 6656 }, 6657 { 6658 name: "SETA", 6659 argLen: 1, 6660 asm: x86.ASETHI, 6661 reg: regInfo{ 6662 outputs: []outputInfo{ 6663 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6664 }, 6665 }, 6666 }, 6667 { 6668 name: "SETAE", 6669 argLen: 1, 6670 asm: x86.ASETCC, 6671 reg: regInfo{ 6672 outputs: []outputInfo{ 6673 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6674 }, 6675 }, 6676 }, 6677 { 6678 name: "SETEQF", 6679 argLen: 1, 6680 clobberFlags: true, 6681 asm: x86.ASETEQ, 6682 reg: regInfo{ 6683 clobbers: 1, // AX 6684 outputs: []outputInfo{ 6685 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6686 }, 6687 }, 6688 }, 6689 { 6690 name: "SETNEF", 6691 argLen: 1, 6692 clobberFlags: true, 6693 asm: x86.ASETNE, 6694 reg: regInfo{ 6695 clobbers: 1, // AX 6696 outputs: []outputInfo{ 6697 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6698 }, 6699 }, 6700 }, 6701 { 6702 name: "SETORD", 6703 argLen: 1, 6704 asm: x86.ASETPC, 6705 reg: regInfo{ 6706 outputs: []outputInfo{ 6707 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6708 }, 6709 }, 6710 }, 6711 { 6712 name: "SETNAN", 6713 argLen: 1, 6714 asm: x86.ASETPS, 6715 reg: regInfo{ 6716 outputs: []outputInfo{ 6717 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6718 }, 6719 }, 6720 }, 6721 { 6722 name: "SETGF", 6723 argLen: 1, 6724 asm: x86.ASETHI, 6725 reg: regInfo{ 6726 outputs: []outputInfo{ 6727 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6728 }, 6729 }, 6730 }, 6731 { 6732 name: "SETGEF", 6733 argLen: 1, 6734 asm: x86.ASETCC, 6735 reg: regInfo{ 6736 outputs: []outputInfo{ 6737 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6738 }, 6739 }, 6740 }, 6741 { 6742 name: "MOVBQSX", 6743 argLen: 1, 6744 asm: x86.AMOVBQSX, 6745 reg: regInfo{ 6746 inputs: []inputInfo{ 6747 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6748 }, 6749 outputs: []outputInfo{ 6750 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6751 }, 6752 }, 6753 }, 6754 { 6755 name: "MOVBQZX", 6756 argLen: 1, 6757 asm: x86.AMOVBLZX, 6758 reg: regInfo{ 6759 inputs: []inputInfo{ 6760 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6761 }, 6762 outputs: []outputInfo{ 6763 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6764 }, 6765 }, 6766 }, 6767 { 6768 name: "MOVWQSX", 6769 argLen: 1, 6770 asm: x86.AMOVWQSX, 6771 reg: regInfo{ 6772 inputs: []inputInfo{ 6773 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6774 }, 6775 outputs: []outputInfo{ 6776 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6777 }, 6778 }, 6779 }, 6780 { 6781 name: "MOVWQZX", 6782 argLen: 1, 6783 asm: x86.AMOVWLZX, 6784 reg: regInfo{ 6785 inputs: []inputInfo{ 6786 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6787 }, 6788 outputs: []outputInfo{ 6789 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6790 }, 6791 }, 6792 }, 6793 { 6794 name: "MOVLQSX", 6795 argLen: 1, 6796 asm: x86.AMOVLQSX, 6797 reg: regInfo{ 6798 inputs: []inputInfo{ 6799 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6800 }, 6801 outputs: []outputInfo{ 6802 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6803 }, 6804 }, 6805 }, 6806 { 6807 name: "MOVLQZX", 6808 argLen: 1, 6809 asm: x86.AMOVL, 6810 reg: regInfo{ 6811 inputs: []inputInfo{ 6812 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6813 }, 6814 outputs: []outputInfo{ 6815 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6816 }, 6817 }, 6818 }, 6819 { 6820 name: "MOVLconst", 6821 auxType: auxInt32, 6822 argLen: 0, 6823 rematerializeable: true, 6824 asm: x86.AMOVL, 6825 reg: regInfo{ 6826 outputs: []outputInfo{ 6827 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6828 }, 6829 }, 6830 }, 6831 { 6832 name: "MOVQconst", 6833 auxType: auxInt64, 6834 argLen: 0, 6835 rematerializeable: true, 6836 asm: x86.AMOVQ, 6837 reg: regInfo{ 6838 outputs: []outputInfo{ 6839 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6840 }, 6841 }, 6842 }, 6843 { 6844 name: "CVTTSD2SL", 6845 argLen: 1, 6846 asm: x86.ACVTTSD2SL, 6847 reg: regInfo{ 6848 inputs: []inputInfo{ 6849 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6850 }, 6851 outputs: []outputInfo{ 6852 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6853 }, 6854 }, 6855 }, 6856 { 6857 name: "CVTTSD2SQ", 6858 argLen: 1, 6859 asm: x86.ACVTTSD2SQ, 6860 reg: regInfo{ 6861 inputs: []inputInfo{ 6862 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6863 }, 6864 outputs: []outputInfo{ 6865 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6866 }, 6867 }, 6868 }, 6869 { 6870 name: "CVTTSS2SL", 6871 argLen: 1, 6872 asm: x86.ACVTTSS2SL, 6873 reg: regInfo{ 6874 inputs: []inputInfo{ 6875 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6876 }, 6877 outputs: []outputInfo{ 6878 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6879 }, 6880 }, 6881 }, 6882 { 6883 name: "CVTTSS2SQ", 6884 argLen: 1, 6885 asm: x86.ACVTTSS2SQ, 6886 reg: regInfo{ 6887 inputs: []inputInfo{ 6888 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6889 }, 6890 outputs: []outputInfo{ 6891 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6892 }, 6893 }, 6894 }, 6895 { 6896 name: "CVTSL2SS", 6897 argLen: 1, 6898 asm: x86.ACVTSL2SS, 6899 reg: regInfo{ 6900 inputs: []inputInfo{ 6901 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6902 }, 6903 outputs: []outputInfo{ 6904 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6905 }, 6906 }, 6907 }, 6908 { 6909 name: "CVTSL2SD", 6910 argLen: 1, 6911 asm: x86.ACVTSL2SD, 6912 reg: regInfo{ 6913 inputs: []inputInfo{ 6914 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6915 }, 6916 outputs: []outputInfo{ 6917 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6918 }, 6919 }, 6920 }, 6921 { 6922 name: "CVTSQ2SS", 6923 argLen: 1, 6924 asm: x86.ACVTSQ2SS, 6925 reg: regInfo{ 6926 inputs: []inputInfo{ 6927 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6928 }, 6929 outputs: []outputInfo{ 6930 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6931 }, 6932 }, 6933 }, 6934 { 6935 name: "CVTSQ2SD", 6936 argLen: 1, 6937 asm: x86.ACVTSQ2SD, 6938 reg: regInfo{ 6939 inputs: []inputInfo{ 6940 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6941 }, 6942 outputs: []outputInfo{ 6943 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6944 }, 6945 }, 6946 }, 6947 { 6948 name: "CVTSD2SS", 6949 argLen: 1, 6950 asm: x86.ACVTSD2SS, 6951 reg: regInfo{ 6952 inputs: []inputInfo{ 6953 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6954 }, 6955 outputs: []outputInfo{ 6956 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6957 }, 6958 }, 6959 }, 6960 { 6961 name: "CVTSS2SD", 6962 argLen: 1, 6963 asm: x86.ACVTSS2SD, 6964 reg: regInfo{ 6965 inputs: []inputInfo{ 6966 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6967 }, 6968 outputs: []outputInfo{ 6969 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6970 }, 6971 }, 6972 }, 6973 { 6974 name: "PXOR", 6975 argLen: 2, 6976 commutative: true, 6977 resultInArg0: true, 6978 asm: x86.APXOR, 6979 reg: regInfo{ 6980 inputs: []inputInfo{ 6981 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6982 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6983 }, 6984 outputs: []outputInfo{ 6985 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6986 }, 6987 }, 6988 }, 6989 { 6990 name: "LEAQ", 6991 auxType: auxSymOff, 6992 argLen: 1, 6993 rematerializeable: true, 6994 symEffect: SymAddr, 6995 asm: x86.ALEAQ, 6996 reg: regInfo{ 6997 inputs: []inputInfo{ 6998 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6999 }, 7000 outputs: []outputInfo{ 7001 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7002 }, 7003 }, 7004 }, 7005 { 7006 name: "LEAQ1", 7007 auxType: auxSymOff, 7008 argLen: 2, 7009 commutative: true, 7010 symEffect: SymAddr, 7011 reg: regInfo{ 7012 inputs: []inputInfo{ 7013 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7014 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7015 }, 7016 outputs: []outputInfo{ 7017 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7018 }, 7019 }, 7020 }, 7021 { 7022 name: "LEAQ2", 7023 auxType: auxSymOff, 7024 argLen: 2, 7025 symEffect: SymAddr, 7026 reg: regInfo{ 7027 inputs: []inputInfo{ 7028 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7029 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7030 }, 7031 outputs: []outputInfo{ 7032 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7033 }, 7034 }, 7035 }, 7036 { 7037 name: "LEAQ4", 7038 auxType: auxSymOff, 7039 argLen: 2, 7040 symEffect: SymAddr, 7041 reg: regInfo{ 7042 inputs: []inputInfo{ 7043 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7044 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7045 }, 7046 outputs: []outputInfo{ 7047 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7048 }, 7049 }, 7050 }, 7051 { 7052 name: "LEAQ8", 7053 auxType: auxSymOff, 7054 argLen: 2, 7055 symEffect: SymAddr, 7056 reg: regInfo{ 7057 inputs: []inputInfo{ 7058 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7059 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7060 }, 7061 outputs: []outputInfo{ 7062 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7063 }, 7064 }, 7065 }, 7066 { 7067 name: "LEAL", 7068 auxType: auxSymOff, 7069 argLen: 1, 7070 rematerializeable: true, 7071 symEffect: SymAddr, 7072 asm: x86.ALEAL, 7073 reg: regInfo{ 7074 inputs: []inputInfo{ 7075 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7076 }, 7077 outputs: []outputInfo{ 7078 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7079 }, 7080 }, 7081 }, 7082 { 7083 name: "MOVBload", 7084 auxType: auxSymOff, 7085 argLen: 2, 7086 faultOnNilArg0: true, 7087 symEffect: SymRead, 7088 asm: x86.AMOVBLZX, 7089 reg: regInfo{ 7090 inputs: []inputInfo{ 7091 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7092 }, 7093 outputs: []outputInfo{ 7094 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7095 }, 7096 }, 7097 }, 7098 { 7099 name: "MOVBQSXload", 7100 auxType: auxSymOff, 7101 argLen: 2, 7102 faultOnNilArg0: true, 7103 symEffect: SymRead, 7104 asm: x86.AMOVBQSX, 7105 reg: regInfo{ 7106 inputs: []inputInfo{ 7107 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7108 }, 7109 outputs: []outputInfo{ 7110 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7111 }, 7112 }, 7113 }, 7114 { 7115 name: "MOVWload", 7116 auxType: auxSymOff, 7117 argLen: 2, 7118 faultOnNilArg0: true, 7119 symEffect: SymRead, 7120 asm: x86.AMOVWLZX, 7121 reg: regInfo{ 7122 inputs: []inputInfo{ 7123 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7124 }, 7125 outputs: []outputInfo{ 7126 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7127 }, 7128 }, 7129 }, 7130 { 7131 name: "MOVWQSXload", 7132 auxType: auxSymOff, 7133 argLen: 2, 7134 faultOnNilArg0: true, 7135 symEffect: SymRead, 7136 asm: x86.AMOVWQSX, 7137 reg: regInfo{ 7138 inputs: []inputInfo{ 7139 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7140 }, 7141 outputs: []outputInfo{ 7142 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7143 }, 7144 }, 7145 }, 7146 { 7147 name: "MOVLload", 7148 auxType: auxSymOff, 7149 argLen: 2, 7150 faultOnNilArg0: true, 7151 symEffect: SymRead, 7152 asm: x86.AMOVL, 7153 reg: regInfo{ 7154 inputs: []inputInfo{ 7155 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7156 }, 7157 outputs: []outputInfo{ 7158 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7159 }, 7160 }, 7161 }, 7162 { 7163 name: "MOVLQSXload", 7164 auxType: auxSymOff, 7165 argLen: 2, 7166 faultOnNilArg0: true, 7167 symEffect: SymRead, 7168 asm: x86.AMOVLQSX, 7169 reg: regInfo{ 7170 inputs: []inputInfo{ 7171 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7172 }, 7173 outputs: []outputInfo{ 7174 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7175 }, 7176 }, 7177 }, 7178 { 7179 name: "MOVQload", 7180 auxType: auxSymOff, 7181 argLen: 2, 7182 faultOnNilArg0: true, 7183 symEffect: SymRead, 7184 asm: x86.AMOVQ, 7185 reg: regInfo{ 7186 inputs: []inputInfo{ 7187 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7188 }, 7189 outputs: []outputInfo{ 7190 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7191 }, 7192 }, 7193 }, 7194 { 7195 name: "MOVBstore", 7196 auxType: auxSymOff, 7197 argLen: 3, 7198 faultOnNilArg0: true, 7199 symEffect: SymWrite, 7200 asm: x86.AMOVB, 7201 reg: regInfo{ 7202 inputs: []inputInfo{ 7203 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7204 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7205 }, 7206 }, 7207 }, 7208 { 7209 name: "MOVWstore", 7210 auxType: auxSymOff, 7211 argLen: 3, 7212 faultOnNilArg0: true, 7213 symEffect: SymWrite, 7214 asm: x86.AMOVW, 7215 reg: regInfo{ 7216 inputs: []inputInfo{ 7217 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7218 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7219 }, 7220 }, 7221 }, 7222 { 7223 name: "MOVLstore", 7224 auxType: auxSymOff, 7225 argLen: 3, 7226 faultOnNilArg0: true, 7227 symEffect: SymWrite, 7228 asm: x86.AMOVL, 7229 reg: regInfo{ 7230 inputs: []inputInfo{ 7231 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7232 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7233 }, 7234 }, 7235 }, 7236 { 7237 name: "MOVQstore", 7238 auxType: auxSymOff, 7239 argLen: 3, 7240 faultOnNilArg0: true, 7241 symEffect: SymWrite, 7242 asm: x86.AMOVQ, 7243 reg: regInfo{ 7244 inputs: []inputInfo{ 7245 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7246 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7247 }, 7248 }, 7249 }, 7250 { 7251 name: "MOVOload", 7252 auxType: auxSymOff, 7253 argLen: 2, 7254 faultOnNilArg0: true, 7255 symEffect: SymRead, 7256 asm: x86.AMOVUPS, 7257 reg: regInfo{ 7258 inputs: []inputInfo{ 7259 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7260 }, 7261 outputs: []outputInfo{ 7262 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7263 }, 7264 }, 7265 }, 7266 { 7267 name: "MOVOstore", 7268 auxType: auxSymOff, 7269 argLen: 3, 7270 faultOnNilArg0: true, 7271 symEffect: SymWrite, 7272 asm: x86.AMOVUPS, 7273 reg: regInfo{ 7274 inputs: []inputInfo{ 7275 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7276 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7277 }, 7278 }, 7279 }, 7280 { 7281 name: "MOVBloadidx1", 7282 auxType: auxSymOff, 7283 argLen: 3, 7284 commutative: true, 7285 symEffect: SymRead, 7286 asm: x86.AMOVBLZX, 7287 reg: regInfo{ 7288 inputs: []inputInfo{ 7289 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7290 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7291 }, 7292 outputs: []outputInfo{ 7293 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7294 }, 7295 }, 7296 }, 7297 { 7298 name: "MOVWloadidx1", 7299 auxType: auxSymOff, 7300 argLen: 3, 7301 commutative: true, 7302 symEffect: SymRead, 7303 asm: x86.AMOVWLZX, 7304 reg: regInfo{ 7305 inputs: []inputInfo{ 7306 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7307 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7308 }, 7309 outputs: []outputInfo{ 7310 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7311 }, 7312 }, 7313 }, 7314 { 7315 name: "MOVWloadidx2", 7316 auxType: auxSymOff, 7317 argLen: 3, 7318 symEffect: SymRead, 7319 asm: x86.AMOVWLZX, 7320 reg: regInfo{ 7321 inputs: []inputInfo{ 7322 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7323 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7324 }, 7325 outputs: []outputInfo{ 7326 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7327 }, 7328 }, 7329 }, 7330 { 7331 name: "MOVLloadidx1", 7332 auxType: auxSymOff, 7333 argLen: 3, 7334 commutative: true, 7335 symEffect: SymRead, 7336 asm: x86.AMOVL, 7337 reg: regInfo{ 7338 inputs: []inputInfo{ 7339 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7340 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7341 }, 7342 outputs: []outputInfo{ 7343 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7344 }, 7345 }, 7346 }, 7347 { 7348 name: "MOVLloadidx4", 7349 auxType: auxSymOff, 7350 argLen: 3, 7351 symEffect: SymRead, 7352 asm: x86.AMOVL, 7353 reg: regInfo{ 7354 inputs: []inputInfo{ 7355 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7356 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7357 }, 7358 outputs: []outputInfo{ 7359 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7360 }, 7361 }, 7362 }, 7363 { 7364 name: "MOVQloadidx1", 7365 auxType: auxSymOff, 7366 argLen: 3, 7367 commutative: true, 7368 symEffect: SymRead, 7369 asm: x86.AMOVQ, 7370 reg: regInfo{ 7371 inputs: []inputInfo{ 7372 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7373 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7374 }, 7375 outputs: []outputInfo{ 7376 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7377 }, 7378 }, 7379 }, 7380 { 7381 name: "MOVQloadidx8", 7382 auxType: auxSymOff, 7383 argLen: 3, 7384 symEffect: SymRead, 7385 asm: x86.AMOVQ, 7386 reg: regInfo{ 7387 inputs: []inputInfo{ 7388 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7389 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7390 }, 7391 outputs: []outputInfo{ 7392 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7393 }, 7394 }, 7395 }, 7396 { 7397 name: "MOVBstoreidx1", 7398 auxType: auxSymOff, 7399 argLen: 4, 7400 symEffect: SymWrite, 7401 asm: x86.AMOVB, 7402 reg: regInfo{ 7403 inputs: []inputInfo{ 7404 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7405 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7406 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7407 }, 7408 }, 7409 }, 7410 { 7411 name: "MOVWstoreidx1", 7412 auxType: auxSymOff, 7413 argLen: 4, 7414 symEffect: SymWrite, 7415 asm: x86.AMOVW, 7416 reg: regInfo{ 7417 inputs: []inputInfo{ 7418 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7419 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7420 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7421 }, 7422 }, 7423 }, 7424 { 7425 name: "MOVWstoreidx2", 7426 auxType: auxSymOff, 7427 argLen: 4, 7428 symEffect: SymWrite, 7429 asm: x86.AMOVW, 7430 reg: regInfo{ 7431 inputs: []inputInfo{ 7432 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7433 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7434 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7435 }, 7436 }, 7437 }, 7438 { 7439 name: "MOVLstoreidx1", 7440 auxType: auxSymOff, 7441 argLen: 4, 7442 symEffect: SymWrite, 7443 asm: x86.AMOVL, 7444 reg: regInfo{ 7445 inputs: []inputInfo{ 7446 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7447 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7448 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7449 }, 7450 }, 7451 }, 7452 { 7453 name: "MOVLstoreidx4", 7454 auxType: auxSymOff, 7455 argLen: 4, 7456 symEffect: SymWrite, 7457 asm: x86.AMOVL, 7458 reg: regInfo{ 7459 inputs: []inputInfo{ 7460 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7461 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7462 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7463 }, 7464 }, 7465 }, 7466 { 7467 name: "MOVQstoreidx1", 7468 auxType: auxSymOff, 7469 argLen: 4, 7470 symEffect: SymWrite, 7471 asm: x86.AMOVQ, 7472 reg: regInfo{ 7473 inputs: []inputInfo{ 7474 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7475 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7476 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7477 }, 7478 }, 7479 }, 7480 { 7481 name: "MOVQstoreidx8", 7482 auxType: auxSymOff, 7483 argLen: 4, 7484 symEffect: SymWrite, 7485 asm: x86.AMOVQ, 7486 reg: regInfo{ 7487 inputs: []inputInfo{ 7488 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7489 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7490 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7491 }, 7492 }, 7493 }, 7494 { 7495 name: "MOVBstoreconst", 7496 auxType: auxSymValAndOff, 7497 argLen: 2, 7498 faultOnNilArg0: true, 7499 symEffect: SymWrite, 7500 asm: x86.AMOVB, 7501 reg: regInfo{ 7502 inputs: []inputInfo{ 7503 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7504 }, 7505 }, 7506 }, 7507 { 7508 name: "MOVWstoreconst", 7509 auxType: auxSymValAndOff, 7510 argLen: 2, 7511 faultOnNilArg0: true, 7512 symEffect: SymWrite, 7513 asm: x86.AMOVW, 7514 reg: regInfo{ 7515 inputs: []inputInfo{ 7516 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7517 }, 7518 }, 7519 }, 7520 { 7521 name: "MOVLstoreconst", 7522 auxType: auxSymValAndOff, 7523 argLen: 2, 7524 faultOnNilArg0: true, 7525 symEffect: SymWrite, 7526 asm: x86.AMOVL, 7527 reg: regInfo{ 7528 inputs: []inputInfo{ 7529 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7530 }, 7531 }, 7532 }, 7533 { 7534 name: "MOVQstoreconst", 7535 auxType: auxSymValAndOff, 7536 argLen: 2, 7537 faultOnNilArg0: true, 7538 symEffect: SymWrite, 7539 asm: x86.AMOVQ, 7540 reg: regInfo{ 7541 inputs: []inputInfo{ 7542 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7543 }, 7544 }, 7545 }, 7546 { 7547 name: "MOVBstoreconstidx1", 7548 auxType: auxSymValAndOff, 7549 argLen: 3, 7550 symEffect: SymWrite, 7551 asm: x86.AMOVB, 7552 reg: regInfo{ 7553 inputs: []inputInfo{ 7554 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7555 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7556 }, 7557 }, 7558 }, 7559 { 7560 name: "MOVWstoreconstidx1", 7561 auxType: auxSymValAndOff, 7562 argLen: 3, 7563 symEffect: SymWrite, 7564 asm: x86.AMOVW, 7565 reg: regInfo{ 7566 inputs: []inputInfo{ 7567 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7568 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7569 }, 7570 }, 7571 }, 7572 { 7573 name: "MOVWstoreconstidx2", 7574 auxType: auxSymValAndOff, 7575 argLen: 3, 7576 symEffect: SymWrite, 7577 asm: x86.AMOVW, 7578 reg: regInfo{ 7579 inputs: []inputInfo{ 7580 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7581 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7582 }, 7583 }, 7584 }, 7585 { 7586 name: "MOVLstoreconstidx1", 7587 auxType: auxSymValAndOff, 7588 argLen: 3, 7589 symEffect: SymWrite, 7590 asm: x86.AMOVL, 7591 reg: regInfo{ 7592 inputs: []inputInfo{ 7593 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7594 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7595 }, 7596 }, 7597 }, 7598 { 7599 name: "MOVLstoreconstidx4", 7600 auxType: auxSymValAndOff, 7601 argLen: 3, 7602 symEffect: SymWrite, 7603 asm: x86.AMOVL, 7604 reg: regInfo{ 7605 inputs: []inputInfo{ 7606 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7607 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7608 }, 7609 }, 7610 }, 7611 { 7612 name: "MOVQstoreconstidx1", 7613 auxType: auxSymValAndOff, 7614 argLen: 3, 7615 symEffect: SymWrite, 7616 asm: x86.AMOVQ, 7617 reg: regInfo{ 7618 inputs: []inputInfo{ 7619 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7620 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7621 }, 7622 }, 7623 }, 7624 { 7625 name: "MOVQstoreconstidx8", 7626 auxType: auxSymValAndOff, 7627 argLen: 3, 7628 symEffect: SymWrite, 7629 asm: x86.AMOVQ, 7630 reg: regInfo{ 7631 inputs: []inputInfo{ 7632 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7633 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7634 }, 7635 }, 7636 }, 7637 { 7638 name: "DUFFZERO", 7639 auxType: auxInt64, 7640 argLen: 3, 7641 clobberFlags: true, 7642 faultOnNilArg0: true, 7643 reg: regInfo{ 7644 inputs: []inputInfo{ 7645 {0, 128}, // DI 7646 {1, 65536}, // X0 7647 }, 7648 clobbers: 128, // DI 7649 }, 7650 }, 7651 { 7652 name: "MOVOconst", 7653 auxType: auxInt128, 7654 argLen: 0, 7655 rematerializeable: true, 7656 reg: regInfo{ 7657 outputs: []outputInfo{ 7658 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7659 }, 7660 }, 7661 }, 7662 { 7663 name: "REPSTOSQ", 7664 argLen: 4, 7665 faultOnNilArg0: true, 7666 reg: regInfo{ 7667 inputs: []inputInfo{ 7668 {0, 128}, // DI 7669 {1, 2}, // CX 7670 {2, 1}, // AX 7671 }, 7672 clobbers: 130, // CX DI 7673 }, 7674 }, 7675 { 7676 name: "CALLstatic", 7677 auxType: auxSymOff, 7678 argLen: 1, 7679 clobberFlags: true, 7680 call: true, 7681 symEffect: SymNone, 7682 reg: regInfo{ 7683 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7684 }, 7685 }, 7686 { 7687 name: "CALLclosure", 7688 auxType: auxInt64, 7689 argLen: 3, 7690 clobberFlags: true, 7691 call: true, 7692 reg: regInfo{ 7693 inputs: []inputInfo{ 7694 {1, 4}, // DX 7695 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7696 }, 7697 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7698 }, 7699 }, 7700 { 7701 name: "CALLinter", 7702 auxType: auxInt64, 7703 argLen: 2, 7704 clobberFlags: true, 7705 call: true, 7706 reg: regInfo{ 7707 inputs: []inputInfo{ 7708 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7709 }, 7710 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7711 }, 7712 }, 7713 { 7714 name: "DUFFCOPY", 7715 auxType: auxInt64, 7716 argLen: 3, 7717 clobberFlags: true, 7718 faultOnNilArg0: true, 7719 faultOnNilArg1: true, 7720 reg: regInfo{ 7721 inputs: []inputInfo{ 7722 {0, 128}, // DI 7723 {1, 64}, // SI 7724 }, 7725 clobbers: 65728, // SI DI X0 7726 }, 7727 }, 7728 { 7729 name: "REPMOVSQ", 7730 argLen: 4, 7731 faultOnNilArg0: true, 7732 faultOnNilArg1: true, 7733 reg: regInfo{ 7734 inputs: []inputInfo{ 7735 {0, 128}, // DI 7736 {1, 64}, // SI 7737 {2, 2}, // CX 7738 }, 7739 clobbers: 194, // CX SI DI 7740 }, 7741 }, 7742 { 7743 name: "InvertFlags", 7744 argLen: 1, 7745 reg: regInfo{}, 7746 }, 7747 { 7748 name: "LoweredGetG", 7749 argLen: 1, 7750 reg: regInfo{ 7751 outputs: []outputInfo{ 7752 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7753 }, 7754 }, 7755 }, 7756 { 7757 name: "LoweredGetClosurePtr", 7758 argLen: 0, 7759 reg: regInfo{ 7760 outputs: []outputInfo{ 7761 {0, 4}, // DX 7762 }, 7763 }, 7764 }, 7765 { 7766 name: "LoweredNilCheck", 7767 argLen: 2, 7768 clobberFlags: true, 7769 nilCheck: true, 7770 faultOnNilArg0: true, 7771 reg: regInfo{ 7772 inputs: []inputInfo{ 7773 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7774 }, 7775 }, 7776 }, 7777 { 7778 name: "MOVQconvert", 7779 argLen: 2, 7780 asm: x86.AMOVQ, 7781 reg: regInfo{ 7782 inputs: []inputInfo{ 7783 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7784 }, 7785 outputs: []outputInfo{ 7786 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7787 }, 7788 }, 7789 }, 7790 { 7791 name: "MOVLconvert", 7792 argLen: 2, 7793 asm: x86.AMOVL, 7794 reg: regInfo{ 7795 inputs: []inputInfo{ 7796 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7797 }, 7798 outputs: []outputInfo{ 7799 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7800 }, 7801 }, 7802 }, 7803 { 7804 name: "FlagEQ", 7805 argLen: 0, 7806 reg: regInfo{}, 7807 }, 7808 { 7809 name: "FlagLT_ULT", 7810 argLen: 0, 7811 reg: regInfo{}, 7812 }, 7813 { 7814 name: "FlagLT_UGT", 7815 argLen: 0, 7816 reg: regInfo{}, 7817 }, 7818 { 7819 name: "FlagGT_UGT", 7820 argLen: 0, 7821 reg: regInfo{}, 7822 }, 7823 { 7824 name: "FlagGT_ULT", 7825 argLen: 0, 7826 reg: regInfo{}, 7827 }, 7828 { 7829 name: "MOVLatomicload", 7830 auxType: auxSymOff, 7831 argLen: 2, 7832 faultOnNilArg0: true, 7833 symEffect: SymRead, 7834 asm: x86.AMOVL, 7835 reg: regInfo{ 7836 inputs: []inputInfo{ 7837 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7838 }, 7839 outputs: []outputInfo{ 7840 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7841 }, 7842 }, 7843 }, 7844 { 7845 name: "MOVQatomicload", 7846 auxType: auxSymOff, 7847 argLen: 2, 7848 faultOnNilArg0: true, 7849 symEffect: SymRead, 7850 asm: x86.AMOVQ, 7851 reg: regInfo{ 7852 inputs: []inputInfo{ 7853 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7854 }, 7855 outputs: []outputInfo{ 7856 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7857 }, 7858 }, 7859 }, 7860 { 7861 name: "XCHGL", 7862 auxType: auxSymOff, 7863 argLen: 3, 7864 resultInArg0: true, 7865 faultOnNilArg1: true, 7866 hasSideEffects: true, 7867 symEffect: SymRdWr, 7868 asm: x86.AXCHGL, 7869 reg: regInfo{ 7870 inputs: []inputInfo{ 7871 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7872 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7873 }, 7874 outputs: []outputInfo{ 7875 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7876 }, 7877 }, 7878 }, 7879 { 7880 name: "XCHGQ", 7881 auxType: auxSymOff, 7882 argLen: 3, 7883 resultInArg0: true, 7884 faultOnNilArg1: true, 7885 hasSideEffects: true, 7886 symEffect: SymRdWr, 7887 asm: x86.AXCHGQ, 7888 reg: regInfo{ 7889 inputs: []inputInfo{ 7890 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7891 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7892 }, 7893 outputs: []outputInfo{ 7894 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7895 }, 7896 }, 7897 }, 7898 { 7899 name: "XADDLlock", 7900 auxType: auxSymOff, 7901 argLen: 3, 7902 resultInArg0: true, 7903 clobberFlags: true, 7904 faultOnNilArg1: true, 7905 hasSideEffects: true, 7906 symEffect: SymRdWr, 7907 asm: x86.AXADDL, 7908 reg: regInfo{ 7909 inputs: []inputInfo{ 7910 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7911 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7912 }, 7913 outputs: []outputInfo{ 7914 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7915 }, 7916 }, 7917 }, 7918 { 7919 name: "XADDQlock", 7920 auxType: auxSymOff, 7921 argLen: 3, 7922 resultInArg0: true, 7923 clobberFlags: true, 7924 faultOnNilArg1: true, 7925 hasSideEffects: true, 7926 symEffect: SymRdWr, 7927 asm: x86.AXADDQ, 7928 reg: regInfo{ 7929 inputs: []inputInfo{ 7930 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7931 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7932 }, 7933 outputs: []outputInfo{ 7934 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7935 }, 7936 }, 7937 }, 7938 { 7939 name: "AddTupleFirst32", 7940 argLen: 2, 7941 reg: regInfo{}, 7942 }, 7943 { 7944 name: "AddTupleFirst64", 7945 argLen: 2, 7946 reg: regInfo{}, 7947 }, 7948 { 7949 name: "CMPXCHGLlock", 7950 auxType: auxSymOff, 7951 argLen: 4, 7952 clobberFlags: true, 7953 faultOnNilArg0: true, 7954 hasSideEffects: true, 7955 symEffect: SymRdWr, 7956 asm: x86.ACMPXCHGL, 7957 reg: regInfo{ 7958 inputs: []inputInfo{ 7959 {1, 1}, // AX 7960 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7961 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7962 }, 7963 clobbers: 1, // AX 7964 outputs: []outputInfo{ 7965 {1, 0}, 7966 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7967 }, 7968 }, 7969 }, 7970 { 7971 name: "CMPXCHGQlock", 7972 auxType: auxSymOff, 7973 argLen: 4, 7974 clobberFlags: true, 7975 faultOnNilArg0: true, 7976 hasSideEffects: true, 7977 symEffect: SymRdWr, 7978 asm: x86.ACMPXCHGQ, 7979 reg: regInfo{ 7980 inputs: []inputInfo{ 7981 {1, 1}, // AX 7982 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7983 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7984 }, 7985 clobbers: 1, // AX 7986 outputs: []outputInfo{ 7987 {1, 0}, 7988 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7989 }, 7990 }, 7991 }, 7992 { 7993 name: "ANDBlock", 7994 auxType: auxSymOff, 7995 argLen: 3, 7996 clobberFlags: true, 7997 faultOnNilArg0: true, 7998 hasSideEffects: true, 7999 symEffect: SymRdWr, 8000 asm: x86.AANDB, 8001 reg: regInfo{ 8002 inputs: []inputInfo{ 8003 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8004 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8005 }, 8006 }, 8007 }, 8008 { 8009 name: "ORBlock", 8010 auxType: auxSymOff, 8011 argLen: 3, 8012 clobberFlags: true, 8013 faultOnNilArg0: true, 8014 hasSideEffects: true, 8015 symEffect: SymRdWr, 8016 asm: x86.AORB, 8017 reg: regInfo{ 8018 inputs: []inputInfo{ 8019 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8020 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8021 }, 8022 }, 8023 }, 8024 8025 { 8026 name: "ADD", 8027 argLen: 2, 8028 commutative: true, 8029 asm: arm.AADD, 8030 reg: regInfo{ 8031 inputs: []inputInfo{ 8032 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8033 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8034 }, 8035 outputs: []outputInfo{ 8036 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8037 }, 8038 }, 8039 }, 8040 { 8041 name: "ADDconst", 8042 auxType: auxInt32, 8043 argLen: 1, 8044 asm: arm.AADD, 8045 reg: regInfo{ 8046 inputs: []inputInfo{ 8047 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 8048 }, 8049 outputs: []outputInfo{ 8050 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8051 }, 8052 }, 8053 }, 8054 { 8055 name: "SUB", 8056 argLen: 2, 8057 asm: arm.ASUB, 8058 reg: regInfo{ 8059 inputs: []inputInfo{ 8060 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8061 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8062 }, 8063 outputs: []outputInfo{ 8064 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8065 }, 8066 }, 8067 }, 8068 { 8069 name: "SUBconst", 8070 auxType: auxInt32, 8071 argLen: 1, 8072 asm: arm.ASUB, 8073 reg: regInfo{ 8074 inputs: []inputInfo{ 8075 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8076 }, 8077 outputs: []outputInfo{ 8078 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8079 }, 8080 }, 8081 }, 8082 { 8083 name: "RSB", 8084 argLen: 2, 8085 asm: arm.ARSB, 8086 reg: regInfo{ 8087 inputs: []inputInfo{ 8088 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8089 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8090 }, 8091 outputs: []outputInfo{ 8092 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8093 }, 8094 }, 8095 }, 8096 { 8097 name: "RSBconst", 8098 auxType: auxInt32, 8099 argLen: 1, 8100 asm: arm.ARSB, 8101 reg: regInfo{ 8102 inputs: []inputInfo{ 8103 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8104 }, 8105 outputs: []outputInfo{ 8106 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8107 }, 8108 }, 8109 }, 8110 { 8111 name: "MUL", 8112 argLen: 2, 8113 commutative: true, 8114 asm: arm.AMUL, 8115 reg: regInfo{ 8116 inputs: []inputInfo{ 8117 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8118 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8119 }, 8120 outputs: []outputInfo{ 8121 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8122 }, 8123 }, 8124 }, 8125 { 8126 name: "HMUL", 8127 argLen: 2, 8128 commutative: true, 8129 asm: arm.AMULL, 8130 reg: regInfo{ 8131 inputs: []inputInfo{ 8132 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8133 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8134 }, 8135 outputs: []outputInfo{ 8136 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8137 }, 8138 }, 8139 }, 8140 { 8141 name: "HMULU", 8142 argLen: 2, 8143 commutative: true, 8144 asm: arm.AMULLU, 8145 reg: regInfo{ 8146 inputs: []inputInfo{ 8147 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8148 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8149 }, 8150 outputs: []outputInfo{ 8151 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8152 }, 8153 }, 8154 }, 8155 { 8156 name: "CALLudiv", 8157 argLen: 2, 8158 clobberFlags: true, 8159 reg: regInfo{ 8160 inputs: []inputInfo{ 8161 {0, 2}, // R1 8162 {1, 1}, // R0 8163 }, 8164 clobbers: 16396, // R2 R3 R14 8165 outputs: []outputInfo{ 8166 {0, 1}, // R0 8167 {1, 2}, // R1 8168 }, 8169 }, 8170 }, 8171 { 8172 name: "ADDS", 8173 argLen: 2, 8174 commutative: true, 8175 asm: arm.AADD, 8176 reg: regInfo{ 8177 inputs: []inputInfo{ 8178 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8179 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8180 }, 8181 outputs: []outputInfo{ 8182 {1, 0}, 8183 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8184 }, 8185 }, 8186 }, 8187 { 8188 name: "ADDSconst", 8189 auxType: auxInt32, 8190 argLen: 1, 8191 asm: arm.AADD, 8192 reg: regInfo{ 8193 inputs: []inputInfo{ 8194 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8195 }, 8196 outputs: []outputInfo{ 8197 {1, 0}, 8198 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8199 }, 8200 }, 8201 }, 8202 { 8203 name: "ADC", 8204 argLen: 3, 8205 commutative: true, 8206 asm: arm.AADC, 8207 reg: regInfo{ 8208 inputs: []inputInfo{ 8209 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8210 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8211 }, 8212 outputs: []outputInfo{ 8213 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8214 }, 8215 }, 8216 }, 8217 { 8218 name: "ADCconst", 8219 auxType: auxInt32, 8220 argLen: 2, 8221 asm: arm.AADC, 8222 reg: regInfo{ 8223 inputs: []inputInfo{ 8224 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8225 }, 8226 outputs: []outputInfo{ 8227 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8228 }, 8229 }, 8230 }, 8231 { 8232 name: "SUBS", 8233 argLen: 2, 8234 asm: arm.ASUB, 8235 reg: regInfo{ 8236 inputs: []inputInfo{ 8237 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8238 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8239 }, 8240 outputs: []outputInfo{ 8241 {1, 0}, 8242 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8243 }, 8244 }, 8245 }, 8246 { 8247 name: "SUBSconst", 8248 auxType: auxInt32, 8249 argLen: 1, 8250 asm: arm.ASUB, 8251 reg: regInfo{ 8252 inputs: []inputInfo{ 8253 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8254 }, 8255 outputs: []outputInfo{ 8256 {1, 0}, 8257 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8258 }, 8259 }, 8260 }, 8261 { 8262 name: "RSBSconst", 8263 auxType: auxInt32, 8264 argLen: 1, 8265 asm: arm.ARSB, 8266 reg: regInfo{ 8267 inputs: []inputInfo{ 8268 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8269 }, 8270 outputs: []outputInfo{ 8271 {1, 0}, 8272 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8273 }, 8274 }, 8275 }, 8276 { 8277 name: "SBC", 8278 argLen: 3, 8279 asm: arm.ASBC, 8280 reg: regInfo{ 8281 inputs: []inputInfo{ 8282 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8283 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8284 }, 8285 outputs: []outputInfo{ 8286 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8287 }, 8288 }, 8289 }, 8290 { 8291 name: "SBCconst", 8292 auxType: auxInt32, 8293 argLen: 2, 8294 asm: arm.ASBC, 8295 reg: regInfo{ 8296 inputs: []inputInfo{ 8297 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8298 }, 8299 outputs: []outputInfo{ 8300 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8301 }, 8302 }, 8303 }, 8304 { 8305 name: "RSCconst", 8306 auxType: auxInt32, 8307 argLen: 2, 8308 asm: arm.ARSC, 8309 reg: regInfo{ 8310 inputs: []inputInfo{ 8311 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8312 }, 8313 outputs: []outputInfo{ 8314 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8315 }, 8316 }, 8317 }, 8318 { 8319 name: "MULLU", 8320 argLen: 2, 8321 commutative: true, 8322 asm: arm.AMULLU, 8323 reg: regInfo{ 8324 inputs: []inputInfo{ 8325 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8326 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8327 }, 8328 outputs: []outputInfo{ 8329 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8330 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8331 }, 8332 }, 8333 }, 8334 { 8335 name: "MULA", 8336 argLen: 3, 8337 asm: arm.AMULA, 8338 reg: regInfo{ 8339 inputs: []inputInfo{ 8340 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8341 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8342 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8343 }, 8344 outputs: []outputInfo{ 8345 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8346 }, 8347 }, 8348 }, 8349 { 8350 name: "ADDF", 8351 argLen: 2, 8352 commutative: true, 8353 asm: arm.AADDF, 8354 reg: regInfo{ 8355 inputs: []inputInfo{ 8356 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8357 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8358 }, 8359 outputs: []outputInfo{ 8360 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8361 }, 8362 }, 8363 }, 8364 { 8365 name: "ADDD", 8366 argLen: 2, 8367 commutative: true, 8368 asm: arm.AADDD, 8369 reg: regInfo{ 8370 inputs: []inputInfo{ 8371 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8372 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8373 }, 8374 outputs: []outputInfo{ 8375 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8376 }, 8377 }, 8378 }, 8379 { 8380 name: "SUBF", 8381 argLen: 2, 8382 asm: arm.ASUBF, 8383 reg: regInfo{ 8384 inputs: []inputInfo{ 8385 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8386 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8387 }, 8388 outputs: []outputInfo{ 8389 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8390 }, 8391 }, 8392 }, 8393 { 8394 name: "SUBD", 8395 argLen: 2, 8396 asm: arm.ASUBD, 8397 reg: regInfo{ 8398 inputs: []inputInfo{ 8399 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8400 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8401 }, 8402 outputs: []outputInfo{ 8403 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8404 }, 8405 }, 8406 }, 8407 { 8408 name: "MULF", 8409 argLen: 2, 8410 commutative: true, 8411 asm: arm.AMULF, 8412 reg: regInfo{ 8413 inputs: []inputInfo{ 8414 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8415 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8416 }, 8417 outputs: []outputInfo{ 8418 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8419 }, 8420 }, 8421 }, 8422 { 8423 name: "MULD", 8424 argLen: 2, 8425 commutative: true, 8426 asm: arm.AMULD, 8427 reg: regInfo{ 8428 inputs: []inputInfo{ 8429 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8430 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8431 }, 8432 outputs: []outputInfo{ 8433 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8434 }, 8435 }, 8436 }, 8437 { 8438 name: "DIVF", 8439 argLen: 2, 8440 asm: arm.ADIVF, 8441 reg: regInfo{ 8442 inputs: []inputInfo{ 8443 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8444 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8445 }, 8446 outputs: []outputInfo{ 8447 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8448 }, 8449 }, 8450 }, 8451 { 8452 name: "DIVD", 8453 argLen: 2, 8454 asm: arm.ADIVD, 8455 reg: regInfo{ 8456 inputs: []inputInfo{ 8457 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8458 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8459 }, 8460 outputs: []outputInfo{ 8461 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8462 }, 8463 }, 8464 }, 8465 { 8466 name: "AND", 8467 argLen: 2, 8468 commutative: true, 8469 asm: arm.AAND, 8470 reg: regInfo{ 8471 inputs: []inputInfo{ 8472 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8473 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8474 }, 8475 outputs: []outputInfo{ 8476 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8477 }, 8478 }, 8479 }, 8480 { 8481 name: "ANDconst", 8482 auxType: auxInt32, 8483 argLen: 1, 8484 asm: arm.AAND, 8485 reg: regInfo{ 8486 inputs: []inputInfo{ 8487 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8488 }, 8489 outputs: []outputInfo{ 8490 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8491 }, 8492 }, 8493 }, 8494 { 8495 name: "OR", 8496 argLen: 2, 8497 commutative: true, 8498 asm: arm.AORR, 8499 reg: regInfo{ 8500 inputs: []inputInfo{ 8501 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8502 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8503 }, 8504 outputs: []outputInfo{ 8505 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8506 }, 8507 }, 8508 }, 8509 { 8510 name: "ORconst", 8511 auxType: auxInt32, 8512 argLen: 1, 8513 asm: arm.AORR, 8514 reg: regInfo{ 8515 inputs: []inputInfo{ 8516 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8517 }, 8518 outputs: []outputInfo{ 8519 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8520 }, 8521 }, 8522 }, 8523 { 8524 name: "XOR", 8525 argLen: 2, 8526 commutative: true, 8527 asm: arm.AEOR, 8528 reg: regInfo{ 8529 inputs: []inputInfo{ 8530 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8531 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8532 }, 8533 outputs: []outputInfo{ 8534 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8535 }, 8536 }, 8537 }, 8538 { 8539 name: "XORconst", 8540 auxType: auxInt32, 8541 argLen: 1, 8542 asm: arm.AEOR, 8543 reg: regInfo{ 8544 inputs: []inputInfo{ 8545 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8546 }, 8547 outputs: []outputInfo{ 8548 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8549 }, 8550 }, 8551 }, 8552 { 8553 name: "BIC", 8554 argLen: 2, 8555 asm: arm.ABIC, 8556 reg: regInfo{ 8557 inputs: []inputInfo{ 8558 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8559 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8560 }, 8561 outputs: []outputInfo{ 8562 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8563 }, 8564 }, 8565 }, 8566 { 8567 name: "BICconst", 8568 auxType: auxInt32, 8569 argLen: 1, 8570 asm: arm.ABIC, 8571 reg: regInfo{ 8572 inputs: []inputInfo{ 8573 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8574 }, 8575 outputs: []outputInfo{ 8576 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8577 }, 8578 }, 8579 }, 8580 { 8581 name: "MVN", 8582 argLen: 1, 8583 asm: arm.AMVN, 8584 reg: regInfo{ 8585 inputs: []inputInfo{ 8586 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8587 }, 8588 outputs: []outputInfo{ 8589 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8590 }, 8591 }, 8592 }, 8593 { 8594 name: "NEGF", 8595 argLen: 1, 8596 asm: arm.ANEGF, 8597 reg: regInfo{ 8598 inputs: []inputInfo{ 8599 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8600 }, 8601 outputs: []outputInfo{ 8602 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8603 }, 8604 }, 8605 }, 8606 { 8607 name: "NEGD", 8608 argLen: 1, 8609 asm: arm.ANEGD, 8610 reg: regInfo{ 8611 inputs: []inputInfo{ 8612 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8613 }, 8614 outputs: []outputInfo{ 8615 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8616 }, 8617 }, 8618 }, 8619 { 8620 name: "SQRTD", 8621 argLen: 1, 8622 asm: arm.ASQRTD, 8623 reg: regInfo{ 8624 inputs: []inputInfo{ 8625 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8626 }, 8627 outputs: []outputInfo{ 8628 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8629 }, 8630 }, 8631 }, 8632 { 8633 name: "CLZ", 8634 argLen: 1, 8635 asm: arm.ACLZ, 8636 reg: regInfo{ 8637 inputs: []inputInfo{ 8638 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8639 }, 8640 outputs: []outputInfo{ 8641 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8642 }, 8643 }, 8644 }, 8645 { 8646 name: "REV", 8647 argLen: 1, 8648 asm: arm.AREV, 8649 reg: regInfo{ 8650 inputs: []inputInfo{ 8651 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8652 }, 8653 outputs: []outputInfo{ 8654 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8655 }, 8656 }, 8657 }, 8658 { 8659 name: "RBIT", 8660 argLen: 1, 8661 asm: arm.ARBIT, 8662 reg: regInfo{ 8663 inputs: []inputInfo{ 8664 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8665 }, 8666 outputs: []outputInfo{ 8667 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8668 }, 8669 }, 8670 }, 8671 { 8672 name: "SLL", 8673 argLen: 2, 8674 asm: arm.ASLL, 8675 reg: regInfo{ 8676 inputs: []inputInfo{ 8677 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8678 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8679 }, 8680 outputs: []outputInfo{ 8681 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8682 }, 8683 }, 8684 }, 8685 { 8686 name: "SLLconst", 8687 auxType: auxInt32, 8688 argLen: 1, 8689 asm: arm.ASLL, 8690 reg: regInfo{ 8691 inputs: []inputInfo{ 8692 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8693 }, 8694 outputs: []outputInfo{ 8695 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8696 }, 8697 }, 8698 }, 8699 { 8700 name: "SRL", 8701 argLen: 2, 8702 asm: arm.ASRL, 8703 reg: regInfo{ 8704 inputs: []inputInfo{ 8705 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8706 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8707 }, 8708 outputs: []outputInfo{ 8709 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8710 }, 8711 }, 8712 }, 8713 { 8714 name: "SRLconst", 8715 auxType: auxInt32, 8716 argLen: 1, 8717 asm: arm.ASRL, 8718 reg: regInfo{ 8719 inputs: []inputInfo{ 8720 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8721 }, 8722 outputs: []outputInfo{ 8723 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8724 }, 8725 }, 8726 }, 8727 { 8728 name: "SRA", 8729 argLen: 2, 8730 asm: arm.ASRA, 8731 reg: regInfo{ 8732 inputs: []inputInfo{ 8733 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8734 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8735 }, 8736 outputs: []outputInfo{ 8737 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8738 }, 8739 }, 8740 }, 8741 { 8742 name: "SRAconst", 8743 auxType: auxInt32, 8744 argLen: 1, 8745 asm: arm.ASRA, 8746 reg: regInfo{ 8747 inputs: []inputInfo{ 8748 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8749 }, 8750 outputs: []outputInfo{ 8751 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8752 }, 8753 }, 8754 }, 8755 { 8756 name: "SRRconst", 8757 auxType: auxInt32, 8758 argLen: 1, 8759 reg: regInfo{ 8760 inputs: []inputInfo{ 8761 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8762 }, 8763 outputs: []outputInfo{ 8764 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8765 }, 8766 }, 8767 }, 8768 { 8769 name: "ADDshiftLL", 8770 auxType: auxInt32, 8771 argLen: 2, 8772 asm: arm.AADD, 8773 reg: regInfo{ 8774 inputs: []inputInfo{ 8775 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8776 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8777 }, 8778 outputs: []outputInfo{ 8779 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8780 }, 8781 }, 8782 }, 8783 { 8784 name: "ADDshiftRL", 8785 auxType: auxInt32, 8786 argLen: 2, 8787 asm: arm.AADD, 8788 reg: regInfo{ 8789 inputs: []inputInfo{ 8790 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8791 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8792 }, 8793 outputs: []outputInfo{ 8794 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8795 }, 8796 }, 8797 }, 8798 { 8799 name: "ADDshiftRA", 8800 auxType: auxInt32, 8801 argLen: 2, 8802 asm: arm.AADD, 8803 reg: regInfo{ 8804 inputs: []inputInfo{ 8805 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8806 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8807 }, 8808 outputs: []outputInfo{ 8809 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8810 }, 8811 }, 8812 }, 8813 { 8814 name: "SUBshiftLL", 8815 auxType: auxInt32, 8816 argLen: 2, 8817 asm: arm.ASUB, 8818 reg: regInfo{ 8819 inputs: []inputInfo{ 8820 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8821 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8822 }, 8823 outputs: []outputInfo{ 8824 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8825 }, 8826 }, 8827 }, 8828 { 8829 name: "SUBshiftRL", 8830 auxType: auxInt32, 8831 argLen: 2, 8832 asm: arm.ASUB, 8833 reg: regInfo{ 8834 inputs: []inputInfo{ 8835 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8836 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8837 }, 8838 outputs: []outputInfo{ 8839 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8840 }, 8841 }, 8842 }, 8843 { 8844 name: "SUBshiftRA", 8845 auxType: auxInt32, 8846 argLen: 2, 8847 asm: arm.ASUB, 8848 reg: regInfo{ 8849 inputs: []inputInfo{ 8850 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8851 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8852 }, 8853 outputs: []outputInfo{ 8854 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8855 }, 8856 }, 8857 }, 8858 { 8859 name: "RSBshiftLL", 8860 auxType: auxInt32, 8861 argLen: 2, 8862 asm: arm.ARSB, 8863 reg: regInfo{ 8864 inputs: []inputInfo{ 8865 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8866 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8867 }, 8868 outputs: []outputInfo{ 8869 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8870 }, 8871 }, 8872 }, 8873 { 8874 name: "RSBshiftRL", 8875 auxType: auxInt32, 8876 argLen: 2, 8877 asm: arm.ARSB, 8878 reg: regInfo{ 8879 inputs: []inputInfo{ 8880 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8881 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8882 }, 8883 outputs: []outputInfo{ 8884 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8885 }, 8886 }, 8887 }, 8888 { 8889 name: "RSBshiftRA", 8890 auxType: auxInt32, 8891 argLen: 2, 8892 asm: arm.ARSB, 8893 reg: regInfo{ 8894 inputs: []inputInfo{ 8895 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8896 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8897 }, 8898 outputs: []outputInfo{ 8899 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8900 }, 8901 }, 8902 }, 8903 { 8904 name: "ANDshiftLL", 8905 auxType: auxInt32, 8906 argLen: 2, 8907 asm: arm.AAND, 8908 reg: regInfo{ 8909 inputs: []inputInfo{ 8910 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8911 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8912 }, 8913 outputs: []outputInfo{ 8914 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8915 }, 8916 }, 8917 }, 8918 { 8919 name: "ANDshiftRL", 8920 auxType: auxInt32, 8921 argLen: 2, 8922 asm: arm.AAND, 8923 reg: regInfo{ 8924 inputs: []inputInfo{ 8925 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8926 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8927 }, 8928 outputs: []outputInfo{ 8929 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8930 }, 8931 }, 8932 }, 8933 { 8934 name: "ANDshiftRA", 8935 auxType: auxInt32, 8936 argLen: 2, 8937 asm: arm.AAND, 8938 reg: regInfo{ 8939 inputs: []inputInfo{ 8940 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8941 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8942 }, 8943 outputs: []outputInfo{ 8944 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8945 }, 8946 }, 8947 }, 8948 { 8949 name: "ORshiftLL", 8950 auxType: auxInt32, 8951 argLen: 2, 8952 asm: arm.AORR, 8953 reg: regInfo{ 8954 inputs: []inputInfo{ 8955 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8956 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8957 }, 8958 outputs: []outputInfo{ 8959 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8960 }, 8961 }, 8962 }, 8963 { 8964 name: "ORshiftRL", 8965 auxType: auxInt32, 8966 argLen: 2, 8967 asm: arm.AORR, 8968 reg: regInfo{ 8969 inputs: []inputInfo{ 8970 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8971 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8972 }, 8973 outputs: []outputInfo{ 8974 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8975 }, 8976 }, 8977 }, 8978 { 8979 name: "ORshiftRA", 8980 auxType: auxInt32, 8981 argLen: 2, 8982 asm: arm.AORR, 8983 reg: regInfo{ 8984 inputs: []inputInfo{ 8985 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8986 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8987 }, 8988 outputs: []outputInfo{ 8989 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8990 }, 8991 }, 8992 }, 8993 { 8994 name: "XORshiftLL", 8995 auxType: auxInt32, 8996 argLen: 2, 8997 asm: arm.AEOR, 8998 reg: regInfo{ 8999 inputs: []inputInfo{ 9000 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9001 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9002 }, 9003 outputs: []outputInfo{ 9004 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9005 }, 9006 }, 9007 }, 9008 { 9009 name: "XORshiftRL", 9010 auxType: auxInt32, 9011 argLen: 2, 9012 asm: arm.AEOR, 9013 reg: regInfo{ 9014 inputs: []inputInfo{ 9015 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9016 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9017 }, 9018 outputs: []outputInfo{ 9019 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9020 }, 9021 }, 9022 }, 9023 { 9024 name: "XORshiftRA", 9025 auxType: auxInt32, 9026 argLen: 2, 9027 asm: arm.AEOR, 9028 reg: regInfo{ 9029 inputs: []inputInfo{ 9030 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9031 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9032 }, 9033 outputs: []outputInfo{ 9034 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9035 }, 9036 }, 9037 }, 9038 { 9039 name: "XORshiftRR", 9040 auxType: auxInt32, 9041 argLen: 2, 9042 asm: arm.AEOR, 9043 reg: regInfo{ 9044 inputs: []inputInfo{ 9045 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9046 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9047 }, 9048 outputs: []outputInfo{ 9049 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9050 }, 9051 }, 9052 }, 9053 { 9054 name: "BICshiftLL", 9055 auxType: auxInt32, 9056 argLen: 2, 9057 asm: arm.ABIC, 9058 reg: regInfo{ 9059 inputs: []inputInfo{ 9060 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9061 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9062 }, 9063 outputs: []outputInfo{ 9064 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9065 }, 9066 }, 9067 }, 9068 { 9069 name: "BICshiftRL", 9070 auxType: auxInt32, 9071 argLen: 2, 9072 asm: arm.ABIC, 9073 reg: regInfo{ 9074 inputs: []inputInfo{ 9075 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9076 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9077 }, 9078 outputs: []outputInfo{ 9079 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9080 }, 9081 }, 9082 }, 9083 { 9084 name: "BICshiftRA", 9085 auxType: auxInt32, 9086 argLen: 2, 9087 asm: arm.ABIC, 9088 reg: regInfo{ 9089 inputs: []inputInfo{ 9090 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9091 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9092 }, 9093 outputs: []outputInfo{ 9094 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9095 }, 9096 }, 9097 }, 9098 { 9099 name: "MVNshiftLL", 9100 auxType: auxInt32, 9101 argLen: 1, 9102 asm: arm.AMVN, 9103 reg: regInfo{ 9104 inputs: []inputInfo{ 9105 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9106 }, 9107 outputs: []outputInfo{ 9108 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9109 }, 9110 }, 9111 }, 9112 { 9113 name: "MVNshiftRL", 9114 auxType: auxInt32, 9115 argLen: 1, 9116 asm: arm.AMVN, 9117 reg: regInfo{ 9118 inputs: []inputInfo{ 9119 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9120 }, 9121 outputs: []outputInfo{ 9122 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9123 }, 9124 }, 9125 }, 9126 { 9127 name: "MVNshiftRA", 9128 auxType: auxInt32, 9129 argLen: 1, 9130 asm: arm.AMVN, 9131 reg: regInfo{ 9132 inputs: []inputInfo{ 9133 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9134 }, 9135 outputs: []outputInfo{ 9136 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9137 }, 9138 }, 9139 }, 9140 { 9141 name: "ADCshiftLL", 9142 auxType: auxInt32, 9143 argLen: 3, 9144 asm: arm.AADC, 9145 reg: regInfo{ 9146 inputs: []inputInfo{ 9147 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9148 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9149 }, 9150 outputs: []outputInfo{ 9151 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9152 }, 9153 }, 9154 }, 9155 { 9156 name: "ADCshiftRL", 9157 auxType: auxInt32, 9158 argLen: 3, 9159 asm: arm.AADC, 9160 reg: regInfo{ 9161 inputs: []inputInfo{ 9162 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9163 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9164 }, 9165 outputs: []outputInfo{ 9166 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9167 }, 9168 }, 9169 }, 9170 { 9171 name: "ADCshiftRA", 9172 auxType: auxInt32, 9173 argLen: 3, 9174 asm: arm.AADC, 9175 reg: regInfo{ 9176 inputs: []inputInfo{ 9177 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9178 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9179 }, 9180 outputs: []outputInfo{ 9181 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9182 }, 9183 }, 9184 }, 9185 { 9186 name: "SBCshiftLL", 9187 auxType: auxInt32, 9188 argLen: 3, 9189 asm: arm.ASBC, 9190 reg: regInfo{ 9191 inputs: []inputInfo{ 9192 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9193 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9194 }, 9195 outputs: []outputInfo{ 9196 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9197 }, 9198 }, 9199 }, 9200 { 9201 name: "SBCshiftRL", 9202 auxType: auxInt32, 9203 argLen: 3, 9204 asm: arm.ASBC, 9205 reg: regInfo{ 9206 inputs: []inputInfo{ 9207 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9208 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9209 }, 9210 outputs: []outputInfo{ 9211 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9212 }, 9213 }, 9214 }, 9215 { 9216 name: "SBCshiftRA", 9217 auxType: auxInt32, 9218 argLen: 3, 9219 asm: arm.ASBC, 9220 reg: regInfo{ 9221 inputs: []inputInfo{ 9222 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9223 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9224 }, 9225 outputs: []outputInfo{ 9226 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9227 }, 9228 }, 9229 }, 9230 { 9231 name: "RSCshiftLL", 9232 auxType: auxInt32, 9233 argLen: 3, 9234 asm: arm.ARSC, 9235 reg: regInfo{ 9236 inputs: []inputInfo{ 9237 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9238 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9239 }, 9240 outputs: []outputInfo{ 9241 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9242 }, 9243 }, 9244 }, 9245 { 9246 name: "RSCshiftRL", 9247 auxType: auxInt32, 9248 argLen: 3, 9249 asm: arm.ARSC, 9250 reg: regInfo{ 9251 inputs: []inputInfo{ 9252 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9253 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9254 }, 9255 outputs: []outputInfo{ 9256 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9257 }, 9258 }, 9259 }, 9260 { 9261 name: "RSCshiftRA", 9262 auxType: auxInt32, 9263 argLen: 3, 9264 asm: arm.ARSC, 9265 reg: regInfo{ 9266 inputs: []inputInfo{ 9267 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9268 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9269 }, 9270 outputs: []outputInfo{ 9271 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9272 }, 9273 }, 9274 }, 9275 { 9276 name: "ADDSshiftLL", 9277 auxType: auxInt32, 9278 argLen: 2, 9279 asm: arm.AADD, 9280 reg: regInfo{ 9281 inputs: []inputInfo{ 9282 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9283 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9284 }, 9285 outputs: []outputInfo{ 9286 {1, 0}, 9287 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9288 }, 9289 }, 9290 }, 9291 { 9292 name: "ADDSshiftRL", 9293 auxType: auxInt32, 9294 argLen: 2, 9295 asm: arm.AADD, 9296 reg: regInfo{ 9297 inputs: []inputInfo{ 9298 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9299 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9300 }, 9301 outputs: []outputInfo{ 9302 {1, 0}, 9303 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9304 }, 9305 }, 9306 }, 9307 { 9308 name: "ADDSshiftRA", 9309 auxType: auxInt32, 9310 argLen: 2, 9311 asm: arm.AADD, 9312 reg: regInfo{ 9313 inputs: []inputInfo{ 9314 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9315 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9316 }, 9317 outputs: []outputInfo{ 9318 {1, 0}, 9319 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9320 }, 9321 }, 9322 }, 9323 { 9324 name: "SUBSshiftLL", 9325 auxType: auxInt32, 9326 argLen: 2, 9327 asm: arm.ASUB, 9328 reg: regInfo{ 9329 inputs: []inputInfo{ 9330 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9331 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9332 }, 9333 outputs: []outputInfo{ 9334 {1, 0}, 9335 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9336 }, 9337 }, 9338 }, 9339 { 9340 name: "SUBSshiftRL", 9341 auxType: auxInt32, 9342 argLen: 2, 9343 asm: arm.ASUB, 9344 reg: regInfo{ 9345 inputs: []inputInfo{ 9346 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9347 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9348 }, 9349 outputs: []outputInfo{ 9350 {1, 0}, 9351 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9352 }, 9353 }, 9354 }, 9355 { 9356 name: "SUBSshiftRA", 9357 auxType: auxInt32, 9358 argLen: 2, 9359 asm: arm.ASUB, 9360 reg: regInfo{ 9361 inputs: []inputInfo{ 9362 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9363 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9364 }, 9365 outputs: []outputInfo{ 9366 {1, 0}, 9367 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9368 }, 9369 }, 9370 }, 9371 { 9372 name: "RSBSshiftLL", 9373 auxType: auxInt32, 9374 argLen: 2, 9375 asm: arm.ARSB, 9376 reg: regInfo{ 9377 inputs: []inputInfo{ 9378 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9379 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9380 }, 9381 outputs: []outputInfo{ 9382 {1, 0}, 9383 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9384 }, 9385 }, 9386 }, 9387 { 9388 name: "RSBSshiftRL", 9389 auxType: auxInt32, 9390 argLen: 2, 9391 asm: arm.ARSB, 9392 reg: regInfo{ 9393 inputs: []inputInfo{ 9394 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9395 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9396 }, 9397 outputs: []outputInfo{ 9398 {1, 0}, 9399 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9400 }, 9401 }, 9402 }, 9403 { 9404 name: "RSBSshiftRA", 9405 auxType: auxInt32, 9406 argLen: 2, 9407 asm: arm.ARSB, 9408 reg: regInfo{ 9409 inputs: []inputInfo{ 9410 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9411 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9412 }, 9413 outputs: []outputInfo{ 9414 {1, 0}, 9415 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9416 }, 9417 }, 9418 }, 9419 { 9420 name: "ADDshiftLLreg", 9421 argLen: 3, 9422 asm: arm.AADD, 9423 reg: regInfo{ 9424 inputs: []inputInfo{ 9425 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9426 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9427 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9428 }, 9429 outputs: []outputInfo{ 9430 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9431 }, 9432 }, 9433 }, 9434 { 9435 name: "ADDshiftRLreg", 9436 argLen: 3, 9437 asm: arm.AADD, 9438 reg: regInfo{ 9439 inputs: []inputInfo{ 9440 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9441 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9442 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9443 }, 9444 outputs: []outputInfo{ 9445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9446 }, 9447 }, 9448 }, 9449 { 9450 name: "ADDshiftRAreg", 9451 argLen: 3, 9452 asm: arm.AADD, 9453 reg: regInfo{ 9454 inputs: []inputInfo{ 9455 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9456 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9457 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9458 }, 9459 outputs: []outputInfo{ 9460 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9461 }, 9462 }, 9463 }, 9464 { 9465 name: "SUBshiftLLreg", 9466 argLen: 3, 9467 asm: arm.ASUB, 9468 reg: regInfo{ 9469 inputs: []inputInfo{ 9470 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9471 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9472 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9473 }, 9474 outputs: []outputInfo{ 9475 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9476 }, 9477 }, 9478 }, 9479 { 9480 name: "SUBshiftRLreg", 9481 argLen: 3, 9482 asm: arm.ASUB, 9483 reg: regInfo{ 9484 inputs: []inputInfo{ 9485 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9486 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9487 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9488 }, 9489 outputs: []outputInfo{ 9490 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9491 }, 9492 }, 9493 }, 9494 { 9495 name: "SUBshiftRAreg", 9496 argLen: 3, 9497 asm: arm.ASUB, 9498 reg: regInfo{ 9499 inputs: []inputInfo{ 9500 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9501 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9502 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9503 }, 9504 outputs: []outputInfo{ 9505 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9506 }, 9507 }, 9508 }, 9509 { 9510 name: "RSBshiftLLreg", 9511 argLen: 3, 9512 asm: arm.ARSB, 9513 reg: regInfo{ 9514 inputs: []inputInfo{ 9515 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9516 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9517 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9518 }, 9519 outputs: []outputInfo{ 9520 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9521 }, 9522 }, 9523 }, 9524 { 9525 name: "RSBshiftRLreg", 9526 argLen: 3, 9527 asm: arm.ARSB, 9528 reg: regInfo{ 9529 inputs: []inputInfo{ 9530 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9531 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9532 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9533 }, 9534 outputs: []outputInfo{ 9535 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9536 }, 9537 }, 9538 }, 9539 { 9540 name: "RSBshiftRAreg", 9541 argLen: 3, 9542 asm: arm.ARSB, 9543 reg: regInfo{ 9544 inputs: []inputInfo{ 9545 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9546 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9547 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9548 }, 9549 outputs: []outputInfo{ 9550 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9551 }, 9552 }, 9553 }, 9554 { 9555 name: "ANDshiftLLreg", 9556 argLen: 3, 9557 asm: arm.AAND, 9558 reg: regInfo{ 9559 inputs: []inputInfo{ 9560 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9561 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9562 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9563 }, 9564 outputs: []outputInfo{ 9565 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9566 }, 9567 }, 9568 }, 9569 { 9570 name: "ANDshiftRLreg", 9571 argLen: 3, 9572 asm: arm.AAND, 9573 reg: regInfo{ 9574 inputs: []inputInfo{ 9575 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9576 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9577 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9578 }, 9579 outputs: []outputInfo{ 9580 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9581 }, 9582 }, 9583 }, 9584 { 9585 name: "ANDshiftRAreg", 9586 argLen: 3, 9587 asm: arm.AAND, 9588 reg: regInfo{ 9589 inputs: []inputInfo{ 9590 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9591 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9592 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9593 }, 9594 outputs: []outputInfo{ 9595 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9596 }, 9597 }, 9598 }, 9599 { 9600 name: "ORshiftLLreg", 9601 argLen: 3, 9602 asm: arm.AORR, 9603 reg: regInfo{ 9604 inputs: []inputInfo{ 9605 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9606 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9607 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9608 }, 9609 outputs: []outputInfo{ 9610 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9611 }, 9612 }, 9613 }, 9614 { 9615 name: "ORshiftRLreg", 9616 argLen: 3, 9617 asm: arm.AORR, 9618 reg: regInfo{ 9619 inputs: []inputInfo{ 9620 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9621 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9622 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9623 }, 9624 outputs: []outputInfo{ 9625 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9626 }, 9627 }, 9628 }, 9629 { 9630 name: "ORshiftRAreg", 9631 argLen: 3, 9632 asm: arm.AORR, 9633 reg: regInfo{ 9634 inputs: []inputInfo{ 9635 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9636 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9637 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9638 }, 9639 outputs: []outputInfo{ 9640 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9641 }, 9642 }, 9643 }, 9644 { 9645 name: "XORshiftLLreg", 9646 argLen: 3, 9647 asm: arm.AEOR, 9648 reg: regInfo{ 9649 inputs: []inputInfo{ 9650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9651 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9652 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9653 }, 9654 outputs: []outputInfo{ 9655 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9656 }, 9657 }, 9658 }, 9659 { 9660 name: "XORshiftRLreg", 9661 argLen: 3, 9662 asm: arm.AEOR, 9663 reg: regInfo{ 9664 inputs: []inputInfo{ 9665 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9666 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9667 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9668 }, 9669 outputs: []outputInfo{ 9670 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9671 }, 9672 }, 9673 }, 9674 { 9675 name: "XORshiftRAreg", 9676 argLen: 3, 9677 asm: arm.AEOR, 9678 reg: regInfo{ 9679 inputs: []inputInfo{ 9680 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9681 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9682 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9683 }, 9684 outputs: []outputInfo{ 9685 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9686 }, 9687 }, 9688 }, 9689 { 9690 name: "BICshiftLLreg", 9691 argLen: 3, 9692 asm: arm.ABIC, 9693 reg: regInfo{ 9694 inputs: []inputInfo{ 9695 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9696 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9697 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9698 }, 9699 outputs: []outputInfo{ 9700 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9701 }, 9702 }, 9703 }, 9704 { 9705 name: "BICshiftRLreg", 9706 argLen: 3, 9707 asm: arm.ABIC, 9708 reg: regInfo{ 9709 inputs: []inputInfo{ 9710 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9711 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9712 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9713 }, 9714 outputs: []outputInfo{ 9715 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9716 }, 9717 }, 9718 }, 9719 { 9720 name: "BICshiftRAreg", 9721 argLen: 3, 9722 asm: arm.ABIC, 9723 reg: regInfo{ 9724 inputs: []inputInfo{ 9725 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9726 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9727 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9728 }, 9729 outputs: []outputInfo{ 9730 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9731 }, 9732 }, 9733 }, 9734 { 9735 name: "MVNshiftLLreg", 9736 argLen: 2, 9737 asm: arm.AMVN, 9738 reg: regInfo{ 9739 inputs: []inputInfo{ 9740 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9741 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9742 }, 9743 outputs: []outputInfo{ 9744 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9745 }, 9746 }, 9747 }, 9748 { 9749 name: "MVNshiftRLreg", 9750 argLen: 2, 9751 asm: arm.AMVN, 9752 reg: regInfo{ 9753 inputs: []inputInfo{ 9754 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9755 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9756 }, 9757 outputs: []outputInfo{ 9758 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9759 }, 9760 }, 9761 }, 9762 { 9763 name: "MVNshiftRAreg", 9764 argLen: 2, 9765 asm: arm.AMVN, 9766 reg: regInfo{ 9767 inputs: []inputInfo{ 9768 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9769 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9770 }, 9771 outputs: []outputInfo{ 9772 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9773 }, 9774 }, 9775 }, 9776 { 9777 name: "ADCshiftLLreg", 9778 argLen: 4, 9779 asm: arm.AADC, 9780 reg: regInfo{ 9781 inputs: []inputInfo{ 9782 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9783 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9784 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9785 }, 9786 outputs: []outputInfo{ 9787 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9788 }, 9789 }, 9790 }, 9791 { 9792 name: "ADCshiftRLreg", 9793 argLen: 4, 9794 asm: arm.AADC, 9795 reg: regInfo{ 9796 inputs: []inputInfo{ 9797 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9798 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9799 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9800 }, 9801 outputs: []outputInfo{ 9802 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9803 }, 9804 }, 9805 }, 9806 { 9807 name: "ADCshiftRAreg", 9808 argLen: 4, 9809 asm: arm.AADC, 9810 reg: regInfo{ 9811 inputs: []inputInfo{ 9812 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9813 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9814 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9815 }, 9816 outputs: []outputInfo{ 9817 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9818 }, 9819 }, 9820 }, 9821 { 9822 name: "SBCshiftLLreg", 9823 argLen: 4, 9824 asm: arm.ASBC, 9825 reg: regInfo{ 9826 inputs: []inputInfo{ 9827 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9828 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9829 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9830 }, 9831 outputs: []outputInfo{ 9832 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9833 }, 9834 }, 9835 }, 9836 { 9837 name: "SBCshiftRLreg", 9838 argLen: 4, 9839 asm: arm.ASBC, 9840 reg: regInfo{ 9841 inputs: []inputInfo{ 9842 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9843 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9844 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9845 }, 9846 outputs: []outputInfo{ 9847 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9848 }, 9849 }, 9850 }, 9851 { 9852 name: "SBCshiftRAreg", 9853 argLen: 4, 9854 asm: arm.ASBC, 9855 reg: regInfo{ 9856 inputs: []inputInfo{ 9857 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9858 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9859 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9860 }, 9861 outputs: []outputInfo{ 9862 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9863 }, 9864 }, 9865 }, 9866 { 9867 name: "RSCshiftLLreg", 9868 argLen: 4, 9869 asm: arm.ARSC, 9870 reg: regInfo{ 9871 inputs: []inputInfo{ 9872 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9873 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9874 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9875 }, 9876 outputs: []outputInfo{ 9877 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9878 }, 9879 }, 9880 }, 9881 { 9882 name: "RSCshiftRLreg", 9883 argLen: 4, 9884 asm: arm.ARSC, 9885 reg: regInfo{ 9886 inputs: []inputInfo{ 9887 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9888 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9889 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9890 }, 9891 outputs: []outputInfo{ 9892 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9893 }, 9894 }, 9895 }, 9896 { 9897 name: "RSCshiftRAreg", 9898 argLen: 4, 9899 asm: arm.ARSC, 9900 reg: regInfo{ 9901 inputs: []inputInfo{ 9902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9903 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9904 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9905 }, 9906 outputs: []outputInfo{ 9907 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9908 }, 9909 }, 9910 }, 9911 { 9912 name: "ADDSshiftLLreg", 9913 argLen: 3, 9914 asm: arm.AADD, 9915 reg: regInfo{ 9916 inputs: []inputInfo{ 9917 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9918 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9919 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9920 }, 9921 outputs: []outputInfo{ 9922 {1, 0}, 9923 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9924 }, 9925 }, 9926 }, 9927 { 9928 name: "ADDSshiftRLreg", 9929 argLen: 3, 9930 asm: arm.AADD, 9931 reg: regInfo{ 9932 inputs: []inputInfo{ 9933 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9934 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9935 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9936 }, 9937 outputs: []outputInfo{ 9938 {1, 0}, 9939 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9940 }, 9941 }, 9942 }, 9943 { 9944 name: "ADDSshiftRAreg", 9945 argLen: 3, 9946 asm: arm.AADD, 9947 reg: regInfo{ 9948 inputs: []inputInfo{ 9949 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9950 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9951 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9952 }, 9953 outputs: []outputInfo{ 9954 {1, 0}, 9955 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9956 }, 9957 }, 9958 }, 9959 { 9960 name: "SUBSshiftLLreg", 9961 argLen: 3, 9962 asm: arm.ASUB, 9963 reg: regInfo{ 9964 inputs: []inputInfo{ 9965 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9966 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9967 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9968 }, 9969 outputs: []outputInfo{ 9970 {1, 0}, 9971 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9972 }, 9973 }, 9974 }, 9975 { 9976 name: "SUBSshiftRLreg", 9977 argLen: 3, 9978 asm: arm.ASUB, 9979 reg: regInfo{ 9980 inputs: []inputInfo{ 9981 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9982 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9983 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9984 }, 9985 outputs: []outputInfo{ 9986 {1, 0}, 9987 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9988 }, 9989 }, 9990 }, 9991 { 9992 name: "SUBSshiftRAreg", 9993 argLen: 3, 9994 asm: arm.ASUB, 9995 reg: regInfo{ 9996 inputs: []inputInfo{ 9997 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9998 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9999 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10000 }, 10001 outputs: []outputInfo{ 10002 {1, 0}, 10003 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10004 }, 10005 }, 10006 }, 10007 { 10008 name: "RSBSshiftLLreg", 10009 argLen: 3, 10010 asm: arm.ARSB, 10011 reg: regInfo{ 10012 inputs: []inputInfo{ 10013 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10014 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10015 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10016 }, 10017 outputs: []outputInfo{ 10018 {1, 0}, 10019 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10020 }, 10021 }, 10022 }, 10023 { 10024 name: "RSBSshiftRLreg", 10025 argLen: 3, 10026 asm: arm.ARSB, 10027 reg: regInfo{ 10028 inputs: []inputInfo{ 10029 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10030 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10031 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10032 }, 10033 outputs: []outputInfo{ 10034 {1, 0}, 10035 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10036 }, 10037 }, 10038 }, 10039 { 10040 name: "RSBSshiftRAreg", 10041 argLen: 3, 10042 asm: arm.ARSB, 10043 reg: regInfo{ 10044 inputs: []inputInfo{ 10045 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10046 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10047 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10048 }, 10049 outputs: []outputInfo{ 10050 {1, 0}, 10051 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10052 }, 10053 }, 10054 }, 10055 { 10056 name: "CMP", 10057 argLen: 2, 10058 asm: arm.ACMP, 10059 reg: regInfo{ 10060 inputs: []inputInfo{ 10061 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10062 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10063 }, 10064 }, 10065 }, 10066 { 10067 name: "CMPconst", 10068 auxType: auxInt32, 10069 argLen: 1, 10070 asm: arm.ACMP, 10071 reg: regInfo{ 10072 inputs: []inputInfo{ 10073 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10074 }, 10075 }, 10076 }, 10077 { 10078 name: "CMN", 10079 argLen: 2, 10080 asm: arm.ACMN, 10081 reg: regInfo{ 10082 inputs: []inputInfo{ 10083 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10084 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10085 }, 10086 }, 10087 }, 10088 { 10089 name: "CMNconst", 10090 auxType: auxInt32, 10091 argLen: 1, 10092 asm: arm.ACMN, 10093 reg: regInfo{ 10094 inputs: []inputInfo{ 10095 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10096 }, 10097 }, 10098 }, 10099 { 10100 name: "TST", 10101 argLen: 2, 10102 commutative: true, 10103 asm: arm.ATST, 10104 reg: regInfo{ 10105 inputs: []inputInfo{ 10106 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10107 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10108 }, 10109 }, 10110 }, 10111 { 10112 name: "TSTconst", 10113 auxType: auxInt32, 10114 argLen: 1, 10115 asm: arm.ATST, 10116 reg: regInfo{ 10117 inputs: []inputInfo{ 10118 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10119 }, 10120 }, 10121 }, 10122 { 10123 name: "TEQ", 10124 argLen: 2, 10125 commutative: true, 10126 asm: arm.ATEQ, 10127 reg: regInfo{ 10128 inputs: []inputInfo{ 10129 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10130 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10131 }, 10132 }, 10133 }, 10134 { 10135 name: "TEQconst", 10136 auxType: auxInt32, 10137 argLen: 1, 10138 asm: arm.ATEQ, 10139 reg: regInfo{ 10140 inputs: []inputInfo{ 10141 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10142 }, 10143 }, 10144 }, 10145 { 10146 name: "CMPF", 10147 argLen: 2, 10148 asm: arm.ACMPF, 10149 reg: regInfo{ 10150 inputs: []inputInfo{ 10151 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10152 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10153 }, 10154 }, 10155 }, 10156 { 10157 name: "CMPD", 10158 argLen: 2, 10159 asm: arm.ACMPD, 10160 reg: regInfo{ 10161 inputs: []inputInfo{ 10162 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10163 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10164 }, 10165 }, 10166 }, 10167 { 10168 name: "CMPshiftLL", 10169 auxType: auxInt32, 10170 argLen: 2, 10171 asm: arm.ACMP, 10172 reg: regInfo{ 10173 inputs: []inputInfo{ 10174 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10175 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10176 }, 10177 }, 10178 }, 10179 { 10180 name: "CMPshiftRL", 10181 auxType: auxInt32, 10182 argLen: 2, 10183 asm: arm.ACMP, 10184 reg: regInfo{ 10185 inputs: []inputInfo{ 10186 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10187 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10188 }, 10189 }, 10190 }, 10191 { 10192 name: "CMPshiftRA", 10193 auxType: auxInt32, 10194 argLen: 2, 10195 asm: arm.ACMP, 10196 reg: regInfo{ 10197 inputs: []inputInfo{ 10198 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10199 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10200 }, 10201 }, 10202 }, 10203 { 10204 name: "CMPshiftLLreg", 10205 argLen: 3, 10206 asm: arm.ACMP, 10207 reg: regInfo{ 10208 inputs: []inputInfo{ 10209 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10210 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10211 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10212 }, 10213 }, 10214 }, 10215 { 10216 name: "CMPshiftRLreg", 10217 argLen: 3, 10218 asm: arm.ACMP, 10219 reg: regInfo{ 10220 inputs: []inputInfo{ 10221 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10222 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10223 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10224 }, 10225 }, 10226 }, 10227 { 10228 name: "CMPshiftRAreg", 10229 argLen: 3, 10230 asm: arm.ACMP, 10231 reg: regInfo{ 10232 inputs: []inputInfo{ 10233 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10234 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10235 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10236 }, 10237 }, 10238 }, 10239 { 10240 name: "CMPF0", 10241 argLen: 1, 10242 asm: arm.ACMPF, 10243 reg: regInfo{ 10244 inputs: []inputInfo{ 10245 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10246 }, 10247 }, 10248 }, 10249 { 10250 name: "CMPD0", 10251 argLen: 1, 10252 asm: arm.ACMPD, 10253 reg: regInfo{ 10254 inputs: []inputInfo{ 10255 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10256 }, 10257 }, 10258 }, 10259 { 10260 name: "MOVWconst", 10261 auxType: auxInt32, 10262 argLen: 0, 10263 rematerializeable: true, 10264 asm: arm.AMOVW, 10265 reg: regInfo{ 10266 outputs: []outputInfo{ 10267 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10268 }, 10269 }, 10270 }, 10271 { 10272 name: "MOVFconst", 10273 auxType: auxFloat64, 10274 argLen: 0, 10275 rematerializeable: true, 10276 asm: arm.AMOVF, 10277 reg: regInfo{ 10278 outputs: []outputInfo{ 10279 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10280 }, 10281 }, 10282 }, 10283 { 10284 name: "MOVDconst", 10285 auxType: auxFloat64, 10286 argLen: 0, 10287 rematerializeable: true, 10288 asm: arm.AMOVD, 10289 reg: regInfo{ 10290 outputs: []outputInfo{ 10291 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10292 }, 10293 }, 10294 }, 10295 { 10296 name: "MOVWaddr", 10297 auxType: auxSymOff, 10298 argLen: 1, 10299 rematerializeable: true, 10300 symEffect: SymAddr, 10301 asm: arm.AMOVW, 10302 reg: regInfo{ 10303 inputs: []inputInfo{ 10304 {0, 4294975488}, // SP SB 10305 }, 10306 outputs: []outputInfo{ 10307 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10308 }, 10309 }, 10310 }, 10311 { 10312 name: "MOVBload", 10313 auxType: auxSymOff, 10314 argLen: 2, 10315 faultOnNilArg0: true, 10316 symEffect: SymRead, 10317 asm: arm.AMOVB, 10318 reg: regInfo{ 10319 inputs: []inputInfo{ 10320 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10321 }, 10322 outputs: []outputInfo{ 10323 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10324 }, 10325 }, 10326 }, 10327 { 10328 name: "MOVBUload", 10329 auxType: auxSymOff, 10330 argLen: 2, 10331 faultOnNilArg0: true, 10332 symEffect: SymRead, 10333 asm: arm.AMOVBU, 10334 reg: regInfo{ 10335 inputs: []inputInfo{ 10336 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10337 }, 10338 outputs: []outputInfo{ 10339 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10340 }, 10341 }, 10342 }, 10343 { 10344 name: "MOVHload", 10345 auxType: auxSymOff, 10346 argLen: 2, 10347 faultOnNilArg0: true, 10348 symEffect: SymRead, 10349 asm: arm.AMOVH, 10350 reg: regInfo{ 10351 inputs: []inputInfo{ 10352 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10353 }, 10354 outputs: []outputInfo{ 10355 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10356 }, 10357 }, 10358 }, 10359 { 10360 name: "MOVHUload", 10361 auxType: auxSymOff, 10362 argLen: 2, 10363 faultOnNilArg0: true, 10364 symEffect: SymRead, 10365 asm: arm.AMOVHU, 10366 reg: regInfo{ 10367 inputs: []inputInfo{ 10368 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10369 }, 10370 outputs: []outputInfo{ 10371 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10372 }, 10373 }, 10374 }, 10375 { 10376 name: "MOVWload", 10377 auxType: auxSymOff, 10378 argLen: 2, 10379 faultOnNilArg0: true, 10380 symEffect: SymRead, 10381 asm: arm.AMOVW, 10382 reg: regInfo{ 10383 inputs: []inputInfo{ 10384 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10385 }, 10386 outputs: []outputInfo{ 10387 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10388 }, 10389 }, 10390 }, 10391 { 10392 name: "MOVFload", 10393 auxType: auxSymOff, 10394 argLen: 2, 10395 faultOnNilArg0: true, 10396 symEffect: SymRead, 10397 asm: arm.AMOVF, 10398 reg: regInfo{ 10399 inputs: []inputInfo{ 10400 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10401 }, 10402 outputs: []outputInfo{ 10403 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10404 }, 10405 }, 10406 }, 10407 { 10408 name: "MOVDload", 10409 auxType: auxSymOff, 10410 argLen: 2, 10411 faultOnNilArg0: true, 10412 symEffect: SymRead, 10413 asm: arm.AMOVD, 10414 reg: regInfo{ 10415 inputs: []inputInfo{ 10416 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10417 }, 10418 outputs: []outputInfo{ 10419 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10420 }, 10421 }, 10422 }, 10423 { 10424 name: "MOVBstore", 10425 auxType: auxSymOff, 10426 argLen: 3, 10427 faultOnNilArg0: true, 10428 symEffect: SymWrite, 10429 asm: arm.AMOVB, 10430 reg: regInfo{ 10431 inputs: []inputInfo{ 10432 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10433 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10434 }, 10435 }, 10436 }, 10437 { 10438 name: "MOVHstore", 10439 auxType: auxSymOff, 10440 argLen: 3, 10441 faultOnNilArg0: true, 10442 symEffect: SymWrite, 10443 asm: arm.AMOVH, 10444 reg: regInfo{ 10445 inputs: []inputInfo{ 10446 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10447 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10448 }, 10449 }, 10450 }, 10451 { 10452 name: "MOVWstore", 10453 auxType: auxSymOff, 10454 argLen: 3, 10455 faultOnNilArg0: true, 10456 symEffect: SymWrite, 10457 asm: arm.AMOVW, 10458 reg: regInfo{ 10459 inputs: []inputInfo{ 10460 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10461 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10462 }, 10463 }, 10464 }, 10465 { 10466 name: "MOVFstore", 10467 auxType: auxSymOff, 10468 argLen: 3, 10469 faultOnNilArg0: true, 10470 symEffect: SymWrite, 10471 asm: arm.AMOVF, 10472 reg: regInfo{ 10473 inputs: []inputInfo{ 10474 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10475 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10476 }, 10477 }, 10478 }, 10479 { 10480 name: "MOVDstore", 10481 auxType: auxSymOff, 10482 argLen: 3, 10483 faultOnNilArg0: true, 10484 symEffect: SymWrite, 10485 asm: arm.AMOVD, 10486 reg: regInfo{ 10487 inputs: []inputInfo{ 10488 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10489 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10490 }, 10491 }, 10492 }, 10493 { 10494 name: "MOVWloadidx", 10495 argLen: 3, 10496 asm: arm.AMOVW, 10497 reg: regInfo{ 10498 inputs: []inputInfo{ 10499 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10500 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10501 }, 10502 outputs: []outputInfo{ 10503 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10504 }, 10505 }, 10506 }, 10507 { 10508 name: "MOVWloadshiftLL", 10509 auxType: auxInt32, 10510 argLen: 3, 10511 asm: arm.AMOVW, 10512 reg: regInfo{ 10513 inputs: []inputInfo{ 10514 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10515 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10516 }, 10517 outputs: []outputInfo{ 10518 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10519 }, 10520 }, 10521 }, 10522 { 10523 name: "MOVWloadshiftRL", 10524 auxType: auxInt32, 10525 argLen: 3, 10526 asm: arm.AMOVW, 10527 reg: regInfo{ 10528 inputs: []inputInfo{ 10529 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10530 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10531 }, 10532 outputs: []outputInfo{ 10533 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10534 }, 10535 }, 10536 }, 10537 { 10538 name: "MOVWloadshiftRA", 10539 auxType: auxInt32, 10540 argLen: 3, 10541 asm: arm.AMOVW, 10542 reg: regInfo{ 10543 inputs: []inputInfo{ 10544 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10545 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10546 }, 10547 outputs: []outputInfo{ 10548 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10549 }, 10550 }, 10551 }, 10552 { 10553 name: "MOVWstoreidx", 10554 argLen: 4, 10555 asm: arm.AMOVW, 10556 reg: regInfo{ 10557 inputs: []inputInfo{ 10558 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10559 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10560 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10561 }, 10562 }, 10563 }, 10564 { 10565 name: "MOVWstoreshiftLL", 10566 auxType: auxInt32, 10567 argLen: 4, 10568 asm: arm.AMOVW, 10569 reg: regInfo{ 10570 inputs: []inputInfo{ 10571 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10572 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10573 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10574 }, 10575 }, 10576 }, 10577 { 10578 name: "MOVWstoreshiftRL", 10579 auxType: auxInt32, 10580 argLen: 4, 10581 asm: arm.AMOVW, 10582 reg: regInfo{ 10583 inputs: []inputInfo{ 10584 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10585 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10586 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10587 }, 10588 }, 10589 }, 10590 { 10591 name: "MOVWstoreshiftRA", 10592 auxType: auxInt32, 10593 argLen: 4, 10594 asm: arm.AMOVW, 10595 reg: regInfo{ 10596 inputs: []inputInfo{ 10597 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10598 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10599 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10600 }, 10601 }, 10602 }, 10603 { 10604 name: "MOVBreg", 10605 argLen: 1, 10606 asm: arm.AMOVBS, 10607 reg: regInfo{ 10608 inputs: []inputInfo{ 10609 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10610 }, 10611 outputs: []outputInfo{ 10612 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10613 }, 10614 }, 10615 }, 10616 { 10617 name: "MOVBUreg", 10618 argLen: 1, 10619 asm: arm.AMOVBU, 10620 reg: regInfo{ 10621 inputs: []inputInfo{ 10622 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10623 }, 10624 outputs: []outputInfo{ 10625 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10626 }, 10627 }, 10628 }, 10629 { 10630 name: "MOVHreg", 10631 argLen: 1, 10632 asm: arm.AMOVHS, 10633 reg: regInfo{ 10634 inputs: []inputInfo{ 10635 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10636 }, 10637 outputs: []outputInfo{ 10638 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10639 }, 10640 }, 10641 }, 10642 { 10643 name: "MOVHUreg", 10644 argLen: 1, 10645 asm: arm.AMOVHU, 10646 reg: regInfo{ 10647 inputs: []inputInfo{ 10648 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10649 }, 10650 outputs: []outputInfo{ 10651 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10652 }, 10653 }, 10654 }, 10655 { 10656 name: "MOVWreg", 10657 argLen: 1, 10658 asm: arm.AMOVW, 10659 reg: regInfo{ 10660 inputs: []inputInfo{ 10661 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10662 }, 10663 outputs: []outputInfo{ 10664 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10665 }, 10666 }, 10667 }, 10668 { 10669 name: "MOVWnop", 10670 argLen: 1, 10671 resultInArg0: true, 10672 reg: regInfo{ 10673 inputs: []inputInfo{ 10674 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10675 }, 10676 outputs: []outputInfo{ 10677 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10678 }, 10679 }, 10680 }, 10681 { 10682 name: "MOVWF", 10683 argLen: 1, 10684 asm: arm.AMOVWF, 10685 reg: regInfo{ 10686 inputs: []inputInfo{ 10687 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10688 }, 10689 clobbers: 2147483648, // F15 10690 outputs: []outputInfo{ 10691 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10692 }, 10693 }, 10694 }, 10695 { 10696 name: "MOVWD", 10697 argLen: 1, 10698 asm: arm.AMOVWD, 10699 reg: regInfo{ 10700 inputs: []inputInfo{ 10701 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10702 }, 10703 clobbers: 2147483648, // F15 10704 outputs: []outputInfo{ 10705 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10706 }, 10707 }, 10708 }, 10709 { 10710 name: "MOVWUF", 10711 argLen: 1, 10712 asm: arm.AMOVWF, 10713 reg: regInfo{ 10714 inputs: []inputInfo{ 10715 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10716 }, 10717 clobbers: 2147483648, // F15 10718 outputs: []outputInfo{ 10719 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10720 }, 10721 }, 10722 }, 10723 { 10724 name: "MOVWUD", 10725 argLen: 1, 10726 asm: arm.AMOVWD, 10727 reg: regInfo{ 10728 inputs: []inputInfo{ 10729 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10730 }, 10731 clobbers: 2147483648, // F15 10732 outputs: []outputInfo{ 10733 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10734 }, 10735 }, 10736 }, 10737 { 10738 name: "MOVFW", 10739 argLen: 1, 10740 asm: arm.AMOVFW, 10741 reg: regInfo{ 10742 inputs: []inputInfo{ 10743 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10744 }, 10745 clobbers: 2147483648, // F15 10746 outputs: []outputInfo{ 10747 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10748 }, 10749 }, 10750 }, 10751 { 10752 name: "MOVDW", 10753 argLen: 1, 10754 asm: arm.AMOVDW, 10755 reg: regInfo{ 10756 inputs: []inputInfo{ 10757 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10758 }, 10759 clobbers: 2147483648, // F15 10760 outputs: []outputInfo{ 10761 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10762 }, 10763 }, 10764 }, 10765 { 10766 name: "MOVFWU", 10767 argLen: 1, 10768 asm: arm.AMOVFW, 10769 reg: regInfo{ 10770 inputs: []inputInfo{ 10771 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10772 }, 10773 clobbers: 2147483648, // F15 10774 outputs: []outputInfo{ 10775 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10776 }, 10777 }, 10778 }, 10779 { 10780 name: "MOVDWU", 10781 argLen: 1, 10782 asm: arm.AMOVDW, 10783 reg: regInfo{ 10784 inputs: []inputInfo{ 10785 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10786 }, 10787 clobbers: 2147483648, // F15 10788 outputs: []outputInfo{ 10789 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10790 }, 10791 }, 10792 }, 10793 { 10794 name: "MOVFD", 10795 argLen: 1, 10796 asm: arm.AMOVFD, 10797 reg: regInfo{ 10798 inputs: []inputInfo{ 10799 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10800 }, 10801 outputs: []outputInfo{ 10802 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10803 }, 10804 }, 10805 }, 10806 { 10807 name: "MOVDF", 10808 argLen: 1, 10809 asm: arm.AMOVDF, 10810 reg: regInfo{ 10811 inputs: []inputInfo{ 10812 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10813 }, 10814 outputs: []outputInfo{ 10815 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10816 }, 10817 }, 10818 }, 10819 { 10820 name: "CMOVWHSconst", 10821 auxType: auxInt32, 10822 argLen: 2, 10823 resultInArg0: true, 10824 asm: arm.AMOVW, 10825 reg: regInfo{ 10826 inputs: []inputInfo{ 10827 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10828 }, 10829 outputs: []outputInfo{ 10830 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10831 }, 10832 }, 10833 }, 10834 { 10835 name: "CMOVWLSconst", 10836 auxType: auxInt32, 10837 argLen: 2, 10838 resultInArg0: true, 10839 asm: arm.AMOVW, 10840 reg: regInfo{ 10841 inputs: []inputInfo{ 10842 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10843 }, 10844 outputs: []outputInfo{ 10845 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10846 }, 10847 }, 10848 }, 10849 { 10850 name: "SRAcond", 10851 argLen: 3, 10852 asm: arm.ASRA, 10853 reg: regInfo{ 10854 inputs: []inputInfo{ 10855 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10856 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10857 }, 10858 outputs: []outputInfo{ 10859 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10860 }, 10861 }, 10862 }, 10863 { 10864 name: "CALLstatic", 10865 auxType: auxSymOff, 10866 argLen: 1, 10867 clobberFlags: true, 10868 call: true, 10869 symEffect: SymNone, 10870 reg: regInfo{ 10871 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10872 }, 10873 }, 10874 { 10875 name: "CALLclosure", 10876 auxType: auxInt64, 10877 argLen: 3, 10878 clobberFlags: true, 10879 call: true, 10880 reg: regInfo{ 10881 inputs: []inputInfo{ 10882 {1, 128}, // R7 10883 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 10884 }, 10885 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10886 }, 10887 }, 10888 { 10889 name: "CALLinter", 10890 auxType: auxInt64, 10891 argLen: 2, 10892 clobberFlags: true, 10893 call: true, 10894 reg: regInfo{ 10895 inputs: []inputInfo{ 10896 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10897 }, 10898 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10899 }, 10900 }, 10901 { 10902 name: "LoweredNilCheck", 10903 argLen: 2, 10904 nilCheck: true, 10905 faultOnNilArg0: true, 10906 reg: regInfo{ 10907 inputs: []inputInfo{ 10908 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10909 }, 10910 }, 10911 }, 10912 { 10913 name: "Equal", 10914 argLen: 1, 10915 reg: regInfo{ 10916 outputs: []outputInfo{ 10917 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10918 }, 10919 }, 10920 }, 10921 { 10922 name: "NotEqual", 10923 argLen: 1, 10924 reg: regInfo{ 10925 outputs: []outputInfo{ 10926 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10927 }, 10928 }, 10929 }, 10930 { 10931 name: "LessThan", 10932 argLen: 1, 10933 reg: regInfo{ 10934 outputs: []outputInfo{ 10935 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10936 }, 10937 }, 10938 }, 10939 { 10940 name: "LessEqual", 10941 argLen: 1, 10942 reg: regInfo{ 10943 outputs: []outputInfo{ 10944 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10945 }, 10946 }, 10947 }, 10948 { 10949 name: "GreaterThan", 10950 argLen: 1, 10951 reg: regInfo{ 10952 outputs: []outputInfo{ 10953 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10954 }, 10955 }, 10956 }, 10957 { 10958 name: "GreaterEqual", 10959 argLen: 1, 10960 reg: regInfo{ 10961 outputs: []outputInfo{ 10962 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10963 }, 10964 }, 10965 }, 10966 { 10967 name: "LessThanU", 10968 argLen: 1, 10969 reg: regInfo{ 10970 outputs: []outputInfo{ 10971 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10972 }, 10973 }, 10974 }, 10975 { 10976 name: "LessEqualU", 10977 argLen: 1, 10978 reg: regInfo{ 10979 outputs: []outputInfo{ 10980 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10981 }, 10982 }, 10983 }, 10984 { 10985 name: "GreaterThanU", 10986 argLen: 1, 10987 reg: regInfo{ 10988 outputs: []outputInfo{ 10989 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10990 }, 10991 }, 10992 }, 10993 { 10994 name: "GreaterEqualU", 10995 argLen: 1, 10996 reg: regInfo{ 10997 outputs: []outputInfo{ 10998 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10999 }, 11000 }, 11001 }, 11002 { 11003 name: "DUFFZERO", 11004 auxType: auxInt64, 11005 argLen: 3, 11006 faultOnNilArg0: true, 11007 reg: regInfo{ 11008 inputs: []inputInfo{ 11009 {0, 2}, // R1 11010 {1, 1}, // R0 11011 }, 11012 clobbers: 16386, // R1 R14 11013 }, 11014 }, 11015 { 11016 name: "DUFFCOPY", 11017 auxType: auxInt64, 11018 argLen: 3, 11019 faultOnNilArg0: true, 11020 faultOnNilArg1: true, 11021 reg: regInfo{ 11022 inputs: []inputInfo{ 11023 {0, 4}, // R2 11024 {1, 2}, // R1 11025 }, 11026 clobbers: 16391, // R0 R1 R2 R14 11027 }, 11028 }, 11029 { 11030 name: "LoweredZero", 11031 auxType: auxInt64, 11032 argLen: 4, 11033 clobberFlags: true, 11034 faultOnNilArg0: true, 11035 reg: regInfo{ 11036 inputs: []inputInfo{ 11037 {0, 2}, // R1 11038 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11039 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11040 }, 11041 clobbers: 2, // R1 11042 }, 11043 }, 11044 { 11045 name: "LoweredMove", 11046 auxType: auxInt64, 11047 argLen: 4, 11048 clobberFlags: true, 11049 faultOnNilArg0: true, 11050 faultOnNilArg1: true, 11051 reg: regInfo{ 11052 inputs: []inputInfo{ 11053 {0, 4}, // R2 11054 {1, 2}, // R1 11055 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11056 }, 11057 clobbers: 6, // R1 R2 11058 }, 11059 }, 11060 { 11061 name: "LoweredGetClosurePtr", 11062 argLen: 0, 11063 reg: regInfo{ 11064 outputs: []outputInfo{ 11065 {0, 128}, // R7 11066 }, 11067 }, 11068 }, 11069 { 11070 name: "MOVWconvert", 11071 argLen: 2, 11072 asm: arm.AMOVW, 11073 reg: regInfo{ 11074 inputs: []inputInfo{ 11075 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11076 }, 11077 outputs: []outputInfo{ 11078 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11079 }, 11080 }, 11081 }, 11082 { 11083 name: "FlagEQ", 11084 argLen: 0, 11085 reg: regInfo{}, 11086 }, 11087 { 11088 name: "FlagLT_ULT", 11089 argLen: 0, 11090 reg: regInfo{}, 11091 }, 11092 { 11093 name: "FlagLT_UGT", 11094 argLen: 0, 11095 reg: regInfo{}, 11096 }, 11097 { 11098 name: "FlagGT_UGT", 11099 argLen: 0, 11100 reg: regInfo{}, 11101 }, 11102 { 11103 name: "FlagGT_ULT", 11104 argLen: 0, 11105 reg: regInfo{}, 11106 }, 11107 { 11108 name: "InvertFlags", 11109 argLen: 1, 11110 reg: regInfo{}, 11111 }, 11112 11113 { 11114 name: "ADD", 11115 argLen: 2, 11116 commutative: true, 11117 asm: arm64.AADD, 11118 reg: regInfo{ 11119 inputs: []inputInfo{ 11120 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11121 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11122 }, 11123 outputs: []outputInfo{ 11124 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11125 }, 11126 }, 11127 }, 11128 { 11129 name: "ADDconst", 11130 auxType: auxInt64, 11131 argLen: 1, 11132 asm: arm64.AADD, 11133 reg: regInfo{ 11134 inputs: []inputInfo{ 11135 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 11136 }, 11137 outputs: []outputInfo{ 11138 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11139 }, 11140 }, 11141 }, 11142 { 11143 name: "SUB", 11144 argLen: 2, 11145 asm: arm64.ASUB, 11146 reg: regInfo{ 11147 inputs: []inputInfo{ 11148 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11149 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11150 }, 11151 outputs: []outputInfo{ 11152 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11153 }, 11154 }, 11155 }, 11156 { 11157 name: "SUBconst", 11158 auxType: auxInt64, 11159 argLen: 1, 11160 asm: arm64.ASUB, 11161 reg: regInfo{ 11162 inputs: []inputInfo{ 11163 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11164 }, 11165 outputs: []outputInfo{ 11166 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11167 }, 11168 }, 11169 }, 11170 { 11171 name: "MUL", 11172 argLen: 2, 11173 commutative: true, 11174 asm: arm64.AMUL, 11175 reg: regInfo{ 11176 inputs: []inputInfo{ 11177 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11178 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11179 }, 11180 outputs: []outputInfo{ 11181 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11182 }, 11183 }, 11184 }, 11185 { 11186 name: "MULW", 11187 argLen: 2, 11188 commutative: true, 11189 asm: arm64.AMULW, 11190 reg: regInfo{ 11191 inputs: []inputInfo{ 11192 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11193 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11194 }, 11195 outputs: []outputInfo{ 11196 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11197 }, 11198 }, 11199 }, 11200 { 11201 name: "MULH", 11202 argLen: 2, 11203 commutative: true, 11204 asm: arm64.ASMULH, 11205 reg: regInfo{ 11206 inputs: []inputInfo{ 11207 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11208 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11209 }, 11210 outputs: []outputInfo{ 11211 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11212 }, 11213 }, 11214 }, 11215 { 11216 name: "UMULH", 11217 argLen: 2, 11218 commutative: true, 11219 asm: arm64.AUMULH, 11220 reg: regInfo{ 11221 inputs: []inputInfo{ 11222 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11223 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11224 }, 11225 outputs: []outputInfo{ 11226 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11227 }, 11228 }, 11229 }, 11230 { 11231 name: "MULL", 11232 argLen: 2, 11233 commutative: true, 11234 asm: arm64.ASMULL, 11235 reg: regInfo{ 11236 inputs: []inputInfo{ 11237 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11238 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11239 }, 11240 outputs: []outputInfo{ 11241 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11242 }, 11243 }, 11244 }, 11245 { 11246 name: "UMULL", 11247 argLen: 2, 11248 commutative: true, 11249 asm: arm64.AUMULL, 11250 reg: regInfo{ 11251 inputs: []inputInfo{ 11252 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11253 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11254 }, 11255 outputs: []outputInfo{ 11256 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11257 }, 11258 }, 11259 }, 11260 { 11261 name: "DIV", 11262 argLen: 2, 11263 asm: arm64.ASDIV, 11264 reg: regInfo{ 11265 inputs: []inputInfo{ 11266 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11267 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11268 }, 11269 outputs: []outputInfo{ 11270 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11271 }, 11272 }, 11273 }, 11274 { 11275 name: "UDIV", 11276 argLen: 2, 11277 asm: arm64.AUDIV, 11278 reg: regInfo{ 11279 inputs: []inputInfo{ 11280 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11281 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11282 }, 11283 outputs: []outputInfo{ 11284 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11285 }, 11286 }, 11287 }, 11288 { 11289 name: "DIVW", 11290 argLen: 2, 11291 asm: arm64.ASDIVW, 11292 reg: regInfo{ 11293 inputs: []inputInfo{ 11294 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11295 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11296 }, 11297 outputs: []outputInfo{ 11298 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11299 }, 11300 }, 11301 }, 11302 { 11303 name: "UDIVW", 11304 argLen: 2, 11305 asm: arm64.AUDIVW, 11306 reg: regInfo{ 11307 inputs: []inputInfo{ 11308 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11309 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11310 }, 11311 outputs: []outputInfo{ 11312 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11313 }, 11314 }, 11315 }, 11316 { 11317 name: "MOD", 11318 argLen: 2, 11319 asm: arm64.AREM, 11320 reg: regInfo{ 11321 inputs: []inputInfo{ 11322 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11323 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11324 }, 11325 outputs: []outputInfo{ 11326 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11327 }, 11328 }, 11329 }, 11330 { 11331 name: "UMOD", 11332 argLen: 2, 11333 asm: arm64.AUREM, 11334 reg: regInfo{ 11335 inputs: []inputInfo{ 11336 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11337 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11338 }, 11339 outputs: []outputInfo{ 11340 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11341 }, 11342 }, 11343 }, 11344 { 11345 name: "MODW", 11346 argLen: 2, 11347 asm: arm64.AREMW, 11348 reg: regInfo{ 11349 inputs: []inputInfo{ 11350 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11351 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11352 }, 11353 outputs: []outputInfo{ 11354 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11355 }, 11356 }, 11357 }, 11358 { 11359 name: "UMODW", 11360 argLen: 2, 11361 asm: arm64.AUREMW, 11362 reg: regInfo{ 11363 inputs: []inputInfo{ 11364 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11365 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11366 }, 11367 outputs: []outputInfo{ 11368 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11369 }, 11370 }, 11371 }, 11372 { 11373 name: "FADDS", 11374 argLen: 2, 11375 commutative: true, 11376 asm: arm64.AFADDS, 11377 reg: regInfo{ 11378 inputs: []inputInfo{ 11379 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11380 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11381 }, 11382 outputs: []outputInfo{ 11383 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11384 }, 11385 }, 11386 }, 11387 { 11388 name: "FADDD", 11389 argLen: 2, 11390 commutative: true, 11391 asm: arm64.AFADDD, 11392 reg: regInfo{ 11393 inputs: []inputInfo{ 11394 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11395 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11396 }, 11397 outputs: []outputInfo{ 11398 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11399 }, 11400 }, 11401 }, 11402 { 11403 name: "FSUBS", 11404 argLen: 2, 11405 asm: arm64.AFSUBS, 11406 reg: regInfo{ 11407 inputs: []inputInfo{ 11408 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11409 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11410 }, 11411 outputs: []outputInfo{ 11412 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11413 }, 11414 }, 11415 }, 11416 { 11417 name: "FSUBD", 11418 argLen: 2, 11419 asm: arm64.AFSUBD, 11420 reg: regInfo{ 11421 inputs: []inputInfo{ 11422 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11423 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11424 }, 11425 outputs: []outputInfo{ 11426 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11427 }, 11428 }, 11429 }, 11430 { 11431 name: "FMULS", 11432 argLen: 2, 11433 commutative: true, 11434 asm: arm64.AFMULS, 11435 reg: regInfo{ 11436 inputs: []inputInfo{ 11437 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11438 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11439 }, 11440 outputs: []outputInfo{ 11441 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11442 }, 11443 }, 11444 }, 11445 { 11446 name: "FMULD", 11447 argLen: 2, 11448 commutative: true, 11449 asm: arm64.AFMULD, 11450 reg: regInfo{ 11451 inputs: []inputInfo{ 11452 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11453 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11454 }, 11455 outputs: []outputInfo{ 11456 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11457 }, 11458 }, 11459 }, 11460 { 11461 name: "FDIVS", 11462 argLen: 2, 11463 asm: arm64.AFDIVS, 11464 reg: regInfo{ 11465 inputs: []inputInfo{ 11466 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11467 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11468 }, 11469 outputs: []outputInfo{ 11470 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11471 }, 11472 }, 11473 }, 11474 { 11475 name: "FDIVD", 11476 argLen: 2, 11477 asm: arm64.AFDIVD, 11478 reg: regInfo{ 11479 inputs: []inputInfo{ 11480 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11481 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11482 }, 11483 outputs: []outputInfo{ 11484 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11485 }, 11486 }, 11487 }, 11488 { 11489 name: "AND", 11490 argLen: 2, 11491 commutative: true, 11492 asm: arm64.AAND, 11493 reg: regInfo{ 11494 inputs: []inputInfo{ 11495 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11496 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11497 }, 11498 outputs: []outputInfo{ 11499 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11500 }, 11501 }, 11502 }, 11503 { 11504 name: "ANDconst", 11505 auxType: auxInt64, 11506 argLen: 1, 11507 asm: arm64.AAND, 11508 reg: regInfo{ 11509 inputs: []inputInfo{ 11510 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11511 }, 11512 outputs: []outputInfo{ 11513 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11514 }, 11515 }, 11516 }, 11517 { 11518 name: "OR", 11519 argLen: 2, 11520 commutative: true, 11521 asm: arm64.AORR, 11522 reg: regInfo{ 11523 inputs: []inputInfo{ 11524 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11525 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11526 }, 11527 outputs: []outputInfo{ 11528 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11529 }, 11530 }, 11531 }, 11532 { 11533 name: "ORconst", 11534 auxType: auxInt64, 11535 argLen: 1, 11536 asm: arm64.AORR, 11537 reg: regInfo{ 11538 inputs: []inputInfo{ 11539 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11540 }, 11541 outputs: []outputInfo{ 11542 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11543 }, 11544 }, 11545 }, 11546 { 11547 name: "XOR", 11548 argLen: 2, 11549 commutative: true, 11550 asm: arm64.AEOR, 11551 reg: regInfo{ 11552 inputs: []inputInfo{ 11553 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11554 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11555 }, 11556 outputs: []outputInfo{ 11557 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11558 }, 11559 }, 11560 }, 11561 { 11562 name: "XORconst", 11563 auxType: auxInt64, 11564 argLen: 1, 11565 asm: arm64.AEOR, 11566 reg: regInfo{ 11567 inputs: []inputInfo{ 11568 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11569 }, 11570 outputs: []outputInfo{ 11571 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11572 }, 11573 }, 11574 }, 11575 { 11576 name: "BIC", 11577 argLen: 2, 11578 asm: arm64.ABIC, 11579 reg: regInfo{ 11580 inputs: []inputInfo{ 11581 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11582 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11583 }, 11584 outputs: []outputInfo{ 11585 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11586 }, 11587 }, 11588 }, 11589 { 11590 name: "BICconst", 11591 auxType: auxInt64, 11592 argLen: 1, 11593 asm: arm64.ABIC, 11594 reg: regInfo{ 11595 inputs: []inputInfo{ 11596 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11597 }, 11598 outputs: []outputInfo{ 11599 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11600 }, 11601 }, 11602 }, 11603 { 11604 name: "MVN", 11605 argLen: 1, 11606 asm: arm64.AMVN, 11607 reg: regInfo{ 11608 inputs: []inputInfo{ 11609 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11610 }, 11611 outputs: []outputInfo{ 11612 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11613 }, 11614 }, 11615 }, 11616 { 11617 name: "NEG", 11618 argLen: 1, 11619 asm: arm64.ANEG, 11620 reg: regInfo{ 11621 inputs: []inputInfo{ 11622 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11623 }, 11624 outputs: []outputInfo{ 11625 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11626 }, 11627 }, 11628 }, 11629 { 11630 name: "FNEGS", 11631 argLen: 1, 11632 asm: arm64.AFNEGS, 11633 reg: regInfo{ 11634 inputs: []inputInfo{ 11635 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11636 }, 11637 outputs: []outputInfo{ 11638 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11639 }, 11640 }, 11641 }, 11642 { 11643 name: "FNEGD", 11644 argLen: 1, 11645 asm: arm64.AFNEGD, 11646 reg: regInfo{ 11647 inputs: []inputInfo{ 11648 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11649 }, 11650 outputs: []outputInfo{ 11651 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11652 }, 11653 }, 11654 }, 11655 { 11656 name: "FSQRTD", 11657 argLen: 1, 11658 asm: arm64.AFSQRTD, 11659 reg: regInfo{ 11660 inputs: []inputInfo{ 11661 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11662 }, 11663 outputs: []outputInfo{ 11664 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11665 }, 11666 }, 11667 }, 11668 { 11669 name: "REV", 11670 argLen: 1, 11671 asm: arm64.AREV, 11672 reg: regInfo{ 11673 inputs: []inputInfo{ 11674 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11675 }, 11676 outputs: []outputInfo{ 11677 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11678 }, 11679 }, 11680 }, 11681 { 11682 name: "REVW", 11683 argLen: 1, 11684 asm: arm64.AREVW, 11685 reg: regInfo{ 11686 inputs: []inputInfo{ 11687 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11688 }, 11689 outputs: []outputInfo{ 11690 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11691 }, 11692 }, 11693 }, 11694 { 11695 name: "REV16W", 11696 argLen: 1, 11697 asm: arm64.AREV16W, 11698 reg: regInfo{ 11699 inputs: []inputInfo{ 11700 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11701 }, 11702 outputs: []outputInfo{ 11703 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11704 }, 11705 }, 11706 }, 11707 { 11708 name: "RBIT", 11709 argLen: 1, 11710 asm: arm64.ARBIT, 11711 reg: regInfo{ 11712 inputs: []inputInfo{ 11713 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11714 }, 11715 outputs: []outputInfo{ 11716 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11717 }, 11718 }, 11719 }, 11720 { 11721 name: "RBITW", 11722 argLen: 1, 11723 asm: arm64.ARBITW, 11724 reg: regInfo{ 11725 inputs: []inputInfo{ 11726 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11727 }, 11728 outputs: []outputInfo{ 11729 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11730 }, 11731 }, 11732 }, 11733 { 11734 name: "CLZ", 11735 argLen: 1, 11736 asm: arm64.ACLZ, 11737 reg: regInfo{ 11738 inputs: []inputInfo{ 11739 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11740 }, 11741 outputs: []outputInfo{ 11742 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11743 }, 11744 }, 11745 }, 11746 { 11747 name: "CLZW", 11748 argLen: 1, 11749 asm: arm64.ACLZW, 11750 reg: regInfo{ 11751 inputs: []inputInfo{ 11752 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11753 }, 11754 outputs: []outputInfo{ 11755 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11756 }, 11757 }, 11758 }, 11759 { 11760 name: "SLL", 11761 argLen: 2, 11762 asm: arm64.ALSL, 11763 reg: regInfo{ 11764 inputs: []inputInfo{ 11765 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11766 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11767 }, 11768 outputs: []outputInfo{ 11769 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11770 }, 11771 }, 11772 }, 11773 { 11774 name: "SLLconst", 11775 auxType: auxInt64, 11776 argLen: 1, 11777 asm: arm64.ALSL, 11778 reg: regInfo{ 11779 inputs: []inputInfo{ 11780 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11781 }, 11782 outputs: []outputInfo{ 11783 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11784 }, 11785 }, 11786 }, 11787 { 11788 name: "SRL", 11789 argLen: 2, 11790 asm: arm64.ALSR, 11791 reg: regInfo{ 11792 inputs: []inputInfo{ 11793 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11794 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11795 }, 11796 outputs: []outputInfo{ 11797 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11798 }, 11799 }, 11800 }, 11801 { 11802 name: "SRLconst", 11803 auxType: auxInt64, 11804 argLen: 1, 11805 asm: arm64.ALSR, 11806 reg: regInfo{ 11807 inputs: []inputInfo{ 11808 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11809 }, 11810 outputs: []outputInfo{ 11811 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11812 }, 11813 }, 11814 }, 11815 { 11816 name: "SRA", 11817 argLen: 2, 11818 asm: arm64.AASR, 11819 reg: regInfo{ 11820 inputs: []inputInfo{ 11821 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11822 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11823 }, 11824 outputs: []outputInfo{ 11825 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11826 }, 11827 }, 11828 }, 11829 { 11830 name: "SRAconst", 11831 auxType: auxInt64, 11832 argLen: 1, 11833 asm: arm64.AASR, 11834 reg: regInfo{ 11835 inputs: []inputInfo{ 11836 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11837 }, 11838 outputs: []outputInfo{ 11839 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11840 }, 11841 }, 11842 }, 11843 { 11844 name: "RORconst", 11845 auxType: auxInt64, 11846 argLen: 1, 11847 asm: arm64.AROR, 11848 reg: regInfo{ 11849 inputs: []inputInfo{ 11850 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11851 }, 11852 outputs: []outputInfo{ 11853 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11854 }, 11855 }, 11856 }, 11857 { 11858 name: "RORWconst", 11859 auxType: auxInt64, 11860 argLen: 1, 11861 asm: arm64.ARORW, 11862 reg: regInfo{ 11863 inputs: []inputInfo{ 11864 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11865 }, 11866 outputs: []outputInfo{ 11867 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11868 }, 11869 }, 11870 }, 11871 { 11872 name: "CMP", 11873 argLen: 2, 11874 asm: arm64.ACMP, 11875 reg: regInfo{ 11876 inputs: []inputInfo{ 11877 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11878 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11879 }, 11880 }, 11881 }, 11882 { 11883 name: "CMPconst", 11884 auxType: auxInt64, 11885 argLen: 1, 11886 asm: arm64.ACMP, 11887 reg: regInfo{ 11888 inputs: []inputInfo{ 11889 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11890 }, 11891 }, 11892 }, 11893 { 11894 name: "CMPW", 11895 argLen: 2, 11896 asm: arm64.ACMPW, 11897 reg: regInfo{ 11898 inputs: []inputInfo{ 11899 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11900 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11901 }, 11902 }, 11903 }, 11904 { 11905 name: "CMPWconst", 11906 auxType: auxInt32, 11907 argLen: 1, 11908 asm: arm64.ACMPW, 11909 reg: regInfo{ 11910 inputs: []inputInfo{ 11911 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11912 }, 11913 }, 11914 }, 11915 { 11916 name: "CMN", 11917 argLen: 2, 11918 asm: arm64.ACMN, 11919 reg: regInfo{ 11920 inputs: []inputInfo{ 11921 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11922 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11923 }, 11924 }, 11925 }, 11926 { 11927 name: "CMNconst", 11928 auxType: auxInt64, 11929 argLen: 1, 11930 asm: arm64.ACMN, 11931 reg: regInfo{ 11932 inputs: []inputInfo{ 11933 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11934 }, 11935 }, 11936 }, 11937 { 11938 name: "CMNW", 11939 argLen: 2, 11940 asm: arm64.ACMNW, 11941 reg: regInfo{ 11942 inputs: []inputInfo{ 11943 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11944 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11945 }, 11946 }, 11947 }, 11948 { 11949 name: "CMNWconst", 11950 auxType: auxInt32, 11951 argLen: 1, 11952 asm: arm64.ACMNW, 11953 reg: regInfo{ 11954 inputs: []inputInfo{ 11955 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11956 }, 11957 }, 11958 }, 11959 { 11960 name: "FCMPS", 11961 argLen: 2, 11962 asm: arm64.AFCMPS, 11963 reg: regInfo{ 11964 inputs: []inputInfo{ 11965 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11966 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11967 }, 11968 }, 11969 }, 11970 { 11971 name: "FCMPD", 11972 argLen: 2, 11973 asm: arm64.AFCMPD, 11974 reg: regInfo{ 11975 inputs: []inputInfo{ 11976 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11977 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11978 }, 11979 }, 11980 }, 11981 { 11982 name: "ADDshiftLL", 11983 auxType: auxInt64, 11984 argLen: 2, 11985 asm: arm64.AADD, 11986 reg: regInfo{ 11987 inputs: []inputInfo{ 11988 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11989 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11990 }, 11991 outputs: []outputInfo{ 11992 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11993 }, 11994 }, 11995 }, 11996 { 11997 name: "ADDshiftRL", 11998 auxType: auxInt64, 11999 argLen: 2, 12000 asm: arm64.AADD, 12001 reg: regInfo{ 12002 inputs: []inputInfo{ 12003 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12004 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12005 }, 12006 outputs: []outputInfo{ 12007 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12008 }, 12009 }, 12010 }, 12011 { 12012 name: "ADDshiftRA", 12013 auxType: auxInt64, 12014 argLen: 2, 12015 asm: arm64.AADD, 12016 reg: regInfo{ 12017 inputs: []inputInfo{ 12018 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12019 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12020 }, 12021 outputs: []outputInfo{ 12022 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12023 }, 12024 }, 12025 }, 12026 { 12027 name: "SUBshiftLL", 12028 auxType: auxInt64, 12029 argLen: 2, 12030 asm: arm64.ASUB, 12031 reg: regInfo{ 12032 inputs: []inputInfo{ 12033 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12034 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12035 }, 12036 outputs: []outputInfo{ 12037 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12038 }, 12039 }, 12040 }, 12041 { 12042 name: "SUBshiftRL", 12043 auxType: auxInt64, 12044 argLen: 2, 12045 asm: arm64.ASUB, 12046 reg: regInfo{ 12047 inputs: []inputInfo{ 12048 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12049 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12050 }, 12051 outputs: []outputInfo{ 12052 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12053 }, 12054 }, 12055 }, 12056 { 12057 name: "SUBshiftRA", 12058 auxType: auxInt64, 12059 argLen: 2, 12060 asm: arm64.ASUB, 12061 reg: regInfo{ 12062 inputs: []inputInfo{ 12063 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12064 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12065 }, 12066 outputs: []outputInfo{ 12067 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12068 }, 12069 }, 12070 }, 12071 { 12072 name: "ANDshiftLL", 12073 auxType: auxInt64, 12074 argLen: 2, 12075 asm: arm64.AAND, 12076 reg: regInfo{ 12077 inputs: []inputInfo{ 12078 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12079 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12080 }, 12081 outputs: []outputInfo{ 12082 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12083 }, 12084 }, 12085 }, 12086 { 12087 name: "ANDshiftRL", 12088 auxType: auxInt64, 12089 argLen: 2, 12090 asm: arm64.AAND, 12091 reg: regInfo{ 12092 inputs: []inputInfo{ 12093 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12094 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12095 }, 12096 outputs: []outputInfo{ 12097 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12098 }, 12099 }, 12100 }, 12101 { 12102 name: "ANDshiftRA", 12103 auxType: auxInt64, 12104 argLen: 2, 12105 asm: arm64.AAND, 12106 reg: regInfo{ 12107 inputs: []inputInfo{ 12108 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12109 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12110 }, 12111 outputs: []outputInfo{ 12112 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12113 }, 12114 }, 12115 }, 12116 { 12117 name: "ORshiftLL", 12118 auxType: auxInt64, 12119 argLen: 2, 12120 asm: arm64.AORR, 12121 reg: regInfo{ 12122 inputs: []inputInfo{ 12123 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12124 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12125 }, 12126 outputs: []outputInfo{ 12127 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12128 }, 12129 }, 12130 }, 12131 { 12132 name: "ORshiftRL", 12133 auxType: auxInt64, 12134 argLen: 2, 12135 asm: arm64.AORR, 12136 reg: regInfo{ 12137 inputs: []inputInfo{ 12138 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12139 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12140 }, 12141 outputs: []outputInfo{ 12142 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12143 }, 12144 }, 12145 }, 12146 { 12147 name: "ORshiftRA", 12148 auxType: auxInt64, 12149 argLen: 2, 12150 asm: arm64.AORR, 12151 reg: regInfo{ 12152 inputs: []inputInfo{ 12153 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12154 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12155 }, 12156 outputs: []outputInfo{ 12157 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12158 }, 12159 }, 12160 }, 12161 { 12162 name: "XORshiftLL", 12163 auxType: auxInt64, 12164 argLen: 2, 12165 asm: arm64.AEOR, 12166 reg: regInfo{ 12167 inputs: []inputInfo{ 12168 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12169 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12170 }, 12171 outputs: []outputInfo{ 12172 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12173 }, 12174 }, 12175 }, 12176 { 12177 name: "XORshiftRL", 12178 auxType: auxInt64, 12179 argLen: 2, 12180 asm: arm64.AEOR, 12181 reg: regInfo{ 12182 inputs: []inputInfo{ 12183 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12184 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12185 }, 12186 outputs: []outputInfo{ 12187 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12188 }, 12189 }, 12190 }, 12191 { 12192 name: "XORshiftRA", 12193 auxType: auxInt64, 12194 argLen: 2, 12195 asm: arm64.AEOR, 12196 reg: regInfo{ 12197 inputs: []inputInfo{ 12198 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12199 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12200 }, 12201 outputs: []outputInfo{ 12202 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12203 }, 12204 }, 12205 }, 12206 { 12207 name: "BICshiftLL", 12208 auxType: auxInt64, 12209 argLen: 2, 12210 asm: arm64.ABIC, 12211 reg: regInfo{ 12212 inputs: []inputInfo{ 12213 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12214 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12215 }, 12216 outputs: []outputInfo{ 12217 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12218 }, 12219 }, 12220 }, 12221 { 12222 name: "BICshiftRL", 12223 auxType: auxInt64, 12224 argLen: 2, 12225 asm: arm64.ABIC, 12226 reg: regInfo{ 12227 inputs: []inputInfo{ 12228 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12229 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12230 }, 12231 outputs: []outputInfo{ 12232 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12233 }, 12234 }, 12235 }, 12236 { 12237 name: "BICshiftRA", 12238 auxType: auxInt64, 12239 argLen: 2, 12240 asm: arm64.ABIC, 12241 reg: regInfo{ 12242 inputs: []inputInfo{ 12243 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12244 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12245 }, 12246 outputs: []outputInfo{ 12247 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12248 }, 12249 }, 12250 }, 12251 { 12252 name: "CMPshiftLL", 12253 auxType: auxInt64, 12254 argLen: 2, 12255 asm: arm64.ACMP, 12256 reg: regInfo{ 12257 inputs: []inputInfo{ 12258 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12259 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12260 }, 12261 }, 12262 }, 12263 { 12264 name: "CMPshiftRL", 12265 auxType: auxInt64, 12266 argLen: 2, 12267 asm: arm64.ACMP, 12268 reg: regInfo{ 12269 inputs: []inputInfo{ 12270 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12271 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12272 }, 12273 }, 12274 }, 12275 { 12276 name: "CMPshiftRA", 12277 auxType: auxInt64, 12278 argLen: 2, 12279 asm: arm64.ACMP, 12280 reg: regInfo{ 12281 inputs: []inputInfo{ 12282 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12283 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12284 }, 12285 }, 12286 }, 12287 { 12288 name: "MOVDconst", 12289 auxType: auxInt64, 12290 argLen: 0, 12291 rematerializeable: true, 12292 asm: arm64.AMOVD, 12293 reg: regInfo{ 12294 outputs: []outputInfo{ 12295 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12296 }, 12297 }, 12298 }, 12299 { 12300 name: "FMOVSconst", 12301 auxType: auxFloat64, 12302 argLen: 0, 12303 rematerializeable: true, 12304 asm: arm64.AFMOVS, 12305 reg: regInfo{ 12306 outputs: []outputInfo{ 12307 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12308 }, 12309 }, 12310 }, 12311 { 12312 name: "FMOVDconst", 12313 auxType: auxFloat64, 12314 argLen: 0, 12315 rematerializeable: true, 12316 asm: arm64.AFMOVD, 12317 reg: regInfo{ 12318 outputs: []outputInfo{ 12319 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12320 }, 12321 }, 12322 }, 12323 { 12324 name: "MOVDaddr", 12325 auxType: auxSymOff, 12326 argLen: 1, 12327 rematerializeable: true, 12328 symEffect: SymAddr, 12329 asm: arm64.AMOVD, 12330 reg: regInfo{ 12331 inputs: []inputInfo{ 12332 {0, 9223372037928517632}, // SP SB 12333 }, 12334 outputs: []outputInfo{ 12335 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12336 }, 12337 }, 12338 }, 12339 { 12340 name: "MOVBload", 12341 auxType: auxSymOff, 12342 argLen: 2, 12343 faultOnNilArg0: true, 12344 symEffect: SymRead, 12345 asm: arm64.AMOVB, 12346 reg: regInfo{ 12347 inputs: []inputInfo{ 12348 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12349 }, 12350 outputs: []outputInfo{ 12351 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12352 }, 12353 }, 12354 }, 12355 { 12356 name: "MOVBUload", 12357 auxType: auxSymOff, 12358 argLen: 2, 12359 faultOnNilArg0: true, 12360 symEffect: SymRead, 12361 asm: arm64.AMOVBU, 12362 reg: regInfo{ 12363 inputs: []inputInfo{ 12364 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12365 }, 12366 outputs: []outputInfo{ 12367 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12368 }, 12369 }, 12370 }, 12371 { 12372 name: "MOVHload", 12373 auxType: auxSymOff, 12374 argLen: 2, 12375 faultOnNilArg0: true, 12376 symEffect: SymRead, 12377 asm: arm64.AMOVH, 12378 reg: regInfo{ 12379 inputs: []inputInfo{ 12380 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12381 }, 12382 outputs: []outputInfo{ 12383 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12384 }, 12385 }, 12386 }, 12387 { 12388 name: "MOVHUload", 12389 auxType: auxSymOff, 12390 argLen: 2, 12391 faultOnNilArg0: true, 12392 symEffect: SymRead, 12393 asm: arm64.AMOVHU, 12394 reg: regInfo{ 12395 inputs: []inputInfo{ 12396 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12397 }, 12398 outputs: []outputInfo{ 12399 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12400 }, 12401 }, 12402 }, 12403 { 12404 name: "MOVWload", 12405 auxType: auxSymOff, 12406 argLen: 2, 12407 faultOnNilArg0: true, 12408 symEffect: SymRead, 12409 asm: arm64.AMOVW, 12410 reg: regInfo{ 12411 inputs: []inputInfo{ 12412 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12413 }, 12414 outputs: []outputInfo{ 12415 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12416 }, 12417 }, 12418 }, 12419 { 12420 name: "MOVWUload", 12421 auxType: auxSymOff, 12422 argLen: 2, 12423 faultOnNilArg0: true, 12424 symEffect: SymRead, 12425 asm: arm64.AMOVWU, 12426 reg: regInfo{ 12427 inputs: []inputInfo{ 12428 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12429 }, 12430 outputs: []outputInfo{ 12431 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12432 }, 12433 }, 12434 }, 12435 { 12436 name: "MOVDload", 12437 auxType: auxSymOff, 12438 argLen: 2, 12439 faultOnNilArg0: true, 12440 symEffect: SymRead, 12441 asm: arm64.AMOVD, 12442 reg: regInfo{ 12443 inputs: []inputInfo{ 12444 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12445 }, 12446 outputs: []outputInfo{ 12447 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12448 }, 12449 }, 12450 }, 12451 { 12452 name: "FMOVSload", 12453 auxType: auxSymOff, 12454 argLen: 2, 12455 faultOnNilArg0: true, 12456 symEffect: SymRead, 12457 asm: arm64.AFMOVS, 12458 reg: regInfo{ 12459 inputs: []inputInfo{ 12460 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12461 }, 12462 outputs: []outputInfo{ 12463 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12464 }, 12465 }, 12466 }, 12467 { 12468 name: "FMOVDload", 12469 auxType: auxSymOff, 12470 argLen: 2, 12471 faultOnNilArg0: true, 12472 symEffect: SymRead, 12473 asm: arm64.AFMOVD, 12474 reg: regInfo{ 12475 inputs: []inputInfo{ 12476 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12477 }, 12478 outputs: []outputInfo{ 12479 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12480 }, 12481 }, 12482 }, 12483 { 12484 name: "MOVBstore", 12485 auxType: auxSymOff, 12486 argLen: 3, 12487 faultOnNilArg0: true, 12488 symEffect: SymWrite, 12489 asm: arm64.AMOVB, 12490 reg: regInfo{ 12491 inputs: []inputInfo{ 12492 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12493 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12494 }, 12495 }, 12496 }, 12497 { 12498 name: "MOVHstore", 12499 auxType: auxSymOff, 12500 argLen: 3, 12501 faultOnNilArg0: true, 12502 symEffect: SymWrite, 12503 asm: arm64.AMOVH, 12504 reg: regInfo{ 12505 inputs: []inputInfo{ 12506 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12507 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12508 }, 12509 }, 12510 }, 12511 { 12512 name: "MOVWstore", 12513 auxType: auxSymOff, 12514 argLen: 3, 12515 faultOnNilArg0: true, 12516 symEffect: SymWrite, 12517 asm: arm64.AMOVW, 12518 reg: regInfo{ 12519 inputs: []inputInfo{ 12520 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12521 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12522 }, 12523 }, 12524 }, 12525 { 12526 name: "MOVDstore", 12527 auxType: auxSymOff, 12528 argLen: 3, 12529 faultOnNilArg0: true, 12530 symEffect: SymWrite, 12531 asm: arm64.AMOVD, 12532 reg: regInfo{ 12533 inputs: []inputInfo{ 12534 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12535 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12536 }, 12537 }, 12538 }, 12539 { 12540 name: "FMOVSstore", 12541 auxType: auxSymOff, 12542 argLen: 3, 12543 faultOnNilArg0: true, 12544 symEffect: SymWrite, 12545 asm: arm64.AFMOVS, 12546 reg: regInfo{ 12547 inputs: []inputInfo{ 12548 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12549 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12550 }, 12551 }, 12552 }, 12553 { 12554 name: "FMOVDstore", 12555 auxType: auxSymOff, 12556 argLen: 3, 12557 faultOnNilArg0: true, 12558 symEffect: SymWrite, 12559 asm: arm64.AFMOVD, 12560 reg: regInfo{ 12561 inputs: []inputInfo{ 12562 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12563 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12564 }, 12565 }, 12566 }, 12567 { 12568 name: "MOVBstorezero", 12569 auxType: auxSymOff, 12570 argLen: 2, 12571 faultOnNilArg0: true, 12572 symEffect: SymWrite, 12573 asm: arm64.AMOVB, 12574 reg: regInfo{ 12575 inputs: []inputInfo{ 12576 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12577 }, 12578 }, 12579 }, 12580 { 12581 name: "MOVHstorezero", 12582 auxType: auxSymOff, 12583 argLen: 2, 12584 faultOnNilArg0: true, 12585 symEffect: SymWrite, 12586 asm: arm64.AMOVH, 12587 reg: regInfo{ 12588 inputs: []inputInfo{ 12589 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12590 }, 12591 }, 12592 }, 12593 { 12594 name: "MOVWstorezero", 12595 auxType: auxSymOff, 12596 argLen: 2, 12597 faultOnNilArg0: true, 12598 symEffect: SymWrite, 12599 asm: arm64.AMOVW, 12600 reg: regInfo{ 12601 inputs: []inputInfo{ 12602 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12603 }, 12604 }, 12605 }, 12606 { 12607 name: "MOVDstorezero", 12608 auxType: auxSymOff, 12609 argLen: 2, 12610 faultOnNilArg0: true, 12611 symEffect: SymWrite, 12612 asm: arm64.AMOVD, 12613 reg: regInfo{ 12614 inputs: []inputInfo{ 12615 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12616 }, 12617 }, 12618 }, 12619 { 12620 name: "MOVBreg", 12621 argLen: 1, 12622 asm: arm64.AMOVB, 12623 reg: regInfo{ 12624 inputs: []inputInfo{ 12625 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12626 }, 12627 outputs: []outputInfo{ 12628 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12629 }, 12630 }, 12631 }, 12632 { 12633 name: "MOVBUreg", 12634 argLen: 1, 12635 asm: arm64.AMOVBU, 12636 reg: regInfo{ 12637 inputs: []inputInfo{ 12638 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12639 }, 12640 outputs: []outputInfo{ 12641 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12642 }, 12643 }, 12644 }, 12645 { 12646 name: "MOVHreg", 12647 argLen: 1, 12648 asm: arm64.AMOVH, 12649 reg: regInfo{ 12650 inputs: []inputInfo{ 12651 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12652 }, 12653 outputs: []outputInfo{ 12654 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12655 }, 12656 }, 12657 }, 12658 { 12659 name: "MOVHUreg", 12660 argLen: 1, 12661 asm: arm64.AMOVHU, 12662 reg: regInfo{ 12663 inputs: []inputInfo{ 12664 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12665 }, 12666 outputs: []outputInfo{ 12667 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12668 }, 12669 }, 12670 }, 12671 { 12672 name: "MOVWreg", 12673 argLen: 1, 12674 asm: arm64.AMOVW, 12675 reg: regInfo{ 12676 inputs: []inputInfo{ 12677 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12678 }, 12679 outputs: []outputInfo{ 12680 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12681 }, 12682 }, 12683 }, 12684 { 12685 name: "MOVWUreg", 12686 argLen: 1, 12687 asm: arm64.AMOVWU, 12688 reg: regInfo{ 12689 inputs: []inputInfo{ 12690 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12691 }, 12692 outputs: []outputInfo{ 12693 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12694 }, 12695 }, 12696 }, 12697 { 12698 name: "MOVDreg", 12699 argLen: 1, 12700 asm: arm64.AMOVD, 12701 reg: regInfo{ 12702 inputs: []inputInfo{ 12703 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12704 }, 12705 outputs: []outputInfo{ 12706 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12707 }, 12708 }, 12709 }, 12710 { 12711 name: "MOVDnop", 12712 argLen: 1, 12713 resultInArg0: true, 12714 reg: regInfo{ 12715 inputs: []inputInfo{ 12716 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12717 }, 12718 outputs: []outputInfo{ 12719 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12720 }, 12721 }, 12722 }, 12723 { 12724 name: "SCVTFWS", 12725 argLen: 1, 12726 asm: arm64.ASCVTFWS, 12727 reg: regInfo{ 12728 inputs: []inputInfo{ 12729 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12730 }, 12731 outputs: []outputInfo{ 12732 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12733 }, 12734 }, 12735 }, 12736 { 12737 name: "SCVTFWD", 12738 argLen: 1, 12739 asm: arm64.ASCVTFWD, 12740 reg: regInfo{ 12741 inputs: []inputInfo{ 12742 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12743 }, 12744 outputs: []outputInfo{ 12745 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12746 }, 12747 }, 12748 }, 12749 { 12750 name: "UCVTFWS", 12751 argLen: 1, 12752 asm: arm64.AUCVTFWS, 12753 reg: regInfo{ 12754 inputs: []inputInfo{ 12755 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12756 }, 12757 outputs: []outputInfo{ 12758 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12759 }, 12760 }, 12761 }, 12762 { 12763 name: "UCVTFWD", 12764 argLen: 1, 12765 asm: arm64.AUCVTFWD, 12766 reg: regInfo{ 12767 inputs: []inputInfo{ 12768 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12769 }, 12770 outputs: []outputInfo{ 12771 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12772 }, 12773 }, 12774 }, 12775 { 12776 name: "SCVTFS", 12777 argLen: 1, 12778 asm: arm64.ASCVTFS, 12779 reg: regInfo{ 12780 inputs: []inputInfo{ 12781 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12782 }, 12783 outputs: []outputInfo{ 12784 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12785 }, 12786 }, 12787 }, 12788 { 12789 name: "SCVTFD", 12790 argLen: 1, 12791 asm: arm64.ASCVTFD, 12792 reg: regInfo{ 12793 inputs: []inputInfo{ 12794 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12795 }, 12796 outputs: []outputInfo{ 12797 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12798 }, 12799 }, 12800 }, 12801 { 12802 name: "UCVTFS", 12803 argLen: 1, 12804 asm: arm64.AUCVTFS, 12805 reg: regInfo{ 12806 inputs: []inputInfo{ 12807 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12808 }, 12809 outputs: []outputInfo{ 12810 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12811 }, 12812 }, 12813 }, 12814 { 12815 name: "UCVTFD", 12816 argLen: 1, 12817 asm: arm64.AUCVTFD, 12818 reg: regInfo{ 12819 inputs: []inputInfo{ 12820 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12821 }, 12822 outputs: []outputInfo{ 12823 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12824 }, 12825 }, 12826 }, 12827 { 12828 name: "FCVTZSSW", 12829 argLen: 1, 12830 asm: arm64.AFCVTZSSW, 12831 reg: regInfo{ 12832 inputs: []inputInfo{ 12833 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12834 }, 12835 outputs: []outputInfo{ 12836 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12837 }, 12838 }, 12839 }, 12840 { 12841 name: "FCVTZSDW", 12842 argLen: 1, 12843 asm: arm64.AFCVTZSDW, 12844 reg: regInfo{ 12845 inputs: []inputInfo{ 12846 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12847 }, 12848 outputs: []outputInfo{ 12849 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12850 }, 12851 }, 12852 }, 12853 { 12854 name: "FCVTZUSW", 12855 argLen: 1, 12856 asm: arm64.AFCVTZUSW, 12857 reg: regInfo{ 12858 inputs: []inputInfo{ 12859 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12860 }, 12861 outputs: []outputInfo{ 12862 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12863 }, 12864 }, 12865 }, 12866 { 12867 name: "FCVTZUDW", 12868 argLen: 1, 12869 asm: arm64.AFCVTZUDW, 12870 reg: regInfo{ 12871 inputs: []inputInfo{ 12872 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12873 }, 12874 outputs: []outputInfo{ 12875 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12876 }, 12877 }, 12878 }, 12879 { 12880 name: "FCVTZSS", 12881 argLen: 1, 12882 asm: arm64.AFCVTZSS, 12883 reg: regInfo{ 12884 inputs: []inputInfo{ 12885 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12886 }, 12887 outputs: []outputInfo{ 12888 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12889 }, 12890 }, 12891 }, 12892 { 12893 name: "FCVTZSD", 12894 argLen: 1, 12895 asm: arm64.AFCVTZSD, 12896 reg: regInfo{ 12897 inputs: []inputInfo{ 12898 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12899 }, 12900 outputs: []outputInfo{ 12901 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12902 }, 12903 }, 12904 }, 12905 { 12906 name: "FCVTZUS", 12907 argLen: 1, 12908 asm: arm64.AFCVTZUS, 12909 reg: regInfo{ 12910 inputs: []inputInfo{ 12911 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12912 }, 12913 outputs: []outputInfo{ 12914 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12915 }, 12916 }, 12917 }, 12918 { 12919 name: "FCVTZUD", 12920 argLen: 1, 12921 asm: arm64.AFCVTZUD, 12922 reg: regInfo{ 12923 inputs: []inputInfo{ 12924 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12925 }, 12926 outputs: []outputInfo{ 12927 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12928 }, 12929 }, 12930 }, 12931 { 12932 name: "FCVTSD", 12933 argLen: 1, 12934 asm: arm64.AFCVTSD, 12935 reg: regInfo{ 12936 inputs: []inputInfo{ 12937 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12938 }, 12939 outputs: []outputInfo{ 12940 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12941 }, 12942 }, 12943 }, 12944 { 12945 name: "FCVTDS", 12946 argLen: 1, 12947 asm: arm64.AFCVTDS, 12948 reg: regInfo{ 12949 inputs: []inputInfo{ 12950 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12951 }, 12952 outputs: []outputInfo{ 12953 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12954 }, 12955 }, 12956 }, 12957 { 12958 name: "CSELULT", 12959 argLen: 3, 12960 asm: arm64.ACSEL, 12961 reg: regInfo{ 12962 inputs: []inputInfo{ 12963 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12964 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12965 }, 12966 outputs: []outputInfo{ 12967 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12968 }, 12969 }, 12970 }, 12971 { 12972 name: "CSELULT0", 12973 argLen: 2, 12974 asm: arm64.ACSEL, 12975 reg: regInfo{ 12976 inputs: []inputInfo{ 12977 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12978 }, 12979 outputs: []outputInfo{ 12980 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12981 }, 12982 }, 12983 }, 12984 { 12985 name: "CALLstatic", 12986 auxType: auxSymOff, 12987 argLen: 1, 12988 clobberFlags: true, 12989 call: true, 12990 symEffect: SymNone, 12991 reg: regInfo{ 12992 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12993 }, 12994 }, 12995 { 12996 name: "CALLclosure", 12997 auxType: auxInt64, 12998 argLen: 3, 12999 clobberFlags: true, 13000 call: true, 13001 reg: regInfo{ 13002 inputs: []inputInfo{ 13003 {1, 67108864}, // R26 13004 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 13005 }, 13006 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13007 }, 13008 }, 13009 { 13010 name: "CALLinter", 13011 auxType: auxInt64, 13012 argLen: 2, 13013 clobberFlags: true, 13014 call: true, 13015 reg: regInfo{ 13016 inputs: []inputInfo{ 13017 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13018 }, 13019 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13020 }, 13021 }, 13022 { 13023 name: "LoweredNilCheck", 13024 argLen: 2, 13025 nilCheck: true, 13026 faultOnNilArg0: true, 13027 reg: regInfo{ 13028 inputs: []inputInfo{ 13029 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13030 }, 13031 }, 13032 }, 13033 { 13034 name: "Equal", 13035 argLen: 1, 13036 reg: regInfo{ 13037 outputs: []outputInfo{ 13038 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13039 }, 13040 }, 13041 }, 13042 { 13043 name: "NotEqual", 13044 argLen: 1, 13045 reg: regInfo{ 13046 outputs: []outputInfo{ 13047 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13048 }, 13049 }, 13050 }, 13051 { 13052 name: "LessThan", 13053 argLen: 1, 13054 reg: regInfo{ 13055 outputs: []outputInfo{ 13056 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13057 }, 13058 }, 13059 }, 13060 { 13061 name: "LessEqual", 13062 argLen: 1, 13063 reg: regInfo{ 13064 outputs: []outputInfo{ 13065 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13066 }, 13067 }, 13068 }, 13069 { 13070 name: "GreaterThan", 13071 argLen: 1, 13072 reg: regInfo{ 13073 outputs: []outputInfo{ 13074 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13075 }, 13076 }, 13077 }, 13078 { 13079 name: "GreaterEqual", 13080 argLen: 1, 13081 reg: regInfo{ 13082 outputs: []outputInfo{ 13083 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13084 }, 13085 }, 13086 }, 13087 { 13088 name: "LessThanU", 13089 argLen: 1, 13090 reg: regInfo{ 13091 outputs: []outputInfo{ 13092 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13093 }, 13094 }, 13095 }, 13096 { 13097 name: "LessEqualU", 13098 argLen: 1, 13099 reg: regInfo{ 13100 outputs: []outputInfo{ 13101 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13102 }, 13103 }, 13104 }, 13105 { 13106 name: "GreaterThanU", 13107 argLen: 1, 13108 reg: regInfo{ 13109 outputs: []outputInfo{ 13110 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13111 }, 13112 }, 13113 }, 13114 { 13115 name: "GreaterEqualU", 13116 argLen: 1, 13117 reg: regInfo{ 13118 outputs: []outputInfo{ 13119 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13120 }, 13121 }, 13122 }, 13123 { 13124 name: "DUFFZERO", 13125 auxType: auxInt64, 13126 argLen: 2, 13127 faultOnNilArg0: true, 13128 reg: regInfo{ 13129 inputs: []inputInfo{ 13130 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13131 }, 13132 clobbers: 536936448, // R16 R30 13133 }, 13134 }, 13135 { 13136 name: "LoweredZero", 13137 argLen: 3, 13138 clobberFlags: true, 13139 faultOnNilArg0: true, 13140 reg: regInfo{ 13141 inputs: []inputInfo{ 13142 {0, 65536}, // R16 13143 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13144 }, 13145 clobbers: 65536, // R16 13146 }, 13147 }, 13148 { 13149 name: "DUFFCOPY", 13150 auxType: auxInt64, 13151 argLen: 3, 13152 faultOnNilArg0: true, 13153 faultOnNilArg1: true, 13154 reg: regInfo{ 13155 inputs: []inputInfo{ 13156 {0, 131072}, // R17 13157 {1, 65536}, // R16 13158 }, 13159 clobbers: 537067520, // R16 R17 R30 13160 }, 13161 }, 13162 { 13163 name: "LoweredMove", 13164 argLen: 4, 13165 clobberFlags: true, 13166 faultOnNilArg0: true, 13167 faultOnNilArg1: true, 13168 reg: regInfo{ 13169 inputs: []inputInfo{ 13170 {0, 131072}, // R17 13171 {1, 65536}, // R16 13172 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13173 }, 13174 clobbers: 196608, // R16 R17 13175 }, 13176 }, 13177 { 13178 name: "LoweredGetClosurePtr", 13179 argLen: 0, 13180 reg: regInfo{ 13181 outputs: []outputInfo{ 13182 {0, 67108864}, // R26 13183 }, 13184 }, 13185 }, 13186 { 13187 name: "MOVDconvert", 13188 argLen: 2, 13189 asm: arm64.AMOVD, 13190 reg: regInfo{ 13191 inputs: []inputInfo{ 13192 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13193 }, 13194 outputs: []outputInfo{ 13195 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13196 }, 13197 }, 13198 }, 13199 { 13200 name: "FlagEQ", 13201 argLen: 0, 13202 reg: regInfo{}, 13203 }, 13204 { 13205 name: "FlagLT_ULT", 13206 argLen: 0, 13207 reg: regInfo{}, 13208 }, 13209 { 13210 name: "FlagLT_UGT", 13211 argLen: 0, 13212 reg: regInfo{}, 13213 }, 13214 { 13215 name: "FlagGT_UGT", 13216 argLen: 0, 13217 reg: regInfo{}, 13218 }, 13219 { 13220 name: "FlagGT_ULT", 13221 argLen: 0, 13222 reg: regInfo{}, 13223 }, 13224 { 13225 name: "InvertFlags", 13226 argLen: 1, 13227 reg: regInfo{}, 13228 }, 13229 { 13230 name: "LDAR", 13231 argLen: 2, 13232 faultOnNilArg0: true, 13233 asm: arm64.ALDAR, 13234 reg: regInfo{ 13235 inputs: []inputInfo{ 13236 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13237 }, 13238 outputs: []outputInfo{ 13239 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13240 }, 13241 }, 13242 }, 13243 { 13244 name: "LDARW", 13245 argLen: 2, 13246 faultOnNilArg0: true, 13247 asm: arm64.ALDARW, 13248 reg: regInfo{ 13249 inputs: []inputInfo{ 13250 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13251 }, 13252 outputs: []outputInfo{ 13253 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13254 }, 13255 }, 13256 }, 13257 { 13258 name: "STLR", 13259 argLen: 3, 13260 faultOnNilArg0: true, 13261 hasSideEffects: true, 13262 asm: arm64.ASTLR, 13263 reg: regInfo{ 13264 inputs: []inputInfo{ 13265 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13266 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13267 }, 13268 }, 13269 }, 13270 { 13271 name: "STLRW", 13272 argLen: 3, 13273 faultOnNilArg0: true, 13274 hasSideEffects: true, 13275 asm: arm64.ASTLRW, 13276 reg: regInfo{ 13277 inputs: []inputInfo{ 13278 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13279 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13280 }, 13281 }, 13282 }, 13283 { 13284 name: "LoweredAtomicExchange64", 13285 argLen: 3, 13286 resultNotInArgs: true, 13287 faultOnNilArg0: true, 13288 hasSideEffects: true, 13289 reg: regInfo{ 13290 inputs: []inputInfo{ 13291 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13292 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13293 }, 13294 outputs: []outputInfo{ 13295 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13296 }, 13297 }, 13298 }, 13299 { 13300 name: "LoweredAtomicExchange32", 13301 argLen: 3, 13302 resultNotInArgs: true, 13303 faultOnNilArg0: true, 13304 hasSideEffects: true, 13305 reg: regInfo{ 13306 inputs: []inputInfo{ 13307 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13308 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13309 }, 13310 outputs: []outputInfo{ 13311 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13312 }, 13313 }, 13314 }, 13315 { 13316 name: "LoweredAtomicAdd64", 13317 argLen: 3, 13318 resultNotInArgs: true, 13319 faultOnNilArg0: true, 13320 hasSideEffects: true, 13321 reg: regInfo{ 13322 inputs: []inputInfo{ 13323 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13324 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13325 }, 13326 outputs: []outputInfo{ 13327 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13328 }, 13329 }, 13330 }, 13331 { 13332 name: "LoweredAtomicAdd32", 13333 argLen: 3, 13334 resultNotInArgs: true, 13335 faultOnNilArg0: true, 13336 hasSideEffects: true, 13337 reg: regInfo{ 13338 inputs: []inputInfo{ 13339 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13340 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13341 }, 13342 outputs: []outputInfo{ 13343 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13344 }, 13345 }, 13346 }, 13347 { 13348 name: "LoweredAtomicCas64", 13349 argLen: 4, 13350 resultNotInArgs: true, 13351 clobberFlags: true, 13352 faultOnNilArg0: true, 13353 hasSideEffects: true, 13354 reg: regInfo{ 13355 inputs: []inputInfo{ 13356 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13357 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13358 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13359 }, 13360 outputs: []outputInfo{ 13361 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13362 }, 13363 }, 13364 }, 13365 { 13366 name: "LoweredAtomicCas32", 13367 argLen: 4, 13368 resultNotInArgs: true, 13369 clobberFlags: true, 13370 faultOnNilArg0: true, 13371 hasSideEffects: true, 13372 reg: regInfo{ 13373 inputs: []inputInfo{ 13374 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13375 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13376 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13377 }, 13378 outputs: []outputInfo{ 13379 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13380 }, 13381 }, 13382 }, 13383 { 13384 name: "LoweredAtomicAnd8", 13385 argLen: 3, 13386 faultOnNilArg0: true, 13387 hasSideEffects: true, 13388 asm: arm64.AAND, 13389 reg: regInfo{ 13390 inputs: []inputInfo{ 13391 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13392 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13393 }, 13394 }, 13395 }, 13396 { 13397 name: "LoweredAtomicOr8", 13398 argLen: 3, 13399 faultOnNilArg0: true, 13400 hasSideEffects: true, 13401 asm: arm64.AORR, 13402 reg: regInfo{ 13403 inputs: []inputInfo{ 13404 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13405 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13406 }, 13407 }, 13408 }, 13409 13410 { 13411 name: "ADD", 13412 argLen: 2, 13413 commutative: true, 13414 asm: mips.AADDU, 13415 reg: regInfo{ 13416 inputs: []inputInfo{ 13417 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13418 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13419 }, 13420 outputs: []outputInfo{ 13421 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13422 }, 13423 }, 13424 }, 13425 { 13426 name: "ADDconst", 13427 auxType: auxInt32, 13428 argLen: 1, 13429 asm: mips.AADDU, 13430 reg: regInfo{ 13431 inputs: []inputInfo{ 13432 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 13433 }, 13434 outputs: []outputInfo{ 13435 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13436 }, 13437 }, 13438 }, 13439 { 13440 name: "SUB", 13441 argLen: 2, 13442 asm: mips.ASUBU, 13443 reg: regInfo{ 13444 inputs: []inputInfo{ 13445 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13446 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13447 }, 13448 outputs: []outputInfo{ 13449 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13450 }, 13451 }, 13452 }, 13453 { 13454 name: "SUBconst", 13455 auxType: auxInt32, 13456 argLen: 1, 13457 asm: mips.ASUBU, 13458 reg: regInfo{ 13459 inputs: []inputInfo{ 13460 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13461 }, 13462 outputs: []outputInfo{ 13463 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13464 }, 13465 }, 13466 }, 13467 { 13468 name: "MUL", 13469 argLen: 2, 13470 commutative: true, 13471 asm: mips.AMUL, 13472 reg: regInfo{ 13473 inputs: []inputInfo{ 13474 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13475 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13476 }, 13477 clobbers: 105553116266496, // HI LO 13478 outputs: []outputInfo{ 13479 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13480 }, 13481 }, 13482 }, 13483 { 13484 name: "MULT", 13485 argLen: 2, 13486 commutative: true, 13487 asm: mips.AMUL, 13488 reg: regInfo{ 13489 inputs: []inputInfo{ 13490 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13491 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13492 }, 13493 outputs: []outputInfo{ 13494 {0, 35184372088832}, // HI 13495 {1, 70368744177664}, // LO 13496 }, 13497 }, 13498 }, 13499 { 13500 name: "MULTU", 13501 argLen: 2, 13502 commutative: true, 13503 asm: mips.AMULU, 13504 reg: regInfo{ 13505 inputs: []inputInfo{ 13506 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13507 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13508 }, 13509 outputs: []outputInfo{ 13510 {0, 35184372088832}, // HI 13511 {1, 70368744177664}, // LO 13512 }, 13513 }, 13514 }, 13515 { 13516 name: "DIV", 13517 argLen: 2, 13518 asm: mips.ADIV, 13519 reg: regInfo{ 13520 inputs: []inputInfo{ 13521 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13522 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13523 }, 13524 outputs: []outputInfo{ 13525 {0, 35184372088832}, // HI 13526 {1, 70368744177664}, // LO 13527 }, 13528 }, 13529 }, 13530 { 13531 name: "DIVU", 13532 argLen: 2, 13533 asm: mips.ADIVU, 13534 reg: regInfo{ 13535 inputs: []inputInfo{ 13536 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13537 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13538 }, 13539 outputs: []outputInfo{ 13540 {0, 35184372088832}, // HI 13541 {1, 70368744177664}, // LO 13542 }, 13543 }, 13544 }, 13545 { 13546 name: "ADDF", 13547 argLen: 2, 13548 commutative: true, 13549 asm: mips.AADDF, 13550 reg: regInfo{ 13551 inputs: []inputInfo{ 13552 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13553 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13554 }, 13555 outputs: []outputInfo{ 13556 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13557 }, 13558 }, 13559 }, 13560 { 13561 name: "ADDD", 13562 argLen: 2, 13563 commutative: true, 13564 asm: mips.AADDD, 13565 reg: regInfo{ 13566 inputs: []inputInfo{ 13567 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13568 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13569 }, 13570 outputs: []outputInfo{ 13571 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13572 }, 13573 }, 13574 }, 13575 { 13576 name: "SUBF", 13577 argLen: 2, 13578 asm: mips.ASUBF, 13579 reg: regInfo{ 13580 inputs: []inputInfo{ 13581 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13582 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13583 }, 13584 outputs: []outputInfo{ 13585 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13586 }, 13587 }, 13588 }, 13589 { 13590 name: "SUBD", 13591 argLen: 2, 13592 asm: mips.ASUBD, 13593 reg: regInfo{ 13594 inputs: []inputInfo{ 13595 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13596 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13597 }, 13598 outputs: []outputInfo{ 13599 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13600 }, 13601 }, 13602 }, 13603 { 13604 name: "MULF", 13605 argLen: 2, 13606 commutative: true, 13607 asm: mips.AMULF, 13608 reg: regInfo{ 13609 inputs: []inputInfo{ 13610 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13611 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13612 }, 13613 outputs: []outputInfo{ 13614 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13615 }, 13616 }, 13617 }, 13618 { 13619 name: "MULD", 13620 argLen: 2, 13621 commutative: true, 13622 asm: mips.AMULD, 13623 reg: regInfo{ 13624 inputs: []inputInfo{ 13625 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13626 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13627 }, 13628 outputs: []outputInfo{ 13629 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13630 }, 13631 }, 13632 }, 13633 { 13634 name: "DIVF", 13635 argLen: 2, 13636 asm: mips.ADIVF, 13637 reg: regInfo{ 13638 inputs: []inputInfo{ 13639 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13640 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13641 }, 13642 outputs: []outputInfo{ 13643 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13644 }, 13645 }, 13646 }, 13647 { 13648 name: "DIVD", 13649 argLen: 2, 13650 asm: mips.ADIVD, 13651 reg: regInfo{ 13652 inputs: []inputInfo{ 13653 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13654 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13655 }, 13656 outputs: []outputInfo{ 13657 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13658 }, 13659 }, 13660 }, 13661 { 13662 name: "AND", 13663 argLen: 2, 13664 commutative: true, 13665 asm: mips.AAND, 13666 reg: regInfo{ 13667 inputs: []inputInfo{ 13668 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13669 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13670 }, 13671 outputs: []outputInfo{ 13672 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13673 }, 13674 }, 13675 }, 13676 { 13677 name: "ANDconst", 13678 auxType: auxInt32, 13679 argLen: 1, 13680 asm: mips.AAND, 13681 reg: regInfo{ 13682 inputs: []inputInfo{ 13683 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13684 }, 13685 outputs: []outputInfo{ 13686 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13687 }, 13688 }, 13689 }, 13690 { 13691 name: "OR", 13692 argLen: 2, 13693 commutative: true, 13694 asm: mips.AOR, 13695 reg: regInfo{ 13696 inputs: []inputInfo{ 13697 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13698 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13699 }, 13700 outputs: []outputInfo{ 13701 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13702 }, 13703 }, 13704 }, 13705 { 13706 name: "ORconst", 13707 auxType: auxInt32, 13708 argLen: 1, 13709 asm: mips.AOR, 13710 reg: regInfo{ 13711 inputs: []inputInfo{ 13712 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13713 }, 13714 outputs: []outputInfo{ 13715 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13716 }, 13717 }, 13718 }, 13719 { 13720 name: "XOR", 13721 argLen: 2, 13722 commutative: true, 13723 asm: mips.AXOR, 13724 reg: regInfo{ 13725 inputs: []inputInfo{ 13726 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13727 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13728 }, 13729 outputs: []outputInfo{ 13730 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13731 }, 13732 }, 13733 }, 13734 { 13735 name: "XORconst", 13736 auxType: auxInt32, 13737 argLen: 1, 13738 asm: mips.AXOR, 13739 reg: regInfo{ 13740 inputs: []inputInfo{ 13741 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13742 }, 13743 outputs: []outputInfo{ 13744 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13745 }, 13746 }, 13747 }, 13748 { 13749 name: "NOR", 13750 argLen: 2, 13751 commutative: true, 13752 asm: mips.ANOR, 13753 reg: regInfo{ 13754 inputs: []inputInfo{ 13755 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13756 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13757 }, 13758 outputs: []outputInfo{ 13759 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13760 }, 13761 }, 13762 }, 13763 { 13764 name: "NORconst", 13765 auxType: auxInt32, 13766 argLen: 1, 13767 asm: mips.ANOR, 13768 reg: regInfo{ 13769 inputs: []inputInfo{ 13770 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13771 }, 13772 outputs: []outputInfo{ 13773 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13774 }, 13775 }, 13776 }, 13777 { 13778 name: "NEG", 13779 argLen: 1, 13780 reg: regInfo{ 13781 inputs: []inputInfo{ 13782 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13783 }, 13784 outputs: []outputInfo{ 13785 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13786 }, 13787 }, 13788 }, 13789 { 13790 name: "NEGF", 13791 argLen: 1, 13792 asm: mips.ANEGF, 13793 reg: regInfo{ 13794 inputs: []inputInfo{ 13795 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13796 }, 13797 outputs: []outputInfo{ 13798 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13799 }, 13800 }, 13801 }, 13802 { 13803 name: "NEGD", 13804 argLen: 1, 13805 asm: mips.ANEGD, 13806 reg: regInfo{ 13807 inputs: []inputInfo{ 13808 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13809 }, 13810 outputs: []outputInfo{ 13811 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13812 }, 13813 }, 13814 }, 13815 { 13816 name: "SQRTD", 13817 argLen: 1, 13818 asm: mips.ASQRTD, 13819 reg: regInfo{ 13820 inputs: []inputInfo{ 13821 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13822 }, 13823 outputs: []outputInfo{ 13824 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13825 }, 13826 }, 13827 }, 13828 { 13829 name: "SLL", 13830 argLen: 2, 13831 asm: mips.ASLL, 13832 reg: regInfo{ 13833 inputs: []inputInfo{ 13834 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13835 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13836 }, 13837 outputs: []outputInfo{ 13838 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13839 }, 13840 }, 13841 }, 13842 { 13843 name: "SLLconst", 13844 auxType: auxInt32, 13845 argLen: 1, 13846 asm: mips.ASLL, 13847 reg: regInfo{ 13848 inputs: []inputInfo{ 13849 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13850 }, 13851 outputs: []outputInfo{ 13852 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13853 }, 13854 }, 13855 }, 13856 { 13857 name: "SRL", 13858 argLen: 2, 13859 asm: mips.ASRL, 13860 reg: regInfo{ 13861 inputs: []inputInfo{ 13862 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13863 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13864 }, 13865 outputs: []outputInfo{ 13866 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13867 }, 13868 }, 13869 }, 13870 { 13871 name: "SRLconst", 13872 auxType: auxInt32, 13873 argLen: 1, 13874 asm: mips.ASRL, 13875 reg: regInfo{ 13876 inputs: []inputInfo{ 13877 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13878 }, 13879 outputs: []outputInfo{ 13880 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13881 }, 13882 }, 13883 }, 13884 { 13885 name: "SRA", 13886 argLen: 2, 13887 asm: mips.ASRA, 13888 reg: regInfo{ 13889 inputs: []inputInfo{ 13890 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13891 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13892 }, 13893 outputs: []outputInfo{ 13894 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13895 }, 13896 }, 13897 }, 13898 { 13899 name: "SRAconst", 13900 auxType: auxInt32, 13901 argLen: 1, 13902 asm: mips.ASRA, 13903 reg: regInfo{ 13904 inputs: []inputInfo{ 13905 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13906 }, 13907 outputs: []outputInfo{ 13908 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13909 }, 13910 }, 13911 }, 13912 { 13913 name: "CLZ", 13914 argLen: 1, 13915 asm: mips.ACLZ, 13916 reg: regInfo{ 13917 inputs: []inputInfo{ 13918 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13919 }, 13920 outputs: []outputInfo{ 13921 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13922 }, 13923 }, 13924 }, 13925 { 13926 name: "SGT", 13927 argLen: 2, 13928 asm: mips.ASGT, 13929 reg: regInfo{ 13930 inputs: []inputInfo{ 13931 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13932 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13933 }, 13934 outputs: []outputInfo{ 13935 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13936 }, 13937 }, 13938 }, 13939 { 13940 name: "SGTconst", 13941 auxType: auxInt32, 13942 argLen: 1, 13943 asm: mips.ASGT, 13944 reg: regInfo{ 13945 inputs: []inputInfo{ 13946 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13947 }, 13948 outputs: []outputInfo{ 13949 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13950 }, 13951 }, 13952 }, 13953 { 13954 name: "SGTzero", 13955 argLen: 1, 13956 asm: mips.ASGT, 13957 reg: regInfo{ 13958 inputs: []inputInfo{ 13959 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13960 }, 13961 outputs: []outputInfo{ 13962 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13963 }, 13964 }, 13965 }, 13966 { 13967 name: "SGTU", 13968 argLen: 2, 13969 asm: mips.ASGTU, 13970 reg: regInfo{ 13971 inputs: []inputInfo{ 13972 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13973 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13974 }, 13975 outputs: []outputInfo{ 13976 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13977 }, 13978 }, 13979 }, 13980 { 13981 name: "SGTUconst", 13982 auxType: auxInt32, 13983 argLen: 1, 13984 asm: mips.ASGTU, 13985 reg: regInfo{ 13986 inputs: []inputInfo{ 13987 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13988 }, 13989 outputs: []outputInfo{ 13990 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13991 }, 13992 }, 13993 }, 13994 { 13995 name: "SGTUzero", 13996 argLen: 1, 13997 asm: mips.ASGTU, 13998 reg: regInfo{ 13999 inputs: []inputInfo{ 14000 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14001 }, 14002 outputs: []outputInfo{ 14003 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14004 }, 14005 }, 14006 }, 14007 { 14008 name: "CMPEQF", 14009 argLen: 2, 14010 asm: mips.ACMPEQF, 14011 reg: regInfo{ 14012 inputs: []inputInfo{ 14013 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14014 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14015 }, 14016 }, 14017 }, 14018 { 14019 name: "CMPEQD", 14020 argLen: 2, 14021 asm: mips.ACMPEQD, 14022 reg: regInfo{ 14023 inputs: []inputInfo{ 14024 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14025 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14026 }, 14027 }, 14028 }, 14029 { 14030 name: "CMPGEF", 14031 argLen: 2, 14032 asm: mips.ACMPGEF, 14033 reg: regInfo{ 14034 inputs: []inputInfo{ 14035 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14036 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14037 }, 14038 }, 14039 }, 14040 { 14041 name: "CMPGED", 14042 argLen: 2, 14043 asm: mips.ACMPGED, 14044 reg: regInfo{ 14045 inputs: []inputInfo{ 14046 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14047 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14048 }, 14049 }, 14050 }, 14051 { 14052 name: "CMPGTF", 14053 argLen: 2, 14054 asm: mips.ACMPGTF, 14055 reg: regInfo{ 14056 inputs: []inputInfo{ 14057 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14058 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14059 }, 14060 }, 14061 }, 14062 { 14063 name: "CMPGTD", 14064 argLen: 2, 14065 asm: mips.ACMPGTD, 14066 reg: regInfo{ 14067 inputs: []inputInfo{ 14068 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14069 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14070 }, 14071 }, 14072 }, 14073 { 14074 name: "MOVWconst", 14075 auxType: auxInt32, 14076 argLen: 0, 14077 rematerializeable: true, 14078 asm: mips.AMOVW, 14079 reg: regInfo{ 14080 outputs: []outputInfo{ 14081 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14082 }, 14083 }, 14084 }, 14085 { 14086 name: "MOVFconst", 14087 auxType: auxFloat32, 14088 argLen: 0, 14089 rematerializeable: true, 14090 asm: mips.AMOVF, 14091 reg: regInfo{ 14092 outputs: []outputInfo{ 14093 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14094 }, 14095 }, 14096 }, 14097 { 14098 name: "MOVDconst", 14099 auxType: auxFloat64, 14100 argLen: 0, 14101 rematerializeable: true, 14102 asm: mips.AMOVD, 14103 reg: regInfo{ 14104 outputs: []outputInfo{ 14105 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14106 }, 14107 }, 14108 }, 14109 { 14110 name: "MOVWaddr", 14111 auxType: auxSymOff, 14112 argLen: 1, 14113 rematerializeable: true, 14114 symEffect: SymAddr, 14115 asm: mips.AMOVW, 14116 reg: regInfo{ 14117 inputs: []inputInfo{ 14118 {0, 140737555464192}, // SP SB 14119 }, 14120 outputs: []outputInfo{ 14121 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14122 }, 14123 }, 14124 }, 14125 { 14126 name: "MOVBload", 14127 auxType: auxSymOff, 14128 argLen: 2, 14129 faultOnNilArg0: true, 14130 symEffect: SymRead, 14131 asm: mips.AMOVB, 14132 reg: regInfo{ 14133 inputs: []inputInfo{ 14134 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14135 }, 14136 outputs: []outputInfo{ 14137 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14138 }, 14139 }, 14140 }, 14141 { 14142 name: "MOVBUload", 14143 auxType: auxSymOff, 14144 argLen: 2, 14145 faultOnNilArg0: true, 14146 symEffect: SymRead, 14147 asm: mips.AMOVBU, 14148 reg: regInfo{ 14149 inputs: []inputInfo{ 14150 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14151 }, 14152 outputs: []outputInfo{ 14153 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14154 }, 14155 }, 14156 }, 14157 { 14158 name: "MOVHload", 14159 auxType: auxSymOff, 14160 argLen: 2, 14161 faultOnNilArg0: true, 14162 symEffect: SymRead, 14163 asm: mips.AMOVH, 14164 reg: regInfo{ 14165 inputs: []inputInfo{ 14166 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14167 }, 14168 outputs: []outputInfo{ 14169 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14170 }, 14171 }, 14172 }, 14173 { 14174 name: "MOVHUload", 14175 auxType: auxSymOff, 14176 argLen: 2, 14177 faultOnNilArg0: true, 14178 symEffect: SymRead, 14179 asm: mips.AMOVHU, 14180 reg: regInfo{ 14181 inputs: []inputInfo{ 14182 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14183 }, 14184 outputs: []outputInfo{ 14185 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14186 }, 14187 }, 14188 }, 14189 { 14190 name: "MOVWload", 14191 auxType: auxSymOff, 14192 argLen: 2, 14193 faultOnNilArg0: true, 14194 symEffect: SymRead, 14195 asm: mips.AMOVW, 14196 reg: regInfo{ 14197 inputs: []inputInfo{ 14198 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14199 }, 14200 outputs: []outputInfo{ 14201 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14202 }, 14203 }, 14204 }, 14205 { 14206 name: "MOVFload", 14207 auxType: auxSymOff, 14208 argLen: 2, 14209 faultOnNilArg0: true, 14210 symEffect: SymRead, 14211 asm: mips.AMOVF, 14212 reg: regInfo{ 14213 inputs: []inputInfo{ 14214 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14215 }, 14216 outputs: []outputInfo{ 14217 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14218 }, 14219 }, 14220 }, 14221 { 14222 name: "MOVDload", 14223 auxType: auxSymOff, 14224 argLen: 2, 14225 faultOnNilArg0: true, 14226 symEffect: SymRead, 14227 asm: mips.AMOVD, 14228 reg: regInfo{ 14229 inputs: []inputInfo{ 14230 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14231 }, 14232 outputs: []outputInfo{ 14233 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14234 }, 14235 }, 14236 }, 14237 { 14238 name: "MOVBstore", 14239 auxType: auxSymOff, 14240 argLen: 3, 14241 faultOnNilArg0: true, 14242 symEffect: SymWrite, 14243 asm: mips.AMOVB, 14244 reg: regInfo{ 14245 inputs: []inputInfo{ 14246 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14247 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14248 }, 14249 }, 14250 }, 14251 { 14252 name: "MOVHstore", 14253 auxType: auxSymOff, 14254 argLen: 3, 14255 faultOnNilArg0: true, 14256 symEffect: SymWrite, 14257 asm: mips.AMOVH, 14258 reg: regInfo{ 14259 inputs: []inputInfo{ 14260 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14261 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14262 }, 14263 }, 14264 }, 14265 { 14266 name: "MOVWstore", 14267 auxType: auxSymOff, 14268 argLen: 3, 14269 faultOnNilArg0: true, 14270 symEffect: SymWrite, 14271 asm: mips.AMOVW, 14272 reg: regInfo{ 14273 inputs: []inputInfo{ 14274 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14275 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14276 }, 14277 }, 14278 }, 14279 { 14280 name: "MOVFstore", 14281 auxType: auxSymOff, 14282 argLen: 3, 14283 faultOnNilArg0: true, 14284 symEffect: SymWrite, 14285 asm: mips.AMOVF, 14286 reg: regInfo{ 14287 inputs: []inputInfo{ 14288 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14289 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14290 }, 14291 }, 14292 }, 14293 { 14294 name: "MOVDstore", 14295 auxType: auxSymOff, 14296 argLen: 3, 14297 faultOnNilArg0: true, 14298 symEffect: SymWrite, 14299 asm: mips.AMOVD, 14300 reg: regInfo{ 14301 inputs: []inputInfo{ 14302 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14303 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14304 }, 14305 }, 14306 }, 14307 { 14308 name: "MOVBstorezero", 14309 auxType: auxSymOff, 14310 argLen: 2, 14311 faultOnNilArg0: true, 14312 symEffect: SymWrite, 14313 asm: mips.AMOVB, 14314 reg: regInfo{ 14315 inputs: []inputInfo{ 14316 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14317 }, 14318 }, 14319 }, 14320 { 14321 name: "MOVHstorezero", 14322 auxType: auxSymOff, 14323 argLen: 2, 14324 faultOnNilArg0: true, 14325 symEffect: SymWrite, 14326 asm: mips.AMOVH, 14327 reg: regInfo{ 14328 inputs: []inputInfo{ 14329 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14330 }, 14331 }, 14332 }, 14333 { 14334 name: "MOVWstorezero", 14335 auxType: auxSymOff, 14336 argLen: 2, 14337 faultOnNilArg0: true, 14338 symEffect: SymWrite, 14339 asm: mips.AMOVW, 14340 reg: regInfo{ 14341 inputs: []inputInfo{ 14342 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14343 }, 14344 }, 14345 }, 14346 { 14347 name: "MOVBreg", 14348 argLen: 1, 14349 asm: mips.AMOVB, 14350 reg: regInfo{ 14351 inputs: []inputInfo{ 14352 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14353 }, 14354 outputs: []outputInfo{ 14355 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14356 }, 14357 }, 14358 }, 14359 { 14360 name: "MOVBUreg", 14361 argLen: 1, 14362 asm: mips.AMOVBU, 14363 reg: regInfo{ 14364 inputs: []inputInfo{ 14365 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14366 }, 14367 outputs: []outputInfo{ 14368 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14369 }, 14370 }, 14371 }, 14372 { 14373 name: "MOVHreg", 14374 argLen: 1, 14375 asm: mips.AMOVH, 14376 reg: regInfo{ 14377 inputs: []inputInfo{ 14378 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14379 }, 14380 outputs: []outputInfo{ 14381 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14382 }, 14383 }, 14384 }, 14385 { 14386 name: "MOVHUreg", 14387 argLen: 1, 14388 asm: mips.AMOVHU, 14389 reg: regInfo{ 14390 inputs: []inputInfo{ 14391 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14392 }, 14393 outputs: []outputInfo{ 14394 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14395 }, 14396 }, 14397 }, 14398 { 14399 name: "MOVWreg", 14400 argLen: 1, 14401 asm: mips.AMOVW, 14402 reg: regInfo{ 14403 inputs: []inputInfo{ 14404 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14405 }, 14406 outputs: []outputInfo{ 14407 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14408 }, 14409 }, 14410 }, 14411 { 14412 name: "MOVWnop", 14413 argLen: 1, 14414 resultInArg0: true, 14415 reg: regInfo{ 14416 inputs: []inputInfo{ 14417 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14418 }, 14419 outputs: []outputInfo{ 14420 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14421 }, 14422 }, 14423 }, 14424 { 14425 name: "CMOVZ", 14426 argLen: 3, 14427 resultInArg0: true, 14428 asm: mips.ACMOVZ, 14429 reg: regInfo{ 14430 inputs: []inputInfo{ 14431 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14432 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14433 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14434 }, 14435 outputs: []outputInfo{ 14436 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14437 }, 14438 }, 14439 }, 14440 { 14441 name: "CMOVZzero", 14442 argLen: 2, 14443 resultInArg0: true, 14444 asm: mips.ACMOVZ, 14445 reg: regInfo{ 14446 inputs: []inputInfo{ 14447 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14448 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14449 }, 14450 outputs: []outputInfo{ 14451 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14452 }, 14453 }, 14454 }, 14455 { 14456 name: "MOVWF", 14457 argLen: 1, 14458 asm: mips.AMOVWF, 14459 reg: regInfo{ 14460 inputs: []inputInfo{ 14461 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14462 }, 14463 outputs: []outputInfo{ 14464 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14465 }, 14466 }, 14467 }, 14468 { 14469 name: "MOVWD", 14470 argLen: 1, 14471 asm: mips.AMOVWD, 14472 reg: regInfo{ 14473 inputs: []inputInfo{ 14474 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14475 }, 14476 outputs: []outputInfo{ 14477 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14478 }, 14479 }, 14480 }, 14481 { 14482 name: "TRUNCFW", 14483 argLen: 1, 14484 asm: mips.ATRUNCFW, 14485 reg: regInfo{ 14486 inputs: []inputInfo{ 14487 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14488 }, 14489 outputs: []outputInfo{ 14490 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14491 }, 14492 }, 14493 }, 14494 { 14495 name: "TRUNCDW", 14496 argLen: 1, 14497 asm: mips.ATRUNCDW, 14498 reg: regInfo{ 14499 inputs: []inputInfo{ 14500 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14501 }, 14502 outputs: []outputInfo{ 14503 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14504 }, 14505 }, 14506 }, 14507 { 14508 name: "MOVFD", 14509 argLen: 1, 14510 asm: mips.AMOVFD, 14511 reg: regInfo{ 14512 inputs: []inputInfo{ 14513 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14514 }, 14515 outputs: []outputInfo{ 14516 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14517 }, 14518 }, 14519 }, 14520 { 14521 name: "MOVDF", 14522 argLen: 1, 14523 asm: mips.AMOVDF, 14524 reg: regInfo{ 14525 inputs: []inputInfo{ 14526 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14527 }, 14528 outputs: []outputInfo{ 14529 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14530 }, 14531 }, 14532 }, 14533 { 14534 name: "CALLstatic", 14535 auxType: auxSymOff, 14536 argLen: 1, 14537 clobberFlags: true, 14538 call: true, 14539 symEffect: SymNone, 14540 reg: regInfo{ 14541 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14542 }, 14543 }, 14544 { 14545 name: "CALLclosure", 14546 auxType: auxInt64, 14547 argLen: 3, 14548 clobberFlags: true, 14549 call: true, 14550 reg: regInfo{ 14551 inputs: []inputInfo{ 14552 {1, 4194304}, // R22 14553 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 14554 }, 14555 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14556 }, 14557 }, 14558 { 14559 name: "CALLinter", 14560 auxType: auxInt64, 14561 argLen: 2, 14562 clobberFlags: true, 14563 call: true, 14564 reg: regInfo{ 14565 inputs: []inputInfo{ 14566 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14567 }, 14568 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14569 }, 14570 }, 14571 { 14572 name: "LoweredAtomicLoad", 14573 argLen: 2, 14574 faultOnNilArg0: true, 14575 reg: regInfo{ 14576 inputs: []inputInfo{ 14577 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14578 }, 14579 outputs: []outputInfo{ 14580 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14581 }, 14582 }, 14583 }, 14584 { 14585 name: "LoweredAtomicStore", 14586 argLen: 3, 14587 faultOnNilArg0: true, 14588 hasSideEffects: true, 14589 reg: regInfo{ 14590 inputs: []inputInfo{ 14591 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14592 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14593 }, 14594 }, 14595 }, 14596 { 14597 name: "LoweredAtomicStorezero", 14598 argLen: 2, 14599 faultOnNilArg0: true, 14600 hasSideEffects: true, 14601 reg: regInfo{ 14602 inputs: []inputInfo{ 14603 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14604 }, 14605 }, 14606 }, 14607 { 14608 name: "LoweredAtomicExchange", 14609 argLen: 3, 14610 resultNotInArgs: true, 14611 faultOnNilArg0: true, 14612 hasSideEffects: true, 14613 reg: regInfo{ 14614 inputs: []inputInfo{ 14615 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14616 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14617 }, 14618 outputs: []outputInfo{ 14619 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14620 }, 14621 }, 14622 }, 14623 { 14624 name: "LoweredAtomicAdd", 14625 argLen: 3, 14626 resultNotInArgs: true, 14627 faultOnNilArg0: true, 14628 hasSideEffects: true, 14629 reg: regInfo{ 14630 inputs: []inputInfo{ 14631 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14632 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14633 }, 14634 outputs: []outputInfo{ 14635 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14636 }, 14637 }, 14638 }, 14639 { 14640 name: "LoweredAtomicAddconst", 14641 auxType: auxInt32, 14642 argLen: 2, 14643 resultNotInArgs: true, 14644 faultOnNilArg0: true, 14645 hasSideEffects: true, 14646 reg: regInfo{ 14647 inputs: []inputInfo{ 14648 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14649 }, 14650 outputs: []outputInfo{ 14651 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14652 }, 14653 }, 14654 }, 14655 { 14656 name: "LoweredAtomicCas", 14657 argLen: 4, 14658 resultNotInArgs: true, 14659 faultOnNilArg0: true, 14660 hasSideEffects: true, 14661 reg: regInfo{ 14662 inputs: []inputInfo{ 14663 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14664 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14665 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14666 }, 14667 outputs: []outputInfo{ 14668 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14669 }, 14670 }, 14671 }, 14672 { 14673 name: "LoweredAtomicAnd", 14674 argLen: 3, 14675 faultOnNilArg0: true, 14676 hasSideEffects: true, 14677 asm: mips.AAND, 14678 reg: regInfo{ 14679 inputs: []inputInfo{ 14680 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14681 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14682 }, 14683 }, 14684 }, 14685 { 14686 name: "LoweredAtomicOr", 14687 argLen: 3, 14688 faultOnNilArg0: true, 14689 hasSideEffects: true, 14690 asm: mips.AOR, 14691 reg: regInfo{ 14692 inputs: []inputInfo{ 14693 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14694 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14695 }, 14696 }, 14697 }, 14698 { 14699 name: "LoweredZero", 14700 auxType: auxInt32, 14701 argLen: 3, 14702 faultOnNilArg0: true, 14703 reg: regInfo{ 14704 inputs: []inputInfo{ 14705 {0, 2}, // R1 14706 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14707 }, 14708 clobbers: 2, // R1 14709 }, 14710 }, 14711 { 14712 name: "LoweredMove", 14713 auxType: auxInt32, 14714 argLen: 4, 14715 faultOnNilArg0: true, 14716 faultOnNilArg1: true, 14717 reg: regInfo{ 14718 inputs: []inputInfo{ 14719 {0, 4}, // R2 14720 {1, 2}, // R1 14721 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14722 }, 14723 clobbers: 6, // R1 R2 14724 }, 14725 }, 14726 { 14727 name: "LoweredNilCheck", 14728 argLen: 2, 14729 nilCheck: true, 14730 faultOnNilArg0: true, 14731 reg: regInfo{ 14732 inputs: []inputInfo{ 14733 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14734 }, 14735 }, 14736 }, 14737 { 14738 name: "FPFlagTrue", 14739 argLen: 1, 14740 reg: regInfo{ 14741 outputs: []outputInfo{ 14742 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14743 }, 14744 }, 14745 }, 14746 { 14747 name: "FPFlagFalse", 14748 argLen: 1, 14749 reg: regInfo{ 14750 outputs: []outputInfo{ 14751 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14752 }, 14753 }, 14754 }, 14755 { 14756 name: "LoweredGetClosurePtr", 14757 argLen: 0, 14758 reg: regInfo{ 14759 outputs: []outputInfo{ 14760 {0, 4194304}, // R22 14761 }, 14762 }, 14763 }, 14764 { 14765 name: "MOVWconvert", 14766 argLen: 2, 14767 asm: mips.AMOVW, 14768 reg: regInfo{ 14769 inputs: []inputInfo{ 14770 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14771 }, 14772 outputs: []outputInfo{ 14773 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14774 }, 14775 }, 14776 }, 14777 14778 { 14779 name: "ADDV", 14780 argLen: 2, 14781 commutative: true, 14782 asm: mips.AADDVU, 14783 reg: regInfo{ 14784 inputs: []inputInfo{ 14785 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14786 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14787 }, 14788 outputs: []outputInfo{ 14789 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14790 }, 14791 }, 14792 }, 14793 { 14794 name: "ADDVconst", 14795 auxType: auxInt64, 14796 argLen: 1, 14797 asm: mips.AADDVU, 14798 reg: regInfo{ 14799 inputs: []inputInfo{ 14800 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 14801 }, 14802 outputs: []outputInfo{ 14803 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14804 }, 14805 }, 14806 }, 14807 { 14808 name: "SUBV", 14809 argLen: 2, 14810 asm: mips.ASUBVU, 14811 reg: regInfo{ 14812 inputs: []inputInfo{ 14813 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14814 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14815 }, 14816 outputs: []outputInfo{ 14817 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14818 }, 14819 }, 14820 }, 14821 { 14822 name: "SUBVconst", 14823 auxType: auxInt64, 14824 argLen: 1, 14825 asm: mips.ASUBVU, 14826 reg: regInfo{ 14827 inputs: []inputInfo{ 14828 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14829 }, 14830 outputs: []outputInfo{ 14831 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14832 }, 14833 }, 14834 }, 14835 { 14836 name: "MULV", 14837 argLen: 2, 14838 commutative: true, 14839 asm: mips.AMULV, 14840 reg: regInfo{ 14841 inputs: []inputInfo{ 14842 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14843 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14844 }, 14845 outputs: []outputInfo{ 14846 {0, 1152921504606846976}, // HI 14847 {1, 2305843009213693952}, // LO 14848 }, 14849 }, 14850 }, 14851 { 14852 name: "MULVU", 14853 argLen: 2, 14854 commutative: true, 14855 asm: mips.AMULVU, 14856 reg: regInfo{ 14857 inputs: []inputInfo{ 14858 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14859 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14860 }, 14861 outputs: []outputInfo{ 14862 {0, 1152921504606846976}, // HI 14863 {1, 2305843009213693952}, // LO 14864 }, 14865 }, 14866 }, 14867 { 14868 name: "DIVV", 14869 argLen: 2, 14870 asm: mips.ADIVV, 14871 reg: regInfo{ 14872 inputs: []inputInfo{ 14873 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14874 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14875 }, 14876 outputs: []outputInfo{ 14877 {0, 1152921504606846976}, // HI 14878 {1, 2305843009213693952}, // LO 14879 }, 14880 }, 14881 }, 14882 { 14883 name: "DIVVU", 14884 argLen: 2, 14885 asm: mips.ADIVVU, 14886 reg: regInfo{ 14887 inputs: []inputInfo{ 14888 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14889 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14890 }, 14891 outputs: []outputInfo{ 14892 {0, 1152921504606846976}, // HI 14893 {1, 2305843009213693952}, // LO 14894 }, 14895 }, 14896 }, 14897 { 14898 name: "ADDF", 14899 argLen: 2, 14900 commutative: true, 14901 asm: mips.AADDF, 14902 reg: regInfo{ 14903 inputs: []inputInfo{ 14904 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14905 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14906 }, 14907 outputs: []outputInfo{ 14908 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14909 }, 14910 }, 14911 }, 14912 { 14913 name: "ADDD", 14914 argLen: 2, 14915 commutative: true, 14916 asm: mips.AADDD, 14917 reg: regInfo{ 14918 inputs: []inputInfo{ 14919 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14920 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14921 }, 14922 outputs: []outputInfo{ 14923 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14924 }, 14925 }, 14926 }, 14927 { 14928 name: "SUBF", 14929 argLen: 2, 14930 asm: mips.ASUBF, 14931 reg: regInfo{ 14932 inputs: []inputInfo{ 14933 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14934 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14935 }, 14936 outputs: []outputInfo{ 14937 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14938 }, 14939 }, 14940 }, 14941 { 14942 name: "SUBD", 14943 argLen: 2, 14944 asm: mips.ASUBD, 14945 reg: regInfo{ 14946 inputs: []inputInfo{ 14947 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14948 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14949 }, 14950 outputs: []outputInfo{ 14951 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14952 }, 14953 }, 14954 }, 14955 { 14956 name: "MULF", 14957 argLen: 2, 14958 commutative: true, 14959 asm: mips.AMULF, 14960 reg: regInfo{ 14961 inputs: []inputInfo{ 14962 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14963 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14964 }, 14965 outputs: []outputInfo{ 14966 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14967 }, 14968 }, 14969 }, 14970 { 14971 name: "MULD", 14972 argLen: 2, 14973 commutative: true, 14974 asm: mips.AMULD, 14975 reg: regInfo{ 14976 inputs: []inputInfo{ 14977 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14978 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14979 }, 14980 outputs: []outputInfo{ 14981 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14982 }, 14983 }, 14984 }, 14985 { 14986 name: "DIVF", 14987 argLen: 2, 14988 asm: mips.ADIVF, 14989 reg: regInfo{ 14990 inputs: []inputInfo{ 14991 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14992 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14993 }, 14994 outputs: []outputInfo{ 14995 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14996 }, 14997 }, 14998 }, 14999 { 15000 name: "DIVD", 15001 argLen: 2, 15002 asm: mips.ADIVD, 15003 reg: regInfo{ 15004 inputs: []inputInfo{ 15005 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15006 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15007 }, 15008 outputs: []outputInfo{ 15009 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15010 }, 15011 }, 15012 }, 15013 { 15014 name: "AND", 15015 argLen: 2, 15016 commutative: true, 15017 asm: mips.AAND, 15018 reg: regInfo{ 15019 inputs: []inputInfo{ 15020 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15021 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15022 }, 15023 outputs: []outputInfo{ 15024 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15025 }, 15026 }, 15027 }, 15028 { 15029 name: "ANDconst", 15030 auxType: auxInt64, 15031 argLen: 1, 15032 asm: mips.AAND, 15033 reg: regInfo{ 15034 inputs: []inputInfo{ 15035 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15036 }, 15037 outputs: []outputInfo{ 15038 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15039 }, 15040 }, 15041 }, 15042 { 15043 name: "OR", 15044 argLen: 2, 15045 commutative: true, 15046 asm: mips.AOR, 15047 reg: regInfo{ 15048 inputs: []inputInfo{ 15049 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15050 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15051 }, 15052 outputs: []outputInfo{ 15053 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15054 }, 15055 }, 15056 }, 15057 { 15058 name: "ORconst", 15059 auxType: auxInt64, 15060 argLen: 1, 15061 asm: mips.AOR, 15062 reg: regInfo{ 15063 inputs: []inputInfo{ 15064 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15065 }, 15066 outputs: []outputInfo{ 15067 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15068 }, 15069 }, 15070 }, 15071 { 15072 name: "XOR", 15073 argLen: 2, 15074 commutative: true, 15075 asm: mips.AXOR, 15076 reg: regInfo{ 15077 inputs: []inputInfo{ 15078 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15079 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15080 }, 15081 outputs: []outputInfo{ 15082 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15083 }, 15084 }, 15085 }, 15086 { 15087 name: "XORconst", 15088 auxType: auxInt64, 15089 argLen: 1, 15090 asm: mips.AXOR, 15091 reg: regInfo{ 15092 inputs: []inputInfo{ 15093 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15094 }, 15095 outputs: []outputInfo{ 15096 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15097 }, 15098 }, 15099 }, 15100 { 15101 name: "NOR", 15102 argLen: 2, 15103 commutative: true, 15104 asm: mips.ANOR, 15105 reg: regInfo{ 15106 inputs: []inputInfo{ 15107 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15108 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15109 }, 15110 outputs: []outputInfo{ 15111 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15112 }, 15113 }, 15114 }, 15115 { 15116 name: "NORconst", 15117 auxType: auxInt64, 15118 argLen: 1, 15119 asm: mips.ANOR, 15120 reg: regInfo{ 15121 inputs: []inputInfo{ 15122 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15123 }, 15124 outputs: []outputInfo{ 15125 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15126 }, 15127 }, 15128 }, 15129 { 15130 name: "NEGV", 15131 argLen: 1, 15132 reg: regInfo{ 15133 inputs: []inputInfo{ 15134 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15135 }, 15136 outputs: []outputInfo{ 15137 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15138 }, 15139 }, 15140 }, 15141 { 15142 name: "NEGF", 15143 argLen: 1, 15144 asm: mips.ANEGF, 15145 reg: regInfo{ 15146 inputs: []inputInfo{ 15147 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15148 }, 15149 outputs: []outputInfo{ 15150 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15151 }, 15152 }, 15153 }, 15154 { 15155 name: "NEGD", 15156 argLen: 1, 15157 asm: mips.ANEGD, 15158 reg: regInfo{ 15159 inputs: []inputInfo{ 15160 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15161 }, 15162 outputs: []outputInfo{ 15163 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15164 }, 15165 }, 15166 }, 15167 { 15168 name: "SLLV", 15169 argLen: 2, 15170 asm: mips.ASLLV, 15171 reg: regInfo{ 15172 inputs: []inputInfo{ 15173 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15174 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15175 }, 15176 outputs: []outputInfo{ 15177 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15178 }, 15179 }, 15180 }, 15181 { 15182 name: "SLLVconst", 15183 auxType: auxInt64, 15184 argLen: 1, 15185 asm: mips.ASLLV, 15186 reg: regInfo{ 15187 inputs: []inputInfo{ 15188 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15189 }, 15190 outputs: []outputInfo{ 15191 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15192 }, 15193 }, 15194 }, 15195 { 15196 name: "SRLV", 15197 argLen: 2, 15198 asm: mips.ASRLV, 15199 reg: regInfo{ 15200 inputs: []inputInfo{ 15201 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15202 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15203 }, 15204 outputs: []outputInfo{ 15205 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15206 }, 15207 }, 15208 }, 15209 { 15210 name: "SRLVconst", 15211 auxType: auxInt64, 15212 argLen: 1, 15213 asm: mips.ASRLV, 15214 reg: regInfo{ 15215 inputs: []inputInfo{ 15216 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15217 }, 15218 outputs: []outputInfo{ 15219 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15220 }, 15221 }, 15222 }, 15223 { 15224 name: "SRAV", 15225 argLen: 2, 15226 asm: mips.ASRAV, 15227 reg: regInfo{ 15228 inputs: []inputInfo{ 15229 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15230 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15231 }, 15232 outputs: []outputInfo{ 15233 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15234 }, 15235 }, 15236 }, 15237 { 15238 name: "SRAVconst", 15239 auxType: auxInt64, 15240 argLen: 1, 15241 asm: mips.ASRAV, 15242 reg: regInfo{ 15243 inputs: []inputInfo{ 15244 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15245 }, 15246 outputs: []outputInfo{ 15247 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15248 }, 15249 }, 15250 }, 15251 { 15252 name: "SGT", 15253 argLen: 2, 15254 asm: mips.ASGT, 15255 reg: regInfo{ 15256 inputs: []inputInfo{ 15257 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15258 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15259 }, 15260 outputs: []outputInfo{ 15261 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15262 }, 15263 }, 15264 }, 15265 { 15266 name: "SGTconst", 15267 auxType: auxInt64, 15268 argLen: 1, 15269 asm: mips.ASGT, 15270 reg: regInfo{ 15271 inputs: []inputInfo{ 15272 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15273 }, 15274 outputs: []outputInfo{ 15275 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15276 }, 15277 }, 15278 }, 15279 { 15280 name: "SGTU", 15281 argLen: 2, 15282 asm: mips.ASGTU, 15283 reg: regInfo{ 15284 inputs: []inputInfo{ 15285 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15286 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15287 }, 15288 outputs: []outputInfo{ 15289 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15290 }, 15291 }, 15292 }, 15293 { 15294 name: "SGTUconst", 15295 auxType: auxInt64, 15296 argLen: 1, 15297 asm: mips.ASGTU, 15298 reg: regInfo{ 15299 inputs: []inputInfo{ 15300 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15301 }, 15302 outputs: []outputInfo{ 15303 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15304 }, 15305 }, 15306 }, 15307 { 15308 name: "CMPEQF", 15309 argLen: 2, 15310 asm: mips.ACMPEQF, 15311 reg: regInfo{ 15312 inputs: []inputInfo{ 15313 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15314 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15315 }, 15316 }, 15317 }, 15318 { 15319 name: "CMPEQD", 15320 argLen: 2, 15321 asm: mips.ACMPEQD, 15322 reg: regInfo{ 15323 inputs: []inputInfo{ 15324 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15325 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15326 }, 15327 }, 15328 }, 15329 { 15330 name: "CMPGEF", 15331 argLen: 2, 15332 asm: mips.ACMPGEF, 15333 reg: regInfo{ 15334 inputs: []inputInfo{ 15335 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15336 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15337 }, 15338 }, 15339 }, 15340 { 15341 name: "CMPGED", 15342 argLen: 2, 15343 asm: mips.ACMPGED, 15344 reg: regInfo{ 15345 inputs: []inputInfo{ 15346 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15347 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15348 }, 15349 }, 15350 }, 15351 { 15352 name: "CMPGTF", 15353 argLen: 2, 15354 asm: mips.ACMPGTF, 15355 reg: regInfo{ 15356 inputs: []inputInfo{ 15357 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15358 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15359 }, 15360 }, 15361 }, 15362 { 15363 name: "CMPGTD", 15364 argLen: 2, 15365 asm: mips.ACMPGTD, 15366 reg: regInfo{ 15367 inputs: []inputInfo{ 15368 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15369 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15370 }, 15371 }, 15372 }, 15373 { 15374 name: "MOVVconst", 15375 auxType: auxInt64, 15376 argLen: 0, 15377 rematerializeable: true, 15378 asm: mips.AMOVV, 15379 reg: regInfo{ 15380 outputs: []outputInfo{ 15381 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15382 }, 15383 }, 15384 }, 15385 { 15386 name: "MOVFconst", 15387 auxType: auxFloat64, 15388 argLen: 0, 15389 rematerializeable: true, 15390 asm: mips.AMOVF, 15391 reg: regInfo{ 15392 outputs: []outputInfo{ 15393 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15394 }, 15395 }, 15396 }, 15397 { 15398 name: "MOVDconst", 15399 auxType: auxFloat64, 15400 argLen: 0, 15401 rematerializeable: true, 15402 asm: mips.AMOVD, 15403 reg: regInfo{ 15404 outputs: []outputInfo{ 15405 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15406 }, 15407 }, 15408 }, 15409 { 15410 name: "MOVVaddr", 15411 auxType: auxSymOff, 15412 argLen: 1, 15413 rematerializeable: true, 15414 symEffect: SymAddr, 15415 asm: mips.AMOVV, 15416 reg: regInfo{ 15417 inputs: []inputInfo{ 15418 {0, 4611686018460942336}, // SP SB 15419 }, 15420 outputs: []outputInfo{ 15421 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15422 }, 15423 }, 15424 }, 15425 { 15426 name: "MOVBload", 15427 auxType: auxSymOff, 15428 argLen: 2, 15429 faultOnNilArg0: true, 15430 symEffect: SymRead, 15431 asm: mips.AMOVB, 15432 reg: regInfo{ 15433 inputs: []inputInfo{ 15434 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15435 }, 15436 outputs: []outputInfo{ 15437 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15438 }, 15439 }, 15440 }, 15441 { 15442 name: "MOVBUload", 15443 auxType: auxSymOff, 15444 argLen: 2, 15445 faultOnNilArg0: true, 15446 symEffect: SymRead, 15447 asm: mips.AMOVBU, 15448 reg: regInfo{ 15449 inputs: []inputInfo{ 15450 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15451 }, 15452 outputs: []outputInfo{ 15453 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15454 }, 15455 }, 15456 }, 15457 { 15458 name: "MOVHload", 15459 auxType: auxSymOff, 15460 argLen: 2, 15461 faultOnNilArg0: true, 15462 symEffect: SymRead, 15463 asm: mips.AMOVH, 15464 reg: regInfo{ 15465 inputs: []inputInfo{ 15466 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15467 }, 15468 outputs: []outputInfo{ 15469 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15470 }, 15471 }, 15472 }, 15473 { 15474 name: "MOVHUload", 15475 auxType: auxSymOff, 15476 argLen: 2, 15477 faultOnNilArg0: true, 15478 symEffect: SymRead, 15479 asm: mips.AMOVHU, 15480 reg: regInfo{ 15481 inputs: []inputInfo{ 15482 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15483 }, 15484 outputs: []outputInfo{ 15485 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15486 }, 15487 }, 15488 }, 15489 { 15490 name: "MOVWload", 15491 auxType: auxSymOff, 15492 argLen: 2, 15493 faultOnNilArg0: true, 15494 symEffect: SymRead, 15495 asm: mips.AMOVW, 15496 reg: regInfo{ 15497 inputs: []inputInfo{ 15498 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15499 }, 15500 outputs: []outputInfo{ 15501 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15502 }, 15503 }, 15504 }, 15505 { 15506 name: "MOVWUload", 15507 auxType: auxSymOff, 15508 argLen: 2, 15509 faultOnNilArg0: true, 15510 symEffect: SymRead, 15511 asm: mips.AMOVWU, 15512 reg: regInfo{ 15513 inputs: []inputInfo{ 15514 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15515 }, 15516 outputs: []outputInfo{ 15517 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15518 }, 15519 }, 15520 }, 15521 { 15522 name: "MOVVload", 15523 auxType: auxSymOff, 15524 argLen: 2, 15525 faultOnNilArg0: true, 15526 symEffect: SymRead, 15527 asm: mips.AMOVV, 15528 reg: regInfo{ 15529 inputs: []inputInfo{ 15530 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15531 }, 15532 outputs: []outputInfo{ 15533 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15534 }, 15535 }, 15536 }, 15537 { 15538 name: "MOVFload", 15539 auxType: auxSymOff, 15540 argLen: 2, 15541 faultOnNilArg0: true, 15542 symEffect: SymRead, 15543 asm: mips.AMOVF, 15544 reg: regInfo{ 15545 inputs: []inputInfo{ 15546 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15547 }, 15548 outputs: []outputInfo{ 15549 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15550 }, 15551 }, 15552 }, 15553 { 15554 name: "MOVDload", 15555 auxType: auxSymOff, 15556 argLen: 2, 15557 faultOnNilArg0: true, 15558 symEffect: SymRead, 15559 asm: mips.AMOVD, 15560 reg: regInfo{ 15561 inputs: []inputInfo{ 15562 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15563 }, 15564 outputs: []outputInfo{ 15565 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15566 }, 15567 }, 15568 }, 15569 { 15570 name: "MOVBstore", 15571 auxType: auxSymOff, 15572 argLen: 3, 15573 faultOnNilArg0: true, 15574 symEffect: SymWrite, 15575 asm: mips.AMOVB, 15576 reg: regInfo{ 15577 inputs: []inputInfo{ 15578 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15579 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15580 }, 15581 }, 15582 }, 15583 { 15584 name: "MOVHstore", 15585 auxType: auxSymOff, 15586 argLen: 3, 15587 faultOnNilArg0: true, 15588 symEffect: SymWrite, 15589 asm: mips.AMOVH, 15590 reg: regInfo{ 15591 inputs: []inputInfo{ 15592 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15593 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15594 }, 15595 }, 15596 }, 15597 { 15598 name: "MOVWstore", 15599 auxType: auxSymOff, 15600 argLen: 3, 15601 faultOnNilArg0: true, 15602 symEffect: SymWrite, 15603 asm: mips.AMOVW, 15604 reg: regInfo{ 15605 inputs: []inputInfo{ 15606 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15607 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15608 }, 15609 }, 15610 }, 15611 { 15612 name: "MOVVstore", 15613 auxType: auxSymOff, 15614 argLen: 3, 15615 faultOnNilArg0: true, 15616 symEffect: SymWrite, 15617 asm: mips.AMOVV, 15618 reg: regInfo{ 15619 inputs: []inputInfo{ 15620 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15621 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15622 }, 15623 }, 15624 }, 15625 { 15626 name: "MOVFstore", 15627 auxType: auxSymOff, 15628 argLen: 3, 15629 faultOnNilArg0: true, 15630 symEffect: SymWrite, 15631 asm: mips.AMOVF, 15632 reg: regInfo{ 15633 inputs: []inputInfo{ 15634 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15635 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15636 }, 15637 }, 15638 }, 15639 { 15640 name: "MOVDstore", 15641 auxType: auxSymOff, 15642 argLen: 3, 15643 faultOnNilArg0: true, 15644 symEffect: SymWrite, 15645 asm: mips.AMOVD, 15646 reg: regInfo{ 15647 inputs: []inputInfo{ 15648 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15649 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15650 }, 15651 }, 15652 }, 15653 { 15654 name: "MOVBstorezero", 15655 auxType: auxSymOff, 15656 argLen: 2, 15657 faultOnNilArg0: true, 15658 symEffect: SymWrite, 15659 asm: mips.AMOVB, 15660 reg: regInfo{ 15661 inputs: []inputInfo{ 15662 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15663 }, 15664 }, 15665 }, 15666 { 15667 name: "MOVHstorezero", 15668 auxType: auxSymOff, 15669 argLen: 2, 15670 faultOnNilArg0: true, 15671 symEffect: SymWrite, 15672 asm: mips.AMOVH, 15673 reg: regInfo{ 15674 inputs: []inputInfo{ 15675 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15676 }, 15677 }, 15678 }, 15679 { 15680 name: "MOVWstorezero", 15681 auxType: auxSymOff, 15682 argLen: 2, 15683 faultOnNilArg0: true, 15684 symEffect: SymWrite, 15685 asm: mips.AMOVW, 15686 reg: regInfo{ 15687 inputs: []inputInfo{ 15688 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15689 }, 15690 }, 15691 }, 15692 { 15693 name: "MOVVstorezero", 15694 auxType: auxSymOff, 15695 argLen: 2, 15696 faultOnNilArg0: true, 15697 symEffect: SymWrite, 15698 asm: mips.AMOVV, 15699 reg: regInfo{ 15700 inputs: []inputInfo{ 15701 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15702 }, 15703 }, 15704 }, 15705 { 15706 name: "MOVBreg", 15707 argLen: 1, 15708 asm: mips.AMOVB, 15709 reg: regInfo{ 15710 inputs: []inputInfo{ 15711 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15712 }, 15713 outputs: []outputInfo{ 15714 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15715 }, 15716 }, 15717 }, 15718 { 15719 name: "MOVBUreg", 15720 argLen: 1, 15721 asm: mips.AMOVBU, 15722 reg: regInfo{ 15723 inputs: []inputInfo{ 15724 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15725 }, 15726 outputs: []outputInfo{ 15727 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15728 }, 15729 }, 15730 }, 15731 { 15732 name: "MOVHreg", 15733 argLen: 1, 15734 asm: mips.AMOVH, 15735 reg: regInfo{ 15736 inputs: []inputInfo{ 15737 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15738 }, 15739 outputs: []outputInfo{ 15740 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15741 }, 15742 }, 15743 }, 15744 { 15745 name: "MOVHUreg", 15746 argLen: 1, 15747 asm: mips.AMOVHU, 15748 reg: regInfo{ 15749 inputs: []inputInfo{ 15750 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15751 }, 15752 outputs: []outputInfo{ 15753 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15754 }, 15755 }, 15756 }, 15757 { 15758 name: "MOVWreg", 15759 argLen: 1, 15760 asm: mips.AMOVW, 15761 reg: regInfo{ 15762 inputs: []inputInfo{ 15763 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15764 }, 15765 outputs: []outputInfo{ 15766 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15767 }, 15768 }, 15769 }, 15770 { 15771 name: "MOVWUreg", 15772 argLen: 1, 15773 asm: mips.AMOVWU, 15774 reg: regInfo{ 15775 inputs: []inputInfo{ 15776 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15777 }, 15778 outputs: []outputInfo{ 15779 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15780 }, 15781 }, 15782 }, 15783 { 15784 name: "MOVVreg", 15785 argLen: 1, 15786 asm: mips.AMOVV, 15787 reg: regInfo{ 15788 inputs: []inputInfo{ 15789 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15790 }, 15791 outputs: []outputInfo{ 15792 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15793 }, 15794 }, 15795 }, 15796 { 15797 name: "MOVVnop", 15798 argLen: 1, 15799 resultInArg0: true, 15800 reg: regInfo{ 15801 inputs: []inputInfo{ 15802 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15803 }, 15804 outputs: []outputInfo{ 15805 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15806 }, 15807 }, 15808 }, 15809 { 15810 name: "MOVWF", 15811 argLen: 1, 15812 asm: mips.AMOVWF, 15813 reg: regInfo{ 15814 inputs: []inputInfo{ 15815 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15816 }, 15817 outputs: []outputInfo{ 15818 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15819 }, 15820 }, 15821 }, 15822 { 15823 name: "MOVWD", 15824 argLen: 1, 15825 asm: mips.AMOVWD, 15826 reg: regInfo{ 15827 inputs: []inputInfo{ 15828 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15829 }, 15830 outputs: []outputInfo{ 15831 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15832 }, 15833 }, 15834 }, 15835 { 15836 name: "MOVVF", 15837 argLen: 1, 15838 asm: mips.AMOVVF, 15839 reg: regInfo{ 15840 inputs: []inputInfo{ 15841 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15842 }, 15843 outputs: []outputInfo{ 15844 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15845 }, 15846 }, 15847 }, 15848 { 15849 name: "MOVVD", 15850 argLen: 1, 15851 asm: mips.AMOVVD, 15852 reg: regInfo{ 15853 inputs: []inputInfo{ 15854 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15855 }, 15856 outputs: []outputInfo{ 15857 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15858 }, 15859 }, 15860 }, 15861 { 15862 name: "TRUNCFW", 15863 argLen: 1, 15864 asm: mips.ATRUNCFW, 15865 reg: regInfo{ 15866 inputs: []inputInfo{ 15867 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15868 }, 15869 outputs: []outputInfo{ 15870 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15871 }, 15872 }, 15873 }, 15874 { 15875 name: "TRUNCDW", 15876 argLen: 1, 15877 asm: mips.ATRUNCDW, 15878 reg: regInfo{ 15879 inputs: []inputInfo{ 15880 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15881 }, 15882 outputs: []outputInfo{ 15883 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15884 }, 15885 }, 15886 }, 15887 { 15888 name: "TRUNCFV", 15889 argLen: 1, 15890 asm: mips.ATRUNCFV, 15891 reg: regInfo{ 15892 inputs: []inputInfo{ 15893 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15894 }, 15895 outputs: []outputInfo{ 15896 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15897 }, 15898 }, 15899 }, 15900 { 15901 name: "TRUNCDV", 15902 argLen: 1, 15903 asm: mips.ATRUNCDV, 15904 reg: regInfo{ 15905 inputs: []inputInfo{ 15906 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15907 }, 15908 outputs: []outputInfo{ 15909 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15910 }, 15911 }, 15912 }, 15913 { 15914 name: "MOVFD", 15915 argLen: 1, 15916 asm: mips.AMOVFD, 15917 reg: regInfo{ 15918 inputs: []inputInfo{ 15919 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15920 }, 15921 outputs: []outputInfo{ 15922 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15923 }, 15924 }, 15925 }, 15926 { 15927 name: "MOVDF", 15928 argLen: 1, 15929 asm: mips.AMOVDF, 15930 reg: regInfo{ 15931 inputs: []inputInfo{ 15932 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15933 }, 15934 outputs: []outputInfo{ 15935 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15936 }, 15937 }, 15938 }, 15939 { 15940 name: "CALLstatic", 15941 auxType: auxSymOff, 15942 argLen: 1, 15943 clobberFlags: true, 15944 call: true, 15945 symEffect: SymNone, 15946 reg: regInfo{ 15947 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15948 }, 15949 }, 15950 { 15951 name: "CALLclosure", 15952 auxType: auxInt64, 15953 argLen: 3, 15954 clobberFlags: true, 15955 call: true, 15956 reg: regInfo{ 15957 inputs: []inputInfo{ 15958 {1, 4194304}, // R22 15959 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 15960 }, 15961 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15962 }, 15963 }, 15964 { 15965 name: "CALLinter", 15966 auxType: auxInt64, 15967 argLen: 2, 15968 clobberFlags: true, 15969 call: true, 15970 reg: regInfo{ 15971 inputs: []inputInfo{ 15972 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15973 }, 15974 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15975 }, 15976 }, 15977 { 15978 name: "DUFFZERO", 15979 auxType: auxInt64, 15980 argLen: 2, 15981 faultOnNilArg0: true, 15982 reg: regInfo{ 15983 inputs: []inputInfo{ 15984 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15985 }, 15986 clobbers: 134217730, // R1 R31 15987 }, 15988 }, 15989 { 15990 name: "LoweredZero", 15991 auxType: auxInt64, 15992 argLen: 3, 15993 clobberFlags: true, 15994 faultOnNilArg0: true, 15995 reg: regInfo{ 15996 inputs: []inputInfo{ 15997 {0, 2}, // R1 15998 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15999 }, 16000 clobbers: 2, // R1 16001 }, 16002 }, 16003 { 16004 name: "LoweredMove", 16005 auxType: auxInt64, 16006 argLen: 4, 16007 clobberFlags: true, 16008 faultOnNilArg0: true, 16009 faultOnNilArg1: true, 16010 reg: regInfo{ 16011 inputs: []inputInfo{ 16012 {0, 4}, // R2 16013 {1, 2}, // R1 16014 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16015 }, 16016 clobbers: 6, // R1 R2 16017 }, 16018 }, 16019 { 16020 name: "LoweredNilCheck", 16021 argLen: 2, 16022 nilCheck: true, 16023 faultOnNilArg0: true, 16024 reg: regInfo{ 16025 inputs: []inputInfo{ 16026 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16027 }, 16028 }, 16029 }, 16030 { 16031 name: "FPFlagTrue", 16032 argLen: 1, 16033 reg: regInfo{ 16034 outputs: []outputInfo{ 16035 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16036 }, 16037 }, 16038 }, 16039 { 16040 name: "FPFlagFalse", 16041 argLen: 1, 16042 reg: regInfo{ 16043 outputs: []outputInfo{ 16044 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16045 }, 16046 }, 16047 }, 16048 { 16049 name: "LoweredGetClosurePtr", 16050 argLen: 0, 16051 reg: regInfo{ 16052 outputs: []outputInfo{ 16053 {0, 4194304}, // R22 16054 }, 16055 }, 16056 }, 16057 { 16058 name: "MOVVconvert", 16059 argLen: 2, 16060 asm: mips.AMOVV, 16061 reg: regInfo{ 16062 inputs: []inputInfo{ 16063 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16064 }, 16065 outputs: []outputInfo{ 16066 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16067 }, 16068 }, 16069 }, 16070 16071 { 16072 name: "ADD", 16073 argLen: 2, 16074 commutative: true, 16075 asm: ppc64.AADD, 16076 reg: regInfo{ 16077 inputs: []inputInfo{ 16078 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16079 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16080 }, 16081 outputs: []outputInfo{ 16082 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16083 }, 16084 }, 16085 }, 16086 { 16087 name: "ADDconst", 16088 auxType: auxSymOff, 16089 argLen: 1, 16090 symEffect: SymAddr, 16091 asm: ppc64.AADD, 16092 reg: regInfo{ 16093 inputs: []inputInfo{ 16094 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16095 }, 16096 outputs: []outputInfo{ 16097 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16098 }, 16099 }, 16100 }, 16101 { 16102 name: "FADD", 16103 argLen: 2, 16104 commutative: true, 16105 asm: ppc64.AFADD, 16106 reg: regInfo{ 16107 inputs: []inputInfo{ 16108 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16109 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16110 }, 16111 outputs: []outputInfo{ 16112 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16113 }, 16114 }, 16115 }, 16116 { 16117 name: "FADDS", 16118 argLen: 2, 16119 commutative: true, 16120 asm: ppc64.AFADDS, 16121 reg: regInfo{ 16122 inputs: []inputInfo{ 16123 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16124 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16125 }, 16126 outputs: []outputInfo{ 16127 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16128 }, 16129 }, 16130 }, 16131 { 16132 name: "SUB", 16133 argLen: 2, 16134 asm: ppc64.ASUB, 16135 reg: regInfo{ 16136 inputs: []inputInfo{ 16137 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16138 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16139 }, 16140 outputs: []outputInfo{ 16141 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16142 }, 16143 }, 16144 }, 16145 { 16146 name: "FSUB", 16147 argLen: 2, 16148 asm: ppc64.AFSUB, 16149 reg: regInfo{ 16150 inputs: []inputInfo{ 16151 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16152 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16153 }, 16154 outputs: []outputInfo{ 16155 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16156 }, 16157 }, 16158 }, 16159 { 16160 name: "FSUBS", 16161 argLen: 2, 16162 asm: ppc64.AFSUBS, 16163 reg: regInfo{ 16164 inputs: []inputInfo{ 16165 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16166 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16167 }, 16168 outputs: []outputInfo{ 16169 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16170 }, 16171 }, 16172 }, 16173 { 16174 name: "MULLD", 16175 argLen: 2, 16176 commutative: true, 16177 asm: ppc64.AMULLD, 16178 reg: regInfo{ 16179 inputs: []inputInfo{ 16180 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16181 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16182 }, 16183 outputs: []outputInfo{ 16184 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16185 }, 16186 }, 16187 }, 16188 { 16189 name: "MULLW", 16190 argLen: 2, 16191 commutative: true, 16192 asm: ppc64.AMULLW, 16193 reg: regInfo{ 16194 inputs: []inputInfo{ 16195 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16196 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16197 }, 16198 outputs: []outputInfo{ 16199 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16200 }, 16201 }, 16202 }, 16203 { 16204 name: "MULHD", 16205 argLen: 2, 16206 commutative: true, 16207 asm: ppc64.AMULHD, 16208 reg: regInfo{ 16209 inputs: []inputInfo{ 16210 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16211 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16212 }, 16213 outputs: []outputInfo{ 16214 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16215 }, 16216 }, 16217 }, 16218 { 16219 name: "MULHW", 16220 argLen: 2, 16221 commutative: true, 16222 asm: ppc64.AMULHW, 16223 reg: regInfo{ 16224 inputs: []inputInfo{ 16225 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16226 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16227 }, 16228 outputs: []outputInfo{ 16229 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16230 }, 16231 }, 16232 }, 16233 { 16234 name: "MULHDU", 16235 argLen: 2, 16236 commutative: true, 16237 asm: ppc64.AMULHDU, 16238 reg: regInfo{ 16239 inputs: []inputInfo{ 16240 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16241 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16242 }, 16243 outputs: []outputInfo{ 16244 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16245 }, 16246 }, 16247 }, 16248 { 16249 name: "MULHWU", 16250 argLen: 2, 16251 commutative: true, 16252 asm: ppc64.AMULHWU, 16253 reg: regInfo{ 16254 inputs: []inputInfo{ 16255 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16256 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16257 }, 16258 outputs: []outputInfo{ 16259 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16260 }, 16261 }, 16262 }, 16263 { 16264 name: "FMUL", 16265 argLen: 2, 16266 commutative: true, 16267 asm: ppc64.AFMUL, 16268 reg: regInfo{ 16269 inputs: []inputInfo{ 16270 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16271 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16272 }, 16273 outputs: []outputInfo{ 16274 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16275 }, 16276 }, 16277 }, 16278 { 16279 name: "FMULS", 16280 argLen: 2, 16281 commutative: true, 16282 asm: ppc64.AFMULS, 16283 reg: regInfo{ 16284 inputs: []inputInfo{ 16285 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16286 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16287 }, 16288 outputs: []outputInfo{ 16289 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16290 }, 16291 }, 16292 }, 16293 { 16294 name: "FMADD", 16295 argLen: 3, 16296 asm: ppc64.AFMADD, 16297 reg: regInfo{ 16298 inputs: []inputInfo{ 16299 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16300 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16301 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16302 }, 16303 outputs: []outputInfo{ 16304 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16305 }, 16306 }, 16307 }, 16308 { 16309 name: "FMADDS", 16310 argLen: 3, 16311 asm: ppc64.AFMADDS, 16312 reg: regInfo{ 16313 inputs: []inputInfo{ 16314 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16315 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16316 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16317 }, 16318 outputs: []outputInfo{ 16319 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16320 }, 16321 }, 16322 }, 16323 { 16324 name: "FMSUB", 16325 argLen: 3, 16326 asm: ppc64.AFMSUB, 16327 reg: regInfo{ 16328 inputs: []inputInfo{ 16329 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16330 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16331 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16332 }, 16333 outputs: []outputInfo{ 16334 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16335 }, 16336 }, 16337 }, 16338 { 16339 name: "FMSUBS", 16340 argLen: 3, 16341 asm: ppc64.AFMSUBS, 16342 reg: regInfo{ 16343 inputs: []inputInfo{ 16344 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16345 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16346 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16347 }, 16348 outputs: []outputInfo{ 16349 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16350 }, 16351 }, 16352 }, 16353 { 16354 name: "SRAD", 16355 argLen: 2, 16356 asm: ppc64.ASRAD, 16357 reg: regInfo{ 16358 inputs: []inputInfo{ 16359 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16360 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16361 }, 16362 outputs: []outputInfo{ 16363 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16364 }, 16365 }, 16366 }, 16367 { 16368 name: "SRAW", 16369 argLen: 2, 16370 asm: ppc64.ASRAW, 16371 reg: regInfo{ 16372 inputs: []inputInfo{ 16373 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16374 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16375 }, 16376 outputs: []outputInfo{ 16377 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16378 }, 16379 }, 16380 }, 16381 { 16382 name: "SRD", 16383 argLen: 2, 16384 asm: ppc64.ASRD, 16385 reg: regInfo{ 16386 inputs: []inputInfo{ 16387 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16388 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16389 }, 16390 outputs: []outputInfo{ 16391 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16392 }, 16393 }, 16394 }, 16395 { 16396 name: "SRW", 16397 argLen: 2, 16398 asm: ppc64.ASRW, 16399 reg: regInfo{ 16400 inputs: []inputInfo{ 16401 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16402 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16403 }, 16404 outputs: []outputInfo{ 16405 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16406 }, 16407 }, 16408 }, 16409 { 16410 name: "SLD", 16411 argLen: 2, 16412 asm: ppc64.ASLD, 16413 reg: regInfo{ 16414 inputs: []inputInfo{ 16415 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16416 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16417 }, 16418 outputs: []outputInfo{ 16419 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16420 }, 16421 }, 16422 }, 16423 { 16424 name: "SLW", 16425 argLen: 2, 16426 asm: ppc64.ASLW, 16427 reg: regInfo{ 16428 inputs: []inputInfo{ 16429 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16430 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16431 }, 16432 outputs: []outputInfo{ 16433 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16434 }, 16435 }, 16436 }, 16437 { 16438 name: "ADDconstForCarry", 16439 auxType: auxInt16, 16440 argLen: 1, 16441 asm: ppc64.AADDC, 16442 reg: regInfo{ 16443 inputs: []inputInfo{ 16444 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16445 }, 16446 clobbers: 2147483648, // R31 16447 }, 16448 }, 16449 { 16450 name: "MaskIfNotCarry", 16451 argLen: 1, 16452 asm: ppc64.AADDME, 16453 reg: regInfo{ 16454 outputs: []outputInfo{ 16455 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16456 }, 16457 }, 16458 }, 16459 { 16460 name: "SRADconst", 16461 auxType: auxInt64, 16462 argLen: 1, 16463 asm: ppc64.ASRAD, 16464 reg: regInfo{ 16465 inputs: []inputInfo{ 16466 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16467 }, 16468 outputs: []outputInfo{ 16469 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16470 }, 16471 }, 16472 }, 16473 { 16474 name: "SRAWconst", 16475 auxType: auxInt64, 16476 argLen: 1, 16477 asm: ppc64.ASRAW, 16478 reg: regInfo{ 16479 inputs: []inputInfo{ 16480 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16481 }, 16482 outputs: []outputInfo{ 16483 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16484 }, 16485 }, 16486 }, 16487 { 16488 name: "SRDconst", 16489 auxType: auxInt64, 16490 argLen: 1, 16491 asm: ppc64.ASRD, 16492 reg: regInfo{ 16493 inputs: []inputInfo{ 16494 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16495 }, 16496 outputs: []outputInfo{ 16497 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16498 }, 16499 }, 16500 }, 16501 { 16502 name: "SRWconst", 16503 auxType: auxInt64, 16504 argLen: 1, 16505 asm: ppc64.ASRW, 16506 reg: regInfo{ 16507 inputs: []inputInfo{ 16508 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16509 }, 16510 outputs: []outputInfo{ 16511 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16512 }, 16513 }, 16514 }, 16515 { 16516 name: "SLDconst", 16517 auxType: auxInt64, 16518 argLen: 1, 16519 asm: ppc64.ASLD, 16520 reg: regInfo{ 16521 inputs: []inputInfo{ 16522 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16523 }, 16524 outputs: []outputInfo{ 16525 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16526 }, 16527 }, 16528 }, 16529 { 16530 name: "SLWconst", 16531 auxType: auxInt64, 16532 argLen: 1, 16533 asm: ppc64.ASLW, 16534 reg: regInfo{ 16535 inputs: []inputInfo{ 16536 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16537 }, 16538 outputs: []outputInfo{ 16539 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16540 }, 16541 }, 16542 }, 16543 { 16544 name: "ROTLconst", 16545 auxType: auxInt64, 16546 argLen: 1, 16547 asm: ppc64.AROTL, 16548 reg: regInfo{ 16549 inputs: []inputInfo{ 16550 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16551 }, 16552 outputs: []outputInfo{ 16553 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16554 }, 16555 }, 16556 }, 16557 { 16558 name: "ROTLWconst", 16559 auxType: auxInt64, 16560 argLen: 1, 16561 asm: ppc64.AROTLW, 16562 reg: regInfo{ 16563 inputs: []inputInfo{ 16564 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16565 }, 16566 outputs: []outputInfo{ 16567 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16568 }, 16569 }, 16570 }, 16571 { 16572 name: "FDIV", 16573 argLen: 2, 16574 asm: ppc64.AFDIV, 16575 reg: regInfo{ 16576 inputs: []inputInfo{ 16577 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16578 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16579 }, 16580 outputs: []outputInfo{ 16581 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16582 }, 16583 }, 16584 }, 16585 { 16586 name: "FDIVS", 16587 argLen: 2, 16588 asm: ppc64.AFDIVS, 16589 reg: regInfo{ 16590 inputs: []inputInfo{ 16591 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16592 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16593 }, 16594 outputs: []outputInfo{ 16595 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16596 }, 16597 }, 16598 }, 16599 { 16600 name: "DIVD", 16601 argLen: 2, 16602 asm: ppc64.ADIVD, 16603 reg: regInfo{ 16604 inputs: []inputInfo{ 16605 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16606 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16607 }, 16608 outputs: []outputInfo{ 16609 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16610 }, 16611 }, 16612 }, 16613 { 16614 name: "DIVW", 16615 argLen: 2, 16616 asm: ppc64.ADIVW, 16617 reg: regInfo{ 16618 inputs: []inputInfo{ 16619 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16620 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16621 }, 16622 outputs: []outputInfo{ 16623 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16624 }, 16625 }, 16626 }, 16627 { 16628 name: "DIVDU", 16629 argLen: 2, 16630 asm: ppc64.ADIVDU, 16631 reg: regInfo{ 16632 inputs: []inputInfo{ 16633 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16634 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16635 }, 16636 outputs: []outputInfo{ 16637 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16638 }, 16639 }, 16640 }, 16641 { 16642 name: "DIVWU", 16643 argLen: 2, 16644 asm: ppc64.ADIVWU, 16645 reg: regInfo{ 16646 inputs: []inputInfo{ 16647 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16648 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16649 }, 16650 outputs: []outputInfo{ 16651 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16652 }, 16653 }, 16654 }, 16655 { 16656 name: "FCTIDZ", 16657 argLen: 1, 16658 asm: ppc64.AFCTIDZ, 16659 reg: regInfo{ 16660 inputs: []inputInfo{ 16661 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16662 }, 16663 outputs: []outputInfo{ 16664 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16665 }, 16666 }, 16667 }, 16668 { 16669 name: "FCTIWZ", 16670 argLen: 1, 16671 asm: ppc64.AFCTIWZ, 16672 reg: regInfo{ 16673 inputs: []inputInfo{ 16674 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16675 }, 16676 outputs: []outputInfo{ 16677 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16678 }, 16679 }, 16680 }, 16681 { 16682 name: "FCFID", 16683 argLen: 1, 16684 asm: ppc64.AFCFID, 16685 reg: regInfo{ 16686 inputs: []inputInfo{ 16687 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16688 }, 16689 outputs: []outputInfo{ 16690 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16691 }, 16692 }, 16693 }, 16694 { 16695 name: "FRSP", 16696 argLen: 1, 16697 asm: ppc64.AFRSP, 16698 reg: regInfo{ 16699 inputs: []inputInfo{ 16700 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16701 }, 16702 outputs: []outputInfo{ 16703 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16704 }, 16705 }, 16706 }, 16707 { 16708 name: "Xf2i64", 16709 argLen: 1, 16710 reg: regInfo{ 16711 inputs: []inputInfo{ 16712 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16713 }, 16714 outputs: []outputInfo{ 16715 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16716 }, 16717 }, 16718 }, 16719 { 16720 name: "Xi2f64", 16721 argLen: 1, 16722 reg: regInfo{ 16723 inputs: []inputInfo{ 16724 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16725 }, 16726 outputs: []outputInfo{ 16727 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16728 }, 16729 }, 16730 }, 16731 { 16732 name: "AND", 16733 argLen: 2, 16734 commutative: true, 16735 asm: ppc64.AAND, 16736 reg: regInfo{ 16737 inputs: []inputInfo{ 16738 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16739 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16740 }, 16741 outputs: []outputInfo{ 16742 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16743 }, 16744 }, 16745 }, 16746 { 16747 name: "ANDN", 16748 argLen: 2, 16749 asm: ppc64.AANDN, 16750 reg: regInfo{ 16751 inputs: []inputInfo{ 16752 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16753 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16754 }, 16755 outputs: []outputInfo{ 16756 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16757 }, 16758 }, 16759 }, 16760 { 16761 name: "OR", 16762 argLen: 2, 16763 commutative: true, 16764 asm: ppc64.AOR, 16765 reg: regInfo{ 16766 inputs: []inputInfo{ 16767 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16768 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16769 }, 16770 outputs: []outputInfo{ 16771 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16772 }, 16773 }, 16774 }, 16775 { 16776 name: "ORN", 16777 argLen: 2, 16778 asm: ppc64.AORN, 16779 reg: regInfo{ 16780 inputs: []inputInfo{ 16781 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16782 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16783 }, 16784 outputs: []outputInfo{ 16785 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16786 }, 16787 }, 16788 }, 16789 { 16790 name: "NOR", 16791 argLen: 2, 16792 commutative: true, 16793 asm: ppc64.ANOR, 16794 reg: regInfo{ 16795 inputs: []inputInfo{ 16796 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16797 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16798 }, 16799 outputs: []outputInfo{ 16800 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16801 }, 16802 }, 16803 }, 16804 { 16805 name: "XOR", 16806 argLen: 2, 16807 commutative: true, 16808 asm: ppc64.AXOR, 16809 reg: regInfo{ 16810 inputs: []inputInfo{ 16811 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16812 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16813 }, 16814 outputs: []outputInfo{ 16815 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16816 }, 16817 }, 16818 }, 16819 { 16820 name: "EQV", 16821 argLen: 2, 16822 commutative: true, 16823 asm: ppc64.AEQV, 16824 reg: regInfo{ 16825 inputs: []inputInfo{ 16826 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16827 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16828 }, 16829 outputs: []outputInfo{ 16830 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16831 }, 16832 }, 16833 }, 16834 { 16835 name: "NEG", 16836 argLen: 1, 16837 asm: ppc64.ANEG, 16838 reg: regInfo{ 16839 inputs: []inputInfo{ 16840 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16841 }, 16842 outputs: []outputInfo{ 16843 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16844 }, 16845 }, 16846 }, 16847 { 16848 name: "FNEG", 16849 argLen: 1, 16850 asm: ppc64.AFNEG, 16851 reg: regInfo{ 16852 inputs: []inputInfo{ 16853 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16854 }, 16855 outputs: []outputInfo{ 16856 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16857 }, 16858 }, 16859 }, 16860 { 16861 name: "FSQRT", 16862 argLen: 1, 16863 asm: ppc64.AFSQRT, 16864 reg: regInfo{ 16865 inputs: []inputInfo{ 16866 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16867 }, 16868 outputs: []outputInfo{ 16869 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16870 }, 16871 }, 16872 }, 16873 { 16874 name: "FSQRTS", 16875 argLen: 1, 16876 asm: ppc64.AFSQRTS, 16877 reg: regInfo{ 16878 inputs: []inputInfo{ 16879 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16880 }, 16881 outputs: []outputInfo{ 16882 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16883 }, 16884 }, 16885 }, 16886 { 16887 name: "ORconst", 16888 auxType: auxInt64, 16889 argLen: 1, 16890 asm: ppc64.AOR, 16891 reg: regInfo{ 16892 inputs: []inputInfo{ 16893 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16894 }, 16895 outputs: []outputInfo{ 16896 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16897 }, 16898 }, 16899 }, 16900 { 16901 name: "XORconst", 16902 auxType: auxInt64, 16903 argLen: 1, 16904 asm: ppc64.AXOR, 16905 reg: regInfo{ 16906 inputs: []inputInfo{ 16907 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16908 }, 16909 outputs: []outputInfo{ 16910 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16911 }, 16912 }, 16913 }, 16914 { 16915 name: "ANDconst", 16916 auxType: auxInt64, 16917 argLen: 1, 16918 clobberFlags: true, 16919 asm: ppc64.AANDCC, 16920 reg: regInfo{ 16921 inputs: []inputInfo{ 16922 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16923 }, 16924 outputs: []outputInfo{ 16925 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16926 }, 16927 }, 16928 }, 16929 { 16930 name: "ANDCCconst", 16931 auxType: auxInt64, 16932 argLen: 1, 16933 asm: ppc64.AANDCC, 16934 reg: regInfo{ 16935 inputs: []inputInfo{ 16936 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16937 }, 16938 }, 16939 }, 16940 { 16941 name: "MOVBreg", 16942 argLen: 1, 16943 asm: ppc64.AMOVB, 16944 reg: regInfo{ 16945 inputs: []inputInfo{ 16946 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16947 }, 16948 outputs: []outputInfo{ 16949 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16950 }, 16951 }, 16952 }, 16953 { 16954 name: "MOVBZreg", 16955 argLen: 1, 16956 asm: ppc64.AMOVBZ, 16957 reg: regInfo{ 16958 inputs: []inputInfo{ 16959 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16960 }, 16961 outputs: []outputInfo{ 16962 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16963 }, 16964 }, 16965 }, 16966 { 16967 name: "MOVHreg", 16968 argLen: 1, 16969 asm: ppc64.AMOVH, 16970 reg: regInfo{ 16971 inputs: []inputInfo{ 16972 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16973 }, 16974 outputs: []outputInfo{ 16975 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16976 }, 16977 }, 16978 }, 16979 { 16980 name: "MOVHZreg", 16981 argLen: 1, 16982 asm: ppc64.AMOVHZ, 16983 reg: regInfo{ 16984 inputs: []inputInfo{ 16985 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16986 }, 16987 outputs: []outputInfo{ 16988 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16989 }, 16990 }, 16991 }, 16992 { 16993 name: "MOVWreg", 16994 argLen: 1, 16995 asm: ppc64.AMOVW, 16996 reg: regInfo{ 16997 inputs: []inputInfo{ 16998 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16999 }, 17000 outputs: []outputInfo{ 17001 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17002 }, 17003 }, 17004 }, 17005 { 17006 name: "MOVWZreg", 17007 argLen: 1, 17008 asm: ppc64.AMOVWZ, 17009 reg: regInfo{ 17010 inputs: []inputInfo{ 17011 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17012 }, 17013 outputs: []outputInfo{ 17014 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17015 }, 17016 }, 17017 }, 17018 { 17019 name: "MOVBZload", 17020 auxType: auxSymOff, 17021 argLen: 2, 17022 faultOnNilArg0: true, 17023 symEffect: SymRead, 17024 asm: ppc64.AMOVBZ, 17025 reg: regInfo{ 17026 inputs: []inputInfo{ 17027 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17028 }, 17029 outputs: []outputInfo{ 17030 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17031 }, 17032 }, 17033 }, 17034 { 17035 name: "MOVHload", 17036 auxType: auxSymOff, 17037 argLen: 2, 17038 faultOnNilArg0: true, 17039 symEffect: SymRead, 17040 asm: ppc64.AMOVH, 17041 reg: regInfo{ 17042 inputs: []inputInfo{ 17043 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17044 }, 17045 outputs: []outputInfo{ 17046 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17047 }, 17048 }, 17049 }, 17050 { 17051 name: "MOVHZload", 17052 auxType: auxSymOff, 17053 argLen: 2, 17054 faultOnNilArg0: true, 17055 symEffect: SymRead, 17056 asm: ppc64.AMOVHZ, 17057 reg: regInfo{ 17058 inputs: []inputInfo{ 17059 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17060 }, 17061 outputs: []outputInfo{ 17062 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17063 }, 17064 }, 17065 }, 17066 { 17067 name: "MOVWload", 17068 auxType: auxSymOff, 17069 argLen: 2, 17070 faultOnNilArg0: true, 17071 symEffect: SymRead, 17072 asm: ppc64.AMOVW, 17073 reg: regInfo{ 17074 inputs: []inputInfo{ 17075 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17076 }, 17077 outputs: []outputInfo{ 17078 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17079 }, 17080 }, 17081 }, 17082 { 17083 name: "MOVWZload", 17084 auxType: auxSymOff, 17085 argLen: 2, 17086 faultOnNilArg0: true, 17087 symEffect: SymRead, 17088 asm: ppc64.AMOVWZ, 17089 reg: regInfo{ 17090 inputs: []inputInfo{ 17091 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17092 }, 17093 outputs: []outputInfo{ 17094 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17095 }, 17096 }, 17097 }, 17098 { 17099 name: "MOVDload", 17100 auxType: auxSymOff, 17101 argLen: 2, 17102 faultOnNilArg0: true, 17103 symEffect: SymRead, 17104 asm: ppc64.AMOVD, 17105 reg: regInfo{ 17106 inputs: []inputInfo{ 17107 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17108 }, 17109 outputs: []outputInfo{ 17110 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17111 }, 17112 }, 17113 }, 17114 { 17115 name: "FMOVDload", 17116 auxType: auxSymOff, 17117 argLen: 2, 17118 faultOnNilArg0: true, 17119 symEffect: SymRead, 17120 asm: ppc64.AFMOVD, 17121 reg: regInfo{ 17122 inputs: []inputInfo{ 17123 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17124 }, 17125 outputs: []outputInfo{ 17126 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17127 }, 17128 }, 17129 }, 17130 { 17131 name: "FMOVSload", 17132 auxType: auxSymOff, 17133 argLen: 2, 17134 faultOnNilArg0: true, 17135 symEffect: SymRead, 17136 asm: ppc64.AFMOVS, 17137 reg: regInfo{ 17138 inputs: []inputInfo{ 17139 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17140 }, 17141 outputs: []outputInfo{ 17142 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17143 }, 17144 }, 17145 }, 17146 { 17147 name: "MOVBstore", 17148 auxType: auxSymOff, 17149 argLen: 3, 17150 faultOnNilArg0: true, 17151 symEffect: SymWrite, 17152 asm: ppc64.AMOVB, 17153 reg: regInfo{ 17154 inputs: []inputInfo{ 17155 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17156 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17157 }, 17158 }, 17159 }, 17160 { 17161 name: "MOVHstore", 17162 auxType: auxSymOff, 17163 argLen: 3, 17164 faultOnNilArg0: true, 17165 symEffect: SymWrite, 17166 asm: ppc64.AMOVH, 17167 reg: regInfo{ 17168 inputs: []inputInfo{ 17169 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17170 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17171 }, 17172 }, 17173 }, 17174 { 17175 name: "MOVWstore", 17176 auxType: auxSymOff, 17177 argLen: 3, 17178 faultOnNilArg0: true, 17179 symEffect: SymWrite, 17180 asm: ppc64.AMOVW, 17181 reg: regInfo{ 17182 inputs: []inputInfo{ 17183 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17184 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17185 }, 17186 }, 17187 }, 17188 { 17189 name: "MOVDstore", 17190 auxType: auxSymOff, 17191 argLen: 3, 17192 faultOnNilArg0: true, 17193 symEffect: SymWrite, 17194 asm: ppc64.AMOVD, 17195 reg: regInfo{ 17196 inputs: []inputInfo{ 17197 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17198 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17199 }, 17200 }, 17201 }, 17202 { 17203 name: "FMOVDstore", 17204 auxType: auxSymOff, 17205 argLen: 3, 17206 faultOnNilArg0: true, 17207 symEffect: SymWrite, 17208 asm: ppc64.AFMOVD, 17209 reg: regInfo{ 17210 inputs: []inputInfo{ 17211 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17212 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17213 }, 17214 }, 17215 }, 17216 { 17217 name: "FMOVSstore", 17218 auxType: auxSymOff, 17219 argLen: 3, 17220 faultOnNilArg0: true, 17221 symEffect: SymWrite, 17222 asm: ppc64.AFMOVS, 17223 reg: regInfo{ 17224 inputs: []inputInfo{ 17225 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17226 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17227 }, 17228 }, 17229 }, 17230 { 17231 name: "MOVBstorezero", 17232 auxType: auxSymOff, 17233 argLen: 2, 17234 faultOnNilArg0: true, 17235 symEffect: SymWrite, 17236 asm: ppc64.AMOVB, 17237 reg: regInfo{ 17238 inputs: []inputInfo{ 17239 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17240 }, 17241 }, 17242 }, 17243 { 17244 name: "MOVHstorezero", 17245 auxType: auxSymOff, 17246 argLen: 2, 17247 faultOnNilArg0: true, 17248 symEffect: SymWrite, 17249 asm: ppc64.AMOVH, 17250 reg: regInfo{ 17251 inputs: []inputInfo{ 17252 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17253 }, 17254 }, 17255 }, 17256 { 17257 name: "MOVWstorezero", 17258 auxType: auxSymOff, 17259 argLen: 2, 17260 faultOnNilArg0: true, 17261 symEffect: SymWrite, 17262 asm: ppc64.AMOVW, 17263 reg: regInfo{ 17264 inputs: []inputInfo{ 17265 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17266 }, 17267 }, 17268 }, 17269 { 17270 name: "MOVDstorezero", 17271 auxType: auxSymOff, 17272 argLen: 2, 17273 faultOnNilArg0: true, 17274 symEffect: SymWrite, 17275 asm: ppc64.AMOVD, 17276 reg: regInfo{ 17277 inputs: []inputInfo{ 17278 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17279 }, 17280 }, 17281 }, 17282 { 17283 name: "MOVDaddr", 17284 auxType: auxSymOff, 17285 argLen: 1, 17286 rematerializeable: true, 17287 symEffect: SymAddr, 17288 asm: ppc64.AMOVD, 17289 reg: regInfo{ 17290 inputs: []inputInfo{ 17291 {0, 6}, // SP SB 17292 }, 17293 outputs: []outputInfo{ 17294 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17295 }, 17296 }, 17297 }, 17298 { 17299 name: "MOVDconst", 17300 auxType: auxInt64, 17301 argLen: 0, 17302 rematerializeable: true, 17303 asm: ppc64.AMOVD, 17304 reg: regInfo{ 17305 outputs: []outputInfo{ 17306 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17307 }, 17308 }, 17309 }, 17310 { 17311 name: "FMOVDconst", 17312 auxType: auxFloat64, 17313 argLen: 0, 17314 rematerializeable: true, 17315 asm: ppc64.AFMOVD, 17316 reg: regInfo{ 17317 outputs: []outputInfo{ 17318 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17319 }, 17320 }, 17321 }, 17322 { 17323 name: "FMOVSconst", 17324 auxType: auxFloat32, 17325 argLen: 0, 17326 rematerializeable: true, 17327 asm: ppc64.AFMOVS, 17328 reg: regInfo{ 17329 outputs: []outputInfo{ 17330 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17331 }, 17332 }, 17333 }, 17334 { 17335 name: "FCMPU", 17336 argLen: 2, 17337 asm: ppc64.AFCMPU, 17338 reg: regInfo{ 17339 inputs: []inputInfo{ 17340 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17341 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17342 }, 17343 }, 17344 }, 17345 { 17346 name: "CMP", 17347 argLen: 2, 17348 asm: ppc64.ACMP, 17349 reg: regInfo{ 17350 inputs: []inputInfo{ 17351 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17352 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17353 }, 17354 }, 17355 }, 17356 { 17357 name: "CMPU", 17358 argLen: 2, 17359 asm: ppc64.ACMPU, 17360 reg: regInfo{ 17361 inputs: []inputInfo{ 17362 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17363 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17364 }, 17365 }, 17366 }, 17367 { 17368 name: "CMPW", 17369 argLen: 2, 17370 asm: ppc64.ACMPW, 17371 reg: regInfo{ 17372 inputs: []inputInfo{ 17373 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17374 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17375 }, 17376 }, 17377 }, 17378 { 17379 name: "CMPWU", 17380 argLen: 2, 17381 asm: ppc64.ACMPWU, 17382 reg: regInfo{ 17383 inputs: []inputInfo{ 17384 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17385 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17386 }, 17387 }, 17388 }, 17389 { 17390 name: "CMPconst", 17391 auxType: auxInt64, 17392 argLen: 1, 17393 asm: ppc64.ACMP, 17394 reg: regInfo{ 17395 inputs: []inputInfo{ 17396 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17397 }, 17398 }, 17399 }, 17400 { 17401 name: "CMPUconst", 17402 auxType: auxInt64, 17403 argLen: 1, 17404 asm: ppc64.ACMPU, 17405 reg: regInfo{ 17406 inputs: []inputInfo{ 17407 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17408 }, 17409 }, 17410 }, 17411 { 17412 name: "CMPWconst", 17413 auxType: auxInt32, 17414 argLen: 1, 17415 asm: ppc64.ACMPW, 17416 reg: regInfo{ 17417 inputs: []inputInfo{ 17418 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17419 }, 17420 }, 17421 }, 17422 { 17423 name: "CMPWUconst", 17424 auxType: auxInt32, 17425 argLen: 1, 17426 asm: ppc64.ACMPWU, 17427 reg: regInfo{ 17428 inputs: []inputInfo{ 17429 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17430 }, 17431 }, 17432 }, 17433 { 17434 name: "Equal", 17435 argLen: 1, 17436 reg: regInfo{ 17437 outputs: []outputInfo{ 17438 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17439 }, 17440 }, 17441 }, 17442 { 17443 name: "NotEqual", 17444 argLen: 1, 17445 reg: regInfo{ 17446 outputs: []outputInfo{ 17447 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17448 }, 17449 }, 17450 }, 17451 { 17452 name: "LessThan", 17453 argLen: 1, 17454 reg: regInfo{ 17455 outputs: []outputInfo{ 17456 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17457 }, 17458 }, 17459 }, 17460 { 17461 name: "FLessThan", 17462 argLen: 1, 17463 reg: regInfo{ 17464 outputs: []outputInfo{ 17465 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17466 }, 17467 }, 17468 }, 17469 { 17470 name: "LessEqual", 17471 argLen: 1, 17472 reg: regInfo{ 17473 outputs: []outputInfo{ 17474 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17475 }, 17476 }, 17477 }, 17478 { 17479 name: "FLessEqual", 17480 argLen: 1, 17481 reg: regInfo{ 17482 outputs: []outputInfo{ 17483 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17484 }, 17485 }, 17486 }, 17487 { 17488 name: "GreaterThan", 17489 argLen: 1, 17490 reg: regInfo{ 17491 outputs: []outputInfo{ 17492 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17493 }, 17494 }, 17495 }, 17496 { 17497 name: "FGreaterThan", 17498 argLen: 1, 17499 reg: regInfo{ 17500 outputs: []outputInfo{ 17501 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17502 }, 17503 }, 17504 }, 17505 { 17506 name: "GreaterEqual", 17507 argLen: 1, 17508 reg: regInfo{ 17509 outputs: []outputInfo{ 17510 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17511 }, 17512 }, 17513 }, 17514 { 17515 name: "FGreaterEqual", 17516 argLen: 1, 17517 reg: regInfo{ 17518 outputs: []outputInfo{ 17519 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17520 }, 17521 }, 17522 }, 17523 { 17524 name: "LoweredGetClosurePtr", 17525 argLen: 0, 17526 reg: regInfo{ 17527 outputs: []outputInfo{ 17528 {0, 2048}, // R11 17529 }, 17530 }, 17531 }, 17532 { 17533 name: "LoweredNilCheck", 17534 argLen: 2, 17535 clobberFlags: true, 17536 nilCheck: true, 17537 faultOnNilArg0: true, 17538 reg: regInfo{ 17539 inputs: []inputInfo{ 17540 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17541 }, 17542 clobbers: 2147483648, // R31 17543 }, 17544 }, 17545 { 17546 name: "LoweredRound32F", 17547 argLen: 1, 17548 resultInArg0: true, 17549 reg: regInfo{ 17550 inputs: []inputInfo{ 17551 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17552 }, 17553 outputs: []outputInfo{ 17554 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17555 }, 17556 }, 17557 }, 17558 { 17559 name: "LoweredRound64F", 17560 argLen: 1, 17561 resultInArg0: true, 17562 reg: regInfo{ 17563 inputs: []inputInfo{ 17564 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17565 }, 17566 outputs: []outputInfo{ 17567 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17568 }, 17569 }, 17570 }, 17571 { 17572 name: "MOVDconvert", 17573 argLen: 2, 17574 asm: ppc64.AMOVD, 17575 reg: regInfo{ 17576 inputs: []inputInfo{ 17577 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17578 }, 17579 outputs: []outputInfo{ 17580 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17581 }, 17582 }, 17583 }, 17584 { 17585 name: "CALLstatic", 17586 auxType: auxSymOff, 17587 argLen: 1, 17588 clobberFlags: true, 17589 call: true, 17590 symEffect: SymNone, 17591 reg: regInfo{ 17592 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17593 }, 17594 }, 17595 { 17596 name: "CALLclosure", 17597 auxType: auxInt64, 17598 argLen: 3, 17599 clobberFlags: true, 17600 call: true, 17601 reg: regInfo{ 17602 inputs: []inputInfo{ 17603 {1, 2048}, // R11 17604 {0, 1073733626}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17605 }, 17606 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17607 }, 17608 }, 17609 { 17610 name: "CALLinter", 17611 auxType: auxInt64, 17612 argLen: 2, 17613 clobberFlags: true, 17614 call: true, 17615 reg: regInfo{ 17616 inputs: []inputInfo{ 17617 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17618 }, 17619 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17620 }, 17621 }, 17622 { 17623 name: "LoweredZero", 17624 auxType: auxInt64, 17625 argLen: 2, 17626 clobberFlags: true, 17627 faultOnNilArg0: true, 17628 reg: regInfo{ 17629 inputs: []inputInfo{ 17630 {0, 8}, // R3 17631 }, 17632 clobbers: 8, // R3 17633 }, 17634 }, 17635 { 17636 name: "LoweredMove", 17637 auxType: auxInt64, 17638 argLen: 3, 17639 clobberFlags: true, 17640 faultOnNilArg0: true, 17641 faultOnNilArg1: true, 17642 reg: regInfo{ 17643 inputs: []inputInfo{ 17644 {0, 8}, // R3 17645 {1, 16}, // R4 17646 }, 17647 clobbers: 1944, // R3 R4 R7 R8 R9 R10 17648 }, 17649 }, 17650 { 17651 name: "LoweredAtomicStore32", 17652 argLen: 3, 17653 faultOnNilArg0: true, 17654 hasSideEffects: true, 17655 reg: regInfo{ 17656 inputs: []inputInfo{ 17657 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17658 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17659 }, 17660 }, 17661 }, 17662 { 17663 name: "LoweredAtomicStore64", 17664 argLen: 3, 17665 faultOnNilArg0: true, 17666 hasSideEffects: true, 17667 reg: regInfo{ 17668 inputs: []inputInfo{ 17669 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17670 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17671 }, 17672 }, 17673 }, 17674 { 17675 name: "LoweredAtomicLoad32", 17676 argLen: 2, 17677 clobberFlags: true, 17678 faultOnNilArg0: true, 17679 reg: regInfo{ 17680 inputs: []inputInfo{ 17681 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17682 }, 17683 outputs: []outputInfo{ 17684 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17685 }, 17686 }, 17687 }, 17688 { 17689 name: "LoweredAtomicLoad64", 17690 argLen: 2, 17691 clobberFlags: true, 17692 faultOnNilArg0: true, 17693 reg: regInfo{ 17694 inputs: []inputInfo{ 17695 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17696 }, 17697 outputs: []outputInfo{ 17698 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17699 }, 17700 }, 17701 }, 17702 { 17703 name: "LoweredAtomicLoadPtr", 17704 argLen: 2, 17705 clobberFlags: true, 17706 faultOnNilArg0: true, 17707 reg: regInfo{ 17708 inputs: []inputInfo{ 17709 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17710 }, 17711 outputs: []outputInfo{ 17712 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17713 }, 17714 }, 17715 }, 17716 { 17717 name: "LoweredAtomicAdd32", 17718 argLen: 3, 17719 resultNotInArgs: true, 17720 clobberFlags: true, 17721 faultOnNilArg0: true, 17722 hasSideEffects: true, 17723 reg: regInfo{ 17724 inputs: []inputInfo{ 17725 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17726 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17727 }, 17728 outputs: []outputInfo{ 17729 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17730 }, 17731 }, 17732 }, 17733 { 17734 name: "LoweredAtomicAdd64", 17735 argLen: 3, 17736 resultNotInArgs: true, 17737 clobberFlags: true, 17738 faultOnNilArg0: true, 17739 hasSideEffects: true, 17740 reg: regInfo{ 17741 inputs: []inputInfo{ 17742 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17743 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17744 }, 17745 outputs: []outputInfo{ 17746 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17747 }, 17748 }, 17749 }, 17750 { 17751 name: "LoweredAtomicExchange32", 17752 argLen: 3, 17753 resultNotInArgs: true, 17754 clobberFlags: true, 17755 faultOnNilArg0: true, 17756 hasSideEffects: true, 17757 reg: regInfo{ 17758 inputs: []inputInfo{ 17759 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17760 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17761 }, 17762 outputs: []outputInfo{ 17763 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17764 }, 17765 }, 17766 }, 17767 { 17768 name: "LoweredAtomicExchange64", 17769 argLen: 3, 17770 resultNotInArgs: true, 17771 clobberFlags: true, 17772 faultOnNilArg0: true, 17773 hasSideEffects: true, 17774 reg: regInfo{ 17775 inputs: []inputInfo{ 17776 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17777 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17778 }, 17779 outputs: []outputInfo{ 17780 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17781 }, 17782 }, 17783 }, 17784 { 17785 name: "LoweredAtomicCas64", 17786 argLen: 4, 17787 resultNotInArgs: true, 17788 clobberFlags: true, 17789 faultOnNilArg0: true, 17790 hasSideEffects: true, 17791 reg: regInfo{ 17792 inputs: []inputInfo{ 17793 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17794 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17795 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17796 }, 17797 outputs: []outputInfo{ 17798 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17799 }, 17800 }, 17801 }, 17802 { 17803 name: "LoweredAtomicCas32", 17804 argLen: 4, 17805 resultNotInArgs: true, 17806 clobberFlags: true, 17807 faultOnNilArg0: true, 17808 hasSideEffects: true, 17809 reg: regInfo{ 17810 inputs: []inputInfo{ 17811 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17812 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17813 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17814 }, 17815 outputs: []outputInfo{ 17816 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17817 }, 17818 }, 17819 }, 17820 { 17821 name: "LoweredAtomicAnd8", 17822 argLen: 3, 17823 faultOnNilArg0: true, 17824 hasSideEffects: true, 17825 asm: ppc64.AAND, 17826 reg: regInfo{ 17827 inputs: []inputInfo{ 17828 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17829 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17830 }, 17831 }, 17832 }, 17833 { 17834 name: "LoweredAtomicOr8", 17835 argLen: 3, 17836 faultOnNilArg0: true, 17837 hasSideEffects: true, 17838 asm: ppc64.AOR, 17839 reg: regInfo{ 17840 inputs: []inputInfo{ 17841 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17842 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17843 }, 17844 }, 17845 }, 17846 { 17847 name: "InvertFlags", 17848 argLen: 1, 17849 reg: regInfo{}, 17850 }, 17851 { 17852 name: "FlagEQ", 17853 argLen: 0, 17854 reg: regInfo{}, 17855 }, 17856 { 17857 name: "FlagLT", 17858 argLen: 0, 17859 reg: regInfo{}, 17860 }, 17861 { 17862 name: "FlagGT", 17863 argLen: 0, 17864 reg: regInfo{}, 17865 }, 17866 17867 { 17868 name: "FADDS", 17869 argLen: 2, 17870 commutative: true, 17871 resultInArg0: true, 17872 clobberFlags: true, 17873 asm: s390x.AFADDS, 17874 reg: regInfo{ 17875 inputs: []inputInfo{ 17876 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17877 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17878 }, 17879 outputs: []outputInfo{ 17880 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17881 }, 17882 }, 17883 }, 17884 { 17885 name: "FADD", 17886 argLen: 2, 17887 commutative: true, 17888 resultInArg0: true, 17889 clobberFlags: true, 17890 asm: s390x.AFADD, 17891 reg: regInfo{ 17892 inputs: []inputInfo{ 17893 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17894 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17895 }, 17896 outputs: []outputInfo{ 17897 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17898 }, 17899 }, 17900 }, 17901 { 17902 name: "FSUBS", 17903 argLen: 2, 17904 resultInArg0: true, 17905 clobberFlags: true, 17906 asm: s390x.AFSUBS, 17907 reg: regInfo{ 17908 inputs: []inputInfo{ 17909 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17910 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17911 }, 17912 outputs: []outputInfo{ 17913 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17914 }, 17915 }, 17916 }, 17917 { 17918 name: "FSUB", 17919 argLen: 2, 17920 resultInArg0: true, 17921 clobberFlags: true, 17922 asm: s390x.AFSUB, 17923 reg: regInfo{ 17924 inputs: []inputInfo{ 17925 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17926 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17927 }, 17928 outputs: []outputInfo{ 17929 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17930 }, 17931 }, 17932 }, 17933 { 17934 name: "FMULS", 17935 argLen: 2, 17936 commutative: true, 17937 resultInArg0: true, 17938 asm: s390x.AFMULS, 17939 reg: regInfo{ 17940 inputs: []inputInfo{ 17941 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17942 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17943 }, 17944 outputs: []outputInfo{ 17945 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17946 }, 17947 }, 17948 }, 17949 { 17950 name: "FMUL", 17951 argLen: 2, 17952 commutative: true, 17953 resultInArg0: true, 17954 asm: s390x.AFMUL, 17955 reg: regInfo{ 17956 inputs: []inputInfo{ 17957 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17958 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17959 }, 17960 outputs: []outputInfo{ 17961 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17962 }, 17963 }, 17964 }, 17965 { 17966 name: "FDIVS", 17967 argLen: 2, 17968 resultInArg0: true, 17969 asm: s390x.AFDIVS, 17970 reg: regInfo{ 17971 inputs: []inputInfo{ 17972 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17973 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17974 }, 17975 outputs: []outputInfo{ 17976 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17977 }, 17978 }, 17979 }, 17980 { 17981 name: "FDIV", 17982 argLen: 2, 17983 resultInArg0: true, 17984 asm: s390x.AFDIV, 17985 reg: regInfo{ 17986 inputs: []inputInfo{ 17987 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17988 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17989 }, 17990 outputs: []outputInfo{ 17991 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17992 }, 17993 }, 17994 }, 17995 { 17996 name: "FNEGS", 17997 argLen: 1, 17998 clobberFlags: true, 17999 asm: s390x.AFNEGS, 18000 reg: regInfo{ 18001 inputs: []inputInfo{ 18002 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18003 }, 18004 outputs: []outputInfo{ 18005 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18006 }, 18007 }, 18008 }, 18009 { 18010 name: "FNEG", 18011 argLen: 1, 18012 clobberFlags: true, 18013 asm: s390x.AFNEG, 18014 reg: regInfo{ 18015 inputs: []inputInfo{ 18016 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18017 }, 18018 outputs: []outputInfo{ 18019 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18020 }, 18021 }, 18022 }, 18023 { 18024 name: "FMADDS", 18025 argLen: 3, 18026 resultInArg0: true, 18027 asm: s390x.AFMADDS, 18028 reg: regInfo{ 18029 inputs: []inputInfo{ 18030 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18031 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18032 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18033 }, 18034 outputs: []outputInfo{ 18035 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18036 }, 18037 }, 18038 }, 18039 { 18040 name: "FMADD", 18041 argLen: 3, 18042 resultInArg0: true, 18043 asm: s390x.AFMADD, 18044 reg: regInfo{ 18045 inputs: []inputInfo{ 18046 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18047 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18048 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18049 }, 18050 outputs: []outputInfo{ 18051 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18052 }, 18053 }, 18054 }, 18055 { 18056 name: "FMSUBS", 18057 argLen: 3, 18058 resultInArg0: true, 18059 asm: s390x.AFMSUBS, 18060 reg: regInfo{ 18061 inputs: []inputInfo{ 18062 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18063 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18064 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18065 }, 18066 outputs: []outputInfo{ 18067 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18068 }, 18069 }, 18070 }, 18071 { 18072 name: "FMSUB", 18073 argLen: 3, 18074 resultInArg0: true, 18075 asm: s390x.AFMSUB, 18076 reg: regInfo{ 18077 inputs: []inputInfo{ 18078 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18079 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18080 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18081 }, 18082 outputs: []outputInfo{ 18083 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18084 }, 18085 }, 18086 }, 18087 { 18088 name: "FMOVSload", 18089 auxType: auxSymOff, 18090 argLen: 2, 18091 faultOnNilArg0: true, 18092 symEffect: SymRead, 18093 asm: s390x.AFMOVS, 18094 reg: regInfo{ 18095 inputs: []inputInfo{ 18096 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18097 }, 18098 outputs: []outputInfo{ 18099 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18100 }, 18101 }, 18102 }, 18103 { 18104 name: "FMOVDload", 18105 auxType: auxSymOff, 18106 argLen: 2, 18107 faultOnNilArg0: true, 18108 symEffect: SymRead, 18109 asm: s390x.AFMOVD, 18110 reg: regInfo{ 18111 inputs: []inputInfo{ 18112 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18113 }, 18114 outputs: []outputInfo{ 18115 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18116 }, 18117 }, 18118 }, 18119 { 18120 name: "FMOVSconst", 18121 auxType: auxFloat32, 18122 argLen: 0, 18123 rematerializeable: true, 18124 asm: s390x.AFMOVS, 18125 reg: regInfo{ 18126 outputs: []outputInfo{ 18127 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18128 }, 18129 }, 18130 }, 18131 { 18132 name: "FMOVDconst", 18133 auxType: auxFloat64, 18134 argLen: 0, 18135 rematerializeable: true, 18136 asm: s390x.AFMOVD, 18137 reg: regInfo{ 18138 outputs: []outputInfo{ 18139 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18140 }, 18141 }, 18142 }, 18143 { 18144 name: "FMOVSloadidx", 18145 auxType: auxSymOff, 18146 argLen: 3, 18147 symEffect: SymRead, 18148 asm: s390x.AFMOVS, 18149 reg: regInfo{ 18150 inputs: []inputInfo{ 18151 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18152 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18153 }, 18154 outputs: []outputInfo{ 18155 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18156 }, 18157 }, 18158 }, 18159 { 18160 name: "FMOVDloadidx", 18161 auxType: auxSymOff, 18162 argLen: 3, 18163 symEffect: SymRead, 18164 asm: s390x.AFMOVD, 18165 reg: regInfo{ 18166 inputs: []inputInfo{ 18167 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18168 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18169 }, 18170 outputs: []outputInfo{ 18171 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18172 }, 18173 }, 18174 }, 18175 { 18176 name: "FMOVSstore", 18177 auxType: auxSymOff, 18178 argLen: 3, 18179 faultOnNilArg0: true, 18180 symEffect: SymWrite, 18181 asm: s390x.AFMOVS, 18182 reg: regInfo{ 18183 inputs: []inputInfo{ 18184 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18185 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18186 }, 18187 }, 18188 }, 18189 { 18190 name: "FMOVDstore", 18191 auxType: auxSymOff, 18192 argLen: 3, 18193 faultOnNilArg0: true, 18194 symEffect: SymWrite, 18195 asm: s390x.AFMOVD, 18196 reg: regInfo{ 18197 inputs: []inputInfo{ 18198 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18199 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18200 }, 18201 }, 18202 }, 18203 { 18204 name: "FMOVSstoreidx", 18205 auxType: auxSymOff, 18206 argLen: 4, 18207 symEffect: SymWrite, 18208 asm: s390x.AFMOVS, 18209 reg: regInfo{ 18210 inputs: []inputInfo{ 18211 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18212 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18213 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18214 }, 18215 }, 18216 }, 18217 { 18218 name: "FMOVDstoreidx", 18219 auxType: auxSymOff, 18220 argLen: 4, 18221 symEffect: SymWrite, 18222 asm: s390x.AFMOVD, 18223 reg: regInfo{ 18224 inputs: []inputInfo{ 18225 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18226 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18227 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18228 }, 18229 }, 18230 }, 18231 { 18232 name: "ADD", 18233 argLen: 2, 18234 commutative: true, 18235 clobberFlags: true, 18236 asm: s390x.AADD, 18237 reg: regInfo{ 18238 inputs: []inputInfo{ 18239 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18240 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18241 }, 18242 outputs: []outputInfo{ 18243 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18244 }, 18245 }, 18246 }, 18247 { 18248 name: "ADDW", 18249 argLen: 2, 18250 commutative: true, 18251 clobberFlags: true, 18252 asm: s390x.AADDW, 18253 reg: regInfo{ 18254 inputs: []inputInfo{ 18255 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18256 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18257 }, 18258 outputs: []outputInfo{ 18259 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18260 }, 18261 }, 18262 }, 18263 { 18264 name: "ADDconst", 18265 auxType: auxInt64, 18266 argLen: 1, 18267 clobberFlags: true, 18268 asm: s390x.AADD, 18269 reg: regInfo{ 18270 inputs: []inputInfo{ 18271 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18272 }, 18273 outputs: []outputInfo{ 18274 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18275 }, 18276 }, 18277 }, 18278 { 18279 name: "ADDWconst", 18280 auxType: auxInt32, 18281 argLen: 1, 18282 clobberFlags: true, 18283 asm: s390x.AADDW, 18284 reg: regInfo{ 18285 inputs: []inputInfo{ 18286 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18287 }, 18288 outputs: []outputInfo{ 18289 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18290 }, 18291 }, 18292 }, 18293 { 18294 name: "ADDload", 18295 auxType: auxSymOff, 18296 argLen: 3, 18297 resultInArg0: true, 18298 clobberFlags: true, 18299 faultOnNilArg1: true, 18300 symEffect: SymRead, 18301 asm: s390x.AADD, 18302 reg: regInfo{ 18303 inputs: []inputInfo{ 18304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18305 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18306 }, 18307 outputs: []outputInfo{ 18308 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18309 }, 18310 }, 18311 }, 18312 { 18313 name: "ADDWload", 18314 auxType: auxSymOff, 18315 argLen: 3, 18316 resultInArg0: true, 18317 clobberFlags: true, 18318 faultOnNilArg1: true, 18319 symEffect: SymRead, 18320 asm: s390x.AADDW, 18321 reg: regInfo{ 18322 inputs: []inputInfo{ 18323 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18324 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18325 }, 18326 outputs: []outputInfo{ 18327 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18328 }, 18329 }, 18330 }, 18331 { 18332 name: "SUB", 18333 argLen: 2, 18334 clobberFlags: true, 18335 asm: s390x.ASUB, 18336 reg: regInfo{ 18337 inputs: []inputInfo{ 18338 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18339 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18340 }, 18341 outputs: []outputInfo{ 18342 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18343 }, 18344 }, 18345 }, 18346 { 18347 name: "SUBW", 18348 argLen: 2, 18349 clobberFlags: true, 18350 asm: s390x.ASUBW, 18351 reg: regInfo{ 18352 inputs: []inputInfo{ 18353 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18354 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18355 }, 18356 outputs: []outputInfo{ 18357 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18358 }, 18359 }, 18360 }, 18361 { 18362 name: "SUBconst", 18363 auxType: auxInt64, 18364 argLen: 1, 18365 resultInArg0: true, 18366 clobberFlags: true, 18367 asm: s390x.ASUB, 18368 reg: regInfo{ 18369 inputs: []inputInfo{ 18370 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18371 }, 18372 outputs: []outputInfo{ 18373 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18374 }, 18375 }, 18376 }, 18377 { 18378 name: "SUBWconst", 18379 auxType: auxInt32, 18380 argLen: 1, 18381 resultInArg0: true, 18382 clobberFlags: true, 18383 asm: s390x.ASUBW, 18384 reg: regInfo{ 18385 inputs: []inputInfo{ 18386 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18387 }, 18388 outputs: []outputInfo{ 18389 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18390 }, 18391 }, 18392 }, 18393 { 18394 name: "SUBload", 18395 auxType: auxSymOff, 18396 argLen: 3, 18397 resultInArg0: true, 18398 clobberFlags: true, 18399 faultOnNilArg1: true, 18400 symEffect: SymRead, 18401 asm: s390x.ASUB, 18402 reg: regInfo{ 18403 inputs: []inputInfo{ 18404 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18405 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18406 }, 18407 outputs: []outputInfo{ 18408 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18409 }, 18410 }, 18411 }, 18412 { 18413 name: "SUBWload", 18414 auxType: auxSymOff, 18415 argLen: 3, 18416 resultInArg0: true, 18417 clobberFlags: true, 18418 faultOnNilArg1: true, 18419 symEffect: SymRead, 18420 asm: s390x.ASUBW, 18421 reg: regInfo{ 18422 inputs: []inputInfo{ 18423 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18424 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18425 }, 18426 outputs: []outputInfo{ 18427 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18428 }, 18429 }, 18430 }, 18431 { 18432 name: "MULLD", 18433 argLen: 2, 18434 commutative: true, 18435 resultInArg0: true, 18436 clobberFlags: true, 18437 asm: s390x.AMULLD, 18438 reg: regInfo{ 18439 inputs: []inputInfo{ 18440 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18441 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18442 }, 18443 outputs: []outputInfo{ 18444 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18445 }, 18446 }, 18447 }, 18448 { 18449 name: "MULLW", 18450 argLen: 2, 18451 commutative: true, 18452 resultInArg0: true, 18453 clobberFlags: true, 18454 asm: s390x.AMULLW, 18455 reg: regInfo{ 18456 inputs: []inputInfo{ 18457 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18458 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18459 }, 18460 outputs: []outputInfo{ 18461 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18462 }, 18463 }, 18464 }, 18465 { 18466 name: "MULLDconst", 18467 auxType: auxInt64, 18468 argLen: 1, 18469 resultInArg0: true, 18470 clobberFlags: true, 18471 asm: s390x.AMULLD, 18472 reg: regInfo{ 18473 inputs: []inputInfo{ 18474 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18475 }, 18476 outputs: []outputInfo{ 18477 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18478 }, 18479 }, 18480 }, 18481 { 18482 name: "MULLWconst", 18483 auxType: auxInt32, 18484 argLen: 1, 18485 resultInArg0: true, 18486 clobberFlags: true, 18487 asm: s390x.AMULLW, 18488 reg: regInfo{ 18489 inputs: []inputInfo{ 18490 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18491 }, 18492 outputs: []outputInfo{ 18493 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18494 }, 18495 }, 18496 }, 18497 { 18498 name: "MULLDload", 18499 auxType: auxSymOff, 18500 argLen: 3, 18501 resultInArg0: true, 18502 clobberFlags: true, 18503 faultOnNilArg1: true, 18504 symEffect: SymRead, 18505 asm: s390x.AMULLD, 18506 reg: regInfo{ 18507 inputs: []inputInfo{ 18508 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18509 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18510 }, 18511 outputs: []outputInfo{ 18512 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18513 }, 18514 }, 18515 }, 18516 { 18517 name: "MULLWload", 18518 auxType: auxSymOff, 18519 argLen: 3, 18520 resultInArg0: true, 18521 clobberFlags: true, 18522 faultOnNilArg1: true, 18523 symEffect: SymRead, 18524 asm: s390x.AMULLW, 18525 reg: regInfo{ 18526 inputs: []inputInfo{ 18527 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18528 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18529 }, 18530 outputs: []outputInfo{ 18531 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18532 }, 18533 }, 18534 }, 18535 { 18536 name: "MULHD", 18537 argLen: 2, 18538 commutative: true, 18539 resultInArg0: true, 18540 clobberFlags: true, 18541 asm: s390x.AMULHD, 18542 reg: regInfo{ 18543 inputs: []inputInfo{ 18544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18545 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18546 }, 18547 outputs: []outputInfo{ 18548 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18549 }, 18550 }, 18551 }, 18552 { 18553 name: "MULHDU", 18554 argLen: 2, 18555 commutative: true, 18556 resultInArg0: true, 18557 clobberFlags: true, 18558 asm: s390x.AMULHDU, 18559 reg: regInfo{ 18560 inputs: []inputInfo{ 18561 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18562 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18563 }, 18564 outputs: []outputInfo{ 18565 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18566 }, 18567 }, 18568 }, 18569 { 18570 name: "DIVD", 18571 argLen: 2, 18572 resultInArg0: true, 18573 clobberFlags: true, 18574 asm: s390x.ADIVD, 18575 reg: regInfo{ 18576 inputs: []inputInfo{ 18577 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18578 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18579 }, 18580 outputs: []outputInfo{ 18581 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18582 }, 18583 }, 18584 }, 18585 { 18586 name: "DIVW", 18587 argLen: 2, 18588 resultInArg0: true, 18589 clobberFlags: true, 18590 asm: s390x.ADIVW, 18591 reg: regInfo{ 18592 inputs: []inputInfo{ 18593 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18594 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18595 }, 18596 outputs: []outputInfo{ 18597 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18598 }, 18599 }, 18600 }, 18601 { 18602 name: "DIVDU", 18603 argLen: 2, 18604 resultInArg0: true, 18605 clobberFlags: true, 18606 asm: s390x.ADIVDU, 18607 reg: regInfo{ 18608 inputs: []inputInfo{ 18609 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18610 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18611 }, 18612 outputs: []outputInfo{ 18613 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18614 }, 18615 }, 18616 }, 18617 { 18618 name: "DIVWU", 18619 argLen: 2, 18620 resultInArg0: true, 18621 clobberFlags: true, 18622 asm: s390x.ADIVWU, 18623 reg: regInfo{ 18624 inputs: []inputInfo{ 18625 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18626 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18627 }, 18628 outputs: []outputInfo{ 18629 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18630 }, 18631 }, 18632 }, 18633 { 18634 name: "MODD", 18635 argLen: 2, 18636 resultInArg0: true, 18637 clobberFlags: true, 18638 asm: s390x.AMODD, 18639 reg: regInfo{ 18640 inputs: []inputInfo{ 18641 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18642 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18643 }, 18644 outputs: []outputInfo{ 18645 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18646 }, 18647 }, 18648 }, 18649 { 18650 name: "MODW", 18651 argLen: 2, 18652 resultInArg0: true, 18653 clobberFlags: true, 18654 asm: s390x.AMODW, 18655 reg: regInfo{ 18656 inputs: []inputInfo{ 18657 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18658 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18659 }, 18660 outputs: []outputInfo{ 18661 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18662 }, 18663 }, 18664 }, 18665 { 18666 name: "MODDU", 18667 argLen: 2, 18668 resultInArg0: true, 18669 clobberFlags: true, 18670 asm: s390x.AMODDU, 18671 reg: regInfo{ 18672 inputs: []inputInfo{ 18673 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18674 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18675 }, 18676 outputs: []outputInfo{ 18677 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18678 }, 18679 }, 18680 }, 18681 { 18682 name: "MODWU", 18683 argLen: 2, 18684 resultInArg0: true, 18685 clobberFlags: true, 18686 asm: s390x.AMODWU, 18687 reg: regInfo{ 18688 inputs: []inputInfo{ 18689 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18690 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18691 }, 18692 outputs: []outputInfo{ 18693 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18694 }, 18695 }, 18696 }, 18697 { 18698 name: "AND", 18699 argLen: 2, 18700 commutative: true, 18701 clobberFlags: true, 18702 asm: s390x.AAND, 18703 reg: regInfo{ 18704 inputs: []inputInfo{ 18705 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18706 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18707 }, 18708 outputs: []outputInfo{ 18709 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18710 }, 18711 }, 18712 }, 18713 { 18714 name: "ANDW", 18715 argLen: 2, 18716 commutative: true, 18717 clobberFlags: true, 18718 asm: s390x.AANDW, 18719 reg: regInfo{ 18720 inputs: []inputInfo{ 18721 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18722 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18723 }, 18724 outputs: []outputInfo{ 18725 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18726 }, 18727 }, 18728 }, 18729 { 18730 name: "ANDconst", 18731 auxType: auxInt64, 18732 argLen: 1, 18733 resultInArg0: true, 18734 clobberFlags: true, 18735 asm: s390x.AAND, 18736 reg: regInfo{ 18737 inputs: []inputInfo{ 18738 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18739 }, 18740 outputs: []outputInfo{ 18741 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18742 }, 18743 }, 18744 }, 18745 { 18746 name: "ANDWconst", 18747 auxType: auxInt32, 18748 argLen: 1, 18749 resultInArg0: true, 18750 clobberFlags: true, 18751 asm: s390x.AANDW, 18752 reg: regInfo{ 18753 inputs: []inputInfo{ 18754 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18755 }, 18756 outputs: []outputInfo{ 18757 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18758 }, 18759 }, 18760 }, 18761 { 18762 name: "ANDload", 18763 auxType: auxSymOff, 18764 argLen: 3, 18765 resultInArg0: true, 18766 clobberFlags: true, 18767 faultOnNilArg1: true, 18768 symEffect: SymRead, 18769 asm: s390x.AAND, 18770 reg: regInfo{ 18771 inputs: []inputInfo{ 18772 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18773 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18774 }, 18775 outputs: []outputInfo{ 18776 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18777 }, 18778 }, 18779 }, 18780 { 18781 name: "ANDWload", 18782 auxType: auxSymOff, 18783 argLen: 3, 18784 resultInArg0: true, 18785 clobberFlags: true, 18786 faultOnNilArg1: true, 18787 symEffect: SymRead, 18788 asm: s390x.AANDW, 18789 reg: regInfo{ 18790 inputs: []inputInfo{ 18791 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18792 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18793 }, 18794 outputs: []outputInfo{ 18795 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18796 }, 18797 }, 18798 }, 18799 { 18800 name: "OR", 18801 argLen: 2, 18802 commutative: true, 18803 clobberFlags: true, 18804 asm: s390x.AOR, 18805 reg: regInfo{ 18806 inputs: []inputInfo{ 18807 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18808 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18809 }, 18810 outputs: []outputInfo{ 18811 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18812 }, 18813 }, 18814 }, 18815 { 18816 name: "ORW", 18817 argLen: 2, 18818 commutative: true, 18819 clobberFlags: true, 18820 asm: s390x.AORW, 18821 reg: regInfo{ 18822 inputs: []inputInfo{ 18823 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18824 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18825 }, 18826 outputs: []outputInfo{ 18827 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18828 }, 18829 }, 18830 }, 18831 { 18832 name: "ORconst", 18833 auxType: auxInt64, 18834 argLen: 1, 18835 resultInArg0: true, 18836 clobberFlags: true, 18837 asm: s390x.AOR, 18838 reg: regInfo{ 18839 inputs: []inputInfo{ 18840 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18841 }, 18842 outputs: []outputInfo{ 18843 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18844 }, 18845 }, 18846 }, 18847 { 18848 name: "ORWconst", 18849 auxType: auxInt32, 18850 argLen: 1, 18851 resultInArg0: true, 18852 clobberFlags: true, 18853 asm: s390x.AORW, 18854 reg: regInfo{ 18855 inputs: []inputInfo{ 18856 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18857 }, 18858 outputs: []outputInfo{ 18859 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18860 }, 18861 }, 18862 }, 18863 { 18864 name: "ORload", 18865 auxType: auxSymOff, 18866 argLen: 3, 18867 resultInArg0: true, 18868 clobberFlags: true, 18869 faultOnNilArg1: true, 18870 symEffect: SymRead, 18871 asm: s390x.AOR, 18872 reg: regInfo{ 18873 inputs: []inputInfo{ 18874 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18875 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18876 }, 18877 outputs: []outputInfo{ 18878 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18879 }, 18880 }, 18881 }, 18882 { 18883 name: "ORWload", 18884 auxType: auxSymOff, 18885 argLen: 3, 18886 resultInArg0: true, 18887 clobberFlags: true, 18888 faultOnNilArg1: true, 18889 symEffect: SymRead, 18890 asm: s390x.AORW, 18891 reg: regInfo{ 18892 inputs: []inputInfo{ 18893 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18894 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18895 }, 18896 outputs: []outputInfo{ 18897 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18898 }, 18899 }, 18900 }, 18901 { 18902 name: "XOR", 18903 argLen: 2, 18904 commutative: true, 18905 clobberFlags: true, 18906 asm: s390x.AXOR, 18907 reg: regInfo{ 18908 inputs: []inputInfo{ 18909 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18910 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18911 }, 18912 outputs: []outputInfo{ 18913 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18914 }, 18915 }, 18916 }, 18917 { 18918 name: "XORW", 18919 argLen: 2, 18920 commutative: true, 18921 clobberFlags: true, 18922 asm: s390x.AXORW, 18923 reg: regInfo{ 18924 inputs: []inputInfo{ 18925 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18926 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18927 }, 18928 outputs: []outputInfo{ 18929 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18930 }, 18931 }, 18932 }, 18933 { 18934 name: "XORconst", 18935 auxType: auxInt64, 18936 argLen: 1, 18937 resultInArg0: true, 18938 clobberFlags: true, 18939 asm: s390x.AXOR, 18940 reg: regInfo{ 18941 inputs: []inputInfo{ 18942 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18943 }, 18944 outputs: []outputInfo{ 18945 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18946 }, 18947 }, 18948 }, 18949 { 18950 name: "XORWconst", 18951 auxType: auxInt32, 18952 argLen: 1, 18953 resultInArg0: true, 18954 clobberFlags: true, 18955 asm: s390x.AXORW, 18956 reg: regInfo{ 18957 inputs: []inputInfo{ 18958 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18959 }, 18960 outputs: []outputInfo{ 18961 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18962 }, 18963 }, 18964 }, 18965 { 18966 name: "XORload", 18967 auxType: auxSymOff, 18968 argLen: 3, 18969 resultInArg0: true, 18970 clobberFlags: true, 18971 faultOnNilArg1: true, 18972 symEffect: SymRead, 18973 asm: s390x.AXOR, 18974 reg: regInfo{ 18975 inputs: []inputInfo{ 18976 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18977 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18978 }, 18979 outputs: []outputInfo{ 18980 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18981 }, 18982 }, 18983 }, 18984 { 18985 name: "XORWload", 18986 auxType: auxSymOff, 18987 argLen: 3, 18988 resultInArg0: true, 18989 clobberFlags: true, 18990 faultOnNilArg1: true, 18991 symEffect: SymRead, 18992 asm: s390x.AXORW, 18993 reg: regInfo{ 18994 inputs: []inputInfo{ 18995 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18996 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18997 }, 18998 outputs: []outputInfo{ 18999 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19000 }, 19001 }, 19002 }, 19003 { 19004 name: "CMP", 19005 argLen: 2, 19006 asm: s390x.ACMP, 19007 reg: regInfo{ 19008 inputs: []inputInfo{ 19009 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19010 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19011 }, 19012 }, 19013 }, 19014 { 19015 name: "CMPW", 19016 argLen: 2, 19017 asm: s390x.ACMPW, 19018 reg: regInfo{ 19019 inputs: []inputInfo{ 19020 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19021 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19022 }, 19023 }, 19024 }, 19025 { 19026 name: "CMPU", 19027 argLen: 2, 19028 asm: s390x.ACMPU, 19029 reg: regInfo{ 19030 inputs: []inputInfo{ 19031 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19032 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19033 }, 19034 }, 19035 }, 19036 { 19037 name: "CMPWU", 19038 argLen: 2, 19039 asm: s390x.ACMPWU, 19040 reg: regInfo{ 19041 inputs: []inputInfo{ 19042 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19043 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19044 }, 19045 }, 19046 }, 19047 { 19048 name: "CMPconst", 19049 auxType: auxInt64, 19050 argLen: 1, 19051 asm: s390x.ACMP, 19052 reg: regInfo{ 19053 inputs: []inputInfo{ 19054 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19055 }, 19056 }, 19057 }, 19058 { 19059 name: "CMPWconst", 19060 auxType: auxInt32, 19061 argLen: 1, 19062 asm: s390x.ACMPW, 19063 reg: regInfo{ 19064 inputs: []inputInfo{ 19065 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19066 }, 19067 }, 19068 }, 19069 { 19070 name: "CMPUconst", 19071 auxType: auxInt64, 19072 argLen: 1, 19073 asm: s390x.ACMPU, 19074 reg: regInfo{ 19075 inputs: []inputInfo{ 19076 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19077 }, 19078 }, 19079 }, 19080 { 19081 name: "CMPWUconst", 19082 auxType: auxInt32, 19083 argLen: 1, 19084 asm: s390x.ACMPWU, 19085 reg: regInfo{ 19086 inputs: []inputInfo{ 19087 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19088 }, 19089 }, 19090 }, 19091 { 19092 name: "FCMPS", 19093 argLen: 2, 19094 asm: s390x.ACEBR, 19095 reg: regInfo{ 19096 inputs: []inputInfo{ 19097 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19098 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19099 }, 19100 }, 19101 }, 19102 { 19103 name: "FCMP", 19104 argLen: 2, 19105 asm: s390x.AFCMPU, 19106 reg: regInfo{ 19107 inputs: []inputInfo{ 19108 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19109 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19110 }, 19111 }, 19112 }, 19113 { 19114 name: "SLD", 19115 argLen: 2, 19116 asm: s390x.ASLD, 19117 reg: regInfo{ 19118 inputs: []inputInfo{ 19119 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19120 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19121 }, 19122 outputs: []outputInfo{ 19123 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19124 }, 19125 }, 19126 }, 19127 { 19128 name: "SLW", 19129 argLen: 2, 19130 asm: s390x.ASLW, 19131 reg: regInfo{ 19132 inputs: []inputInfo{ 19133 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19134 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19135 }, 19136 outputs: []outputInfo{ 19137 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19138 }, 19139 }, 19140 }, 19141 { 19142 name: "SLDconst", 19143 auxType: auxInt8, 19144 argLen: 1, 19145 asm: s390x.ASLD, 19146 reg: regInfo{ 19147 inputs: []inputInfo{ 19148 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19149 }, 19150 outputs: []outputInfo{ 19151 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19152 }, 19153 }, 19154 }, 19155 { 19156 name: "SLWconst", 19157 auxType: auxInt8, 19158 argLen: 1, 19159 asm: s390x.ASLW, 19160 reg: regInfo{ 19161 inputs: []inputInfo{ 19162 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19163 }, 19164 outputs: []outputInfo{ 19165 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19166 }, 19167 }, 19168 }, 19169 { 19170 name: "SRD", 19171 argLen: 2, 19172 asm: s390x.ASRD, 19173 reg: regInfo{ 19174 inputs: []inputInfo{ 19175 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19176 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19177 }, 19178 outputs: []outputInfo{ 19179 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19180 }, 19181 }, 19182 }, 19183 { 19184 name: "SRW", 19185 argLen: 2, 19186 asm: s390x.ASRW, 19187 reg: regInfo{ 19188 inputs: []inputInfo{ 19189 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19190 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19191 }, 19192 outputs: []outputInfo{ 19193 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19194 }, 19195 }, 19196 }, 19197 { 19198 name: "SRDconst", 19199 auxType: auxInt8, 19200 argLen: 1, 19201 asm: s390x.ASRD, 19202 reg: regInfo{ 19203 inputs: []inputInfo{ 19204 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19205 }, 19206 outputs: []outputInfo{ 19207 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19208 }, 19209 }, 19210 }, 19211 { 19212 name: "SRWconst", 19213 auxType: auxInt8, 19214 argLen: 1, 19215 asm: s390x.ASRW, 19216 reg: regInfo{ 19217 inputs: []inputInfo{ 19218 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19219 }, 19220 outputs: []outputInfo{ 19221 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19222 }, 19223 }, 19224 }, 19225 { 19226 name: "SRAD", 19227 argLen: 2, 19228 clobberFlags: true, 19229 asm: s390x.ASRAD, 19230 reg: regInfo{ 19231 inputs: []inputInfo{ 19232 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19233 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19234 }, 19235 outputs: []outputInfo{ 19236 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19237 }, 19238 }, 19239 }, 19240 { 19241 name: "SRAW", 19242 argLen: 2, 19243 clobberFlags: true, 19244 asm: s390x.ASRAW, 19245 reg: regInfo{ 19246 inputs: []inputInfo{ 19247 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19248 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19249 }, 19250 outputs: []outputInfo{ 19251 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19252 }, 19253 }, 19254 }, 19255 { 19256 name: "SRADconst", 19257 auxType: auxInt8, 19258 argLen: 1, 19259 clobberFlags: true, 19260 asm: s390x.ASRAD, 19261 reg: regInfo{ 19262 inputs: []inputInfo{ 19263 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19264 }, 19265 outputs: []outputInfo{ 19266 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19267 }, 19268 }, 19269 }, 19270 { 19271 name: "SRAWconst", 19272 auxType: auxInt8, 19273 argLen: 1, 19274 clobberFlags: true, 19275 asm: s390x.ASRAW, 19276 reg: regInfo{ 19277 inputs: []inputInfo{ 19278 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19279 }, 19280 outputs: []outputInfo{ 19281 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19282 }, 19283 }, 19284 }, 19285 { 19286 name: "RLLGconst", 19287 auxType: auxInt8, 19288 argLen: 1, 19289 asm: s390x.ARLLG, 19290 reg: regInfo{ 19291 inputs: []inputInfo{ 19292 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19293 }, 19294 outputs: []outputInfo{ 19295 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19296 }, 19297 }, 19298 }, 19299 { 19300 name: "RLLconst", 19301 auxType: auxInt8, 19302 argLen: 1, 19303 asm: s390x.ARLL, 19304 reg: regInfo{ 19305 inputs: []inputInfo{ 19306 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19307 }, 19308 outputs: []outputInfo{ 19309 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19310 }, 19311 }, 19312 }, 19313 { 19314 name: "NEG", 19315 argLen: 1, 19316 clobberFlags: true, 19317 asm: s390x.ANEG, 19318 reg: regInfo{ 19319 inputs: []inputInfo{ 19320 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19321 }, 19322 outputs: []outputInfo{ 19323 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19324 }, 19325 }, 19326 }, 19327 { 19328 name: "NEGW", 19329 argLen: 1, 19330 clobberFlags: true, 19331 asm: s390x.ANEGW, 19332 reg: regInfo{ 19333 inputs: []inputInfo{ 19334 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19335 }, 19336 outputs: []outputInfo{ 19337 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19338 }, 19339 }, 19340 }, 19341 { 19342 name: "NOT", 19343 argLen: 1, 19344 resultInArg0: true, 19345 clobberFlags: true, 19346 reg: regInfo{ 19347 inputs: []inputInfo{ 19348 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19349 }, 19350 outputs: []outputInfo{ 19351 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19352 }, 19353 }, 19354 }, 19355 { 19356 name: "NOTW", 19357 argLen: 1, 19358 resultInArg0: true, 19359 clobberFlags: true, 19360 reg: regInfo{ 19361 inputs: []inputInfo{ 19362 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19363 }, 19364 outputs: []outputInfo{ 19365 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19366 }, 19367 }, 19368 }, 19369 { 19370 name: "FSQRT", 19371 argLen: 1, 19372 asm: s390x.AFSQRT, 19373 reg: regInfo{ 19374 inputs: []inputInfo{ 19375 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19376 }, 19377 outputs: []outputInfo{ 19378 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19379 }, 19380 }, 19381 }, 19382 { 19383 name: "SUBEcarrymask", 19384 argLen: 1, 19385 asm: s390x.ASUBE, 19386 reg: regInfo{ 19387 outputs: []outputInfo{ 19388 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19389 }, 19390 }, 19391 }, 19392 { 19393 name: "SUBEWcarrymask", 19394 argLen: 1, 19395 asm: s390x.ASUBE, 19396 reg: regInfo{ 19397 outputs: []outputInfo{ 19398 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19399 }, 19400 }, 19401 }, 19402 { 19403 name: "MOVDEQ", 19404 argLen: 3, 19405 resultInArg0: true, 19406 asm: s390x.AMOVDEQ, 19407 reg: regInfo{ 19408 inputs: []inputInfo{ 19409 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19410 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19411 }, 19412 outputs: []outputInfo{ 19413 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19414 }, 19415 }, 19416 }, 19417 { 19418 name: "MOVDNE", 19419 argLen: 3, 19420 resultInArg0: true, 19421 asm: s390x.AMOVDNE, 19422 reg: regInfo{ 19423 inputs: []inputInfo{ 19424 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19425 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19426 }, 19427 outputs: []outputInfo{ 19428 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19429 }, 19430 }, 19431 }, 19432 { 19433 name: "MOVDLT", 19434 argLen: 3, 19435 resultInArg0: true, 19436 asm: s390x.AMOVDLT, 19437 reg: regInfo{ 19438 inputs: []inputInfo{ 19439 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19440 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19441 }, 19442 outputs: []outputInfo{ 19443 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19444 }, 19445 }, 19446 }, 19447 { 19448 name: "MOVDLE", 19449 argLen: 3, 19450 resultInArg0: true, 19451 asm: s390x.AMOVDLE, 19452 reg: regInfo{ 19453 inputs: []inputInfo{ 19454 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19455 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19456 }, 19457 outputs: []outputInfo{ 19458 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19459 }, 19460 }, 19461 }, 19462 { 19463 name: "MOVDGT", 19464 argLen: 3, 19465 resultInArg0: true, 19466 asm: s390x.AMOVDGT, 19467 reg: regInfo{ 19468 inputs: []inputInfo{ 19469 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19470 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19471 }, 19472 outputs: []outputInfo{ 19473 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19474 }, 19475 }, 19476 }, 19477 { 19478 name: "MOVDGE", 19479 argLen: 3, 19480 resultInArg0: true, 19481 asm: s390x.AMOVDGE, 19482 reg: regInfo{ 19483 inputs: []inputInfo{ 19484 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19485 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19486 }, 19487 outputs: []outputInfo{ 19488 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19489 }, 19490 }, 19491 }, 19492 { 19493 name: "MOVDGTnoinv", 19494 argLen: 3, 19495 resultInArg0: true, 19496 asm: s390x.AMOVDGT, 19497 reg: regInfo{ 19498 inputs: []inputInfo{ 19499 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19500 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19501 }, 19502 outputs: []outputInfo{ 19503 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19504 }, 19505 }, 19506 }, 19507 { 19508 name: "MOVDGEnoinv", 19509 argLen: 3, 19510 resultInArg0: true, 19511 asm: s390x.AMOVDGE, 19512 reg: regInfo{ 19513 inputs: []inputInfo{ 19514 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19515 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19516 }, 19517 outputs: []outputInfo{ 19518 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19519 }, 19520 }, 19521 }, 19522 { 19523 name: "MOVBreg", 19524 argLen: 1, 19525 asm: s390x.AMOVB, 19526 reg: regInfo{ 19527 inputs: []inputInfo{ 19528 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19529 }, 19530 outputs: []outputInfo{ 19531 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19532 }, 19533 }, 19534 }, 19535 { 19536 name: "MOVBZreg", 19537 argLen: 1, 19538 asm: s390x.AMOVBZ, 19539 reg: regInfo{ 19540 inputs: []inputInfo{ 19541 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19542 }, 19543 outputs: []outputInfo{ 19544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19545 }, 19546 }, 19547 }, 19548 { 19549 name: "MOVHreg", 19550 argLen: 1, 19551 asm: s390x.AMOVH, 19552 reg: regInfo{ 19553 inputs: []inputInfo{ 19554 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19555 }, 19556 outputs: []outputInfo{ 19557 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19558 }, 19559 }, 19560 }, 19561 { 19562 name: "MOVHZreg", 19563 argLen: 1, 19564 asm: s390x.AMOVHZ, 19565 reg: regInfo{ 19566 inputs: []inputInfo{ 19567 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19568 }, 19569 outputs: []outputInfo{ 19570 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19571 }, 19572 }, 19573 }, 19574 { 19575 name: "MOVWreg", 19576 argLen: 1, 19577 asm: s390x.AMOVW, 19578 reg: regInfo{ 19579 inputs: []inputInfo{ 19580 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19581 }, 19582 outputs: []outputInfo{ 19583 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19584 }, 19585 }, 19586 }, 19587 { 19588 name: "MOVWZreg", 19589 argLen: 1, 19590 asm: s390x.AMOVWZ, 19591 reg: regInfo{ 19592 inputs: []inputInfo{ 19593 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19594 }, 19595 outputs: []outputInfo{ 19596 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19597 }, 19598 }, 19599 }, 19600 { 19601 name: "MOVDreg", 19602 argLen: 1, 19603 asm: s390x.AMOVD, 19604 reg: regInfo{ 19605 inputs: []inputInfo{ 19606 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19607 }, 19608 outputs: []outputInfo{ 19609 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19610 }, 19611 }, 19612 }, 19613 { 19614 name: "MOVDnop", 19615 argLen: 1, 19616 resultInArg0: true, 19617 reg: regInfo{ 19618 inputs: []inputInfo{ 19619 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19620 }, 19621 outputs: []outputInfo{ 19622 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19623 }, 19624 }, 19625 }, 19626 { 19627 name: "MOVDconst", 19628 auxType: auxInt64, 19629 argLen: 0, 19630 rematerializeable: true, 19631 asm: s390x.AMOVD, 19632 reg: regInfo{ 19633 outputs: []outputInfo{ 19634 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19635 }, 19636 }, 19637 }, 19638 { 19639 name: "CFDBRA", 19640 argLen: 1, 19641 asm: s390x.ACFDBRA, 19642 reg: regInfo{ 19643 inputs: []inputInfo{ 19644 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19645 }, 19646 outputs: []outputInfo{ 19647 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19648 }, 19649 }, 19650 }, 19651 { 19652 name: "CGDBRA", 19653 argLen: 1, 19654 asm: s390x.ACGDBRA, 19655 reg: regInfo{ 19656 inputs: []inputInfo{ 19657 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19658 }, 19659 outputs: []outputInfo{ 19660 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19661 }, 19662 }, 19663 }, 19664 { 19665 name: "CFEBRA", 19666 argLen: 1, 19667 asm: s390x.ACFEBRA, 19668 reg: regInfo{ 19669 inputs: []inputInfo{ 19670 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19671 }, 19672 outputs: []outputInfo{ 19673 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19674 }, 19675 }, 19676 }, 19677 { 19678 name: "CGEBRA", 19679 argLen: 1, 19680 asm: s390x.ACGEBRA, 19681 reg: regInfo{ 19682 inputs: []inputInfo{ 19683 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19684 }, 19685 outputs: []outputInfo{ 19686 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19687 }, 19688 }, 19689 }, 19690 { 19691 name: "CEFBRA", 19692 argLen: 1, 19693 asm: s390x.ACEFBRA, 19694 reg: regInfo{ 19695 inputs: []inputInfo{ 19696 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19697 }, 19698 outputs: []outputInfo{ 19699 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19700 }, 19701 }, 19702 }, 19703 { 19704 name: "CDFBRA", 19705 argLen: 1, 19706 asm: s390x.ACDFBRA, 19707 reg: regInfo{ 19708 inputs: []inputInfo{ 19709 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19710 }, 19711 outputs: []outputInfo{ 19712 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19713 }, 19714 }, 19715 }, 19716 { 19717 name: "CEGBRA", 19718 argLen: 1, 19719 asm: s390x.ACEGBRA, 19720 reg: regInfo{ 19721 inputs: []inputInfo{ 19722 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19723 }, 19724 outputs: []outputInfo{ 19725 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19726 }, 19727 }, 19728 }, 19729 { 19730 name: "CDGBRA", 19731 argLen: 1, 19732 asm: s390x.ACDGBRA, 19733 reg: regInfo{ 19734 inputs: []inputInfo{ 19735 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19736 }, 19737 outputs: []outputInfo{ 19738 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19739 }, 19740 }, 19741 }, 19742 { 19743 name: "LEDBR", 19744 argLen: 1, 19745 asm: s390x.ALEDBR, 19746 reg: regInfo{ 19747 inputs: []inputInfo{ 19748 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19749 }, 19750 outputs: []outputInfo{ 19751 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19752 }, 19753 }, 19754 }, 19755 { 19756 name: "LDEBR", 19757 argLen: 1, 19758 asm: s390x.ALDEBR, 19759 reg: regInfo{ 19760 inputs: []inputInfo{ 19761 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19762 }, 19763 outputs: []outputInfo{ 19764 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19765 }, 19766 }, 19767 }, 19768 { 19769 name: "MOVDaddr", 19770 auxType: auxSymOff, 19771 argLen: 1, 19772 rematerializeable: true, 19773 clobberFlags: true, 19774 symEffect: SymRead, 19775 reg: regInfo{ 19776 inputs: []inputInfo{ 19777 {0, 4295000064}, // SP SB 19778 }, 19779 outputs: []outputInfo{ 19780 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19781 }, 19782 }, 19783 }, 19784 { 19785 name: "MOVDaddridx", 19786 auxType: auxSymOff, 19787 argLen: 2, 19788 clobberFlags: true, 19789 symEffect: SymRead, 19790 reg: regInfo{ 19791 inputs: []inputInfo{ 19792 {0, 4295000064}, // SP SB 19793 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19794 }, 19795 outputs: []outputInfo{ 19796 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19797 }, 19798 }, 19799 }, 19800 { 19801 name: "MOVBZload", 19802 auxType: auxSymOff, 19803 argLen: 2, 19804 clobberFlags: true, 19805 faultOnNilArg0: true, 19806 symEffect: SymRead, 19807 asm: s390x.AMOVBZ, 19808 reg: regInfo{ 19809 inputs: []inputInfo{ 19810 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19811 }, 19812 outputs: []outputInfo{ 19813 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19814 }, 19815 }, 19816 }, 19817 { 19818 name: "MOVBload", 19819 auxType: auxSymOff, 19820 argLen: 2, 19821 clobberFlags: true, 19822 faultOnNilArg0: true, 19823 symEffect: SymRead, 19824 asm: s390x.AMOVB, 19825 reg: regInfo{ 19826 inputs: []inputInfo{ 19827 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19828 }, 19829 outputs: []outputInfo{ 19830 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19831 }, 19832 }, 19833 }, 19834 { 19835 name: "MOVHZload", 19836 auxType: auxSymOff, 19837 argLen: 2, 19838 clobberFlags: true, 19839 faultOnNilArg0: true, 19840 symEffect: SymRead, 19841 asm: s390x.AMOVHZ, 19842 reg: regInfo{ 19843 inputs: []inputInfo{ 19844 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19845 }, 19846 outputs: []outputInfo{ 19847 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19848 }, 19849 }, 19850 }, 19851 { 19852 name: "MOVHload", 19853 auxType: auxSymOff, 19854 argLen: 2, 19855 clobberFlags: true, 19856 faultOnNilArg0: true, 19857 symEffect: SymRead, 19858 asm: s390x.AMOVH, 19859 reg: regInfo{ 19860 inputs: []inputInfo{ 19861 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19862 }, 19863 outputs: []outputInfo{ 19864 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19865 }, 19866 }, 19867 }, 19868 { 19869 name: "MOVWZload", 19870 auxType: auxSymOff, 19871 argLen: 2, 19872 clobberFlags: true, 19873 faultOnNilArg0: true, 19874 symEffect: SymRead, 19875 asm: s390x.AMOVWZ, 19876 reg: regInfo{ 19877 inputs: []inputInfo{ 19878 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19879 }, 19880 outputs: []outputInfo{ 19881 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19882 }, 19883 }, 19884 }, 19885 { 19886 name: "MOVWload", 19887 auxType: auxSymOff, 19888 argLen: 2, 19889 clobberFlags: true, 19890 faultOnNilArg0: true, 19891 symEffect: SymRead, 19892 asm: s390x.AMOVW, 19893 reg: regInfo{ 19894 inputs: []inputInfo{ 19895 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19896 }, 19897 outputs: []outputInfo{ 19898 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19899 }, 19900 }, 19901 }, 19902 { 19903 name: "MOVDload", 19904 auxType: auxSymOff, 19905 argLen: 2, 19906 clobberFlags: true, 19907 faultOnNilArg0: true, 19908 symEffect: SymRead, 19909 asm: s390x.AMOVD, 19910 reg: regInfo{ 19911 inputs: []inputInfo{ 19912 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19913 }, 19914 outputs: []outputInfo{ 19915 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19916 }, 19917 }, 19918 }, 19919 { 19920 name: "MOVWBR", 19921 argLen: 1, 19922 asm: s390x.AMOVWBR, 19923 reg: regInfo{ 19924 inputs: []inputInfo{ 19925 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19926 }, 19927 outputs: []outputInfo{ 19928 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19929 }, 19930 }, 19931 }, 19932 { 19933 name: "MOVDBR", 19934 argLen: 1, 19935 asm: s390x.AMOVDBR, 19936 reg: regInfo{ 19937 inputs: []inputInfo{ 19938 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19939 }, 19940 outputs: []outputInfo{ 19941 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19942 }, 19943 }, 19944 }, 19945 { 19946 name: "MOVHBRload", 19947 auxType: auxSymOff, 19948 argLen: 2, 19949 clobberFlags: true, 19950 faultOnNilArg0: true, 19951 symEffect: SymRead, 19952 asm: s390x.AMOVHBR, 19953 reg: regInfo{ 19954 inputs: []inputInfo{ 19955 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19956 }, 19957 outputs: []outputInfo{ 19958 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19959 }, 19960 }, 19961 }, 19962 { 19963 name: "MOVWBRload", 19964 auxType: auxSymOff, 19965 argLen: 2, 19966 clobberFlags: true, 19967 faultOnNilArg0: true, 19968 symEffect: SymRead, 19969 asm: s390x.AMOVWBR, 19970 reg: regInfo{ 19971 inputs: []inputInfo{ 19972 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19973 }, 19974 outputs: []outputInfo{ 19975 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19976 }, 19977 }, 19978 }, 19979 { 19980 name: "MOVDBRload", 19981 auxType: auxSymOff, 19982 argLen: 2, 19983 clobberFlags: true, 19984 faultOnNilArg0: true, 19985 symEffect: SymRead, 19986 asm: s390x.AMOVDBR, 19987 reg: regInfo{ 19988 inputs: []inputInfo{ 19989 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19990 }, 19991 outputs: []outputInfo{ 19992 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19993 }, 19994 }, 19995 }, 19996 { 19997 name: "MOVBstore", 19998 auxType: auxSymOff, 19999 argLen: 3, 20000 clobberFlags: true, 20001 faultOnNilArg0: true, 20002 symEffect: SymWrite, 20003 asm: s390x.AMOVB, 20004 reg: regInfo{ 20005 inputs: []inputInfo{ 20006 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20007 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20008 }, 20009 }, 20010 }, 20011 { 20012 name: "MOVHstore", 20013 auxType: auxSymOff, 20014 argLen: 3, 20015 clobberFlags: true, 20016 faultOnNilArg0: true, 20017 symEffect: SymWrite, 20018 asm: s390x.AMOVH, 20019 reg: regInfo{ 20020 inputs: []inputInfo{ 20021 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20022 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20023 }, 20024 }, 20025 }, 20026 { 20027 name: "MOVWstore", 20028 auxType: auxSymOff, 20029 argLen: 3, 20030 clobberFlags: true, 20031 faultOnNilArg0: true, 20032 symEffect: SymWrite, 20033 asm: s390x.AMOVW, 20034 reg: regInfo{ 20035 inputs: []inputInfo{ 20036 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20037 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20038 }, 20039 }, 20040 }, 20041 { 20042 name: "MOVDstore", 20043 auxType: auxSymOff, 20044 argLen: 3, 20045 clobberFlags: true, 20046 faultOnNilArg0: true, 20047 symEffect: SymWrite, 20048 asm: s390x.AMOVD, 20049 reg: regInfo{ 20050 inputs: []inputInfo{ 20051 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20052 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20053 }, 20054 }, 20055 }, 20056 { 20057 name: "MOVHBRstore", 20058 auxType: auxSymOff, 20059 argLen: 3, 20060 clobberFlags: true, 20061 faultOnNilArg0: true, 20062 symEffect: SymWrite, 20063 asm: s390x.AMOVHBR, 20064 reg: regInfo{ 20065 inputs: []inputInfo{ 20066 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20067 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20068 }, 20069 }, 20070 }, 20071 { 20072 name: "MOVWBRstore", 20073 auxType: auxSymOff, 20074 argLen: 3, 20075 clobberFlags: true, 20076 faultOnNilArg0: true, 20077 symEffect: SymWrite, 20078 asm: s390x.AMOVWBR, 20079 reg: regInfo{ 20080 inputs: []inputInfo{ 20081 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20082 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20083 }, 20084 }, 20085 }, 20086 { 20087 name: "MOVDBRstore", 20088 auxType: auxSymOff, 20089 argLen: 3, 20090 clobberFlags: true, 20091 faultOnNilArg0: true, 20092 symEffect: SymWrite, 20093 asm: s390x.AMOVDBR, 20094 reg: regInfo{ 20095 inputs: []inputInfo{ 20096 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20097 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20098 }, 20099 }, 20100 }, 20101 { 20102 name: "MVC", 20103 auxType: auxSymValAndOff, 20104 argLen: 3, 20105 clobberFlags: true, 20106 faultOnNilArg0: true, 20107 faultOnNilArg1: true, 20108 symEffect: SymNone, 20109 asm: s390x.AMVC, 20110 reg: regInfo{ 20111 inputs: []inputInfo{ 20112 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20113 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20114 }, 20115 }, 20116 }, 20117 { 20118 name: "MOVBZloadidx", 20119 auxType: auxSymOff, 20120 argLen: 3, 20121 commutative: true, 20122 clobberFlags: true, 20123 symEffect: SymRead, 20124 asm: s390x.AMOVBZ, 20125 reg: regInfo{ 20126 inputs: []inputInfo{ 20127 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20128 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20129 }, 20130 outputs: []outputInfo{ 20131 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20132 }, 20133 }, 20134 }, 20135 { 20136 name: "MOVHZloadidx", 20137 auxType: auxSymOff, 20138 argLen: 3, 20139 commutative: true, 20140 clobberFlags: true, 20141 symEffect: SymRead, 20142 asm: s390x.AMOVHZ, 20143 reg: regInfo{ 20144 inputs: []inputInfo{ 20145 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20146 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20147 }, 20148 outputs: []outputInfo{ 20149 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20150 }, 20151 }, 20152 }, 20153 { 20154 name: "MOVWZloadidx", 20155 auxType: auxSymOff, 20156 argLen: 3, 20157 commutative: true, 20158 clobberFlags: true, 20159 symEffect: SymRead, 20160 asm: s390x.AMOVWZ, 20161 reg: regInfo{ 20162 inputs: []inputInfo{ 20163 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20164 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20165 }, 20166 outputs: []outputInfo{ 20167 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20168 }, 20169 }, 20170 }, 20171 { 20172 name: "MOVDloadidx", 20173 auxType: auxSymOff, 20174 argLen: 3, 20175 commutative: true, 20176 clobberFlags: true, 20177 symEffect: SymRead, 20178 asm: s390x.AMOVD, 20179 reg: regInfo{ 20180 inputs: []inputInfo{ 20181 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20182 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20183 }, 20184 outputs: []outputInfo{ 20185 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20186 }, 20187 }, 20188 }, 20189 { 20190 name: "MOVHBRloadidx", 20191 auxType: auxSymOff, 20192 argLen: 3, 20193 commutative: true, 20194 clobberFlags: true, 20195 symEffect: SymRead, 20196 asm: s390x.AMOVHBR, 20197 reg: regInfo{ 20198 inputs: []inputInfo{ 20199 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20200 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20201 }, 20202 outputs: []outputInfo{ 20203 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20204 }, 20205 }, 20206 }, 20207 { 20208 name: "MOVWBRloadidx", 20209 auxType: auxSymOff, 20210 argLen: 3, 20211 commutative: true, 20212 clobberFlags: true, 20213 symEffect: SymRead, 20214 asm: s390x.AMOVWBR, 20215 reg: regInfo{ 20216 inputs: []inputInfo{ 20217 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20218 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20219 }, 20220 outputs: []outputInfo{ 20221 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20222 }, 20223 }, 20224 }, 20225 { 20226 name: "MOVDBRloadidx", 20227 auxType: auxSymOff, 20228 argLen: 3, 20229 commutative: true, 20230 clobberFlags: true, 20231 symEffect: SymRead, 20232 asm: s390x.AMOVDBR, 20233 reg: regInfo{ 20234 inputs: []inputInfo{ 20235 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20236 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20237 }, 20238 outputs: []outputInfo{ 20239 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20240 }, 20241 }, 20242 }, 20243 { 20244 name: "MOVBstoreidx", 20245 auxType: auxSymOff, 20246 argLen: 4, 20247 commutative: true, 20248 clobberFlags: true, 20249 symEffect: SymWrite, 20250 asm: s390x.AMOVB, 20251 reg: regInfo{ 20252 inputs: []inputInfo{ 20253 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20254 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20255 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20256 }, 20257 }, 20258 }, 20259 { 20260 name: "MOVHstoreidx", 20261 auxType: auxSymOff, 20262 argLen: 4, 20263 commutative: true, 20264 clobberFlags: true, 20265 symEffect: SymWrite, 20266 asm: s390x.AMOVH, 20267 reg: regInfo{ 20268 inputs: []inputInfo{ 20269 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20270 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20271 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20272 }, 20273 }, 20274 }, 20275 { 20276 name: "MOVWstoreidx", 20277 auxType: auxSymOff, 20278 argLen: 4, 20279 commutative: true, 20280 clobberFlags: true, 20281 symEffect: SymWrite, 20282 asm: s390x.AMOVW, 20283 reg: regInfo{ 20284 inputs: []inputInfo{ 20285 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20286 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20287 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20288 }, 20289 }, 20290 }, 20291 { 20292 name: "MOVDstoreidx", 20293 auxType: auxSymOff, 20294 argLen: 4, 20295 commutative: true, 20296 clobberFlags: true, 20297 symEffect: SymWrite, 20298 asm: s390x.AMOVD, 20299 reg: regInfo{ 20300 inputs: []inputInfo{ 20301 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20302 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20303 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20304 }, 20305 }, 20306 }, 20307 { 20308 name: "MOVHBRstoreidx", 20309 auxType: auxSymOff, 20310 argLen: 4, 20311 commutative: true, 20312 clobberFlags: true, 20313 symEffect: SymWrite, 20314 asm: s390x.AMOVHBR, 20315 reg: regInfo{ 20316 inputs: []inputInfo{ 20317 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20318 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20319 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20320 }, 20321 }, 20322 }, 20323 { 20324 name: "MOVWBRstoreidx", 20325 auxType: auxSymOff, 20326 argLen: 4, 20327 commutative: true, 20328 clobberFlags: true, 20329 symEffect: SymWrite, 20330 asm: s390x.AMOVWBR, 20331 reg: regInfo{ 20332 inputs: []inputInfo{ 20333 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20334 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20335 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20336 }, 20337 }, 20338 }, 20339 { 20340 name: "MOVDBRstoreidx", 20341 auxType: auxSymOff, 20342 argLen: 4, 20343 commutative: true, 20344 clobberFlags: true, 20345 symEffect: SymWrite, 20346 asm: s390x.AMOVDBR, 20347 reg: regInfo{ 20348 inputs: []inputInfo{ 20349 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20350 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20351 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20352 }, 20353 }, 20354 }, 20355 { 20356 name: "MOVBstoreconst", 20357 auxType: auxSymValAndOff, 20358 argLen: 2, 20359 clobberFlags: true, 20360 faultOnNilArg0: true, 20361 symEffect: SymWrite, 20362 asm: s390x.AMOVB, 20363 reg: regInfo{ 20364 inputs: []inputInfo{ 20365 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20366 }, 20367 }, 20368 }, 20369 { 20370 name: "MOVHstoreconst", 20371 auxType: auxSymValAndOff, 20372 argLen: 2, 20373 clobberFlags: true, 20374 faultOnNilArg0: true, 20375 symEffect: SymWrite, 20376 asm: s390x.AMOVH, 20377 reg: regInfo{ 20378 inputs: []inputInfo{ 20379 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20380 }, 20381 }, 20382 }, 20383 { 20384 name: "MOVWstoreconst", 20385 auxType: auxSymValAndOff, 20386 argLen: 2, 20387 clobberFlags: true, 20388 faultOnNilArg0: true, 20389 symEffect: SymWrite, 20390 asm: s390x.AMOVW, 20391 reg: regInfo{ 20392 inputs: []inputInfo{ 20393 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20394 }, 20395 }, 20396 }, 20397 { 20398 name: "MOVDstoreconst", 20399 auxType: auxSymValAndOff, 20400 argLen: 2, 20401 clobberFlags: true, 20402 faultOnNilArg0: true, 20403 symEffect: SymWrite, 20404 asm: s390x.AMOVD, 20405 reg: regInfo{ 20406 inputs: []inputInfo{ 20407 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20408 }, 20409 }, 20410 }, 20411 { 20412 name: "CLEAR", 20413 auxType: auxSymValAndOff, 20414 argLen: 2, 20415 clobberFlags: true, 20416 faultOnNilArg0: true, 20417 symEffect: SymWrite, 20418 asm: s390x.ACLEAR, 20419 reg: regInfo{ 20420 inputs: []inputInfo{ 20421 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20422 }, 20423 }, 20424 }, 20425 { 20426 name: "CALLstatic", 20427 auxType: auxSymOff, 20428 argLen: 1, 20429 clobberFlags: true, 20430 call: true, 20431 symEffect: SymNone, 20432 reg: regInfo{ 20433 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20434 }, 20435 }, 20436 { 20437 name: "CALLclosure", 20438 auxType: auxInt64, 20439 argLen: 3, 20440 clobberFlags: true, 20441 call: true, 20442 reg: regInfo{ 20443 inputs: []inputInfo{ 20444 {1, 4096}, // R12 20445 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20446 }, 20447 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20448 }, 20449 }, 20450 { 20451 name: "CALLinter", 20452 auxType: auxInt64, 20453 argLen: 2, 20454 clobberFlags: true, 20455 call: true, 20456 reg: regInfo{ 20457 inputs: []inputInfo{ 20458 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20459 }, 20460 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20461 }, 20462 }, 20463 { 20464 name: "InvertFlags", 20465 argLen: 1, 20466 reg: regInfo{}, 20467 }, 20468 { 20469 name: "LoweredGetG", 20470 argLen: 1, 20471 reg: regInfo{ 20472 outputs: []outputInfo{ 20473 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20474 }, 20475 }, 20476 }, 20477 { 20478 name: "LoweredGetClosurePtr", 20479 argLen: 0, 20480 reg: regInfo{ 20481 outputs: []outputInfo{ 20482 {0, 4096}, // R12 20483 }, 20484 }, 20485 }, 20486 { 20487 name: "LoweredNilCheck", 20488 argLen: 2, 20489 clobberFlags: true, 20490 nilCheck: true, 20491 faultOnNilArg0: true, 20492 reg: regInfo{ 20493 inputs: []inputInfo{ 20494 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20495 }, 20496 }, 20497 }, 20498 { 20499 name: "LoweredRound32F", 20500 argLen: 1, 20501 resultInArg0: true, 20502 reg: regInfo{ 20503 inputs: []inputInfo{ 20504 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20505 }, 20506 outputs: []outputInfo{ 20507 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20508 }, 20509 }, 20510 }, 20511 { 20512 name: "LoweredRound64F", 20513 argLen: 1, 20514 resultInArg0: true, 20515 reg: regInfo{ 20516 inputs: []inputInfo{ 20517 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20518 }, 20519 outputs: []outputInfo{ 20520 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20521 }, 20522 }, 20523 }, 20524 { 20525 name: "MOVDconvert", 20526 argLen: 2, 20527 asm: s390x.AMOVD, 20528 reg: regInfo{ 20529 inputs: []inputInfo{ 20530 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20531 }, 20532 outputs: []outputInfo{ 20533 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20534 }, 20535 }, 20536 }, 20537 { 20538 name: "FlagEQ", 20539 argLen: 0, 20540 reg: regInfo{}, 20541 }, 20542 { 20543 name: "FlagLT", 20544 argLen: 0, 20545 reg: regInfo{}, 20546 }, 20547 { 20548 name: "FlagGT", 20549 argLen: 0, 20550 reg: regInfo{}, 20551 }, 20552 { 20553 name: "MOVWZatomicload", 20554 auxType: auxSymOff, 20555 argLen: 2, 20556 faultOnNilArg0: true, 20557 symEffect: SymRead, 20558 asm: s390x.AMOVWZ, 20559 reg: regInfo{ 20560 inputs: []inputInfo{ 20561 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20562 }, 20563 outputs: []outputInfo{ 20564 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20565 }, 20566 }, 20567 }, 20568 { 20569 name: "MOVDatomicload", 20570 auxType: auxSymOff, 20571 argLen: 2, 20572 faultOnNilArg0: true, 20573 symEffect: SymRead, 20574 asm: s390x.AMOVD, 20575 reg: regInfo{ 20576 inputs: []inputInfo{ 20577 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20578 }, 20579 outputs: []outputInfo{ 20580 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20581 }, 20582 }, 20583 }, 20584 { 20585 name: "MOVWatomicstore", 20586 auxType: auxSymOff, 20587 argLen: 3, 20588 clobberFlags: true, 20589 faultOnNilArg0: true, 20590 hasSideEffects: true, 20591 symEffect: SymWrite, 20592 asm: s390x.AMOVW, 20593 reg: regInfo{ 20594 inputs: []inputInfo{ 20595 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20596 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20597 }, 20598 }, 20599 }, 20600 { 20601 name: "MOVDatomicstore", 20602 auxType: auxSymOff, 20603 argLen: 3, 20604 clobberFlags: true, 20605 faultOnNilArg0: true, 20606 hasSideEffects: true, 20607 symEffect: SymWrite, 20608 asm: s390x.AMOVD, 20609 reg: regInfo{ 20610 inputs: []inputInfo{ 20611 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20612 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20613 }, 20614 }, 20615 }, 20616 { 20617 name: "LAA", 20618 auxType: auxSymOff, 20619 argLen: 3, 20620 faultOnNilArg0: true, 20621 hasSideEffects: true, 20622 symEffect: SymRdWr, 20623 asm: s390x.ALAA, 20624 reg: regInfo{ 20625 inputs: []inputInfo{ 20626 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20627 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20628 }, 20629 outputs: []outputInfo{ 20630 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20631 }, 20632 }, 20633 }, 20634 { 20635 name: "LAAG", 20636 auxType: auxSymOff, 20637 argLen: 3, 20638 faultOnNilArg0: true, 20639 hasSideEffects: true, 20640 symEffect: SymRdWr, 20641 asm: s390x.ALAAG, 20642 reg: regInfo{ 20643 inputs: []inputInfo{ 20644 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20645 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20646 }, 20647 outputs: []outputInfo{ 20648 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20649 }, 20650 }, 20651 }, 20652 { 20653 name: "AddTupleFirst32", 20654 argLen: 2, 20655 reg: regInfo{}, 20656 }, 20657 { 20658 name: "AddTupleFirst64", 20659 argLen: 2, 20660 reg: regInfo{}, 20661 }, 20662 { 20663 name: "LoweredAtomicCas32", 20664 auxType: auxSymOff, 20665 argLen: 4, 20666 clobberFlags: true, 20667 faultOnNilArg0: true, 20668 hasSideEffects: true, 20669 symEffect: SymRdWr, 20670 asm: s390x.ACS, 20671 reg: regInfo{ 20672 inputs: []inputInfo{ 20673 {1, 1}, // R0 20674 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20675 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20676 }, 20677 clobbers: 1, // R0 20678 outputs: []outputInfo{ 20679 {1, 0}, 20680 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20681 }, 20682 }, 20683 }, 20684 { 20685 name: "LoweredAtomicCas64", 20686 auxType: auxSymOff, 20687 argLen: 4, 20688 clobberFlags: true, 20689 faultOnNilArg0: true, 20690 hasSideEffects: true, 20691 symEffect: SymRdWr, 20692 asm: s390x.ACSG, 20693 reg: regInfo{ 20694 inputs: []inputInfo{ 20695 {1, 1}, // R0 20696 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20697 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20698 }, 20699 clobbers: 1, // R0 20700 outputs: []outputInfo{ 20701 {1, 0}, 20702 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20703 }, 20704 }, 20705 }, 20706 { 20707 name: "LoweredAtomicExchange32", 20708 auxType: auxSymOff, 20709 argLen: 3, 20710 clobberFlags: true, 20711 faultOnNilArg0: true, 20712 hasSideEffects: true, 20713 symEffect: SymRdWr, 20714 asm: s390x.ACS, 20715 reg: regInfo{ 20716 inputs: []inputInfo{ 20717 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20718 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20719 }, 20720 outputs: []outputInfo{ 20721 {1, 0}, 20722 {0, 1}, // R0 20723 }, 20724 }, 20725 }, 20726 { 20727 name: "LoweredAtomicExchange64", 20728 auxType: auxSymOff, 20729 argLen: 3, 20730 clobberFlags: true, 20731 faultOnNilArg0: true, 20732 hasSideEffects: true, 20733 symEffect: SymRdWr, 20734 asm: s390x.ACSG, 20735 reg: regInfo{ 20736 inputs: []inputInfo{ 20737 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20738 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20739 }, 20740 outputs: []outputInfo{ 20741 {1, 0}, 20742 {0, 1}, // R0 20743 }, 20744 }, 20745 }, 20746 { 20747 name: "FLOGR", 20748 argLen: 1, 20749 clobberFlags: true, 20750 asm: s390x.AFLOGR, 20751 reg: regInfo{ 20752 inputs: []inputInfo{ 20753 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20754 }, 20755 clobbers: 2, // R1 20756 outputs: []outputInfo{ 20757 {0, 1}, // R0 20758 }, 20759 }, 20760 }, 20761 { 20762 name: "STMG2", 20763 auxType: auxSymOff, 20764 argLen: 4, 20765 faultOnNilArg0: true, 20766 symEffect: SymWrite, 20767 asm: s390x.ASTMG, 20768 reg: regInfo{ 20769 inputs: []inputInfo{ 20770 {1, 2}, // R1 20771 {2, 4}, // R2 20772 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20773 }, 20774 }, 20775 }, 20776 { 20777 name: "STMG3", 20778 auxType: auxSymOff, 20779 argLen: 5, 20780 faultOnNilArg0: true, 20781 symEffect: SymWrite, 20782 asm: s390x.ASTMG, 20783 reg: regInfo{ 20784 inputs: []inputInfo{ 20785 {1, 2}, // R1 20786 {2, 4}, // R2 20787 {3, 8}, // R3 20788 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20789 }, 20790 }, 20791 }, 20792 { 20793 name: "STMG4", 20794 auxType: auxSymOff, 20795 argLen: 6, 20796 faultOnNilArg0: true, 20797 symEffect: SymWrite, 20798 asm: s390x.ASTMG, 20799 reg: regInfo{ 20800 inputs: []inputInfo{ 20801 {1, 2}, // R1 20802 {2, 4}, // R2 20803 {3, 8}, // R3 20804 {4, 16}, // R4 20805 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20806 }, 20807 }, 20808 }, 20809 { 20810 name: "STM2", 20811 auxType: auxSymOff, 20812 argLen: 4, 20813 faultOnNilArg0: true, 20814 symEffect: SymWrite, 20815 asm: s390x.ASTMY, 20816 reg: regInfo{ 20817 inputs: []inputInfo{ 20818 {1, 2}, // R1 20819 {2, 4}, // R2 20820 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20821 }, 20822 }, 20823 }, 20824 { 20825 name: "STM3", 20826 auxType: auxSymOff, 20827 argLen: 5, 20828 faultOnNilArg0: true, 20829 symEffect: SymWrite, 20830 asm: s390x.ASTMY, 20831 reg: regInfo{ 20832 inputs: []inputInfo{ 20833 {1, 2}, // R1 20834 {2, 4}, // R2 20835 {3, 8}, // R3 20836 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20837 }, 20838 }, 20839 }, 20840 { 20841 name: "STM4", 20842 auxType: auxSymOff, 20843 argLen: 6, 20844 faultOnNilArg0: true, 20845 symEffect: SymWrite, 20846 asm: s390x.ASTMY, 20847 reg: regInfo{ 20848 inputs: []inputInfo{ 20849 {1, 2}, // R1 20850 {2, 4}, // R2 20851 {3, 8}, // R3 20852 {4, 16}, // R4 20853 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20854 }, 20855 }, 20856 }, 20857 { 20858 name: "LoweredMove", 20859 auxType: auxInt64, 20860 argLen: 4, 20861 clobberFlags: true, 20862 faultOnNilArg0: true, 20863 faultOnNilArg1: true, 20864 reg: regInfo{ 20865 inputs: []inputInfo{ 20866 {0, 2}, // R1 20867 {1, 4}, // R2 20868 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20869 }, 20870 clobbers: 6, // R1 R2 20871 }, 20872 }, 20873 { 20874 name: "LoweredZero", 20875 auxType: auxInt64, 20876 argLen: 3, 20877 clobberFlags: true, 20878 faultOnNilArg0: true, 20879 reg: regInfo{ 20880 inputs: []inputInfo{ 20881 {0, 2}, // R1 20882 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20883 }, 20884 clobbers: 2, // R1 20885 }, 20886 }, 20887 20888 { 20889 name: "Add8", 20890 argLen: 2, 20891 commutative: true, 20892 generic: true, 20893 }, 20894 { 20895 name: "Add16", 20896 argLen: 2, 20897 commutative: true, 20898 generic: true, 20899 }, 20900 { 20901 name: "Add32", 20902 argLen: 2, 20903 commutative: true, 20904 generic: true, 20905 }, 20906 { 20907 name: "Add64", 20908 argLen: 2, 20909 commutative: true, 20910 generic: true, 20911 }, 20912 { 20913 name: "AddPtr", 20914 argLen: 2, 20915 generic: true, 20916 }, 20917 { 20918 name: "Add32F", 20919 argLen: 2, 20920 commutative: true, 20921 generic: true, 20922 }, 20923 { 20924 name: "Add64F", 20925 argLen: 2, 20926 commutative: true, 20927 generic: true, 20928 }, 20929 { 20930 name: "Sub8", 20931 argLen: 2, 20932 generic: true, 20933 }, 20934 { 20935 name: "Sub16", 20936 argLen: 2, 20937 generic: true, 20938 }, 20939 { 20940 name: "Sub32", 20941 argLen: 2, 20942 generic: true, 20943 }, 20944 { 20945 name: "Sub64", 20946 argLen: 2, 20947 generic: true, 20948 }, 20949 { 20950 name: "SubPtr", 20951 argLen: 2, 20952 generic: true, 20953 }, 20954 { 20955 name: "Sub32F", 20956 argLen: 2, 20957 generic: true, 20958 }, 20959 { 20960 name: "Sub64F", 20961 argLen: 2, 20962 generic: true, 20963 }, 20964 { 20965 name: "Mul8", 20966 argLen: 2, 20967 commutative: true, 20968 generic: true, 20969 }, 20970 { 20971 name: "Mul16", 20972 argLen: 2, 20973 commutative: true, 20974 generic: true, 20975 }, 20976 { 20977 name: "Mul32", 20978 argLen: 2, 20979 commutative: true, 20980 generic: true, 20981 }, 20982 { 20983 name: "Mul64", 20984 argLen: 2, 20985 commutative: true, 20986 generic: true, 20987 }, 20988 { 20989 name: "Mul32F", 20990 argLen: 2, 20991 commutative: true, 20992 generic: true, 20993 }, 20994 { 20995 name: "Mul64F", 20996 argLen: 2, 20997 commutative: true, 20998 generic: true, 20999 }, 21000 { 21001 name: "Div32F", 21002 argLen: 2, 21003 generic: true, 21004 }, 21005 { 21006 name: "Div64F", 21007 argLen: 2, 21008 generic: true, 21009 }, 21010 { 21011 name: "Hmul32", 21012 argLen: 2, 21013 commutative: true, 21014 generic: true, 21015 }, 21016 { 21017 name: "Hmul32u", 21018 argLen: 2, 21019 commutative: true, 21020 generic: true, 21021 }, 21022 { 21023 name: "Hmul64", 21024 argLen: 2, 21025 commutative: true, 21026 generic: true, 21027 }, 21028 { 21029 name: "Hmul64u", 21030 argLen: 2, 21031 commutative: true, 21032 generic: true, 21033 }, 21034 { 21035 name: "Mul32uhilo", 21036 argLen: 2, 21037 commutative: true, 21038 generic: true, 21039 }, 21040 { 21041 name: "Mul64uhilo", 21042 argLen: 2, 21043 commutative: true, 21044 generic: true, 21045 }, 21046 { 21047 name: "Avg32u", 21048 argLen: 2, 21049 generic: true, 21050 }, 21051 { 21052 name: "Avg64u", 21053 argLen: 2, 21054 generic: true, 21055 }, 21056 { 21057 name: "Div8", 21058 argLen: 2, 21059 generic: true, 21060 }, 21061 { 21062 name: "Div8u", 21063 argLen: 2, 21064 generic: true, 21065 }, 21066 { 21067 name: "Div16", 21068 argLen: 2, 21069 generic: true, 21070 }, 21071 { 21072 name: "Div16u", 21073 argLen: 2, 21074 generic: true, 21075 }, 21076 { 21077 name: "Div32", 21078 argLen: 2, 21079 generic: true, 21080 }, 21081 { 21082 name: "Div32u", 21083 argLen: 2, 21084 generic: true, 21085 }, 21086 { 21087 name: "Div64", 21088 argLen: 2, 21089 generic: true, 21090 }, 21091 { 21092 name: "Div64u", 21093 argLen: 2, 21094 generic: true, 21095 }, 21096 { 21097 name: "Div128u", 21098 argLen: 3, 21099 generic: true, 21100 }, 21101 { 21102 name: "Mod8", 21103 argLen: 2, 21104 generic: true, 21105 }, 21106 { 21107 name: "Mod8u", 21108 argLen: 2, 21109 generic: true, 21110 }, 21111 { 21112 name: "Mod16", 21113 argLen: 2, 21114 generic: true, 21115 }, 21116 { 21117 name: "Mod16u", 21118 argLen: 2, 21119 generic: true, 21120 }, 21121 { 21122 name: "Mod32", 21123 argLen: 2, 21124 generic: true, 21125 }, 21126 { 21127 name: "Mod32u", 21128 argLen: 2, 21129 generic: true, 21130 }, 21131 { 21132 name: "Mod64", 21133 argLen: 2, 21134 generic: true, 21135 }, 21136 { 21137 name: "Mod64u", 21138 argLen: 2, 21139 generic: true, 21140 }, 21141 { 21142 name: "And8", 21143 argLen: 2, 21144 commutative: true, 21145 generic: true, 21146 }, 21147 { 21148 name: "And16", 21149 argLen: 2, 21150 commutative: true, 21151 generic: true, 21152 }, 21153 { 21154 name: "And32", 21155 argLen: 2, 21156 commutative: true, 21157 generic: true, 21158 }, 21159 { 21160 name: "And64", 21161 argLen: 2, 21162 commutative: true, 21163 generic: true, 21164 }, 21165 { 21166 name: "Or8", 21167 argLen: 2, 21168 commutative: true, 21169 generic: true, 21170 }, 21171 { 21172 name: "Or16", 21173 argLen: 2, 21174 commutative: true, 21175 generic: true, 21176 }, 21177 { 21178 name: "Or32", 21179 argLen: 2, 21180 commutative: true, 21181 generic: true, 21182 }, 21183 { 21184 name: "Or64", 21185 argLen: 2, 21186 commutative: true, 21187 generic: true, 21188 }, 21189 { 21190 name: "Xor8", 21191 argLen: 2, 21192 commutative: true, 21193 generic: true, 21194 }, 21195 { 21196 name: "Xor16", 21197 argLen: 2, 21198 commutative: true, 21199 generic: true, 21200 }, 21201 { 21202 name: "Xor32", 21203 argLen: 2, 21204 commutative: true, 21205 generic: true, 21206 }, 21207 { 21208 name: "Xor64", 21209 argLen: 2, 21210 commutative: true, 21211 generic: true, 21212 }, 21213 { 21214 name: "Lsh8x8", 21215 argLen: 2, 21216 generic: true, 21217 }, 21218 { 21219 name: "Lsh8x16", 21220 argLen: 2, 21221 generic: true, 21222 }, 21223 { 21224 name: "Lsh8x32", 21225 argLen: 2, 21226 generic: true, 21227 }, 21228 { 21229 name: "Lsh8x64", 21230 argLen: 2, 21231 generic: true, 21232 }, 21233 { 21234 name: "Lsh16x8", 21235 argLen: 2, 21236 generic: true, 21237 }, 21238 { 21239 name: "Lsh16x16", 21240 argLen: 2, 21241 generic: true, 21242 }, 21243 { 21244 name: "Lsh16x32", 21245 argLen: 2, 21246 generic: true, 21247 }, 21248 { 21249 name: "Lsh16x64", 21250 argLen: 2, 21251 generic: true, 21252 }, 21253 { 21254 name: "Lsh32x8", 21255 argLen: 2, 21256 generic: true, 21257 }, 21258 { 21259 name: "Lsh32x16", 21260 argLen: 2, 21261 generic: true, 21262 }, 21263 { 21264 name: "Lsh32x32", 21265 argLen: 2, 21266 generic: true, 21267 }, 21268 { 21269 name: "Lsh32x64", 21270 argLen: 2, 21271 generic: true, 21272 }, 21273 { 21274 name: "Lsh64x8", 21275 argLen: 2, 21276 generic: true, 21277 }, 21278 { 21279 name: "Lsh64x16", 21280 argLen: 2, 21281 generic: true, 21282 }, 21283 { 21284 name: "Lsh64x32", 21285 argLen: 2, 21286 generic: true, 21287 }, 21288 { 21289 name: "Lsh64x64", 21290 argLen: 2, 21291 generic: true, 21292 }, 21293 { 21294 name: "Rsh8x8", 21295 argLen: 2, 21296 generic: true, 21297 }, 21298 { 21299 name: "Rsh8x16", 21300 argLen: 2, 21301 generic: true, 21302 }, 21303 { 21304 name: "Rsh8x32", 21305 argLen: 2, 21306 generic: true, 21307 }, 21308 { 21309 name: "Rsh8x64", 21310 argLen: 2, 21311 generic: true, 21312 }, 21313 { 21314 name: "Rsh16x8", 21315 argLen: 2, 21316 generic: true, 21317 }, 21318 { 21319 name: "Rsh16x16", 21320 argLen: 2, 21321 generic: true, 21322 }, 21323 { 21324 name: "Rsh16x32", 21325 argLen: 2, 21326 generic: true, 21327 }, 21328 { 21329 name: "Rsh16x64", 21330 argLen: 2, 21331 generic: true, 21332 }, 21333 { 21334 name: "Rsh32x8", 21335 argLen: 2, 21336 generic: true, 21337 }, 21338 { 21339 name: "Rsh32x16", 21340 argLen: 2, 21341 generic: true, 21342 }, 21343 { 21344 name: "Rsh32x32", 21345 argLen: 2, 21346 generic: true, 21347 }, 21348 { 21349 name: "Rsh32x64", 21350 argLen: 2, 21351 generic: true, 21352 }, 21353 { 21354 name: "Rsh64x8", 21355 argLen: 2, 21356 generic: true, 21357 }, 21358 { 21359 name: "Rsh64x16", 21360 argLen: 2, 21361 generic: true, 21362 }, 21363 { 21364 name: "Rsh64x32", 21365 argLen: 2, 21366 generic: true, 21367 }, 21368 { 21369 name: "Rsh64x64", 21370 argLen: 2, 21371 generic: true, 21372 }, 21373 { 21374 name: "Rsh8Ux8", 21375 argLen: 2, 21376 generic: true, 21377 }, 21378 { 21379 name: "Rsh8Ux16", 21380 argLen: 2, 21381 generic: true, 21382 }, 21383 { 21384 name: "Rsh8Ux32", 21385 argLen: 2, 21386 generic: true, 21387 }, 21388 { 21389 name: "Rsh8Ux64", 21390 argLen: 2, 21391 generic: true, 21392 }, 21393 { 21394 name: "Rsh16Ux8", 21395 argLen: 2, 21396 generic: true, 21397 }, 21398 { 21399 name: "Rsh16Ux16", 21400 argLen: 2, 21401 generic: true, 21402 }, 21403 { 21404 name: "Rsh16Ux32", 21405 argLen: 2, 21406 generic: true, 21407 }, 21408 { 21409 name: "Rsh16Ux64", 21410 argLen: 2, 21411 generic: true, 21412 }, 21413 { 21414 name: "Rsh32Ux8", 21415 argLen: 2, 21416 generic: true, 21417 }, 21418 { 21419 name: "Rsh32Ux16", 21420 argLen: 2, 21421 generic: true, 21422 }, 21423 { 21424 name: "Rsh32Ux32", 21425 argLen: 2, 21426 generic: true, 21427 }, 21428 { 21429 name: "Rsh32Ux64", 21430 argLen: 2, 21431 generic: true, 21432 }, 21433 { 21434 name: "Rsh64Ux8", 21435 argLen: 2, 21436 generic: true, 21437 }, 21438 { 21439 name: "Rsh64Ux16", 21440 argLen: 2, 21441 generic: true, 21442 }, 21443 { 21444 name: "Rsh64Ux32", 21445 argLen: 2, 21446 generic: true, 21447 }, 21448 { 21449 name: "Rsh64Ux64", 21450 argLen: 2, 21451 generic: true, 21452 }, 21453 { 21454 name: "Eq8", 21455 argLen: 2, 21456 commutative: true, 21457 generic: true, 21458 }, 21459 { 21460 name: "Eq16", 21461 argLen: 2, 21462 commutative: true, 21463 generic: true, 21464 }, 21465 { 21466 name: "Eq32", 21467 argLen: 2, 21468 commutative: true, 21469 generic: true, 21470 }, 21471 { 21472 name: "Eq64", 21473 argLen: 2, 21474 commutative: true, 21475 generic: true, 21476 }, 21477 { 21478 name: "EqPtr", 21479 argLen: 2, 21480 commutative: true, 21481 generic: true, 21482 }, 21483 { 21484 name: "EqInter", 21485 argLen: 2, 21486 generic: true, 21487 }, 21488 { 21489 name: "EqSlice", 21490 argLen: 2, 21491 generic: true, 21492 }, 21493 { 21494 name: "Eq32F", 21495 argLen: 2, 21496 commutative: true, 21497 generic: true, 21498 }, 21499 { 21500 name: "Eq64F", 21501 argLen: 2, 21502 commutative: true, 21503 generic: true, 21504 }, 21505 { 21506 name: "Neq8", 21507 argLen: 2, 21508 commutative: true, 21509 generic: true, 21510 }, 21511 { 21512 name: "Neq16", 21513 argLen: 2, 21514 commutative: true, 21515 generic: true, 21516 }, 21517 { 21518 name: "Neq32", 21519 argLen: 2, 21520 commutative: true, 21521 generic: true, 21522 }, 21523 { 21524 name: "Neq64", 21525 argLen: 2, 21526 commutative: true, 21527 generic: true, 21528 }, 21529 { 21530 name: "NeqPtr", 21531 argLen: 2, 21532 commutative: true, 21533 generic: true, 21534 }, 21535 { 21536 name: "NeqInter", 21537 argLen: 2, 21538 generic: true, 21539 }, 21540 { 21541 name: "NeqSlice", 21542 argLen: 2, 21543 generic: true, 21544 }, 21545 { 21546 name: "Neq32F", 21547 argLen: 2, 21548 commutative: true, 21549 generic: true, 21550 }, 21551 { 21552 name: "Neq64F", 21553 argLen: 2, 21554 commutative: true, 21555 generic: true, 21556 }, 21557 { 21558 name: "Less8", 21559 argLen: 2, 21560 generic: true, 21561 }, 21562 { 21563 name: "Less8U", 21564 argLen: 2, 21565 generic: true, 21566 }, 21567 { 21568 name: "Less16", 21569 argLen: 2, 21570 generic: true, 21571 }, 21572 { 21573 name: "Less16U", 21574 argLen: 2, 21575 generic: true, 21576 }, 21577 { 21578 name: "Less32", 21579 argLen: 2, 21580 generic: true, 21581 }, 21582 { 21583 name: "Less32U", 21584 argLen: 2, 21585 generic: true, 21586 }, 21587 { 21588 name: "Less64", 21589 argLen: 2, 21590 generic: true, 21591 }, 21592 { 21593 name: "Less64U", 21594 argLen: 2, 21595 generic: true, 21596 }, 21597 { 21598 name: "Less32F", 21599 argLen: 2, 21600 generic: true, 21601 }, 21602 { 21603 name: "Less64F", 21604 argLen: 2, 21605 generic: true, 21606 }, 21607 { 21608 name: "Leq8", 21609 argLen: 2, 21610 generic: true, 21611 }, 21612 { 21613 name: "Leq8U", 21614 argLen: 2, 21615 generic: true, 21616 }, 21617 { 21618 name: "Leq16", 21619 argLen: 2, 21620 generic: true, 21621 }, 21622 { 21623 name: "Leq16U", 21624 argLen: 2, 21625 generic: true, 21626 }, 21627 { 21628 name: "Leq32", 21629 argLen: 2, 21630 generic: true, 21631 }, 21632 { 21633 name: "Leq32U", 21634 argLen: 2, 21635 generic: true, 21636 }, 21637 { 21638 name: "Leq64", 21639 argLen: 2, 21640 generic: true, 21641 }, 21642 { 21643 name: "Leq64U", 21644 argLen: 2, 21645 generic: true, 21646 }, 21647 { 21648 name: "Leq32F", 21649 argLen: 2, 21650 generic: true, 21651 }, 21652 { 21653 name: "Leq64F", 21654 argLen: 2, 21655 generic: true, 21656 }, 21657 { 21658 name: "Greater8", 21659 argLen: 2, 21660 generic: true, 21661 }, 21662 { 21663 name: "Greater8U", 21664 argLen: 2, 21665 generic: true, 21666 }, 21667 { 21668 name: "Greater16", 21669 argLen: 2, 21670 generic: true, 21671 }, 21672 { 21673 name: "Greater16U", 21674 argLen: 2, 21675 generic: true, 21676 }, 21677 { 21678 name: "Greater32", 21679 argLen: 2, 21680 generic: true, 21681 }, 21682 { 21683 name: "Greater32U", 21684 argLen: 2, 21685 generic: true, 21686 }, 21687 { 21688 name: "Greater64", 21689 argLen: 2, 21690 generic: true, 21691 }, 21692 { 21693 name: "Greater64U", 21694 argLen: 2, 21695 generic: true, 21696 }, 21697 { 21698 name: "Greater32F", 21699 argLen: 2, 21700 generic: true, 21701 }, 21702 { 21703 name: "Greater64F", 21704 argLen: 2, 21705 generic: true, 21706 }, 21707 { 21708 name: "Geq8", 21709 argLen: 2, 21710 generic: true, 21711 }, 21712 { 21713 name: "Geq8U", 21714 argLen: 2, 21715 generic: true, 21716 }, 21717 { 21718 name: "Geq16", 21719 argLen: 2, 21720 generic: true, 21721 }, 21722 { 21723 name: "Geq16U", 21724 argLen: 2, 21725 generic: true, 21726 }, 21727 { 21728 name: "Geq32", 21729 argLen: 2, 21730 generic: true, 21731 }, 21732 { 21733 name: "Geq32U", 21734 argLen: 2, 21735 generic: true, 21736 }, 21737 { 21738 name: "Geq64", 21739 argLen: 2, 21740 generic: true, 21741 }, 21742 { 21743 name: "Geq64U", 21744 argLen: 2, 21745 generic: true, 21746 }, 21747 { 21748 name: "Geq32F", 21749 argLen: 2, 21750 generic: true, 21751 }, 21752 { 21753 name: "Geq64F", 21754 argLen: 2, 21755 generic: true, 21756 }, 21757 { 21758 name: "AndB", 21759 argLen: 2, 21760 generic: true, 21761 }, 21762 { 21763 name: "OrB", 21764 argLen: 2, 21765 generic: true, 21766 }, 21767 { 21768 name: "EqB", 21769 argLen: 2, 21770 generic: true, 21771 }, 21772 { 21773 name: "NeqB", 21774 argLen: 2, 21775 generic: true, 21776 }, 21777 { 21778 name: "Not", 21779 argLen: 1, 21780 generic: true, 21781 }, 21782 { 21783 name: "Neg8", 21784 argLen: 1, 21785 generic: true, 21786 }, 21787 { 21788 name: "Neg16", 21789 argLen: 1, 21790 generic: true, 21791 }, 21792 { 21793 name: "Neg32", 21794 argLen: 1, 21795 generic: true, 21796 }, 21797 { 21798 name: "Neg64", 21799 argLen: 1, 21800 generic: true, 21801 }, 21802 { 21803 name: "Neg32F", 21804 argLen: 1, 21805 generic: true, 21806 }, 21807 { 21808 name: "Neg64F", 21809 argLen: 1, 21810 generic: true, 21811 }, 21812 { 21813 name: "Com8", 21814 argLen: 1, 21815 generic: true, 21816 }, 21817 { 21818 name: "Com16", 21819 argLen: 1, 21820 generic: true, 21821 }, 21822 { 21823 name: "Com32", 21824 argLen: 1, 21825 generic: true, 21826 }, 21827 { 21828 name: "Com64", 21829 argLen: 1, 21830 generic: true, 21831 }, 21832 { 21833 name: "Ctz32", 21834 argLen: 1, 21835 generic: true, 21836 }, 21837 { 21838 name: "Ctz64", 21839 argLen: 1, 21840 generic: true, 21841 }, 21842 { 21843 name: "BitLen32", 21844 argLen: 1, 21845 generic: true, 21846 }, 21847 { 21848 name: "BitLen64", 21849 argLen: 1, 21850 generic: true, 21851 }, 21852 { 21853 name: "Bswap32", 21854 argLen: 1, 21855 generic: true, 21856 }, 21857 { 21858 name: "Bswap64", 21859 argLen: 1, 21860 generic: true, 21861 }, 21862 { 21863 name: "BitRev8", 21864 argLen: 1, 21865 generic: true, 21866 }, 21867 { 21868 name: "BitRev16", 21869 argLen: 1, 21870 generic: true, 21871 }, 21872 { 21873 name: "BitRev32", 21874 argLen: 1, 21875 generic: true, 21876 }, 21877 { 21878 name: "BitRev64", 21879 argLen: 1, 21880 generic: true, 21881 }, 21882 { 21883 name: "PopCount8", 21884 argLen: 1, 21885 generic: true, 21886 }, 21887 { 21888 name: "PopCount16", 21889 argLen: 1, 21890 generic: true, 21891 }, 21892 { 21893 name: "PopCount32", 21894 argLen: 1, 21895 generic: true, 21896 }, 21897 { 21898 name: "PopCount64", 21899 argLen: 1, 21900 generic: true, 21901 }, 21902 { 21903 name: "Sqrt", 21904 argLen: 1, 21905 generic: true, 21906 }, 21907 { 21908 name: "Phi", 21909 argLen: -1, 21910 generic: true, 21911 }, 21912 { 21913 name: "Copy", 21914 argLen: 1, 21915 generic: true, 21916 }, 21917 { 21918 name: "Convert", 21919 argLen: 2, 21920 generic: true, 21921 }, 21922 { 21923 name: "ConstBool", 21924 auxType: auxBool, 21925 argLen: 0, 21926 generic: true, 21927 }, 21928 { 21929 name: "ConstString", 21930 auxType: auxString, 21931 argLen: 0, 21932 generic: true, 21933 }, 21934 { 21935 name: "ConstNil", 21936 argLen: 0, 21937 generic: true, 21938 }, 21939 { 21940 name: "Const8", 21941 auxType: auxInt8, 21942 argLen: 0, 21943 generic: true, 21944 }, 21945 { 21946 name: "Const16", 21947 auxType: auxInt16, 21948 argLen: 0, 21949 generic: true, 21950 }, 21951 { 21952 name: "Const32", 21953 auxType: auxInt32, 21954 argLen: 0, 21955 generic: true, 21956 }, 21957 { 21958 name: "Const64", 21959 auxType: auxInt64, 21960 argLen: 0, 21961 generic: true, 21962 }, 21963 { 21964 name: "Const32F", 21965 auxType: auxFloat32, 21966 argLen: 0, 21967 generic: true, 21968 }, 21969 { 21970 name: "Const64F", 21971 auxType: auxFloat64, 21972 argLen: 0, 21973 generic: true, 21974 }, 21975 { 21976 name: "ConstInterface", 21977 argLen: 0, 21978 generic: true, 21979 }, 21980 { 21981 name: "ConstSlice", 21982 argLen: 0, 21983 generic: true, 21984 }, 21985 { 21986 name: "InitMem", 21987 argLen: 0, 21988 generic: true, 21989 }, 21990 { 21991 name: "Arg", 21992 auxType: auxSymOff, 21993 argLen: 0, 21994 symEffect: SymNone, 21995 generic: true, 21996 }, 21997 { 21998 name: "Addr", 21999 auxType: auxSym, 22000 argLen: 1, 22001 symEffect: SymAddr, 22002 generic: true, 22003 }, 22004 { 22005 name: "SP", 22006 argLen: 0, 22007 generic: true, 22008 }, 22009 { 22010 name: "SB", 22011 argLen: 0, 22012 generic: true, 22013 }, 22014 { 22015 name: "Load", 22016 argLen: 2, 22017 generic: true, 22018 }, 22019 { 22020 name: "Store", 22021 auxType: auxTyp, 22022 argLen: 3, 22023 generic: true, 22024 }, 22025 { 22026 name: "Move", 22027 auxType: auxTypSize, 22028 argLen: 3, 22029 generic: true, 22030 }, 22031 { 22032 name: "Zero", 22033 auxType: auxTypSize, 22034 argLen: 2, 22035 generic: true, 22036 }, 22037 { 22038 name: "StoreWB", 22039 auxType: auxTyp, 22040 argLen: 3, 22041 generic: true, 22042 }, 22043 { 22044 name: "MoveWB", 22045 auxType: auxTypSize, 22046 argLen: 3, 22047 generic: true, 22048 }, 22049 { 22050 name: "ZeroWB", 22051 auxType: auxTypSize, 22052 argLen: 2, 22053 generic: true, 22054 }, 22055 { 22056 name: "ClosureCall", 22057 auxType: auxInt64, 22058 argLen: 3, 22059 call: true, 22060 generic: true, 22061 }, 22062 { 22063 name: "StaticCall", 22064 auxType: auxSymOff, 22065 argLen: 1, 22066 call: true, 22067 symEffect: SymNone, 22068 generic: true, 22069 }, 22070 { 22071 name: "InterCall", 22072 auxType: auxInt64, 22073 argLen: 2, 22074 call: true, 22075 generic: true, 22076 }, 22077 { 22078 name: "SignExt8to16", 22079 argLen: 1, 22080 generic: true, 22081 }, 22082 { 22083 name: "SignExt8to32", 22084 argLen: 1, 22085 generic: true, 22086 }, 22087 { 22088 name: "SignExt8to64", 22089 argLen: 1, 22090 generic: true, 22091 }, 22092 { 22093 name: "SignExt16to32", 22094 argLen: 1, 22095 generic: true, 22096 }, 22097 { 22098 name: "SignExt16to64", 22099 argLen: 1, 22100 generic: true, 22101 }, 22102 { 22103 name: "SignExt32to64", 22104 argLen: 1, 22105 generic: true, 22106 }, 22107 { 22108 name: "ZeroExt8to16", 22109 argLen: 1, 22110 generic: true, 22111 }, 22112 { 22113 name: "ZeroExt8to32", 22114 argLen: 1, 22115 generic: true, 22116 }, 22117 { 22118 name: "ZeroExt8to64", 22119 argLen: 1, 22120 generic: true, 22121 }, 22122 { 22123 name: "ZeroExt16to32", 22124 argLen: 1, 22125 generic: true, 22126 }, 22127 { 22128 name: "ZeroExt16to64", 22129 argLen: 1, 22130 generic: true, 22131 }, 22132 { 22133 name: "ZeroExt32to64", 22134 argLen: 1, 22135 generic: true, 22136 }, 22137 { 22138 name: "Trunc16to8", 22139 argLen: 1, 22140 generic: true, 22141 }, 22142 { 22143 name: "Trunc32to8", 22144 argLen: 1, 22145 generic: true, 22146 }, 22147 { 22148 name: "Trunc32to16", 22149 argLen: 1, 22150 generic: true, 22151 }, 22152 { 22153 name: "Trunc64to8", 22154 argLen: 1, 22155 generic: true, 22156 }, 22157 { 22158 name: "Trunc64to16", 22159 argLen: 1, 22160 generic: true, 22161 }, 22162 { 22163 name: "Trunc64to32", 22164 argLen: 1, 22165 generic: true, 22166 }, 22167 { 22168 name: "Cvt32to32F", 22169 argLen: 1, 22170 generic: true, 22171 }, 22172 { 22173 name: "Cvt32to64F", 22174 argLen: 1, 22175 generic: true, 22176 }, 22177 { 22178 name: "Cvt64to32F", 22179 argLen: 1, 22180 generic: true, 22181 }, 22182 { 22183 name: "Cvt64to64F", 22184 argLen: 1, 22185 generic: true, 22186 }, 22187 { 22188 name: "Cvt32Fto32", 22189 argLen: 1, 22190 generic: true, 22191 }, 22192 { 22193 name: "Cvt32Fto64", 22194 argLen: 1, 22195 generic: true, 22196 }, 22197 { 22198 name: "Cvt64Fto32", 22199 argLen: 1, 22200 generic: true, 22201 }, 22202 { 22203 name: "Cvt64Fto64", 22204 argLen: 1, 22205 generic: true, 22206 }, 22207 { 22208 name: "Cvt32Fto64F", 22209 argLen: 1, 22210 generic: true, 22211 }, 22212 { 22213 name: "Cvt64Fto32F", 22214 argLen: 1, 22215 generic: true, 22216 }, 22217 { 22218 name: "Round32F", 22219 argLen: 1, 22220 generic: true, 22221 }, 22222 { 22223 name: "Round64F", 22224 argLen: 1, 22225 generic: true, 22226 }, 22227 { 22228 name: "IsNonNil", 22229 argLen: 1, 22230 generic: true, 22231 }, 22232 { 22233 name: "IsInBounds", 22234 argLen: 2, 22235 generic: true, 22236 }, 22237 { 22238 name: "IsSliceInBounds", 22239 argLen: 2, 22240 generic: true, 22241 }, 22242 { 22243 name: "NilCheck", 22244 argLen: 2, 22245 generic: true, 22246 }, 22247 { 22248 name: "GetG", 22249 argLen: 1, 22250 generic: true, 22251 }, 22252 { 22253 name: "GetClosurePtr", 22254 argLen: 0, 22255 generic: true, 22256 }, 22257 { 22258 name: "PtrIndex", 22259 argLen: 2, 22260 generic: true, 22261 }, 22262 { 22263 name: "OffPtr", 22264 auxType: auxInt64, 22265 argLen: 1, 22266 generic: true, 22267 }, 22268 { 22269 name: "SliceMake", 22270 argLen: 3, 22271 generic: true, 22272 }, 22273 { 22274 name: "SlicePtr", 22275 argLen: 1, 22276 generic: true, 22277 }, 22278 { 22279 name: "SliceLen", 22280 argLen: 1, 22281 generic: true, 22282 }, 22283 { 22284 name: "SliceCap", 22285 argLen: 1, 22286 generic: true, 22287 }, 22288 { 22289 name: "ComplexMake", 22290 argLen: 2, 22291 generic: true, 22292 }, 22293 { 22294 name: "ComplexReal", 22295 argLen: 1, 22296 generic: true, 22297 }, 22298 { 22299 name: "ComplexImag", 22300 argLen: 1, 22301 generic: true, 22302 }, 22303 { 22304 name: "StringMake", 22305 argLen: 2, 22306 generic: true, 22307 }, 22308 { 22309 name: "StringPtr", 22310 argLen: 1, 22311 generic: true, 22312 }, 22313 { 22314 name: "StringLen", 22315 argLen: 1, 22316 generic: true, 22317 }, 22318 { 22319 name: "IMake", 22320 argLen: 2, 22321 generic: true, 22322 }, 22323 { 22324 name: "ITab", 22325 argLen: 1, 22326 generic: true, 22327 }, 22328 { 22329 name: "IData", 22330 argLen: 1, 22331 generic: true, 22332 }, 22333 { 22334 name: "StructMake0", 22335 argLen: 0, 22336 generic: true, 22337 }, 22338 { 22339 name: "StructMake1", 22340 argLen: 1, 22341 generic: true, 22342 }, 22343 { 22344 name: "StructMake2", 22345 argLen: 2, 22346 generic: true, 22347 }, 22348 { 22349 name: "StructMake3", 22350 argLen: 3, 22351 generic: true, 22352 }, 22353 { 22354 name: "StructMake4", 22355 argLen: 4, 22356 generic: true, 22357 }, 22358 { 22359 name: "StructSelect", 22360 auxType: auxInt64, 22361 argLen: 1, 22362 generic: true, 22363 }, 22364 { 22365 name: "ArrayMake0", 22366 argLen: 0, 22367 generic: true, 22368 }, 22369 { 22370 name: "ArrayMake1", 22371 argLen: 1, 22372 generic: true, 22373 }, 22374 { 22375 name: "ArraySelect", 22376 auxType: auxInt64, 22377 argLen: 1, 22378 generic: true, 22379 }, 22380 { 22381 name: "StoreReg", 22382 argLen: 1, 22383 generic: true, 22384 }, 22385 { 22386 name: "LoadReg", 22387 argLen: 1, 22388 generic: true, 22389 }, 22390 { 22391 name: "FwdRef", 22392 auxType: auxSym, 22393 argLen: 0, 22394 symEffect: SymNone, 22395 generic: true, 22396 }, 22397 { 22398 name: "Unknown", 22399 argLen: 0, 22400 generic: true, 22401 }, 22402 { 22403 name: "VarDef", 22404 auxType: auxSym, 22405 argLen: 1, 22406 symEffect: SymNone, 22407 generic: true, 22408 }, 22409 { 22410 name: "VarKill", 22411 auxType: auxSym, 22412 argLen: 1, 22413 symEffect: SymNone, 22414 generic: true, 22415 }, 22416 { 22417 name: "VarLive", 22418 auxType: auxSym, 22419 argLen: 1, 22420 symEffect: SymNone, 22421 generic: true, 22422 }, 22423 { 22424 name: "KeepAlive", 22425 argLen: 2, 22426 generic: true, 22427 }, 22428 { 22429 name: "Int64Make", 22430 argLen: 2, 22431 generic: true, 22432 }, 22433 { 22434 name: "Int64Hi", 22435 argLen: 1, 22436 generic: true, 22437 }, 22438 { 22439 name: "Int64Lo", 22440 argLen: 1, 22441 generic: true, 22442 }, 22443 { 22444 name: "Add32carry", 22445 argLen: 2, 22446 commutative: true, 22447 generic: true, 22448 }, 22449 { 22450 name: "Add32withcarry", 22451 argLen: 3, 22452 commutative: true, 22453 generic: true, 22454 }, 22455 { 22456 name: "Sub32carry", 22457 argLen: 2, 22458 generic: true, 22459 }, 22460 { 22461 name: "Sub32withcarry", 22462 argLen: 3, 22463 generic: true, 22464 }, 22465 { 22466 name: "Signmask", 22467 argLen: 1, 22468 generic: true, 22469 }, 22470 { 22471 name: "Zeromask", 22472 argLen: 1, 22473 generic: true, 22474 }, 22475 { 22476 name: "Slicemask", 22477 argLen: 1, 22478 generic: true, 22479 }, 22480 { 22481 name: "Cvt32Uto32F", 22482 argLen: 1, 22483 generic: true, 22484 }, 22485 { 22486 name: "Cvt32Uto64F", 22487 argLen: 1, 22488 generic: true, 22489 }, 22490 { 22491 name: "Cvt32Fto32U", 22492 argLen: 1, 22493 generic: true, 22494 }, 22495 { 22496 name: "Cvt64Fto32U", 22497 argLen: 1, 22498 generic: true, 22499 }, 22500 { 22501 name: "Cvt64Uto32F", 22502 argLen: 1, 22503 generic: true, 22504 }, 22505 { 22506 name: "Cvt64Uto64F", 22507 argLen: 1, 22508 generic: true, 22509 }, 22510 { 22511 name: "Cvt32Fto64U", 22512 argLen: 1, 22513 generic: true, 22514 }, 22515 { 22516 name: "Cvt64Fto64U", 22517 argLen: 1, 22518 generic: true, 22519 }, 22520 { 22521 name: "Select0", 22522 argLen: 1, 22523 generic: true, 22524 }, 22525 { 22526 name: "Select1", 22527 argLen: 1, 22528 generic: true, 22529 }, 22530 { 22531 name: "AtomicLoad32", 22532 argLen: 2, 22533 generic: true, 22534 }, 22535 { 22536 name: "AtomicLoad64", 22537 argLen: 2, 22538 generic: true, 22539 }, 22540 { 22541 name: "AtomicLoadPtr", 22542 argLen: 2, 22543 generic: true, 22544 }, 22545 { 22546 name: "AtomicStore32", 22547 argLen: 3, 22548 hasSideEffects: true, 22549 generic: true, 22550 }, 22551 { 22552 name: "AtomicStore64", 22553 argLen: 3, 22554 hasSideEffects: true, 22555 generic: true, 22556 }, 22557 { 22558 name: "AtomicStorePtrNoWB", 22559 argLen: 3, 22560 hasSideEffects: true, 22561 generic: true, 22562 }, 22563 { 22564 name: "AtomicExchange32", 22565 argLen: 3, 22566 hasSideEffects: true, 22567 generic: true, 22568 }, 22569 { 22570 name: "AtomicExchange64", 22571 argLen: 3, 22572 hasSideEffects: true, 22573 generic: true, 22574 }, 22575 { 22576 name: "AtomicAdd32", 22577 argLen: 3, 22578 hasSideEffects: true, 22579 generic: true, 22580 }, 22581 { 22582 name: "AtomicAdd64", 22583 argLen: 3, 22584 hasSideEffects: true, 22585 generic: true, 22586 }, 22587 { 22588 name: "AtomicCompareAndSwap32", 22589 argLen: 4, 22590 hasSideEffects: true, 22591 generic: true, 22592 }, 22593 { 22594 name: "AtomicCompareAndSwap64", 22595 argLen: 4, 22596 hasSideEffects: true, 22597 generic: true, 22598 }, 22599 { 22600 name: "AtomicAnd8", 22601 argLen: 3, 22602 hasSideEffects: true, 22603 generic: true, 22604 }, 22605 { 22606 name: "AtomicOr8", 22607 argLen: 3, 22608 hasSideEffects: true, 22609 generic: true, 22610 }, 22611 { 22612 name: "Clobber", 22613 auxType: auxSymOff, 22614 argLen: 0, 22615 symEffect: SymNone, 22616 generic: true, 22617 }, 22618 } 22619 22620 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 22621 func (o Op) String() string { return opcodeTable[o].name } 22622 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 22623 func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } 22624 func (o Op) IsCall() bool { return opcodeTable[o].call } 22625 22626 var registers386 = [...]Register{ 22627 {0, x86.REG_AX, "AX"}, 22628 {1, x86.REG_CX, "CX"}, 22629 {2, x86.REG_DX, "DX"}, 22630 {3, x86.REG_BX, "BX"}, 22631 {4, x86.REGSP, "SP"}, 22632 {5, x86.REG_BP, "BP"}, 22633 {6, x86.REG_SI, "SI"}, 22634 {7, x86.REG_DI, "DI"}, 22635 {8, x86.REG_X0, "X0"}, 22636 {9, x86.REG_X1, "X1"}, 22637 {10, x86.REG_X2, "X2"}, 22638 {11, x86.REG_X3, "X3"}, 22639 {12, x86.REG_X4, "X4"}, 22640 {13, x86.REG_X5, "X5"}, 22641 {14, x86.REG_X6, "X6"}, 22642 {15, x86.REG_X7, "X7"}, 22643 {16, 0, "SB"}, 22644 } 22645 var gpRegMask386 = regMask(239) 22646 var fpRegMask386 = regMask(65280) 22647 var specialRegMask386 = regMask(0) 22648 var framepointerReg386 = int8(5) 22649 var linkReg386 = int8(-1) 22650 var registersAMD64 = [...]Register{ 22651 {0, x86.REG_AX, "AX"}, 22652 {1, x86.REG_CX, "CX"}, 22653 {2, x86.REG_DX, "DX"}, 22654 {3, x86.REG_BX, "BX"}, 22655 {4, x86.REGSP, "SP"}, 22656 {5, x86.REG_BP, "BP"}, 22657 {6, x86.REG_SI, "SI"}, 22658 {7, x86.REG_DI, "DI"}, 22659 {8, x86.REG_R8, "R8"}, 22660 {9, x86.REG_R9, "R9"}, 22661 {10, x86.REG_R10, "R10"}, 22662 {11, x86.REG_R11, "R11"}, 22663 {12, x86.REG_R12, "R12"}, 22664 {13, x86.REG_R13, "R13"}, 22665 {14, x86.REG_R14, "R14"}, 22666 {15, x86.REG_R15, "R15"}, 22667 {16, x86.REG_X0, "X0"}, 22668 {17, x86.REG_X1, "X1"}, 22669 {18, x86.REG_X2, "X2"}, 22670 {19, x86.REG_X3, "X3"}, 22671 {20, x86.REG_X4, "X4"}, 22672 {21, x86.REG_X5, "X5"}, 22673 {22, x86.REG_X6, "X6"}, 22674 {23, x86.REG_X7, "X7"}, 22675 {24, x86.REG_X8, "X8"}, 22676 {25, x86.REG_X9, "X9"}, 22677 {26, x86.REG_X10, "X10"}, 22678 {27, x86.REG_X11, "X11"}, 22679 {28, x86.REG_X12, "X12"}, 22680 {29, x86.REG_X13, "X13"}, 22681 {30, x86.REG_X14, "X14"}, 22682 {31, x86.REG_X15, "X15"}, 22683 {32, 0, "SB"}, 22684 } 22685 var gpRegMaskAMD64 = regMask(65519) 22686 var fpRegMaskAMD64 = regMask(4294901760) 22687 var specialRegMaskAMD64 = regMask(0) 22688 var framepointerRegAMD64 = int8(5) 22689 var linkRegAMD64 = int8(-1) 22690 var registersARM = [...]Register{ 22691 {0, arm.REG_R0, "R0"}, 22692 {1, arm.REG_R1, "R1"}, 22693 {2, arm.REG_R2, "R2"}, 22694 {3, arm.REG_R3, "R3"}, 22695 {4, arm.REG_R4, "R4"}, 22696 {5, arm.REG_R5, "R5"}, 22697 {6, arm.REG_R6, "R6"}, 22698 {7, arm.REG_R7, "R7"}, 22699 {8, arm.REG_R8, "R8"}, 22700 {9, arm.REG_R9, "R9"}, 22701 {10, arm.REGG, "g"}, 22702 {11, arm.REG_R11, "R11"}, 22703 {12, arm.REG_R12, "R12"}, 22704 {13, arm.REGSP, "SP"}, 22705 {14, arm.REG_R14, "R14"}, 22706 {15, arm.REG_R15, "R15"}, 22707 {16, arm.REG_F0, "F0"}, 22708 {17, arm.REG_F1, "F1"}, 22709 {18, arm.REG_F2, "F2"}, 22710 {19, arm.REG_F3, "F3"}, 22711 {20, arm.REG_F4, "F4"}, 22712 {21, arm.REG_F5, "F5"}, 22713 {22, arm.REG_F6, "F6"}, 22714 {23, arm.REG_F7, "F7"}, 22715 {24, arm.REG_F8, "F8"}, 22716 {25, arm.REG_F9, "F9"}, 22717 {26, arm.REG_F10, "F10"}, 22718 {27, arm.REG_F11, "F11"}, 22719 {28, arm.REG_F12, "F12"}, 22720 {29, arm.REG_F13, "F13"}, 22721 {30, arm.REG_F14, "F14"}, 22722 {31, arm.REG_F15, "F15"}, 22723 {32, 0, "SB"}, 22724 } 22725 var gpRegMaskARM = regMask(21503) 22726 var fpRegMaskARM = regMask(4294901760) 22727 var specialRegMaskARM = regMask(0) 22728 var framepointerRegARM = int8(-1) 22729 var linkRegARM = int8(14) 22730 var registersARM64 = [...]Register{ 22731 {0, arm64.REG_R0, "R0"}, 22732 {1, arm64.REG_R1, "R1"}, 22733 {2, arm64.REG_R2, "R2"}, 22734 {3, arm64.REG_R3, "R3"}, 22735 {4, arm64.REG_R4, "R4"}, 22736 {5, arm64.REG_R5, "R5"}, 22737 {6, arm64.REG_R6, "R6"}, 22738 {7, arm64.REG_R7, "R7"}, 22739 {8, arm64.REG_R8, "R8"}, 22740 {9, arm64.REG_R9, "R9"}, 22741 {10, arm64.REG_R10, "R10"}, 22742 {11, arm64.REG_R11, "R11"}, 22743 {12, arm64.REG_R12, "R12"}, 22744 {13, arm64.REG_R13, "R13"}, 22745 {14, arm64.REG_R14, "R14"}, 22746 {15, arm64.REG_R15, "R15"}, 22747 {16, arm64.REG_R16, "R16"}, 22748 {17, arm64.REG_R17, "R17"}, 22749 {18, arm64.REG_R18, "R18"}, 22750 {19, arm64.REG_R19, "R19"}, 22751 {20, arm64.REG_R20, "R20"}, 22752 {21, arm64.REG_R21, "R21"}, 22753 {22, arm64.REG_R22, "R22"}, 22754 {23, arm64.REG_R23, "R23"}, 22755 {24, arm64.REG_R24, "R24"}, 22756 {25, arm64.REG_R25, "R25"}, 22757 {26, arm64.REG_R26, "R26"}, 22758 {27, arm64.REGG, "g"}, 22759 {28, arm64.REG_R29, "R29"}, 22760 {29, arm64.REG_R30, "R30"}, 22761 {30, arm64.REGSP, "SP"}, 22762 {31, arm64.REG_F0, "F0"}, 22763 {32, arm64.REG_F1, "F1"}, 22764 {33, arm64.REG_F2, "F2"}, 22765 {34, arm64.REG_F3, "F3"}, 22766 {35, arm64.REG_F4, "F4"}, 22767 {36, arm64.REG_F5, "F5"}, 22768 {37, arm64.REG_F6, "F6"}, 22769 {38, arm64.REG_F7, "F7"}, 22770 {39, arm64.REG_F8, "F8"}, 22771 {40, arm64.REG_F9, "F9"}, 22772 {41, arm64.REG_F10, "F10"}, 22773 {42, arm64.REG_F11, "F11"}, 22774 {43, arm64.REG_F12, "F12"}, 22775 {44, arm64.REG_F13, "F13"}, 22776 {45, arm64.REG_F14, "F14"}, 22777 {46, arm64.REG_F15, "F15"}, 22778 {47, arm64.REG_F16, "F16"}, 22779 {48, arm64.REG_F17, "F17"}, 22780 {49, arm64.REG_F18, "F18"}, 22781 {50, arm64.REG_F19, "F19"}, 22782 {51, arm64.REG_F20, "F20"}, 22783 {52, arm64.REG_F21, "F21"}, 22784 {53, arm64.REG_F22, "F22"}, 22785 {54, arm64.REG_F23, "F23"}, 22786 {55, arm64.REG_F24, "F24"}, 22787 {56, arm64.REG_F25, "F25"}, 22788 {57, arm64.REG_F26, "F26"}, 22789 {58, arm64.REG_F27, "F27"}, 22790 {59, arm64.REG_F28, "F28"}, 22791 {60, arm64.REG_F29, "F29"}, 22792 {61, arm64.REG_F30, "F30"}, 22793 {62, arm64.REG_F31, "F31"}, 22794 {63, 0, "SB"}, 22795 } 22796 var gpRegMaskARM64 = regMask(670826495) 22797 var fpRegMaskARM64 = regMask(9223372034707292160) 22798 var specialRegMaskARM64 = regMask(0) 22799 var framepointerRegARM64 = int8(-1) 22800 var linkRegARM64 = int8(29) 22801 var registersMIPS = [...]Register{ 22802 {0, mips.REG_R0, "R0"}, 22803 {1, mips.REG_R1, "R1"}, 22804 {2, mips.REG_R2, "R2"}, 22805 {3, mips.REG_R3, "R3"}, 22806 {4, mips.REG_R4, "R4"}, 22807 {5, mips.REG_R5, "R5"}, 22808 {6, mips.REG_R6, "R6"}, 22809 {7, mips.REG_R7, "R7"}, 22810 {8, mips.REG_R8, "R8"}, 22811 {9, mips.REG_R9, "R9"}, 22812 {10, mips.REG_R10, "R10"}, 22813 {11, mips.REG_R11, "R11"}, 22814 {12, mips.REG_R12, "R12"}, 22815 {13, mips.REG_R13, "R13"}, 22816 {14, mips.REG_R14, "R14"}, 22817 {15, mips.REG_R15, "R15"}, 22818 {16, mips.REG_R16, "R16"}, 22819 {17, mips.REG_R17, "R17"}, 22820 {18, mips.REG_R18, "R18"}, 22821 {19, mips.REG_R19, "R19"}, 22822 {20, mips.REG_R20, "R20"}, 22823 {21, mips.REG_R21, "R21"}, 22824 {22, mips.REG_R22, "R22"}, 22825 {23, mips.REG_R24, "R24"}, 22826 {24, mips.REG_R25, "R25"}, 22827 {25, mips.REG_R28, "R28"}, 22828 {26, mips.REGSP, "SP"}, 22829 {27, mips.REGG, "g"}, 22830 {28, mips.REG_R31, "R31"}, 22831 {29, mips.REG_F0, "F0"}, 22832 {30, mips.REG_F2, "F2"}, 22833 {31, mips.REG_F4, "F4"}, 22834 {32, mips.REG_F6, "F6"}, 22835 {33, mips.REG_F8, "F8"}, 22836 {34, mips.REG_F10, "F10"}, 22837 {35, mips.REG_F12, "F12"}, 22838 {36, mips.REG_F14, "F14"}, 22839 {37, mips.REG_F16, "F16"}, 22840 {38, mips.REG_F18, "F18"}, 22841 {39, mips.REG_F20, "F20"}, 22842 {40, mips.REG_F22, "F22"}, 22843 {41, mips.REG_F24, "F24"}, 22844 {42, mips.REG_F26, "F26"}, 22845 {43, mips.REG_F28, "F28"}, 22846 {44, mips.REG_F30, "F30"}, 22847 {45, mips.REG_HI, "HI"}, 22848 {46, mips.REG_LO, "LO"}, 22849 {47, 0, "SB"}, 22850 } 22851 var gpRegMaskMIPS = regMask(335544318) 22852 var fpRegMaskMIPS = regMask(35183835217920) 22853 var specialRegMaskMIPS = regMask(105553116266496) 22854 var framepointerRegMIPS = int8(-1) 22855 var linkRegMIPS = int8(28) 22856 var registersMIPS64 = [...]Register{ 22857 {0, mips.REG_R0, "R0"}, 22858 {1, mips.REG_R1, "R1"}, 22859 {2, mips.REG_R2, "R2"}, 22860 {3, mips.REG_R3, "R3"}, 22861 {4, mips.REG_R4, "R4"}, 22862 {5, mips.REG_R5, "R5"}, 22863 {6, mips.REG_R6, "R6"}, 22864 {7, mips.REG_R7, "R7"}, 22865 {8, mips.REG_R8, "R8"}, 22866 {9, mips.REG_R9, "R9"}, 22867 {10, mips.REG_R10, "R10"}, 22868 {11, mips.REG_R11, "R11"}, 22869 {12, mips.REG_R12, "R12"}, 22870 {13, mips.REG_R13, "R13"}, 22871 {14, mips.REG_R14, "R14"}, 22872 {15, mips.REG_R15, "R15"}, 22873 {16, mips.REG_R16, "R16"}, 22874 {17, mips.REG_R17, "R17"}, 22875 {18, mips.REG_R18, "R18"}, 22876 {19, mips.REG_R19, "R19"}, 22877 {20, mips.REG_R20, "R20"}, 22878 {21, mips.REG_R21, "R21"}, 22879 {22, mips.REG_R22, "R22"}, 22880 {23, mips.REG_R24, "R24"}, 22881 {24, mips.REG_R25, "R25"}, 22882 {25, mips.REGSP, "SP"}, 22883 {26, mips.REGG, "g"}, 22884 {27, mips.REG_R31, "R31"}, 22885 {28, mips.REG_F0, "F0"}, 22886 {29, mips.REG_F1, "F1"}, 22887 {30, mips.REG_F2, "F2"}, 22888 {31, mips.REG_F3, "F3"}, 22889 {32, mips.REG_F4, "F4"}, 22890 {33, mips.REG_F5, "F5"}, 22891 {34, mips.REG_F6, "F6"}, 22892 {35, mips.REG_F7, "F7"}, 22893 {36, mips.REG_F8, "F8"}, 22894 {37, mips.REG_F9, "F9"}, 22895 {38, mips.REG_F10, "F10"}, 22896 {39, mips.REG_F11, "F11"}, 22897 {40, mips.REG_F12, "F12"}, 22898 {41, mips.REG_F13, "F13"}, 22899 {42, mips.REG_F14, "F14"}, 22900 {43, mips.REG_F15, "F15"}, 22901 {44, mips.REG_F16, "F16"}, 22902 {45, mips.REG_F17, "F17"}, 22903 {46, mips.REG_F18, "F18"}, 22904 {47, mips.REG_F19, "F19"}, 22905 {48, mips.REG_F20, "F20"}, 22906 {49, mips.REG_F21, "F21"}, 22907 {50, mips.REG_F22, "F22"}, 22908 {51, mips.REG_F23, "F23"}, 22909 {52, mips.REG_F24, "F24"}, 22910 {53, mips.REG_F25, "F25"}, 22911 {54, mips.REG_F26, "F26"}, 22912 {55, mips.REG_F27, "F27"}, 22913 {56, mips.REG_F28, "F28"}, 22914 {57, mips.REG_F29, "F29"}, 22915 {58, mips.REG_F30, "F30"}, 22916 {59, mips.REG_F31, "F31"}, 22917 {60, mips.REG_HI, "HI"}, 22918 {61, mips.REG_LO, "LO"}, 22919 {62, 0, "SB"}, 22920 } 22921 var gpRegMaskMIPS64 = regMask(167772158) 22922 var fpRegMaskMIPS64 = regMask(1152921504338411520) 22923 var specialRegMaskMIPS64 = regMask(3458764513820540928) 22924 var framepointerRegMIPS64 = int8(-1) 22925 var linkRegMIPS64 = int8(27) 22926 var registersPPC64 = [...]Register{ 22927 {0, ppc64.REG_R0, "R0"}, 22928 {1, ppc64.REGSP, "SP"}, 22929 {2, 0, "SB"}, 22930 {3, ppc64.REG_R3, "R3"}, 22931 {4, ppc64.REG_R4, "R4"}, 22932 {5, ppc64.REG_R5, "R5"}, 22933 {6, ppc64.REG_R6, "R6"}, 22934 {7, ppc64.REG_R7, "R7"}, 22935 {8, ppc64.REG_R8, "R8"}, 22936 {9, ppc64.REG_R9, "R9"}, 22937 {10, ppc64.REG_R10, "R10"}, 22938 {11, ppc64.REG_R11, "R11"}, 22939 {12, ppc64.REG_R12, "R12"}, 22940 {13, ppc64.REG_R13, "R13"}, 22941 {14, ppc64.REG_R14, "R14"}, 22942 {15, ppc64.REG_R15, "R15"}, 22943 {16, ppc64.REG_R16, "R16"}, 22944 {17, ppc64.REG_R17, "R17"}, 22945 {18, ppc64.REG_R18, "R18"}, 22946 {19, ppc64.REG_R19, "R19"}, 22947 {20, ppc64.REG_R20, "R20"}, 22948 {21, ppc64.REG_R21, "R21"}, 22949 {22, ppc64.REG_R22, "R22"}, 22950 {23, ppc64.REG_R23, "R23"}, 22951 {24, ppc64.REG_R24, "R24"}, 22952 {25, ppc64.REG_R25, "R25"}, 22953 {26, ppc64.REG_R26, "R26"}, 22954 {27, ppc64.REG_R27, "R27"}, 22955 {28, ppc64.REG_R28, "R28"}, 22956 {29, ppc64.REG_R29, "R29"}, 22957 {30, ppc64.REGG, "g"}, 22958 {31, ppc64.REG_R31, "R31"}, 22959 {32, ppc64.REG_F0, "F0"}, 22960 {33, ppc64.REG_F1, "F1"}, 22961 {34, ppc64.REG_F2, "F2"}, 22962 {35, ppc64.REG_F3, "F3"}, 22963 {36, ppc64.REG_F4, "F4"}, 22964 {37, ppc64.REG_F5, "F5"}, 22965 {38, ppc64.REG_F6, "F6"}, 22966 {39, ppc64.REG_F7, "F7"}, 22967 {40, ppc64.REG_F8, "F8"}, 22968 {41, ppc64.REG_F9, "F9"}, 22969 {42, ppc64.REG_F10, "F10"}, 22970 {43, ppc64.REG_F11, "F11"}, 22971 {44, ppc64.REG_F12, "F12"}, 22972 {45, ppc64.REG_F13, "F13"}, 22973 {46, ppc64.REG_F14, "F14"}, 22974 {47, ppc64.REG_F15, "F15"}, 22975 {48, ppc64.REG_F16, "F16"}, 22976 {49, ppc64.REG_F17, "F17"}, 22977 {50, ppc64.REG_F18, "F18"}, 22978 {51, ppc64.REG_F19, "F19"}, 22979 {52, ppc64.REG_F20, "F20"}, 22980 {53, ppc64.REG_F21, "F21"}, 22981 {54, ppc64.REG_F22, "F22"}, 22982 {55, ppc64.REG_F23, "F23"}, 22983 {56, ppc64.REG_F24, "F24"}, 22984 {57, ppc64.REG_F25, "F25"}, 22985 {58, ppc64.REG_F26, "F26"}, 22986 {59, ppc64.REG_F27, "F27"}, 22987 {60, ppc64.REG_F28, "F28"}, 22988 {61, ppc64.REG_F29, "F29"}, 22989 {62, ppc64.REG_F30, "F30"}, 22990 {63, ppc64.REG_F31, "F31"}, 22991 } 22992 var gpRegMaskPPC64 = regMask(1073733624) 22993 var fpRegMaskPPC64 = regMask(576460743713488896) 22994 var specialRegMaskPPC64 = regMask(0) 22995 var framepointerRegPPC64 = int8(1) 22996 var linkRegPPC64 = int8(-1) 22997 var registersS390X = [...]Register{ 22998 {0, s390x.REG_R0, "R0"}, 22999 {1, s390x.REG_R1, "R1"}, 23000 {2, s390x.REG_R2, "R2"}, 23001 {3, s390x.REG_R3, "R3"}, 23002 {4, s390x.REG_R4, "R4"}, 23003 {5, s390x.REG_R5, "R5"}, 23004 {6, s390x.REG_R6, "R6"}, 23005 {7, s390x.REG_R7, "R7"}, 23006 {8, s390x.REG_R8, "R8"}, 23007 {9, s390x.REG_R9, "R9"}, 23008 {10, s390x.REG_R10, "R10"}, 23009 {11, s390x.REG_R11, "R11"}, 23010 {12, s390x.REG_R12, "R12"}, 23011 {13, s390x.REGG, "g"}, 23012 {14, s390x.REG_R14, "R14"}, 23013 {15, s390x.REGSP, "SP"}, 23014 {16, s390x.REG_F0, "F0"}, 23015 {17, s390x.REG_F1, "F1"}, 23016 {18, s390x.REG_F2, "F2"}, 23017 {19, s390x.REG_F3, "F3"}, 23018 {20, s390x.REG_F4, "F4"}, 23019 {21, s390x.REG_F5, "F5"}, 23020 {22, s390x.REG_F6, "F6"}, 23021 {23, s390x.REG_F7, "F7"}, 23022 {24, s390x.REG_F8, "F8"}, 23023 {25, s390x.REG_F9, "F9"}, 23024 {26, s390x.REG_F10, "F10"}, 23025 {27, s390x.REG_F11, "F11"}, 23026 {28, s390x.REG_F12, "F12"}, 23027 {29, s390x.REG_F13, "F13"}, 23028 {30, s390x.REG_F14, "F14"}, 23029 {31, s390x.REG_F15, "F15"}, 23030 {32, 0, "SB"}, 23031 } 23032 var gpRegMaskS390X = regMask(21503) 23033 var fpRegMaskS390X = regMask(4294901760) 23034 var specialRegMaskS390X = regMask(0) 23035 var framepointerRegS390X = int8(-1) 23036 var linkRegS390X = int8(14)