github.com/slayercat/go@v0.0.0-20170428012452-c51559813f61/src/cmd/internal/obj/ppc64/asm9.go (about) 1 // cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "encoding/binary" 36 "fmt" 37 "log" 38 "sort" 39 ) 40 41 // ctxt9 holds state while assembling a single function. 42 // Each function gets a fresh ctxt9. 43 // This allows for multiple functions to be safely concurrently assembled. 44 type ctxt9 struct { 45 ctxt *obj.Link 46 newprog obj.ProgAlloc 47 cursym *obj.LSym 48 autosize int32 49 instoffset int64 50 pc int64 51 } 52 53 // Instruction layout. 54 55 const ( 56 funcAlign = 8 57 ) 58 59 const ( 60 r0iszero = 1 61 ) 62 63 type Optab struct { 64 as obj.As // Opcode 65 a1 uint8 66 a2 uint8 67 a3 uint8 68 a4 uint8 69 type_ int8 // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r 70 size int8 71 param int16 72 } 73 74 var optab = []Optab{ 75 {obj.ATEXT, C_LEXT, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 76 {obj.ATEXT, C_LEXT, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 77 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 78 {obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 79 /* move register */ 80 {AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0}, 81 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 82 {AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 83 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 84 {AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 85 {AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 86 {AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 87 {AADD, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 88 {AADD, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 89 {AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0}, 90 {AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0}, 91 {AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 92 {AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 93 {AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 94 {AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 95 {AADDC, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 96 {AADDC, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 97 {AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 98 {AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 99 {AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, no literal */ 100 {AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 101 {AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 102 {AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 103 {AANDCC, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 104 {AANDCC, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 105 {AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 106 {AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 107 {AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 108 {AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 109 {AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 110 {AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 111 {AMULLW, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 112 {AMULLW, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 113 {AMULLW, C_ANDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 114 {AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 115 {AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 116 {AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 117 {ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, 118 {ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 119 {ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0}, 120 {ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0}, 121 {AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, literal not cc (or/xor) */ 122 {AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 123 {AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 124 {AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 125 {AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 126 {AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 127 {AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 128 {AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 129 {ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, /* op r1[,r2],r3 */ 130 {ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 131 {ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, /* op r2[,r1],r3 */ 132 {ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 133 {ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 134 {ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 135 {ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 136 {ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 137 {ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0}, 138 {ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0}, 139 {ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0}, 140 {ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0}, 141 {ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 142 {ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 143 {ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 144 {ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 145 {ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 146 {ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 147 {ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 148 {ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 149 {ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0}, 150 {ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0}, 151 {ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0}, 152 {ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 153 {ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 154 {ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 155 {ARLDICL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 156 {ARLDICL, C_SCON, C_REG, C_LCON, C_REG, 14, 4, 0}, 157 {ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0}, 158 {AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0}, 159 {AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 4, 0}, 160 {AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 161 {AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 162 {AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 163 {AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 4, 0}, 164 {AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0}, 165 {AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 4, 0}, 166 167 /* store, short offset */ 168 {AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 169 {AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 170 {AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 171 {AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 172 {AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 173 {AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 174 {AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 175 {AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 176 {AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 177 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 178 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 179 {AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 180 {AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 181 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 182 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 183 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 184 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 185 {AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 186 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 187 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 188 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 189 {AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 190 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 191 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 192 193 /* load, short offset */ 194 {AMOVD, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 195 {AMOVW, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 196 {AMOVWZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 197 {AMOVBZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 198 {AMOVBZU, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 199 {AMOVB, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 200 {AMOVBU, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 201 {AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 202 {AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 203 {AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 204 {AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 205 {AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB}, 206 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 207 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 208 {AMOVWZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 209 {AMOVBZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 210 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, 9, 8, REGSP}, 211 {AMOVD, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 212 {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 213 {AMOVWZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 214 {AMOVBZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 215 {AMOVBZU, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 216 {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 217 {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 218 219 /* store, long offset */ 220 {AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 221 {AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 222 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 223 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 224 {AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 225 {AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 226 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 227 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 228 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 229 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 230 {AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 231 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 232 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 233 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 234 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 235 {AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 236 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 237 {AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 238 {AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 239 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 240 241 /* load, long offset */ 242 {AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 243 {AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 244 {AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 245 {AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 246 {AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB}, 247 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 248 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 249 {AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 250 {AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 251 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 37, 12, REGSP}, 252 {AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 253 {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 254 {AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 255 {AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 256 {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 37, 12, REGZERO}, 257 {AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 258 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 259 {AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 260 {AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 261 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0}, 262 263 {AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 79, 4, 0}, 264 {AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 80, 8, 0}, 265 266 {AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 81, 8, 0}, 267 268 /* load constant */ 269 {AMOVD, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, 270 {AMOVD, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 271 {AMOVD, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 272 {AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 273 {AMOVD, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 274 {AMOVW, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 275 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 276 {AMOVW, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 277 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 278 {AMOVW, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 279 {AMOVWZ, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 280 {AMOVWZ, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 281 {AMOVWZ, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 282 {AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 283 {AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 284 285 /* load unsigned/long constants (TO DO: check) */ 286 {AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 287 {AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 288 {AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 289 {AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 290 {AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 291 {AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 292 {AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 293 {AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 294 {AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 295 {AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 296 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0}, 297 {ASYSCALL, C_REG, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 298 {ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 299 {ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 300 {ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 301 {ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, 302 {ABR, C_NONE, C_NONE, C_NONE, C_LBRAPIC, 11, 8, 0}, 303 {ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0}, 304 {ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0}, 305 {ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0}, 306 {ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 307 {ABR, C_REG, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 308 {ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 309 {ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0}, 310 {ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0}, 311 {ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0}, 312 {ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0}, 313 {ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 314 {AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB}, 315 {AFMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, 8, 4, REGSP}, 316 {AFMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, 8, 4, REGZERO}, 317 {AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 36, 8, REGSB}, 318 {AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, 8, REGSP}, 319 {AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 8, REGZERO}, 320 {AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0}, 321 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 322 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 323 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 324 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 325 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 326 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 327 {AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 328 {AFMOVSX, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 329 {AFMOVSX, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 330 {AFMOVSX, C_FREG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 331 {AFMOVSX, C_FREG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 332 {AFMOVSZ, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 333 {AFMOVSZ, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 334 {ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 335 {AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0}, 336 {ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 337 {ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 338 {AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 339 {AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0}, 340 {AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0}, 341 {AISEL, C_LCON, C_REG, C_REG, C_REG, 84, 4, 0}, 342 {AISEL, C_ZCON, C_REG, C_REG, C_REG, 84, 4, 0}, 343 {ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 344 {ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0}, 345 {AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0}, 346 {AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0}, 347 {AREMU, C_REG, C_NONE, C_NONE, C_REG, 50, 16, 0}, 348 {AREMU, C_REG, C_REG, C_NONE, C_REG, 50, 16, 0}, 349 {AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 350 {AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 351 {AREMDU, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 352 {AREMDU, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 353 {AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0}, 354 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0}, 355 {AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0}, 356 {AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0}, 357 {AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0}, 358 {AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0}, /* mfmsr */ 359 {AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsrd */ 360 {AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */ 361 362 /* Other ISA 2.05+ instructions */ 363 {APOPCNTD, C_REG, C_NONE, C_NONE, C_REG, 93, 4, 0}, /* population count, x-form */ 364 {ACMPB, C_REG, C_REG, C_NONE, C_REG, 92, 4, 0}, /* compare byte, x-form */ 365 {AFTDIV, C_FREG, C_FREG, C_NONE, C_SCON, 92, 4, 0}, /* floating test for sw divide, x-form */ 366 {AFTSQRT, C_FREG, C_NONE, C_NONE, C_SCON, 93, 4, 0}, /* floating test for sw square root, x-form */ 367 368 /* Vector instructions */ 369 370 /* Vector load */ 371 {ALV, C_SOREG, C_NONE, C_NONE, C_VREG, 45, 4, 0}, /* vector load, x-form */ 372 373 /* Vector store */ 374 {ASTV, C_VREG, C_NONE, C_NONE, C_SOREG, 44, 4, 0}, /* vector store, x-form */ 375 376 /* Vector logical */ 377 {AVAND, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector and, vx-form */ 378 {AVOR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector or, vx-form */ 379 380 /* Vector add */ 381 {AVADDUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned modulo, vx-form */ 382 {AVADDCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add & write carry unsigned, vx-form */ 383 {AVADDUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned saturate, vx-form */ 384 {AVADDSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add signed saturate, vx-form */ 385 {AVADDE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector add extended, va-form */ 386 387 /* Vector subtract */ 388 {AVSUBUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned modulo, vx-form */ 389 {AVSUBCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract & write carry unsigned, vx-form */ 390 {AVSUBUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned saturate, vx-form */ 391 {AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */ 392 {AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector subtract extended, va-form */ 393 394 /* Vector multiply */ 395 {AVPMSUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector polynomial multiply & sum, vx-form */ 396 397 /* Vector rotate */ 398 {AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */ 399 400 /* Vector shift */ 401 {AVS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift, vx-form */ 402 {AVSA, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift algebraic, vx-form */ 403 {AVSOI, C_ANDCON, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector shift by octet immediate, va-form */ 404 405 /* Vector count */ 406 {AVCLZ, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector count leading zeros, vx-form */ 407 {AVPOPCNT, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector population count, vx-form */ 408 409 /* Vector compare */ 410 {AVCMPEQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare equal, vc-form */ 411 {AVCMPGT, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare greater than, vc-form */ 412 413 /* Vector permute */ 414 {AVPERM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector permute, va-form */ 415 416 /* Vector select */ 417 {AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector select, va-form */ 418 419 /* Vector splat */ 420 {AVSPLT, C_SCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector splat, vx-form */ 421 {AVSPLT, C_ADDCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, 422 {AVSPLTI, C_SCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector splat immediate, vx-form */ 423 {AVSPLTI, C_ADDCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, 424 425 /* Vector AES */ 426 {AVCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES cipher, vx-form */ 427 {AVNCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES inverse cipher, vx-form */ 428 {AVSBOX, C_VREG, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector AES subbytes, vx-form */ 429 430 /* Vector SHA */ 431 {AVSHASIGMA, C_ANDCON, C_VREG, C_ANDCON, C_VREG, 82, 4, 0}, /* vector SHA sigma, vx-form */ 432 433 /* VSX vector load */ 434 {ALXV, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx vector load, xx1-form */ 435 436 /* VSX vector store */ 437 {ASTXV, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx vector store, xx1-form */ 438 439 /* VSX scalar load */ 440 {ALXS, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar load, xx1-form */ 441 442 /* VSX scalar store */ 443 {ASTXS, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar store, xx1-form */ 444 445 /* VSX scalar as integer load */ 446 {ALXSI, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar as integer load, xx1-form */ 447 448 /* VSX scalar store as integer */ 449 {ASTXSI, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar as integer store, xx1-form */ 450 451 /* VSX move from VSR */ 452 {AMFVSR, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */ 453 {AMFVSR, C_FREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 454 {AMFVSR, C_VREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 455 456 /* VSX move to VSR */ 457 {AMTVSR, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */ 458 {AMTVSR, C_REG, C_NONE, C_NONE, C_FREG, 88, 4, 0}, 459 {AMTVSR, C_REG, C_NONE, C_NONE, C_VREG, 88, 4, 0}, 460 461 /* VSX logical */ 462 {AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */ 463 {AXXLOR, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx or, xx3-form */ 464 465 /* VSX select */ 466 {AXXSEL, C_VSREG, C_VSREG, C_VSREG, C_VSREG, 91, 4, 0}, /* vsx select, xx4-form */ 467 468 /* VSX merge */ 469 {AXXMRG, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx merge, xx3-form */ 470 471 /* VSX splat */ 472 {AXXSPLT, C_VSREG, C_NONE, C_SCON, C_VSREG, 89, 4, 0}, /* vsx splat, xx2-form */ 473 474 /* VSX permute */ 475 {AXXPERM, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx permute, xx3-form */ 476 477 /* VSX shift */ 478 {AXXSI, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx shift immediate, xx3-form */ 479 480 /* VSX scalar FP-FP conversion */ 481 {AXSCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-fp conversion, xx2-form */ 482 483 /* VSX vector FP-FP conversion */ 484 {AXVCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-fp conversion, xx2-form */ 485 486 /* VSX scalar FP-integer conversion */ 487 {AXSCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-integer conversion, xx2-form */ 488 489 /* VSX scalar integer-FP conversion */ 490 {AXSCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar integer-fp conversion, xx2-form */ 491 492 /* VSX vector FP-integer conversion */ 493 {AXVCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-integer conversion, xx2-form */ 494 495 /* VSX vector integer-FP conversion */ 496 {AXVCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector integer-fp conversion, xx2-form */ 497 498 /* 64-bit special registers */ 499 {AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 500 {AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0}, 501 {AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 502 {AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 503 {AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 504 {AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 505 {AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 506 {AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 507 508 /* 32-bit special registers (gloss over sign-extension or not?) */ 509 {AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 510 {AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 511 {AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 512 {AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 513 {AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 514 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 515 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 516 {AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 517 {AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 518 {AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 519 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0}, 520 {AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0}, 521 {AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 522 {AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 523 {AMOVFL, C_REG, C_NONE, C_LCON, C_CREG, 69, 4, 0}, 524 {AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 525 {AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 526 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 527 {ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 528 {ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 529 {ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0}, 530 {ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0}, 531 {ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 532 {ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 533 {ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0}, 534 {ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0}, 535 {AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0}, 536 {AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0}, 537 {ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0}, 538 {ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0}, 539 {ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 540 {ADCBF, C_ZOREG, C_REG, C_NONE, C_NONE, 43, 4, 0}, 541 {AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 542 {AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 543 {AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 544 {AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 545 {AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 546 {ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0}, 547 {ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0}, 548 {ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 549 {ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 550 {ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 551 {ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0}, 552 {ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 553 {ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0}, 554 {obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 4, 0}, 555 {obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0, 0}, 556 {obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0, 0}, 557 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0}, 558 {obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 559 {obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 560 561 {obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0}, 562 } 563 564 var oprange [ALAST & obj.AMask][]Optab 565 566 var xcmp [C_NCLASS][C_NCLASS]bool 567 568 func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 569 p := cursym.Func.Text 570 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 571 return 572 } 573 574 if oprange[AANDN&obj.AMask] == nil { 575 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first") 576 } 577 578 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 579 580 pc := int64(0) 581 p.Pc = pc 582 583 var m int 584 var o *Optab 585 for p = p.Link; p != nil; p = p.Link { 586 p.Pc = pc 587 o = c.oplook(p) 588 m = int(o.size) 589 if m == 0 { 590 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 591 c.ctxt.Diag("zero-width instruction\n%v", p) 592 } 593 continue 594 } 595 596 pc += int64(m) 597 } 598 599 c.cursym.Size = pc 600 601 /* 602 * if any procedure is large enough to 603 * generate a large SBRA branch, then 604 * generate extra passes putting branches 605 * around jmps to fix. this is rare. 606 */ 607 bflag := 1 608 609 var otxt int64 610 var q *obj.Prog 611 for bflag != 0 { 612 bflag = 0 613 pc = 0 614 for p = c.cursym.Func.Text.Link; p != nil; p = p.Link { 615 p.Pc = pc 616 o = c.oplook(p) 617 618 // very large conditional branches 619 if (o.type_ == 16 || o.type_ == 17) && p.Pcond != nil { 620 otxt = p.Pcond.Pc - pc 621 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 { 622 q = c.newprog() 623 q.Link = p.Link 624 p.Link = q 625 q.As = ABR 626 q.To.Type = obj.TYPE_BRANCH 627 q.Pcond = p.Pcond 628 p.Pcond = q 629 q = c.newprog() 630 q.Link = p.Link 631 p.Link = q 632 q.As = ABR 633 q.To.Type = obj.TYPE_BRANCH 634 q.Pcond = q.Link.Link 635 636 //addnop(p->link); 637 //addnop(p); 638 bflag = 1 639 } 640 } 641 642 m = int(o.size) 643 if m == 0 { 644 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 645 c.ctxt.Diag("zero-width instruction\n%v", p) 646 } 647 continue 648 } 649 650 pc += int64(m) 651 } 652 653 c.cursym.Size = pc 654 } 655 656 pc += -pc & (funcAlign - 1) 657 c.cursym.Size = pc 658 659 /* 660 * lay out the code, emitting code and data relocations. 661 */ 662 663 c.cursym.Grow(c.cursym.Size) 664 665 bp := c.cursym.P 666 var i int32 667 var out [6]uint32 668 for p := c.cursym.Func.Text.Link; p != nil; p = p.Link { 669 c.pc = p.Pc 670 o = c.oplook(p) 671 if int(o.size) > 4*len(out) { 672 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p) 673 } 674 c.asmout(p, o, out[:]) 675 for i = 0; i < int32(o.size/4); i++ { 676 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i]) 677 bp = bp[4:] 678 } 679 } 680 } 681 682 func isint32(v int64) bool { 683 return int64(int32(v)) == v 684 } 685 686 func isuint32(v uint64) bool { 687 return uint64(uint32(v)) == v 688 } 689 690 func (c *ctxt9) aclass(a *obj.Addr) int { 691 switch a.Type { 692 case obj.TYPE_NONE: 693 return C_NONE 694 695 case obj.TYPE_REG: 696 if REG_R0 <= a.Reg && a.Reg <= REG_R31 { 697 return C_REG 698 } 699 if REG_F0 <= a.Reg && a.Reg <= REG_F31 { 700 return C_FREG 701 } 702 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 703 return C_VREG 704 } 705 if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 { 706 return C_VSREG 707 } 708 if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR { 709 return C_CREG 710 } 711 if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 { 712 switch a.Reg { 713 case REG_LR: 714 return C_LR 715 716 case REG_XER: 717 return C_XER 718 719 case REG_CTR: 720 return C_CTR 721 } 722 723 return C_SPR 724 } 725 726 if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 { 727 return C_SPR 728 } 729 if a.Reg == REG_FPSCR { 730 return C_FPSCR 731 } 732 if a.Reg == REG_MSR { 733 return C_MSR 734 } 735 return C_GOK 736 737 case obj.TYPE_MEM: 738 switch a.Name { 739 case obj.NAME_EXTERN, 740 obj.NAME_STATIC: 741 if a.Sym == nil { 742 break 743 } 744 c.instoffset = a.Offset 745 if a.Sym != nil { // use relocation 746 if a.Sym.Type == objabi.STLSBSS { 747 if c.ctxt.Flag_shared { 748 return C_TLS_IE 749 } else { 750 return C_TLS_LE 751 } 752 } 753 return C_ADDR 754 } 755 return C_LEXT 756 757 case obj.NAME_GOTREF: 758 return C_GOTADDR 759 760 case obj.NAME_AUTO: 761 c.instoffset = int64(c.autosize) + a.Offset 762 if c.instoffset >= -BIG && c.instoffset < BIG { 763 return C_SAUTO 764 } 765 return C_LAUTO 766 767 case obj.NAME_PARAM: 768 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 769 if c.instoffset >= -BIG && c.instoffset < BIG { 770 return C_SAUTO 771 } 772 return C_LAUTO 773 774 case obj.NAME_NONE: 775 c.instoffset = a.Offset 776 if c.instoffset == 0 { 777 return C_ZOREG 778 } 779 if c.instoffset >= -BIG && c.instoffset < BIG { 780 return C_SOREG 781 } 782 return C_LOREG 783 } 784 785 return C_GOK 786 787 case obj.TYPE_TEXTSIZE: 788 return C_TEXTSIZE 789 790 case obj.TYPE_CONST, 791 obj.TYPE_ADDR: 792 switch a.Name { 793 case obj.NAME_NONE: 794 c.instoffset = a.Offset 795 if a.Reg != 0 { 796 if -BIG <= c.instoffset && c.instoffset <= BIG { 797 return C_SACON 798 } 799 if isint32(c.instoffset) { 800 return C_LACON 801 } 802 return C_DACON 803 } 804 805 goto consize 806 807 case obj.NAME_EXTERN, 808 obj.NAME_STATIC: 809 s := a.Sym 810 if s == nil { 811 break 812 } 813 if s.Type == objabi.SCONST { 814 c.instoffset = a.Offset 815 goto consize 816 } 817 818 c.instoffset = a.Offset 819 820 /* not sure why this barfs */ 821 return C_LCON 822 823 case obj.NAME_AUTO: 824 c.instoffset = int64(c.autosize) + a.Offset 825 if c.instoffset >= -BIG && c.instoffset < BIG { 826 return C_SACON 827 } 828 return C_LACON 829 830 case obj.NAME_PARAM: 831 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 832 if c.instoffset >= -BIG && c.instoffset < BIG { 833 return C_SACON 834 } 835 return C_LACON 836 } 837 838 return C_GOK 839 840 consize: 841 if c.instoffset >= 0 { 842 if c.instoffset == 0 { 843 return C_ZCON 844 } 845 if c.instoffset <= 0x7fff { 846 return C_SCON 847 } 848 if c.instoffset <= 0xffff { 849 return C_ANDCON 850 } 851 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 852 return C_UCON 853 } 854 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 855 return C_LCON 856 } 857 return C_DCON 858 } 859 860 if c.instoffset >= -0x8000 { 861 return C_ADDCON 862 } 863 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 864 return C_UCON 865 } 866 if isint32(c.instoffset) { 867 return C_LCON 868 } 869 return C_DCON 870 871 case obj.TYPE_BRANCH: 872 if a.Sym != nil && c.ctxt.Flag_dynlink { 873 return C_LBRAPIC 874 } 875 return C_SBRA 876 } 877 878 return C_GOK 879 } 880 881 func prasm(p *obj.Prog) { 882 fmt.Printf("%v\n", p) 883 } 884 885 func (c *ctxt9) oplook(p *obj.Prog) *Optab { 886 a1 := int(p.Optab) 887 if a1 != 0 { 888 return &optab[a1-1] 889 } 890 a1 = int(p.From.Class) 891 if a1 == 0 { 892 a1 = c.aclass(&p.From) + 1 893 p.From.Class = int8(a1) 894 } 895 896 a1-- 897 a3 := C_NONE + 1 898 if p.From3 != nil { 899 a3 = int(p.From3.Class) 900 if a3 == 0 { 901 a3 = c.aclass(p.From3) + 1 902 p.From3.Class = int8(a3) 903 } 904 } 905 906 a3-- 907 a4 := int(p.To.Class) 908 if a4 == 0 { 909 a4 = c.aclass(&p.To) + 1 910 p.To.Class = int8(a4) 911 } 912 913 a4-- 914 a2 := C_NONE 915 if p.Reg != 0 { 916 if REG_R0 <= p.Reg && p.Reg <= REG_R31 { 917 a2 = C_REG 918 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 919 a2 = C_VREG 920 } else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 { 921 a2 = C_VSREG 922 } else if REG_F0 <= p.Reg && p.Reg <= REG_F31 { 923 a2 = C_FREG 924 } 925 } 926 927 //print("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4); 928 ops := oprange[p.As&obj.AMask] 929 c1 := &xcmp[a1] 930 c3 := &xcmp[a3] 931 c4 := &xcmp[a4] 932 for i := range ops { 933 op := &ops[i] 934 if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] { 935 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 936 return op 937 } 938 } 939 940 c.ctxt.Diag("illegal combination %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 941 prasm(p) 942 if ops == nil { 943 ops = optab 944 } 945 return &ops[0] 946 } 947 948 func cmp(a int, b int) bool { 949 if a == b { 950 return true 951 } 952 switch a { 953 case C_LCON: 954 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 955 return true 956 } 957 958 case C_ADDCON: 959 if b == C_ZCON || b == C_SCON { 960 return true 961 } 962 963 case C_ANDCON: 964 if b == C_ZCON || b == C_SCON { 965 return true 966 } 967 968 case C_SPR: 969 if b == C_LR || b == C_XER || b == C_CTR { 970 return true 971 } 972 973 case C_UCON: 974 if b == C_ZCON { 975 return true 976 } 977 978 case C_SCON: 979 if b == C_ZCON { 980 return true 981 } 982 983 case C_LACON: 984 if b == C_SACON { 985 return true 986 } 987 988 case C_LBRA: 989 if b == C_SBRA { 990 return true 991 } 992 993 case C_LEXT: 994 if b == C_SEXT { 995 return true 996 } 997 998 case C_LAUTO: 999 if b == C_SAUTO { 1000 return true 1001 } 1002 1003 case C_REG: 1004 if b == C_ZCON { 1005 return r0iszero != 0 /*TypeKind(100016)*/ 1006 } 1007 1008 case C_LOREG: 1009 if b == C_ZOREG || b == C_SOREG { 1010 return true 1011 } 1012 1013 case C_SOREG: 1014 if b == C_ZOREG { 1015 return true 1016 } 1017 1018 case C_ANY: 1019 return true 1020 } 1021 1022 return false 1023 } 1024 1025 type ocmp []Optab 1026 1027 func (x ocmp) Len() int { 1028 return len(x) 1029 } 1030 1031 func (x ocmp) Swap(i, j int) { 1032 x[i], x[j] = x[j], x[i] 1033 } 1034 1035 func (x ocmp) Less(i, j int) bool { 1036 p1 := &x[i] 1037 p2 := &x[j] 1038 n := int(p1.as) - int(p2.as) 1039 if n != 0 { 1040 return n < 0 1041 } 1042 n = int(p1.a1) - int(p2.a1) 1043 if n != 0 { 1044 return n < 0 1045 } 1046 n = int(p1.a2) - int(p2.a2) 1047 if n != 0 { 1048 return n < 0 1049 } 1050 n = int(p1.a3) - int(p2.a3) 1051 if n != 0 { 1052 return n < 0 1053 } 1054 n = int(p1.a4) - int(p2.a4) 1055 if n != 0 { 1056 return n < 0 1057 } 1058 return false 1059 } 1060 func opset(a, b0 obj.As) { 1061 oprange[a&obj.AMask] = oprange[b0] 1062 } 1063 1064 func buildop(ctxt *obj.Link) { 1065 if oprange[AANDN&obj.AMask] != nil { 1066 // Already initialized; stop now. 1067 // This happens in the cmd/asm tests, 1068 // each of which re-initializes the arch. 1069 return 1070 } 1071 1072 var n int 1073 1074 for i := 0; i < C_NCLASS; i++ { 1075 for n = 0; n < C_NCLASS; n++ { 1076 if cmp(n, i) { 1077 xcmp[i][n] = true 1078 } 1079 } 1080 } 1081 for n = 0; optab[n].as != obj.AXXX; n++ { 1082 } 1083 sort.Sort(ocmp(optab[:n])) 1084 for i := 0; i < n; i++ { 1085 r := optab[i].as 1086 r0 := r & obj.AMask 1087 start := i 1088 for optab[i].as == r { 1089 i++ 1090 } 1091 oprange[r0] = optab[start:i] 1092 i-- 1093 1094 switch r { 1095 default: 1096 ctxt.Diag("unknown op in build: %v", r) 1097 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r) 1098 1099 case ADCBF: /* unary indexed: op (b+a); op (b) */ 1100 opset(ADCBI, r0) 1101 1102 opset(ADCBST, r0) 1103 opset(ADCBT, r0) 1104 opset(ADCBTST, r0) 1105 opset(ADCBZ, r0) 1106 opset(AICBI, r0) 1107 1108 case AECOWX: /* indexed store: op s,(b+a); op s,(b) */ 1109 opset(ASTWCCC, r0) 1110 opset(ASTBCCC, r0) 1111 1112 opset(ASTDCCC, r0) 1113 1114 case AREM: /* macro */ 1115 opset(AREMCC, r0) 1116 1117 opset(AREMV, r0) 1118 opset(AREMVCC, r0) 1119 1120 case AREMU: 1121 opset(AREMU, r0) 1122 opset(AREMUCC, r0) 1123 opset(AREMUV, r0) 1124 opset(AREMUVCC, r0) 1125 1126 case AREMD: 1127 opset(AREMDCC, r0) 1128 opset(AREMDV, r0) 1129 opset(AREMDVCC, r0) 1130 1131 case AREMDU: 1132 opset(AREMDU, r0) 1133 opset(AREMDUCC, r0) 1134 opset(AREMDUV, r0) 1135 opset(AREMDUVCC, r0) 1136 1137 case ADIVW: /* op Rb[,Ra],Rd */ 1138 opset(AMULHW, r0) 1139 1140 opset(AMULHWCC, r0) 1141 opset(AMULHWU, r0) 1142 opset(AMULHWUCC, r0) 1143 opset(AMULLWCC, r0) 1144 opset(AMULLWVCC, r0) 1145 opset(AMULLWV, r0) 1146 opset(ADIVWCC, r0) 1147 opset(ADIVWV, r0) 1148 opset(ADIVWVCC, r0) 1149 opset(ADIVWU, r0) 1150 opset(ADIVWUCC, r0) 1151 opset(ADIVWUV, r0) 1152 opset(ADIVWUVCC, r0) 1153 opset(AADDCC, r0) 1154 opset(AADDCV, r0) 1155 opset(AADDCVCC, r0) 1156 opset(AADDV, r0) 1157 opset(AADDVCC, r0) 1158 opset(AADDE, r0) 1159 opset(AADDECC, r0) 1160 opset(AADDEV, r0) 1161 opset(AADDEVCC, r0) 1162 opset(ACRAND, r0) 1163 opset(ACRANDN, r0) 1164 opset(ACREQV, r0) 1165 opset(ACRNAND, r0) 1166 opset(ACRNOR, r0) 1167 opset(ACROR, r0) 1168 opset(ACRORN, r0) 1169 opset(ACRXOR, r0) 1170 opset(AMULHD, r0) 1171 opset(AMULHDCC, r0) 1172 opset(AMULHDU, r0) 1173 opset(AMULHDUCC, r0) 1174 opset(AMULLD, r0) 1175 opset(AMULLDCC, r0) 1176 opset(AMULLDVCC, r0) 1177 opset(AMULLDV, r0) 1178 opset(ADIVD, r0) 1179 opset(ADIVDCC, r0) 1180 opset(ADIVDE, r0) 1181 opset(ADIVDEU, r0) 1182 opset(ADIVDECC, r0) 1183 opset(ADIVDEUCC, r0) 1184 opset(ADIVDVCC, r0) 1185 opset(ADIVDV, r0) 1186 opset(ADIVDU, r0) 1187 opset(ADIVDUCC, r0) 1188 opset(ADIVDUVCC, r0) 1189 opset(ADIVDUCC, r0) 1190 1191 case APOPCNTD: 1192 opset(APOPCNTW, r0) 1193 opset(APOPCNTB, r0) 1194 1195 case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */ 1196 opset(AMOVH, r0) 1197 1198 opset(AMOVHZ, r0) 1199 1200 case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */ 1201 opset(AMOVHU, r0) 1202 1203 opset(AMOVHZU, r0) 1204 opset(AMOVWU, r0) 1205 opset(AMOVWZU, r0) 1206 opset(AMOVDU, r0) 1207 opset(AMOVMW, r0) 1208 1209 case ALV: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */ 1210 opset(ALVEBX, r0) 1211 opset(ALVEHX, r0) 1212 opset(ALVEWX, r0) 1213 opset(ALVX, r0) 1214 opset(ALVXL, r0) 1215 opset(ALVSL, r0) 1216 opset(ALVSR, r0) 1217 1218 case ASTV: /* stvebx, stvehx, stvewx, stvx, stvxl */ 1219 opset(ASTVEBX, r0) 1220 opset(ASTVEHX, r0) 1221 opset(ASTVEWX, r0) 1222 opset(ASTVX, r0) 1223 opset(ASTVXL, r0) 1224 1225 case AVAND: /* vand, vandc, vnand */ 1226 opset(AVAND, r0) 1227 opset(AVANDC, r0) 1228 opset(AVNAND, r0) 1229 1230 case AVOR: /* vor, vorc, vxor, vnor, veqv */ 1231 opset(AVOR, r0) 1232 opset(AVORC, r0) 1233 opset(AVXOR, r0) 1234 opset(AVNOR, r0) 1235 opset(AVEQV, r0) 1236 1237 case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */ 1238 opset(AVADDUBM, r0) 1239 opset(AVADDUHM, r0) 1240 opset(AVADDUWM, r0) 1241 opset(AVADDUDM, r0) 1242 opset(AVADDUQM, r0) 1243 1244 case AVADDCU: /* vaddcuq, vaddcuw */ 1245 opset(AVADDCUQ, r0) 1246 opset(AVADDCUW, r0) 1247 1248 case AVADDUS: /* vaddubs, vadduhs, vadduws */ 1249 opset(AVADDUBS, r0) 1250 opset(AVADDUHS, r0) 1251 opset(AVADDUWS, r0) 1252 1253 case AVADDSS: /* vaddsbs, vaddshs, vaddsws */ 1254 opset(AVADDSBS, r0) 1255 opset(AVADDSHS, r0) 1256 opset(AVADDSWS, r0) 1257 1258 case AVADDE: /* vaddeuqm, vaddecuq */ 1259 opset(AVADDEUQM, r0) 1260 opset(AVADDECUQ, r0) 1261 1262 case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */ 1263 opset(AVSUBUBM, r0) 1264 opset(AVSUBUHM, r0) 1265 opset(AVSUBUWM, r0) 1266 opset(AVSUBUDM, r0) 1267 opset(AVSUBUQM, r0) 1268 1269 case AVSUBCU: /* vsubcuq, vsubcuw */ 1270 opset(AVSUBCUQ, r0) 1271 opset(AVSUBCUW, r0) 1272 1273 case AVSUBUS: /* vsububs, vsubuhs, vsubuws */ 1274 opset(AVSUBUBS, r0) 1275 opset(AVSUBUHS, r0) 1276 opset(AVSUBUWS, r0) 1277 1278 case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */ 1279 opset(AVSUBSBS, r0) 1280 opset(AVSUBSHS, r0) 1281 opset(AVSUBSWS, r0) 1282 1283 case AVSUBE: /* vsubeuqm, vsubecuq */ 1284 opset(AVSUBEUQM, r0) 1285 opset(AVSUBECUQ, r0) 1286 1287 case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */ 1288 opset(AVPMSUMB, r0) 1289 opset(AVPMSUMH, r0) 1290 opset(AVPMSUMW, r0) 1291 opset(AVPMSUMD, r0) 1292 1293 case AVR: /* vrlb, vrlh, vrlw, vrld */ 1294 opset(AVRLB, r0) 1295 opset(AVRLH, r0) 1296 opset(AVRLW, r0) 1297 opset(AVRLD, r0) 1298 1299 case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */ 1300 opset(AVSLB, r0) 1301 opset(AVSLH, r0) 1302 opset(AVSLW, r0) 1303 opset(AVSL, r0) 1304 opset(AVSLO, r0) 1305 opset(AVSRB, r0) 1306 opset(AVSRH, r0) 1307 opset(AVSRW, r0) 1308 opset(AVSR, r0) 1309 opset(AVSRO, r0) 1310 opset(AVSLD, r0) 1311 opset(AVSRD, r0) 1312 1313 case AVSA: /* vsrab, vsrah, vsraw, vsrad */ 1314 opset(AVSRAB, r0) 1315 opset(AVSRAH, r0) 1316 opset(AVSRAW, r0) 1317 opset(AVSRAD, r0) 1318 1319 case AVSOI: /* vsldoi */ 1320 opset(AVSLDOI, r0) 1321 1322 case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */ 1323 opset(AVCLZB, r0) 1324 opset(AVCLZH, r0) 1325 opset(AVCLZW, r0) 1326 opset(AVCLZD, r0) 1327 1328 case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */ 1329 opset(AVPOPCNTB, r0) 1330 opset(AVPOPCNTH, r0) 1331 opset(AVPOPCNTW, r0) 1332 opset(AVPOPCNTD, r0) 1333 1334 case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */ 1335 opset(AVCMPEQUB, r0) 1336 opset(AVCMPEQUBCC, r0) 1337 opset(AVCMPEQUH, r0) 1338 opset(AVCMPEQUHCC, r0) 1339 opset(AVCMPEQUW, r0) 1340 opset(AVCMPEQUWCC, r0) 1341 opset(AVCMPEQUD, r0) 1342 opset(AVCMPEQUDCC, r0) 1343 1344 case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */ 1345 opset(AVCMPGTUB, r0) 1346 opset(AVCMPGTUBCC, r0) 1347 opset(AVCMPGTUH, r0) 1348 opset(AVCMPGTUHCC, r0) 1349 opset(AVCMPGTUW, r0) 1350 opset(AVCMPGTUWCC, r0) 1351 opset(AVCMPGTUD, r0) 1352 opset(AVCMPGTUDCC, r0) 1353 opset(AVCMPGTSB, r0) 1354 opset(AVCMPGTSBCC, r0) 1355 opset(AVCMPGTSH, r0) 1356 opset(AVCMPGTSHCC, r0) 1357 opset(AVCMPGTSW, r0) 1358 opset(AVCMPGTSWCC, r0) 1359 opset(AVCMPGTSD, r0) 1360 opset(AVCMPGTSDCC, r0) 1361 1362 case AVPERM: /* vperm */ 1363 opset(AVPERM, r0) 1364 1365 case AVSEL: /* vsel */ 1366 opset(AVSEL, r0) 1367 1368 case AVSPLT: /* vspltb, vsplth, vspltw */ 1369 opset(AVSPLTB, r0) 1370 opset(AVSPLTH, r0) 1371 opset(AVSPLTW, r0) 1372 1373 case AVSPLTI: /* vspltisb, vspltish, vspltisw */ 1374 opset(AVSPLTISB, r0) 1375 opset(AVSPLTISH, r0) 1376 opset(AVSPLTISW, r0) 1377 1378 case AVCIPH: /* vcipher, vcipherlast */ 1379 opset(AVCIPHER, r0) 1380 opset(AVCIPHERLAST, r0) 1381 1382 case AVNCIPH: /* vncipher, vncipherlast */ 1383 opset(AVNCIPHER, r0) 1384 opset(AVNCIPHERLAST, r0) 1385 1386 case AVSBOX: /* vsbox */ 1387 opset(AVSBOX, r0) 1388 1389 case AVSHASIGMA: /* vshasigmaw, vshasigmad */ 1390 opset(AVSHASIGMAW, r0) 1391 opset(AVSHASIGMAD, r0) 1392 1393 case ALXV: /* lxvd2x, lxvdsx, lxvw4x */ 1394 opset(ALXVD2X, r0) 1395 opset(ALXVDSX, r0) 1396 opset(ALXVW4X, r0) 1397 1398 case ASTXV: /* stxvd2x, stxvdsx, stxvw4x */ 1399 opset(ASTXVD2X, r0) 1400 opset(ASTXVW4X, r0) 1401 1402 case ALXS: /* lxsdx */ 1403 opset(ALXSDX, r0) 1404 1405 case ASTXS: /* stxsdx */ 1406 opset(ASTXSDX, r0) 1407 1408 case ALXSI: /* lxsiwax, lxsiwzx */ 1409 opset(ALXSIWAX, r0) 1410 opset(ALXSIWZX, r0) 1411 1412 case ASTXSI: /* stxsiwx */ 1413 opset(ASTXSIWX, r0) 1414 1415 case AMFVSR: /* mfvsrd, mfvsrwz (and extended mnemonics) */ 1416 opset(AMFVSRD, r0) 1417 opset(AMFFPRD, r0) 1418 opset(AMFVRD, r0) 1419 opset(AMFVSRWZ, r0) 1420 1421 case AMTVSR: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics) */ 1422 opset(AMTVSRD, r0) 1423 opset(AMTFPRD, r0) 1424 opset(AMTVRD, r0) 1425 opset(AMTVSRWA, r0) 1426 opset(AMTVSRWZ, r0) 1427 1428 case AXXLAND: /* xxland, xxlandc, xxleqv, xxlnand */ 1429 opset(AXXLANDQ, r0) 1430 opset(AXXLANDC, r0) 1431 opset(AXXLEQV, r0) 1432 opset(AXXLNAND, r0) 1433 1434 case AXXLOR: /* xxlorc, xxlnor, xxlor, xxlxor */ 1435 opset(AXXLORC, r0) 1436 opset(AXXLNOR, r0) 1437 opset(AXXLORQ, r0) 1438 opset(AXXLXOR, r0) 1439 1440 case AXXSEL: /* xxsel */ 1441 opset(AXXSEL, r0) 1442 1443 case AXXMRG: /* xxmrghw, xxmrglw */ 1444 opset(AXXMRGHW, r0) 1445 opset(AXXMRGLW, r0) 1446 1447 case AXXSPLT: /* xxspltw */ 1448 opset(AXXSPLTW, r0) 1449 1450 case AXXPERM: /* xxpermdi */ 1451 opset(AXXPERMDI, r0) 1452 1453 case AXXSI: /* xxsldwi */ 1454 opset(AXXSLDWI, r0) 1455 1456 case AXSCV: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */ 1457 opset(AXSCVDPSP, r0) 1458 opset(AXSCVSPDP, r0) 1459 opset(AXSCVDPSPN, r0) 1460 opset(AXSCVSPDPN, r0) 1461 1462 case AXVCV: /* xvcvdpsp, xvcvspdp */ 1463 opset(AXVCVDPSP, r0) 1464 opset(AXVCVSPDP, r0) 1465 1466 case AXSCVX: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */ 1467 opset(AXSCVDPSXDS, r0) 1468 opset(AXSCVDPSXWS, r0) 1469 opset(AXSCVDPUXDS, r0) 1470 opset(AXSCVDPUXWS, r0) 1471 1472 case AXSCVXP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */ 1473 opset(AXSCVSXDDP, r0) 1474 opset(AXSCVUXDDP, r0) 1475 opset(AXSCVSXDSP, r0) 1476 opset(AXSCVUXDSP, r0) 1477 1478 case AXVCVX: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */ 1479 opset(AXVCVDPSXDS, r0) 1480 opset(AXVCVDPSXWS, r0) 1481 opset(AXVCVDPUXDS, r0) 1482 opset(AXVCVDPUXWS, r0) 1483 opset(AXVCVSPSXDS, r0) 1484 opset(AXVCVSPSXWS, r0) 1485 opset(AXVCVSPUXDS, r0) 1486 opset(AXVCVSPUXWS, r0) 1487 1488 case AXVCVXP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */ 1489 opset(AXVCVSXDDP, r0) 1490 opset(AXVCVSXWDP, r0) 1491 opset(AXVCVUXDDP, r0) 1492 opset(AXVCVUXWDP, r0) 1493 opset(AXVCVSXDSP, r0) 1494 opset(AXVCVSXWSP, r0) 1495 opset(AXVCVUXDSP, r0) 1496 opset(AXVCVUXWSP, r0) 1497 1498 case AAND: /* logical op Rb,Rs,Ra; no literal */ 1499 opset(AANDN, r0) 1500 1501 opset(AANDNCC, r0) 1502 opset(AEQV, r0) 1503 opset(AEQVCC, r0) 1504 opset(ANAND, r0) 1505 opset(ANANDCC, r0) 1506 opset(ANOR, r0) 1507 opset(ANORCC, r0) 1508 opset(AORCC, r0) 1509 opset(AORN, r0) 1510 opset(AORNCC, r0) 1511 opset(AXORCC, r0) 1512 1513 case AADDME: /* op Ra, Rd */ 1514 opset(AADDMECC, r0) 1515 1516 opset(AADDMEV, r0) 1517 opset(AADDMEVCC, r0) 1518 opset(AADDZE, r0) 1519 opset(AADDZECC, r0) 1520 opset(AADDZEV, r0) 1521 opset(AADDZEVCC, r0) 1522 opset(ASUBME, r0) 1523 opset(ASUBMECC, r0) 1524 opset(ASUBMEV, r0) 1525 opset(ASUBMEVCC, r0) 1526 opset(ASUBZE, r0) 1527 opset(ASUBZECC, r0) 1528 opset(ASUBZEV, r0) 1529 opset(ASUBZEVCC, r0) 1530 1531 case AADDC: 1532 opset(AADDCCC, r0) 1533 1534 case ABEQ: 1535 opset(ABGE, r0) 1536 opset(ABGT, r0) 1537 opset(ABLE, r0) 1538 opset(ABLT, r0) 1539 opset(ABNE, r0) 1540 opset(ABVC, r0) 1541 opset(ABVS, r0) 1542 1543 case ABR: 1544 opset(ABL, r0) 1545 1546 case ABC: 1547 opset(ABCL, r0) 1548 1549 case AEXTSB: /* op Rs, Ra */ 1550 opset(AEXTSBCC, r0) 1551 1552 opset(AEXTSH, r0) 1553 opset(AEXTSHCC, r0) 1554 opset(ACNTLZW, r0) 1555 opset(ACNTLZWCC, r0) 1556 opset(ACNTLZD, r0) 1557 opset(AEXTSW, r0) 1558 opset(AEXTSWCC, r0) 1559 opset(ACNTLZDCC, r0) 1560 1561 case AFABS: /* fop [s,]d */ 1562 opset(AFABSCC, r0) 1563 1564 opset(AFNABS, r0) 1565 opset(AFNABSCC, r0) 1566 opset(AFNEG, r0) 1567 opset(AFNEGCC, r0) 1568 opset(AFRSP, r0) 1569 opset(AFRSPCC, r0) 1570 opset(AFCTIW, r0) 1571 opset(AFCTIWCC, r0) 1572 opset(AFCTIWZ, r0) 1573 opset(AFCTIWZCC, r0) 1574 opset(AFCTID, r0) 1575 opset(AFCTIDCC, r0) 1576 opset(AFCTIDZ, r0) 1577 opset(AFCTIDZCC, r0) 1578 opset(AFCFID, r0) 1579 opset(AFCFIDCC, r0) 1580 opset(AFCFIDU, r0) 1581 opset(AFCFIDUCC, r0) 1582 opset(AFRES, r0) 1583 opset(AFRESCC, r0) 1584 opset(AFRIM, r0) 1585 opset(AFRIMCC, r0) 1586 opset(AFRIP, r0) 1587 opset(AFRIPCC, r0) 1588 opset(AFRIZ, r0) 1589 opset(AFRIZCC, r0) 1590 opset(AFRSQRTE, r0) 1591 opset(AFRSQRTECC, r0) 1592 opset(AFSQRT, r0) 1593 opset(AFSQRTCC, r0) 1594 opset(AFSQRTS, r0) 1595 opset(AFSQRTSCC, r0) 1596 1597 case AFADD: 1598 opset(AFADDS, r0) 1599 opset(AFADDCC, r0) 1600 opset(AFADDSCC, r0) 1601 opset(AFDIV, r0) 1602 opset(AFDIVS, r0) 1603 opset(AFDIVCC, r0) 1604 opset(AFDIVSCC, r0) 1605 opset(AFSUB, r0) 1606 opset(AFSUBS, r0) 1607 opset(AFSUBCC, r0) 1608 opset(AFSUBSCC, r0) 1609 1610 case AFMADD: 1611 opset(AFMADDCC, r0) 1612 opset(AFMADDS, r0) 1613 opset(AFMADDSCC, r0) 1614 opset(AFMSUB, r0) 1615 opset(AFMSUBCC, r0) 1616 opset(AFMSUBS, r0) 1617 opset(AFMSUBSCC, r0) 1618 opset(AFNMADD, r0) 1619 opset(AFNMADDCC, r0) 1620 opset(AFNMADDS, r0) 1621 opset(AFNMADDSCC, r0) 1622 opset(AFNMSUB, r0) 1623 opset(AFNMSUBCC, r0) 1624 opset(AFNMSUBS, r0) 1625 opset(AFNMSUBSCC, r0) 1626 opset(AFSEL, r0) 1627 opset(AFSELCC, r0) 1628 1629 case AFMUL: 1630 opset(AFMULS, r0) 1631 opset(AFMULCC, r0) 1632 opset(AFMULSCC, r0) 1633 1634 case AFCMPO: 1635 opset(AFCMPU, r0) 1636 1637 case AISEL: 1638 opset(AISEL, r0) 1639 1640 case AMTFSB0: 1641 opset(AMTFSB0CC, r0) 1642 opset(AMTFSB1, r0) 1643 opset(AMTFSB1CC, r0) 1644 1645 case ANEG: /* op [Ra,] Rd */ 1646 opset(ANEGCC, r0) 1647 1648 opset(ANEGV, r0) 1649 opset(ANEGVCC, r0) 1650 1651 case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,Ra; oris/xoris $uimm,Rs,Ra */ 1652 opset(AXOR, r0) 1653 1654 case ASLW: 1655 opset(ASLWCC, r0) 1656 opset(ASRW, r0) 1657 opset(ASRWCC, r0) 1658 opset(AROTLW, r0) 1659 1660 case ASLD: 1661 opset(ASLDCC, r0) 1662 opset(ASRD, r0) 1663 opset(ASRDCC, r0) 1664 opset(AROTL, r0) 1665 1666 case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1667 opset(ASRAWCC, r0) 1668 1669 case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1670 opset(ASRADCC, r0) 1671 1672 case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */ 1673 opset(ASUB, r0) 1674 1675 opset(ASUBCC, r0) 1676 opset(ASUBV, r0) 1677 opset(ASUBVCC, r0) 1678 opset(ASUBCCC, r0) 1679 opset(ASUBCV, r0) 1680 opset(ASUBCVCC, r0) 1681 opset(ASUBE, r0) 1682 opset(ASUBECC, r0) 1683 opset(ASUBEV, r0) 1684 opset(ASUBEVCC, r0) 1685 1686 case ASYNC: 1687 opset(AISYNC, r0) 1688 opset(ALWSYNC, r0) 1689 opset(APTESYNC, r0) 1690 opset(ATLBSYNC, r0) 1691 1692 case ARLWMI: 1693 opset(ARLWMICC, r0) 1694 opset(ARLWNM, r0) 1695 opset(ARLWNMCC, r0) 1696 1697 case ARLDMI: 1698 opset(ARLDMICC, r0) 1699 opset(ARLDIMI, r0) 1700 opset(ARLDIMICC, r0) 1701 1702 case ARLDC: 1703 opset(ARLDCCC, r0) 1704 1705 case ARLDCL: 1706 opset(ARLDCR, r0) 1707 opset(ARLDCLCC, r0) 1708 opset(ARLDCRCC, r0) 1709 1710 case ARLDICL: 1711 opset(ARLDICLCC, r0) 1712 opset(ARLDICR, r0) 1713 opset(ARLDICRCC, r0) 1714 1715 case AFMOVD: 1716 opset(AFMOVDCC, r0) 1717 opset(AFMOVDU, r0) 1718 opset(AFMOVS, r0) 1719 opset(AFMOVSU, r0) 1720 1721 case AECIWX: 1722 opset(ALBAR, r0) 1723 opset(ALWAR, r0) 1724 opset(ALDAR, r0) 1725 1726 case ASYSCALL: /* just the op; flow of control */ 1727 opset(ARFI, r0) 1728 1729 opset(ARFCI, r0) 1730 opset(ARFID, r0) 1731 opset(AHRFID, r0) 1732 1733 case AMOVHBR: 1734 opset(AMOVWBR, r0) 1735 opset(AMOVDBR, r0) 1736 1737 case ASLBMFEE: 1738 opset(ASLBMFEV, r0) 1739 1740 case ATW: 1741 opset(ATD, r0) 1742 1743 case ATLBIE: 1744 opset(ASLBIE, r0) 1745 opset(ATLBIEL, r0) 1746 1747 case AEIEIO: 1748 opset(ASLBIA, r0) 1749 1750 case ACMP: 1751 opset(ACMPW, r0) 1752 1753 case ACMPU: 1754 opset(ACMPWU, r0) 1755 1756 case ACMPB: 1757 opset(ACMPB, r0) 1758 1759 case AFTDIV: 1760 opset(AFTDIV, r0) 1761 1762 case AFTSQRT: 1763 opset(AFTSQRT, r0) 1764 1765 case AADD, 1766 AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra; andis. $uimm,Rs,Ra */ 1767 AFMOVSX, 1768 AFMOVSZ, 1769 ALSW, 1770 AMOVW, 1771 /* load/store/move word with sign extension; special 32-bit move; move 32-bit literals */ 1772 AMOVWZ, /* load/store/move word with zero extension; move 32-bit literals */ 1773 AMOVD, /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */ 1774 AMOVB, /* macro: move byte with sign extension */ 1775 AMOVBU, /* macro: move byte with sign extension & update */ 1776 AMOVFL, 1777 AMULLW, 1778 /* op $s[,r2],r3; op r1[,r2],r3; no cc/v */ 1779 ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */ 1780 ASTSW, 1781 ASLBMTE, 1782 AWORD, 1783 ADWORD, 1784 obj.ANOP, 1785 obj.ATEXT, 1786 obj.AUNDEF, 1787 obj.AFUNCDATA, 1788 obj.APCDATA, 1789 obj.ADUFFZERO, 1790 obj.ADUFFCOPY: 1791 break 1792 } 1793 } 1794 } 1795 1796 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 { 1797 return o<<26 | xo<<1 | oe<<11 1798 } 1799 1800 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 { 1801 return o<<26 | xo<<2 | oe<<11 1802 } 1803 1804 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 { 1805 return o<<26 | xo<<3 | oe<<11 1806 } 1807 1808 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 { 1809 return o<<26 | xo<<4 | oe<<11 1810 } 1811 1812 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1813 return o<<26 | xo | oe<<11 | rc&1 1814 } 1815 1816 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1817 return o<<26 | xo | oe<<11 | (rc&1)<<10 1818 } 1819 1820 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1821 return o<<26 | xo<<1 | oe<<10 | rc&1 1822 } 1823 1824 func OPCC(o uint32, xo uint32, rc uint32) uint32 { 1825 return OPVCC(o, xo, 0, rc) 1826 } 1827 1828 func OP(o uint32, xo uint32) uint32 { 1829 return OPVCC(o, xo, 0, 0) 1830 } 1831 1832 /* the order is dest, a/s, b/imm for both arithmetic and logical operations */ 1833 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 { 1834 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 1835 } 1836 1837 /* VX-form 2-register operands, r/none/r */ 1838 func AOP_RR(op uint32, d uint32, a uint32) uint32 { 1839 return op | (d&31)<<21 | (a&31)<<11 1840 } 1841 1842 /* VA-form 4-register operands */ 1843 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1844 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6 1845 } 1846 1847 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1848 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF 1849 } 1850 1851 /* VX-form 2-register + UIM operands */ 1852 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1853 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11 1854 } 1855 1856 /* VX-form 2-register + ST + SIX operands */ 1857 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 { 1858 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11 1859 } 1860 1861 /* VA-form 3-register + SHB operands */ 1862 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 { 1863 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6 1864 } 1865 1866 /* VX-form 1-register + SIM operands */ 1867 func AOP_IR(op uint32, d uint32, simm uint32) uint32 { 1868 return op | (d&31)<<21 | (simm&31)<<16 1869 } 1870 1871 /* XX1-form 3-register operands, 1 VSR operand */ 1872 func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32 { 1873 /* For the XX-form encodings, we need the VSX register number to be exactly */ 1874 /* between 0-63, so we can properly set the rightmost bits. */ 1875 r := d - REG_VS0 1876 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5 1877 } 1878 1879 /* XX2-form 3-register operands, 2 VSR operands */ 1880 func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32 { 1881 xt := d - REG_VS0 1882 xb := b - REG_VS0 1883 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5 1884 } 1885 1886 /* XX3-form 3 VSR operands */ 1887 func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32 { 1888 xt := d - REG_VS0 1889 xa := a - REG_VS0 1890 xb := b - REG_VS0 1891 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1892 } 1893 1894 /* XX3-form 3 VSR operands + immediate */ 1895 func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1896 xt := d - REG_VS0 1897 xa := a - REG_VS0 1898 xb := b - REG_VS0 1899 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1900 } 1901 1902 /* XX4-form, 4 VSR operands */ 1903 func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1904 xt := d - REG_VS0 1905 xa := a - REG_VS0 1906 xb := b - REG_VS0 1907 xc := c - REG_VS0 1908 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1909 } 1910 1911 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 { 1912 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11 1913 } 1914 1915 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 { 1916 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF 1917 } 1918 1919 func OP_BR(op uint32, li uint32, aa uint32) uint32 { 1920 return op | li&0x03FFFFFC | aa<<1 1921 } 1922 1923 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 { 1924 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1 1925 } 1926 1927 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 { 1928 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 1929 } 1930 1931 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 { 1932 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1 1933 } 1934 1935 func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 { 1936 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5 1937 } 1938 1939 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 { 1940 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6 1941 } 1942 1943 const ( 1944 /* each rhs is OPVCC(_, _, _, _) */ 1945 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0 1946 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0 1947 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0 1948 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0 1949 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0 1950 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0 1951 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0 1952 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0 1953 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0 1954 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0 1955 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0 1956 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0 1957 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0 1958 OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0 1959 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0 1960 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0 1961 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0 1962 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0 1963 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0 1964 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0 1965 OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0 1966 OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0 1967 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0 1968 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0 1969 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0 1970 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0 1971 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0 1972 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0 1973 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0 1974 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0 1975 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0 1976 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0 1977 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0 1978 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0 1979 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0 1980 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0 1981 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0 1982 ) 1983 1984 func oclass(a *obj.Addr) int { 1985 return int(a.Class) - 1 1986 } 1987 1988 const ( 1989 D_FORM = iota 1990 DS_FORM 1991 ) 1992 1993 // This function determines when a non-indexed load or store is D or 1994 // DS form for use in finding the size of the offset field in the instruction. 1995 // The size is needed when setting the offset value in the instruction 1996 // and when generating relocation for that field. 1997 // DS form instructions include: ld, ldu, lwa, std, stdu. All other 1998 // loads and stores with an offset field are D form. This function should 1999 // only be called with the same opcodes as are handled by opstore and opload. 2000 func (c *ctxt9) opform(insn uint32) int { 2001 switch insn { 2002 default: 2003 c.ctxt.Diag("bad insn in loadform: %x", insn) 2004 case OPVCC(58, 0, 0, 0), // ld 2005 OPVCC(58, 0, 0, 1), // ldu 2006 OPVCC(58, 0, 0, 0) | 1<<1, // lwa 2007 OPVCC(62, 0, 0, 0), // std 2008 OPVCC(62, 0, 0, 1): //stdu 2009 return DS_FORM 2010 case OP_ADDI, // add 2011 OPVCC(32, 0, 0, 0), // lwz 2012 OPVCC(33, 0, 0, 0), // lwzu 2013 OPVCC(34, 0, 0, 0), // lbz 2014 OPVCC(35, 0, 0, 0), // lbzu 2015 OPVCC(40, 0, 0, 0), // lhz 2016 OPVCC(41, 0, 0, 0), // lhzu 2017 OPVCC(42, 0, 0, 0), // lha 2018 OPVCC(43, 0, 0, 0), // lhau 2019 OPVCC(46, 0, 0, 0), // lmw 2020 OPVCC(48, 0, 0, 0), // lfs 2021 OPVCC(49, 0, 0, 0), // lfsu 2022 OPVCC(50, 0, 0, 0), // lfd 2023 OPVCC(51, 0, 0, 0), // lfdu 2024 OPVCC(36, 0, 0, 0), // stw 2025 OPVCC(37, 0, 0, 0), // stwu 2026 OPVCC(38, 0, 0, 0), // stb 2027 OPVCC(39, 0, 0, 0), // stbu 2028 OPVCC(44, 0, 0, 0), // sth 2029 OPVCC(45, 0, 0, 0), // sthu 2030 OPVCC(47, 0, 0, 0), // stmw 2031 OPVCC(52, 0, 0, 0), // stfs 2032 OPVCC(53, 0, 0, 0), // stfsu 2033 OPVCC(54, 0, 0, 0), // stfd 2034 OPVCC(55, 0, 0, 0): // stfdu 2035 return D_FORM 2036 } 2037 return 0 2038 } 2039 2040 // Encode instructions and create relocation for accessing s+d according to the 2041 // instruction op with source or destination (as appropriate) register reg. 2042 func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32) (o1, o2 uint32) { 2043 var base uint32 2044 form := c.opform(op) 2045 if c.ctxt.Flag_shared { 2046 base = REG_R2 2047 } else { 2048 base = REG_R0 2049 } 2050 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0) 2051 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0) 2052 rel := obj.Addrel(c.cursym) 2053 rel.Off = int32(c.pc) 2054 rel.Siz = 8 2055 rel.Sym = s 2056 rel.Add = d 2057 if c.ctxt.Flag_shared { 2058 switch form { 2059 case D_FORM: 2060 rel.Type = objabi.R_ADDRPOWER_TOCREL 2061 case DS_FORM: 2062 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS 2063 } 2064 2065 } else { 2066 switch form { 2067 case D_FORM: 2068 rel.Type = objabi.R_ADDRPOWER 2069 case DS_FORM: 2070 rel.Type = objabi.R_ADDRPOWER_DS 2071 } 2072 } 2073 return 2074 } 2075 2076 /* 2077 * 32-bit masks 2078 */ 2079 func getmask(m []byte, v uint32) bool { 2080 m[1] = 0 2081 m[0] = m[1] 2082 if v != ^uint32(0) && v&(1<<31) != 0 && v&1 != 0 { /* MB > ME */ 2083 if getmask(m, ^v) { 2084 i := int(m[0]) 2085 m[0] = m[1] + 1 2086 m[1] = byte(i - 1) 2087 return true 2088 } 2089 2090 return false 2091 } 2092 2093 for i := 0; i < 32; i++ { 2094 if v&(1<<uint(31-i)) != 0 { 2095 m[0] = byte(i) 2096 for { 2097 m[1] = byte(i) 2098 i++ 2099 if i >= 32 || v&(1<<uint(31-i)) == 0 { 2100 break 2101 } 2102 } 2103 2104 for ; i < 32; i++ { 2105 if v&(1<<uint(31-i)) != 0 { 2106 return false 2107 } 2108 } 2109 return true 2110 } 2111 } 2112 2113 return false 2114 } 2115 2116 func (c *ctxt9) maskgen(p *obj.Prog, m []byte, v uint32) { 2117 if !getmask(m, v) { 2118 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2119 } 2120 } 2121 2122 /* 2123 * 64-bit masks (rldic etc) 2124 */ 2125 func getmask64(m []byte, v uint64) bool { 2126 m[1] = 0 2127 m[0] = m[1] 2128 for i := 0; i < 64; i++ { 2129 if v&(uint64(1)<<uint(63-i)) != 0 { 2130 m[0] = byte(i) 2131 for { 2132 m[1] = byte(i) 2133 i++ 2134 if i >= 64 || v&(uint64(1)<<uint(63-i)) == 0 { 2135 break 2136 } 2137 } 2138 2139 for ; i < 64; i++ { 2140 if v&(uint64(1)<<uint(63-i)) != 0 { 2141 return false 2142 } 2143 } 2144 return true 2145 } 2146 } 2147 2148 return false 2149 } 2150 2151 func (c *ctxt9) maskgen64(p *obj.Prog, m []byte, v uint64) { 2152 if !getmask64(m, v) { 2153 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2154 } 2155 } 2156 2157 func loadu32(r int, d int64) uint32 { 2158 v := int32(d >> 16) 2159 if isuint32(uint64(d)) { 2160 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v)) 2161 } 2162 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v)) 2163 } 2164 2165 func high16adjusted(d int32) uint16 { 2166 if d&0x8000 != 0 { 2167 return uint16((d >> 16) + 1) 2168 } 2169 return uint16(d >> 16) 2170 } 2171 2172 func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) { 2173 o1 := uint32(0) 2174 o2 := uint32(0) 2175 o3 := uint32(0) 2176 o4 := uint32(0) 2177 o5 := uint32(0) 2178 2179 //print("%v => case %d\n", p, o->type); 2180 switch o.type_ { 2181 default: 2182 c.ctxt.Diag("unknown type %d", o.type_) 2183 prasm(p) 2184 2185 case 0: /* pseudo ops */ 2186 break 2187 2188 case 1: /* mov r1,r2 ==> OR Rs,Rs,Ra */ 2189 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2190 v := c.regoff(&p.From) 2191 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2192 //nerrors--; 2193 c.ctxt.Diag("literal operation on R0\n%v", p) 2194 } 2195 2196 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2197 break 2198 } 2199 2200 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg)) 2201 2202 case 2: /* int/cr/fp op Rb,[Ra],Rd */ 2203 r := int(p.Reg) 2204 2205 if r == 0 { 2206 r = int(p.To.Reg) 2207 } 2208 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2209 2210 case 3: /* mov $soreg/addcon/ucon, r ==> addis/addi $i,reg',r */ 2211 d := c.vregoff(&p.From) 2212 2213 v := int32(d) 2214 r := int(p.From.Reg) 2215 if r == 0 { 2216 r = int(o.param) 2217 } 2218 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) { 2219 c.ctxt.Diag("literal operation on R0\n%v", p) 2220 } 2221 a := OP_ADDI 2222 if o.a1 == C_UCON { 2223 if d&0xffff != 0 { 2224 log.Fatalf("invalid handling of %v", p) 2225 } 2226 v >>= 16 2227 if r == REGZERO && isuint32(uint64(d)) { 2228 o1 = LOP_IRR(OP_ORIS, uint32(p.To.Reg), REGZERO, uint32(v)) 2229 break 2230 } 2231 2232 a = OP_ADDIS 2233 } else { 2234 if int64(int16(d)) != d { 2235 log.Fatalf("invalid handling of %v", p) 2236 } 2237 } 2238 2239 o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v)) 2240 2241 case 4: /* add/mul $scon,[r1],r2 */ 2242 v := c.regoff(&p.From) 2243 2244 r := int(p.Reg) 2245 if r == 0 { 2246 r = int(p.To.Reg) 2247 } 2248 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 { 2249 c.ctxt.Diag("literal operation on R0\n%v", p) 2250 } 2251 if int32(int16(v)) != v { 2252 log.Fatalf("mishandled instruction %v", p) 2253 } 2254 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2255 2256 case 5: /* syscall */ 2257 o1 = c.oprrr(p.As) 2258 2259 case 6: /* logical op Rb,[Rs,]Ra; no literal */ 2260 r := int(p.Reg) 2261 2262 if r == 0 { 2263 r = int(p.To.Reg) 2264 } 2265 // AROTL and AROTLW are extended mnemonics, which map to RLDCL and RLWNM. 2266 switch p.As { 2267 case AROTL: 2268 o1 = AOP_RLDIC(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0)) 2269 case AROTLW: 2270 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31) 2271 default: 2272 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2273 } 2274 2275 case 7: /* mov r, soreg ==> stw o(r) */ 2276 r := int(p.To.Reg) 2277 2278 if r == 0 { 2279 r = int(o.param) 2280 } 2281 v := c.regoff(&p.To) 2282 if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 { 2283 if v != 0 { 2284 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2285 } 2286 if c.ctxt.Flag_shared && r == REG_R13 { 2287 rel := obj.Addrel(c.cursym) 2288 rel.Off = int32(c.pc) 2289 rel.Siz = 4 2290 // This (and the matching part in the load case 2291 // below) are the only places in the ppc64 toolchain 2292 // that knows the name of the tls variable. Possibly 2293 // we could add some assembly syntax so that the name 2294 // of the variable does not have to be assumed. 2295 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2296 rel.Type = objabi.R_POWER_TLS 2297 } 2298 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r)) 2299 } else { 2300 if int32(int16(v)) != v { 2301 log.Fatalf("mishandled instruction %v", p) 2302 } 2303 // Offsets in DS form stores must be a multiple of 4 2304 inst := c.opstore(p.As) 2305 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2306 log.Fatalf("invalid offset for DS form load/store %v", p) 2307 } 2308 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v)) 2309 } 2310 2311 case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r) */ 2312 r := int(p.From.Reg) 2313 2314 if r == 0 { 2315 r = int(o.param) 2316 } 2317 v := c.regoff(&p.From) 2318 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2319 if v != 0 { 2320 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2321 } 2322 if c.ctxt.Flag_shared && r == REG_R13 { 2323 rel := obj.Addrel(c.cursym) 2324 rel.Off = int32(c.pc) 2325 rel.Siz = 4 2326 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2327 rel.Type = objabi.R_POWER_TLS 2328 } 2329 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2330 } else { 2331 if int32(int16(v)) != v { 2332 log.Fatalf("mishandled instruction %v", p) 2333 } 2334 // Offsets in DS form loads must be a multiple of 4 2335 inst := c.opload(p.As) 2336 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2337 log.Fatalf("invalid offset for DS form load/store %v", p) 2338 } 2339 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v)) 2340 } 2341 2342 case 9: /* movb soreg, r ==> lbz o(r),r2; extsb r2,r2 */ 2343 r := int(p.From.Reg) 2344 2345 if r == 0 { 2346 r = int(o.param) 2347 } 2348 v := c.regoff(&p.From) 2349 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2350 if v != 0 { 2351 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2352 } 2353 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2354 } else { 2355 o1 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2356 } 2357 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2358 2359 case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */ 2360 r := int(p.Reg) 2361 2362 if r == 0 { 2363 r = int(p.To.Reg) 2364 } 2365 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r)) 2366 2367 case 11: /* br/bl lbra */ 2368 v := int32(0) 2369 2370 if p.Pcond != nil { 2371 v = int32(p.Pcond.Pc - p.Pc) 2372 if v&03 != 0 { 2373 c.ctxt.Diag("odd branch target address\n%v", p) 2374 v &^= 03 2375 } 2376 2377 if v < -(1<<25) || v >= 1<<24 { 2378 c.ctxt.Diag("branch too far\n%v", p) 2379 } 2380 } 2381 2382 o1 = OP_BR(c.opirr(p.As), uint32(v), 0) 2383 if p.To.Sym != nil { 2384 rel := obj.Addrel(c.cursym) 2385 rel.Off = int32(c.pc) 2386 rel.Siz = 4 2387 rel.Sym = p.To.Sym 2388 v += int32(p.To.Offset) 2389 if v&03 != 0 { 2390 c.ctxt.Diag("odd branch target address\n%v", p) 2391 v &^= 03 2392 } 2393 2394 rel.Add = int64(v) 2395 rel.Type = objabi.R_CALLPOWER 2396 } 2397 o2 = 0x60000000 // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking 2398 2399 case 12: /* movb r,r (extsb); movw r,r (extsw) */ 2400 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2401 v := c.regoff(&p.From) 2402 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2403 c.ctxt.Diag("literal operation on R0\n%v", p) 2404 } 2405 2406 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2407 break 2408 } 2409 2410 if p.As == AMOVW { 2411 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2412 } else { 2413 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2414 } 2415 2416 case 13: /* mov[bhw]z r,r; uses rlwinm not andi. to avoid changing CC */ 2417 if p.As == AMOVBZ { 2418 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31) 2419 } else if p.As == AMOVH { 2420 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2421 } else if p.As == AMOVHZ { 2422 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31) 2423 } else if p.As == AMOVWZ { 2424 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */ 2425 } else { 2426 c.ctxt.Diag("internal: bad mov[bhw]z\n%v", p) 2427 } 2428 2429 case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */ 2430 r := int(p.Reg) 2431 2432 if r == 0 { 2433 r = int(p.To.Reg) 2434 } 2435 d := c.vregoff(p.From3) 2436 var a int 2437 switch p.As { 2438 2439 // These opcodes expect a mask operand that has to be converted into the 2440 // appropriate operand. The way these were defined, not all valid masks are possible. 2441 // Left here for compatibility in case they were used or generated. 2442 case ARLDCL, ARLDCLCC: 2443 var mask [2]uint8 2444 c.maskgen64(p, mask[:], uint64(d)) 2445 2446 a = int(mask[0]) /* MB */ 2447 if mask[1] != 63 { 2448 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p) 2449 } 2450 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2451 o1 |= (uint32(a) & 31) << 6 2452 if a&0x20 != 0 { 2453 o1 |= 1 << 5 /* mb[5] is top bit */ 2454 } 2455 2456 case ARLDCR, ARLDCRCC: 2457 var mask [2]uint8 2458 c.maskgen64(p, mask[:], uint64(d)) 2459 2460 a = int(mask[1]) /* ME */ 2461 if mask[0] != 0 { 2462 c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p) 2463 } 2464 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2465 o1 |= (uint32(a) & 31) << 6 2466 if a&0x20 != 0 { 2467 o1 |= 1 << 5 /* mb[5] is top bit */ 2468 } 2469 2470 // These opcodes use a shift count like the ppc64 asm, no mask conversion done 2471 case ARLDICR, ARLDICRCC: 2472 me := int(d) 2473 sh := c.regoff(&p.From) 2474 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me)) 2475 2476 case ARLDICL, ARLDICLCC: 2477 mb := int(d) 2478 sh := c.regoff(&p.From) 2479 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb)) 2480 2481 default: 2482 c.ctxt.Diag("unexpected op in rldc case\n%v", p) 2483 a = 0 2484 } 2485 2486 case 17, /* bc bo,bi,lbra (same for now) */ 2487 16: /* bc bo,bi,sbra */ 2488 a := 0 2489 2490 r := int(p.Reg) 2491 2492 if p.From.Type == obj.TYPE_CONST { 2493 a = int(c.regoff(&p.From)) 2494 } else if p.From.Type == obj.TYPE_REG { 2495 if r != 0 { 2496 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r) 2497 } 2498 // BI values for the CR 2499 switch p.From.Reg { 2500 case REG_CR0: 2501 r = BI_CR0 2502 case REG_CR1: 2503 r = BI_CR1 2504 case REG_CR2: 2505 r = BI_CR2 2506 case REG_CR3: 2507 r = BI_CR3 2508 case REG_CR4: 2509 r = BI_CR4 2510 case REG_CR5: 2511 r = BI_CR5 2512 case REG_CR6: 2513 r = BI_CR6 2514 case REG_CR7: 2515 r = BI_CR7 2516 default: 2517 c.ctxt.Diag("unrecognized register: expecting CR\n") 2518 } 2519 } 2520 v := int32(0) 2521 if p.Pcond != nil { 2522 v = int32(p.Pcond.Pc - p.Pc) 2523 } 2524 if v&03 != 0 { 2525 c.ctxt.Diag("odd branch target address\n%v", p) 2526 v &^= 03 2527 } 2528 2529 if v < -(1<<16) || v >= 1<<15 { 2530 c.ctxt.Diag("branch too far\n%v", p) 2531 } 2532 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0) 2533 2534 case 15: /* br/bl (r) => mov r,lr; br/bl (lr) */ 2535 var v int32 2536 if p.As == ABC || p.As == ABCL { 2537 v = c.regoff(&p.To) & 31 2538 } else { 2539 v = 20 /* unconditional */ 2540 } 2541 o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11 2542 o2 = OPVCC(19, 16, 0, 0) 2543 if p.As == ABL || p.As == ABCL { 2544 o2 |= 1 2545 } 2546 o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index)) 2547 2548 case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */ 2549 var v int32 2550 if p.As == ABC || p.As == ABCL { 2551 v = c.regoff(&p.From) & 31 2552 } else { 2553 v = 20 /* unconditional */ 2554 } 2555 r := int(p.Reg) 2556 if r == 0 { 2557 r = 0 2558 } 2559 switch oclass(&p.To) { 2560 case C_CTR: 2561 o1 = OPVCC(19, 528, 0, 0) 2562 2563 case C_LR: 2564 o1 = OPVCC(19, 16, 0, 0) 2565 2566 default: 2567 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p) 2568 v = 0 2569 } 2570 2571 if p.As == ABL || p.As == ABCL { 2572 o1 |= 1 2573 } 2574 o1 = OP_BCR(o1, uint32(v), uint32(r)) 2575 2576 case 19: /* mov $lcon,r ==> cau+or */ 2577 d := c.vregoff(&p.From) 2578 2579 if p.From.Sym == nil { 2580 o1 = loadu32(int(p.To.Reg), d) 2581 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d))) 2582 } else { 2583 o1, o2 = c.symbolAccess(p.From.Sym, d, p.To.Reg, OP_ADDI) 2584 } 2585 2586 //if(dlm) reloc(&p->from, p->pc, 0); 2587 2588 case 20: /* add $ucon,,r */ 2589 v := c.regoff(&p.From) 2590 2591 r := int(p.Reg) 2592 if r == 0 { 2593 r = int(p.To.Reg) 2594 } 2595 if p.As == AADD && (r0iszero == 0 /*TypeKind(100016)*/ && p.Reg == 0 || r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0) { 2596 c.ctxt.Diag("literal operation on R0\n%v", p) 2597 } 2598 o1 = AOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) 2599 2600 case 22: /* add $lcon,r1,r2 ==> cau+or+add */ /* could do add/sub more efficiently */ 2601 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2602 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2603 } 2604 d := c.vregoff(&p.From) 2605 o1 = loadu32(REGTMP, d) 2606 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2607 r := int(p.Reg) 2608 if r == 0 { 2609 r = int(p.To.Reg) 2610 } 2611 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2612 if p.From.Sym != nil { 2613 c.ctxt.Diag("%v is not supported", p) 2614 } 2615 2616 //if(dlm) reloc(&p->from, p->pc, 0); 2617 2618 case 23: /* and $lcon,r1,r2 ==> cau+or+and */ /* masks could be done using rlnm etc. */ 2619 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2620 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2621 } 2622 d := c.vregoff(&p.From) 2623 o1 = loadu32(REGTMP, d) 2624 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2625 r := int(p.Reg) 2626 if r == 0 { 2627 r = int(p.To.Reg) 2628 } 2629 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2630 if p.From.Sym != nil { 2631 c.ctxt.Diag("%v is not supported", p) 2632 } 2633 2634 //if(dlm) reloc(&p->from, p->pc, 0); 2635 2636 /*24*/ 2637 case 25: 2638 /* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */ 2639 v := c.regoff(&p.From) 2640 2641 if v < 0 { 2642 v = 0 2643 } else if v > 63 { 2644 v = 63 2645 } 2646 r := int(p.Reg) 2647 if r == 0 { 2648 r = int(p.To.Reg) 2649 } 2650 var a int 2651 op := uint32(0) 2652 switch p.As { 2653 case ASLD, ASLDCC: 2654 a = int(63 - v) 2655 op = OP_RLDICR 2656 2657 case ASRD, ASRDCC: 2658 a = int(v) 2659 v = 64 - v 2660 op = OP_RLDICL 2661 case AROTL: 2662 a = int(0) 2663 op = OP_RLDICL 2664 default: 2665 c.ctxt.Diag("unexpected op in sldi case\n%v", p) 2666 a = 0 2667 o1 = 0 2668 } 2669 2670 o1 = AOP_RLDIC(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a)) 2671 if p.As == ASLDCC || p.As == ASRDCC { 2672 o1 |= 1 // Set the condition code bit 2673 } 2674 2675 case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */ 2676 if p.To.Reg == REGTMP { 2677 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2678 } 2679 v := c.regoff(&p.From) 2680 r := int(p.From.Reg) 2681 if r == 0 { 2682 r = int(o.param) 2683 } 2684 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2685 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGTMP, uint32(v)) 2686 2687 case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */ 2688 v := c.regoff(p.From3) 2689 2690 r := int(p.From.Reg) 2691 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2692 2693 case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */ 2694 if p.To.Reg == REGTMP || p.From.Reg == REGTMP { 2695 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2696 } 2697 v := c.regoff(p.From3) 2698 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16) 2699 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(v)) 2700 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP) 2701 if p.From.Sym != nil { 2702 c.ctxt.Diag("%v is not supported", p) 2703 } 2704 2705 //if(dlm) reloc(&p->from3, p->pc, 0); 2706 2707 case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */ 2708 v := c.regoff(&p.From) 2709 2710 d := c.vregoff(p.From3) 2711 var mask [2]uint8 2712 c.maskgen64(p, mask[:], uint64(d)) 2713 var a int 2714 switch p.As { 2715 case ARLDC, ARLDCCC: 2716 a = int(mask[0]) /* MB */ 2717 if int32(mask[1]) != (63 - v) { 2718 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2719 } 2720 2721 case ARLDCL, ARLDCLCC: 2722 a = int(mask[0]) /* MB */ 2723 if mask[1] != 63 { 2724 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2725 } 2726 2727 case ARLDCR, ARLDCRCC: 2728 a = int(mask[1]) /* ME */ 2729 if mask[0] != 0 { 2730 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2731 } 2732 2733 default: 2734 c.ctxt.Diag("unexpected op in rldic case\n%v", p) 2735 a = 0 2736 } 2737 2738 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2739 o1 |= (uint32(a) & 31) << 6 2740 if v&0x20 != 0 { 2741 o1 |= 1 << 1 2742 } 2743 if a&0x20 != 0 { 2744 o1 |= 1 << 5 /* mb[5] is top bit */ 2745 } 2746 2747 case 30: /* rldimi $sh,s,$mask,a */ 2748 v := c.regoff(&p.From) 2749 2750 d := c.vregoff(p.From3) 2751 2752 // Original opcodes had mask operands which had to be converted to a shift count as expected by 2753 // the ppc64 asm. 2754 switch p.As { 2755 case ARLDMI, ARLDMICC: 2756 var mask [2]uint8 2757 c.maskgen64(p, mask[:], uint64(d)) 2758 if int32(mask[1]) != (63 - v) { 2759 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2760 } 2761 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2762 o1 |= (uint32(mask[0]) & 31) << 6 2763 if v&0x20 != 0 { 2764 o1 |= 1 << 1 2765 } 2766 if mask[0]&0x20 != 0 { 2767 o1 |= 1 << 5 /* mb[5] is top bit */ 2768 } 2769 2770 // Opcodes with shift count operands. 2771 case ARLDIMI, ARLDIMICC: 2772 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2773 o1 |= (uint32(d) & 31) << 6 2774 if d&0x20 != 0 { 2775 o1 |= 1 << 5 2776 } 2777 if v&0x20 != 0 { 2778 o1 |= 1 << 1 2779 } 2780 } 2781 2782 case 31: /* dword */ 2783 d := c.vregoff(&p.From) 2784 2785 if c.ctxt.Arch.ByteOrder == binary.BigEndian { 2786 o1 = uint32(d >> 32) 2787 o2 = uint32(d) 2788 } else { 2789 o1 = uint32(d) 2790 o2 = uint32(d >> 32) 2791 } 2792 2793 if p.From.Sym != nil { 2794 rel := obj.Addrel(c.cursym) 2795 rel.Off = int32(c.pc) 2796 rel.Siz = 8 2797 rel.Sym = p.From.Sym 2798 rel.Add = p.From.Offset 2799 rel.Type = objabi.R_ADDR 2800 o2 = 0 2801 o1 = o2 2802 } 2803 2804 case 32: /* fmul frc,fra,frd */ 2805 r := int(p.Reg) 2806 2807 if r == 0 { 2808 r = int(p.To.Reg) 2809 } 2810 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6 2811 2812 case 33: /* fabs [frb,]frd; fmr. frb,frd */ 2813 r := int(p.From.Reg) 2814 2815 if oclass(&p.From) == C_NONE { 2816 r = int(p.To.Reg) 2817 } 2818 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r)) 2819 2820 case 34: /* FMADDx fra,frb,frc,frt (t=a*c±b) */ 2821 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.From3.Reg)&31)<<6 2822 2823 case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */ 2824 v := c.regoff(&p.To) 2825 2826 r := int(p.To.Reg) 2827 if r == 0 { 2828 r = int(o.param) 2829 } 2830 // Offsets in DS form stores must be a multiple of 4 2831 inst := c.opstore(p.As) 2832 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2833 log.Fatalf("invalid offset for DS form load/store %v", p) 2834 } 2835 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2836 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v)) 2837 2838 case 36: /* mov bz/h/hz lext/lauto/lreg,r ==> lbz/lha/lhz etc */ 2839 v := c.regoff(&p.From) 2840 2841 r := int(p.From.Reg) 2842 if r == 0 { 2843 r = int(o.param) 2844 } 2845 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2846 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2847 2848 case 37: /* movb lext/lauto/lreg,r ==> lbz o(reg),r; extsb r */ 2849 v := c.regoff(&p.From) 2850 2851 r := int(p.From.Reg) 2852 if r == 0 { 2853 r = int(o.param) 2854 } 2855 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2856 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2857 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2858 2859 case 40: /* word */ 2860 o1 = uint32(c.regoff(&p.From)) 2861 2862 case 41: /* stswi */ 2863 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.From3))&0x7F)<<11 2864 2865 case 42: /* lswi */ 2866 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.From3))&0x7F)<<11 2867 2868 case 43: /* unary indexed source: dcbf (b); dcbf (a+b) */ 2869 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg)) 2870 2871 case 44: /* indexed store */ 2872 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 2873 2874 case 45: /* indexed load */ 2875 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 2876 2877 case 46: /* plain op */ 2878 o1 = c.oprrr(p.As) 2879 2880 case 47: /* op Ra, Rd; also op [Ra,] Rd */ 2881 r := int(p.From.Reg) 2882 2883 if r == 0 { 2884 r = int(p.To.Reg) 2885 } 2886 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2887 2888 case 48: /* op Rs, Ra */ 2889 r := int(p.From.Reg) 2890 2891 if r == 0 { 2892 r = int(p.To.Reg) 2893 } 2894 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2895 2896 case 49: /* op Rb; op $n, Rb */ 2897 if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */ 2898 v := c.regoff(&p.From) & 1 2899 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21 2900 } else { 2901 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg)) 2902 } 2903 2904 case 50: /* rem[u] r1[,r2],r3 */ 2905 r := int(p.Reg) 2906 2907 if r == 0 { 2908 r = int(p.To.Reg) 2909 } 2910 v := c.oprrr(p.As) 2911 t := v & (1<<10 | 1) /* OE|Rc */ 2912 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2913 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg)) 2914 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2915 if p.As == AREMU { 2916 o4 = o3 2917 2918 /* Clear top 32 bits */ 2919 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5 2920 } 2921 2922 case 51: /* remd[u] r1[,r2],r3 */ 2923 r := int(p.Reg) 2924 2925 if r == 0 { 2926 r = int(p.To.Reg) 2927 } 2928 v := c.oprrr(p.As) 2929 t := v & (1<<10 | 1) /* OE|Rc */ 2930 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2931 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg)) 2932 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2933 2934 case 52: /* mtfsbNx cr(n) */ 2935 v := c.regoff(&p.From) & 31 2936 2937 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0) 2938 2939 case 53: /* mffsX ,fr1 */ 2940 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0) 2941 2942 case 54: /* mov msr,r1; mov r1, msr*/ 2943 if oclass(&p.From) == C_REG { 2944 if p.As == AMOVD { 2945 o1 = AOP_RRR(OP_MTMSRD, uint32(p.From.Reg), 0, 0) 2946 } else { 2947 o1 = AOP_RRR(OP_MTMSR, uint32(p.From.Reg), 0, 0) 2948 } 2949 } else { 2950 o1 = AOP_RRR(OP_MFMSR, uint32(p.To.Reg), 0, 0) 2951 } 2952 2953 case 55: /* op Rb, Rd */ 2954 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg)) 2955 2956 case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */ 2957 v := c.regoff(&p.From) 2958 2959 r := int(p.Reg) 2960 if r == 0 { 2961 r = int(p.To.Reg) 2962 } 2963 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31) 2964 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) { 2965 o1 |= 1 << 1 /* mb[5] */ 2966 } 2967 2968 case 57: /* slw $sh,[s,]a -> rlwinm ... */ 2969 v := c.regoff(&p.From) 2970 2971 r := int(p.Reg) 2972 if r == 0 { 2973 r = int(p.To.Reg) 2974 } 2975 2976 /* 2977 * Let user (gs) shoot himself in the foot. 2978 * qc has already complained. 2979 * 2980 if(v < 0 || v > 31) 2981 ctxt->diag("illegal shift %ld\n%v", v, p); 2982 */ 2983 if v < 0 { 2984 v = 0 2985 } else if v > 32 { 2986 v = 32 2987 } 2988 var mask [2]uint8 2989 switch p.As { 2990 case AROTLW: 2991 mask[0], mask[1] = 0, 31 2992 case ASRW, ASRWCC: 2993 mask[0], mask[1] = uint8(v), 31 2994 v = 32 - v 2995 default: 2996 mask[0], mask[1] = 0, uint8(31-v) 2997 } 2998 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1])) 2999 if p.As == ASLWCC || p.As == ASRWCC { 3000 o1 |= 1 // set the condition code 3001 } 3002 3003 case 58: /* logical $andcon,[s],a */ 3004 v := c.regoff(&p.From) 3005 3006 r := int(p.Reg) 3007 if r == 0 { 3008 r = int(p.To.Reg) 3009 } 3010 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 3011 3012 case 59: /* or/and $ucon,,r */ 3013 v := c.regoff(&p.From) 3014 3015 r := int(p.Reg) 3016 if r == 0 { 3017 r = int(p.To.Reg) 3018 } 3019 o1 = LOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) /* oris, xoris, andis */ 3020 3021 case 60: /* tw to,a,b */ 3022 r := int(c.regoff(&p.From) & 31) 3023 3024 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg)) 3025 3026 case 61: /* tw to,a,$simm */ 3027 r := int(c.regoff(&p.From) & 31) 3028 3029 v := c.regoff(&p.To) 3030 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v)) 3031 3032 case 62: /* rlwmi $sh,s,$mask,a */ 3033 v := c.regoff(&p.From) 3034 3035 var mask [2]uint8 3036 c.maskgen(p, mask[:], uint32(c.regoff(p.From3))) 3037 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v)) 3038 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3039 3040 case 63: /* rlwmi b,s,$mask,a */ 3041 var mask [2]uint8 3042 c.maskgen(p, mask[:], uint32(c.regoff(p.From3))) 3043 3044 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg)) 3045 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3046 3047 case 64: /* mtfsf fr[, $m] {,fpcsr} */ 3048 var v int32 3049 if p.From3Type() != obj.TYPE_NONE { 3050 v = c.regoff(p.From3) & 255 3051 } else { 3052 v = 255 3053 } 3054 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11 3055 3056 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */ 3057 if p.To.Reg == 0 { 3058 c.ctxt.Diag("must specify FPSCR(n)\n%v", p) 3059 } 3060 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12 3061 3062 case 66: /* mov spr,r1; mov r1,spr, also dcr */ 3063 var r int 3064 var v int32 3065 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 { 3066 r = int(p.From.Reg) 3067 v = int32(p.To.Reg) 3068 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3069 o1 = OPVCC(31, 451, 0, 0) /* mtdcr */ 3070 } else { 3071 o1 = OPVCC(31, 467, 0, 0) /* mtspr */ 3072 } 3073 } else { 3074 r = int(p.To.Reg) 3075 v = int32(p.From.Reg) 3076 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3077 o1 = OPVCC(31, 323, 0, 0) /* mfdcr */ 3078 } else { 3079 o1 = OPVCC(31, 339, 0, 0) /* mfspr */ 3080 } 3081 } 3082 3083 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11 3084 3085 case 67: /* mcrf crfD,crfS */ 3086 if p.From.Type != obj.TYPE_REG || p.From.Reg < REG_CR0 || REG_CR7 < p.From.Reg || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3087 c.ctxt.Diag("illegal CR field number\n%v", p) 3088 } 3089 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0) 3090 3091 case 68: /* mfcr rD; mfocrf CRM,rD */ 3092 if p.From.Type == obj.TYPE_REG && REG_CR0 <= p.From.Reg && p.From.Reg <= REG_CR7 { 3093 v := int32(1 << uint(7-(p.To.Reg&7))) /* CR(n) */ 3094 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) | 1<<20 | uint32(v)<<12 /* new form, mfocrf */ 3095 } else { 3096 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /* old form, whole register */ 3097 } 3098 3099 case 69: /* mtcrf CRM,rS */ 3100 var v int32 3101 if p.From3Type() != obj.TYPE_NONE { 3102 if p.To.Reg != 0 { 3103 c.ctxt.Diag("can't use both mask and CR(n)\n%v", p) 3104 } 3105 v = c.regoff(p.From3) & 0xff 3106 } else { 3107 if p.To.Reg == 0 { 3108 v = 0xff /* CR */ 3109 } else { 3110 v = 1 << uint(7-(p.To.Reg&7)) /* CR(n) */ 3111 } 3112 } 3113 3114 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12 3115 3116 case 70: /* [f]cmp r,r,cr*/ 3117 var r int 3118 if p.Reg == 0 { 3119 r = 0 3120 } else { 3121 r = (int(p.Reg) & 7) << 2 3122 } 3123 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg)) 3124 3125 case 71: /* cmp[l] r,i,cr*/ 3126 var r int 3127 if p.Reg == 0 { 3128 r = 0 3129 } else { 3130 r = (int(p.Reg) & 7) << 2 3131 } 3132 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(c.regoff(&p.To))&0xffff 3133 3134 case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */ 3135 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg)) 3136 3137 case 73: /* mcrfs crfD,crfS */ 3138 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3139 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p) 3140 } 3141 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0) 3142 3143 case 77: /* syscall $scon, syscall Rx */ 3144 if p.From.Type == obj.TYPE_CONST { 3145 if p.From.Offset > BIG || p.From.Offset < -BIG { 3146 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p) 3147 } 3148 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset)) 3149 } else if p.From.Type == obj.TYPE_REG { 3150 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg)) 3151 } else { 3152 c.ctxt.Diag("illegal syscall: %v", p) 3153 o1 = 0x7fe00008 // trap always 3154 } 3155 3156 o2 = c.oprrr(p.As) 3157 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0 3158 3159 case 78: /* undef */ 3160 o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed 3161 always to be an illegal instruction." */ 3162 3163 /* relocation operations */ 3164 case 74: 3165 v := c.vregoff(&p.To) 3166 // Offsets in DS form stores must be a multiple of 4 3167 inst := c.opstore(p.As) 3168 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3169 log.Fatalf("invalid offset for DS form load/store %v", p) 3170 } 3171 o1, o2 = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst) 3172 3173 //if(dlm) reloc(&p->to, p->pc, 1); 3174 3175 case 75: 3176 v := c.vregoff(&p.From) 3177 // Offsets in DS form loads must be a multiple of 4 3178 inst := c.opload(p.As) 3179 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3180 log.Fatalf("invalid offset for DS form load/store %v", p) 3181 } 3182 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3183 3184 //if(dlm) reloc(&p->from, p->pc, 1); 3185 3186 case 76: 3187 v := c.vregoff(&p.From) 3188 // Offsets in DS form loads must be a multiple of 4 3189 inst := c.opload(p.As) 3190 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3191 log.Fatalf("invalid offset for DS form load/store %v", p) 3192 } 3193 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3194 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 3195 3196 //if(dlm) reloc(&p->from, p->pc, 1); 3197 3198 case 79: 3199 if p.From.Offset != 0 { 3200 c.ctxt.Diag("invalid offset against tls var %v", p) 3201 } 3202 o1 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGZERO, 0) 3203 rel := obj.Addrel(c.cursym) 3204 rel.Off = int32(c.pc) 3205 rel.Siz = 4 3206 rel.Sym = p.From.Sym 3207 rel.Type = objabi.R_POWER_TLS_LE 3208 3209 case 80: 3210 if p.From.Offset != 0 { 3211 c.ctxt.Diag("invalid offset against tls var %v", p) 3212 } 3213 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3214 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3215 rel := obj.Addrel(c.cursym) 3216 rel.Off = int32(c.pc) 3217 rel.Siz = 8 3218 rel.Sym = p.From.Sym 3219 rel.Type = objabi.R_POWER_TLS_IE 3220 3221 case 81: 3222 v := c.vregoff(&p.To) 3223 if v != 0 { 3224 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3225 } 3226 3227 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3228 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3229 rel := obj.Addrel(c.cursym) 3230 rel.Off = int32(c.pc) 3231 rel.Siz = 8 3232 rel.Sym = p.From.Sym 3233 rel.Type = objabi.R_ADDRPOWER_GOT 3234 case 82: /* vector instructions, VX-form and VC-form */ 3235 if p.From.Type == obj.TYPE_REG { 3236 /* reg reg none OR reg reg reg */ 3237 /* 3-register operand order: VRA, VRB, VRT */ 3238 /* 2-register operand order: VRA, VRT */ 3239 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3240 } else if p.From3Type() == obj.TYPE_CONST { 3241 /* imm imm reg reg */ 3242 /* operand order: SIX, VRA, ST, VRT */ 3243 six := int(c.regoff(&p.From)) 3244 st := int(c.regoff(p.From3)) 3245 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six)) 3246 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 { 3247 /* imm reg reg */ 3248 /* operand order: UIM, VRB, VRT */ 3249 uim := int(c.regoff(&p.From)) 3250 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim)) 3251 } else { 3252 /* imm reg */ 3253 /* operand order: SIM, VRT */ 3254 sim := int(c.regoff(&p.From)) 3255 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim)) 3256 } 3257 3258 case 83: /* vector instructions, VA-form */ 3259 if p.From.Type == obj.TYPE_REG { 3260 /* reg reg reg reg */ 3261 /* 4-register operand order: VRA, VRB, VRC, VRT */ 3262 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.From3.Reg)) 3263 } else if p.From.Type == obj.TYPE_CONST { 3264 /* imm reg reg reg */ 3265 /* operand order: SHB, VRA, VRB, VRT */ 3266 shb := int(c.regoff(&p.From)) 3267 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), uint32(shb)) 3268 } 3269 3270 case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc 3271 bc := c.vregoff(&p.From) 3272 3273 // rt = To.Reg, ra = p.Reg, rb = p.From3.Reg 3274 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), uint32(bc)) 3275 3276 case 85: /* vector instructions, VX-form */ 3277 /* reg none reg */ 3278 /* 2-register operand order: VRB, VRT */ 3279 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg)) 3280 3281 case 86: /* VSX indexed store, XX1-form */ 3282 /* reg reg reg */ 3283 /* 3-register operand order: XT, (RB)(RA*1) */ 3284 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 3285 3286 case 87: /* VSX indexed load, XX1-form */ 3287 /* reg reg reg */ 3288 /* 3-register operand order: (RB)(RA*1), XT */ 3289 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 3290 3291 case 88: /* VSX instructions, XX1-form */ 3292 /* reg reg none OR reg reg reg */ 3293 /* 3-register operand order: RA, RB, XT */ 3294 /* 2-register operand order: XS, RA or RA, XT */ 3295 xt := int32(p.To.Reg) 3296 xs := int32(p.From.Reg) 3297 /* We need to treat the special case of extended mnemonics that may have a FREG/VREG as an argument */ 3298 if REG_V0 <= xt && xt <= REG_V31 { 3299 /* Convert V0-V31 to VS32-VS63 */ 3300 xt = xt + 64 3301 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3302 } else if REG_F0 <= xt && xt <= REG_F31 { 3303 /* Convert F0-F31 to VS0-VS31 */ 3304 xt = xt + 64 3305 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3306 } else if REG_VS0 <= xt && xt <= REG_VS63 { 3307 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3308 } else if REG_V0 <= xs && xs <= REG_V31 { 3309 /* Likewise for XS */ 3310 xs = xs + 64 3311 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3312 } else if REG_F0 <= xs && xs <= REG_F31 { 3313 xs = xs + 64 3314 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3315 } else if REG_VS0 <= xs && xs <= REG_VS63 { 3316 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3317 } 3318 3319 case 89: /* VSX instructions, XX2-form */ 3320 /* reg none reg OR reg imm reg */ 3321 /* 2-register operand order: XB, XT or XB, UIM, XT*/ 3322 uim := int(c.regoff(p.From3)) 3323 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg)) 3324 3325 case 90: /* VSX instructions, XX3-form */ 3326 if p.From3Type() == obj.TYPE_NONE { 3327 /* reg reg reg */ 3328 /* 3-register operand order: XA, XB, XT */ 3329 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3330 } else if p.From3Type() == obj.TYPE_CONST { 3331 /* reg reg reg imm */ 3332 /* operand order: XA, XB, DM, XT */ 3333 dm := int(c.regoff(p.From3)) 3334 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm)) 3335 } 3336 3337 case 91: /* VSX instructions, XX4-form */ 3338 /* reg reg reg reg */ 3339 /* 3-register operand order: XA, XB, XC, XT */ 3340 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.From3.Reg)) 3341 3342 case 92: /* X-form instructions, 3-operands */ 3343 if p.To.Type == obj.TYPE_CONST { 3344 /* imm reg reg */ 3345 /* operand order: FRA, FRB, BF */ 3346 bf := int(c.regoff(&p.To)) << 2 3347 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3348 } else if p.To.Type == obj.TYPE_REG { 3349 /* reg reg reg */ 3350 /* operand order: RS, RB, RA */ 3351 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3352 } 3353 3354 case 93: /* X-form instructions, 2-operands */ 3355 if p.To.Type == obj.TYPE_CONST { 3356 /* imm reg */ 3357 /* operand order: FRB, BF */ 3358 bf := int(c.regoff(&p.To)) << 2 3359 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg)) 3360 } else if p.Reg == 0 { 3361 /* popcnt* r,r, X-form */ 3362 /* operand order: RS, RA */ 3363 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3364 } 3365 3366 } 3367 3368 out[0] = o1 3369 out[1] = o2 3370 out[2] = o3 3371 out[3] = o4 3372 out[4] = o5 3373 return 3374 } 3375 3376 func (c *ctxt9) vregoff(a *obj.Addr) int64 { 3377 c.instoffset = 0 3378 if a != nil { 3379 c.aclass(a) 3380 } 3381 return c.instoffset 3382 } 3383 3384 func (c *ctxt9) regoff(a *obj.Addr) int32 { 3385 return int32(c.vregoff(a)) 3386 } 3387 3388 func (c *ctxt9) oprrr(a obj.As) uint32 { 3389 switch a { 3390 case AADD: 3391 return OPVCC(31, 266, 0, 0) 3392 case AADDCC: 3393 return OPVCC(31, 266, 0, 1) 3394 case AADDV: 3395 return OPVCC(31, 266, 1, 0) 3396 case AADDVCC: 3397 return OPVCC(31, 266, 1, 1) 3398 case AADDC: 3399 return OPVCC(31, 10, 0, 0) 3400 case AADDCCC: 3401 return OPVCC(31, 10, 0, 1) 3402 case AADDCV: 3403 return OPVCC(31, 10, 1, 0) 3404 case AADDCVCC: 3405 return OPVCC(31, 10, 1, 1) 3406 case AADDE: 3407 return OPVCC(31, 138, 0, 0) 3408 case AADDECC: 3409 return OPVCC(31, 138, 0, 1) 3410 case AADDEV: 3411 return OPVCC(31, 138, 1, 0) 3412 case AADDEVCC: 3413 return OPVCC(31, 138, 1, 1) 3414 case AADDME: 3415 return OPVCC(31, 234, 0, 0) 3416 case AADDMECC: 3417 return OPVCC(31, 234, 0, 1) 3418 case AADDMEV: 3419 return OPVCC(31, 234, 1, 0) 3420 case AADDMEVCC: 3421 return OPVCC(31, 234, 1, 1) 3422 case AADDZE: 3423 return OPVCC(31, 202, 0, 0) 3424 case AADDZECC: 3425 return OPVCC(31, 202, 0, 1) 3426 case AADDZEV: 3427 return OPVCC(31, 202, 1, 0) 3428 case AADDZEVCC: 3429 return OPVCC(31, 202, 1, 1) 3430 3431 case AAND: 3432 return OPVCC(31, 28, 0, 0) 3433 case AANDCC: 3434 return OPVCC(31, 28, 0, 1) 3435 case AANDN: 3436 return OPVCC(31, 60, 0, 0) 3437 case AANDNCC: 3438 return OPVCC(31, 60, 0, 1) 3439 3440 case ACMP: 3441 return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */ 3442 case ACMPU: 3443 return OPVCC(31, 32, 0, 0) | 1<<21 3444 case ACMPW: 3445 return OPVCC(31, 0, 0, 0) /* L=0 */ 3446 case ACMPWU: 3447 return OPVCC(31, 32, 0, 0) 3448 case ACMPB: 3449 return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */ 3450 3451 case ACNTLZW: 3452 return OPVCC(31, 26, 0, 0) 3453 case ACNTLZWCC: 3454 return OPVCC(31, 26, 0, 1) 3455 case ACNTLZD: 3456 return OPVCC(31, 58, 0, 0) 3457 case ACNTLZDCC: 3458 return OPVCC(31, 58, 0, 1) 3459 3460 case ACRAND: 3461 return OPVCC(19, 257, 0, 0) 3462 case ACRANDN: 3463 return OPVCC(19, 129, 0, 0) 3464 case ACREQV: 3465 return OPVCC(19, 289, 0, 0) 3466 case ACRNAND: 3467 return OPVCC(19, 225, 0, 0) 3468 case ACRNOR: 3469 return OPVCC(19, 33, 0, 0) 3470 case ACROR: 3471 return OPVCC(19, 449, 0, 0) 3472 case ACRORN: 3473 return OPVCC(19, 417, 0, 0) 3474 case ACRXOR: 3475 return OPVCC(19, 193, 0, 0) 3476 3477 case ADCBF: 3478 return OPVCC(31, 86, 0, 0) 3479 case ADCBI: 3480 return OPVCC(31, 470, 0, 0) 3481 case ADCBST: 3482 return OPVCC(31, 54, 0, 0) 3483 case ADCBT: 3484 return OPVCC(31, 278, 0, 0) 3485 case ADCBTST: 3486 return OPVCC(31, 246, 0, 0) 3487 case ADCBZ: 3488 return OPVCC(31, 1014, 0, 0) 3489 3490 case AREM, ADIVW: 3491 return OPVCC(31, 491, 0, 0) 3492 3493 case AREMCC, ADIVWCC: 3494 return OPVCC(31, 491, 0, 1) 3495 3496 case AREMV, ADIVWV: 3497 return OPVCC(31, 491, 1, 0) 3498 3499 case AREMVCC, ADIVWVCC: 3500 return OPVCC(31, 491, 1, 1) 3501 3502 case AREMU, ADIVWU: 3503 return OPVCC(31, 459, 0, 0) 3504 3505 case AREMUCC, ADIVWUCC: 3506 return OPVCC(31, 459, 0, 1) 3507 3508 case AREMUV, ADIVWUV: 3509 return OPVCC(31, 459, 1, 0) 3510 3511 case AREMUVCC, ADIVWUVCC: 3512 return OPVCC(31, 459, 1, 1) 3513 3514 case AREMD, ADIVD: 3515 return OPVCC(31, 489, 0, 0) 3516 3517 case AREMDCC, ADIVDCC: 3518 return OPVCC(31, 489, 0, 1) 3519 3520 case ADIVDE: 3521 return OPVCC(31, 425, 0, 0) 3522 3523 case ADIVDECC: 3524 return OPVCC(31, 425, 0, 1) 3525 3526 case ADIVDEU: 3527 return OPVCC(31, 393, 0, 0) 3528 3529 case ADIVDEUCC: 3530 return OPVCC(31, 393, 0, 1) 3531 3532 case AREMDV, ADIVDV: 3533 return OPVCC(31, 489, 1, 0) 3534 3535 case AREMDVCC, ADIVDVCC: 3536 return OPVCC(31, 489, 1, 1) 3537 3538 case AREMDU, ADIVDU: 3539 return OPVCC(31, 457, 0, 0) 3540 3541 case AREMDUCC, ADIVDUCC: 3542 return OPVCC(31, 457, 0, 1) 3543 3544 case AREMDUV, ADIVDUV: 3545 return OPVCC(31, 457, 1, 0) 3546 3547 case AREMDUVCC, ADIVDUVCC: 3548 return OPVCC(31, 457, 1, 1) 3549 3550 case AEIEIO: 3551 return OPVCC(31, 854, 0, 0) 3552 3553 case AEQV: 3554 return OPVCC(31, 284, 0, 0) 3555 case AEQVCC: 3556 return OPVCC(31, 284, 0, 1) 3557 3558 case AEXTSB: 3559 return OPVCC(31, 954, 0, 0) 3560 case AEXTSBCC: 3561 return OPVCC(31, 954, 0, 1) 3562 case AEXTSH: 3563 return OPVCC(31, 922, 0, 0) 3564 case AEXTSHCC: 3565 return OPVCC(31, 922, 0, 1) 3566 case AEXTSW: 3567 return OPVCC(31, 986, 0, 0) 3568 case AEXTSWCC: 3569 return OPVCC(31, 986, 0, 1) 3570 3571 case AFABS: 3572 return OPVCC(63, 264, 0, 0) 3573 case AFABSCC: 3574 return OPVCC(63, 264, 0, 1) 3575 case AFADD: 3576 return OPVCC(63, 21, 0, 0) 3577 case AFADDCC: 3578 return OPVCC(63, 21, 0, 1) 3579 case AFADDS: 3580 return OPVCC(59, 21, 0, 0) 3581 case AFADDSCC: 3582 return OPVCC(59, 21, 0, 1) 3583 case AFCMPO: 3584 return OPVCC(63, 32, 0, 0) 3585 case AFCMPU: 3586 return OPVCC(63, 0, 0, 0) 3587 case AFCFID: 3588 return OPVCC(63, 846, 0, 0) 3589 case AFCFIDCC: 3590 return OPVCC(63, 846, 0, 1) 3591 case AFCFIDU: 3592 return OPVCC(63, 974, 0, 0) 3593 case AFCFIDUCC: 3594 return OPVCC(63, 974, 0, 1) 3595 case AFCTIW: 3596 return OPVCC(63, 14, 0, 0) 3597 case AFCTIWCC: 3598 return OPVCC(63, 14, 0, 1) 3599 case AFCTIWZ: 3600 return OPVCC(63, 15, 0, 0) 3601 case AFCTIWZCC: 3602 return OPVCC(63, 15, 0, 1) 3603 case AFCTID: 3604 return OPVCC(63, 814, 0, 0) 3605 case AFCTIDCC: 3606 return OPVCC(63, 814, 0, 1) 3607 case AFCTIDZ: 3608 return OPVCC(63, 815, 0, 0) 3609 case AFCTIDZCC: 3610 return OPVCC(63, 815, 0, 1) 3611 case AFDIV: 3612 return OPVCC(63, 18, 0, 0) 3613 case AFDIVCC: 3614 return OPVCC(63, 18, 0, 1) 3615 case AFDIVS: 3616 return OPVCC(59, 18, 0, 0) 3617 case AFDIVSCC: 3618 return OPVCC(59, 18, 0, 1) 3619 case AFMADD: 3620 return OPVCC(63, 29, 0, 0) 3621 case AFMADDCC: 3622 return OPVCC(63, 29, 0, 1) 3623 case AFMADDS: 3624 return OPVCC(59, 29, 0, 0) 3625 case AFMADDSCC: 3626 return OPVCC(59, 29, 0, 1) 3627 3628 case AFMOVS, AFMOVD: 3629 return OPVCC(63, 72, 0, 0) /* load */ 3630 case AFMOVDCC: 3631 return OPVCC(63, 72, 0, 1) 3632 case AFMSUB: 3633 return OPVCC(63, 28, 0, 0) 3634 case AFMSUBCC: 3635 return OPVCC(63, 28, 0, 1) 3636 case AFMSUBS: 3637 return OPVCC(59, 28, 0, 0) 3638 case AFMSUBSCC: 3639 return OPVCC(59, 28, 0, 1) 3640 case AFMUL: 3641 return OPVCC(63, 25, 0, 0) 3642 case AFMULCC: 3643 return OPVCC(63, 25, 0, 1) 3644 case AFMULS: 3645 return OPVCC(59, 25, 0, 0) 3646 case AFMULSCC: 3647 return OPVCC(59, 25, 0, 1) 3648 case AFNABS: 3649 return OPVCC(63, 136, 0, 0) 3650 case AFNABSCC: 3651 return OPVCC(63, 136, 0, 1) 3652 case AFNEG: 3653 return OPVCC(63, 40, 0, 0) 3654 case AFNEGCC: 3655 return OPVCC(63, 40, 0, 1) 3656 case AFNMADD: 3657 return OPVCC(63, 31, 0, 0) 3658 case AFNMADDCC: 3659 return OPVCC(63, 31, 0, 1) 3660 case AFNMADDS: 3661 return OPVCC(59, 31, 0, 0) 3662 case AFNMADDSCC: 3663 return OPVCC(59, 31, 0, 1) 3664 case AFNMSUB: 3665 return OPVCC(63, 30, 0, 0) 3666 case AFNMSUBCC: 3667 return OPVCC(63, 30, 0, 1) 3668 case AFNMSUBS: 3669 return OPVCC(59, 30, 0, 0) 3670 case AFNMSUBSCC: 3671 return OPVCC(59, 30, 0, 1) 3672 case AFRES: 3673 return OPVCC(59, 24, 0, 0) 3674 case AFRESCC: 3675 return OPVCC(59, 24, 0, 1) 3676 case AFRIM: 3677 return OPVCC(63, 488, 0, 0) 3678 case AFRIMCC: 3679 return OPVCC(63, 488, 0, 1) 3680 case AFRIP: 3681 return OPVCC(63, 456, 0, 0) 3682 case AFRIPCC: 3683 return OPVCC(63, 456, 0, 1) 3684 case AFRIZ: 3685 return OPVCC(63, 424, 0, 0) 3686 case AFRIZCC: 3687 return OPVCC(63, 424, 0, 1) 3688 case AFRSP: 3689 return OPVCC(63, 12, 0, 0) 3690 case AFRSPCC: 3691 return OPVCC(63, 12, 0, 1) 3692 case AFRSQRTE: 3693 return OPVCC(63, 26, 0, 0) 3694 case AFRSQRTECC: 3695 return OPVCC(63, 26, 0, 1) 3696 case AFSEL: 3697 return OPVCC(63, 23, 0, 0) 3698 case AFSELCC: 3699 return OPVCC(63, 23, 0, 1) 3700 case AFSQRT: 3701 return OPVCC(63, 22, 0, 0) 3702 case AFSQRTCC: 3703 return OPVCC(63, 22, 0, 1) 3704 case AFSQRTS: 3705 return OPVCC(59, 22, 0, 0) 3706 case AFSQRTSCC: 3707 return OPVCC(59, 22, 0, 1) 3708 case AFSUB: 3709 return OPVCC(63, 20, 0, 0) 3710 case AFSUBCC: 3711 return OPVCC(63, 20, 0, 1) 3712 case AFSUBS: 3713 return OPVCC(59, 20, 0, 0) 3714 case AFSUBSCC: 3715 return OPVCC(59, 20, 0, 1) 3716 3717 case AICBI: 3718 return OPVCC(31, 982, 0, 0) 3719 case AISYNC: 3720 return OPVCC(19, 150, 0, 0) 3721 3722 case AMTFSB0: 3723 return OPVCC(63, 70, 0, 0) 3724 case AMTFSB0CC: 3725 return OPVCC(63, 70, 0, 1) 3726 case AMTFSB1: 3727 return OPVCC(63, 38, 0, 0) 3728 case AMTFSB1CC: 3729 return OPVCC(63, 38, 0, 1) 3730 3731 case AMULHW: 3732 return OPVCC(31, 75, 0, 0) 3733 case AMULHWCC: 3734 return OPVCC(31, 75, 0, 1) 3735 case AMULHWU: 3736 return OPVCC(31, 11, 0, 0) 3737 case AMULHWUCC: 3738 return OPVCC(31, 11, 0, 1) 3739 case AMULLW: 3740 return OPVCC(31, 235, 0, 0) 3741 case AMULLWCC: 3742 return OPVCC(31, 235, 0, 1) 3743 case AMULLWV: 3744 return OPVCC(31, 235, 1, 0) 3745 case AMULLWVCC: 3746 return OPVCC(31, 235, 1, 1) 3747 3748 case AMULHD: 3749 return OPVCC(31, 73, 0, 0) 3750 case AMULHDCC: 3751 return OPVCC(31, 73, 0, 1) 3752 case AMULHDU: 3753 return OPVCC(31, 9, 0, 0) 3754 case AMULHDUCC: 3755 return OPVCC(31, 9, 0, 1) 3756 case AMULLD: 3757 return OPVCC(31, 233, 0, 0) 3758 case AMULLDCC: 3759 return OPVCC(31, 233, 0, 1) 3760 case AMULLDV: 3761 return OPVCC(31, 233, 1, 0) 3762 case AMULLDVCC: 3763 return OPVCC(31, 233, 1, 1) 3764 3765 case ANAND: 3766 return OPVCC(31, 476, 0, 0) 3767 case ANANDCC: 3768 return OPVCC(31, 476, 0, 1) 3769 case ANEG: 3770 return OPVCC(31, 104, 0, 0) 3771 case ANEGCC: 3772 return OPVCC(31, 104, 0, 1) 3773 case ANEGV: 3774 return OPVCC(31, 104, 1, 0) 3775 case ANEGVCC: 3776 return OPVCC(31, 104, 1, 1) 3777 case ANOR: 3778 return OPVCC(31, 124, 0, 0) 3779 case ANORCC: 3780 return OPVCC(31, 124, 0, 1) 3781 case AOR: 3782 return OPVCC(31, 444, 0, 0) 3783 case AORCC: 3784 return OPVCC(31, 444, 0, 1) 3785 case AORN: 3786 return OPVCC(31, 412, 0, 0) 3787 case AORNCC: 3788 return OPVCC(31, 412, 0, 1) 3789 3790 case APOPCNTD: 3791 return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */ 3792 case APOPCNTW: 3793 return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */ 3794 case APOPCNTB: 3795 return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */ 3796 3797 case ARFI: 3798 return OPVCC(19, 50, 0, 0) 3799 case ARFCI: 3800 return OPVCC(19, 51, 0, 0) 3801 case ARFID: 3802 return OPVCC(19, 18, 0, 0) 3803 case AHRFID: 3804 return OPVCC(19, 274, 0, 0) 3805 3806 case ARLWMI: 3807 return OPVCC(20, 0, 0, 0) 3808 case ARLWMICC: 3809 return OPVCC(20, 0, 0, 1) 3810 case ARLWNM: 3811 return OPVCC(23, 0, 0, 0) 3812 case ARLWNMCC: 3813 return OPVCC(23, 0, 0, 1) 3814 3815 case ARLDCL: 3816 return OPVCC(30, 8, 0, 0) 3817 case ARLDCR: 3818 return OPVCC(30, 9, 0, 0) 3819 3820 case ARLDICL: 3821 return OPVCC(30, 0, 0, 0) 3822 case ARLDICLCC: 3823 return OPVCC(30, 0, 0, 1) 3824 case ARLDICR: 3825 return OPVCC(30, 0, 0, 0) | 2<<1 // rldicr 3826 case ARLDICRCC: 3827 return OPVCC(30, 0, 0, 1) | 2<<1 // rldicr. 3828 3829 case ASYSCALL: 3830 return OPVCC(17, 1, 0, 0) 3831 3832 case ASLW: 3833 return OPVCC(31, 24, 0, 0) 3834 case ASLWCC: 3835 return OPVCC(31, 24, 0, 1) 3836 case ASLD: 3837 return OPVCC(31, 27, 0, 0) 3838 case ASLDCC: 3839 return OPVCC(31, 27, 0, 1) 3840 3841 case ASRAW: 3842 return OPVCC(31, 792, 0, 0) 3843 case ASRAWCC: 3844 return OPVCC(31, 792, 0, 1) 3845 case ASRAD: 3846 return OPVCC(31, 794, 0, 0) 3847 case ASRADCC: 3848 return OPVCC(31, 794, 0, 1) 3849 3850 case ASRW: 3851 return OPVCC(31, 536, 0, 0) 3852 case ASRWCC: 3853 return OPVCC(31, 536, 0, 1) 3854 case ASRD: 3855 return OPVCC(31, 539, 0, 0) 3856 case ASRDCC: 3857 return OPVCC(31, 539, 0, 1) 3858 3859 case ASUB: 3860 return OPVCC(31, 40, 0, 0) 3861 case ASUBCC: 3862 return OPVCC(31, 40, 0, 1) 3863 case ASUBV: 3864 return OPVCC(31, 40, 1, 0) 3865 case ASUBVCC: 3866 return OPVCC(31, 40, 1, 1) 3867 case ASUBC: 3868 return OPVCC(31, 8, 0, 0) 3869 case ASUBCCC: 3870 return OPVCC(31, 8, 0, 1) 3871 case ASUBCV: 3872 return OPVCC(31, 8, 1, 0) 3873 case ASUBCVCC: 3874 return OPVCC(31, 8, 1, 1) 3875 case ASUBE: 3876 return OPVCC(31, 136, 0, 0) 3877 case ASUBECC: 3878 return OPVCC(31, 136, 0, 1) 3879 case ASUBEV: 3880 return OPVCC(31, 136, 1, 0) 3881 case ASUBEVCC: 3882 return OPVCC(31, 136, 1, 1) 3883 case ASUBME: 3884 return OPVCC(31, 232, 0, 0) 3885 case ASUBMECC: 3886 return OPVCC(31, 232, 0, 1) 3887 case ASUBMEV: 3888 return OPVCC(31, 232, 1, 0) 3889 case ASUBMEVCC: 3890 return OPVCC(31, 232, 1, 1) 3891 case ASUBZE: 3892 return OPVCC(31, 200, 0, 0) 3893 case ASUBZECC: 3894 return OPVCC(31, 200, 0, 1) 3895 case ASUBZEV: 3896 return OPVCC(31, 200, 1, 0) 3897 case ASUBZEVCC: 3898 return OPVCC(31, 200, 1, 1) 3899 3900 case ASYNC: 3901 return OPVCC(31, 598, 0, 0) 3902 case ALWSYNC: 3903 return OPVCC(31, 598, 0, 0) | 1<<21 3904 3905 case APTESYNC: 3906 return OPVCC(31, 598, 0, 0) | 2<<21 3907 3908 case ATLBIE: 3909 return OPVCC(31, 306, 0, 0) 3910 case ATLBIEL: 3911 return OPVCC(31, 274, 0, 0) 3912 case ATLBSYNC: 3913 return OPVCC(31, 566, 0, 0) 3914 case ASLBIA: 3915 return OPVCC(31, 498, 0, 0) 3916 case ASLBIE: 3917 return OPVCC(31, 434, 0, 0) 3918 case ASLBMFEE: 3919 return OPVCC(31, 915, 0, 0) 3920 case ASLBMFEV: 3921 return OPVCC(31, 851, 0, 0) 3922 case ASLBMTE: 3923 return OPVCC(31, 402, 0, 0) 3924 3925 case ATW: 3926 return OPVCC(31, 4, 0, 0) 3927 case ATD: 3928 return OPVCC(31, 68, 0, 0) 3929 3930 /* Vector (VMX/Altivec) instructions */ 3931 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 3932 /* are enabled starting at POWER6 (ISA 2.05). */ 3933 case AVAND: 3934 return OPVX(4, 1028, 0, 0) /* vand - v2.03 */ 3935 case AVANDC: 3936 return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */ 3937 case AVNAND: 3938 return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */ 3939 3940 case AVOR: 3941 return OPVX(4, 1156, 0, 0) /* vor - v2.03 */ 3942 case AVORC: 3943 return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */ 3944 case AVNOR: 3945 return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */ 3946 case AVXOR: 3947 return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */ 3948 case AVEQV: 3949 return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */ 3950 3951 case AVADDUBM: 3952 return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */ 3953 case AVADDUHM: 3954 return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */ 3955 case AVADDUWM: 3956 return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */ 3957 case AVADDUDM: 3958 return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */ 3959 case AVADDUQM: 3960 return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */ 3961 3962 case AVADDCUQ: 3963 return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */ 3964 case AVADDCUW: 3965 return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */ 3966 3967 case AVADDUBS: 3968 return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */ 3969 case AVADDUHS: 3970 return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */ 3971 case AVADDUWS: 3972 return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */ 3973 3974 case AVADDSBS: 3975 return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */ 3976 case AVADDSHS: 3977 return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */ 3978 case AVADDSWS: 3979 return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */ 3980 3981 case AVADDEUQM: 3982 return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */ 3983 case AVADDECUQ: 3984 return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */ 3985 3986 case AVPMSUMB: 3987 return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */ 3988 case AVPMSUMH: 3989 return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */ 3990 case AVPMSUMW: 3991 return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */ 3992 case AVPMSUMD: 3993 return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */ 3994 3995 case AVSUBUBM: 3996 return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */ 3997 case AVSUBUHM: 3998 return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */ 3999 case AVSUBUWM: 4000 return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */ 4001 case AVSUBUDM: 4002 return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */ 4003 case AVSUBUQM: 4004 return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */ 4005 4006 case AVSUBCUQ: 4007 return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */ 4008 case AVSUBCUW: 4009 return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */ 4010 4011 case AVSUBUBS: 4012 return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */ 4013 case AVSUBUHS: 4014 return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */ 4015 case AVSUBUWS: 4016 return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */ 4017 4018 case AVSUBSBS: 4019 return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */ 4020 case AVSUBSHS: 4021 return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */ 4022 case AVSUBSWS: 4023 return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */ 4024 4025 case AVSUBEUQM: 4026 return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */ 4027 case AVSUBECUQ: 4028 return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */ 4029 4030 case AVRLB: 4031 return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */ 4032 case AVRLH: 4033 return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */ 4034 case AVRLW: 4035 return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */ 4036 case AVRLD: 4037 return OPVX(4, 196, 0, 0) /* vrld - v2.07 */ 4038 4039 case AVSLB: 4040 return OPVX(4, 260, 0, 0) /* vslh - v2.03 */ 4041 case AVSLH: 4042 return OPVX(4, 324, 0, 0) /* vslh - v2.03 */ 4043 case AVSLW: 4044 return OPVX(4, 388, 0, 0) /* vslw - v2.03 */ 4045 case AVSL: 4046 return OPVX(4, 452, 0, 0) /* vsl - v2.03 */ 4047 case AVSLO: 4048 return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */ 4049 case AVSRB: 4050 return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */ 4051 case AVSRH: 4052 return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */ 4053 case AVSRW: 4054 return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */ 4055 case AVSR: 4056 return OPVX(4, 708, 0, 0) /* vsr - v2.03 */ 4057 case AVSRO: 4058 return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */ 4059 case AVSLD: 4060 return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */ 4061 case AVSRD: 4062 return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */ 4063 4064 case AVSRAB: 4065 return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */ 4066 case AVSRAH: 4067 return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */ 4068 case AVSRAW: 4069 return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */ 4070 case AVSRAD: 4071 return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */ 4072 4073 case AVCLZB: 4074 return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */ 4075 case AVCLZH: 4076 return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */ 4077 case AVCLZW: 4078 return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */ 4079 case AVCLZD: 4080 return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */ 4081 4082 case AVPOPCNTB: 4083 return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */ 4084 case AVPOPCNTH: 4085 return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */ 4086 case AVPOPCNTW: 4087 return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */ 4088 case AVPOPCNTD: 4089 return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */ 4090 4091 case AVCMPEQUB: 4092 return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */ 4093 case AVCMPEQUBCC: 4094 return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */ 4095 case AVCMPEQUH: 4096 return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */ 4097 case AVCMPEQUHCC: 4098 return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */ 4099 case AVCMPEQUW: 4100 return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */ 4101 case AVCMPEQUWCC: 4102 return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */ 4103 case AVCMPEQUD: 4104 return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */ 4105 case AVCMPEQUDCC: 4106 return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */ 4107 4108 case AVCMPGTUB: 4109 return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */ 4110 case AVCMPGTUBCC: 4111 return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */ 4112 case AVCMPGTUH: 4113 return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */ 4114 case AVCMPGTUHCC: 4115 return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */ 4116 case AVCMPGTUW: 4117 return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */ 4118 case AVCMPGTUWCC: 4119 return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */ 4120 case AVCMPGTUD: 4121 return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */ 4122 case AVCMPGTUDCC: 4123 return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */ 4124 case AVCMPGTSB: 4125 return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */ 4126 case AVCMPGTSBCC: 4127 return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */ 4128 case AVCMPGTSH: 4129 return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */ 4130 case AVCMPGTSHCC: 4131 return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */ 4132 case AVCMPGTSW: 4133 return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */ 4134 case AVCMPGTSWCC: 4135 return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */ 4136 case AVCMPGTSD: 4137 return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */ 4138 case AVCMPGTSDCC: 4139 return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */ 4140 4141 case AVPERM: 4142 return OPVX(4, 43, 0, 0) /* vperm - v2.03 */ 4143 4144 case AVSEL: 4145 return OPVX(4, 42, 0, 0) /* vsel - v2.03 */ 4146 4147 case AVCIPHER: 4148 return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */ 4149 case AVCIPHERLAST: 4150 return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */ 4151 case AVNCIPHER: 4152 return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */ 4153 case AVNCIPHERLAST: 4154 return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */ 4155 case AVSBOX: 4156 return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */ 4157 /* End of vector instructions */ 4158 4159 /* Vector scalar (VSX) instructions */ 4160 /* ISA 2.06 enables these for POWER7. */ 4161 case AMFVSRD, AMFVRD, AMFFPRD: 4162 return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */ 4163 case AMFVSRWZ: 4164 return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */ 4165 4166 case AMTVSRD, AMTFPRD, AMTVRD: 4167 return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */ 4168 case AMTVSRWA: 4169 return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */ 4170 case AMTVSRWZ: 4171 return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */ 4172 4173 case AXXLANDQ: 4174 return OPVXX3(60, 130, 0) /* xxland - v2.06 */ 4175 case AXXLANDC: 4176 return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */ 4177 case AXXLEQV: 4178 return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */ 4179 case AXXLNAND: 4180 return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */ 4181 4182 case AXXLORC: 4183 return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */ 4184 case AXXLNOR: 4185 return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */ 4186 case AXXLORQ: 4187 return OPVXX3(60, 146, 0) /* xxlor - v2.06 */ 4188 case AXXLXOR: 4189 return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */ 4190 4191 case AXXSEL: 4192 return OPVXX4(60, 3, 0) /* xxsel - v2.06 */ 4193 4194 case AXXMRGHW: 4195 return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */ 4196 case AXXMRGLW: 4197 return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */ 4198 4199 case AXXSPLTW: 4200 return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */ 4201 4202 case AXXPERMDI: 4203 return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */ 4204 4205 case AXXSLDWI: 4206 return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */ 4207 4208 case AXSCVDPSP: 4209 return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */ 4210 case AXSCVSPDP: 4211 return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */ 4212 case AXSCVDPSPN: 4213 return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */ 4214 case AXSCVSPDPN: 4215 return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */ 4216 4217 case AXVCVDPSP: 4218 return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */ 4219 case AXVCVSPDP: 4220 return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */ 4221 4222 case AXSCVDPSXDS: 4223 return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */ 4224 case AXSCVDPSXWS: 4225 return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */ 4226 case AXSCVDPUXDS: 4227 return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */ 4228 case AXSCVDPUXWS: 4229 return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */ 4230 4231 case AXSCVSXDDP: 4232 return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */ 4233 case AXSCVUXDDP: 4234 return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */ 4235 case AXSCVSXDSP: 4236 return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */ 4237 case AXSCVUXDSP: 4238 return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */ 4239 4240 case AXVCVDPSXDS: 4241 return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */ 4242 case AXVCVDPSXWS: 4243 return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */ 4244 case AXVCVDPUXDS: 4245 return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */ 4246 case AXVCVDPUXWS: 4247 return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */ 4248 case AXVCVSPSXDS: 4249 return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */ 4250 case AXVCVSPSXWS: 4251 return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */ 4252 case AXVCVSPUXDS: 4253 return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */ 4254 case AXVCVSPUXWS: 4255 return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */ 4256 4257 case AXVCVSXDDP: 4258 return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */ 4259 case AXVCVSXWDP: 4260 return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */ 4261 case AXVCVUXDDP: 4262 return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */ 4263 case AXVCVUXWDP: 4264 return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */ 4265 case AXVCVSXDSP: 4266 return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */ 4267 case AXVCVSXWSP: 4268 return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */ 4269 case AXVCVUXDSP: 4270 return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */ 4271 case AXVCVUXWSP: 4272 return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */ 4273 /* End of VSX instructions */ 4274 4275 case AXOR: 4276 return OPVCC(31, 316, 0, 0) 4277 case AXORCC: 4278 return OPVCC(31, 316, 0, 1) 4279 } 4280 4281 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a) 4282 return 0 4283 } 4284 4285 func (c *ctxt9) opirrr(a obj.As) uint32 { 4286 switch a { 4287 /* Vector (VMX/Altivec) instructions */ 4288 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4289 /* are enabled starting at POWER6 (ISA 2.05). */ 4290 case AVSLDOI: 4291 return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */ 4292 } 4293 4294 c.ctxt.Diag("bad i/r/r/r opcode %v", a) 4295 return 0 4296 } 4297 4298 func (c *ctxt9) opiirr(a obj.As) uint32 { 4299 switch a { 4300 /* Vector (VMX/Altivec) instructions */ 4301 /* ISA 2.07 enables these for POWER8 and beyond. */ 4302 case AVSHASIGMAW: 4303 return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */ 4304 case AVSHASIGMAD: 4305 return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */ 4306 } 4307 4308 c.ctxt.Diag("bad i/i/r/r opcode %v", a) 4309 return 0 4310 } 4311 4312 func (c *ctxt9) opirr(a obj.As) uint32 { 4313 switch a { 4314 case AADD: 4315 return OPVCC(14, 0, 0, 0) 4316 case AADDC: 4317 return OPVCC(12, 0, 0, 0) 4318 case AADDCCC: 4319 return OPVCC(13, 0, 0, 0) 4320 case -AADD: 4321 return OPVCC(15, 0, 0, 0) /* ADDIS/CAU */ 4322 4323 case AANDCC: 4324 return OPVCC(28, 0, 0, 0) 4325 case -AANDCC: 4326 return OPVCC(29, 0, 0, 0) /* ANDIS./ANDIU. */ 4327 4328 case ABR: 4329 return OPVCC(18, 0, 0, 0) 4330 case ABL: 4331 return OPVCC(18, 0, 0, 0) | 1 4332 case obj.ADUFFZERO: 4333 return OPVCC(18, 0, 0, 0) | 1 4334 case obj.ADUFFCOPY: 4335 return OPVCC(18, 0, 0, 0) | 1 4336 case ABC: 4337 return OPVCC(16, 0, 0, 0) 4338 case ABCL: 4339 return OPVCC(16, 0, 0, 0) | 1 4340 4341 case ABEQ: 4342 return AOP_RRR(16<<26, 12, 2, 0) 4343 case ABGE: 4344 return AOP_RRR(16<<26, 4, 0, 0) 4345 case ABGT: 4346 return AOP_RRR(16<<26, 12, 1, 0) 4347 case ABLE: 4348 return AOP_RRR(16<<26, 4, 1, 0) 4349 case ABLT: 4350 return AOP_RRR(16<<26, 12, 0, 0) 4351 case ABNE: 4352 return AOP_RRR(16<<26, 4, 2, 0) 4353 case ABVC: 4354 return AOP_RRR(16<<26, 4, 3, 0) // apparently unordered-clear 4355 case ABVS: 4356 return AOP_RRR(16<<26, 12, 3, 0) // apparently unordered-set 4357 4358 case ACMP: 4359 return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */ 4360 case ACMPU: 4361 return OPVCC(10, 0, 0, 0) | 1<<21 4362 case ACMPW: 4363 return OPVCC(11, 0, 0, 0) /* L=0 */ 4364 case ACMPWU: 4365 return OPVCC(10, 0, 0, 0) 4366 case ALSW: 4367 return OPVCC(31, 597, 0, 0) 4368 4369 case AMULLW: 4370 return OPVCC(7, 0, 0, 0) 4371 4372 case AOR: 4373 return OPVCC(24, 0, 0, 0) 4374 case -AOR: 4375 return OPVCC(25, 0, 0, 0) /* ORIS/ORIU */ 4376 4377 case ARLWMI: 4378 return OPVCC(20, 0, 0, 0) /* rlwimi */ 4379 case ARLWMICC: 4380 return OPVCC(20, 0, 0, 1) 4381 case ARLDMI: 4382 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4383 case ARLDMICC: 4384 return OPVCC(30, 0, 0, 1) | 3<<2 4385 case ARLDIMI: 4386 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4387 case ARLDIMICC: 4388 return OPVCC(30, 0, 0, 1) | 3<<2 4389 case ARLWNM: 4390 return OPVCC(21, 0, 0, 0) /* rlwinm */ 4391 case ARLWNMCC: 4392 return OPVCC(21, 0, 0, 1) 4393 4394 case ARLDCL: 4395 return OPVCC(30, 0, 0, 0) /* rldicl */ 4396 case ARLDCLCC: 4397 return OPVCC(30, 0, 0, 1) 4398 case ARLDCR: 4399 return OPVCC(30, 1, 0, 0) /* rldicr */ 4400 case ARLDCRCC: 4401 return OPVCC(30, 1, 0, 1) 4402 case ARLDC: 4403 return OPVCC(30, 0, 0, 0) | 2<<2 4404 case ARLDCCC: 4405 return OPVCC(30, 0, 0, 1) | 2<<2 4406 4407 case ASRAW: 4408 return OPVCC(31, 824, 0, 0) 4409 case ASRAWCC: 4410 return OPVCC(31, 824, 0, 1) 4411 case ASRAD: 4412 return OPVCC(31, (413 << 1), 0, 0) 4413 case ASRADCC: 4414 return OPVCC(31, (413 << 1), 0, 1) 4415 4416 case ASTSW: 4417 return OPVCC(31, 725, 0, 0) 4418 4419 case ASUBC: 4420 return OPVCC(8, 0, 0, 0) 4421 4422 case ATW: 4423 return OPVCC(3, 0, 0, 0) 4424 case ATD: 4425 return OPVCC(2, 0, 0, 0) 4426 4427 /* Vector (VMX/Altivec) instructions */ 4428 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4429 /* are enabled starting at POWER6 (ISA 2.05). */ 4430 case AVSPLTB: 4431 return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */ 4432 case AVSPLTH: 4433 return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */ 4434 case AVSPLTW: 4435 return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */ 4436 4437 case AVSPLTISB: 4438 return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */ 4439 case AVSPLTISH: 4440 return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */ 4441 case AVSPLTISW: 4442 return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */ 4443 /* End of vector instructions */ 4444 4445 case AFTDIV: 4446 return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */ 4447 case AFTSQRT: 4448 return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */ 4449 4450 case AXOR: 4451 return OPVCC(26, 0, 0, 0) /* XORIL */ 4452 case -AXOR: 4453 return OPVCC(27, 0, 0, 0) /* XORIU */ 4454 } 4455 4456 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a) 4457 return 0 4458 } 4459 4460 /* 4461 * load o(a),d 4462 */ 4463 func (c *ctxt9) opload(a obj.As) uint32 { 4464 switch a { 4465 case AMOVD: 4466 return OPVCC(58, 0, 0, 0) /* ld */ 4467 case AMOVDU: 4468 return OPVCC(58, 0, 0, 1) /* ldu */ 4469 case AMOVWZ: 4470 return OPVCC(32, 0, 0, 0) /* lwz */ 4471 case AMOVWZU: 4472 return OPVCC(33, 0, 0, 0) /* lwzu */ 4473 case AMOVW: 4474 return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */ 4475 4476 /* no AMOVWU */ 4477 case AMOVB, AMOVBZ: 4478 return OPVCC(34, 0, 0, 0) 4479 /* load */ 4480 4481 case AMOVBU, AMOVBZU: 4482 return OPVCC(35, 0, 0, 0) 4483 case AFMOVD: 4484 return OPVCC(50, 0, 0, 0) 4485 case AFMOVDU: 4486 return OPVCC(51, 0, 0, 0) 4487 case AFMOVS: 4488 return OPVCC(48, 0, 0, 0) 4489 case AFMOVSU: 4490 return OPVCC(49, 0, 0, 0) 4491 case AMOVH: 4492 return OPVCC(42, 0, 0, 0) 4493 case AMOVHU: 4494 return OPVCC(43, 0, 0, 0) 4495 case AMOVHZ: 4496 return OPVCC(40, 0, 0, 0) 4497 case AMOVHZU: 4498 return OPVCC(41, 0, 0, 0) 4499 case AMOVMW: 4500 return OPVCC(46, 0, 0, 0) /* lmw */ 4501 } 4502 4503 c.ctxt.Diag("bad load opcode %v", a) 4504 return 0 4505 } 4506 4507 /* 4508 * indexed load a(b),d 4509 */ 4510 func (c *ctxt9) oploadx(a obj.As) uint32 { 4511 switch a { 4512 case AMOVWZ: 4513 return OPVCC(31, 23, 0, 0) /* lwzx */ 4514 case AMOVWZU: 4515 return OPVCC(31, 55, 0, 0) /* lwzux */ 4516 case AMOVW: 4517 return OPVCC(31, 341, 0, 0) /* lwax */ 4518 case AMOVWU: 4519 return OPVCC(31, 373, 0, 0) /* lwaux */ 4520 4521 case AMOVB, AMOVBZ: 4522 return OPVCC(31, 87, 0, 0) /* lbzx */ 4523 4524 case AMOVBU, AMOVBZU: 4525 return OPVCC(31, 119, 0, 0) /* lbzux */ 4526 case AFMOVD: 4527 return OPVCC(31, 599, 0, 0) /* lfdx */ 4528 case AFMOVDU: 4529 return OPVCC(31, 631, 0, 0) /* lfdux */ 4530 case AFMOVS: 4531 return OPVCC(31, 535, 0, 0) /* lfsx */ 4532 case AFMOVSU: 4533 return OPVCC(31, 567, 0, 0) /* lfsux */ 4534 case AFMOVSX: 4535 return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */ 4536 case AFMOVSZ: 4537 return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */ 4538 case AMOVH: 4539 return OPVCC(31, 343, 0, 0) /* lhax */ 4540 case AMOVHU: 4541 return OPVCC(31, 375, 0, 0) /* lhaux */ 4542 case AMOVHBR: 4543 return OPVCC(31, 790, 0, 0) /* lhbrx */ 4544 case AMOVWBR: 4545 return OPVCC(31, 534, 0, 0) /* lwbrx */ 4546 case AMOVDBR: 4547 return OPVCC(31, 532, 0, 0) /* ldbrx */ 4548 case AMOVHZ: 4549 return OPVCC(31, 279, 0, 0) /* lhzx */ 4550 case AMOVHZU: 4551 return OPVCC(31, 311, 0, 0) /* lhzux */ 4552 case AECIWX: 4553 return OPVCC(31, 310, 0, 0) /* eciwx */ 4554 case ALBAR: 4555 return OPVCC(31, 52, 0, 0) /* lbarx */ 4556 case ALWAR: 4557 return OPVCC(31, 20, 0, 0) /* lwarx */ 4558 case ALDAR: 4559 return OPVCC(31, 84, 0, 0) 4560 case ALSW: 4561 return OPVCC(31, 533, 0, 0) /* lswx */ 4562 case AMOVD: 4563 return OPVCC(31, 21, 0, 0) /* ldx */ 4564 case AMOVDU: 4565 return OPVCC(31, 53, 0, 0) /* ldux */ 4566 4567 /* Vector (VMX/Altivec) instructions */ 4568 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4569 /* are enabled starting at POWER6 (ISA 2.05). */ 4570 case ALVEBX: 4571 return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */ 4572 case ALVEHX: 4573 return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */ 4574 case ALVEWX: 4575 return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */ 4576 case ALVX: 4577 return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */ 4578 case ALVXL: 4579 return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */ 4580 case ALVSL: 4581 return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */ 4582 case ALVSR: 4583 return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */ 4584 /* End of vector instructions */ 4585 4586 /* Vector scalar (VSX) instructions */ 4587 /* ISA 2.06 enables these for POWER7. */ 4588 case ALXVD2X: 4589 return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */ 4590 case ALXVDSX: 4591 return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */ 4592 case ALXVW4X: 4593 return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */ 4594 4595 case ALXSDX: 4596 return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */ 4597 4598 case ALXSIWAX: 4599 return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */ 4600 case ALXSIWZX: 4601 return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */ 4602 /* End of vector scalar instructions */ 4603 4604 } 4605 4606 c.ctxt.Diag("bad loadx opcode %v", a) 4607 return 0 4608 } 4609 4610 /* 4611 * store s,o(d) 4612 */ 4613 func (c *ctxt9) opstore(a obj.As) uint32 { 4614 switch a { 4615 case AMOVB, AMOVBZ: 4616 return OPVCC(38, 0, 0, 0) /* stb */ 4617 4618 case AMOVBU, AMOVBZU: 4619 return OPVCC(39, 0, 0, 0) /* stbu */ 4620 case AFMOVD: 4621 return OPVCC(54, 0, 0, 0) /* stfd */ 4622 case AFMOVDU: 4623 return OPVCC(55, 0, 0, 0) /* stfdu */ 4624 case AFMOVS: 4625 return OPVCC(52, 0, 0, 0) /* stfs */ 4626 case AFMOVSU: 4627 return OPVCC(53, 0, 0, 0) /* stfsu */ 4628 4629 case AMOVHZ, AMOVH: 4630 return OPVCC(44, 0, 0, 0) /* sth */ 4631 4632 case AMOVHZU, AMOVHU: 4633 return OPVCC(45, 0, 0, 0) /* sthu */ 4634 case AMOVMW: 4635 return OPVCC(47, 0, 0, 0) /* stmw */ 4636 case ASTSW: 4637 return OPVCC(31, 725, 0, 0) /* stswi */ 4638 4639 case AMOVWZ, AMOVW: 4640 return OPVCC(36, 0, 0, 0) /* stw */ 4641 4642 case AMOVWZU, AMOVWU: 4643 return OPVCC(37, 0, 0, 0) /* stwu */ 4644 case AMOVD: 4645 return OPVCC(62, 0, 0, 0) /* std */ 4646 case AMOVDU: 4647 return OPVCC(62, 0, 0, 1) /* stdu */ 4648 } 4649 4650 c.ctxt.Diag("unknown store opcode %v", a) 4651 return 0 4652 } 4653 4654 /* 4655 * indexed store s,a(b) 4656 */ 4657 func (c *ctxt9) opstorex(a obj.As) uint32 { 4658 switch a { 4659 case AMOVB, AMOVBZ: 4660 return OPVCC(31, 215, 0, 0) /* stbx */ 4661 4662 case AMOVBU, AMOVBZU: 4663 return OPVCC(31, 247, 0, 0) /* stbux */ 4664 case AFMOVD: 4665 return OPVCC(31, 727, 0, 0) /* stfdx */ 4666 case AFMOVDU: 4667 return OPVCC(31, 759, 0, 0) /* stfdux */ 4668 case AFMOVS: 4669 return OPVCC(31, 663, 0, 0) /* stfsx */ 4670 case AFMOVSU: 4671 return OPVCC(31, 695, 0, 0) /* stfsux */ 4672 case AFMOVSX: 4673 return OPVCC(31, 983, 0, 0) /* stfiwx */ 4674 4675 case AMOVHZ, AMOVH: 4676 return OPVCC(31, 407, 0, 0) /* sthx */ 4677 case AMOVHBR: 4678 return OPVCC(31, 918, 0, 0) /* sthbrx */ 4679 4680 case AMOVHZU, AMOVHU: 4681 return OPVCC(31, 439, 0, 0) /* sthux */ 4682 4683 case AMOVWZ, AMOVW: 4684 return OPVCC(31, 151, 0, 0) /* stwx */ 4685 4686 case AMOVWZU, AMOVWU: 4687 return OPVCC(31, 183, 0, 0) /* stwux */ 4688 case ASTSW: 4689 return OPVCC(31, 661, 0, 0) /* stswx */ 4690 case AMOVWBR: 4691 return OPVCC(31, 662, 0, 0) /* stwbrx */ 4692 case ASTBCCC: 4693 return OPVCC(31, 694, 0, 1) /* stbcx. */ 4694 case ASTWCCC: 4695 return OPVCC(31, 150, 0, 1) /* stwcx. */ 4696 case ASTDCCC: 4697 return OPVCC(31, 214, 0, 1) /* stwdx. */ 4698 case AECOWX: 4699 return OPVCC(31, 438, 0, 0) /* ecowx */ 4700 case AMOVD: 4701 return OPVCC(31, 149, 0, 0) /* stdx */ 4702 case AMOVDU: 4703 return OPVCC(31, 181, 0, 0) /* stdux */ 4704 4705 /* Vector (VMX/Altivec) instructions */ 4706 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4707 /* are enabled starting at POWER6 (ISA 2.05). */ 4708 case ASTVEBX: 4709 return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */ 4710 case ASTVEHX: 4711 return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */ 4712 case ASTVEWX: 4713 return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */ 4714 case ASTVX: 4715 return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */ 4716 case ASTVXL: 4717 return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */ 4718 /* End of vector instructions */ 4719 4720 /* Vector scalar (VSX) instructions */ 4721 /* ISA 2.06 enables these for POWER7. */ 4722 case ASTXVD2X: 4723 return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */ 4724 case ASTXVW4X: 4725 return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */ 4726 4727 case ASTXSDX: 4728 return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */ 4729 4730 case ASTXSIWX: 4731 return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */ 4732 /* End of vector scalar instructions */ 4733 4734 } 4735 4736 c.ctxt.Diag("unknown storex opcode %v", a) 4737 return 0 4738 }