github.com/slayercat/go@v0.0.0-20170428012452-c51559813f61/src/cmd/internal/obj/s390x/asmz.go (about) 1 // Based on cmd/internal/obj/ppc64/asm9.go. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package s390x 31 32 import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "log" 36 "math" 37 "sort" 38 ) 39 40 // ctxtz holds state while assembling a single function. 41 // Each function gets a fresh ctxtz. 42 // This allows for multiple functions to be safely concurrently assembled. 43 type ctxtz struct { 44 ctxt *obj.Link 45 newprog obj.ProgAlloc 46 cursym *obj.LSym 47 autosize int32 48 instoffset int64 49 pc int64 50 } 51 52 // instruction layout. 53 const ( 54 funcAlign = 16 55 ) 56 57 type Optab struct { 58 as obj.As // opcode 59 a1 uint8 // From 60 a2 uint8 // Reg 61 a3 uint8 // From3 62 a4 uint8 // To 63 type_ int8 64 param int16 // REGSP for auto variables 65 } 66 67 var optab = []Optab{ 68 // instruction, From, Reg, From3, To, type, param 69 Optab{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0}, 70 Optab{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0}, 71 72 // move register 73 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 74 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 75 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 76 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 77 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 78 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 1, 0}, 79 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 80 81 // load constant 82 Optab{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 83 Optab{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 84 Optab{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 85 Optab{AMOVD, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 86 Optab{AMOVW, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 87 Optab{AMOVWZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 88 Optab{AMOVB, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 89 Optab{AMOVBZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 90 91 // store constant 92 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 93 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 94 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 95 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 96 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 97 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 98 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 99 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 100 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 101 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 102 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 103 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 104 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 105 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 106 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 107 108 // store 109 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 110 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 111 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 112 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 113 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 114 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 115 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 116 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 117 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 118 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 119 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 120 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 121 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 122 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 123 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 124 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 125 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 126 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 127 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 128 129 // load 130 Optab{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 131 Optab{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 132 Optab{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 133 Optab{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 134 Optab{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 135 Optab{AMOVDBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 136 Optab{AMOVHBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 137 Optab{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 138 Optab{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 139 Optab{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 140 Optab{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 141 Optab{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 142 Optab{AMOVDBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 143 Optab{AMOVHBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 144 Optab{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 145 Optab{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 146 Optab{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 147 Optab{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 148 Optab{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 149 150 // interlocked load and op 151 Optab{ALAAG, C_REG, C_REG, C_NONE, C_LOREG, 99, 0}, 152 153 // integer arithmetic 154 Optab{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 155 Optab{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 156 Optab{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 0}, 157 Optab{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 0}, 158 Optab{AADD, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 159 Optab{AADD, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 160 Optab{ASUB, C_LCON, C_REG, C_NONE, C_REG, 21, 0}, 161 Optab{ASUB, C_LCON, C_NONE, C_NONE, C_REG, 21, 0}, 162 Optab{ASUB, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 163 Optab{ASUB, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 164 Optab{AMULHD, C_REG, C_NONE, C_NONE, C_REG, 4, 0}, 165 Optab{AMULHD, C_REG, C_REG, C_NONE, C_REG, 4, 0}, 166 Optab{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 167 Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 168 Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0}, 169 Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0}, 170 Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0}, 171 Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0}, 172 173 // integer logical 174 Optab{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 175 Optab{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 176 Optab{AAND, C_LCON, C_NONE, C_NONE, C_REG, 23, 0}, 177 Optab{AAND, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 178 Optab{AAND, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 179 Optab{AANDW, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 180 Optab{AANDW, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 181 Optab{AANDW, C_LCON, C_NONE, C_NONE, C_REG, 24, 0}, 182 Optab{AANDW, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 183 Optab{AANDW, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 184 Optab{ASLD, C_REG, C_NONE, C_NONE, C_REG, 7, 0}, 185 Optab{ASLD, C_REG, C_REG, C_NONE, C_REG, 7, 0}, 186 Optab{ASLD, C_SCON, C_REG, C_NONE, C_REG, 7, 0}, 187 Optab{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 7, 0}, 188 189 // compare and swap 190 Optab{ACSG, C_REG, C_REG, C_NONE, C_SOREG, 79, 0}, 191 192 // floating point 193 Optab{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 194 Optab{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 0}, 195 Optab{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 0}, 196 Optab{AFMADD, C_FREG, C_FREG, C_NONE, C_FREG, 34, 0}, 197 Optab{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 198 Optab{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, REGSP}, 199 Optab{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 0}, 200 Optab{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 0}, 201 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 202 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 0}, 203 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 0}, 204 Optab{AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 67, 0}, 205 Optab{ALDGR, C_REG, C_NONE, C_NONE, C_FREG, 81, 0}, 206 Optab{ALGDR, C_FREG, C_NONE, C_NONE, C_REG, 81, 0}, 207 Optab{ACEFBRA, C_REG, C_NONE, C_NONE, C_FREG, 82, 0}, 208 Optab{ACFEBRA, C_FREG, C_NONE, C_NONE, C_REG, 83, 0}, 209 Optab{AFIEBR, C_SCON, C_FREG, C_NONE, C_FREG, 48, 0}, 210 211 // load symbol address (plus offset) 212 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_REG, 19, 0}, 213 Optab{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 93, 0}, 214 Optab{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 94, 0}, 215 Optab{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 95, 0}, 216 217 // system call 218 Optab{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 0}, 219 Optab{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 0}, 220 221 // branch 222 Optab{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 0}, 223 Optab{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 0}, 224 Optab{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 16, 0}, 225 Optab{ABR, C_NONE, C_NONE, C_NONE, C_REG, 18, 0}, 226 Optab{ABR, C_REG, C_NONE, C_NONE, C_REG, 18, 0}, 227 Optab{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 228 Optab{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 229 Optab{ACMPBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 230 Optab{ACMPBEQ, C_REG, C_NONE, C_ADDCON, C_SBRA, 90, 0}, 231 Optab{ACMPBEQ, C_REG, C_NONE, C_SCON, C_SBRA, 90, 0}, 232 Optab{ACMPUBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 233 Optab{ACMPUBEQ, C_REG, C_NONE, C_ANDCON, C_SBRA, 90, 0}, 234 235 // move on condition 236 Optab{AMOVDEQ, C_REG, C_NONE, C_NONE, C_REG, 17, 0}, 237 238 // find leftmost one 239 Optab{AFLOGR, C_REG, C_NONE, C_NONE, C_REG, 8, 0}, 240 241 // compare 242 Optab{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 243 Optab{ACMP, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 244 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 245 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 246 Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0}, 247 Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0}, 248 249 // 32-bit access registers 250 Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 251 Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 252 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 253 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 254 255 // macros 256 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LOREG, 96, 0}, 257 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LAUTO, 96, REGSP}, 258 259 // load/store multiple 260 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LOREG, 97, 0}, 261 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LAUTO, 97, REGSP}, 262 Optab{ALMG, C_LOREG, C_REG, C_NONE, C_REG, 98, 0}, 263 Optab{ALMG, C_LAUTO, C_REG, C_NONE, C_REG, 98, REGSP}, 264 265 // bytes 266 Optab{ABYTE, C_SCON, C_NONE, C_NONE, C_NONE, 40, 0}, 267 Optab{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 0}, 268 Optab{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 0}, 269 Optab{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 0}, 270 271 // fast synchronization 272 Optab{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 80, 0}, 273 274 // store clock 275 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SAUTO, 88, REGSP}, 276 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SOREG, 88, 0}, 277 278 // storage and storage 279 Optab{AMVC, C_SCON, C_NONE, C_LOREG, C_LOREG, 84, 0}, 280 Optab{AMVC, C_SCON, C_NONE, C_LOREG, C_LAUTO, 84, REGSP}, 281 Optab{AMVC, C_SCON, C_NONE, C_LAUTO, C_LAUTO, 84, REGSP}, 282 283 // address 284 Optab{ALARL, C_LCON, C_NONE, C_NONE, C_REG, 85, 0}, 285 Optab{ALARL, C_SYMADDR, C_NONE, C_NONE, C_REG, 85, 0}, 286 Optab{ALA, C_SOREG, C_NONE, C_NONE, C_REG, 86, 0}, 287 Optab{ALA, C_SAUTO, C_NONE, C_NONE, C_REG, 86, REGSP}, 288 Optab{AEXRL, C_SYMADDR, C_NONE, C_NONE, C_REG, 87, 0}, 289 290 // misc 291 Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 0}, 292 Optab{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0}, 293 Optab{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0}, 294 Optab{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0}, 295 Optab{obj.ANOP, C_SAUTO, C_NONE, C_NONE, C_NONE, 0, 0}, 296 297 // vector instructions 298 299 // VRX store 300 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SOREG, 100, 0}, 301 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SAUTO, 100, REGSP}, 302 Optab{AVSTEG, C_SCON, C_VREG, C_NONE, C_SOREG, 100, 0}, 303 Optab{AVSTEG, C_SCON, C_VREG, C_NONE, C_SAUTO, 100, REGSP}, 304 305 // VRX load 306 Optab{AVL, C_SOREG, C_NONE, C_NONE, C_VREG, 101, 0}, 307 Optab{AVL, C_SAUTO, C_NONE, C_NONE, C_VREG, 101, REGSP}, 308 Optab{AVLEG, C_SCON, C_NONE, C_SOREG, C_VREG, 101, 0}, 309 Optab{AVLEG, C_SCON, C_NONE, C_SAUTO, C_VREG, 101, REGSP}, 310 311 // VRV scatter 312 Optab{AVSCEG, C_SCON, C_VREG, C_NONE, C_SOREG, 102, 0}, 313 Optab{AVSCEG, C_SCON, C_VREG, C_NONE, C_SAUTO, 102, REGSP}, 314 315 // VRV gather 316 Optab{AVGEG, C_SCON, C_NONE, C_SOREG, C_VREG, 103, 0}, 317 Optab{AVGEG, C_SCON, C_NONE, C_SAUTO, C_VREG, 103, REGSP}, 318 319 // VRS element shift/rotate and load gr to/from vr element 320 Optab{AVESLG, C_SCON, C_VREG, C_NONE, C_VREG, 104, 0}, 321 Optab{AVESLG, C_REG, C_VREG, C_NONE, C_VREG, 104, 0}, 322 Optab{AVESLG, C_SCON, C_NONE, C_NONE, C_VREG, 104, 0}, 323 Optab{AVESLG, C_REG, C_NONE, C_NONE, C_VREG, 104, 0}, 324 Optab{AVLGVG, C_SCON, C_VREG, C_NONE, C_REG, 104, 0}, 325 Optab{AVLGVG, C_REG, C_VREG, C_NONE, C_REG, 104, 0}, 326 Optab{AVLVGG, C_SCON, C_REG, C_NONE, C_VREG, 104, 0}, 327 Optab{AVLVGG, C_REG, C_REG, C_NONE, C_VREG, 104, 0}, 328 329 // VRS store multiple 330 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SOREG, 105, 0}, 331 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SAUTO, 105, REGSP}, 332 333 // VRS load multiple 334 Optab{AVLM, C_SOREG, C_VREG, C_NONE, C_VREG, 106, 0}, 335 Optab{AVLM, C_SAUTO, C_VREG, C_NONE, C_VREG, 106, REGSP}, 336 337 // VRS store with length 338 Optab{AVSTL, C_REG, C_VREG, C_NONE, C_SOREG, 107, 0}, 339 Optab{AVSTL, C_REG, C_VREG, C_NONE, C_SAUTO, 107, REGSP}, 340 341 // VRS load with length 342 Optab{AVLL, C_REG, C_NONE, C_SOREG, C_VREG, 108, 0}, 343 Optab{AVLL, C_REG, C_NONE, C_SAUTO, C_VREG, 108, REGSP}, 344 345 // VRI-a 346 Optab{AVGBM, C_ANDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 347 Optab{AVZERO, C_NONE, C_NONE, C_NONE, C_VREG, 109, 0}, 348 Optab{AVREPIG, C_ADDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 349 Optab{AVREPIG, C_SCON, C_NONE, C_NONE, C_VREG, 109, 0}, 350 Optab{AVLEIG, C_SCON, C_NONE, C_ADDCON, C_VREG, 109, 0}, 351 Optab{AVLEIG, C_SCON, C_NONE, C_SCON, C_VREG, 109, 0}, 352 353 // VRI-b generate mask 354 Optab{AVGMG, C_SCON, C_NONE, C_SCON, C_VREG, 110, 0}, 355 356 // VRI-c replicate 357 Optab{AVREPG, C_UCON, C_VREG, C_NONE, C_VREG, 111, 0}, 358 359 // VRI-d element rotate and insert under mask and 360 // shift left double by byte 361 Optab{AVERIMG, C_SCON, C_VREG, C_VREG, C_VREG, 112, 0}, 362 Optab{AVSLDB, C_SCON, C_VREG, C_VREG, C_VREG, 112, 0}, 363 364 // VRI-d fp test data class immediate 365 Optab{AVFTCIDB, C_SCON, C_VREG, C_NONE, C_VREG, 113, 0}, 366 367 // VRR-a load reg 368 Optab{AVLR, C_VREG, C_NONE, C_NONE, C_VREG, 114, 0}, 369 370 // VRR-a compare 371 Optab{AVECG, C_VREG, C_NONE, C_NONE, C_VREG, 115, 0}, 372 373 // VRR-b 374 Optab{AVCEQG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 375 Optab{AVFAEF, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 376 Optab{AVPKSG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 377 378 // VRR-c 379 Optab{AVAQ, C_VREG, C_VREG, C_NONE, C_VREG, 118, 0}, 380 Optab{AVAQ, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 381 Optab{AVNOT, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 382 Optab{AVPDI, C_SCON, C_VREG, C_VREG, C_VREG, 123, 0}, 383 384 // VRR-c shifts 385 Optab{AVERLLVG, C_VREG, C_VREG, C_NONE, C_VREG, 119, 0}, 386 Optab{AVERLLVG, C_VREG, C_NONE, C_NONE, C_VREG, 119, 0}, 387 388 // VRR-d 389 // 2 3 1 4 390 Optab{AVACQ, C_VREG, C_VREG, C_VREG, C_VREG, 120, 0}, 391 392 // VRR-e 393 Optab{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 121, 0}, 394 395 // VRR-f 396 Optab{AVLVGP, C_REG, C_REG, C_NONE, C_VREG, 122, 0}, 397 } 398 399 var oprange [ALAST & obj.AMask][]Optab 400 401 var xcmp [C_NCLASS][C_NCLASS]bool 402 403 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 404 p := cursym.Func.Text 405 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 406 return 407 } 408 409 if oprange[AORW&obj.AMask] == nil { 410 ctxt.Diag("s390x ops not initialized, call s390x.buildop first") 411 } 412 413 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 414 415 buffer := make([]byte, 0) 416 changed := true 417 loop := 0 418 for changed { 419 if loop > 10 { 420 c.ctxt.Diag("stuck in spanz loop") 421 break 422 } 423 changed = false 424 buffer = buffer[:0] 425 c.cursym.R = make([]obj.Reloc, 0) 426 for p := c.cursym.Func.Text; p != nil; p = p.Link { 427 pc := int64(len(buffer)) 428 if pc != p.Pc { 429 changed = true 430 } 431 p.Pc = pc 432 c.pc = p.Pc 433 c.asmout(p, &buffer) 434 if pc == int64(len(buffer)) { 435 switch p.As { 436 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 437 // ok 438 default: 439 c.ctxt.Diag("zero-width instruction\n%v", p) 440 } 441 } 442 } 443 loop++ 444 } 445 446 c.cursym.Size = int64(len(buffer)) 447 if c.cursym.Size%funcAlign != 0 { 448 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign) 449 } 450 c.cursym.Grow(c.cursym.Size) 451 copy(c.cursym.P, buffer) 452 } 453 454 func isint32(v int64) bool { 455 return int64(int32(v)) == v 456 } 457 458 func isuint32(v uint64) bool { 459 return uint64(uint32(v)) == v 460 } 461 462 func (c *ctxtz) aclass(a *obj.Addr) int { 463 switch a.Type { 464 case obj.TYPE_NONE: 465 return C_NONE 466 467 case obj.TYPE_REG: 468 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 469 return C_REG 470 } 471 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 472 return C_FREG 473 } 474 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 475 return C_AREG 476 } 477 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 478 return C_VREG 479 } 480 return C_GOK 481 482 case obj.TYPE_MEM: 483 switch a.Name { 484 case obj.NAME_EXTERN, 485 obj.NAME_STATIC: 486 if a.Sym == nil { 487 // must have a symbol 488 break 489 } 490 c.instoffset = a.Offset 491 if a.Sym.Type == objabi.STLSBSS { 492 if c.ctxt.Flag_shared { 493 return C_TLS_IE // initial exec model 494 } 495 return C_TLS_LE // local exec model 496 } 497 return C_ADDR 498 499 case obj.NAME_GOTREF: 500 return C_GOTADDR 501 502 case obj.NAME_AUTO: 503 c.instoffset = int64(c.autosize) + a.Offset 504 if c.instoffset >= -BIG && c.instoffset < BIG { 505 return C_SAUTO 506 } 507 return C_LAUTO 508 509 case obj.NAME_PARAM: 510 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 511 if c.instoffset >= -BIG && c.instoffset < BIG { 512 return C_SAUTO 513 } 514 return C_LAUTO 515 516 case obj.NAME_NONE: 517 c.instoffset = a.Offset 518 if c.instoffset == 0 { 519 return C_ZOREG 520 } 521 if c.instoffset >= -BIG && c.instoffset < BIG { 522 return C_SOREG 523 } 524 return C_LOREG 525 } 526 527 return C_GOK 528 529 case obj.TYPE_TEXTSIZE: 530 return C_TEXTSIZE 531 532 case obj.TYPE_FCONST: 533 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 534 return C_ZCON 535 } 536 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val) 537 538 case obj.TYPE_CONST, 539 obj.TYPE_ADDR: 540 switch a.Name { 541 case obj.NAME_NONE: 542 c.instoffset = a.Offset 543 if a.Reg != 0 { 544 if -BIG <= c.instoffset && c.instoffset <= BIG { 545 return C_SACON 546 } 547 if isint32(c.instoffset) { 548 return C_LACON 549 } 550 return C_DACON 551 } 552 goto consize 553 554 case obj.NAME_EXTERN, 555 obj.NAME_STATIC: 556 s := a.Sym 557 if s == nil { 558 break 559 } 560 c.instoffset = a.Offset 561 if s.Type == objabi.SCONST { 562 goto consize 563 } 564 565 return C_SYMADDR 566 567 case obj.NAME_AUTO: 568 c.instoffset = int64(c.autosize) + a.Offset 569 if c.instoffset >= -BIG && c.instoffset < BIG { 570 return C_SACON 571 } 572 return C_LACON 573 574 case obj.NAME_PARAM: 575 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 576 if c.instoffset >= -BIG && c.instoffset < BIG { 577 return C_SACON 578 } 579 return C_LACON 580 } 581 582 return C_GOK 583 584 consize: 585 if c.instoffset == 0 { 586 return C_ZCON 587 } 588 if c.instoffset >= 0 { 589 if c.instoffset <= 0x7fff { 590 return C_SCON 591 } 592 if c.instoffset <= 0xffff { 593 return C_ANDCON 594 } 595 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 596 return C_UCON 597 } 598 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 599 return C_LCON 600 } 601 return C_DCON 602 } 603 604 if c.instoffset >= -0x8000 { 605 return C_ADDCON 606 } 607 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 608 return C_UCON 609 } 610 if isint32(c.instoffset) { 611 return C_LCON 612 } 613 return C_DCON 614 615 case obj.TYPE_BRANCH: 616 return C_SBRA 617 } 618 619 return C_GOK 620 } 621 622 func (c *ctxtz) oplook(p *obj.Prog) *Optab { 623 a1 := int(p.Optab) 624 if a1 != 0 { 625 return &optab[a1-1] 626 } 627 a1 = int(p.From.Class) 628 if a1 == 0 { 629 a1 = c.aclass(&p.From) + 1 630 p.From.Class = int8(a1) 631 } 632 633 a1-- 634 a3 := C_NONE + 1 635 if p.From3 != nil { 636 a3 = int(p.From3.Class) 637 if a3 == 0 { 638 a3 = c.aclass(p.From3) + 1 639 p.From3.Class = int8(a3) 640 } 641 } 642 643 a3-- 644 a4 := int(p.To.Class) 645 if a4 == 0 { 646 a4 = c.aclass(&p.To) + 1 647 p.To.Class = int8(a4) 648 } 649 650 a4-- 651 a2 := C_NONE 652 if p.Reg != 0 { 653 if REG_R0 <= p.Reg && p.Reg <= REG_R15 { 654 a2 = C_REG 655 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 656 a2 = C_VREG 657 } else if REG_F0 <= p.Reg && p.Reg <= REG_F15 { 658 a2 = C_FREG 659 } else if REG_AR0 <= p.Reg && p.Reg <= REG_AR15 { 660 a2 = C_AREG 661 } 662 } 663 664 ops := oprange[p.As&obj.AMask] 665 c1 := &xcmp[a1] 666 c2 := &xcmp[a2] 667 c3 := &xcmp[a3] 668 c4 := &xcmp[a4] 669 for i := range ops { 670 op := &ops[i] 671 if (int(op.a2) == a2 || c2[op.a2]) && c4[op.a4] && c1[op.a1] && c3[op.a3] { 672 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 673 return op 674 } 675 } 676 677 // cannot find a case; abort 678 c.ctxt.Diag("illegal combination %v %v %v %v %v\n", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 679 c.ctxt.Diag("prog: %v\n", p) 680 return nil 681 } 682 683 func cmp(a int, b int) bool { 684 if a == b { 685 return true 686 } 687 switch a { 688 case C_DCON: 689 if b == C_LCON { 690 return true 691 } 692 fallthrough 693 case C_LCON: 694 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 695 return true 696 } 697 698 case C_ADDCON: 699 if b == C_ZCON || b == C_SCON { 700 return true 701 } 702 703 case C_ANDCON: 704 if b == C_ZCON || b == C_SCON { 705 return true 706 } 707 708 case C_UCON: 709 if b == C_ZCON || b == C_SCON { 710 return true 711 } 712 713 case C_SCON: 714 if b == C_ZCON { 715 return true 716 } 717 718 case C_LACON: 719 if b == C_SACON { 720 return true 721 } 722 723 case C_LBRA: 724 if b == C_SBRA { 725 return true 726 } 727 728 case C_LAUTO: 729 if b == C_SAUTO { 730 return true 731 } 732 733 case C_LOREG: 734 if b == C_ZOREG || b == C_SOREG { 735 return true 736 } 737 738 case C_SOREG: 739 if b == C_ZOREG { 740 return true 741 } 742 743 case C_ANY: 744 return true 745 } 746 747 return false 748 } 749 750 type ocmp []Optab 751 752 func (x ocmp) Len() int { 753 return len(x) 754 } 755 756 func (x ocmp) Swap(i, j int) { 757 x[i], x[j] = x[j], x[i] 758 } 759 760 func (x ocmp) Less(i, j int) bool { 761 p1 := &x[i] 762 p2 := &x[j] 763 n := int(p1.as) - int(p2.as) 764 if n != 0 { 765 return n < 0 766 } 767 n = int(p1.a1) - int(p2.a1) 768 if n != 0 { 769 return n < 0 770 } 771 n = int(p1.a2) - int(p2.a2) 772 if n != 0 { 773 return n < 0 774 } 775 n = int(p1.a3) - int(p2.a3) 776 if n != 0 { 777 return n < 0 778 } 779 n = int(p1.a4) - int(p2.a4) 780 if n != 0 { 781 return n < 0 782 } 783 return false 784 } 785 func opset(a, b obj.As) { 786 oprange[a&obj.AMask] = oprange[b&obj.AMask] 787 } 788 789 func buildop(ctxt *obj.Link) { 790 if oprange[AORW&obj.AMask] != nil { 791 // Already initialized; stop now. 792 // This happens in the cmd/asm tests, 793 // each of which re-initializes the arch. 794 return 795 } 796 797 for i := 0; i < C_NCLASS; i++ { 798 for n := 0; n < C_NCLASS; n++ { 799 if cmp(n, i) { 800 xcmp[i][n] = true 801 } 802 } 803 } 804 sort.Sort(ocmp(optab)) 805 for i := 0; i < len(optab); i++ { 806 r := optab[i].as 807 start := i 808 for ; i+1 < len(optab); i++ { 809 if optab[i+1].as != r { 810 break 811 } 812 } 813 oprange[r&obj.AMask] = optab[start : i+1] 814 815 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 816 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 817 switch r { 818 case AADD: 819 opset(AADDC, r) 820 opset(AADDW, r) 821 opset(AMULLD, r) 822 opset(AMULLW, r) 823 case ADIVW: 824 opset(AADDE, r) 825 opset(ADIVD, r) 826 opset(ADIVDU, r) 827 opset(ADIVWU, r) 828 opset(AMODD, r) 829 opset(AMODDU, r) 830 opset(AMODW, r) 831 opset(AMODWU, r) 832 case AMULHD: 833 opset(AMULHDU, r) 834 case AMOVBZ: 835 opset(AMOVH, r) 836 opset(AMOVHZ, r) 837 case ALA: 838 opset(ALAY, r) 839 case AMVC: 840 opset(ACLC, r) 841 opset(AXC, r) 842 opset(AOC, r) 843 opset(ANC, r) 844 case ASTCK: 845 opset(ASTCKC, r) 846 opset(ASTCKE, r) 847 opset(ASTCKF, r) 848 case ALAAG: 849 opset(ALAA, r) 850 opset(ALAAL, r) 851 opset(ALAALG, r) 852 opset(ALAN, r) 853 opset(ALANG, r) 854 opset(ALAX, r) 855 opset(ALAXG, r) 856 opset(ALAO, r) 857 opset(ALAOG, r) 858 case ASTMG: 859 opset(ASTMY, r) 860 case ALMG: 861 opset(ALMY, r) 862 case ABEQ: 863 opset(ABGE, r) 864 opset(ABGT, r) 865 opset(ABLE, r) 866 opset(ABLT, r) 867 opset(ABNE, r) 868 opset(ABVC, r) 869 opset(ABVS, r) 870 opset(ABLEU, r) 871 opset(ABLTU, r) 872 case ABR: 873 opset(ABL, r) 874 case ABC: 875 opset(ABCL, r) 876 case AFABS: 877 opset(AFNABS, r) 878 opset(AFNEG, r) 879 opset(AFNEGS, r) 880 opset(ALEDBR, r) 881 opset(ALDEBR, r) 882 opset(AFSQRT, r) 883 opset(AFSQRTS, r) 884 case AFADD: 885 opset(AFADDS, r) 886 opset(AFDIV, r) 887 opset(AFDIVS, r) 888 opset(AFSUB, r) 889 opset(AFSUBS, r) 890 case AFMADD: 891 opset(AFMADDS, r) 892 opset(AFMSUB, r) 893 opset(AFMSUBS, r) 894 case AFMUL: 895 opset(AFMULS, r) 896 case AFCMPO: 897 opset(AFCMPU, r) 898 opset(ACEBR, r) 899 case AAND: 900 opset(AOR, r) 901 opset(AXOR, r) 902 case AANDW: 903 opset(AORW, r) 904 opset(AXORW, r) 905 case ASLD: 906 opset(ASRD, r) 907 opset(ASLW, r) 908 opset(ASRW, r) 909 opset(ASRAD, r) 910 opset(ASRAW, r) 911 opset(ARLL, r) 912 opset(ARLLG, r) 913 case ACSG: 914 opset(ACS, r) 915 case ASUB: 916 opset(ASUBC, r) 917 opset(ASUBE, r) 918 opset(ASUBW, r) 919 case ANEG: 920 opset(ANEGW, r) 921 case AFMOVD: 922 opset(AFMOVS, r) 923 case AMOVDBR: 924 opset(AMOVWBR, r) 925 case ACMP: 926 opset(ACMPW, r) 927 case ACMPU: 928 opset(ACMPWU, r) 929 case ACEFBRA: 930 opset(ACDFBRA, r) 931 opset(ACEGBRA, r) 932 opset(ACDGBRA, r) 933 opset(ACELFBR, r) 934 opset(ACDLFBR, r) 935 opset(ACELGBR, r) 936 opset(ACDLGBR, r) 937 case ACFEBRA: 938 opset(ACFDBRA, r) 939 opset(ACGEBRA, r) 940 opset(ACGDBRA, r) 941 opset(ACLFEBR, r) 942 opset(ACLFDBR, r) 943 opset(ACLGEBR, r) 944 opset(ACLGDBR, r) 945 case AFIEBR: 946 opset(AFIDBR, r) 947 case ACMPBEQ: 948 opset(ACMPBGE, r) 949 opset(ACMPBGT, r) 950 opset(ACMPBLE, r) 951 opset(ACMPBLT, r) 952 opset(ACMPBNE, r) 953 case ACMPUBEQ: 954 opset(ACMPUBGE, r) 955 opset(ACMPUBGT, r) 956 opset(ACMPUBLE, r) 957 opset(ACMPUBLT, r) 958 opset(ACMPUBNE, r) 959 case AMOVDEQ: 960 opset(AMOVDGE, r) 961 opset(AMOVDGT, r) 962 opset(AMOVDLE, r) 963 opset(AMOVDLT, r) 964 opset(AMOVDNE, r) 965 case AVL: 966 opset(AVLLEZB, r) 967 opset(AVLLEZH, r) 968 opset(AVLLEZF, r) 969 opset(AVLLEZG, r) 970 opset(AVLREPB, r) 971 opset(AVLREPH, r) 972 opset(AVLREPF, r) 973 opset(AVLREPG, r) 974 case AVLEG: 975 opset(AVLBB, r) 976 opset(AVLEB, r) 977 opset(AVLEH, r) 978 opset(AVLEF, r) 979 opset(AVLEG, r) 980 opset(AVLREP, r) 981 case AVSTEG: 982 opset(AVSTEB, r) 983 opset(AVSTEH, r) 984 opset(AVSTEF, r) 985 case AVSCEG: 986 opset(AVSCEF, r) 987 case AVGEG: 988 opset(AVGEF, r) 989 case AVESLG: 990 opset(AVESLB, r) 991 opset(AVESLH, r) 992 opset(AVESLF, r) 993 opset(AVERLLB, r) 994 opset(AVERLLH, r) 995 opset(AVERLLF, r) 996 opset(AVERLLG, r) 997 opset(AVESRAB, r) 998 opset(AVESRAH, r) 999 opset(AVESRAF, r) 1000 opset(AVESRAG, r) 1001 opset(AVESRLB, r) 1002 opset(AVESRLH, r) 1003 opset(AVESRLF, r) 1004 opset(AVESRLG, r) 1005 case AVLGVG: 1006 opset(AVLGVB, r) 1007 opset(AVLGVH, r) 1008 opset(AVLGVF, r) 1009 case AVLVGG: 1010 opset(AVLVGB, r) 1011 opset(AVLVGH, r) 1012 opset(AVLVGF, r) 1013 case AVZERO: 1014 opset(AVONE, r) 1015 case AVREPIG: 1016 opset(AVREPIB, r) 1017 opset(AVREPIH, r) 1018 opset(AVREPIF, r) 1019 case AVLEIG: 1020 opset(AVLEIB, r) 1021 opset(AVLEIH, r) 1022 opset(AVLEIF, r) 1023 case AVGMG: 1024 opset(AVGMB, r) 1025 opset(AVGMH, r) 1026 opset(AVGMF, r) 1027 case AVREPG: 1028 opset(AVREPB, r) 1029 opset(AVREPH, r) 1030 opset(AVREPF, r) 1031 case AVERIMG: 1032 opset(AVERIMB, r) 1033 opset(AVERIMH, r) 1034 opset(AVERIMF, r) 1035 case AVFTCIDB: 1036 opset(AWFTCIDB, r) 1037 case AVLR: 1038 opset(AVUPHB, r) 1039 opset(AVUPHH, r) 1040 opset(AVUPHF, r) 1041 opset(AVUPLHB, r) 1042 opset(AVUPLHH, r) 1043 opset(AVUPLHF, r) 1044 opset(AVUPLB, r) 1045 opset(AVUPLHW, r) 1046 opset(AVUPLF, r) 1047 opset(AVUPLLB, r) 1048 opset(AVUPLLH, r) 1049 opset(AVUPLLF, r) 1050 opset(AVCLZB, r) 1051 opset(AVCLZH, r) 1052 opset(AVCLZF, r) 1053 opset(AVCLZG, r) 1054 opset(AVCTZB, r) 1055 opset(AVCTZH, r) 1056 opset(AVCTZF, r) 1057 opset(AVCTZG, r) 1058 opset(AVLDEB, r) 1059 opset(AWLDEB, r) 1060 opset(AVFLCDB, r) 1061 opset(AWFLCDB, r) 1062 opset(AVFLNDB, r) 1063 opset(AWFLNDB, r) 1064 opset(AVFLPDB, r) 1065 opset(AWFLPDB, r) 1066 opset(AVFSQDB, r) 1067 opset(AWFSQDB, r) 1068 opset(AVISTRB, r) 1069 opset(AVISTRH, r) 1070 opset(AVISTRF, r) 1071 opset(AVISTRBS, r) 1072 opset(AVISTRHS, r) 1073 opset(AVISTRFS, r) 1074 opset(AVLCB, r) 1075 opset(AVLCH, r) 1076 opset(AVLCF, r) 1077 opset(AVLCG, r) 1078 opset(AVLPB, r) 1079 opset(AVLPH, r) 1080 opset(AVLPF, r) 1081 opset(AVLPG, r) 1082 opset(AVPOPCT, r) 1083 opset(AVSEGB, r) 1084 opset(AVSEGH, r) 1085 opset(AVSEGF, r) 1086 case AVECG: 1087 opset(AVECB, r) 1088 opset(AVECH, r) 1089 opset(AVECF, r) 1090 opset(AVECLB, r) 1091 opset(AVECLH, r) 1092 opset(AVECLF, r) 1093 opset(AVECLG, r) 1094 opset(AWFCDB, r) 1095 opset(AWFKDB, r) 1096 case AVCEQG: 1097 opset(AVCEQB, r) 1098 opset(AVCEQH, r) 1099 opset(AVCEQF, r) 1100 opset(AVCEQBS, r) 1101 opset(AVCEQHS, r) 1102 opset(AVCEQFS, r) 1103 opset(AVCEQGS, r) 1104 opset(AVCHB, r) 1105 opset(AVCHH, r) 1106 opset(AVCHF, r) 1107 opset(AVCHG, r) 1108 opset(AVCHBS, r) 1109 opset(AVCHHS, r) 1110 opset(AVCHFS, r) 1111 opset(AVCHGS, r) 1112 opset(AVCHLB, r) 1113 opset(AVCHLH, r) 1114 opset(AVCHLF, r) 1115 opset(AVCHLG, r) 1116 opset(AVCHLBS, r) 1117 opset(AVCHLHS, r) 1118 opset(AVCHLFS, r) 1119 opset(AVCHLGS, r) 1120 case AVFAEF: 1121 opset(AVFAEB, r) 1122 opset(AVFAEH, r) 1123 opset(AVFAEBS, r) 1124 opset(AVFAEHS, r) 1125 opset(AVFAEFS, r) 1126 opset(AVFAEZB, r) 1127 opset(AVFAEZH, r) 1128 opset(AVFAEZF, r) 1129 opset(AVFAEZBS, r) 1130 opset(AVFAEZHS, r) 1131 opset(AVFAEZFS, r) 1132 opset(AVFEEB, r) 1133 opset(AVFEEH, r) 1134 opset(AVFEEF, r) 1135 opset(AVFEEBS, r) 1136 opset(AVFEEHS, r) 1137 opset(AVFEEFS, r) 1138 opset(AVFEEZB, r) 1139 opset(AVFEEZH, r) 1140 opset(AVFEEZF, r) 1141 opset(AVFEEZBS, r) 1142 opset(AVFEEZHS, r) 1143 opset(AVFEEZFS, r) 1144 opset(AVFENEB, r) 1145 opset(AVFENEH, r) 1146 opset(AVFENEF, r) 1147 opset(AVFENEBS, r) 1148 opset(AVFENEHS, r) 1149 opset(AVFENEFS, r) 1150 opset(AVFENEZB, r) 1151 opset(AVFENEZH, r) 1152 opset(AVFENEZF, r) 1153 opset(AVFENEZBS, r) 1154 opset(AVFENEZHS, r) 1155 opset(AVFENEZFS, r) 1156 case AVPKSG: 1157 opset(AVPKSH, r) 1158 opset(AVPKSF, r) 1159 opset(AVPKSHS, r) 1160 opset(AVPKSFS, r) 1161 opset(AVPKSGS, r) 1162 opset(AVPKLSH, r) 1163 opset(AVPKLSF, r) 1164 opset(AVPKLSG, r) 1165 opset(AVPKLSHS, r) 1166 opset(AVPKLSFS, r) 1167 opset(AVPKLSGS, r) 1168 case AVAQ: 1169 opset(AVAB, r) 1170 opset(AVAH, r) 1171 opset(AVAF, r) 1172 opset(AVAG, r) 1173 opset(AVACCB, r) 1174 opset(AVACCH, r) 1175 opset(AVACCF, r) 1176 opset(AVACCG, r) 1177 opset(AVACCQ, r) 1178 opset(AVN, r) 1179 opset(AVNC, r) 1180 opset(AVAVGB, r) 1181 opset(AVAVGH, r) 1182 opset(AVAVGF, r) 1183 opset(AVAVGG, r) 1184 opset(AVAVGLB, r) 1185 opset(AVAVGLH, r) 1186 opset(AVAVGLF, r) 1187 opset(AVAVGLG, r) 1188 opset(AVCKSM, r) 1189 opset(AVX, r) 1190 opset(AVFADB, r) 1191 opset(AWFADB, r) 1192 opset(AVFCEDB, r) 1193 opset(AVFCEDBS, r) 1194 opset(AWFCEDB, r) 1195 opset(AWFCEDBS, r) 1196 opset(AVFCHDB, r) 1197 opset(AVFCHDBS, r) 1198 opset(AWFCHDB, r) 1199 opset(AWFCHDBS, r) 1200 opset(AVFCHEDB, r) 1201 opset(AVFCHEDBS, r) 1202 opset(AWFCHEDB, r) 1203 opset(AWFCHEDBS, r) 1204 opset(AVFMDB, r) 1205 opset(AWFMDB, r) 1206 opset(AVGFMB, r) 1207 opset(AVGFMH, r) 1208 opset(AVGFMF, r) 1209 opset(AVGFMG, r) 1210 opset(AVMXB, r) 1211 opset(AVMXH, r) 1212 opset(AVMXF, r) 1213 opset(AVMXG, r) 1214 opset(AVMXLB, r) 1215 opset(AVMXLH, r) 1216 opset(AVMXLF, r) 1217 opset(AVMXLG, r) 1218 opset(AVMNB, r) 1219 opset(AVMNH, r) 1220 opset(AVMNF, r) 1221 opset(AVMNG, r) 1222 opset(AVMNLB, r) 1223 opset(AVMNLH, r) 1224 opset(AVMNLF, r) 1225 opset(AVMNLG, r) 1226 opset(AVMRHB, r) 1227 opset(AVMRHH, r) 1228 opset(AVMRHF, r) 1229 opset(AVMRHG, r) 1230 opset(AVMRLB, r) 1231 opset(AVMRLH, r) 1232 opset(AVMRLF, r) 1233 opset(AVMRLG, r) 1234 opset(AVMEB, r) 1235 opset(AVMEH, r) 1236 opset(AVMEF, r) 1237 opset(AVMLEB, r) 1238 opset(AVMLEH, r) 1239 opset(AVMLEF, r) 1240 opset(AVMOB, r) 1241 opset(AVMOH, r) 1242 opset(AVMOF, r) 1243 opset(AVMLOB, r) 1244 opset(AVMLOH, r) 1245 opset(AVMLOF, r) 1246 opset(AVMHB, r) 1247 opset(AVMHH, r) 1248 opset(AVMHF, r) 1249 opset(AVMLHB, r) 1250 opset(AVMLHH, r) 1251 opset(AVMLHF, r) 1252 opset(AVMLH, r) 1253 opset(AVMLHW, r) 1254 opset(AVMLF, r) 1255 opset(AVNO, r) 1256 opset(AVO, r) 1257 opset(AVPKH, r) 1258 opset(AVPKF, r) 1259 opset(AVPKG, r) 1260 opset(AVSUMGH, r) 1261 opset(AVSUMGF, r) 1262 opset(AVSUMQF, r) 1263 opset(AVSUMQG, r) 1264 opset(AVSUMB, r) 1265 opset(AVSUMH, r) 1266 case AVERLLVG: 1267 opset(AVERLLVB, r) 1268 opset(AVERLLVH, r) 1269 opset(AVERLLVF, r) 1270 opset(AVESLVB, r) 1271 opset(AVESLVH, r) 1272 opset(AVESLVF, r) 1273 opset(AVESLVG, r) 1274 opset(AVESRAVB, r) 1275 opset(AVESRAVH, r) 1276 opset(AVESRAVF, r) 1277 opset(AVESRAVG, r) 1278 opset(AVESRLVB, r) 1279 opset(AVESRLVH, r) 1280 opset(AVESRLVF, r) 1281 opset(AVESRLVG, r) 1282 opset(AVFDDB, r) 1283 opset(AWFDDB, r) 1284 opset(AVFSDB, r) 1285 opset(AWFSDB, r) 1286 opset(AVSL, r) 1287 opset(AVSLB, r) 1288 opset(AVSRA, r) 1289 opset(AVSRAB, r) 1290 opset(AVSRL, r) 1291 opset(AVSRLB, r) 1292 opset(AVSF, r) 1293 opset(AVSG, r) 1294 opset(AVSQ, r) 1295 opset(AVSCBIB, r) 1296 opset(AVSCBIH, r) 1297 opset(AVSCBIF, r) 1298 opset(AVSCBIG, r) 1299 opset(AVSCBIQ, r) 1300 case AVACQ: 1301 opset(AVACCCQ, r) 1302 opset(AVGFMAB, r) 1303 opset(AVGFMAH, r) 1304 opset(AVGFMAF, r) 1305 opset(AVGFMAG, r) 1306 opset(AVMALB, r) 1307 opset(AVMALHW, r) 1308 opset(AVMALF, r) 1309 opset(AVMAHB, r) 1310 opset(AVMAHH, r) 1311 opset(AVMAHF, r) 1312 opset(AVMALHB, r) 1313 opset(AVMALHH, r) 1314 opset(AVMALHF, r) 1315 opset(AVMAEB, r) 1316 opset(AVMAEH, r) 1317 opset(AVMAEF, r) 1318 opset(AVMALEB, r) 1319 opset(AVMALEH, r) 1320 opset(AVMALEF, r) 1321 opset(AVMAOB, r) 1322 opset(AVMAOH, r) 1323 opset(AVMAOF, r) 1324 opset(AVMALOB, r) 1325 opset(AVMALOH, r) 1326 opset(AVMALOF, r) 1327 opset(AVSTRCB, r) 1328 opset(AVSTRCH, r) 1329 opset(AVSTRCF, r) 1330 opset(AVSTRCBS, r) 1331 opset(AVSTRCHS, r) 1332 opset(AVSTRCFS, r) 1333 opset(AVSTRCZB, r) 1334 opset(AVSTRCZH, r) 1335 opset(AVSTRCZF, r) 1336 opset(AVSTRCZBS, r) 1337 opset(AVSTRCZHS, r) 1338 opset(AVSTRCZFS, r) 1339 opset(AVSBCBIQ, r) 1340 opset(AVSBIQ, r) 1341 case AVSEL: 1342 opset(AVFMADB, r) 1343 opset(AWFMADB, r) 1344 opset(AVFMSDB, r) 1345 opset(AWFMSDB, r) 1346 opset(AVPERM, r) 1347 } 1348 } 1349 } 1350 1351 const ( 1352 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1353 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1354 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1355 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1356 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1357 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1358 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1359 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1360 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1361 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1362 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1363 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1364 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1365 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1366 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1367 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1368 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1369 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1370 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1371 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1372 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1373 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1374 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1375 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1376 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1377 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1378 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1379 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1380 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1381 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1382 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1383 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1384 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1385 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1386 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1387 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1388 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1389 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1390 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1391 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1392 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1393 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1394 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1395 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1396 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1397 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1398 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1399 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1400 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1401 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1402 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1403 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1404 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1405 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1406 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1407 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1408 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1409 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1410 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1411 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1412 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1413 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1414 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1415 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1416 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1417 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1418 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1419 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1420 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1421 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1422 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1423 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1424 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1425 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1426 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1427 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1428 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1429 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1430 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1431 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1432 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1433 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1434 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1435 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1436 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1437 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1438 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1439 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1440 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1441 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1442 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1443 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1444 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1445 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1446 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1447 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1448 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1449 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1450 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1451 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1452 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1453 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1454 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1455 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1456 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1457 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1458 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1459 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1460 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1461 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1462 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1463 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1464 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1465 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1466 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1467 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1468 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1469 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1470 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1471 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1472 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1473 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1474 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1475 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1476 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1477 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1478 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1479 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1480 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1481 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1482 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1483 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1484 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1485 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1486 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1487 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1488 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1489 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1490 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1491 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1492 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1493 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1494 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1495 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1496 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1497 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1498 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1499 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1500 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1501 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1502 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1503 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1504 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1505 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1506 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1507 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1508 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1509 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1510 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1511 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1512 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1513 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1514 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1515 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1516 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1517 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1518 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1519 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1520 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1521 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1522 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1523 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1524 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1525 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1526 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1527 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1528 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1529 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1530 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1531 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1532 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1533 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1534 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1535 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1536 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1537 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1538 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1539 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1540 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1541 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1542 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1543 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1544 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1545 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1546 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1547 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1548 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1549 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1550 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1551 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1552 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1553 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1554 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1555 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1556 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1557 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1558 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1559 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1560 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1561 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1562 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1563 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1564 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1565 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1566 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1567 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1568 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1569 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1570 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1571 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1572 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1573 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1574 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1575 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1576 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1577 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1578 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1579 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1580 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1581 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1582 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1583 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1584 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1585 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1586 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1587 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1588 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1589 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1590 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1591 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1592 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1593 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1594 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1595 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1596 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1597 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1598 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1599 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1600 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1601 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1602 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1603 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1604 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1605 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1606 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1607 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1608 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1609 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1610 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1611 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1612 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1613 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1614 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1615 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1616 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1617 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1618 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1619 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1620 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1621 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1622 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1623 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1624 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1625 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1626 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1627 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1628 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1629 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1630 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1631 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1632 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1633 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1634 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1635 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1636 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1637 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1638 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1639 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1640 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1641 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1642 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1643 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1644 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1645 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1646 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1647 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1648 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1649 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1650 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1651 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1652 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1653 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1654 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1655 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1656 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1657 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1658 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1659 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1660 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1661 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1662 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1663 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1664 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1665 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1666 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1667 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1668 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1669 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1670 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1671 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1672 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1673 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1674 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1675 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1676 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1677 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1678 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1679 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1680 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1681 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1682 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1683 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1684 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1685 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1686 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1687 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1688 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1689 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1690 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1691 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1692 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1693 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1694 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1695 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1696 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1697 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1698 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1699 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1700 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1701 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1702 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1703 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1704 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1705 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1706 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1707 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1708 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1709 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1710 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1711 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1712 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1713 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1714 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1715 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1716 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1717 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1718 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1719 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1720 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1721 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1722 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1723 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1724 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1725 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1726 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1727 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1728 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1729 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1730 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1731 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1732 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1733 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1734 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1735 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1736 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1737 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1738 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1739 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1740 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1741 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1742 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1743 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1744 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1745 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1746 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1747 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1748 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1749 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1750 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1751 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1752 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1753 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1754 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1755 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1756 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1757 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1758 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1759 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1760 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1761 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1762 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1763 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1764 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1765 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1766 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1767 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1768 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1769 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1770 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1771 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1772 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1773 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1774 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1775 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1776 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1777 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1778 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1779 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1780 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1781 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1782 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1783 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1784 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1785 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1786 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1787 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1788 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1789 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1790 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1791 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1792 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1793 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1794 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1795 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1796 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1797 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1798 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1799 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1800 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1801 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1802 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1803 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1804 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1805 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1806 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1807 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1808 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1809 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1810 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1811 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1812 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1813 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1814 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1815 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1816 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1817 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1818 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1819 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1820 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1821 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1822 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1823 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1824 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1825 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1826 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1827 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1828 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1829 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1830 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1831 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1832 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1833 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1834 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1835 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1836 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1837 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1838 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1839 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1840 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1841 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1842 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1843 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1844 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 1845 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 1846 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 1847 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 1848 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 1849 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 1850 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 1851 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 1852 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 1853 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 1854 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 1855 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 1856 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 1857 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 1858 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 1859 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 1860 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 1861 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 1862 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 1863 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 1864 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 1865 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 1866 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 1867 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 1868 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 1869 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 1870 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 1871 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 1872 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 1873 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 1874 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 1875 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 1876 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 1877 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 1878 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 1879 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 1880 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 1881 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 1882 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 1883 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 1884 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 1885 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 1886 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 1887 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 1888 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 1889 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 1890 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 1891 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 1892 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 1893 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 1894 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 1895 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 1896 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 1897 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 1898 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 1899 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 1900 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 1901 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 1902 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 1903 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1904 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1905 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 1906 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 1907 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 1908 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 1909 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 1910 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 1911 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 1912 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 1913 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 1914 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 1915 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 1916 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 1917 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 1918 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 1919 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 1920 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 1921 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 1922 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 1923 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 1924 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 1925 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 1926 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 1927 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 1928 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 1929 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 1930 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 1931 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 1932 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 1933 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 1934 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 1935 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 1936 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 1937 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 1938 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 1939 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 1940 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 1941 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 1942 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 1943 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 1944 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 1945 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 1946 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 1947 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 1948 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 1949 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 1950 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1951 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1952 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1953 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1954 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1955 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1956 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 1957 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 1958 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 1959 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 1960 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1961 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 1962 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 1963 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1964 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 1965 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1966 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1967 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1968 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 1969 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 1970 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 1971 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 1972 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1973 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 1974 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 1975 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 1976 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 1977 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 1978 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 1979 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 1980 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 1981 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 1982 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 1983 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 1984 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 1985 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 1986 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 1987 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 1988 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 1989 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 1990 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 1991 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 1992 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 1993 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 1994 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 1995 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 1996 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 1997 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 1998 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 1999 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 2000 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 2001 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 2002 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 2003 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 2004 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 2005 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 2006 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 2007 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 2008 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 2009 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 2010 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 2011 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 2012 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 2013 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 2014 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 2015 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 2016 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 2017 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 2018 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 2019 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 2020 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 2021 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 2022 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 2023 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 2024 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 2025 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 2026 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 2027 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 2028 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 2029 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 2030 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2031 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2032 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 2033 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 2034 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 2035 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 2036 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 2037 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 2038 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 2039 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 2040 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 2041 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 2042 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 2043 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 2044 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 2045 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 2046 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 2047 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 2048 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2049 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2050 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2051 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2052 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2053 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2054 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2055 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2056 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2057 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2058 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2059 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2060 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2061 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2062 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2063 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2064 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2065 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2066 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2067 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2068 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2069 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2070 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2071 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2072 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2073 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2074 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2075 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2076 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2077 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2078 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2079 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2080 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2081 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2082 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2083 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2084 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2085 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2086 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2087 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2088 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2089 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2090 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2091 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2092 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2093 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2094 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2095 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2096 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2097 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2098 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2099 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2100 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2101 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2102 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2103 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2104 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2105 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2106 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2107 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2108 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2109 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2110 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2111 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2112 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2113 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2114 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2115 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2116 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2117 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2118 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2119 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2120 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2121 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2122 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2123 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2124 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2125 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2126 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2127 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2128 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2129 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2130 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2131 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2132 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2133 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2134 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2135 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2136 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2137 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2138 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2139 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2140 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2141 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2142 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2143 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2144 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2145 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2146 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2147 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2148 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2149 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2150 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2151 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2152 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2153 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2154 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2155 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2156 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2157 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2158 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2159 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2160 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2161 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2162 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2163 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2164 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2165 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2166 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2167 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2168 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2169 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2170 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2171 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2172 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2173 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2174 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2175 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2176 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2177 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2178 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2179 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2180 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2181 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2182 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2183 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2184 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2185 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2186 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2187 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2188 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2189 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2190 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2191 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2192 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2193 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2194 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2195 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2196 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2197 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2198 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2199 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2200 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2201 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2202 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2203 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2204 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2205 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2206 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2207 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2208 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2209 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2210 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2211 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2212 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2213 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2214 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2215 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2216 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2217 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2218 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2219 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2220 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2221 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2222 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2223 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2224 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2225 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2226 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2227 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2228 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2229 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2230 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2231 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2232 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2233 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2234 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2235 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2236 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2237 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2238 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2239 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2240 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2241 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2242 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2243 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2244 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2245 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2246 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2247 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2248 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2249 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2250 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2251 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2252 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2253 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2254 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2255 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2256 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2257 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2258 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2259 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2260 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2261 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2262 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2263 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2264 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2265 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2266 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2267 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2268 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2269 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2270 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2271 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2272 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2273 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2274 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2275 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2276 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2277 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2278 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2279 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2280 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2281 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2282 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2283 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2284 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2285 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2286 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2287 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2288 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2289 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2290 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2291 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2292 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2293 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2294 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2295 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2296 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2297 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2298 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2299 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2300 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2301 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2302 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2303 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2304 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2305 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2306 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2307 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2308 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2309 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2310 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2311 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2312 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2313 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2314 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2315 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2316 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2317 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2318 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2319 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2320 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2321 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2322 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2323 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2324 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2325 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2326 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2327 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2328 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2329 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2330 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2331 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2332 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2333 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2334 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2335 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2336 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2337 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2338 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2339 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2340 2341 // added in z13 2342 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2343 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2344 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2345 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2346 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2347 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2348 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2349 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2350 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2351 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2352 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2353 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2354 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2355 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2356 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2357 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2358 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2359 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2360 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2361 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2362 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2363 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2364 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2365 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2366 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2367 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2368 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2369 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2370 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2371 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2372 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2373 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2374 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2375 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2376 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2377 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2378 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2379 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2380 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2381 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2382 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2383 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2384 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2385 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2386 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2387 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2388 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2389 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2390 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2391 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2392 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2393 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2394 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2395 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2396 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2397 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2398 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2399 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2400 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2401 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2402 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2403 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2404 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2405 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2406 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2407 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2408 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2409 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2410 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2411 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2412 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2413 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2414 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2415 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2416 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2417 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2418 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2419 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2420 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2421 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2422 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2423 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2424 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2425 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2426 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2427 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2428 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2429 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2430 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2431 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2432 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2433 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2434 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2435 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2436 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2437 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2438 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2439 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2440 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2441 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2442 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2443 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2444 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2445 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2446 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2447 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2448 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2449 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2450 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2451 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2452 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2453 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2454 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2455 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2456 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2457 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2458 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2459 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2460 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2461 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2462 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2463 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2464 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2465 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2466 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2467 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2468 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2469 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2470 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2471 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2472 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2473 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2474 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2475 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2476 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2477 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2478 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2479 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2480 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2481 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2482 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2483 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2484 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2485 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2486 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2487 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2488 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2489 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2490 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2491 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2492 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2493 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2494 ) 2495 2496 func oclass(a *obj.Addr) int { 2497 return int(a.Class) - 1 2498 } 2499 2500 // Add a relocation for the immediate in a RIL style instruction. 2501 // The addend will be adjusted as required. 2502 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) *obj.Reloc { 2503 if sym == nil { 2504 c.ctxt.Diag("require symbol to apply relocation") 2505 } 2506 offset := int64(2) // relocation offset from start of instruction 2507 rel := obj.Addrel(c.cursym) 2508 rel.Off = int32(c.pc + offset) 2509 rel.Siz = 4 2510 rel.Sym = sym 2511 rel.Add = add + offset + int64(rel.Siz) 2512 rel.Type = objabi.R_PCRELDBL 2513 return rel 2514 } 2515 2516 func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) *obj.Reloc { 2517 if sym == nil { 2518 c.ctxt.Diag("require symbol to apply relocation") 2519 } 2520 offset += int64(2) // relocation offset from start of instruction 2521 rel := obj.Addrel(c.cursym) 2522 rel.Off = int32(c.pc + offset) 2523 rel.Siz = 4 2524 rel.Sym = sym 2525 rel.Add = add + offset + int64(rel.Siz) 2526 rel.Type = objabi.R_PCRELDBL 2527 return rel 2528 } 2529 2530 // Add a CALL relocation for the immediate in a RIL style instruction. 2531 // The addend will be adjusted as required. 2532 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) *obj.Reloc { 2533 if sym == nil { 2534 c.ctxt.Diag("require symbol to apply relocation") 2535 } 2536 offset := int64(2) // relocation offset from start of instruction 2537 rel := obj.Addrel(c.cursym) 2538 rel.Off = int32(c.pc + offset) 2539 rel.Siz = 4 2540 rel.Sym = sym 2541 rel.Add = add + offset + int64(rel.Siz) 2542 rel.Type = objabi.R_CALL 2543 return rel 2544 } 2545 2546 func (c *ctxtz) branchMask(p *obj.Prog) uint32 { 2547 switch p.As { 2548 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ: 2549 return 0x8 2550 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE: 2551 return 0xA 2552 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT: 2553 return 0x2 2554 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE: 2555 return 0xC 2556 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT: 2557 return 0x4 2558 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE: 2559 return 0x7 2560 case ABLEU: // LE or unordered 2561 return 0xD 2562 case ABLTU: // LT or unordered 2563 return 0x5 2564 case ABVC: 2565 return 0x0 // needs extra instruction 2566 case ABVS: 2567 return 0x1 // unordered 2568 } 2569 c.ctxt.Diag("unknown conditional branch %v", p.As) 2570 return 0xF 2571 } 2572 2573 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) { 2574 o := c.oplook(p) 2575 2576 switch o.type_ { 2577 default: 2578 c.ctxt.Diag("unknown type %d", o.type_) 2579 2580 case 0: // PSEUDO OPS 2581 break 2582 2583 case 1: // mov reg reg 2584 switch p.As { 2585 default: 2586 c.ctxt.Diag("unhandled operation: %v", p.As) 2587 case AMOVD: 2588 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2589 // sign extend 2590 case AMOVW: 2591 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2592 case AMOVH: 2593 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2594 case AMOVB: 2595 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2596 // zero extend 2597 case AMOVWZ: 2598 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2599 case AMOVHZ: 2600 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2601 case AMOVBZ: 2602 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2603 // reverse bytes 2604 case AMOVDBR: 2605 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2606 case AMOVWBR: 2607 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2608 // floating point 2609 case AFMOVD, AFMOVS: 2610 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2611 } 2612 2613 case 2: // arithmetic op reg [reg] reg 2614 r := p.Reg 2615 if r == 0 { 2616 r = p.To.Reg 2617 } 2618 2619 var opcode uint32 2620 2621 switch p.As { 2622 default: 2623 c.ctxt.Diag("invalid opcode") 2624 case AADD: 2625 opcode = op_AGRK 2626 case AADDC: 2627 opcode = op_ALGRK 2628 case AADDE: 2629 opcode = op_ALCGR 2630 case AADDW: 2631 opcode = op_ARK 2632 case AMULLW: 2633 opcode = op_MSGFR 2634 case AMULLD: 2635 opcode = op_MSGR 2636 case ADIVW, AMODW: 2637 opcode = op_DSGFR 2638 case ADIVWU, AMODWU: 2639 opcode = op_DLR 2640 case ADIVD, AMODD: 2641 opcode = op_DSGR 2642 case ADIVDU, AMODDU: 2643 opcode = op_DLGR 2644 } 2645 2646 switch p.As { 2647 default: 2648 2649 case AADD, AADDC, AADDW: 2650 if p.As == AADDW && r == p.To.Reg { 2651 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2652 } else { 2653 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2654 } 2655 2656 case AADDE, AMULLW, AMULLD: 2657 if r == p.To.Reg { 2658 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2659 } else if p.From.Reg == p.To.Reg { 2660 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2661 } else { 2662 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2663 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2664 } 2665 2666 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2667 if p.As == ADIVWU || p.As == ADIVDU { 2668 zRI(op_LGHI, REGTMP, 0, asm) 2669 } 2670 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2671 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2672 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2673 2674 case AMODW, AMODWU, AMODD, AMODDU: 2675 if p.As == AMODWU || p.As == AMODDU { 2676 zRI(op_LGHI, REGTMP, 0, asm) 2677 } 2678 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2679 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2680 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2681 2682 } 2683 2684 case 3: // mov $constant reg 2685 v := c.vregoff(&p.From) 2686 switch p.As { 2687 case AMOVBZ: 2688 v = int64(uint8(v)) 2689 case AMOVHZ: 2690 v = int64(uint16(v)) 2691 case AMOVWZ: 2692 v = int64(uint32(v)) 2693 case AMOVB: 2694 v = int64(int8(v)) 2695 case AMOVH: 2696 v = int64(int16(v)) 2697 case AMOVW: 2698 v = int64(int32(v)) 2699 } 2700 if int64(int16(v)) == v { 2701 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2702 } else if v&0xffff0000 == v { 2703 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2704 } else if v&0xffff00000000 == v { 2705 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2706 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2707 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2708 } else if int64(int32(v)) == v { 2709 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2710 } else if int64(uint32(v)) == v { 2711 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2712 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2713 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2714 } else { 2715 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2716 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2717 } 2718 2719 case 4: // multiply high (a*b)>>64 2720 r := p.Reg 2721 if r == 0 { 2722 r = p.To.Reg 2723 } 2724 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2725 zRRE(op_MLGR, REGTMP, uint32(p.From.Reg), asm) 2726 switch p.As { 2727 case AMULHDU: 2728 // Unsigned: move result into correct register. 2729 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2730 case AMULHD: 2731 // Signed: need to convert result. 2732 // See Hacker's Delight 8-3. 2733 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm) 2734 zRRE(op_NGR, REGTMP2, uint32(r), asm) 2735 zRRE(op_SGR, REGTMP, REGTMP2, asm) 2736 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm) 2737 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm) 2738 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), REGTMP, asm) 2739 } 2740 2741 case 5: // syscall 2742 zI(op_SVC, 0, asm) 2743 2744 case 6: // logical op reg [reg] reg 2745 var oprr, oprre, oprrf uint32 2746 switch p.As { 2747 case AAND: 2748 oprre = op_NGR 2749 oprrf = op_NGRK 2750 case AANDW: 2751 oprr = op_NR 2752 oprrf = op_NRK 2753 case AOR: 2754 oprre = op_OGR 2755 oprrf = op_OGRK 2756 case AORW: 2757 oprr = op_OR 2758 oprrf = op_ORK 2759 case AXOR: 2760 oprre = op_XGR 2761 oprrf = op_XGRK 2762 case AXORW: 2763 oprr = op_XR 2764 oprrf = op_XRK 2765 } 2766 if p.Reg == 0 { 2767 if oprr != 0 { 2768 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2769 } else { 2770 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2771 } 2772 } else { 2773 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2774 } 2775 2776 case 7: // shift/rotate reg [reg] reg 2777 d2 := c.vregoff(&p.From) 2778 b2 := p.From.Reg 2779 r3 := p.Reg 2780 if r3 == 0 { 2781 r3 = p.To.Reg 2782 } 2783 r1 := p.To.Reg 2784 var opcode uint32 2785 switch p.As { 2786 default: 2787 case ASLD: 2788 opcode = op_SLLG 2789 case ASRD: 2790 opcode = op_SRLG 2791 case ASLW: 2792 opcode = op_SLLK 2793 case ASRW: 2794 opcode = op_SRLK 2795 case ARLL: 2796 opcode = op_RLL 2797 case ARLLG: 2798 opcode = op_RLLG 2799 case ASRAW: 2800 opcode = op_SRAK 2801 case ASRAD: 2802 opcode = op_SRAG 2803 } 2804 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2805 2806 case 8: // find leftmost one 2807 if p.To.Reg&1 != 0 { 2808 c.ctxt.Diag("target must be an even-numbered register") 2809 } 2810 // FLOGR also writes a mask to p.To.Reg+1. 2811 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2812 2813 case 10: // subtract reg [reg] reg 2814 r := int(p.Reg) 2815 2816 switch p.As { 2817 default: 2818 case ASUB: 2819 if r == 0 { 2820 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2821 } else { 2822 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2823 } 2824 case ASUBC: 2825 if r == 0 { 2826 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2827 } else { 2828 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2829 } 2830 case ASUBE: 2831 if r == 0 { 2832 r = int(p.To.Reg) 2833 } 2834 if r == int(p.To.Reg) { 2835 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2836 } else if p.From.Reg == p.To.Reg { 2837 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 2838 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2839 zRRE(op_SLBGR, uint32(p.To.Reg), REGTMP, asm) 2840 } else { 2841 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2842 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2843 } 2844 case ASUBW: 2845 if r == 0 { 2846 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2847 } else { 2848 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2849 } 2850 } 2851 2852 case 11: // br/bl 2853 v := int32(0) 2854 2855 if p.Pcond != nil { 2856 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2857 } 2858 2859 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 2860 zRI(op_BRC, 0xF, uint32(v), asm) 2861 } else { 2862 if p.As == ABL { 2863 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 2864 } else { 2865 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 2866 } 2867 if p.To.Sym != nil { 2868 c.addcallreloc(p.To.Sym, p.To.Offset) 2869 } 2870 } 2871 2872 case 12: 2873 r1 := p.To.Reg 2874 d2 := c.vregoff(&p.From) 2875 b2 := p.From.Reg 2876 if b2 == 0 { 2877 b2 = o.param 2878 } 2879 x2 := p.From.Index 2880 if -DISP20/2 > d2 || d2 >= DISP20/2 { 2881 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 2882 if x2 != 0 { 2883 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 2884 } 2885 x2 = REGTMP 2886 d2 = 0 2887 } 2888 var opx, opxy uint32 2889 switch p.As { 2890 case AADD: 2891 opxy = op_AG 2892 case AADDC: 2893 opxy = op_ALG 2894 case AADDW: 2895 opx = op_A 2896 opxy = op_AY 2897 case AMULLW: 2898 opx = op_MS 2899 opxy = op_MSY 2900 case AMULLD: 2901 opxy = op_MSG 2902 case ASUB: 2903 opxy = op_SG 2904 case ASUBC: 2905 opxy = op_SLG 2906 case ASUBE: 2907 opxy = op_SLBG 2908 case ASUBW: 2909 opx = op_S 2910 opxy = op_SY 2911 case AAND: 2912 opxy = op_NG 2913 case AANDW: 2914 opx = op_N 2915 opxy = op_NY 2916 case AOR: 2917 opxy = op_OG 2918 case AORW: 2919 opx = op_O 2920 opxy = op_OY 2921 case AXOR: 2922 opxy = op_XG 2923 case AXORW: 2924 opx = op_X 2925 opxy = op_XY 2926 } 2927 if opx != 0 && 0 <= d2 && d2 < DISP12 { 2928 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2929 } else { 2930 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2931 } 2932 2933 case 15: // br/bl (reg) 2934 r := p.To.Reg 2935 if p.As == ABCL || p.As == ABL { 2936 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 2937 } else { 2938 zRR(op_BCR, 0xF, uint32(r), asm) 2939 } 2940 2941 case 16: // conditional branch 2942 v := int32(0) 2943 if p.Pcond != nil { 2944 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2945 } 2946 mask := c.branchMask(p) 2947 if p.To.Sym == nil && int32(int16(v)) == v { 2948 zRI(op_BRC, mask, uint32(v), asm) 2949 } else { 2950 zRIL(_c, op_BRCL, mask, uint32(v), asm) 2951 } 2952 if p.To.Sym != nil { 2953 c.addrilreloc(p.To.Sym, p.To.Offset) 2954 } 2955 2956 case 17: // move on condition 2957 m3 := c.branchMask(p) 2958 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2959 2960 case 18: // br/bl reg 2961 if p.As == ABL { 2962 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 2963 } else { 2964 zRR(op_BCR, 0xF, uint32(p.To.Reg), asm) 2965 } 2966 2967 case 19: // mov $sym+n(SB) reg 2968 d := c.vregoff(&p.From) 2969 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 2970 if d&1 != 0 { 2971 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 2972 d -= 1 2973 } 2974 c.addrilreloc(p.From.Sym, d) 2975 2976 case 21: // subtract $constant [reg] reg 2977 v := c.vregoff(&p.From) 2978 r := p.Reg 2979 if r == 0 { 2980 r = p.To.Reg 2981 } 2982 switch p.As { 2983 case ASUB: 2984 zRIL(_a, op_LGFI, uint32(REGTMP), uint32(v), asm) 2985 zRRF(op_SLGRK, uint32(REGTMP), 0, uint32(p.To.Reg), uint32(r), asm) 2986 case ASUBC: 2987 if r != p.To.Reg { 2988 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2989 } 2990 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm) 2991 case ASUBW: 2992 if r != p.To.Reg { 2993 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 2994 } 2995 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm) 2996 } 2997 2998 case 22: // add/multiply $constant [reg] reg 2999 v := c.vregoff(&p.From) 3000 r := p.Reg 3001 if r == 0 { 3002 r = p.To.Reg 3003 } 3004 var opri, opril, oprie uint32 3005 switch p.As { 3006 case AADD: 3007 opri = op_AGHI 3008 opril = op_AGFI 3009 oprie = op_AGHIK 3010 case AADDC: 3011 opril = op_ALGFI 3012 oprie = op_ALGHSIK 3013 case AADDW: 3014 opri = op_AHI 3015 opril = op_AFI 3016 oprie = op_AHIK 3017 case AMULLW: 3018 opri = op_MHI 3019 opril = op_MSFI 3020 case AMULLD: 3021 opri = op_MGHI 3022 opril = op_MSGFI 3023 } 3024 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) { 3025 switch p.As { 3026 case AADD, AADDC, AMULLD: 3027 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3028 case AADDW, AMULLW: 3029 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3030 } 3031 r = p.To.Reg 3032 } 3033 if r == p.To.Reg { 3034 if opri != 0 && int64(int16(v)) == v { 3035 zRI(opri, uint32(p.To.Reg), uint32(v), asm) 3036 } else { 3037 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm) 3038 } 3039 } else { 3040 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 3041 } 3042 3043 case 23: // 64-bit logical op $constant reg 3044 // TODO(mundaym): merge with case 24. 3045 v := c.vregoff(&p.From) 3046 switch p.As { 3047 default: 3048 c.ctxt.Diag("%v is not supported", p) 3049 case AAND: 3050 if v >= 0 { // needs zero extend 3051 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3052 zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm) 3053 } else if int64(int16(v)) == v { 3054 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3055 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 3056 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3057 } 3058 case AOR: 3059 if int64(uint32(v)) != v { // needs sign extend 3060 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3061 zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm) 3062 } else if int64(uint16(v)) == v { 3063 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3064 } else { 3065 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3066 } 3067 case AXOR: 3068 if int64(uint32(v)) != v { // needs sign extend 3069 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3070 zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm) 3071 } else { 3072 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3073 } 3074 } 3075 3076 case 24: // 32-bit logical op $constant reg 3077 v := c.vregoff(&p.From) 3078 switch p.As { 3079 case AANDW: 3080 if uint32(v&0xffff0000) == 0xffff0000 { 3081 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3082 } else if uint32(v&0x0000ffff) == 0x0000ffff { 3083 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3084 } else { 3085 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3086 } 3087 case AORW: 3088 if uint32(v&0xffff0000) == 0 { 3089 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3090 } else if uint32(v&0x0000ffff) == 0 { 3091 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3092 } else { 3093 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3094 } 3095 case AXORW: 3096 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3097 } 3098 3099 case 26: // MOVD $offset(base)(index), reg 3100 v := c.regoff(&p.From) 3101 r := p.From.Reg 3102 if r == 0 { 3103 r = o.param 3104 } 3105 i := p.From.Index 3106 if v >= 0 && v < DISP12 { 3107 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3108 } else if v >= -DISP20/2 && v < DISP20/2 { 3109 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3110 } else { 3111 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3112 zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, uint32(i), asm) 3113 } 3114 3115 case 31: // dword 3116 wd := uint64(c.vregoff(&p.From)) 3117 *asm = append(*asm, 3118 uint8(wd>>56), 3119 uint8(wd>>48), 3120 uint8(wd>>40), 3121 uint8(wd>>32), 3122 uint8(wd>>24), 3123 uint8(wd>>16), 3124 uint8(wd>>8), 3125 uint8(wd)) 3126 3127 case 32: // float op freg freg 3128 var opcode uint32 3129 switch p.As { 3130 default: 3131 c.ctxt.Diag("invalid opcode") 3132 case AFADD: 3133 opcode = op_ADBR 3134 case AFADDS: 3135 opcode = op_AEBR 3136 case AFDIV: 3137 opcode = op_DDBR 3138 case AFDIVS: 3139 opcode = op_DEBR 3140 case AFMUL: 3141 opcode = op_MDBR 3142 case AFMULS: 3143 opcode = op_MEEBR 3144 case AFSUB: 3145 opcode = op_SDBR 3146 case AFSUBS: 3147 opcode = op_SEBR 3148 } 3149 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3150 3151 case 33: // float op [freg] freg 3152 r := p.From.Reg 3153 if oclass(&p.From) == C_NONE { 3154 r = p.To.Reg 3155 } 3156 var opcode uint32 3157 switch p.As { 3158 default: 3159 case AFABS: 3160 opcode = op_LPDBR 3161 case AFNABS: 3162 opcode = op_LNDBR 3163 case AFNEG: 3164 opcode = op_LCDFR 3165 case AFNEGS: 3166 opcode = op_LCEBR 3167 case ALEDBR: 3168 opcode = op_LEDBR 3169 case ALDEBR: 3170 opcode = op_LDEBR 3171 case AFSQRT: 3172 opcode = op_SQDBR 3173 case AFSQRTS: 3174 opcode = op_SQEBR 3175 } 3176 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3177 3178 case 34: // float multiply-add freg freg freg 3179 var opcode uint32 3180 switch p.As { 3181 default: 3182 c.ctxt.Diag("invalid opcode") 3183 case AFMADD: 3184 opcode = op_MADBR 3185 case AFMADDS: 3186 opcode = op_MAEBR 3187 case AFMSUB: 3188 opcode = op_MSDBR 3189 case AFMSUBS: 3190 opcode = op_MSEBR 3191 } 3192 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 3193 3194 case 35: // mov reg mem (no relocation) 3195 d2 := c.regoff(&p.To) 3196 b2 := p.To.Reg 3197 if b2 == 0 { 3198 b2 = o.param 3199 } 3200 x2 := p.To.Index 3201 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3202 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3203 if x2 != 0 { 3204 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3205 } 3206 x2 = REGTMP 3207 d2 = 0 3208 } 3209 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3210 3211 case 36: // mov mem reg (no relocation) 3212 d2 := c.regoff(&p.From) 3213 b2 := p.From.Reg 3214 if b2 == 0 { 3215 b2 = o.param 3216 } 3217 x2 := p.From.Index 3218 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3219 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3220 if x2 != 0 { 3221 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3222 } 3223 x2 = REGTMP 3224 d2 = 0 3225 } 3226 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3227 3228 case 40: // word/byte 3229 wd := uint32(c.regoff(&p.From)) 3230 if p.As == AWORD { //WORD 3231 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3232 } else { //BYTE 3233 *asm = append(*asm, uint8(wd)) 3234 } 3235 3236 case 47: // negate [reg] reg 3237 r := p.From.Reg 3238 if r == 0 { 3239 r = p.To.Reg 3240 } 3241 switch p.As { 3242 case ANEG: 3243 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3244 case ANEGW: 3245 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm) 3246 } 3247 3248 case 48: // floating-point round to integer 3249 m3 := c.vregoff(&p.From) 3250 if 0 > m3 || m3 > 7 { 3251 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3) 3252 } 3253 var opcode uint32 3254 switch p.As { 3255 case AFIEBR: 3256 opcode = op_FIEBR 3257 case AFIDBR: 3258 opcode = op_FIDBR 3259 } 3260 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3261 3262 case 67: // fmov $0 freg 3263 var opcode uint32 3264 switch p.As { 3265 case AFMOVS: 3266 opcode = op_LZER 3267 case AFMOVD: 3268 opcode = op_LZDR 3269 } 3270 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3271 3272 case 68: // movw areg reg 3273 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3274 3275 case 69: // movw reg areg 3276 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3277 3278 case 70: // cmp reg reg 3279 if p.As == ACMPW || p.As == ACMPWU { 3280 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3281 } else { 3282 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3283 } 3284 3285 case 71: // cmp reg $constant 3286 v := c.vregoff(&p.To) 3287 switch p.As { 3288 case ACMP, ACMPW: 3289 if int64(int32(v)) != v { 3290 c.ctxt.Diag("%v overflows an int32", v) 3291 } 3292 case ACMPU, ACMPWU: 3293 if int64(uint32(v)) != v { 3294 c.ctxt.Diag("%v overflows a uint32", v) 3295 } 3296 } 3297 if p.As == ACMP && int64(int16(v)) == v { 3298 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm) 3299 } else if p.As == ACMPW && int64(int16(v)) == v { 3300 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm) 3301 } else { 3302 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm) 3303 } 3304 3305 case 72: // mov $constant mem 3306 v := c.regoff(&p.From) 3307 d := c.regoff(&p.To) 3308 r := p.To.Reg 3309 x := p.To.Index 3310 if r == 0 { 3311 r = o.param 3312 } 3313 if int32(int16(v)) == v && x == 0 { 3314 if d < 0 || d >= DISP12 { 3315 if r == REGTMP || r == REGTMP2 { 3316 zRIL(_a, op_AGFI, uint32(r), uint32(d), asm) 3317 } else { 3318 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3319 zRRE(op_AGR, REGTMP, uint32(r), asm) 3320 r = REGTMP 3321 } 3322 d = 0 3323 } 3324 var opcode uint32 3325 switch p.As { 3326 case AMOVD: 3327 opcode = op_MVGHI 3328 case AMOVW, AMOVWZ: 3329 opcode = op_MVHI 3330 case AMOVH, AMOVHZ: 3331 opcode = op_MVHHI 3332 case AMOVB, AMOVBZ: 3333 opcode = op_MVI 3334 } 3335 if opcode == op_MVI { 3336 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3337 } else { 3338 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3339 } 3340 } else { 3341 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm) 3342 if d < -DISP20/2 || d >= DISP20/2 { 3343 if r == REGTMP { 3344 zRIL(_a, op_AGFI, REGTMP, uint32(d), asm) 3345 } else { 3346 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3347 if x != 0 { 3348 zRRE(op_AGR, REGTMP, uint32(x), asm) 3349 } 3350 x = REGTMP 3351 } 3352 d = 0 3353 } 3354 zRXY(c.zopstore(p.As), REGTMP2, uint32(x), uint32(r), uint32(d), asm) 3355 } 3356 3357 case 73: // mov $constant addr (including relocation) 3358 v := c.regoff(&p.From) 3359 d := c.regoff(&p.To) 3360 a := uint32(0) 3361 if d&1 != 0 { 3362 d -= 1 3363 a = 1 3364 } 3365 zRIL(_b, op_LARL, REGTMP, uint32(d), asm) 3366 c.addrilreloc(p.To.Sym, int64(d)) 3367 if int32(int16(v)) == v { 3368 var opcode uint32 3369 switch p.As { 3370 case AMOVD: 3371 opcode = op_MVGHI 3372 case AMOVW, AMOVWZ: 3373 opcode = op_MVHI 3374 case AMOVH, AMOVHZ: 3375 opcode = op_MVHHI 3376 case AMOVB, AMOVBZ: 3377 opcode = op_MVI 3378 } 3379 if opcode == op_MVI { 3380 zSI(opcode, uint32(v), REGTMP, a, asm) 3381 } else { 3382 zSIL(opcode, REGTMP, a, uint32(v), asm) 3383 } 3384 } else { 3385 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm) 3386 zRXY(c.zopstore(p.As), REGTMP2, 0, REGTMP, a, asm) 3387 } 3388 3389 case 74: // mov reg addr (including relocation) 3390 i2 := c.regoff(&p.To) 3391 switch p.As { 3392 case AMOVD: 3393 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3394 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3395 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3396 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3397 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3398 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3399 zRIL(_b, op_LARL, REGTMP, 0, asm) 3400 adj := uint32(0) // adjustment needed for odd addresses 3401 if i2&1 != 0 { 3402 i2 -= 1 3403 adj = 1 3404 } 3405 zRX(op_STC, uint32(p.From.Reg), 0, REGTMP, adj, asm) 3406 case AFMOVD: 3407 zRIL(_b, op_LARL, REGTMP, 0, asm) 3408 zRX(op_STD, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3409 case AFMOVS: 3410 zRIL(_b, op_LARL, REGTMP, 0, asm) 3411 zRX(op_STE, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3412 } 3413 c.addrilreloc(p.To.Sym, int64(i2)) 3414 3415 case 75: // mov addr reg (including relocation) 3416 i2 := c.regoff(&p.From) 3417 switch p.As { 3418 case AMOVD: 3419 if i2&1 != 0 { 3420 zRIL(_b, op_LARL, REGTMP, 0, asm) 3421 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 1, asm) 3422 i2 -= 1 3423 } else { 3424 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3425 } 3426 case AMOVW: 3427 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3428 case AMOVWZ: 3429 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3430 case AMOVH: 3431 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3432 case AMOVHZ: 3433 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3434 case AMOVB, AMOVBZ: 3435 zRIL(_b, op_LARL, REGTMP, 0, asm) 3436 adj := uint32(0) // adjustment needed for odd addresses 3437 if i2&1 != 0 { 3438 i2 -= 1 3439 adj = 1 3440 } 3441 switch p.As { 3442 case AMOVB: 3443 zRXY(op_LGB, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3444 case AMOVBZ: 3445 zRXY(op_LLGC, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3446 } 3447 case AFMOVD: 3448 zRIL(_a, op_LARL, REGTMP, 0, asm) 3449 zRX(op_LD, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3450 case AFMOVS: 3451 zRIL(_a, op_LARL, REGTMP, 0, asm) 3452 zRX(op_LE, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3453 } 3454 c.addrilreloc(p.From.Sym, int64(i2)) 3455 3456 case 77: // syscall $constant 3457 if p.From.Offset > 255 || p.From.Offset < 1 { 3458 c.ctxt.Diag("illegal system call; system call number out of range: %v", p) 3459 zE(op_TRAP2, asm) // trap always 3460 } else { 3461 zI(op_SVC, uint32(p.From.Offset), asm) 3462 } 3463 3464 case 78: // undef 3465 // "An instruction consisting entirely of binary 0s is guaranteed 3466 // always to be an illegal instruction." 3467 *asm = append(*asm, 0, 0, 0, 0) 3468 3469 case 79: // compare and swap reg reg reg 3470 v := c.regoff(&p.To) 3471 if v < 0 { 3472 v = 0 3473 } 3474 if p.As == ACS { 3475 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3476 } else if p.As == ACSG { 3477 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3478 } 3479 3480 case 80: // sync 3481 zRR(op_BCR, 0xE, 0, asm) 3482 3483 case 81: // float to fixed and fixed to float moves (no conversion) 3484 switch p.As { 3485 case ALDGR: 3486 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3487 case ALGDR: 3488 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3489 } 3490 3491 case 82: // fixed to float conversion 3492 var opcode uint32 3493 switch p.As { 3494 default: 3495 log.Fatalf("unexpected opcode %v", p.As) 3496 case ACEFBRA: 3497 opcode = op_CEFBRA 3498 case ACDFBRA: 3499 opcode = op_CDFBRA 3500 case ACEGBRA: 3501 opcode = op_CEGBRA 3502 case ACDGBRA: 3503 opcode = op_CDGBRA 3504 case ACELFBR: 3505 opcode = op_CELFBR 3506 case ACDLFBR: 3507 opcode = op_CDLFBR 3508 case ACELGBR: 3509 opcode = op_CELGBR 3510 case ACDLGBR: 3511 opcode = op_CDLGBR 3512 } 3513 // set immediate operand M3 to 0 to use the default BFP rounding mode 3514 // (usually round to nearest, ties to even) 3515 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3516 // M4 is reserved and must be 0 3517 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3518 3519 case 83: // float to fixed conversion 3520 var opcode uint32 3521 switch p.As { 3522 default: 3523 log.Fatalf("unexpected opcode %v", p.As) 3524 case ACFEBRA: 3525 opcode = op_CFEBRA 3526 case ACFDBRA: 3527 opcode = op_CFDBRA 3528 case ACGEBRA: 3529 opcode = op_CGEBRA 3530 case ACGDBRA: 3531 opcode = op_CGDBRA 3532 case ACLFEBR: 3533 opcode = op_CLFEBR 3534 case ACLFDBR: 3535 opcode = op_CLFDBR 3536 case ACLGEBR: 3537 opcode = op_CLGEBR 3538 case ACLGDBR: 3539 opcode = op_CLGDBR 3540 } 3541 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3542 // M4 is reserved and must be 0 3543 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3544 3545 case 84: // storage-and-storage operations $length mem mem 3546 l := c.regoff(&p.From) 3547 if l < 1 || l > 256 { 3548 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3549 } 3550 if p.From3.Index != 0 || p.To.Index != 0 { 3551 c.ctxt.Diag("cannot use index reg") 3552 } 3553 b1 := p.To.Reg 3554 b2 := p.From3.Reg 3555 if b1 == 0 { 3556 b1 = o.param 3557 } 3558 if b2 == 0 { 3559 b2 = o.param 3560 } 3561 d1 := c.regoff(&p.To) 3562 d2 := c.regoff(p.From3) 3563 if d1 < 0 || d1 >= DISP12 { 3564 if b2 == REGTMP { 3565 c.ctxt.Diag("REGTMP conflict") 3566 } 3567 if b1 != REGTMP { 3568 zRRE(op_LGR, REGTMP, uint32(b1), asm) 3569 } 3570 zRIL(_a, op_AGFI, REGTMP, uint32(d1), asm) 3571 if d1 == d2 && b1 == b2 { 3572 d2 = 0 3573 b2 = REGTMP 3574 } 3575 d1 = 0 3576 b1 = REGTMP 3577 } 3578 if d2 < 0 || d2 >= DISP12 { 3579 if b1 == REGTMP2 { 3580 c.ctxt.Diag("REGTMP2 conflict") 3581 } 3582 if b2 != REGTMP2 { 3583 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3584 } 3585 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3586 d2 = 0 3587 b2 = REGTMP2 3588 } 3589 var opcode uint32 3590 switch p.As { 3591 default: 3592 c.ctxt.Diag("unexpected opcode %v", p.As) 3593 case AMVC: 3594 opcode = op_MVC 3595 case ACLC: 3596 opcode = op_CLC 3597 // swap operand order for CLC so that it matches CMP 3598 b1, b2 = b2, b1 3599 d1, d2 = d2, d1 3600 case AXC: 3601 opcode = op_XC 3602 case AOC: 3603 opcode = op_OC 3604 case ANC: 3605 opcode = op_NC 3606 } 3607 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3608 3609 case 85: // load address relative long 3610 v := c.regoff(&p.From) 3611 if p.From.Sym == nil { 3612 if (v & 1) != 0 { 3613 c.ctxt.Diag("cannot use LARL with odd offset: %v", v) 3614 } 3615 } else { 3616 c.addrilreloc(p.From.Sym, int64(v)) 3617 v = 0 3618 } 3619 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3620 3621 case 86: // load address 3622 d := c.vregoff(&p.From) 3623 x := p.From.Index 3624 b := p.From.Reg 3625 if b == 0 { 3626 b = o.param 3627 } 3628 switch p.As { 3629 case ALA: 3630 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3631 case ALAY: 3632 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3633 } 3634 3635 case 87: // execute relative long 3636 v := c.vregoff(&p.From) 3637 if p.From.Sym == nil { 3638 if v&1 != 0 { 3639 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3640 } 3641 } else { 3642 c.addrilreloc(p.From.Sym, v) 3643 v = 0 3644 } 3645 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3646 3647 case 88: // store clock 3648 var opcode uint32 3649 switch p.As { 3650 case ASTCK: 3651 opcode = op_STCK 3652 case ASTCKC: 3653 opcode = op_STCKC 3654 case ASTCKE: 3655 opcode = op_STCKE 3656 case ASTCKF: 3657 opcode = op_STCKF 3658 } 3659 v := c.vregoff(&p.To) 3660 r := int(p.To.Reg) 3661 if r == 0 { 3662 r = int(o.param) 3663 } 3664 zS(opcode, uint32(r), uint32(v), asm) 3665 3666 case 89: // compare and branch reg reg 3667 var v int32 3668 if p.Pcond != nil { 3669 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3670 } 3671 var opcode, opcode2 uint32 3672 switch p.As { 3673 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3674 opcode = op_CGRJ 3675 opcode2 = op_CGR 3676 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3677 opcode = op_CLGRJ 3678 opcode2 = op_CLGR 3679 } 3680 mask := c.branchMask(p) 3681 if int32(int16(v)) != v { 3682 zRRE(opcode2, uint32(p.From.Reg), uint32(p.Reg), asm) 3683 zRIL(_c, op_BRCL, mask, uint32(v-sizeRRE/2), asm) 3684 } else { 3685 zRIE(_b, opcode, uint32(p.From.Reg), uint32(p.Reg), uint32(v), 0, 0, mask, 0, asm) 3686 } 3687 3688 case 90: // compare and branch reg $constant 3689 var v int32 3690 if p.Pcond != nil { 3691 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3692 } 3693 var opcode, opcode2 uint32 3694 switch p.As { 3695 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3696 opcode = op_CGIJ 3697 opcode2 = op_CGFI 3698 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3699 opcode = op_CLGIJ 3700 opcode2 = op_CLGFI 3701 } 3702 mask := c.branchMask(p) 3703 if int32(int16(v)) != v { 3704 zRIL(_a, opcode2, uint32(p.From.Reg), uint32(c.regoff(p.From3)), asm) 3705 zRIL(_c, op_BRCL, mask, uint32(v-sizeRIL/2), asm) 3706 } else { 3707 zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(c.regoff(p.From3)), asm) 3708 } 3709 3710 case 93: // GOT lookup 3711 v := c.vregoff(&p.To) 3712 if v != 0 { 3713 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3714 } 3715 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3716 rel := obj.Addrel(c.cursym) 3717 rel.Off = int32(c.pc + 2) 3718 rel.Siz = 4 3719 rel.Sym = p.From.Sym 3720 rel.Type = objabi.R_GOTPCREL 3721 rel.Add = 2 + int64(rel.Siz) 3722 3723 case 94: // TLS local exec model 3724 zRIL(_b, op_LARL, REGTMP, (sizeRIL+sizeRXY+sizeRI)>>1, asm) 3725 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3726 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 3727 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 3728 rel := obj.Addrel(c.cursym) 3729 rel.Off = int32(c.pc + sizeRIL + sizeRXY + sizeRI) 3730 rel.Siz = 8 3731 rel.Sym = p.From.Sym 3732 rel.Type = objabi.R_TLS_LE 3733 rel.Add = 0 3734 3735 case 95: // TLS initial exec model 3736 // Assembly | Relocation symbol | Done Here? 3737 // -------------------------------------------------------------- 3738 // ear %r11, %a0 | | 3739 // sllg %r11, %r11, 32 | | 3740 // ear %r11, %a1 | | 3741 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 3742 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 3743 // la %r10, 0(%r10, %r11) | | 3744 // -------------------------------------------------------------- 3745 3746 // R_390_TLS_IEENT 3747 zRIL(_b, op_LARL, REGTMP, 0, asm) 3748 ieent := obj.Addrel(c.cursym) 3749 ieent.Off = int32(c.pc + 2) 3750 ieent.Siz = 4 3751 ieent.Sym = p.From.Sym 3752 ieent.Type = objabi.R_TLS_IE 3753 ieent.Add = 2 + int64(ieent.Siz) 3754 3755 // R_390_TLS_LOAD 3756 zRXY(op_LGF, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3757 // TODO(mundaym): add R_390_TLS_LOAD relocation here 3758 // not strictly required but might allow the linker to optimize 3759 3760 case 96: // clear macro 3761 length := c.vregoff(&p.From) 3762 offset := c.vregoff(&p.To) 3763 reg := p.To.Reg 3764 if reg == 0 { 3765 reg = o.param 3766 } 3767 if length <= 0 { 3768 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 3769 } 3770 for length > 0 { 3771 if offset < 0 || offset >= DISP12 { 3772 if offset >= -DISP20/2 && offset < DISP20/2 { 3773 zRXY(op_LAY, REGTMP, uint32(reg), 0, uint32(offset), asm) 3774 } else { 3775 if reg != REGTMP { 3776 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3777 } 3778 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3779 } 3780 reg = REGTMP 3781 offset = 0 3782 } 3783 size := length 3784 if size > 256 { 3785 size = 256 3786 } 3787 3788 switch size { 3789 case 1: 3790 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 3791 case 2: 3792 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 3793 case 4: 3794 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 3795 case 8: 3796 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 3797 default: 3798 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 3799 } 3800 3801 length -= size 3802 offset += size 3803 } 3804 3805 case 97: // store multiple 3806 rstart := p.From.Reg 3807 rend := p.Reg 3808 offset := c.regoff(&p.To) 3809 reg := p.To.Reg 3810 if reg == 0 { 3811 reg = o.param 3812 } 3813 if offset < -DISP20/2 || offset >= DISP20/2 { 3814 if reg != REGTMP { 3815 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3816 } 3817 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3818 reg = REGTMP 3819 offset = 0 3820 } 3821 switch p.As { 3822 case ASTMY: 3823 if offset >= 0 && offset < DISP12 { 3824 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3825 } else { 3826 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3827 } 3828 case ASTMG: 3829 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3830 } 3831 3832 case 98: // load multiple 3833 rstart := p.Reg 3834 rend := p.To.Reg 3835 offset := c.regoff(&p.From) 3836 reg := p.From.Reg 3837 if reg == 0 { 3838 reg = o.param 3839 } 3840 if offset < -DISP20/2 || offset >= DISP20/2 { 3841 if reg != REGTMP { 3842 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3843 } 3844 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3845 reg = REGTMP 3846 offset = 0 3847 } 3848 switch p.As { 3849 case ALMY: 3850 if offset >= 0 && offset < DISP12 { 3851 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3852 } else { 3853 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3854 } 3855 case ALMG: 3856 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3857 } 3858 3859 case 99: // interlocked load and op 3860 if p.To.Index != 0 { 3861 c.ctxt.Diag("cannot use indexed address") 3862 } 3863 offset := c.regoff(&p.To) 3864 if offset < -DISP20/2 || offset >= DISP20/2 { 3865 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset) 3866 } 3867 var opcode uint32 3868 switch p.As { 3869 case ALAA: 3870 opcode = op_LAA 3871 case ALAAG: 3872 opcode = op_LAAG 3873 case ALAAL: 3874 opcode = op_LAAL 3875 case ALAALG: 3876 opcode = op_LAALG 3877 case ALAN: 3878 opcode = op_LAN 3879 case ALANG: 3880 opcode = op_LANG 3881 case ALAX: 3882 opcode = op_LAX 3883 case ALAXG: 3884 opcode = op_LAXG 3885 case ALAO: 3886 opcode = op_LAO 3887 case ALAOG: 3888 opcode = op_LAOG 3889 } 3890 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm) 3891 3892 case 100: // VRX STORE 3893 op, m3, _ := vop(p.As) 3894 v1 := p.From.Reg 3895 if p.Reg != 0 { 3896 m3 = uint32(c.vregoff(&p.From)) 3897 v1 = p.Reg 3898 } 3899 b2 := p.To.Reg 3900 if b2 == 0 { 3901 b2 = o.param 3902 } 3903 d2 := uint32(c.vregoff(&p.To)) 3904 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3905 3906 case 101: // VRX LOAD 3907 op, m3, _ := vop(p.As) 3908 src := &p.From 3909 if p.From3 != nil { 3910 m3 = uint32(c.vregoff(&p.From)) 3911 src = p.From3 3912 } 3913 b2 := src.Reg 3914 if b2 == 0 { 3915 b2 = o.param 3916 } 3917 d2 := uint32(c.vregoff(src)) 3918 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm) 3919 3920 case 102: // VRV SCATTER 3921 op, _, _ := vop(p.As) 3922 m3 := uint32(c.vregoff(&p.From)) 3923 b2 := p.To.Reg 3924 if b2 == 0 { 3925 b2 = o.param 3926 } 3927 d2 := uint32(c.vregoff(&p.To)) 3928 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3929 3930 case 103: // VRV GATHER 3931 op, _, _ := vop(p.As) 3932 m3 := uint32(c.vregoff(&p.From)) 3933 b2 := p.From3.Reg 3934 if b2 == 0 { 3935 b2 = o.param 3936 } 3937 d2 := uint32(c.vregoff(p.From3)) 3938 zVRV(op, uint32(p.To.Reg), uint32(p.From3.Index), uint32(b2), d2, m3, asm) 3939 3940 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 3941 op, m4, _ := vop(p.As) 3942 fr := p.Reg 3943 if fr == 0 { 3944 fr = p.To.Reg 3945 } 3946 bits := uint32(c.vregoff(&p.From)) 3947 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 3948 3949 case 105: // VRS STORE MULTIPLE 3950 op, _, _ := vop(p.As) 3951 offset := uint32(c.vregoff(&p.To)) 3952 reg := p.To.Reg 3953 if reg == 0 { 3954 reg = o.param 3955 } 3956 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 3957 3958 case 106: // VRS LOAD MULTIPLE 3959 op, _, _ := vop(p.As) 3960 offset := uint32(c.vregoff(&p.From)) 3961 reg := p.From.Reg 3962 if reg == 0 { 3963 reg = o.param 3964 } 3965 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 3966 3967 case 107: // VRS STORE WITH LENGTH 3968 op, _, _ := vop(p.As) 3969 offset := uint32(c.vregoff(&p.To)) 3970 reg := p.To.Reg 3971 if reg == 0 { 3972 reg = o.param 3973 } 3974 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 3975 3976 case 108: // VRS LOAD WITH LENGTH 3977 op, _, _ := vop(p.As) 3978 offset := uint32(c.vregoff(p.From3)) 3979 reg := p.From3.Reg 3980 if reg == 0 { 3981 reg = o.param 3982 } 3983 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 3984 3985 case 109: // VRI-a 3986 op, m3, _ := vop(p.As) 3987 i2 := uint32(c.vregoff(&p.From)) 3988 if p.From3 != nil { 3989 m3 = uint32(c.vregoff(&p.From)) 3990 i2 = uint32(c.vregoff(p.From3)) 3991 } 3992 switch p.As { 3993 case AVZERO: 3994 i2 = 0 3995 case AVONE: 3996 i2 = 0xffff 3997 } 3998 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 3999 4000 case 110: 4001 op, m4, _ := vop(p.As) 4002 i2 := uint32(c.vregoff(&p.From)) 4003 i3 := uint32(c.vregoff(p.From3)) 4004 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 4005 4006 case 111: 4007 op, m4, _ := vop(p.As) 4008 i2 := uint32(c.vregoff(&p.From)) 4009 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 4010 4011 case 112: 4012 op, m5, _ := vop(p.As) 4013 i4 := uint32(c.vregoff(&p.From)) 4014 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), i4, m5, asm) 4015 4016 case 113: 4017 op, m4, _ := vop(p.As) 4018 m5 := singleElementMask(p.As) 4019 i3 := uint32(c.vregoff(&p.From)) 4020 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 4021 4022 case 114: // VRR-a 4023 op, m3, m5 := vop(p.As) 4024 m4 := singleElementMask(p.As) 4025 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 4026 4027 case 115: // VRR-a COMPARE 4028 op, m3, m5 := vop(p.As) 4029 m4 := singleElementMask(p.As) 4030 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 4031 4032 case 117: // VRR-b 4033 op, m4, m5 := vop(p.As) 4034 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 4035 4036 case 118: // VRR-c 4037 op, m4, m6 := vop(p.As) 4038 m5 := singleElementMask(p.As) 4039 v3 := p.Reg 4040 if v3 == 0 { 4041 v3 = p.To.Reg 4042 } 4043 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 4044 4045 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 4046 op, m4, m6 := vop(p.As) 4047 m5 := singleElementMask(p.As) 4048 v2 := p.Reg 4049 if v2 == 0 { 4050 v2 = p.To.Reg 4051 } 4052 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 4053 4054 case 120: // VRR-d 4055 op, m6, _ := vop(p.As) 4056 m5 := singleElementMask(p.As) 4057 v1 := uint32(p.To.Reg) 4058 v2 := uint32(p.From.Reg) 4059 v3 := uint32(p.Reg) 4060 v4 := uint32(p.From3.Reg) 4061 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 4062 4063 case 121: // VRR-e 4064 op, m6, _ := vop(p.As) 4065 m5 := singleElementMask(p.As) 4066 v1 := uint32(p.To.Reg) 4067 v2 := uint32(p.From.Reg) 4068 v3 := uint32(p.Reg) 4069 v4 := uint32(p.From3.Reg) 4070 zVRRe(op, v1, v2, v3, m6, m5, v4, asm) 4071 4072 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 4073 op, _, _ := vop(p.As) 4074 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 4075 4076 case 123: // VPDI $m4, V2, V3, V1 4077 op, _, _ := vop(p.As) 4078 m4 := c.regoff(&p.From) 4079 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), 0, 0, uint32(m4), asm) 4080 } 4081 } 4082 4083 func (c *ctxtz) vregoff(a *obj.Addr) int64 { 4084 c.instoffset = 0 4085 if a != nil { 4086 c.aclass(a) 4087 } 4088 return c.instoffset 4089 } 4090 4091 func (c *ctxtz) regoff(a *obj.Addr) int32 { 4092 return int32(c.vregoff(a)) 4093 } 4094 4095 // zopload returns the RXY op for the given load 4096 func (c *ctxtz) zopload(a obj.As) uint32 { 4097 switch a { 4098 // fixed point load 4099 case AMOVD: 4100 return op_LG 4101 case AMOVW: 4102 return op_LGF 4103 case AMOVWZ: 4104 return op_LLGF 4105 case AMOVH: 4106 return op_LGH 4107 case AMOVHZ: 4108 return op_LLGH 4109 case AMOVB: 4110 return op_LGB 4111 case AMOVBZ: 4112 return op_LLGC 4113 4114 // floating point load 4115 case AFMOVD: 4116 return op_LDY 4117 case AFMOVS: 4118 return op_LEY 4119 4120 // byte reversed load 4121 case AMOVDBR: 4122 return op_LRVG 4123 case AMOVWBR: 4124 return op_LRV 4125 case AMOVHBR: 4126 return op_LRVH 4127 } 4128 4129 c.ctxt.Diag("unknown store opcode %v", a) 4130 return 0 4131 } 4132 4133 // zopstore returns the RXY op for the given store 4134 func (c *ctxtz) zopstore(a obj.As) uint32 { 4135 switch a { 4136 // fixed point store 4137 case AMOVD: 4138 return op_STG 4139 case AMOVW, AMOVWZ: 4140 return op_STY 4141 case AMOVH, AMOVHZ: 4142 return op_STHY 4143 case AMOVB, AMOVBZ: 4144 return op_STCY 4145 4146 // floating point store 4147 case AFMOVD: 4148 return op_STDY 4149 case AFMOVS: 4150 return op_STEY 4151 4152 // byte reversed store 4153 case AMOVDBR: 4154 return op_STRVG 4155 case AMOVWBR: 4156 return op_STRV 4157 case AMOVHBR: 4158 return op_STRVH 4159 } 4160 4161 c.ctxt.Diag("unknown store opcode %v", a) 4162 return 0 4163 } 4164 4165 // zoprre returns the RRE op for the given a 4166 func (c *ctxtz) zoprre(a obj.As) uint32 { 4167 switch a { 4168 case ACMP: 4169 return op_CGR 4170 case ACMPU: 4171 return op_CLGR 4172 case AFCMPO: //ordered 4173 return op_KDBR 4174 case AFCMPU: //unordered 4175 return op_CDBR 4176 case ACEBR: 4177 return op_CEBR 4178 } 4179 c.ctxt.Diag("unknown rre opcode %v", a) 4180 return 0 4181 } 4182 4183 // zoprr returns the RR op for the given a 4184 func (c *ctxtz) zoprr(a obj.As) uint32 { 4185 switch a { 4186 case ACMPW: 4187 return op_CR 4188 case ACMPWU: 4189 return op_CLR 4190 } 4191 c.ctxt.Diag("unknown rr opcode %v", a) 4192 return 0 4193 } 4194 4195 // zopril returns the RIL op for the given a 4196 func (c *ctxtz) zopril(a obj.As) uint32 { 4197 switch a { 4198 case ACMP: 4199 return op_CGFI 4200 case ACMPU: 4201 return op_CLGFI 4202 case ACMPW: 4203 return op_CFI 4204 case ACMPWU: 4205 return op_CLFI 4206 } 4207 c.ctxt.Diag("unknown ril opcode %v", a) 4208 return 0 4209 } 4210 4211 // z instructions sizes 4212 const ( 4213 sizeE = 2 4214 sizeI = 2 4215 sizeIE = 4 4216 sizeMII = 6 4217 sizeRI = 4 4218 sizeRI1 = 4 4219 sizeRI2 = 4 4220 sizeRI3 = 4 4221 sizeRIE = 6 4222 sizeRIE1 = 6 4223 sizeRIE2 = 6 4224 sizeRIE3 = 6 4225 sizeRIE4 = 6 4226 sizeRIE5 = 6 4227 sizeRIE6 = 6 4228 sizeRIL = 6 4229 sizeRIL1 = 6 4230 sizeRIL2 = 6 4231 sizeRIL3 = 6 4232 sizeRIS = 6 4233 sizeRR = 2 4234 sizeRRD = 4 4235 sizeRRE = 4 4236 sizeRRF = 4 4237 sizeRRF1 = 4 4238 sizeRRF2 = 4 4239 sizeRRF3 = 4 4240 sizeRRF4 = 4 4241 sizeRRF5 = 4 4242 sizeRRR = 2 4243 sizeRRS = 6 4244 sizeRS = 4 4245 sizeRS1 = 4 4246 sizeRS2 = 4 4247 sizeRSI = 4 4248 sizeRSL = 6 4249 sizeRSY = 6 4250 sizeRSY1 = 6 4251 sizeRSY2 = 6 4252 sizeRX = 4 4253 sizeRX1 = 4 4254 sizeRX2 = 4 4255 sizeRXE = 6 4256 sizeRXF = 6 4257 sizeRXY = 6 4258 sizeRXY1 = 6 4259 sizeRXY2 = 6 4260 sizeS = 4 4261 sizeSI = 4 4262 sizeSIL = 6 4263 sizeSIY = 6 4264 sizeSMI = 6 4265 sizeSS = 6 4266 sizeSS1 = 6 4267 sizeSS2 = 6 4268 sizeSS3 = 6 4269 sizeSS4 = 6 4270 sizeSS5 = 6 4271 sizeSS6 = 6 4272 sizeSSE = 6 4273 sizeSSF = 6 4274 ) 4275 4276 // instruction format variations 4277 type form int 4278 4279 const ( 4280 _a form = iota 4281 _b 4282 _c 4283 _d 4284 _e 4285 _f 4286 ) 4287 4288 func zE(op uint32, asm *[]byte) { 4289 *asm = append(*asm, uint8(op>>8), uint8(op)) 4290 } 4291 4292 func zI(op, i1 uint32, asm *[]byte) { 4293 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4294 } 4295 4296 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4297 *asm = append(*asm, 4298 uint8(op>>8), 4299 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4300 uint8(ri2), 4301 uint8(ri3>>16), 4302 uint8(ri3>>8), 4303 uint8(ri3)) 4304 } 4305 4306 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4307 *asm = append(*asm, 4308 uint8(op>>8), 4309 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4310 uint8(i2_ri2>>8), 4311 uint8(i2_ri2)) 4312 } 4313 4314 // Expected argument values for the instruction formats. 4315 // 4316 // Format a1 a2 a3 a4 a5 a6 a7 4317 // ------------------------------------ 4318 // a r1, 0, i2, 0, 0, m3, 0 4319 // b r1, r2, ri4, 0, 0, m3, 0 4320 // c r1, m3, ri4, 0, 0, 0, i2 4321 // d r1, r3, i2, 0, 0, 0, 0 4322 // e r1, r3, ri2, 0, 0, 0, 0 4323 // f r1, r2, 0, i3, i4, 0, i5 4324 // g r1, m3, i2, 0, 0, 0, 0 4325 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4326 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4327 4328 switch f { 4329 default: 4330 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4331 case _f: 4332 *asm = append(*asm, uint8(i3), uint8(i4)) 4333 } 4334 4335 switch f { 4336 case _a, _b: 4337 *asm = append(*asm, uint8(m3)<<4) 4338 default: 4339 *asm = append(*asm, uint8(i2_i5)) 4340 } 4341 4342 *asm = append(*asm, uint8(op)) 4343 } 4344 4345 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4346 if f == _a || f == _b { 4347 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4348 } 4349 *asm = append(*asm, 4350 uint8(op>>8), 4351 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4352 uint8(i2_ri2>>24), 4353 uint8(i2_ri2>>16), 4354 uint8(i2_ri2>>8), 4355 uint8(i2_ri2)) 4356 } 4357 4358 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4359 *asm = append(*asm, 4360 uint8(op>>8), 4361 (uint8(r1)<<4)|uint8(m3&0x0F), 4362 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4363 uint8(d4), 4364 uint8(i2), 4365 uint8(op)) 4366 } 4367 4368 func zRR(op, r1, r2 uint32, asm *[]byte) { 4369 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4370 } 4371 4372 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4373 *asm = append(*asm, 4374 uint8(op>>8), 4375 uint8(op), 4376 uint8(r1)<<4, 4377 (uint8(r3)<<4)|uint8(r2&0x0F)) 4378 } 4379 4380 func zRRE(op, r1, r2 uint32, asm *[]byte) { 4381 *asm = append(*asm, 4382 uint8(op>>8), 4383 uint8(op), 4384 0, 4385 (uint8(r1)<<4)|uint8(r2&0x0F)) 4386 } 4387 4388 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4389 *asm = append(*asm, 4390 uint8(op>>8), 4391 uint8(op), 4392 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4393 (uint8(r1)<<4)|uint8(r2&0x0F)) 4394 } 4395 4396 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4397 *asm = append(*asm, 4398 uint8(op>>8), 4399 (uint8(r1)<<4)|uint8(r2&0x0F), 4400 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4401 uint8(d4), 4402 uint8(m3)<<4, 4403 uint8(op)) 4404 } 4405 4406 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4407 *asm = append(*asm, 4408 uint8(op>>8), 4409 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4410 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4411 uint8(d2)) 4412 } 4413 4414 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4415 *asm = append(*asm, 4416 uint8(op>>8), 4417 (uint8(r1)<<4)|uint8(r3&0x0F), 4418 uint8(ri2>>8), 4419 uint8(ri2)) 4420 } 4421 4422 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4423 *asm = append(*asm, 4424 uint8(op>>8), 4425 uint8(l1), 4426 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4427 uint8(d2), 4428 uint8(op)) 4429 } 4430 4431 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4432 dl2 := uint16(d2) & 0x0FFF 4433 *asm = append(*asm, 4434 uint8(op>>8), 4435 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4436 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4437 uint8(dl2), 4438 uint8(d2>>12), 4439 uint8(op)) 4440 } 4441 4442 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4443 *asm = append(*asm, 4444 uint8(op>>8), 4445 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4446 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4447 uint8(d2)) 4448 } 4449 4450 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4451 *asm = append(*asm, 4452 uint8(op>>8), 4453 (uint8(r1)<<4)|uint8(x2&0x0F), 4454 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4455 uint8(d2), 4456 uint8(m3)<<4, 4457 uint8(op)) 4458 } 4459 4460 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4461 *asm = append(*asm, 4462 uint8(op>>8), 4463 (uint8(r3)<<4)|uint8(x2&0x0F), 4464 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4465 uint8(d2), 4466 uint8(m1)<<4, 4467 uint8(op)) 4468 } 4469 4470 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4471 dl2 := uint16(d2) & 0x0FFF 4472 *asm = append(*asm, 4473 uint8(op>>8), 4474 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4475 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4476 uint8(dl2), 4477 uint8(d2>>12), 4478 uint8(op)) 4479 } 4480 4481 func zS(op, b2, d2 uint32, asm *[]byte) { 4482 *asm = append(*asm, 4483 uint8(op>>8), 4484 uint8(op), 4485 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4486 uint8(d2)) 4487 } 4488 4489 func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4490 *asm = append(*asm, 4491 uint8(op>>8), 4492 uint8(i2), 4493 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4494 uint8(d1)) 4495 } 4496 4497 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4498 *asm = append(*asm, 4499 uint8(op>>8), 4500 uint8(op), 4501 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4502 uint8(d1), 4503 uint8(i2>>8), 4504 uint8(i2)) 4505 } 4506 4507 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4508 dl1 := uint16(d1) & 0x0FFF 4509 *asm = append(*asm, 4510 uint8(op>>8), 4511 uint8(i2), 4512 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4513 uint8(dl1), 4514 uint8(d1>>12), 4515 uint8(op)) 4516 } 4517 4518 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4519 *asm = append(*asm, 4520 uint8(op>>8), 4521 uint8(m1)<<4, 4522 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4523 uint8(d3), 4524 uint8(ri2>>8), 4525 uint8(ri2)) 4526 } 4527 4528 // Expected argument values for the instruction formats. 4529 // 4530 // Format a1 a2 a3 a4 a5 a6 4531 // ------------------------------- 4532 // a l1, 0, b1, d1, b2, d2 4533 // b l1, l2, b1, d1, b2, d2 4534 // c l1, i3, b1, d1, b2, d2 4535 // d r1, r3, b1, d1, b2, d2 4536 // e r1, r3, b2, d2, b4, d4 4537 // f 0, l2, b1, d1, b2, d2 4538 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4539 *asm = append(*asm, uint8(op>>8)) 4540 4541 switch f { 4542 case _a: 4543 *asm = append(*asm, uint8(l1_r1)) 4544 case _b, _c, _d, _e: 4545 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4546 case _f: 4547 *asm = append(*asm, uint8(l2_i3_r3)) 4548 } 4549 4550 *asm = append(*asm, 4551 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4552 uint8(d1_d2), 4553 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4554 uint8(d2_d4)) 4555 } 4556 4557 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4558 *asm = append(*asm, 4559 uint8(op>>8), 4560 uint8(op), 4561 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4562 uint8(d1), 4563 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4564 uint8(d2)) 4565 } 4566 4567 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4568 *asm = append(*asm, 4569 uint8(op>>8), 4570 (uint8(r3)<<4)|(uint8(op)&0x0F), 4571 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4572 uint8(d1), 4573 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4574 uint8(d2)) 4575 } 4576 4577 func rxb(va, vb, vc, vd uint32) uint8 { 4578 mask := uint8(0) 4579 if va >= REG_V16 && va <= REG_V31 { 4580 mask |= 0x8 4581 } 4582 if vb >= REG_V16 && vb <= REG_V31 { 4583 mask |= 0x4 4584 } 4585 if vc >= REG_V16 && vc <= REG_V31 { 4586 mask |= 0x2 4587 } 4588 if vd >= REG_V16 && vd <= REG_V31 { 4589 mask |= 0x1 4590 } 4591 return mask 4592 } 4593 4594 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 4595 *asm = append(*asm, 4596 uint8(op>>8), 4597 (uint8(v1)<<4)|(uint8(x2)&0xf), 4598 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4599 uint8(d2), 4600 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4601 uint8(op)) 4602 } 4603 4604 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 4605 *asm = append(*asm, 4606 uint8(op>>8), 4607 (uint8(v1)<<4)|(uint8(v2)&0xf), 4608 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4609 uint8(d2), 4610 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4611 uint8(op)) 4612 } 4613 4614 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 4615 *asm = append(*asm, 4616 uint8(op>>8), 4617 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 4618 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4619 uint8(d2), 4620 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 4621 uint8(op)) 4622 } 4623 4624 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 4625 *asm = append(*asm, 4626 uint8(op>>8), 4627 (uint8(v1)<<4)|(uint8(v2)&0xf), 4628 0, 4629 (uint8(m5)<<4)|(uint8(m4)&0xf), 4630 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4631 uint8(op)) 4632 } 4633 4634 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 4635 *asm = append(*asm, 4636 uint8(op>>8), 4637 (uint8(v1)<<4)|(uint8(v2)&0xf), 4638 uint8(v3)<<4, 4639 uint8(m5)<<4, 4640 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4641 uint8(op)) 4642 } 4643 4644 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 4645 *asm = append(*asm, 4646 uint8(op>>8), 4647 (uint8(v1)<<4)|(uint8(v2)&0xf), 4648 uint8(v3)<<4, 4649 (uint8(m6)<<4)|(uint8(m5)&0xf), 4650 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4651 uint8(op)) 4652 } 4653 4654 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 4655 *asm = append(*asm, 4656 uint8(op>>8), 4657 (uint8(v1)<<4)|(uint8(v2)&0xf), 4658 (uint8(v3)<<4)|(uint8(m5)&0xf), 4659 uint8(m6)<<4, 4660 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4661 uint8(op)) 4662 } 4663 4664 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 4665 *asm = append(*asm, 4666 uint8(op>>8), 4667 (uint8(v1)<<4)|(uint8(v2)&0xf), 4668 (uint8(v3)<<4)|(uint8(m6)&0xf), 4669 uint8(m5), 4670 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4671 uint8(op)) 4672 } 4673 4674 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 4675 *asm = append(*asm, 4676 uint8(op>>8), 4677 (uint8(v1)<<4)|(uint8(r2)&0xf), 4678 uint8(r3)<<4, 4679 0, 4680 rxb(v1, 0, 0, 0), 4681 uint8(op)) 4682 } 4683 4684 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 4685 *asm = append(*asm, 4686 uint8(op>>8), 4687 uint8(v1)<<4, 4688 uint8(i2>>8), 4689 uint8(i2), 4690 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4691 uint8(op)) 4692 } 4693 4694 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 4695 *asm = append(*asm, 4696 uint8(op>>8), 4697 uint8(v1)<<4, 4698 uint8(i2), 4699 uint8(i3), 4700 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 4701 uint8(op)) 4702 } 4703 4704 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 4705 *asm = append(*asm, 4706 uint8(op>>8), 4707 (uint8(v1)<<4)|(uint8(v3)&0xf), 4708 uint8(i2>>8), 4709 uint8(i2), 4710 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 4711 uint8(op)) 4712 } 4713 4714 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 4715 *asm = append(*asm, 4716 uint8(op>>8), 4717 (uint8(v1)<<4)|(uint8(v2)&0xf), 4718 uint8(v3)<<4, 4719 uint8(i4), 4720 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 4721 uint8(op)) 4722 } 4723 4724 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 4725 *asm = append(*asm, 4726 uint8(op>>8), 4727 (uint8(v1)<<4)|(uint8(v2)&0xf), 4728 uint8(i3>>4), 4729 (uint8(i3)<<4)|(uint8(m5)&0xf), 4730 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 4731 uint8(op)) 4732 }