github.com/spotify/syslog-redirector-golang@v0.0.0-20140320174030-4859f03d829a/src/cmd/8g/opt.h (about) 1 // Derived from Inferno utils/6c/gc.h 2 // http://code.google.com/p/inferno-os/source/browse/utils/6c/gc.h 3 // 4 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 6 // Portions Copyright © 1997-1999 Vita Nuova Limited 7 // Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8 // Portions Copyright © 2004,2006 Bruce Ellis 9 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 10 // Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11 // Portions Copyright © 2009 The Go Authors. All rights reserved. 12 // 13 // Permission is hereby granted, free of charge, to any person obtaining a copy 14 // of this software and associated documentation files (the "Software"), to deal 15 // in the Software without restriction, including without limitation the rights 16 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 // copies of the Software, and to permit persons to whom the Software is 18 // furnished to do so, subject to the following conditions: 19 // 20 // The above copyright notice and this permission notice shall be included in 21 // all copies or substantial portions of the Software. 22 // 23 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 // THE SOFTWARE. 30 31 #include "../gc/popt.h" 32 33 #define Z N 34 #define Adr Addr 35 36 #define D_HI D_NONE 37 #define D_LO D_NONE 38 39 #define BLOAD(r) band(bnot(r->refbehind), r->refahead) 40 #define BSTORE(r) band(bnot(r->calbehind), r->calahead) 41 #define LOAD(r) (~r->refbehind.b[z] & r->refahead.b[z]) 42 #define STORE(r) (~r->calbehind.b[z] & r->calahead.b[z]) 43 44 #define CLOAD 5 45 #define CREF 5 46 #define CINF 1000 47 #define LOOP 3 48 49 typedef struct Reg Reg; 50 typedef struct Rgn Rgn; 51 52 // A Reg is a wrapper around a single Prog (one instruction) that holds 53 // register optimization information while the optimizer runs. 54 // r->prog is the instruction. 55 // r->prog->opt points back to r. 56 struct Reg 57 { 58 Flow f; 59 60 Bits set; // variables written by this instruction. 61 Bits use1; // variables read by prog->from. 62 Bits use2; // variables read by prog->to. 63 64 Bits refbehind; 65 Bits refahead; 66 Bits calbehind; 67 Bits calahead; 68 Bits regdiff; 69 Bits act; 70 71 int32 regu; // register used bitmap 72 int32 rpo; // reverse post ordering 73 int32 active; 74 75 uint16 loop; // x5 for every loop 76 uchar refset; // diagnostic generated 77 78 Reg* p1; // predecessors of this instruction: p1, 79 Reg* p2; // and then p2 linked though p2link. 80 Reg* p2link; 81 Reg* s1; // successors of this instruction (at most two: s1 and s2). 82 Reg* s2; 83 Reg* link; // next instruction in function code 84 Prog* prog; // actual instruction 85 }; 86 #define R ((Reg*)0) 87 88 #define NRGN 600 89 struct Rgn 90 { 91 Reg* enter; 92 short cost; 93 short varno; 94 short regno; 95 }; 96 97 EXTERN int32 exregoffset; // not set 98 EXTERN int32 exfregoffset; // not set 99 EXTERN Reg zreg; 100 EXTERN Reg* freer; 101 EXTERN Reg** rpo2r; 102 EXTERN Rgn region[NRGN]; 103 EXTERN Rgn* rgp; 104 EXTERN int nregion; 105 EXTERN int nvar; 106 EXTERN int32 regbits; 107 EXTERN int32 exregbits; 108 EXTERN Bits externs; 109 EXTERN Bits params; 110 EXTERN Bits consts; 111 EXTERN Bits addrs; 112 EXTERN Bits ovar; 113 EXTERN int change; 114 EXTERN int32 maxnr; 115 EXTERN int32* idom; 116 117 EXTERN struct 118 { 119 int32 ncvtreg; 120 int32 nspill; 121 int32 nreload; 122 int32 ndelmov; 123 int32 nvar; 124 int32 naddr; 125 } ostats; 126 127 /* 128 * reg.c 129 */ 130 Reg* rega(void); 131 int rcmp(const void*, const void*); 132 void regopt(Prog*); 133 void addmove(Reg*, int, int, int); 134 Bits mkvar(Reg*, Adr*); 135 void prop(Reg*, Bits, Bits); 136 void loopit(Reg*, int32); 137 void synch(Reg*, Bits); 138 uint32 allreg(uint32, Rgn*); 139 void paint1(Reg*, int); 140 uint32 paint2(Reg*, int); 141 void paint3(Reg*, int, int32, int); 142 void addreg(Adr*, int); 143 void dumpone(Flow*, int); 144 void dumpit(char*, Flow*, int); 145 146 /* 147 * peep.c 148 */ 149 void peep(Prog*); 150 void excise(Flow*); 151 int copyu(Prog*, Adr*, Adr*); 152 153 int32 RtoB(int); 154 int32 FtoB(int); 155 int BtoR(int32); 156 int BtoF(int32); 157 158 #pragma varargck type "D" Adr* 159 160 /* 161 * prog.c 162 */ 163 typedef struct ProgInfo ProgInfo; 164 struct ProgInfo 165 { 166 uint32 flags; // the bits below 167 uint32 reguse; // required registers used by this instruction 168 uint32 regset; // required registers set by this instruction 169 uint32 regindex; // registers used by addressing mode 170 }; 171 172 enum 173 { 174 // Pseudo-op, like TEXT, GLOBL, TYPE, PCDATA, FUNCDATA. 175 Pseudo = 1<<1, 176 177 // There's nothing to say about the instruction, 178 // but it's still okay to see. 179 OK = 1<<2, 180 181 // Size of right-side write, or right-side read if no write. 182 SizeB = 1<<3, 183 SizeW = 1<<4, 184 SizeL = 1<<5, 185 SizeQ = 1<<6, 186 SizeF = 1<<7, // float aka float32 187 SizeD = 1<<8, // double aka float64 188 189 // Left side: address taken, read, write. 190 LeftAddr = 1<<9, 191 LeftRead = 1<<10, 192 LeftWrite = 1<<11, 193 194 // Right side: address taken, read, write. 195 RightAddr = 1<<12, 196 RightRead = 1<<13, 197 RightWrite = 1<<14, 198 199 // Set, use, or kill of carry bit. 200 // Kill means we never look at the carry bit after this kind of instruction. 201 SetCarry = 1<<15, 202 UseCarry = 1<<16, 203 KillCarry = 1<<17, 204 205 // Instruction kinds 206 Move = 1<<18, // straight move 207 Conv = 1<<19, // size conversion 208 Cjmp = 1<<20, // conditional jump 209 Break = 1<<21, // breaks control flow (no fallthrough) 210 Call = 1<<22, // function call 211 Jump = 1<<23, // jump 212 Skip = 1<<24, // data instruction 213 214 // Special cases for register use. 215 ShiftCX = 1<<25, // possible shift by CX 216 ImulAXDX = 1<<26, // possible multiply into DX:AX 217 }; 218 219 void proginfo(ProgInfo*, Prog*);