github.com/spotify/syslog-redirector-golang@v0.0.0-20140320174030-4859f03d829a/src/cmd/8g/prog.c (about) 1 // Copyright 2013 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 #include <u.h> 6 #include <libc.h> 7 #include "gg.h" 8 #include "opt.h" 9 10 // Matches real RtoB but can be used in global initializer. 11 #define RtoB(r) (1<<((r)-D_AX)) 12 13 enum { 14 AX = RtoB(D_AX), 15 BX = RtoB(D_BX), 16 CX = RtoB(D_CX), 17 DX = RtoB(D_DX), 18 DI = RtoB(D_DI), 19 SI = RtoB(D_SI), 20 21 LeftRdwr = LeftRead | LeftWrite, 22 RightRdwr = RightRead | RightWrite, 23 }; 24 25 #undef RtoB 26 27 // This table gives the basic information about instruction 28 // generated by the compiler and processed in the optimizer. 29 // See opt.h for bit definitions. 30 // 31 // Instructions not generated need not be listed. 32 // As an exception to that rule, we typically write down all the 33 // size variants of an operation even if we just use a subset. 34 // 35 // The table is formatted for 8-space tabs. 36 static ProgInfo progtable[ALAST] = { 37 [ATYPE]= {Pseudo | Skip}, 38 [ATEXT]= {Pseudo}, 39 [AFUNCDATA]= {Pseudo}, 40 [APCDATA]= {Pseudo}, 41 [AUNDEF]= {OK}, 42 [AUSEFIELD]= {OK}, 43 [ACHECKNIL]= {LeftRead}, 44 45 // NOP is an internal no-op that also stands 46 // for USED and SET annotations, not the Intel opcode. 47 [ANOP]= {LeftRead | RightWrite}, 48 49 [AADCL]= {SizeL | LeftRead | RightRdwr | SetCarry | UseCarry}, 50 [AADCW]= {SizeW | LeftRead | RightRdwr | SetCarry | UseCarry}, 51 52 [AADDB]= {SizeB | LeftRead | RightRdwr | SetCarry}, 53 [AADDL]= {SizeL | LeftRead | RightRdwr | SetCarry}, 54 [AADDW]= {SizeW | LeftRead | RightRdwr | SetCarry}, 55 56 [AADDSD]= {SizeD | LeftRead | RightRdwr}, 57 [AADDSS]= {SizeF | LeftRead | RightRdwr}, 58 59 [AANDB]= {SizeB | LeftRead | RightRdwr | SetCarry}, 60 [AANDL]= {SizeL | LeftRead | RightRdwr | SetCarry}, 61 [AANDW]= {SizeW | LeftRead | RightRdwr | SetCarry}, 62 63 [ACALL]= {RightAddr | Call | KillCarry}, 64 65 [ACDQ]= {OK, AX, AX | DX}, 66 [ACWD]= {OK, AX, AX | DX}, 67 68 [ACLD]= {OK}, 69 [ASTD]= {OK}, 70 71 [ACMPB]= {SizeB | LeftRead | RightRead | SetCarry}, 72 [ACMPL]= {SizeL | LeftRead | RightRead | SetCarry}, 73 [ACMPW]= {SizeW | LeftRead | RightRead | SetCarry}, 74 75 [ACOMISD]= {SizeD | LeftRead | RightRead | SetCarry}, 76 [ACOMISS]= {SizeF | LeftRead | RightRead | SetCarry}, 77 78 [ACVTSD2SL]= {SizeL | LeftRead | RightWrite | Conv}, 79 [ACVTSD2SS]= {SizeF | LeftRead | RightWrite | Conv}, 80 [ACVTSL2SD]= {SizeD | LeftRead | RightWrite | Conv}, 81 [ACVTSL2SS]= {SizeF | LeftRead | RightWrite | Conv}, 82 [ACVTSS2SD]= {SizeD | LeftRead | RightWrite | Conv}, 83 [ACVTSS2SL]= {SizeL | LeftRead | RightWrite | Conv}, 84 [ACVTTSD2SL]= {SizeL | LeftRead | RightWrite | Conv}, 85 [ACVTTSS2SL]= {SizeL | LeftRead | RightWrite | Conv}, 86 87 [ADECB]= {SizeB | RightRdwr}, 88 [ADECL]= {SizeL | RightRdwr}, 89 [ADECW]= {SizeW | RightRdwr}, 90 91 [ADIVB]= {SizeB | LeftRead | SetCarry, AX, AX}, 92 [ADIVL]= {SizeL | LeftRead | SetCarry, AX|DX, AX|DX}, 93 [ADIVW]= {SizeW | LeftRead | SetCarry, AX|DX, AX|DX}, 94 95 [ADIVSD]= {SizeD | LeftRead | RightRdwr}, 96 [ADIVSS]= {SizeF | LeftRead | RightRdwr}, 97 98 [AFLDCW]= {SizeW | LeftAddr}, 99 [AFSTCW]= {SizeW | RightAddr}, 100 101 [AFSTSW]= {SizeW | RightAddr | RightWrite}, 102 103 [AFADDD]= {SizeD | LeftAddr | RightRdwr}, 104 [AFADDDP]= {SizeD | LeftAddr | RightRdwr}, 105 [AFADDF]= {SizeF | LeftAddr | RightRdwr}, 106 107 [AFCOMD]= {SizeD | LeftAddr | RightRead}, 108 [AFCOMDP]= {SizeD | LeftAddr | RightRead}, 109 [AFCOMDPP]= {SizeD | LeftAddr | RightRead}, 110 [AFCOMF]= {SizeF | LeftAddr | RightRead}, 111 [AFCOMFP]= {SizeF | LeftAddr | RightRead}, 112 [AFUCOMIP]= {SizeF | LeftAddr | RightRead}, 113 114 [AFCHS]= {SizeD | RightRdwr}, // also SizeF 115 116 [AFDIVDP]= {SizeD | LeftAddr | RightRdwr}, 117 [AFDIVF]= {SizeF | LeftAddr | RightRdwr}, 118 [AFDIVD]= {SizeD | LeftAddr | RightRdwr}, 119 120 [AFDIVRDP]= {SizeD | LeftAddr | RightRdwr}, 121 [AFDIVRF]= {SizeF | LeftAddr | RightRdwr}, 122 [AFDIVRD]= {SizeD | LeftAddr | RightRdwr}, 123 124 [AFXCHD]= {SizeD | LeftRdwr | RightRdwr}, 125 126 [AFSUBD]= {SizeD | LeftAddr | RightRdwr}, 127 [AFSUBDP]= {SizeD | LeftAddr | RightRdwr}, 128 [AFSUBF]= {SizeF | LeftAddr | RightRdwr}, 129 [AFSUBRD]= {SizeD | LeftAddr | RightRdwr}, 130 [AFSUBRDP]= {SizeD | LeftAddr | RightRdwr}, 131 [AFSUBRF]= {SizeF | LeftAddr | RightRdwr}, 132 133 [AFMOVD]= {SizeD | LeftAddr | RightWrite}, 134 [AFMOVF]= {SizeF | LeftAddr | RightWrite}, 135 [AFMOVL]= {SizeL | LeftAddr | RightWrite}, 136 [AFMOVW]= {SizeW | LeftAddr | RightWrite}, 137 [AFMOVV]= {SizeQ | LeftAddr | RightWrite}, 138 139 [AFMOVDP]= {SizeD | LeftRead | RightAddr}, 140 [AFMOVFP]= {SizeF | LeftRead | RightAddr}, 141 [AFMOVLP]= {SizeL | LeftRead | RightAddr}, 142 [AFMOVWP]= {SizeW | LeftRead | RightAddr}, 143 [AFMOVVP]= {SizeQ | LeftRead | RightAddr}, 144 145 [AFMULD]= {SizeD | LeftAddr | RightRdwr}, 146 [AFMULDP]= {SizeD | LeftAddr | RightRdwr}, 147 [AFMULF]= {SizeF | LeftAddr | RightRdwr}, 148 149 [AIDIVB]= {SizeB | LeftRead | SetCarry, AX, AX}, 150 [AIDIVL]= {SizeL | LeftRead | SetCarry, AX|DX, AX|DX}, 151 [AIDIVW]= {SizeW | LeftRead | SetCarry, AX|DX, AX|DX}, 152 153 [AIMULB]= {SizeB | LeftRead | SetCarry, AX, AX}, 154 [AIMULL]= {SizeL | LeftRead | ImulAXDX | SetCarry}, 155 [AIMULW]= {SizeW | LeftRead | ImulAXDX | SetCarry}, 156 157 [AINCB]= {SizeB | RightRdwr}, 158 [AINCL]= {SizeL | RightRdwr}, 159 [AINCW]= {SizeW | RightRdwr}, 160 161 [AJCC]= {Cjmp | UseCarry}, 162 [AJCS]= {Cjmp | UseCarry}, 163 [AJEQ]= {Cjmp | UseCarry}, 164 [AJGE]= {Cjmp | UseCarry}, 165 [AJGT]= {Cjmp | UseCarry}, 166 [AJHI]= {Cjmp | UseCarry}, 167 [AJLE]= {Cjmp | UseCarry}, 168 [AJLS]= {Cjmp | UseCarry}, 169 [AJLT]= {Cjmp | UseCarry}, 170 [AJMI]= {Cjmp | UseCarry}, 171 [AJNE]= {Cjmp | UseCarry}, 172 [AJOC]= {Cjmp | UseCarry}, 173 [AJOS]= {Cjmp | UseCarry}, 174 [AJPC]= {Cjmp | UseCarry}, 175 [AJPL]= {Cjmp | UseCarry}, 176 [AJPS]= {Cjmp | UseCarry}, 177 178 [AJMP]= {Jump | Break | KillCarry}, 179 180 [ALEAL]= {LeftAddr | RightWrite}, 181 182 [AMOVBLSX]= {SizeL | LeftRead | RightWrite | Conv}, 183 [AMOVBLZX]= {SizeL | LeftRead | RightWrite | Conv}, 184 [AMOVBWSX]= {SizeW | LeftRead | RightWrite | Conv}, 185 [AMOVBWZX]= {SizeW | LeftRead | RightWrite | Conv}, 186 [AMOVWLSX]= {SizeL | LeftRead | RightWrite | Conv}, 187 [AMOVWLZX]= {SizeL | LeftRead | RightWrite | Conv}, 188 189 [AMOVB]= {SizeB | LeftRead | RightWrite | Move}, 190 [AMOVL]= {SizeL | LeftRead | RightWrite | Move}, 191 [AMOVW]= {SizeW | LeftRead | RightWrite | Move}, 192 193 [AMOVSB]= {OK, DI|SI, DI|SI}, 194 [AMOVSL]= {OK, DI|SI, DI|SI}, 195 [AMOVSW]= {OK, DI|SI, DI|SI}, 196 197 [AMOVSD]= {SizeD | LeftRead | RightWrite | Move}, 198 [AMOVSS]= {SizeF | LeftRead | RightWrite | Move}, 199 200 // We use MOVAPD as a faster synonym for MOVSD. 201 [AMOVAPD]= {SizeD | LeftRead | RightWrite | Move}, 202 203 [AMULB]= {SizeB | LeftRead | SetCarry, AX, AX}, 204 [AMULL]= {SizeL | LeftRead | SetCarry, AX, AX|DX}, 205 [AMULW]= {SizeW | LeftRead | SetCarry, AX, AX|DX}, 206 207 [AMULSD]= {SizeD | LeftRead | RightRdwr}, 208 [AMULSS]= {SizeF | LeftRead | RightRdwr}, 209 210 [ANEGB]= {SizeB | RightRdwr | SetCarry}, 211 [ANEGL]= {SizeL | RightRdwr | SetCarry}, 212 [ANEGW]= {SizeW | RightRdwr | SetCarry}, 213 214 [ANOTB]= {SizeB | RightRdwr}, 215 [ANOTL]= {SizeL | RightRdwr}, 216 [ANOTW]= {SizeW | RightRdwr}, 217 218 [AORB]= {SizeB | LeftRead | RightRdwr | SetCarry}, 219 [AORL]= {SizeL | LeftRead | RightRdwr | SetCarry}, 220 [AORW]= {SizeW | LeftRead | RightRdwr | SetCarry}, 221 222 [APOPL]= {SizeL | RightWrite}, 223 [APUSHL]= {SizeL | LeftRead}, 224 225 [ARCLB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry}, 226 [ARCLL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry}, 227 [ARCLW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry}, 228 229 [ARCRB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry}, 230 [ARCRL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry}, 231 [ARCRW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry}, 232 233 [AREP]= {OK, CX, CX}, 234 [AREPN]= {OK, CX, CX}, 235 236 [ARET]= {Break | KillCarry}, 237 238 [AROLB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry}, 239 [AROLL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry}, 240 [AROLW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry}, 241 242 [ARORB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry}, 243 [ARORL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry}, 244 [ARORW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry}, 245 246 [ASAHF]= {OK, AX, AX}, 247 248 [ASALB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry}, 249 [ASALL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry}, 250 [ASALW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry}, 251 252 [ASARB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry}, 253 [ASARL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry}, 254 [ASARW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry}, 255 256 [ASBBB]= {SizeB | LeftRead | RightRdwr | SetCarry | UseCarry}, 257 [ASBBL]= {SizeL | LeftRead | RightRdwr | SetCarry | UseCarry}, 258 [ASBBW]= {SizeW | LeftRead | RightRdwr | SetCarry | UseCarry}, 259 260 [ASETCC]= {SizeB | RightRdwr | UseCarry}, 261 [ASETCS]= {SizeB | RightRdwr | UseCarry}, 262 [ASETEQ]= {SizeB | RightRdwr | UseCarry}, 263 [ASETGE]= {SizeB | RightRdwr | UseCarry}, 264 [ASETGT]= {SizeB | RightRdwr | UseCarry}, 265 [ASETHI]= {SizeB | RightRdwr | UseCarry}, 266 [ASETLE]= {SizeB | RightRdwr | UseCarry}, 267 [ASETLS]= {SizeB | RightRdwr | UseCarry}, 268 [ASETLT]= {SizeB | RightRdwr | UseCarry}, 269 [ASETMI]= {SizeB | RightRdwr | UseCarry}, 270 [ASETNE]= {SizeB | RightRdwr | UseCarry}, 271 [ASETOC]= {SizeB | RightRdwr | UseCarry}, 272 [ASETOS]= {SizeB | RightRdwr | UseCarry}, 273 [ASETPC]= {SizeB | RightRdwr | UseCarry}, 274 [ASETPL]= {SizeB | RightRdwr | UseCarry}, 275 [ASETPS]= {SizeB | RightRdwr | UseCarry}, 276 277 [ASHLB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry}, 278 [ASHLL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry}, 279 [ASHLW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry}, 280 281 [ASHRB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry}, 282 [ASHRL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry}, 283 [ASHRW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry}, 284 285 [ASTOSB]= {OK, AX|DI, DI}, 286 [ASTOSL]= {OK, AX|DI, DI}, 287 [ASTOSW]= {OK, AX|DI, DI}, 288 289 [ASUBB]= {SizeB | LeftRead | RightRdwr | SetCarry}, 290 [ASUBL]= {SizeL | LeftRead | RightRdwr | SetCarry}, 291 [ASUBW]= {SizeW | LeftRead | RightRdwr | SetCarry}, 292 293 [ASUBSD]= {SizeD | LeftRead | RightRdwr}, 294 [ASUBSS]= {SizeF | LeftRead | RightRdwr}, 295 296 [ATESTB]= {SizeB | LeftRead | RightRead | SetCarry}, 297 [ATESTL]= {SizeL | LeftRead | RightRead | SetCarry}, 298 [ATESTW]= {SizeW | LeftRead | RightRead | SetCarry}, 299 300 [AUCOMISD]= {SizeD | LeftRead | RightRead}, 301 [AUCOMISS]= {SizeF | LeftRead | RightRead}, 302 303 [AXCHGB]= {SizeB | LeftRdwr | RightRdwr}, 304 [AXCHGL]= {SizeL | LeftRdwr | RightRdwr}, 305 [AXCHGW]= {SizeW | LeftRdwr | RightRdwr}, 306 307 [AXORB]= {SizeB | LeftRead | RightRdwr | SetCarry}, 308 [AXORL]= {SizeL | LeftRead | RightRdwr | SetCarry}, 309 [AXORW]= {SizeW | LeftRead | RightRdwr | SetCarry}, 310 }; 311 312 void 313 proginfo(ProgInfo *info, Prog *p) 314 { 315 *info = progtable[p->as]; 316 if(info->flags == 0) 317 fatal("unknown instruction %P", p); 318 319 if((info->flags & ShiftCX) && p->from.type != D_CONST) 320 info->reguse |= CX; 321 322 if(info->flags & ImulAXDX) { 323 if(p->to.type == D_NONE) { 324 info->reguse |= AX; 325 info->regset |= AX | DX; 326 } else { 327 info->flags |= RightRdwr; 328 } 329 } 330 331 // Addressing makes some registers used. 332 if(p->from.type >= D_INDIR) 333 info->regindex |= RtoB(p->from.type-D_INDIR); 334 if(p->from.index != D_NONE) 335 info->regindex |= RtoB(p->from.index); 336 if(p->to.type >= D_INDIR) 337 info->regindex |= RtoB(p->to.type-D_INDIR); 338 if(p->to.index != D_NONE) 339 info->regindex |= RtoB(p->to.index); 340 }