github.com/tencent/goom@v1.0.1/internal/arch/arm64asm/arg.go (about) 1 // Package arm64asm arm64指令解析 2 // Generated by ARM internal tool 3 // DO NOT EDIT 4 5 // Copyright 2017 The Go Authors. All rights reserved. 6 // Use of this source code is governed by a BSD-style 7 // license that can be found in the LICENSE file. 8 9 package arm64asm 10 11 // Naming for Go decoder arguments: 12 // 13 // - arg_Wd: a W register encoded in the Rd[4:0] field (31 is wzr) 14 // 15 // - arg_Xd: a X register encoded in the Rd[4:0] field (31 is xzr) 16 // 17 // - arg_Wds: a W register encoded in the Rd[4:0] field (31 is wsp) 18 // 19 // - arg_Xds: a X register encoded in the Rd[4:0] field (31 is sp) 20 // 21 // - arg_Wn: encoded in Rn[9:5] 22 // 23 // - arg_Wm: encoded in Rm[20:16] 24 // 25 // - arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4: 26 // a W register encoded in Rm with an extend encoded in option[15:13] and an amount 27 // encoded in imm3[12:10] in the range [0,4]. 28 // 29 // - arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4: 30 // a W or X register encoded in Rm with an extend encoded in option[15:13] and an 31 // amount encoded in imm3[12:10] in the range [0,4]. If the extend is UXTX or SXTX, 32 // it's an X register else, it's a W register. 33 // 34 // - arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31: 35 // a W register encoded in Rm with a shift encoded in shift[23:22] and an amount 36 // encoded in imm6[15:10] in the range [0,31]. 37 // 38 // - arg_IAddSub: 39 // An immediate for a add/sub instruction encoded in imm12[21:10] with an optional 40 // left shift of 12 encoded in shift[23:22]. 41 // 42 // - arg_Rt_31_1__W_0__X_1: 43 // a W or X register encoded in Rt[4:0]. The width specifier is encoded in the field 44 // [31:31] (offset 31, bit count 1) and the register is W for 0 and X for 1. 45 // 46 // - arg_[s|u]label_FIELDS_POWER: 47 // a program label encoded as "FIELDS" times 2^POWER in the range [MIN, MAX] (determined 48 // by signd/unsigned, FIELDS and POWER), e.g. 49 // arg_slabel_imm14_2 50 // arg_slabel_imm19_2 51 // arg_slabel_imm26_2 52 // arg_slabel_immhi_immlo_0 53 // arg_slabel_immhi_immlo_12 54 // 55 // - arg_Xns_mem_post_imm7_8_signed: 56 // addressing mode of post-index with a base register: Xns and a signed offset encoded 57 // in the "imm7" field times 8 58 // 59 // - arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1: 60 // addressing mode of extended register with a base register: Xns, an offset register 61 // (<Wm>|<Xm>) with an extend encoded in option[15:13] and a shift amount encoded in 62 // S[12:12] in the range [0,3] (S=0:0, S=1:3). 63 // 64 // - arg_Xns_mem_optional_imm12_4_unsigned: 65 // addressing mode of unsigned offset with a base register: Xns and an optional unsigned 66 // offset encoded in the "imm12" field times 4 67 // 68 // - arg_Xns_mem_wb_imm7_4_signed: 69 // addressing mode of pre-index with a base register: Xns and the signed offset encoded 70 // in the "imm7" field times 4 71 // 72 // - arg_Xns_mem_post_size_1_8_unsigned__4_0__8_1__16_2__32_3: 73 // a post-index immediate offset, encoded in the "size" field. It can have the following values: 74 // #4 when size = 00 75 // #8 when size = 01 76 // #16 when size = 10 77 // #32 when size = 11 78 // 79 // - arg_immediate_0_127_CRm_op2: 80 // an immediate encoded in "CRm:op2" in the range 0 to 127 81 // 82 // - arg_immediate_bitmask_64_N_imms_immr: 83 // a bitmask immediate for 64-bit variant and encoded in "N:imms:immr" 84 // 85 // - arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms: 86 // an immediate for the <width> bitfield of SBFX 64-bit variant 87 // 88 // - arg_immediate_shift_32_implicit_inverse_imm16_hw: 89 // a 32-bit immediate of the bitwise inverse of which can be encoded in "imm16:hw" 90 // 91 // - arg_cond_[Not]AllowALNV_[Invert|Normal]: 92 // a standard condition, encoded in the "cond" field, excluding (NotAllow) AL and NV with 93 // its least significant bit [Yes|No] inverted, e.g. 94 // arg_cond_AllowALNV_Normal 95 // arg_cond_NotAllowALNV_Invert 96 // 97 // - arg_immediate_OptLSL_amount_16_0_48: 98 // An immediate for MOV[KNZ] instruction encoded in imm16[20:5] with an optional 99 // left shift of 16 in the range [0, 48] encoded in hw[22, 21] 100 // 101 // - arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8: 102 // the left shift amount, in the range 0 to the operand width in bits minus 1, 103 // encoded in the "immh:immb" field. It can have the following values: 104 // (UInt(immh:immb)-8) when immh = 0001 105 // (UInt(immh:immb)-16) when immh = 001x 106 // (UInt(immh:immb)-32) when immh = 01xx 107 // (UInt(immh:immb)-64) when immh = 1xxx 108 // 109 // - arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4: 110 // the right shift amount, in the range 1 to the destination operand width in 111 // bits, encoded in the "immh:immb" field. It can have the following values: 112 // (16-UInt(immh:immb)) when immh = 0001 113 // (32-UInt(immh:immb)) when immh = 001x 114 // (64-UInt(immh:immb)) when immh = 01xx 115 // 116 // - arg_immediate_8x8_a_b_c_d_e_f_g_h: 117 // a 64-bit immediate 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh', 118 // encoded in "a:b:c:d:e:f:g:h". 119 // 120 // - arg_immediate_fbits_min_1_max_32_sub_64_scale: 121 // the number of bits after the binary point in the fixed-point destination, 122 // in the range 1 to 32, encoded as 64 minus "scale". 123 // 124 // - arg_immediate_floatzero: #0.0 125 // 126 // - arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h: 127 // a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, 128 // encoded in "a:b:c:d:e:f:g:h" 129 // 130 // - arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8: 131 // the number of fractional bits, in the range 1 to the operand width, encoded 132 // in the "immh:immb" field. It can have the following values: 133 // (64-UInt(immh:immb)) when immh = 01xx 134 // (128-UInt(immh:immb)) when immh = 1xxx 135 // 136 // - arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10: 137 // the lowest numbered byte element to be extracted, encoded in the "Q:imm4" field. 138 // It can have the following values: 139 // imm4<2:0> when Q = 0, imm4<3> = 0 140 // imm4 when Q = 1, imm4<3> = x 141 // 142 // - arg_sysop_AT_SYS_CR_system: 143 // system operation for system instruction: AT encoded in the "op1:CRm<0>:op2" field 144 // 145 // - arg_prfop_Rt: 146 // prefectch operation encoded in the "Rt" 147 // 148 // - arg_sysreg_o0_op1_CRn_CRm_op2: 149 // system register name encoded in the "o0:op1:CRn:CRm:op2" 150 // 151 // - arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37: 152 // PSTATE field name encoded in the "op1:op2" field 153 // 154 // - arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31: 155 // one register with arrangement specifier encoded in the "size:Q" field which can have the following values: 156 // 8B when size = 00, Q = 0 157 // 16B when size = 00, Q = 1 158 // 4H when size = 01, Q = 0 159 // 8H when size = 01, Q = 1 160 // 2S when size = 10, Q = 0 161 // 4S when size = 10, Q = 1 162 // 2D when size = 11, Q = 1 163 // The encoding size = 11, Q = 0 is reserved. 164 // 165 // - arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31: 166 // three registers with arrangement specifier encoded in the "size:Q" field which can have the following values: 167 // 8B when size = 00, Q = 0 168 // 16B when size = 00, Q = 1 169 // 4H when size = 01, Q = 0 170 // 8H when size = 01, Q = 1 171 // 2S when size = 10, Q = 0 172 // 4S when size = 10, Q = 1 173 // 2D when size = 11, Q = 1 174 // The encoding size = 11, Q = 0 is reserved. 175 // 176 // - arg_Vt_1_arrangement_H_index__Q_S_size_1: 177 // one register with arrangement:H and element index encoded in "Q:S:size<1>". 178 179 type instArg uint16 180 181 // nolint 182 const ( 183 _ instArg = iota 184 arg_Bt 185 arg_Cm 186 arg_Cn 187 arg_cond_AllowALNV_Normal 188 arg_conditional 189 arg_cond_NotAllowALNV_Invert 190 arg_Da 191 arg_Dd 192 arg_Dm 193 arg_Dn 194 arg_Dt 195 arg_Dt2 196 arg_Hd 197 arg_Hn 198 arg_Ht 199 arg_IAddSub 200 arg_immediate_0_127_CRm_op2 201 arg_immediate_0_15_CRm 202 arg_immediate_0_15_nzcv 203 arg_immediate_0_31_imm5 204 arg_immediate_0_31_immr 205 arg_immediate_0_31_imms 206 arg_immediate_0_63_b5_b40 207 arg_immediate_0_63_immh_immb__UIntimmhimmb64_8 208 arg_immediate_0_63_immr 209 arg_immediate_0_63_imms 210 arg_immediate_0_65535_imm16 211 arg_immediate_0_7_op1 212 arg_immediate_0_7_op2 213 arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4 214 arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8 215 arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8 216 arg_immediate_0_width_size__8_0__16_1__32_2 217 arg_immediate_1_64_immh_immb__128UIntimmhimmb_8 218 arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4 219 arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4 220 arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8 221 arg_immediate_8x8_a_b_c_d_e_f_g_h 222 arg_immediate_ASR_SBFM_32M_bitfield_0_31_immr 223 arg_immediate_ASR_SBFM_64M_bitfield_0_63_immr 224 arg_immediate_BFI_BFM_32M_bitfield_lsb_32_immr 225 arg_immediate_BFI_BFM_32M_bitfield_width_32_imms 226 arg_immediate_BFI_BFM_64M_bitfield_lsb_64_immr 227 arg_immediate_BFI_BFM_64M_bitfield_width_64_imms 228 arg_immediate_BFXIL_BFM_32M_bitfield_lsb_32_immr 229 arg_immediate_BFXIL_BFM_32M_bitfield_width_32_imms 230 arg_immediate_BFXIL_BFM_64M_bitfield_lsb_64_immr 231 arg_immediate_BFXIL_BFM_64M_bitfield_width_64_imms 232 arg_immediate_bitmask_32_imms_immr 233 arg_immediate_bitmask_64_N_imms_immr 234 arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h 235 arg_immediate_exp_3_pre_4_imm8 236 arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8 237 arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8 238 arg_immediate_fbits_min_1_max_32_sub_64_scale 239 arg_immediate_fbits_min_1_max_64_sub_64_scale 240 arg_immediate_floatzero 241 arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10 242 arg_immediate_LSL_UBFM_32M_bitfield_0_31_immr 243 arg_immediate_LSL_UBFM_64M_bitfield_0_63_immr 244 arg_immediate_LSR_UBFM_32M_bitfield_0_31_immr 245 arg_immediate_LSR_UBFM_64M_bitfield_0_63_immr 246 arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1 247 arg_immediate_optional_0_15_CRm 248 arg_immediate_optional_0_65535_imm16 249 arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1 250 arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3 251 arg_immediate_OptLSL_amount_16_0_16 252 arg_immediate_OptLSL_amount_16_0_48 253 arg_immediate_OptLSLZero__a_b_c_d_e_f_g_h 254 arg_immediate_SBFIZ_SBFM_32M_bitfield_lsb_32_immr 255 arg_immediate_SBFIZ_SBFM_32M_bitfield_width_32_imms 256 arg_immediate_SBFIZ_SBFM_64M_bitfield_lsb_64_immr 257 arg_immediate_SBFIZ_SBFM_64M_bitfield_width_64_imms 258 arg_immediate_SBFX_SBFM_32M_bitfield_lsb_32_immr 259 arg_immediate_SBFX_SBFM_32M_bitfield_width_32_imms 260 arg_immediate_SBFX_SBFM_64M_bitfield_lsb_64_immr 261 arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms 262 arg_immediate_shift_32_implicit_imm16_hw 263 arg_immediate_shift_32_implicit_inverse_imm16_hw 264 arg_immediate_shift_64_implicit_imm16_hw 265 arg_immediate_shift_64_implicit_inverse_imm16_hw 266 arg_immediate_UBFIZ_UBFM_32M_bitfield_lsb_32_immr 267 arg_immediate_UBFIZ_UBFM_32M_bitfield_width_32_imms 268 arg_immediate_UBFIZ_UBFM_64M_bitfield_lsb_64_immr 269 arg_immediate_UBFIZ_UBFM_64M_bitfield_width_64_imms 270 arg_immediate_UBFX_UBFM_32M_bitfield_lsb_32_immr 271 arg_immediate_UBFX_UBFM_32M_bitfield_width_32_imms 272 arg_immediate_UBFX_UBFM_64M_bitfield_lsb_64_immr 273 arg_immediate_UBFX_UBFM_64M_bitfield_width_64_imms 274 arg_immediate_zero 275 arg_option_DMB_BO_system_CRm 276 arg_option_DSB_BO_system_CRm 277 arg_option_ISB_BI_system_CRm 278 arg_prfop_Rt 279 arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37 280 arg_Qd 281 arg_Qn 282 arg_Qt 283 arg_Qt2 284 arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4 285 arg_Rn_16_5__W_1__W_2__W_4__X_8 286 arg_Rt_31_1__W_0__X_1 287 arg_Sa 288 arg_Sd 289 arg_slabel_imm14_2 290 arg_slabel_imm19_2 291 arg_slabel_imm26_2 292 arg_slabel_immhi_immlo_0 293 arg_slabel_immhi_immlo_12 294 arg_Sm 295 arg_Sn 296 arg_St 297 arg_St2 298 arg_sysop_AT_SYS_CR_system 299 arg_sysop_DC_SYS_CR_system 300 arg_sysop_IC_SYS_CR_system 301 arg_sysop_SYS_CR_system 302 arg_sysop_TLBI_SYS_CR_system 303 arg_sysreg_o0_op1_CRn_CRm_op2 304 arg_Vd_16_5__B_1__H_2__S_4__D_8 305 arg_Vd_19_4__B_1__H_2__S_4 306 arg_Vd_19_4__B_1__H_2__S_4__D_8 307 arg_Vd_19_4__D_8 308 arg_Vd_19_4__S_4__D_8 309 arg_Vd_22_1__S_0 310 arg_Vd_22_1__S_0__D_1 311 arg_Vd_22_1__S_1 312 arg_Vd_22_2__B_0__H_1__S_2 313 arg_Vd_22_2__B_0__H_1__S_2__D_3 314 arg_Vd_22_2__D_3 315 arg_Vd_22_2__H_0__S_1__D_2 316 arg_Vd_22_2__H_1__S_2 317 arg_Vd_22_2__S_1__D_2 318 arg_Vd_arrangement_16B 319 arg_Vd_arrangement_2D 320 arg_Vd_arrangement_4S 321 arg_Vd_arrangement_D_index__1 322 arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1 323 arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81 324 arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81 325 arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41 326 arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81 327 arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4 328 arg_Vd_arrangement_Q___2S_0__4S_1 329 arg_Vd_arrangement_Q___4H_0__8H_1 330 arg_Vd_arrangement_Q___8B_0__16B_1 331 arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11 332 arg_Vd_arrangement_size___4S_1__2D_2 333 arg_Vd_arrangement_size___8H_0__1Q_3 334 arg_Vd_arrangement_size___8H_0__4S_1__2D_2 335 arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21 336 arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21 337 arg_Vd_arrangement_size_Q___8B_00__16B_01 338 arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11 339 arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21 340 arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 341 arg_Vd_arrangement_sz___4S_0__2D_1 342 arg_Vd_arrangement_sz_Q___2S_00__4S_01 343 arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11 344 arg_Vd_arrangement_sz_Q___2S_10__4S_11 345 arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11 346 arg_Vm_22_1__S_0__D_1 347 arg_Vm_22_2__B_0__H_1__S_2__D_3 348 arg_Vm_22_2__D_3 349 arg_Vm_22_2__H_1__S_2 350 arg_Vm_arrangement_4S 351 arg_Vm_arrangement_Q___8B_0__16B_1 352 arg_Vm_arrangement_size___8H_0__4S_1__2D_2 353 arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1 354 arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21 355 arg_Vm_arrangement_size_Q___8B_00__16B_01 356 arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31 357 arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21 358 arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 359 arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11 360 arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1 361 arg_Vn_19_4__B_1__H_2__S_4__D_8 362 arg_Vn_19_4__D_8 363 arg_Vn_19_4__H_1__S_2__D_4 364 arg_Vn_19_4__S_4__D_8 365 arg_Vn_1_arrangement_16B 366 arg_Vn_22_1__D_1 367 arg_Vn_22_1__S_0__D_1 368 arg_Vn_22_2__B_0__H_1__S_2__D_3 369 arg_Vn_22_2__D_3 370 arg_Vn_22_2__H_0__S_1__D_2 371 arg_Vn_22_2__H_1__S_2 372 arg_Vn_2_arrangement_16B 373 arg_Vn_3_arrangement_16B 374 arg_Vn_4_arrangement_16B 375 arg_Vn_arrangement_16B 376 arg_Vn_arrangement_4S 377 arg_Vn_arrangement_D_index__1 378 arg_Vn_arrangement_D_index__imm5_1 379 arg_Vn_arrangement_imm5___B_1__H_2_index__imm5__imm5lt41gt_1__imm5lt42gt_2_1 380 arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1 381 arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1 382 arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1 383 arg_Vn_arrangement_imm5___D_8_index__imm5_1 384 arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81 385 arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41 386 arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81 387 arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4 388 arg_Vn_arrangement_Q___8B_0__16B_1 389 arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11 390 arg_Vn_arrangement_Q_sz___4S_10 391 arg_Vn_arrangement_S_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1 392 arg_Vn_arrangement_size___2D_3 393 arg_Vn_arrangement_size___8H_0__4S_1__2D_2 394 arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21 395 arg_Vn_arrangement_size_Q___8B_00__16B_01 396 arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31 397 arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11 398 arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21 399 arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 400 arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21 401 arg_Vn_arrangement_sz___2D_1 402 arg_Vn_arrangement_sz___2S_0__2D_1 403 arg_Vn_arrangement_sz___4S_0__2D_1 404 arg_Vn_arrangement_sz_Q___2S_00__4S_01 405 arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11 406 arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11 407 arg_Vt_1_arrangement_B_index__Q_S_size_1 408 arg_Vt_1_arrangement_D_index__Q_1 409 arg_Vt_1_arrangement_H_index__Q_S_size_1 410 arg_Vt_1_arrangement_S_index__Q_S_1 411 arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31 412 arg_Vt_2_arrangement_B_index__Q_S_size_1 413 arg_Vt_2_arrangement_D_index__Q_1 414 arg_Vt_2_arrangement_H_index__Q_S_size_1 415 arg_Vt_2_arrangement_S_index__Q_S_1 416 arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31 417 arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 418 arg_Vt_3_arrangement_B_index__Q_S_size_1 419 arg_Vt_3_arrangement_D_index__Q_1 420 arg_Vt_3_arrangement_H_index__Q_S_size_1 421 arg_Vt_3_arrangement_S_index__Q_S_1 422 arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31 423 arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 424 arg_Vt_4_arrangement_B_index__Q_S_size_1 425 arg_Vt_4_arrangement_D_index__Q_1 426 arg_Vt_4_arrangement_H_index__Q_S_size_1 427 arg_Vt_4_arrangement_S_index__Q_S_1 428 arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31 429 arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 430 arg_Wa 431 arg_Wd 432 arg_Wds 433 arg_Wm 434 arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4 435 arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31 436 arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31 437 arg_Wn 438 arg_Wns 439 arg_Ws 440 arg_Wt 441 arg_Wt2 442 arg_Xa 443 arg_Xd 444 arg_Xds 445 arg_Xm 446 arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63 447 arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63 448 arg_Xn 449 arg_Xns 450 arg_Xns_mem 451 arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1 452 arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1 453 arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1 454 arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1 455 arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1 456 arg_Xns_mem_offset 457 arg_Xns_mem_optional_imm12_16_unsigned 458 arg_Xns_mem_optional_imm12_1_unsigned 459 arg_Xns_mem_optional_imm12_2_unsigned 460 arg_Xns_mem_optional_imm12_4_unsigned 461 arg_Xns_mem_optional_imm12_8_unsigned 462 arg_Xns_mem_optional_imm7_16_signed 463 arg_Xns_mem_optional_imm7_4_signed 464 arg_Xns_mem_optional_imm7_8_signed 465 arg_Xns_mem_optional_imm9_1_signed 466 arg_Xns_mem_post_fixedimm_1 467 arg_Xns_mem_post_fixedimm_12 468 arg_Xns_mem_post_fixedimm_16 469 arg_Xns_mem_post_fixedimm_2 470 arg_Xns_mem_post_fixedimm_24 471 arg_Xns_mem_post_fixedimm_3 472 arg_Xns_mem_post_fixedimm_32 473 arg_Xns_mem_post_fixedimm_4 474 arg_Xns_mem_post_fixedimm_6 475 arg_Xns_mem_post_fixedimm_8 476 arg_Xns_mem_post_imm7_16_signed 477 arg_Xns_mem_post_imm7_4_signed 478 arg_Xns_mem_post_imm7_8_signed 479 arg_Xns_mem_post_imm9_1_signed 480 arg_Xns_mem_post_Q__16_0__32_1 481 arg_Xns_mem_post_Q__24_0__48_1 482 arg_Xns_mem_post_Q__32_0__64_1 483 arg_Xns_mem_post_Q__8_0__16_1 484 arg_Xns_mem_post_size__1_0__2_1__4_2__8_3 485 arg_Xns_mem_post_size__2_0__4_1__8_2__16_3 486 arg_Xns_mem_post_size__3_0__6_1__12_2__24_3 487 arg_Xns_mem_post_size__4_0__8_1__16_2__32_3 488 arg_Xns_mem_post_Xm 489 arg_Xns_mem_wb_imm7_16_signed 490 arg_Xns_mem_wb_imm7_4_signed 491 arg_Xns_mem_wb_imm7_8_signed 492 arg_Xns_mem_wb_imm9_1_signed 493 arg_Xs 494 arg_Xt 495 arg_Xt2 496 )