github.com/tetratelabs/wazero@v1.7.3-0.20240513003603-48f702e154b5/internal/engine/wazevo/backend/isa/amd64/instr_test.go (about)

     1  package amd64
     2  
     3  import (
     4  	"testing"
     5  
     6  	"github.com/tetratelabs/wazero/internal/engine/wazevo/backend/regalloc"
     7  	"github.com/tetratelabs/wazero/internal/testing/require"
     8  )
     9  
    10  func TestMachine_lowerAluRmiROp_Uses_AssignUse(t *testing.T) {
    11  	vr0 := regalloc.VReg(0).SetRegType(regalloc.RegTypeInt)
    12  	vr1 := regalloc.VReg(1).SetRegType(regalloc.RegTypeInt)
    13  	tests := []struct {
    14  		name     string
    15  		instr    func(*instruction)
    16  		expected string
    17  	}{
    18  		{
    19  			name:     "reg_reg",
    20  			instr:    func(i *instruction) { i.asAluRmiR(aluRmiROpcodeAdd, newOperandReg(vr0), vr1, false) },
    21  			expected: "add %eax, %ecx",
    22  		},
    23  		{
    24  			name: "mem_reg",
    25  			instr: func(i *instruction) {
    26  				_, _, m := newSetupWithMockContext()
    27  				i.asAluRmiR(aluRmiROpcodeAdd, newOperandMem(m.newAmodeImmReg(123, vr0)), vr1, false)
    28  			},
    29  			expected: "add 123(%rax), %ecx",
    30  		},
    31  		{
    32  			name:     "imm_reg",
    33  			instr:    func(i *instruction) { i.asAluRmiR(aluRmiROpcodeAdd, newOperandImm32(123), vr1, false) },
    34  			expected: "add $123, %eax",
    35  		},
    36  	}
    37  	rs := []regalloc.RealReg{rax, rcx}
    38  	for _, tt := range tests {
    39  		tc := tt
    40  		t.Run(tt.name, func(t *testing.T) {
    41  			regs := &[]regalloc.VReg{}
    42  			instr := &instruction{}
    43  			tc.instr(instr)
    44  			for i, use := range instr.Uses(regs) {
    45  				instr.AssignUse(i, use.SetRealReg(rs[i]))
    46  			}
    47  			require.Equal(t, tc.expected, instr.String())
    48  		})
    49  	}
    50  }