github.com/tidwall/go@v0.0.0-20170415222209-6694a6888b7d/src/cmd/compile/internal/ssa/gen/S390X.rules (about) 1 // Copyright 2016 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 // Lowering arithmetic 6 (Add64 x y) -> (ADD x y) 7 (AddPtr x y) -> (ADD x y) 8 (Add32 x y) -> (ADDW x y) 9 (Add16 x y) -> (ADDW x y) 10 (Add8 x y) -> (ADDW x y) 11 (Add32F x y) -> (FADDS x y) 12 (Add64F x y) -> (FADD x y) 13 14 (Sub64 x y) -> (SUB x y) 15 (SubPtr x y) -> (SUB x y) 16 (Sub32 x y) -> (SUBW x y) 17 (Sub16 x y) -> (SUBW x y) 18 (Sub8 x y) -> (SUBW x y) 19 (Sub32F x y) -> (FSUBS x y) 20 (Sub64F x y) -> (FSUB x y) 21 22 (Mul64 x y) -> (MULLD x y) 23 (Mul32 x y) -> (MULLW x y) 24 (Mul16 x y) -> (MULLW x y) 25 (Mul8 x y) -> (MULLW x y) 26 (Mul32F x y) -> (FMULS x y) 27 (Mul64F x y) -> (FMUL x y) 28 29 (Div32F x y) -> (FDIVS x y) 30 (Div64F x y) -> (FDIV x y) 31 32 (Div64 x y) -> (DIVD x y) 33 (Div64u x y) -> (DIVDU x y) 34 // DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor, 35 // so a sign/zero extension of the dividend is required. 36 (Div32 x y) -> (DIVW (MOVWreg x) y) 37 (Div32u x y) -> (DIVWU (MOVWZreg x) y) 38 (Div16 x y) -> (DIVW (MOVHreg x) (MOVHreg y)) 39 (Div16u x y) -> (DIVWU (MOVHZreg x) (MOVHZreg y)) 40 (Div8 x y) -> (DIVW (MOVBreg x) (MOVBreg y)) 41 (Div8u x y) -> (DIVWU (MOVBZreg x) (MOVBZreg y)) 42 43 (Hmul64 x y) -> (MULHD x y) 44 (Hmul64u x y) -> (MULHDU x y) 45 (Hmul32 x y) -> (SRDconst [32] (MULLD (MOVWreg x) (MOVWreg y))) 46 (Hmul32u x y) -> (SRDconst [32] (MULLD (MOVWZreg x) (MOVWZreg y))) 47 48 (Mod64 x y) -> (MODD x y) 49 (Mod64u x y) -> (MODDU x y) 50 // MODW/MODWU has a 64-bit dividend and a 32-bit divisor, 51 // so a sign/zero extension of the dividend is required. 52 (Mod32 x y) -> (MODW (MOVWreg x) y) 53 (Mod32u x y) -> (MODWU (MOVWZreg x) y) 54 (Mod16 x y) -> (MODW (MOVHreg x) (MOVHreg y)) 55 (Mod16u x y) -> (MODWU (MOVHZreg x) (MOVHZreg y)) 56 (Mod8 x y) -> (MODW (MOVBreg x) (MOVBreg y)) 57 (Mod8u x y) -> (MODWU (MOVBZreg x) (MOVBZreg y)) 58 59 // (x + y) / 2 with x>=y -> (x - y) / 2 + y 60 (Avg64u <t> x y) -> (ADD (SRDconst <t> (SUB <t> x y) [1]) y) 61 62 (And64 x y) -> (AND x y) 63 (And32 x y) -> (ANDW x y) 64 (And16 x y) -> (ANDW x y) 65 (And8 x y) -> (ANDW x y) 66 67 (Or64 x y) -> (OR x y) 68 (Or32 x y) -> (ORW x y) 69 (Or16 x y) -> (ORW x y) 70 (Or8 x y) -> (ORW x y) 71 72 (Xor64 x y) -> (XOR x y) 73 (Xor32 x y) -> (XORW x y) 74 (Xor16 x y) -> (XORW x y) 75 (Xor8 x y) -> (XORW x y) 76 77 (Neg64 x) -> (NEG x) 78 (Neg32 x) -> (NEGW x) 79 (Neg16 x) -> (NEGW (MOVHreg x)) 80 (Neg8 x) -> (NEGW (MOVBreg x)) 81 (Neg32F x) -> (FNEGS x) 82 (Neg64F x) -> (FNEG x) 83 84 (Com64 x) -> (NOT x) 85 (Com32 x) -> (NOTW x) 86 (Com16 x) -> (NOTW x) 87 (Com8 x) -> (NOTW x) 88 (NOT x) && true -> (XOR (MOVDconst [-1]) x) 89 (NOTW x) && true -> (XORWconst [-1] x) 90 91 // Lowering boolean ops 92 (AndB x y) -> (ANDW x y) 93 (OrB x y) -> (ORW x y) 94 (Not x) -> (XORWconst [1] x) 95 96 // Lowering pointer arithmetic 97 (OffPtr [off] ptr:(SP)) -> (MOVDaddr [off] ptr) 98 (OffPtr [off] ptr) && is32Bit(off) -> (ADDconst [off] ptr) 99 (OffPtr [off] ptr) -> (ADD (MOVDconst [off]) ptr) 100 101 // Ctz(x) = 64 - findLeftmostOne((x-1)&^x) 102 (Ctz64 <t> x) -> (SUB (MOVDconst [64]) (FLOGR (AND <t> (SUBconst <t> [1] x) (NOT <t> x)))) 103 (Ctz32 <t> x) -> (SUB (MOVDconst [64]) (FLOGR (MOVWZreg (ANDW <t> (SUBWconst <t> [1] x) (NOTW <t> x))))) 104 105 (BitLen64 x) -> (SUB (MOVDconst [64]) (FLOGR x)) 106 107 (Bswap64 x) -> (MOVDBR x) 108 (Bswap32 x) -> (MOVWBR x) 109 110 (Sqrt x) -> (FSQRT x) 111 112 // Atomic loads. 113 (AtomicLoad32 ptr mem) -> (MOVWZatomicload ptr mem) 114 (AtomicLoad64 ptr mem) -> (MOVDatomicload ptr mem) 115 (AtomicLoadPtr ptr mem) -> (MOVDatomicload ptr mem) 116 117 // Atomic stores. 118 (AtomicStore32 ptr val mem) -> (MOVWatomicstore ptr val mem) 119 (AtomicStore64 ptr val mem) -> (MOVDatomicstore ptr val mem) 120 (AtomicStorePtrNoWB ptr val mem) -> (MOVDatomicstore ptr val mem) 121 122 // Atomic adds. 123 (AtomicAdd32 ptr val mem) -> (AddTupleFirst32 (LAA ptr val mem) val) 124 (AtomicAdd64 ptr val mem) -> (AddTupleFirst64 (LAAG ptr val mem) val) 125 (Select0 <t> (AddTupleFirst32 tuple val)) -> (ADDW val (Select0 <t> tuple)) 126 (Select1 (AddTupleFirst32 tuple _ )) -> (Select1 tuple) 127 (Select0 <t> (AddTupleFirst64 tuple val)) -> (ADD val (Select0 <t> tuple)) 128 (Select1 (AddTupleFirst64 tuple _ )) -> (Select1 tuple) 129 130 // Atomic exchanges. 131 (AtomicExchange32 ptr val mem) -> (LoweredAtomicExchange32 ptr val mem) 132 (AtomicExchange64 ptr val mem) -> (LoweredAtomicExchange64 ptr val mem) 133 134 // Atomic compare and swap. 135 (AtomicCompareAndSwap32 ptr old new_ mem) -> (LoweredAtomicCas32 ptr old new_ mem) 136 (AtomicCompareAndSwap64 ptr old new_ mem) -> (LoweredAtomicCas64 ptr old new_ mem) 137 138 // Lowering extension 139 // Note: we always extend to 64 bits even though some ops don't need that many result bits. 140 (SignExt8to16 x) -> (MOVBreg x) 141 (SignExt8to32 x) -> (MOVBreg x) 142 (SignExt8to64 x) -> (MOVBreg x) 143 (SignExt16to32 x) -> (MOVHreg x) 144 (SignExt16to64 x) -> (MOVHreg x) 145 (SignExt32to64 x) -> (MOVWreg x) 146 147 (ZeroExt8to16 x) -> (MOVBZreg x) 148 (ZeroExt8to32 x) -> (MOVBZreg x) 149 (ZeroExt8to64 x) -> (MOVBZreg x) 150 (ZeroExt16to32 x) -> (MOVHZreg x) 151 (ZeroExt16to64 x) -> (MOVHZreg x) 152 (ZeroExt32to64 x) -> (MOVWZreg x) 153 154 (Slicemask <t> x) -> (SRADconst (NEG <t> x) [63]) 155 156 // Lowering truncation 157 // Because we ignore high parts of registers, truncates are just copies. 158 (Trunc16to8 x) -> x 159 (Trunc32to8 x) -> x 160 (Trunc32to16 x) -> x 161 (Trunc64to8 x) -> x 162 (Trunc64to16 x) -> x 163 (Trunc64to32 x) -> x 164 165 // Lowering float <-> int 166 (Cvt32to32F x) -> (CEFBRA x) 167 (Cvt32to64F x) -> (CDFBRA x) 168 (Cvt64to32F x) -> (CEGBRA x) 169 (Cvt64to64F x) -> (CDGBRA x) 170 171 (Cvt32Fto32 x) -> (CFEBRA x) 172 (Cvt32Fto64 x) -> (CGEBRA x) 173 (Cvt64Fto32 x) -> (CFDBRA x) 174 (Cvt64Fto64 x) -> (CGDBRA x) 175 176 (Cvt32Fto64F x) -> (LDEBR x) 177 (Cvt64Fto32F x) -> (LEDBR x) 178 179 (Round32F x) -> (LoweredRound32F x) 180 (Round64F x) -> (LoweredRound64F x) 181 182 // Lowering shifts 183 // Unsigned shifts need to return 0 if shift amount is >= width of shifted value. 184 // result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff) 185 (Lsh64x64 <t> x y) -> (AND (SLD <t> x y) (SUBEcarrymask <t> (CMPUconst y [63]))) 186 (Lsh64x32 <t> x y) -> (AND (SLD <t> x y) (SUBEcarrymask <t> (CMPWUconst y [63]))) 187 (Lsh64x16 <t> x y) -> (AND (SLD <t> x y) (SUBEcarrymask <t> (CMPWUconst (MOVHZreg y) [63]))) 188 (Lsh64x8 <t> x y) -> (AND (SLD <t> x y) (SUBEcarrymask <t> (CMPWUconst (MOVBZreg y) [63]))) 189 190 (Lsh32x64 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPUconst y [31]))) 191 (Lsh32x32 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst y [31]))) 192 (Lsh32x16 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [31]))) 193 (Lsh32x8 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [31]))) 194 195 (Lsh16x64 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPUconst y [31]))) 196 (Lsh16x32 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst y [31]))) 197 (Lsh16x16 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [31]))) 198 (Lsh16x8 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [31]))) 199 200 (Lsh8x64 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPUconst y [31]))) 201 (Lsh8x32 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst y [31]))) 202 (Lsh8x16 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [31]))) 203 (Lsh8x8 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [31]))) 204 205 (Rsh64Ux64 <t> x y) -> (AND (SRD <t> x y) (SUBEcarrymask <t> (CMPUconst y [63]))) 206 (Rsh64Ux32 <t> x y) -> (AND (SRD <t> x y) (SUBEcarrymask <t> (CMPWUconst y [63]))) 207 (Rsh64Ux16 <t> x y) -> (AND (SRD <t> x y) (SUBEcarrymask <t> (CMPWUconst (MOVHZreg y) [63]))) 208 (Rsh64Ux8 <t> x y) -> (AND (SRD <t> x y) (SUBEcarrymask <t> (CMPWUconst (MOVBZreg y) [63]))) 209 210 (Rsh32Ux64 <t> x y) -> (ANDW (SRW <t> x y) (SUBEWcarrymask <t> (CMPUconst y [31]))) 211 (Rsh32Ux32 <t> x y) -> (ANDW (SRW <t> x y) (SUBEWcarrymask <t> (CMPWUconst y [31]))) 212 (Rsh32Ux16 <t> x y) -> (ANDW (SRW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [31]))) 213 (Rsh32Ux8 <t> x y) -> (ANDW (SRW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [31]))) 214 215 (Rsh16Ux64 <t> x y) -> (ANDW (SRW <t> (MOVHZreg x) y) (SUBEWcarrymask <t> (CMPUconst y [15]))) 216 (Rsh16Ux32 <t> x y) -> (ANDW (SRW <t> (MOVHZreg x) y) (SUBEWcarrymask <t> (CMPWUconst y [15]))) 217 (Rsh16Ux16 <t> x y) -> (ANDW (SRW <t> (MOVHZreg x) y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [15]))) 218 (Rsh16Ux8 <t> x y) -> (ANDW (SRW <t> (MOVHZreg x) y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [15]))) 219 220 (Rsh8Ux64 <t> x y) -> (ANDW (SRW <t> (MOVBZreg x) y) (SUBEWcarrymask <t> (CMPUconst y [7]))) 221 (Rsh8Ux32 <t> x y) -> (ANDW (SRW <t> (MOVBZreg x) y) (SUBEWcarrymask <t> (CMPWUconst y [7]))) 222 (Rsh8Ux16 <t> x y) -> (ANDW (SRW <t> (MOVBZreg x) y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [7]))) 223 (Rsh8Ux8 <t> x y) -> (ANDW (SRW <t> (MOVBZreg x) y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [7]))) 224 225 // Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value. 226 // We implement this by setting the shift value to -1 (all ones) if the shift value is >= width. 227 (Rsh64x64 <t> x y) -> (SRAD <t> x (OR <y.Type> y (NOT <y.Type> (SUBEcarrymask <y.Type> (CMPUconst y [63]))))) 228 (Rsh64x32 <t> x y) -> (SRAD <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst y [63]))))) 229 (Rsh64x16 <t> x y) -> (SRAD <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVHZreg y) [63]))))) 230 (Rsh64x8 <t> x y) -> (SRAD <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVBZreg y) [63]))))) 231 232 (Rsh32x64 <t> x y) -> (SRAW <t> x (OR <y.Type> y (NOT <y.Type> (SUBEcarrymask <y.Type> (CMPUconst y [31]))))) 233 (Rsh32x32 <t> x y) -> (SRAW <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst y [31]))))) 234 (Rsh32x16 <t> x y) -> (SRAW <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVHZreg y) [31]))))) 235 (Rsh32x8 <t> x y) -> (SRAW <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVBZreg y) [31]))))) 236 237 (Rsh16x64 <t> x y) -> (SRAW <t> (MOVHreg x) (OR <y.Type> y (NOT <y.Type> (SUBEcarrymask <y.Type> (CMPUconst y [15]))))) 238 (Rsh16x32 <t> x y) -> (SRAW <t> (MOVHreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst y [15]))))) 239 (Rsh16x16 <t> x y) -> (SRAW <t> (MOVHreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVHZreg y) [15]))))) 240 (Rsh16x8 <t> x y) -> (SRAW <t> (MOVHreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVBZreg y) [15]))))) 241 242 (Rsh8x64 <t> x y) -> (SRAW <t> (MOVBreg x) (OR <y.Type> y (NOT <y.Type> (SUBEcarrymask <y.Type> (CMPUconst y [7]))))) 243 (Rsh8x32 <t> x y) -> (SRAW <t> (MOVBreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst y [7]))))) 244 (Rsh8x16 <t> x y) -> (SRAW <t> (MOVBreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVHZreg y) [7]))))) 245 (Rsh8x8 <t> x y) -> (SRAW <t> (MOVBreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVBZreg y) [7]))))) 246 247 // Lowering comparisons 248 (Less64 x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 249 (Less32 x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 250 (Less16 x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 251 (Less8 x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 252 (Less64U x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPU x y)) 253 (Less32U x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y)) 254 (Less16U x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVHZreg x) (MOVHZreg y))) 255 (Less8U x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVBZreg x) (MOVBZreg y))) 256 // Use SETG with reversed operands to dodge NaN case. 257 (Less64F x y) -> (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMP y x)) 258 (Less32F x y) -> (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMPS y x)) 259 260 (Leq64 x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 261 (Leq32 x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 262 (Leq16 x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 263 (Leq8 x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 264 (Leq64U x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPU x y)) 265 (Leq32U x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y)) 266 (Leq16U x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVHZreg x) (MOVHZreg y))) 267 (Leq8U x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVBZreg x) (MOVBZreg y))) 268 // Use SETGE with reversed operands to dodge NaN case. 269 (Leq64F x y) -> (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMP y x)) 270 (Leq32F x y) -> (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMPS y x)) 271 272 (Greater64 x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 273 (Greater32 x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 274 (Greater16 x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 275 (Greater8 x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 276 (Greater64U x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPU x y)) 277 (Greater32U x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y)) 278 (Greater16U x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVHZreg x) (MOVHZreg y))) 279 (Greater8U x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVBZreg x) (MOVBZreg y))) 280 (Greater64F x y) -> (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMP x y)) 281 (Greater32F x y) -> (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y)) 282 283 (Geq64 x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 284 (Geq32 x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 285 (Geq16 x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 286 (Geq8 x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 287 (Geq64U x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPU x y)) 288 (Geq32U x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y)) 289 (Geq16U x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVHZreg x) (MOVHZreg y))) 290 (Geq8U x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVBZreg x) (MOVBZreg y))) 291 (Geq64F x y) -> (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMP x y)) 292 (Geq32F x y) -> (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y)) 293 294 (Eq64 x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 295 (Eq32 x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 296 (Eq16 x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 297 (Eq8 x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 298 (EqB x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 299 (EqPtr x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 300 (Eq64F x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (FCMP x y)) 301 (Eq32F x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y)) 302 303 (Neq64 x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 304 (Neq32 x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 305 (Neq16 x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 306 (Neq8 x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 307 (NeqB x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 308 (NeqPtr x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 309 (Neq64F x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (FCMP x y)) 310 (Neq32F x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y)) 311 312 // Lowering loads 313 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) -> (MOVDload ptr mem) 314 (Load <t> ptr mem) && is32BitInt(t) && isSigned(t) -> (MOVWload ptr mem) 315 (Load <t> ptr mem) && is32BitInt(t) && !isSigned(t) -> (MOVWZload ptr mem) 316 (Load <t> ptr mem) && is16BitInt(t) && isSigned(t) -> (MOVHload ptr mem) 317 (Load <t> ptr mem) && is16BitInt(t) && !isSigned(t) -> (MOVHZload ptr mem) 318 (Load <t> ptr mem) && is8BitInt(t) && isSigned(t) -> (MOVBload ptr mem) 319 (Load <t> ptr mem) && (t.IsBoolean() || (is8BitInt(t) && !isSigned(t))) -> (MOVBZload ptr mem) 320 (Load <t> ptr mem) && is32BitFloat(t) -> (FMOVSload ptr mem) 321 (Load <t> ptr mem) && is64BitFloat(t) -> (FMOVDload ptr mem) 322 323 // Lowering stores 324 // These more-specific FP versions of Store pattern should come first. 325 (Store {t} ptr val mem) && t.(Type).Size() == 8 && is64BitFloat(val.Type) -> (FMOVDstore ptr val mem) 326 (Store {t} ptr val mem) && t.(Type).Size() == 4 && is32BitFloat(val.Type) -> (FMOVSstore ptr val mem) 327 328 (Store {t} ptr val mem) && t.(Type).Size() == 8 -> (MOVDstore ptr val mem) 329 (Store {t} ptr val mem) && t.(Type).Size() == 4 -> (MOVWstore ptr val mem) 330 (Store {t} ptr val mem) && t.(Type).Size() == 2 -> (MOVHstore ptr val mem) 331 (Store {t} ptr val mem) && t.(Type).Size() == 1 -> (MOVBstore ptr val mem) 332 333 // Lowering moves 334 335 // Load and store for small copies. 336 (Move [0] _ _ mem) -> mem 337 (Move [1] dst src mem) -> (MOVBstore dst (MOVBZload src mem) mem) 338 (Move [2] dst src mem) -> (MOVHstore dst (MOVHZload src mem) mem) 339 (Move [4] dst src mem) -> (MOVWstore dst (MOVWZload src mem) mem) 340 (Move [8] dst src mem) -> (MOVDstore dst (MOVDload src mem) mem) 341 (Move [16] dst src mem) -> 342 (MOVDstore [8] dst (MOVDload [8] src mem) 343 (MOVDstore dst (MOVDload src mem) mem)) 344 (Move [24] dst src mem) -> 345 (MOVDstore [16] dst (MOVDload [16] src mem) 346 (MOVDstore [8] dst (MOVDload [8] src mem) 347 (MOVDstore dst (MOVDload src mem) mem))) 348 (Move [3] dst src mem) -> 349 (MOVBstore [2] dst (MOVBZload [2] src mem) 350 (MOVHstore dst (MOVHZload src mem) mem)) 351 (Move [5] dst src mem) -> 352 (MOVBstore [4] dst (MOVBZload [4] src mem) 353 (MOVWstore dst (MOVWZload src mem) mem)) 354 (Move [6] dst src mem) -> 355 (MOVHstore [4] dst (MOVHZload [4] src mem) 356 (MOVWstore dst (MOVWZload src mem) mem)) 357 (Move [7] dst src mem) -> 358 (MOVBstore [6] dst (MOVBZload [6] src mem) 359 (MOVHstore [4] dst (MOVHZload [4] src mem) 360 (MOVWstore dst (MOVWZload src mem) mem))) 361 362 // MVC for other moves. Use up to 4 instructions (sizes up to 1024 bytes). 363 (Move [s] dst src mem) && s > 0 && s <= 256 -> 364 (MVC [makeValAndOff(s, 0)] dst src mem) 365 (Move [s] dst src mem) && s > 256 && s <= 512 -> 366 (MVC [makeValAndOff(s-256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem)) 367 (Move [s] dst src mem) && s > 512 && s <= 768 -> 368 (MVC [makeValAndOff(s-512, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem))) 369 (Move [s] dst src mem) && s > 768 && s <= 1024 -> 370 (MVC [makeValAndOff(s-768, 768)] dst src (MVC [makeValAndOff(256, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem)))) 371 372 // Move more than 1024 bytes using a loop. 373 (Move [s] dst src mem) && s > 1024 -> 374 (LoweredMove [s%256] dst src (ADDconst <src.Type> src [(s/256)*256]) mem) 375 376 // Lowering Zero instructions 377 (Zero [0] _ mem) -> mem 378 (Zero [1] destptr mem) -> (MOVBstoreconst [0] destptr mem) 379 (Zero [2] destptr mem) -> (MOVHstoreconst [0] destptr mem) 380 (Zero [4] destptr mem) -> (MOVWstoreconst [0] destptr mem) 381 (Zero [8] destptr mem) -> (MOVDstoreconst [0] destptr mem) 382 (Zero [3] destptr mem) -> 383 (MOVBstoreconst [makeValAndOff(0,2)] destptr 384 (MOVHstoreconst [0] destptr mem)) 385 (Zero [5] destptr mem) -> 386 (MOVBstoreconst [makeValAndOff(0,4)] destptr 387 (MOVWstoreconst [0] destptr mem)) 388 (Zero [6] destptr mem) -> 389 (MOVHstoreconst [makeValAndOff(0,4)] destptr 390 (MOVWstoreconst [0] destptr mem)) 391 (Zero [7] destptr mem) -> 392 (MOVWstoreconst [makeValAndOff(0,3)] destptr 393 (MOVWstoreconst [0] destptr mem)) 394 395 (Zero [s] destptr mem) && s > 0 && s <= 1024 -> 396 (CLEAR [makeValAndOff(s, 0)] destptr mem) 397 398 // Move more than 1024 bytes using a loop. 399 (Zero [s] destptr mem) && s > 1024 -> 400 (LoweredZero [s%256] destptr (ADDconst <destptr.Type> destptr [(s/256)*256]) mem) 401 402 // Lowering constants 403 (Const8 [val]) -> (MOVDconst [val]) 404 (Const16 [val]) -> (MOVDconst [val]) 405 (Const32 [val]) -> (MOVDconst [val]) 406 (Const64 [val]) -> (MOVDconst [val]) 407 (Const32F [val]) -> (FMOVSconst [val]) 408 (Const64F [val]) -> (FMOVDconst [val]) 409 (ConstNil) -> (MOVDconst [0]) 410 (ConstBool [b]) -> (MOVDconst [b]) 411 412 // Lowering calls 413 (StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem) 414 (ClosureCall [argwid] entry closure mem) -> (CALLclosure [argwid] entry closure mem) 415 (InterCall [argwid] entry mem) -> (CALLinter [argwid] entry mem) 416 417 // Miscellaneous 418 (Convert <t> x mem) -> (MOVDconvert <t> x mem) 419 (IsNonNil p) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMPconst p [0])) 420 (IsInBounds idx len) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPU idx len)) 421 (IsSliceInBounds idx len) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPU idx len)) 422 (NilCheck ptr mem) -> (LoweredNilCheck ptr mem) 423 (GetG mem) -> (LoweredGetG mem) 424 (GetClosurePtr) -> (LoweredGetClosurePtr) 425 (Addr {sym} base) -> (MOVDaddr {sym} base) 426 (ITab (Load ptr mem)) -> (MOVDload ptr mem) 427 428 // block rewrites 429 (If (MOVDLT (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (LT cmp yes no) 430 (If (MOVDLE (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (LE cmp yes no) 431 (If (MOVDGT (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (GT cmp yes no) 432 (If (MOVDGE (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (GE cmp yes no) 433 (If (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (EQ cmp yes no) 434 (If (MOVDNE (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (NE cmp yes no) 435 436 // Special case for floating point - LF/LEF not generated. 437 (If (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (GTF cmp yes no) 438 (If (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (GEF cmp yes no) 439 440 (If cond yes no) -> (NE (CMPWconst [0] (MOVBZreg <types.Bool> cond)) yes no) 441 442 // *************************** 443 // Above: lowering rules 444 // Below: optimizations 445 // *************************** 446 // TODO: Should the optimizations be a separate pass? 447 448 // Fold unnecessary type conversions. 449 (MOVDreg <t> x) && t.Compare(x.Type) == CMPeq -> x 450 (MOVDnop <t> x) && t.Compare(x.Type) == CMPeq -> x 451 452 // Propagate constants through type conversions. 453 (MOVDreg (MOVDconst [c])) -> (MOVDconst [c]) 454 (MOVDnop (MOVDconst [c])) -> (MOVDconst [c]) 455 456 // If a register move has only 1 use, just use the same register without emitting instruction. 457 // MOVDnop doesn't emit instruction, only for ensuring the type. 458 (MOVDreg x) && x.Uses == 1 -> (MOVDnop x) 459 460 // Fold type changes into loads. 461 (MOVDreg <t> x:(MOVBZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZload <t> [off] {sym} ptr mem) 462 (MOVDreg <t> x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <t> [off] {sym} ptr mem) 463 (MOVDreg <t> x:(MOVHZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZload <t> [off] {sym} ptr mem) 464 (MOVDreg <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHload <t> [off] {sym} ptr mem) 465 (MOVDreg <t> x:(MOVWZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZload <t> [off] {sym} ptr mem) 466 (MOVDreg <t> x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <t> [off] {sym} ptr mem) 467 (MOVDreg <t> x:(MOVDload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVDload <t> [off] {sym} ptr mem) 468 469 (MOVDnop <t> x:(MOVBZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZload <t> [off] {sym} ptr mem) 470 (MOVDnop <t> x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <t> [off] {sym} ptr mem) 471 (MOVDnop <t> x:(MOVHZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZload <t> [off] {sym} ptr mem) 472 (MOVDnop <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHload <t> [off] {sym} ptr mem) 473 (MOVDnop <t> x:(MOVWZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZload <t> [off] {sym} ptr mem) 474 (MOVDnop <t> x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <t> [off] {sym} ptr mem) 475 (MOVDnop <t> x:(MOVDload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVDload <t> [off] {sym} ptr mem) 476 477 // TODO(mundaym): uncomment rules once signed indexed loads are added. 478 (MOVDreg <t> x:(MOVBZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZloadidx <t> [off] {sym} ptr idx mem) 479 //(MOVDreg <t> x:(MOVBloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBloadidx <t> [off] {sym} ptr idx mem) 480 (MOVDreg <t> x:(MOVHZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZloadidx <t> [off] {sym} ptr idx mem) 481 //(MOVDreg <t> x:(MOVHloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHloadidx <t> [off] {sym} ptr idx mem) 482 (MOVDreg <t> x:(MOVWZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZloadidx <t> [off] {sym} ptr idx mem) 483 //(MOVDreg <t> x:(MOVWloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx <t> [off] {sym} ptr idx mem) 484 (MOVDreg <t> x:(MOVDloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVDloadidx <t> [off] {sym} ptr idx mem) 485 486 (MOVDnop <t> x:(MOVBZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZloadidx <t> [off] {sym} ptr idx mem) 487 //(MOVDnop <t> x:(MOVBloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBloadidx <t> [off] {sym} ptr idx mem) 488 (MOVDnop <t> x:(MOVHZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZloadidx <t> [off] {sym} ptr idx mem) 489 //(MOVDnop <t> x:(MOVHloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHloadidx <t> [off] {sym} ptr idx mem) 490 (MOVDnop <t> x:(MOVWZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZloadidx <t> [off] {sym} ptr idx mem) 491 //(MOVDnop <t> x:(MOVWloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx <t> [off] {sym} ptr idx mem) 492 (MOVDnop <t> x:(MOVDloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVDloadidx <t> [off] {sym} ptr idx mem) 493 494 // Fold sign extensions into conditional moves of constants. 495 // Designed to remove the MOVBZreg inserted by the If lowering. 496 (MOVBZreg x:(MOVDLT (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 497 (MOVBZreg x:(MOVDLE (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 498 (MOVBZreg x:(MOVDGT (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 499 (MOVBZreg x:(MOVDGE (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 500 (MOVBZreg x:(MOVDEQ (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 501 (MOVBZreg x:(MOVDNE (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 502 (MOVBZreg x:(MOVDGTnoinv (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 503 (MOVBZreg x:(MOVDGEnoinv (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 504 505 // Fold boolean tests into blocks. 506 (NE (CMPWconst [0] (MOVDLT (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (LT cmp yes no) 507 (NE (CMPWconst [0] (MOVDLE (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (LE cmp yes no) 508 (NE (CMPWconst [0] (MOVDGT (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (GT cmp yes no) 509 (NE (CMPWconst [0] (MOVDGE (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (GE cmp yes no) 510 (NE (CMPWconst [0] (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (EQ cmp yes no) 511 (NE (CMPWconst [0] (MOVDNE (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (NE cmp yes no) 512 (NE (CMPWconst [0] (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (GTF cmp yes no) 513 (NE (CMPWconst [0] (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (GEF cmp yes no) 514 515 // Fold constants into instructions. 516 (ADD x (MOVDconst [c])) && is32Bit(c) -> (ADDconst [c] x) 517 (ADDW x (MOVDconst [c])) -> (ADDWconst [c] x) 518 519 (SUB x (MOVDconst [c])) && is32Bit(c) -> (SUBconst x [c]) 520 (SUB (MOVDconst [c]) x) && is32Bit(c) -> (NEG (SUBconst <v.Type> x [c])) 521 (SUBW x (MOVDconst [c])) -> (SUBWconst x [c]) 522 (SUBW (MOVDconst [c]) x) -> (NEGW (SUBWconst <v.Type> x [c])) 523 524 (MULLD x (MOVDconst [c])) && is32Bit(c) -> (MULLDconst [c] x) 525 (MULLW x (MOVDconst [c])) -> (MULLWconst [c] x) 526 527 // NILF instructions leave the high 32 bits unchanged which is 528 // equivalent to the leftmost 32 bits being set. 529 // TODO(mundaym): modify the assembler to accept 64-bit values 530 // and use isU32Bit(^c). 531 (AND x (MOVDconst [c])) && is32Bit(c) && c < 0 -> (ANDconst [c] x) 532 (ANDW x (MOVDconst [c])) -> (ANDWconst [c] x) 533 534 (ANDWconst [c] (ANDWconst [d] x)) -> (ANDWconst [c & d] x) 535 (ANDconst [c] (ANDconst [d] x)) -> (ANDconst [c & d] x) 536 537 (OR x (MOVDconst [c])) && isU32Bit(c) -> (ORconst [c] x) 538 (ORW x (MOVDconst [c])) -> (ORWconst [c] x) 539 540 (XOR x (MOVDconst [c])) && isU32Bit(c) -> (XORconst [c] x) 541 (XORW x (MOVDconst [c])) -> (XORWconst [c] x) 542 543 (SLD x (MOVDconst [c])) -> (SLDconst [c&63] x) 544 (SLW x (MOVDconst [c])) -> (SLWconst [c&63] x) 545 (SRD x (MOVDconst [c])) -> (SRDconst [c&63] x) 546 (SRW x (MOVDconst [c])) -> (SRWconst [c&63] x) 547 (SRAD x (MOVDconst [c])) -> (SRADconst [c&63] x) 548 (SRAW x (MOVDconst [c])) -> (SRAWconst [c&63] x) 549 550 (SRAW x (ANDWconst [63] y)) -> (SRAW x y) 551 (SRAD x (ANDconst [63] y)) -> (SRAD x y) 552 (SLW x (ANDWconst [63] y)) -> (SLW x y) 553 (SLD x (ANDconst [63] y)) -> (SLD x y) 554 (SRW x (ANDWconst [63] y)) -> (SRW x y) 555 (SRD x (ANDconst [63] y)) -> (SRD x y) 556 557 // Rotate generation 558 (ADD (SLDconst x [c]) (SRDconst x [d])) && d == 64-c -> (RLLGconst [c] x) 559 ( OR (SLDconst x [c]) (SRDconst x [d])) && d == 64-c -> (RLLGconst [c] x) 560 (XOR (SLDconst x [c]) (SRDconst x [d])) && d == 64-c -> (RLLGconst [c] x) 561 562 (ADDW (SLWconst x [c]) (SRWconst x [d])) && d == 32-c -> (RLLconst [c] x) 563 ( ORW (SLWconst x [c]) (SRWconst x [d])) && d == 32-c -> (RLLconst [c] x) 564 (XORW (SLWconst x [c]) (SRWconst x [d])) && d == 32-c -> (RLLconst [c] x) 565 566 (CMP x (MOVDconst [c])) && is32Bit(c) -> (CMPconst x [c]) 567 (CMP (MOVDconst [c]) x) && is32Bit(c) -> (InvertFlags (CMPconst x [c])) 568 (CMPW x (MOVDconst [c])) -> (CMPWconst x [c]) 569 (CMPW (MOVDconst [c]) x) -> (InvertFlags (CMPWconst x [c])) 570 (CMPU x (MOVDconst [c])) && isU32Bit(c) -> (CMPUconst x [int64(uint32(c))]) 571 (CMPU (MOVDconst [c]) x) && isU32Bit(c) -> (InvertFlags (CMPUconst x [int64(uint32(c))])) 572 (CMPWU x (MOVDconst [c])) -> (CMPWUconst x [int64(uint32(c))]) 573 (CMPWU (MOVDconst [c]) x) -> (InvertFlags (CMPWUconst x [int64(uint32(c))])) 574 575 // Using MOV{W,H,B}Zreg instead of AND is cheaper. 576 (AND x (MOVDconst [0xFF])) -> (MOVBZreg x) 577 (AND x (MOVDconst [0xFFFF])) -> (MOVHZreg x) 578 (AND x (MOVDconst [0xFFFFFFFF])) -> (MOVWZreg x) 579 (ANDWconst [0xFF] x) -> (MOVBZreg x) 580 (ANDWconst [0xFFFF] x) -> (MOVHZreg x) 581 582 // strength reduction 583 (MULLDconst [-1] x) -> (NEG x) 584 (MULLDconst [0] _) -> (MOVDconst [0]) 585 (MULLDconst [1] x) -> x 586 (MULLDconst [c] x) && isPowerOfTwo(c) -> (SLDconst [log2(c)] x) 587 (MULLDconst [c] x) && isPowerOfTwo(c+1) && c >= 15 -> (SUB (SLDconst <v.Type> [log2(c+1)] x) x) 588 (MULLDconst [c] x) && isPowerOfTwo(c-1) && c >= 17 -> (ADD (SLDconst <v.Type> [log2(c-1)] x) x) 589 590 (MULLWconst [-1] x) -> (NEGW x) 591 (MULLWconst [0] _) -> (MOVDconst [0]) 592 (MULLWconst [1] x) -> x 593 (MULLWconst [c] x) && isPowerOfTwo(c) -> (SLWconst [log2(c)] x) 594 (MULLWconst [c] x) && isPowerOfTwo(c+1) && c >= 15 -> (SUBW (SLWconst <v.Type> [log2(c+1)] x) x) 595 (MULLWconst [c] x) && isPowerOfTwo(c-1) && c >= 17 -> (ADDW (SLWconst <v.Type> [log2(c-1)] x) x) 596 597 // Fold ADD into MOVDaddr. Odd offsets from SB shouldn't be folded (LARL can't handle them). 598 (ADDconst [c] (MOVDaddr [d] {s} x:(SB))) && ((c+d)&1 == 0) && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x) 599 (ADDconst [c] (MOVDaddr [d] {s} x)) && x.Op != OpSB && is20Bit(c+d) -> (MOVDaddr [c+d] {s} x) 600 (ADD idx (MOVDaddr [c] {s} ptr)) && ptr.Op != OpSB && idx.Op != OpSB -> (MOVDaddridx [c] {s} ptr idx) 601 602 // fold ADDconst into MOVDaddrx 603 (ADDconst [c] (MOVDaddridx [d] {s} x y)) && is20Bit(c+d) -> (MOVDaddridx [c+d] {s} x y) 604 (MOVDaddridx [c] {s} (ADDconst [d] x) y) && is20Bit(c+d) && x.Op != OpSB -> (MOVDaddridx [c+d] {s} x y) 605 (MOVDaddridx [c] {s} x (ADDconst [d] y)) && is20Bit(c+d) && y.Op != OpSB -> (MOVDaddridx [c+d] {s} x y) 606 607 // reverse ordering of compare instruction 608 (MOVDLT x y (InvertFlags cmp)) -> (MOVDGT x y cmp) 609 (MOVDGT x y (InvertFlags cmp)) -> (MOVDLT x y cmp) 610 (MOVDLE x y (InvertFlags cmp)) -> (MOVDGE x y cmp) 611 (MOVDGE x y (InvertFlags cmp)) -> (MOVDLE x y cmp) 612 (MOVDEQ x y (InvertFlags cmp)) -> (MOVDEQ x y cmp) 613 (MOVDNE x y (InvertFlags cmp)) -> (MOVDNE x y cmp) 614 615 // don't extend after proper load 616 (MOVBreg x:(MOVBload _ _)) -> (MOVDreg x) 617 (MOVBZreg x:(MOVBZload _ _)) -> (MOVDreg x) 618 (MOVHreg x:(MOVBload _ _)) -> (MOVDreg x) 619 (MOVHreg x:(MOVBZload _ _)) -> (MOVDreg x) 620 (MOVHreg x:(MOVHload _ _)) -> (MOVDreg x) 621 (MOVHZreg x:(MOVBZload _ _)) -> (MOVDreg x) 622 (MOVHZreg x:(MOVHZload _ _)) -> (MOVDreg x) 623 (MOVWreg x:(MOVBload _ _)) -> (MOVDreg x) 624 (MOVWreg x:(MOVBZload _ _)) -> (MOVDreg x) 625 (MOVWreg x:(MOVHload _ _)) -> (MOVDreg x) 626 (MOVWreg x:(MOVHZload _ _)) -> (MOVDreg x) 627 (MOVWreg x:(MOVWload _ _)) -> (MOVDreg x) 628 (MOVWZreg x:(MOVBZload _ _)) -> (MOVDreg x) 629 (MOVWZreg x:(MOVHZload _ _)) -> (MOVDreg x) 630 (MOVWZreg x:(MOVWZload _ _)) -> (MOVDreg x) 631 632 // don't extend if argument is already extended 633 (MOVBreg x:(Arg <t>)) && is8BitInt(t) && isSigned(t) -> (MOVDreg x) 634 (MOVBZreg x:(Arg <t>)) && is8BitInt(t) && !isSigned(t) -> (MOVDreg x) 635 (MOVHreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && isSigned(t) -> (MOVDreg x) 636 (MOVHZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && !isSigned(t) -> (MOVDreg x) 637 (MOVWreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && isSigned(t) -> (MOVDreg x) 638 (MOVWZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !isSigned(t) -> (MOVDreg x) 639 640 // fold double extensions 641 (MOVBreg x:(MOVBreg _)) -> (MOVDreg x) 642 (MOVBZreg x:(MOVBZreg _)) -> (MOVDreg x) 643 (MOVHreg x:(MOVBreg _)) -> (MOVDreg x) 644 (MOVHreg x:(MOVBZreg _)) -> (MOVDreg x) 645 (MOVHreg x:(MOVHreg _)) -> (MOVDreg x) 646 (MOVHZreg x:(MOVBZreg _)) -> (MOVDreg x) 647 (MOVHZreg x:(MOVHZreg _)) -> (MOVDreg x) 648 (MOVWreg x:(MOVBreg _)) -> (MOVDreg x) 649 (MOVWreg x:(MOVBZreg _)) -> (MOVDreg x) 650 (MOVWreg x:(MOVHreg _)) -> (MOVDreg x) 651 (MOVWreg x:(MOVHreg _)) -> (MOVDreg x) 652 (MOVWreg x:(MOVWreg _)) -> (MOVDreg x) 653 (MOVWZreg x:(MOVBZreg _)) -> (MOVDreg x) 654 (MOVWZreg x:(MOVHZreg _)) -> (MOVDreg x) 655 (MOVWZreg x:(MOVWZreg _)) -> (MOVDreg x) 656 657 // fold extensions into constants 658 (MOVBreg (MOVDconst [c])) -> (MOVDconst [int64(int8(c))]) 659 (MOVBZreg (MOVDconst [c])) -> (MOVDconst [int64(uint8(c))]) 660 (MOVHreg (MOVDconst [c])) -> (MOVDconst [int64(int16(c))]) 661 (MOVHZreg (MOVDconst [c])) -> (MOVDconst [int64(uint16(c))]) 662 (MOVWreg (MOVDconst [c])) -> (MOVDconst [int64(int32(c))]) 663 (MOVWZreg (MOVDconst [c])) -> (MOVDconst [int64(uint32(c))]) 664 665 // sign extended loads 666 // Note: The combined instruction must end up in the same block 667 // as the original load. If not, we end up making a value with 668 // memory type live in two different blocks, which can lead to 669 // multiple memory values alive simultaneously. 670 // Make sure we don't combine these ops if the load has another use. 671 // This prevents a single load from being split into multiple loads 672 // which then might return different values. See test/atomicload.go. 673 (MOVBreg x:(MOVBZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <v.Type> [off] {sym} ptr mem) 674 (MOVBZreg x:(MOVBZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZload <v.Type> [off] {sym} ptr mem) 675 (MOVHreg x:(MOVHZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHload <v.Type> [off] {sym} ptr mem) 676 (MOVHZreg x:(MOVHZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZload <v.Type> [off] {sym} ptr mem) 677 (MOVWreg x:(MOVWZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <v.Type> [off] {sym} ptr mem) 678 (MOVWZreg x:(MOVWZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZload <v.Type> [off] {sym} ptr mem) 679 680 (MOVBZreg x:(MOVBZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZloadidx <v.Type> [off] {sym} ptr idx mem) 681 (MOVHZreg x:(MOVHZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZloadidx <v.Type> [off] {sym} ptr idx mem) 682 (MOVWZreg x:(MOVWZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZloadidx <v.Type> [off] {sym} ptr idx mem) 683 684 // replace load from same location as preceding store with copy 685 (MOVBZload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVBZreg x) 686 (MOVHZload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVHZreg x) 687 (MOVWZload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVWZreg x) 688 (MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVDreg x) 689 690 // Don't extend before storing 691 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 692 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 693 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 694 (MOVWstore [off] {sym} ptr (MOVWZreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 695 (MOVHstore [off] {sym} ptr (MOVHZreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 696 (MOVBstore [off] {sym} ptr (MOVBZreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 697 698 // Fold constants into memory operations. 699 // Note that this is not always a good idea because if not all the uses of 700 // the ADDconst get eliminated, we still have to compute the ADDconst and we now 701 // have potentially two live values (ptr and (ADDconst [off] ptr)) instead of one. 702 // Nevertheless, let's do it! 703 (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem) 704 (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem) 705 (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVHload [off1+off2] {sym} ptr mem) 706 (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem) 707 (MOVWZload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVWZload [off1+off2] {sym} ptr mem) 708 (MOVHZload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVHZload [off1+off2] {sym} ptr mem) 709 (MOVBZload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVBZload [off1+off2] {sym} ptr mem) 710 (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (FMOVSload [off1+off2] {sym} ptr mem) 711 (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (FMOVDload [off1+off2] {sym} ptr mem) 712 713 (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} ptr val mem) 714 (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem) 715 (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} ptr val mem) 716 (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem) 717 (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (FMOVSstore [off1+off2] {sym} ptr val mem) 718 (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (FMOVDstore [off1+off2] {sym} ptr val mem) 719 720 // Fold constants into stores. 721 (MOVDstore [off] {sym} ptr (MOVDconst [c]) mem) && validValAndOff(c,off) && int64(int16(c)) == c && ptr.Op != OpSB -> 722 (MOVDstoreconst [makeValAndOff(c,off)] {sym} ptr mem) 723 (MOVWstore [off] {sym} ptr (MOVDconst [c]) mem) && validOff(off) && int64(int16(c)) == c && ptr.Op != OpSB -> 724 (MOVWstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) 725 (MOVHstore [off] {sym} ptr (MOVDconst [c]) mem) && validOff(off) && ptr.Op != OpSB -> 726 (MOVHstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) 727 (MOVBstore [off] {sym} ptr (MOVDconst [c]) mem) && validOff(off) && ptr.Op != OpSB -> 728 (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) 729 730 // Fold address offsets into constant stores. 731 (MOVDstoreconst [sc] {s} (ADDconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 732 (MOVDstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 733 (MOVWstoreconst [sc] {s} (ADDconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 734 (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 735 (MOVHstoreconst [sc] {s} (ADDconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 736 (MOVHstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 737 (MOVBstoreconst [sc] {s} (ADDconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 738 (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 739 740 // We need to fold MOVDaddr into the MOVx ops so that the live variable analysis knows 741 // what variables are being read/written by the ops. 742 (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 743 (MOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem) 744 (MOVWZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 745 (MOVWZload [off1+off2] {mergeSym(sym1,sym2)} base mem) 746 (MOVHZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 747 (MOVHZload [off1+off2] {mergeSym(sym1,sym2)} base mem) 748 (MOVBZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 749 (MOVBZload [off1+off2] {mergeSym(sym1,sym2)} base mem) 750 (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 751 (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} base mem) 752 (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 753 (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem) 754 755 (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 756 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) 757 (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 758 (MOVHload [off1+off2] {mergeSym(sym1,sym2)} base mem) 759 (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 760 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) 761 762 (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 763 (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 764 (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 765 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 766 (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 767 (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 768 (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 769 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 770 (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 771 (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 772 (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 773 (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 774 775 (MOVDstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 776 (MOVDstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 777 (MOVWstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 778 (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 779 (MOVHstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 780 (MOVHstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 781 (MOVBstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 782 (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 783 784 // generating indexed loads and stores 785 (MOVBZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 786 (MOVBZloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 787 (MOVHZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 788 (MOVHZloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 789 (MOVWZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 790 (MOVWZloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 791 (MOVDload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 792 (MOVDloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 793 (FMOVSload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 794 (FMOVSloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 795 (FMOVDload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 796 (FMOVDloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 797 798 (MOVBstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 799 (MOVBstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 800 (MOVHstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 801 (MOVHstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 802 (MOVWstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 803 (MOVWstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 804 (MOVDstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 805 (MOVDstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 806 (FMOVSstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 807 (FMOVSstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 808 (FMOVDstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 809 (FMOVDstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 810 811 (MOVBZload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVBZloadidx [off] {sym} ptr idx mem) 812 (MOVHZload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVHZloadidx [off] {sym} ptr idx mem) 813 (MOVWZload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVWZloadidx [off] {sym} ptr idx mem) 814 (MOVDload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVDloadidx [off] {sym} ptr idx mem) 815 (FMOVSload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (FMOVSloadidx [off] {sym} ptr idx mem) 816 (FMOVDload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (FMOVDloadidx [off] {sym} ptr idx mem) 817 (MOVBstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVBstoreidx [off] {sym} ptr idx val mem) 818 (MOVHstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVHstoreidx [off] {sym} ptr idx val mem) 819 (MOVWstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVWstoreidx [off] {sym} ptr idx val mem) 820 (MOVDstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVDstoreidx [off] {sym} ptr idx val mem) 821 (FMOVSstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (FMOVSstoreidx [off] {sym} ptr idx val mem) 822 (FMOVDstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (FMOVDstoreidx [off] {sym} ptr idx val mem) 823 824 // combine ADD into indexed loads and stores 825 (MOVBZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVBZloadidx [c+d] {sym} ptr idx mem) 826 (MOVHZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVHZloadidx [c+d] {sym} ptr idx mem) 827 (MOVWZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVWZloadidx [c+d] {sym} ptr idx mem) 828 (MOVDloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVDloadidx [c+d] {sym} ptr idx mem) 829 (FMOVSloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (FMOVSloadidx [c+d] {sym} ptr idx mem) 830 (FMOVDloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (FMOVDloadidx [c+d] {sym} ptr idx mem) 831 832 (MOVBstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVBstoreidx [c+d] {sym} ptr idx val mem) 833 (MOVHstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVHstoreidx [c+d] {sym} ptr idx val mem) 834 (MOVWstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVWstoreidx [c+d] {sym} ptr idx val mem) 835 (MOVDstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVDstoreidx [c+d] {sym} ptr idx val mem) 836 (FMOVSstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (FMOVSstoreidx [c+d] {sym} ptr idx val mem) 837 (FMOVDstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (FMOVDstoreidx [c+d] {sym} ptr idx val mem) 838 839 (MOVBZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVBZloadidx [c+d] {sym} ptr idx mem) 840 (MOVHZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVHZloadidx [c+d] {sym} ptr idx mem) 841 (MOVWZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVWZloadidx [c+d] {sym} ptr idx mem) 842 (MOVDloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVDloadidx [c+d] {sym} ptr idx mem) 843 (FMOVSloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (FMOVSloadidx [c+d] {sym} ptr idx mem) 844 (FMOVDloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (FMOVDloadidx [c+d] {sym} ptr idx mem) 845 846 (MOVBstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVBstoreidx [c+d] {sym} ptr idx val mem) 847 (MOVHstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVHstoreidx [c+d] {sym} ptr idx val mem) 848 (MOVWstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVWstoreidx [c+d] {sym} ptr idx val mem) 849 (MOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVDstoreidx [c+d] {sym} ptr idx val mem) 850 (FMOVSstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (FMOVSstoreidx [c+d] {sym} ptr idx val mem) 851 (FMOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (FMOVDstoreidx [c+d] {sym} ptr idx val mem) 852 853 // MOVDaddr into MOVDaddridx 854 (MOVDaddridx [off1] {sym1} (MOVDaddr [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB -> 855 (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y) 856 (MOVDaddridx [off1] {sym1} x (MOVDaddr [off2] {sym2} y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && y.Op != OpSB -> 857 (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y) 858 859 // Absorb InvertFlags into branches. 860 (LT (InvertFlags cmp) yes no) -> (GT cmp yes no) 861 (GT (InvertFlags cmp) yes no) -> (LT cmp yes no) 862 (LE (InvertFlags cmp) yes no) -> (GE cmp yes no) 863 (GE (InvertFlags cmp) yes no) -> (LE cmp yes no) 864 (EQ (InvertFlags cmp) yes no) -> (EQ cmp yes no) 865 (NE (InvertFlags cmp) yes no) -> (NE cmp yes no) 866 867 // Constant comparisons. 868 (CMPconst (MOVDconst [x]) [y]) && x==y -> (FlagEQ) 869 (CMPconst (MOVDconst [x]) [y]) && x<y -> (FlagLT) 870 (CMPconst (MOVDconst [x]) [y]) && x>y -> (FlagGT) 871 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)==uint64(y) -> (FlagEQ) 872 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)<uint64(y) -> (FlagLT) 873 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)>uint64(y) -> (FlagGT) 874 875 (CMPWconst (MOVDconst [x]) [y]) && int32(x)==int32(y) -> (FlagEQ) 876 (CMPWconst (MOVDconst [x]) [y]) && int32(x)<int32(y) -> (FlagLT) 877 (CMPWconst (MOVDconst [x]) [y]) && int32(x)>int32(y) -> (FlagGT) 878 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)==uint32(y) -> (FlagEQ) 879 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)<uint32(y) -> (FlagLT) 880 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)>uint32(y) -> (FlagGT) 881 882 // Other known comparisons. 883 (CMPconst (MOVBZreg _) [c]) && 0xFF < c -> (FlagLT) 884 (CMPconst (MOVHZreg _) [c]) && 0xFFFF < c -> (FlagLT) 885 (CMPconst (MOVWZreg _) [c]) && 0xFFFFFFFF < c -> (FlagLT) 886 (CMPWconst (SRWconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n) -> (FlagLT) 887 (CMPconst (SRDconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n) -> (FlagLT) 888 (CMPconst (ANDconst _ [m]) [n]) && 0 <= m && m < n -> (FlagLT) 889 (CMPWconst (ANDWconst _ [m]) [n]) && 0 <= int32(m) && int32(m) < int32(n) -> (FlagLT) 890 891 // Absorb flag constants into SBB ops. 892 (SUBEcarrymask (FlagEQ)) -> (MOVDconst [-1]) 893 (SUBEcarrymask (FlagLT)) -> (MOVDconst [-1]) 894 (SUBEcarrymask (FlagGT)) -> (MOVDconst [0]) 895 (SUBEWcarrymask (FlagEQ)) -> (MOVDconst [-1]) 896 (SUBEWcarrymask (FlagLT)) -> (MOVDconst [-1]) 897 (SUBEWcarrymask (FlagGT)) -> (MOVDconst [0]) 898 899 // Absorb flag constants into branches. 900 (EQ (FlagEQ) yes no) -> (First nil yes no) 901 (EQ (FlagLT) yes no) -> (First nil no yes) 902 (EQ (FlagGT) yes no) -> (First nil no yes) 903 904 (NE (FlagEQ) yes no) -> (First nil no yes) 905 (NE (FlagLT) yes no) -> (First nil yes no) 906 (NE (FlagGT) yes no) -> (First nil yes no) 907 908 (LT (FlagEQ) yes no) -> (First nil no yes) 909 (LT (FlagLT) yes no) -> (First nil yes no) 910 (LT (FlagGT) yes no) -> (First nil no yes) 911 912 (LE (FlagEQ) yes no) -> (First nil yes no) 913 (LE (FlagLT) yes no) -> (First nil yes no) 914 (LE (FlagGT) yes no) -> (First nil no yes) 915 916 (GT (FlagEQ) yes no) -> (First nil no yes) 917 (GT (FlagLT) yes no) -> (First nil no yes) 918 (GT (FlagGT) yes no) -> (First nil yes no) 919 920 (GE (FlagEQ) yes no) -> (First nil yes no) 921 (GE (FlagLT) yes no) -> (First nil no yes) 922 (GE (FlagGT) yes no) -> (First nil yes no) 923 924 // Absorb flag constants into SETxx ops. 925 (MOVDEQ _ x (FlagEQ)) -> x 926 (MOVDEQ y _ (FlagLT)) -> y 927 (MOVDEQ y _ (FlagGT)) -> y 928 929 (MOVDNE y _ (FlagEQ)) -> y 930 (MOVDNE _ x (FlagLT)) -> x 931 (MOVDNE _ x (FlagGT)) -> x 932 933 (MOVDLT y _ (FlagEQ)) -> y 934 (MOVDLT _ x (FlagLT)) -> x 935 (MOVDLT y _ (FlagGT)) -> y 936 937 (MOVDLE _ x (FlagEQ)) -> x 938 (MOVDLE _ x (FlagLT)) -> x 939 (MOVDLE y _ (FlagGT)) -> y 940 941 (MOVDGT y _ (FlagEQ)) -> y 942 (MOVDGT y _ (FlagLT)) -> y 943 (MOVDGT _ x (FlagGT)) -> x 944 945 (MOVDGE _ x (FlagEQ)) -> x 946 (MOVDGE y _ (FlagLT)) -> y 947 (MOVDGE _ x (FlagGT)) -> x 948 949 // Remove redundant *const ops 950 (ADDconst [0] x) -> x 951 (ADDWconst [c] x) && int32(c)==0 -> x 952 (SUBconst [0] x) -> x 953 (SUBWconst [c] x) && int32(c) == 0 -> x 954 (ANDconst [0] _) -> (MOVDconst [0]) 955 (ANDWconst [c] _) && int32(c)==0 -> (MOVDconst [0]) 956 (ANDconst [-1] x) -> x 957 (ANDWconst [c] x) && int32(c)==-1 -> x 958 (ORconst [0] x) -> x 959 (ORWconst [c] x) && int32(c)==0 -> x 960 (ORconst [-1] _) -> (MOVDconst [-1]) 961 (ORWconst [c] _) && int32(c)==-1 -> (MOVDconst [-1]) 962 (XORconst [0] x) -> x 963 (XORWconst [c] x) && int32(c)==0 -> x 964 965 // Convert constant subtracts to constant adds. 966 (SUBconst [c] x) && c != -(1<<31) -> (ADDconst [-c] x) 967 (SUBWconst [c] x) -> (ADDWconst [int64(int32(-c))] x) 968 969 // generic constant folding 970 // TODO: more of this 971 (ADDconst [c] (MOVDconst [d])) -> (MOVDconst [c+d]) 972 (ADDWconst [c] (MOVDconst [d])) -> (MOVDconst [int64(int32(c+d))]) 973 (ADDconst [c] (ADDconst [d] x)) && is32Bit(c+d) -> (ADDconst [c+d] x) 974 (ADDWconst [c] (ADDWconst [d] x)) -> (ADDWconst [int64(int32(c+d))] x) 975 (SUBconst (MOVDconst [d]) [c]) -> (MOVDconst [d-c]) 976 (SUBconst (SUBconst x [d]) [c]) && is32Bit(-c-d) -> (ADDconst [-c-d] x) 977 (SRADconst [c] (MOVDconst [d])) -> (MOVDconst [d>>uint64(c)]) 978 (SRAWconst [c] (MOVDconst [d])) -> (MOVDconst [d>>uint64(c)]) 979 (NEG (MOVDconst [c])) -> (MOVDconst [-c]) 980 (NEGW (MOVDconst [c])) -> (MOVDconst [int64(int32(-c))]) 981 (MULLDconst [c] (MOVDconst [d])) -> (MOVDconst [c*d]) 982 (MULLWconst [c] (MOVDconst [d])) -> (MOVDconst [int64(int32(c*d))]) 983 (AND (MOVDconst [c]) (MOVDconst [d])) -> (MOVDconst [c&d]) 984 (ANDconst [c] (MOVDconst [d])) -> (MOVDconst [c&d]) 985 (ANDWconst [c] (MOVDconst [d])) -> (MOVDconst [c&d]) 986 (OR (MOVDconst [c]) (MOVDconst [d])) -> (MOVDconst [c|d]) 987 (ORconst [c] (MOVDconst [d])) -> (MOVDconst [c|d]) 988 (ORWconst [c] (MOVDconst [d])) -> (MOVDconst [c|d]) 989 (XOR (MOVDconst [c]) (MOVDconst [d])) -> (MOVDconst [c^d]) 990 (XORconst [c] (MOVDconst [d])) -> (MOVDconst [c^d]) 991 (XORWconst [c] (MOVDconst [d])) -> (MOVDconst [c^d]) 992 (LoweredRound32F x:(FMOVSconst)) -> x 993 (LoweredRound64F x:(FMOVDconst)) -> x 994 995 // generic simplifications 996 // TODO: more of this 997 (ADD x (NEG y)) -> (SUB x y) 998 (ADDW x (NEGW y)) -> (SUBW x y) 999 (SUB x x) -> (MOVDconst [0]) 1000 (SUBW x x) -> (MOVDconst [0]) 1001 (AND x x) -> x 1002 (ANDW x x) -> x 1003 (OR x x) -> x 1004 (ORW x x) -> x 1005 (XOR x x) -> (MOVDconst [0]) 1006 (XORW x x) -> (MOVDconst [0]) 1007 (NEG (ADDconst [c] (NEG x))) && c != -(1<<31) -> (ADDconst [-c] x) 1008 1009 // fused multiply-add 1010 (FADD (FMUL y z) x) -> (FMADD x y z) 1011 (FADDS (FMULS y z) x) -> (FMADDS x y z) 1012 (FSUB (FMUL y z) x) -> (FMSUB x y z) 1013 (FSUBS (FMULS y z) x) -> (FMSUBS x y z) 1014 1015 // Fold memory operations into operations. 1016 // Exclude global data (SB) because these instructions cannot handle relative addresses. 1017 // TODO(mundaym): use LARL in the assembler to handle SB? 1018 // TODO(mundaym): indexed versions of these? 1019 (ADD <t> x g:(MOVDload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1020 -> (ADDload <t> [off] {sym} x ptr mem) 1021 (ADD <t> g:(MOVDload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1022 -> (ADDload <t> [off] {sym} x ptr mem) 1023 (ADDW <t> x g:(MOVWload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1024 -> (ADDWload <t> [off] {sym} x ptr mem) 1025 (ADDW <t> g:(MOVWload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1026 -> (ADDWload <t> [off] {sym} x ptr mem) 1027 (ADDW <t> x g:(MOVWZload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1028 -> (ADDWload <t> [off] {sym} x ptr mem) 1029 (ADDW <t> g:(MOVWZload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1030 -> (ADDWload <t> [off] {sym} x ptr mem) 1031 (MULLD <t> x g:(MOVDload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1032 -> (MULLDload <t> [off] {sym} x ptr mem) 1033 (MULLD <t> g:(MOVDload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1034 -> (MULLDload <t> [off] {sym} x ptr mem) 1035 (MULLW <t> x g:(MOVWload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1036 -> (MULLWload <t> [off] {sym} x ptr mem) 1037 (MULLW <t> g:(MOVWload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1038 -> (MULLWload <t> [off] {sym} x ptr mem) 1039 (MULLW <t> x g:(MOVWZload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1040 -> (MULLWload <t> [off] {sym} x ptr mem) 1041 (MULLW <t> g:(MOVWZload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1042 -> (MULLWload <t> [off] {sym} x ptr mem) 1043 (SUB <t> x g:(MOVDload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1044 -> (SUBload <t> [off] {sym} x ptr mem) 1045 (SUBW <t> x g:(MOVWload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1046 -> (SUBWload <t> [off] {sym} x ptr mem) 1047 (SUBW <t> x g:(MOVWZload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1048 -> (SUBWload <t> [off] {sym} x ptr mem) 1049 (AND <t> x g:(MOVDload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1050 -> (ANDload <t> [off] {sym} x ptr mem) 1051 (AND <t> g:(MOVDload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1052 -> (ANDload <t> [off] {sym} x ptr mem) 1053 (ANDW <t> x g:(MOVWload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1054 -> (ANDWload <t> [off] {sym} x ptr mem) 1055 (ANDW <t> g:(MOVWload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1056 -> (ANDWload <t> [off] {sym} x ptr mem) 1057 (ANDW <t> x g:(MOVWZload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1058 -> (ANDWload <t> [off] {sym} x ptr mem) 1059 (ANDW <t> g:(MOVWZload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1060 -> (ANDWload <t> [off] {sym} x ptr mem) 1061 (OR <t> x g:(MOVDload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1062 -> (ORload <t> [off] {sym} x ptr mem) 1063 (OR <t> g:(MOVDload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1064 -> (ORload <t> [off] {sym} x ptr mem) 1065 (ORW <t> x g:(MOVWload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1066 -> (ORWload <t> [off] {sym} x ptr mem) 1067 (ORW <t> g:(MOVWload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1068 -> (ORWload <t> [off] {sym} x ptr mem) 1069 (ORW <t> x g:(MOVWZload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1070 -> (ORWload <t> [off] {sym} x ptr mem) 1071 (ORW <t> g:(MOVWZload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1072 -> (ORWload <t> [off] {sym} x ptr mem) 1073 (XOR <t> x g:(MOVDload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1074 -> (XORload <t> [off] {sym} x ptr mem) 1075 (XOR <t> g:(MOVDload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1076 -> (XORload <t> [off] {sym} x ptr mem) 1077 (XORW <t> x g:(MOVWload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1078 -> (XORWload <t> [off] {sym} x ptr mem) 1079 (XORW <t> g:(MOVWload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1080 -> (XORWload <t> [off] {sym} x ptr mem) 1081 (XORW <t> x g:(MOVWZload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1082 -> (XORWload <t> [off] {sym} x ptr mem) 1083 (XORW <t> g:(MOVWZload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1084 -> (XORWload <t> [off] {sym} x ptr mem) 1085 1086 // Combine constant stores into larger (unaligned) stores. 1087 // It doesn't work to global data (based on SB), 1088 // because STGRL doesn't support unaligned address 1089 (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem)) 1090 && p.Op != OpSB 1091 && x.Uses == 1 1092 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() 1093 && clobber(x) 1094 -> (MOVHstoreconst [makeValAndOff(ValAndOff(c).Val()&0xff | ValAndOff(a).Val()<<8, ValAndOff(a).Off())] {s} p mem) 1095 (MOVHstoreconst [c] {s} p x:(MOVHstoreconst [a] {s} p mem)) 1096 && p.Op != OpSB 1097 && x.Uses == 1 1098 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() 1099 && clobber(x) 1100 -> (MOVWstoreconst [makeValAndOff(ValAndOff(c).Val()&0xffff | ValAndOff(a).Val()<<16, ValAndOff(a).Off())] {s} p mem) 1101 (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem)) 1102 && p.Op != OpSB 1103 && x.Uses == 1 1104 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() 1105 && clobber(x) 1106 -> (MOVDstore [ValAndOff(a).Off()] {s} p (MOVDconst [ValAndOff(c).Val()&0xffffffff | ValAndOff(a).Val()<<32]) mem) 1107 1108 // Combine stores into larger (unaligned) stores. 1109 // It doesn't work on global data (based on SB) because stores with relative addressing 1110 // require that the memory operand be aligned. 1111 (MOVBstore [i] {s} p w x:(MOVBstore [i-1] {s} p (SRDconst [8] w) mem)) 1112 && p.Op != OpSB 1113 && x.Uses == 1 1114 && clobber(x) 1115 -> (MOVHstore [i-1] {s} p w mem) 1116 (MOVBstore [i] {s} p w0:(SRDconst [j] w) x:(MOVBstore [i-1] {s} p (SRDconst [j+8] w) mem)) 1117 && p.Op != OpSB 1118 && x.Uses == 1 1119 && clobber(x) 1120 -> (MOVHstore [i-1] {s} p w0 mem) 1121 (MOVBstore [i] {s} p w x:(MOVBstore [i-1] {s} p (SRWconst [8] w) mem)) 1122 && p.Op != OpSB 1123 && x.Uses == 1 1124 && clobber(x) 1125 -> (MOVHstore [i-1] {s} p w mem) 1126 (MOVBstore [i] {s} p w0:(SRWconst [j] w) x:(MOVBstore [i-1] {s} p (SRWconst [j+8] w) mem)) 1127 && p.Op != OpSB 1128 && x.Uses == 1 1129 && clobber(x) 1130 -> (MOVHstore [i-1] {s} p w0 mem) 1131 (MOVHstore [i] {s} p w x:(MOVHstore [i-2] {s} p (SRDconst [16] w) mem)) 1132 && p.Op != OpSB 1133 && x.Uses == 1 1134 && clobber(x) 1135 -> (MOVWstore [i-2] {s} p w mem) 1136 (MOVHstore [i] {s} p w0:(SRDconst [j] w) x:(MOVHstore [i-2] {s} p (SRDconst [j+16] w) mem)) 1137 && p.Op != OpSB 1138 && x.Uses == 1 1139 && clobber(x) 1140 -> (MOVWstore [i-2] {s} p w0 mem) 1141 (MOVHstore [i] {s} p w x:(MOVHstore [i-2] {s} p (SRWconst [16] w) mem)) 1142 && p.Op != OpSB 1143 && x.Uses == 1 1144 && clobber(x) 1145 -> (MOVWstore [i-2] {s} p w mem) 1146 (MOVHstore [i] {s} p w0:(SRWconst [j] w) x:(MOVHstore [i-2] {s} p (SRWconst [j+16] w) mem)) 1147 && p.Op != OpSB 1148 && x.Uses == 1 1149 && clobber(x) 1150 -> (MOVWstore [i-2] {s} p w0 mem) 1151 (MOVWstore [i] {s} p (SRDconst [32] w) x:(MOVWstore [i-4] {s} p w mem)) 1152 && p.Op != OpSB 1153 && x.Uses == 1 1154 && clobber(x) 1155 -> (MOVDstore [i-4] {s} p w mem) 1156 (MOVWstore [i] {s} p w0:(SRDconst [j] w) x:(MOVWstore [i-4] {s} p (SRDconst [j+32] w) mem)) 1157 && p.Op != OpSB 1158 && x.Uses == 1 1159 && clobber(x) 1160 -> (MOVDstore [i-4] {s} p w0 mem) 1161 1162 (MOVBstoreidx [i] {s} p idx w x:(MOVBstoreidx [i-1] {s} p idx (SRDconst [8] w) mem)) 1163 && x.Uses == 1 1164 && clobber(x) 1165 -> (MOVHstoreidx [i-1] {s} p idx w mem) 1166 (MOVBstoreidx [i] {s} p idx w0:(SRDconst [j] w) x:(MOVBstoreidx [i-1] {s} p idx (SRDconst [j+8] w) mem)) 1167 && x.Uses == 1 1168 && clobber(x) 1169 -> (MOVHstoreidx [i-1] {s} p idx w0 mem) 1170 (MOVBstoreidx [i] {s} p idx w x:(MOVBstoreidx [i-1] {s} p idx (SRWconst [8] w) mem)) 1171 && x.Uses == 1 1172 && clobber(x) 1173 -> (MOVHstoreidx [i-1] {s} p idx w mem) 1174 (MOVBstoreidx [i] {s} p idx w0:(SRWconst [j] w) x:(MOVBstoreidx [i-1] {s} p idx (SRWconst [j+8] w) mem)) 1175 && x.Uses == 1 1176 && clobber(x) 1177 -> (MOVHstoreidx [i-1] {s} p idx w0 mem) 1178 (MOVHstoreidx [i] {s} p idx w x:(MOVHstoreidx [i-2] {s} p idx (SRDconst [16] w) mem)) 1179 && x.Uses == 1 1180 && clobber(x) 1181 -> (MOVWstoreidx [i-2] {s} p idx w mem) 1182 (MOVHstoreidx [i] {s} p idx w0:(SRDconst [j] w) x:(MOVHstoreidx [i-2] {s} p idx (SRDconst [j+16] w) mem)) 1183 && x.Uses == 1 1184 && clobber(x) 1185 -> (MOVWstoreidx [i-2] {s} p idx w0 mem) 1186 (MOVHstoreidx [i] {s} p idx w x:(MOVHstoreidx [i-2] {s} p idx (SRWconst [16] w) mem)) 1187 && x.Uses == 1 1188 && clobber(x) 1189 -> (MOVWstoreidx [i-2] {s} p idx w mem) 1190 (MOVHstoreidx [i] {s} p idx w0:(SRWconst [j] w) x:(MOVHstoreidx [i-2] {s} p idx (SRWconst [j+16] w) mem)) 1191 && x.Uses == 1 1192 && clobber(x) 1193 -> (MOVWstoreidx [i-2] {s} p idx w0 mem) 1194 (MOVWstoreidx [i] {s} p idx w x:(MOVWstoreidx [i-4] {s} p idx (SRDconst [32] w) mem)) 1195 && x.Uses == 1 1196 && clobber(x) 1197 -> (MOVDstoreidx [i-4] {s} p idx w mem) 1198 (MOVWstoreidx [i] {s} p idx w0:(SRDconst [j] w) x:(MOVWstoreidx [i-4] {s} p idx (SRDconst [j+32] w) mem)) 1199 && x.Uses == 1 1200 && clobber(x) 1201 -> (MOVDstoreidx [i-4] {s} p idx w0 mem) 1202 1203 // Combine stores into larger (unaligned) stores with the bytes reversed (little endian). 1204 // Store-with-bytes-reversed instructions do not support relative memory addresses, 1205 // so these stores can't operate on global data (SB). 1206 (MOVBstore [i] {s} p (SRDconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) 1207 && p.Op != OpSB 1208 && x.Uses == 1 1209 && clobber(x) 1210 -> (MOVHBRstore [i-1] {s} p w mem) 1211 (MOVBstore [i] {s} p (SRDconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SRDconst [j-8] w) mem)) 1212 && p.Op != OpSB 1213 && x.Uses == 1 1214 && clobber(x) 1215 -> (MOVHBRstore [i-1] {s} p w0 mem) 1216 (MOVBstore [i] {s} p (SRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) 1217 && p.Op != OpSB 1218 && x.Uses == 1 1219 && clobber(x) 1220 -> (MOVHBRstore [i-1] {s} p w mem) 1221 (MOVBstore [i] {s} p (SRWconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SRWconst [j-8] w) mem)) 1222 && p.Op != OpSB 1223 && x.Uses == 1 1224 && clobber(x) 1225 -> (MOVHBRstore [i-1] {s} p w0 mem) 1226 (MOVHBRstore [i] {s} p (SRDconst [16] w) x:(MOVHBRstore [i-2] {s} p w mem)) 1227 && x.Uses == 1 1228 && clobber(x) 1229 -> (MOVWBRstore [i-2] {s} p w mem) 1230 (MOVHBRstore [i] {s} p (SRDconst [j] w) x:(MOVHBRstore [i-2] {s} p w0:(SRDconst [j-16] w) mem)) 1231 && x.Uses == 1 1232 && clobber(x) 1233 -> (MOVWBRstore [i-2] {s} p w0 mem) 1234 (MOVHBRstore [i] {s} p (SRWconst [16] w) x:(MOVHBRstore [i-2] {s} p w mem)) 1235 && x.Uses == 1 1236 && clobber(x) 1237 -> (MOVWBRstore [i-2] {s} p w mem) 1238 (MOVHBRstore [i] {s} p (SRWconst [j] w) x:(MOVHBRstore [i-2] {s} p w0:(SRWconst [j-16] w) mem)) 1239 && x.Uses == 1 1240 && clobber(x) 1241 -> (MOVWBRstore [i-2] {s} p w0 mem) 1242 (MOVWBRstore [i] {s} p (SRDconst [32] w) x:(MOVWBRstore [i-4] {s} p w mem)) 1243 && x.Uses == 1 1244 && clobber(x) 1245 -> (MOVDBRstore [i-4] {s} p w mem) 1246 (MOVWBRstore [i] {s} p (SRDconst [j] w) x:(MOVWBRstore [i-4] {s} p w0:(SRDconst [j-32] w) mem)) 1247 && x.Uses == 1 1248 && clobber(x) 1249 -> (MOVDBRstore [i-4] {s} p w0 mem) 1250 1251 (MOVBstoreidx [i] {s} p idx (SRDconst [8] w) x:(MOVBstoreidx [i-1] {s} p idx w mem)) 1252 && x.Uses == 1 1253 && clobber(x) 1254 -> (MOVHBRstoreidx [i-1] {s} p idx w mem) 1255 (MOVBstoreidx [i] {s} p idx (SRDconst [j] w) x:(MOVBstoreidx [i-1] {s} p idx w0:(SRDconst [j-8] w) mem)) 1256 && x.Uses == 1 1257 && clobber(x) 1258 -> (MOVHBRstoreidx [i-1] {s} p idx w0 mem) 1259 (MOVBstoreidx [i] {s} p idx (SRWconst [8] w) x:(MOVBstoreidx [i-1] {s} p idx w mem)) 1260 && x.Uses == 1 1261 && clobber(x) 1262 -> (MOVHBRstoreidx [i-1] {s} p idx w mem) 1263 (MOVBstoreidx [i] {s} p idx (SRWconst [j] w) x:(MOVBstoreidx [i-1] {s} p idx w0:(SRWconst [j-8] w) mem)) 1264 && x.Uses == 1 1265 && clobber(x) 1266 -> (MOVHBRstoreidx [i-1] {s} p idx w0 mem) 1267 (MOVHBRstoreidx [i] {s} p idx (SRDconst [16] w) x:(MOVHBRstoreidx [i-2] {s} p idx w mem)) 1268 && x.Uses == 1 1269 && clobber(x) 1270 -> (MOVWBRstoreidx [i-2] {s} p idx w mem) 1271 (MOVHBRstoreidx [i] {s} p idx (SRDconst [j] w) x:(MOVHBRstoreidx [i-2] {s} p idx w0:(SRDconst [j-16] w) mem)) 1272 && x.Uses == 1 1273 && clobber(x) 1274 -> (MOVWBRstoreidx [i-2] {s} p idx w0 mem) 1275 (MOVHBRstoreidx [i] {s} p idx (SRWconst [16] w) x:(MOVHBRstoreidx [i-2] {s} p idx w mem)) 1276 && x.Uses == 1 1277 && clobber(x) 1278 -> (MOVWBRstoreidx [i-2] {s} p idx w mem) 1279 (MOVHBRstoreidx [i] {s} p idx (SRWconst [j] w) x:(MOVHBRstoreidx [i-2] {s} p idx w0:(SRWconst [j-16] w) mem)) 1280 && x.Uses == 1 1281 && clobber(x) 1282 -> (MOVWBRstoreidx [i-2] {s} p idx w0 mem) 1283 (MOVWBRstoreidx [i] {s} p idx (SRDconst [32] w) x:(MOVWBRstoreidx [i-4] {s} p idx w mem)) 1284 && x.Uses == 1 1285 && clobber(x) 1286 -> (MOVDBRstoreidx [i-4] {s} p idx w mem) 1287 (MOVWBRstoreidx [i] {s} p idx (SRDconst [j] w) x:(MOVWBRstoreidx [i-4] {s} p idx w0:(SRDconst [j-32] w) mem)) 1288 && x.Uses == 1 1289 && clobber(x) 1290 -> (MOVDBRstoreidx [i-4] {s} p idx w0 mem) 1291 1292 // Combining byte loads into larger (unaligned) loads. 1293 1294 // Big-endian loads 1295 1296 (ORW x1:(MOVBZload [i1] {s} p mem) 1297 sh:(SLWconst [8] x0:(MOVBZload [i0] {s} p mem))) 1298 && i1 == i0+1 1299 && p.Op != OpSB 1300 && x0.Uses == 1 1301 && x1.Uses == 1 1302 && sh.Uses == 1 1303 && mergePoint(b,x0,x1) != nil 1304 && clobber(x0) 1305 && clobber(x1) 1306 && clobber(sh) 1307 -> @mergePoint(b,x0,x1) (MOVHZload [i0] {s} p mem) 1308 1309 (OR x1:(MOVBZload [i1] {s} p mem) 1310 sh:(SLDconst [8] x0:(MOVBZload [i0] {s} p mem))) 1311 && i1 == i0+1 1312 && p.Op != OpSB 1313 && x0.Uses == 1 1314 && x1.Uses == 1 1315 && sh.Uses == 1 1316 && mergePoint(b,x0,x1) != nil 1317 && clobber(x0) 1318 && clobber(x1) 1319 && clobber(sh) 1320 -> @mergePoint(b,x0,x1) (MOVHZload [i0] {s} p mem) 1321 1322 (ORW x1:(MOVHZload [i1] {s} p mem) 1323 sh:(SLWconst [16] x0:(MOVHZload [i0] {s} p mem))) 1324 && i1 == i0+2 1325 && p.Op != OpSB 1326 && x0.Uses == 1 1327 && x1.Uses == 1 1328 && sh.Uses == 1 1329 && mergePoint(b,x0,x1) != nil 1330 && clobber(x0) 1331 && clobber(x1) 1332 && clobber(sh) 1333 -> @mergePoint(b,x0,x1) (MOVWZload [i0] {s} p mem) 1334 1335 (OR x1:(MOVHZload [i1] {s} p mem) 1336 sh:(SLDconst [16] x0:(MOVHZload [i0] {s} p mem))) 1337 && i1 == i0+2 1338 && p.Op != OpSB 1339 && x0.Uses == 1 1340 && x1.Uses == 1 1341 && sh.Uses == 1 1342 && mergePoint(b,x0,x1) != nil 1343 && clobber(x0) 1344 && clobber(x1) 1345 && clobber(sh) 1346 -> @mergePoint(b,x0,x1) (MOVWZload [i0] {s} p mem) 1347 1348 (OR x1:(MOVWZload [i1] {s} p mem) 1349 sh:(SLDconst [32] x0:(MOVWZload [i0] {s} p mem))) 1350 && i1 == i0+4 1351 && p.Op != OpSB 1352 && x0.Uses == 1 1353 && x1.Uses == 1 1354 && sh.Uses == 1 1355 && mergePoint(b,x0,x1) != nil 1356 && clobber(x0) 1357 && clobber(x1) 1358 && clobber(sh) 1359 -> @mergePoint(b,x0,x1) (MOVDload [i0] {s} p mem) 1360 1361 (ORW 1362 s0:(SLWconst [j0] x0:(MOVBZload [i0] {s} p mem)) 1363 or:(ORW 1364 s1:(SLWconst [j1] x1:(MOVBZload [i1] {s} p mem)) 1365 y)) 1366 && i1 == i0+1 1367 && j1 == j0-8 1368 && j1 % 16 == 0 1369 && x0.Uses == 1 1370 && x1.Uses == 1 1371 && s0.Uses == 1 1372 && s1.Uses == 1 1373 && or.Uses == 1 1374 && mergePoint(b,x0,x1) != nil 1375 && clobber(x0) 1376 && clobber(x1) 1377 && clobber(s0) 1378 && clobber(s1) 1379 && clobber(or) 1380 -> @mergePoint(b,x0,x1) (ORW <v.Type> (SLWconst <v.Type> [j1] (MOVHZload [i0] {s} p mem)) y) 1381 1382 (OR 1383 s0:(SLDconst [j0] x0:(MOVBZload [i0] {s} p mem)) 1384 or:(OR 1385 s1:(SLDconst [j1] x1:(MOVBZload [i1] {s} p mem)) 1386 y)) 1387 && i1 == i0+1 1388 && j1 == j0-8 1389 && j1 % 16 == 0 1390 && x0.Uses == 1 1391 && x1.Uses == 1 1392 && s0.Uses == 1 1393 && s1.Uses == 1 1394 && or.Uses == 1 1395 && mergePoint(b,x0,x1) != nil 1396 && clobber(x0) 1397 && clobber(x1) 1398 && clobber(s0) 1399 && clobber(s1) 1400 && clobber(or) 1401 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j1] (MOVHZload [i0] {s} p mem)) y) 1402 1403 (OR 1404 s0:(SLDconst [j0] x0:(MOVHZload [i0] {s} p mem)) 1405 or:(OR 1406 s1:(SLDconst [j1] x1:(MOVHZload [i1] {s} p mem)) 1407 y)) 1408 && i1 == i0+2 1409 && j1 == j0-16 1410 && j1 % 32 == 0 1411 && x0.Uses == 1 1412 && x1.Uses == 1 1413 && s0.Uses == 1 1414 && s1.Uses == 1 1415 && or.Uses == 1 1416 && mergePoint(b,x0,x1) != nil 1417 && clobber(x0) 1418 && clobber(x1) 1419 && clobber(s0) 1420 && clobber(s1) 1421 && clobber(or) 1422 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j1] (MOVWZload [i0] {s} p mem)) y) 1423 1424 // Big-endian indexed loads 1425 1426 (ORW x1:(MOVBZloadidx [i1] {s} p idx mem) 1427 sh:(SLWconst [8] x0:(MOVBZloadidx [i0] {s} p idx mem))) 1428 && i1 == i0+1 1429 && p.Op != OpSB 1430 && x0.Uses == 1 1431 && x1.Uses == 1 1432 && sh.Uses == 1 1433 && mergePoint(b,x0,x1) != nil 1434 && clobber(x0) 1435 && clobber(x1) 1436 && clobber(sh) 1437 -> @mergePoint(b,x0,x1) (MOVHZloadidx [i0] {s} p idx mem) 1438 1439 (OR x1:(MOVBZloadidx [i1] {s} p idx mem) 1440 sh:(SLDconst [8] x0:(MOVBZloadidx [i0] {s} p idx mem))) 1441 && i1 == i0+1 1442 && p.Op != OpSB 1443 && x0.Uses == 1 1444 && x1.Uses == 1 1445 && sh.Uses == 1 1446 && mergePoint(b,x0,x1) != nil 1447 && clobber(x0) 1448 && clobber(x1) 1449 && clobber(sh) 1450 -> @mergePoint(b,x0,x1) (MOVHZloadidx [i0] {s} p idx mem) 1451 1452 (ORW x1:(MOVHZloadidx [i1] {s} p idx mem) 1453 sh:(SLWconst [16] x0:(MOVHZloadidx [i0] {s} p idx mem))) 1454 && i1 == i0+2 1455 && p.Op != OpSB 1456 && x0.Uses == 1 1457 && x1.Uses == 1 1458 && sh.Uses == 1 1459 && mergePoint(b,x0,x1) != nil 1460 && clobber(x0) 1461 && clobber(x1) 1462 && clobber(sh) 1463 -> @mergePoint(b,x0,x1) (MOVWZloadidx [i0] {s} p idx mem) 1464 1465 (OR x1:(MOVHZloadidx [i1] {s} p idx mem) 1466 sh:(SLDconst [16] x0:(MOVHZloadidx [i0] {s} p idx mem))) 1467 && i1 == i0+2 1468 && p.Op != OpSB 1469 && x0.Uses == 1 1470 && x1.Uses == 1 1471 && sh.Uses == 1 1472 && mergePoint(b,x0,x1) != nil 1473 && clobber(x0) 1474 && clobber(x1) 1475 && clobber(sh) 1476 -> @mergePoint(b,x0,x1) (MOVWZloadidx [i0] {s} p idx mem) 1477 1478 (OR x1:(MOVWZloadidx [i1] {s} p idx mem) 1479 sh:(SLDconst [32] x0:(MOVWZloadidx [i0] {s} p idx mem))) 1480 && i1 == i0+4 1481 && p.Op != OpSB 1482 && x0.Uses == 1 1483 && x1.Uses == 1 1484 && sh.Uses == 1 1485 && mergePoint(b,x0,x1) != nil 1486 && clobber(x0) 1487 && clobber(x1) 1488 && clobber(sh) 1489 -> @mergePoint(b,x0,x1) (MOVDloadidx [i0] {s} p idx mem) 1490 1491 (ORW 1492 s0:(SLWconst [j0] x0:(MOVBZloadidx [i0] {s} p idx mem)) 1493 or:(ORW 1494 s1:(SLWconst [j1] x1:(MOVBZloadidx [i1] {s} p idx mem)) 1495 y)) 1496 && i1 == i0+1 1497 && j1 == j0-8 1498 && j1 % 16 == 0 1499 && x0.Uses == 1 1500 && x1.Uses == 1 1501 && s0.Uses == 1 1502 && s1.Uses == 1 1503 && or.Uses == 1 1504 && mergePoint(b,x0,x1) != nil 1505 && clobber(x0) 1506 && clobber(x1) 1507 && clobber(s0) 1508 && clobber(s1) 1509 && clobber(or) 1510 -> @mergePoint(b,x0,x1) (ORW <v.Type> (SLWconst <v.Type> [j1] (MOVHZloadidx [i0] {s} p idx mem)) y) 1511 1512 (OR 1513 s0:(SLDconst [j0] x0:(MOVBZloadidx [i0] {s} p idx mem)) 1514 or:(OR 1515 s1:(SLDconst [j1] x1:(MOVBZloadidx [i1] {s} p idx mem)) 1516 y)) 1517 && i1 == i0+1 1518 && j1 == j0-8 1519 && j1 % 16 == 0 1520 && x0.Uses == 1 1521 && x1.Uses == 1 1522 && s0.Uses == 1 1523 && s1.Uses == 1 1524 && or.Uses == 1 1525 && mergePoint(b,x0,x1) != nil 1526 && clobber(x0) 1527 && clobber(x1) 1528 && clobber(s0) 1529 && clobber(s1) 1530 && clobber(or) 1531 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j1] (MOVHZloadidx [i0] {s} p idx mem)) y) 1532 1533 (OR 1534 s0:(SLDconst [j0] x0:(MOVHZloadidx [i0] {s} p idx mem)) 1535 or:(OR 1536 s1:(SLDconst [j1] x1:(MOVHZloadidx [i1] {s} p idx mem)) 1537 y)) 1538 && i1 == i0+2 1539 && j1 == j0-16 1540 && j1 % 32 == 0 1541 && x0.Uses == 1 1542 && x1.Uses == 1 1543 && s0.Uses == 1 1544 && s1.Uses == 1 1545 && or.Uses == 1 1546 && mergePoint(b,x0,x1) != nil 1547 && clobber(x0) 1548 && clobber(x1) 1549 && clobber(s0) 1550 && clobber(s1) 1551 && clobber(or) 1552 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j1] (MOVWZloadidx [i0] {s} p idx mem)) y) 1553 1554 // Little-endian loads 1555 1556 (ORW x0:(MOVBZload [i0] {s} p mem) 1557 sh:(SLWconst [8] x1:(MOVBZload [i1] {s} p mem))) 1558 && p.Op != OpSB 1559 && i1 == i0+1 1560 && x0.Uses == 1 1561 && x1.Uses == 1 1562 && sh.Uses == 1 1563 && mergePoint(b,x0,x1) != nil 1564 && clobber(x0) 1565 && clobber(x1) 1566 && clobber(sh) 1567 -> @mergePoint(b,x0,x1) (MOVHZreg (MOVHBRload [i0] {s} p mem)) 1568 1569 (OR x0:(MOVBZload [i0] {s} p mem) 1570 sh:(SLDconst [8] x1:(MOVBZload [i1] {s} p mem))) 1571 && p.Op != OpSB 1572 && i1 == i0+1 1573 && x0.Uses == 1 1574 && x1.Uses == 1 1575 && sh.Uses == 1 1576 && mergePoint(b,x0,x1) != nil 1577 && clobber(x0) 1578 && clobber(x1) 1579 && clobber(sh) 1580 -> @mergePoint(b,x0,x1) (MOVHZreg (MOVHBRload [i0] {s} p mem)) 1581 1582 (ORW r0:(MOVHZreg x0:(MOVHBRload [i0] {s} p mem)) 1583 sh:(SLWconst [16] r1:(MOVHZreg x1:(MOVHBRload [i1] {s} p mem)))) 1584 && i1 == i0+2 1585 && x0.Uses == 1 1586 && x1.Uses == 1 1587 && r0.Uses == 1 1588 && r1.Uses == 1 1589 && sh.Uses == 1 1590 && mergePoint(b,x0,x1) != nil 1591 && clobber(x0) 1592 && clobber(x1) 1593 && clobber(r0) 1594 && clobber(r1) 1595 && clobber(sh) 1596 -> @mergePoint(b,x0,x1) (MOVWBRload [i0] {s} p mem) 1597 1598 (OR r0:(MOVHZreg x0:(MOVHBRload [i0] {s} p mem)) 1599 sh:(SLDconst [16] r1:(MOVHZreg x1:(MOVHBRload [i1] {s} p mem)))) 1600 && i1 == i0+2 1601 && x0.Uses == 1 1602 && x1.Uses == 1 1603 && r0.Uses == 1 1604 && r1.Uses == 1 1605 && sh.Uses == 1 1606 && mergePoint(b,x0,x1) != nil 1607 && clobber(x0) 1608 && clobber(x1) 1609 && clobber(r0) 1610 && clobber(r1) 1611 && clobber(sh) 1612 -> @mergePoint(b,x0,x1) (MOVWZreg (MOVWBRload [i0] {s} p mem)) 1613 1614 (OR r0:(MOVWZreg x0:(MOVWBRload [i0] {s} p mem)) 1615 sh:(SLDconst [32] r1:(MOVWZreg x1:(MOVWBRload [i1] {s} p mem)))) 1616 && i1 == i0+4 1617 && x0.Uses == 1 1618 && x1.Uses == 1 1619 && r0.Uses == 1 1620 && r1.Uses == 1 1621 && sh.Uses == 1 1622 && mergePoint(b,x0,x1) != nil 1623 && clobber(x0) 1624 && clobber(x1) 1625 && clobber(r0) 1626 && clobber(r1) 1627 && clobber(sh) 1628 -> @mergePoint(b,x0,x1) (MOVDBRload [i0] {s} p mem) 1629 1630 (ORW 1631 s1:(SLWconst [j1] x1:(MOVBZload [i1] {s} p mem)) 1632 or:(ORW 1633 s0:(SLWconst [j0] x0:(MOVBZload [i0] {s} p mem)) 1634 y)) 1635 && p.Op != OpSB 1636 && i1 == i0+1 1637 && j1 == j0+8 1638 && j0 % 16 == 0 1639 && x0.Uses == 1 1640 && x1.Uses == 1 1641 && s0.Uses == 1 1642 && s1.Uses == 1 1643 && or.Uses == 1 1644 && mergePoint(b,x0,x1) != nil 1645 && clobber(x0) 1646 && clobber(x1) 1647 && clobber(s0) 1648 && clobber(s1) 1649 && clobber(or) 1650 -> @mergePoint(b,x0,x1) (ORW <v.Type> (SLWconst <v.Type> [j0] (MOVHZreg (MOVHBRload [i0] {s} p mem))) y) 1651 1652 (OR 1653 s1:(SLDconst [j1] x1:(MOVBZload [i1] {s} p mem)) 1654 or:(OR 1655 s0:(SLDconst [j0] x0:(MOVBZload [i0] {s} p mem)) 1656 y)) 1657 && p.Op != OpSB 1658 && i1 == i0+1 1659 && j1 == j0+8 1660 && j0 % 16 == 0 1661 && x0.Uses == 1 1662 && x1.Uses == 1 1663 && s0.Uses == 1 1664 && s1.Uses == 1 1665 && or.Uses == 1 1666 && mergePoint(b,x0,x1) != nil 1667 && clobber(x0) 1668 && clobber(x1) 1669 && clobber(s0) 1670 && clobber(s1) 1671 && clobber(or) 1672 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j0] (MOVHZreg (MOVHBRload [i0] {s} p mem))) y) 1673 1674 (OR 1675 s1:(SLDconst [j1] r1:(MOVHZreg x1:(MOVHBRload [i1] {s} p mem))) 1676 or:(OR 1677 s0:(SLDconst [j0] r0:(MOVHZreg x0:(MOVHBRload [i0] {s} p mem))) 1678 y)) 1679 && i1 == i0+2 1680 && j1 == j0+16 1681 && j0 % 32 == 0 1682 && x0.Uses == 1 1683 && x1.Uses == 1 1684 && r0.Uses == 1 1685 && r1.Uses == 1 1686 && s0.Uses == 1 1687 && s1.Uses == 1 1688 && or.Uses == 1 1689 && mergePoint(b,x0,x1) != nil 1690 && clobber(x0) 1691 && clobber(x1) 1692 && clobber(r0) 1693 && clobber(r1) 1694 && clobber(s0) 1695 && clobber(s1) 1696 && clobber(or) 1697 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j0] (MOVWZreg (MOVWBRload [i0] {s} p mem))) y) 1698 1699 // Little-endian indexed loads 1700 1701 (ORW x0:(MOVBZloadidx [i0] {s} p idx mem) 1702 sh:(SLWconst [8] x1:(MOVBZloadidx [i1] {s} p idx mem))) 1703 && p.Op != OpSB 1704 && i1 == i0+1 1705 && x0.Uses == 1 1706 && x1.Uses == 1 1707 && sh.Uses == 1 1708 && mergePoint(b,x0,x1) != nil 1709 && clobber(x0) 1710 && clobber(x1) 1711 && clobber(sh) 1712 -> @mergePoint(b,x0,x1) (MOVHZreg (MOVHBRloadidx [i0] {s} p idx mem)) 1713 1714 (OR x0:(MOVBZloadidx [i0] {s} p idx mem) 1715 sh:(SLDconst [8] x1:(MOVBZloadidx [i1] {s} p idx mem))) 1716 && p.Op != OpSB 1717 && i1 == i0+1 1718 && x0.Uses == 1 1719 && x1.Uses == 1 1720 && sh.Uses == 1 1721 && mergePoint(b,x0,x1) != nil 1722 && clobber(x0) 1723 && clobber(x1) 1724 && clobber(sh) 1725 -> @mergePoint(b,x0,x1) (MOVHZreg (MOVHBRloadidx [i0] {s} p idx mem)) 1726 1727 (ORW r0:(MOVHZreg x0:(MOVHBRloadidx [i0] {s} p idx mem)) 1728 sh:(SLWconst [16] r1:(MOVHZreg x1:(MOVHBRloadidx [i1] {s} p idx mem)))) 1729 && i1 == i0+2 1730 && x0.Uses == 1 1731 && x1.Uses == 1 1732 && r0.Uses == 1 1733 && r1.Uses == 1 1734 && sh.Uses == 1 1735 && mergePoint(b,x0,x1) != nil 1736 && clobber(x0) 1737 && clobber(x1) 1738 && clobber(r0) 1739 && clobber(r1) 1740 && clobber(sh) 1741 -> @mergePoint(b,x0,x1) (MOVWBRloadidx [i0] {s} p idx mem) 1742 1743 (OR r0:(MOVHZreg x0:(MOVHBRloadidx [i0] {s} p idx mem)) 1744 sh:(SLDconst [16] r1:(MOVHZreg x1:(MOVHBRloadidx [i1] {s} p idx mem)))) 1745 && i1 == i0+2 1746 && x0.Uses == 1 1747 && x1.Uses == 1 1748 && r0.Uses == 1 1749 && r1.Uses == 1 1750 && sh.Uses == 1 1751 && mergePoint(b,x0,x1) != nil 1752 && clobber(x0) 1753 && clobber(x1) 1754 && clobber(r0) 1755 && clobber(r1) 1756 && clobber(sh) 1757 -> @mergePoint(b,x0,x1) (MOVWZreg (MOVWBRloadidx [i0] {s} p idx mem)) 1758 1759 (OR r0:(MOVWZreg x0:(MOVWBRloadidx [i0] {s} p idx mem)) 1760 sh:(SLDconst [32] r1:(MOVWZreg x1:(MOVWBRloadidx [i1] {s} p idx mem)))) 1761 && i1 == i0+4 1762 && x0.Uses == 1 1763 && x1.Uses == 1 1764 && r0.Uses == 1 1765 && r1.Uses == 1 1766 && sh.Uses == 1 1767 && mergePoint(b,x0,x1) != nil 1768 && clobber(x0) 1769 && clobber(x1) 1770 && clobber(r0) 1771 && clobber(r1) 1772 && clobber(sh) 1773 -> @mergePoint(b,x0,x1) (MOVDBRloadidx [i0] {s} p idx mem) 1774 1775 (ORW 1776 s1:(SLWconst [j1] x1:(MOVBZloadidx [i1] {s} p idx mem)) 1777 or:(ORW 1778 s0:(SLWconst [j0] x0:(MOVBZloadidx [i0] {s} p idx mem)) 1779 y)) 1780 && p.Op != OpSB 1781 && i1 == i0+1 1782 && j1 == j0+8 1783 && j0 % 16 == 0 1784 && x0.Uses == 1 1785 && x1.Uses == 1 1786 && s0.Uses == 1 1787 && s1.Uses == 1 1788 && or.Uses == 1 1789 && mergePoint(b,x0,x1) != nil 1790 && clobber(x0) 1791 && clobber(x1) 1792 && clobber(s0) 1793 && clobber(s1) 1794 && clobber(or) 1795 -> @mergePoint(b,x0,x1) (ORW <v.Type> (SLWconst <v.Type> [j0] (MOVHZreg (MOVHBRloadidx [i0] {s} p idx mem))) y) 1796 1797 (OR 1798 s1:(SLDconst [j1] x1:(MOVBZloadidx [i1] {s} p idx mem)) 1799 or:(OR 1800 s0:(SLDconst [j0] x0:(MOVBZloadidx [i0] {s} p idx mem)) 1801 y)) 1802 && p.Op != OpSB 1803 && i1 == i0+1 1804 && j1 == j0+8 1805 && j0 % 16 == 0 1806 && x0.Uses == 1 1807 && x1.Uses == 1 1808 && s0.Uses == 1 1809 && s1.Uses == 1 1810 && or.Uses == 1 1811 && mergePoint(b,x0,x1) != nil 1812 && clobber(x0) 1813 && clobber(x1) 1814 && clobber(s0) 1815 && clobber(s1) 1816 && clobber(or) 1817 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j0] (MOVHZreg (MOVHBRloadidx [i0] {s} p idx mem))) y) 1818 1819 (OR 1820 s1:(SLDconst [j1] r1:(MOVHZreg x1:(MOVHBRloadidx [i1] {s} p idx mem))) 1821 or:(OR 1822 s0:(SLDconst [j0] r0:(MOVHZreg x0:(MOVHBRloadidx [i0] {s} p idx mem))) 1823 y)) 1824 && i1 == i0+2 1825 && j1 == j0+16 1826 && j0 % 32 == 0 1827 && x0.Uses == 1 1828 && x1.Uses == 1 1829 && r0.Uses == 1 1830 && r1.Uses == 1 1831 && s0.Uses == 1 1832 && s1.Uses == 1 1833 && or.Uses == 1 1834 && mergePoint(b,x0,x1) != nil 1835 && clobber(x0) 1836 && clobber(x1) 1837 && clobber(r0) 1838 && clobber(r1) 1839 && clobber(s0) 1840 && clobber(s1) 1841 && clobber(or) 1842 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j0] (MOVWZreg (MOVWBRloadidx [i0] {s} p idx mem))) y) 1843 1844 // Combine stores into store multiples. 1845 // 32-bit 1846 (MOVWstore [i] {s} p w1 x:(MOVWstore [i-4] {s} p w0 mem)) 1847 && p.Op != OpSB 1848 && x.Uses == 1 1849 && is20Bit(i-4) 1850 && clobber(x) 1851 -> (STM2 [i-4] {s} p w0 w1 mem) 1852 (MOVWstore [i] {s} p w2 x:(STM2 [i-8] {s} p w0 w1 mem)) 1853 && x.Uses == 1 1854 && is20Bit(i-8) 1855 && clobber(x) 1856 -> (STM3 [i-8] {s} p w0 w1 w2 mem) 1857 (MOVWstore [i] {s} p w3 x:(STM3 [i-12] {s} p w0 w1 w2 mem)) 1858 && x.Uses == 1 1859 && is20Bit(i-12) 1860 && clobber(x) 1861 -> (STM4 [i-12] {s} p w0 w1 w2 w3 mem) 1862 (STM2 [i] {s} p w2 w3 x:(STM2 [i-8] {s} p w0 w1 mem)) 1863 && x.Uses == 1 1864 && is20Bit(i-8) 1865 && clobber(x) 1866 -> (STM4 [i-8] {s} p w0 w1 w2 w3 mem) 1867 // 64-bit 1868 (MOVDstore [i] {s} p w1 x:(MOVDstore [i-8] {s} p w0 mem)) 1869 && p.Op != OpSB 1870 && x.Uses == 1 1871 && is20Bit(i-8) 1872 && clobber(x) 1873 -> (STMG2 [i-8] {s} p w0 w1 mem) 1874 (MOVDstore [i] {s} p w2 x:(STMG2 [i-16] {s} p w0 w1 mem)) 1875 && x.Uses == 1 1876 && is20Bit(i-16) 1877 && clobber(x) 1878 -> (STMG3 [i-16] {s} p w0 w1 w2 mem) 1879 (MOVDstore [i] {s} p w3 x:(STMG3 [i-24] {s} p w0 w1 w2 mem)) 1880 && x.Uses == 1 1881 && is20Bit(i-24) 1882 && clobber(x) 1883 -> (STMG4 [i-24] {s} p w0 w1 w2 w3 mem) 1884 (STMG2 [i] {s} p w2 w3 x:(STMG2 [i-16] {s} p w0 w1 mem)) 1885 && x.Uses == 1 1886 && is20Bit(i-16) 1887 && clobber(x) 1888 -> (STMG4 [i-16] {s} p w0 w1 w2 w3 mem) 1889 1890 // Convert 32-bit store multiples into 64-bit stores. 1891 (STM2 [i] {s} p (SRDconst [32] x) x mem) -> (MOVDstore [i] {s} p x mem)