github.com/tidwall/go@v0.0.0-20170415222209-6694a6888b7d/src/cmd/compile/internal/ssa/opGen.go (about) 1 // Code generated from gen/*Ops.go; DO NOT EDIT. 2 3 package ssa 4 5 import ( 6 "cmd/internal/obj" 7 "cmd/internal/obj/arm" 8 "cmd/internal/obj/arm64" 9 "cmd/internal/obj/mips" 10 "cmd/internal/obj/ppc64" 11 "cmd/internal/obj/s390x" 12 "cmd/internal/obj/x86" 13 ) 14 15 const ( 16 BlockInvalid BlockKind = iota 17 18 Block386EQ 19 Block386NE 20 Block386LT 21 Block386LE 22 Block386GT 23 Block386GE 24 Block386ULT 25 Block386ULE 26 Block386UGT 27 Block386UGE 28 Block386EQF 29 Block386NEF 30 Block386ORD 31 Block386NAN 32 33 BlockAMD64EQ 34 BlockAMD64NE 35 BlockAMD64LT 36 BlockAMD64LE 37 BlockAMD64GT 38 BlockAMD64GE 39 BlockAMD64ULT 40 BlockAMD64ULE 41 BlockAMD64UGT 42 BlockAMD64UGE 43 BlockAMD64EQF 44 BlockAMD64NEF 45 BlockAMD64ORD 46 BlockAMD64NAN 47 48 BlockARMEQ 49 BlockARMNE 50 BlockARMLT 51 BlockARMLE 52 BlockARMGT 53 BlockARMGE 54 BlockARMULT 55 BlockARMULE 56 BlockARMUGT 57 BlockARMUGE 58 59 BlockARM64EQ 60 BlockARM64NE 61 BlockARM64LT 62 BlockARM64LE 63 BlockARM64GT 64 BlockARM64GE 65 BlockARM64ULT 66 BlockARM64ULE 67 BlockARM64UGT 68 BlockARM64UGE 69 BlockARM64Z 70 BlockARM64NZ 71 BlockARM64ZW 72 BlockARM64NZW 73 74 BlockMIPSEQ 75 BlockMIPSNE 76 BlockMIPSLTZ 77 BlockMIPSLEZ 78 BlockMIPSGTZ 79 BlockMIPSGEZ 80 BlockMIPSFPT 81 BlockMIPSFPF 82 83 BlockMIPS64EQ 84 BlockMIPS64NE 85 BlockMIPS64LTZ 86 BlockMIPS64LEZ 87 BlockMIPS64GTZ 88 BlockMIPS64GEZ 89 BlockMIPS64FPT 90 BlockMIPS64FPF 91 92 BlockPPC64EQ 93 BlockPPC64NE 94 BlockPPC64LT 95 BlockPPC64LE 96 BlockPPC64GT 97 BlockPPC64GE 98 BlockPPC64FLT 99 BlockPPC64FLE 100 BlockPPC64FGT 101 BlockPPC64FGE 102 103 BlockS390XEQ 104 BlockS390XNE 105 BlockS390XLT 106 BlockS390XLE 107 BlockS390XGT 108 BlockS390XGE 109 BlockS390XGTF 110 BlockS390XGEF 111 112 BlockPlain 113 BlockIf 114 BlockDefer 115 BlockRet 116 BlockRetJmp 117 BlockExit 118 BlockFirst 119 ) 120 121 var blockString = [...]string{ 122 BlockInvalid: "BlockInvalid", 123 124 Block386EQ: "EQ", 125 Block386NE: "NE", 126 Block386LT: "LT", 127 Block386LE: "LE", 128 Block386GT: "GT", 129 Block386GE: "GE", 130 Block386ULT: "ULT", 131 Block386ULE: "ULE", 132 Block386UGT: "UGT", 133 Block386UGE: "UGE", 134 Block386EQF: "EQF", 135 Block386NEF: "NEF", 136 Block386ORD: "ORD", 137 Block386NAN: "NAN", 138 139 BlockAMD64EQ: "EQ", 140 BlockAMD64NE: "NE", 141 BlockAMD64LT: "LT", 142 BlockAMD64LE: "LE", 143 BlockAMD64GT: "GT", 144 BlockAMD64GE: "GE", 145 BlockAMD64ULT: "ULT", 146 BlockAMD64ULE: "ULE", 147 BlockAMD64UGT: "UGT", 148 BlockAMD64UGE: "UGE", 149 BlockAMD64EQF: "EQF", 150 BlockAMD64NEF: "NEF", 151 BlockAMD64ORD: "ORD", 152 BlockAMD64NAN: "NAN", 153 154 BlockARMEQ: "EQ", 155 BlockARMNE: "NE", 156 BlockARMLT: "LT", 157 BlockARMLE: "LE", 158 BlockARMGT: "GT", 159 BlockARMGE: "GE", 160 BlockARMULT: "ULT", 161 BlockARMULE: "ULE", 162 BlockARMUGT: "UGT", 163 BlockARMUGE: "UGE", 164 165 BlockARM64EQ: "EQ", 166 BlockARM64NE: "NE", 167 BlockARM64LT: "LT", 168 BlockARM64LE: "LE", 169 BlockARM64GT: "GT", 170 BlockARM64GE: "GE", 171 BlockARM64ULT: "ULT", 172 BlockARM64ULE: "ULE", 173 BlockARM64UGT: "UGT", 174 BlockARM64UGE: "UGE", 175 BlockARM64Z: "Z", 176 BlockARM64NZ: "NZ", 177 BlockARM64ZW: "ZW", 178 BlockARM64NZW: "NZW", 179 180 BlockMIPSEQ: "EQ", 181 BlockMIPSNE: "NE", 182 BlockMIPSLTZ: "LTZ", 183 BlockMIPSLEZ: "LEZ", 184 BlockMIPSGTZ: "GTZ", 185 BlockMIPSGEZ: "GEZ", 186 BlockMIPSFPT: "FPT", 187 BlockMIPSFPF: "FPF", 188 189 BlockMIPS64EQ: "EQ", 190 BlockMIPS64NE: "NE", 191 BlockMIPS64LTZ: "LTZ", 192 BlockMIPS64LEZ: "LEZ", 193 BlockMIPS64GTZ: "GTZ", 194 BlockMIPS64GEZ: "GEZ", 195 BlockMIPS64FPT: "FPT", 196 BlockMIPS64FPF: "FPF", 197 198 BlockPPC64EQ: "EQ", 199 BlockPPC64NE: "NE", 200 BlockPPC64LT: "LT", 201 BlockPPC64LE: "LE", 202 BlockPPC64GT: "GT", 203 BlockPPC64GE: "GE", 204 BlockPPC64FLT: "FLT", 205 BlockPPC64FLE: "FLE", 206 BlockPPC64FGT: "FGT", 207 BlockPPC64FGE: "FGE", 208 209 BlockS390XEQ: "EQ", 210 BlockS390XNE: "NE", 211 BlockS390XLT: "LT", 212 BlockS390XLE: "LE", 213 BlockS390XGT: "GT", 214 BlockS390XGE: "GE", 215 BlockS390XGTF: "GTF", 216 BlockS390XGEF: "GEF", 217 218 BlockPlain: "Plain", 219 BlockIf: "If", 220 BlockDefer: "Defer", 221 BlockRet: "Ret", 222 BlockRetJmp: "RetJmp", 223 BlockExit: "Exit", 224 BlockFirst: "First", 225 } 226 227 func (k BlockKind) String() string { return blockString[k] } 228 229 const ( 230 OpInvalid Op = iota 231 232 Op386ADDSS 233 Op386ADDSD 234 Op386SUBSS 235 Op386SUBSD 236 Op386MULSS 237 Op386MULSD 238 Op386DIVSS 239 Op386DIVSD 240 Op386MOVSSload 241 Op386MOVSDload 242 Op386MOVSSconst 243 Op386MOVSDconst 244 Op386MOVSSloadidx1 245 Op386MOVSSloadidx4 246 Op386MOVSDloadidx1 247 Op386MOVSDloadidx8 248 Op386MOVSSstore 249 Op386MOVSDstore 250 Op386MOVSSstoreidx1 251 Op386MOVSSstoreidx4 252 Op386MOVSDstoreidx1 253 Op386MOVSDstoreidx8 254 Op386ADDL 255 Op386ADDLconst 256 Op386ADDLcarry 257 Op386ADDLconstcarry 258 Op386ADCL 259 Op386ADCLconst 260 Op386SUBL 261 Op386SUBLconst 262 Op386SUBLcarry 263 Op386SUBLconstcarry 264 Op386SBBL 265 Op386SBBLconst 266 Op386MULL 267 Op386MULLconst 268 Op386HMULL 269 Op386HMULLU 270 Op386MULLQU 271 Op386AVGLU 272 Op386DIVL 273 Op386DIVW 274 Op386DIVLU 275 Op386DIVWU 276 Op386MODL 277 Op386MODW 278 Op386MODLU 279 Op386MODWU 280 Op386ANDL 281 Op386ANDLconst 282 Op386ORL 283 Op386ORLconst 284 Op386XORL 285 Op386XORLconst 286 Op386CMPL 287 Op386CMPW 288 Op386CMPB 289 Op386CMPLconst 290 Op386CMPWconst 291 Op386CMPBconst 292 Op386UCOMISS 293 Op386UCOMISD 294 Op386TESTL 295 Op386TESTW 296 Op386TESTB 297 Op386TESTLconst 298 Op386TESTWconst 299 Op386TESTBconst 300 Op386SHLL 301 Op386SHLLconst 302 Op386SHRL 303 Op386SHRW 304 Op386SHRB 305 Op386SHRLconst 306 Op386SHRWconst 307 Op386SHRBconst 308 Op386SARL 309 Op386SARW 310 Op386SARB 311 Op386SARLconst 312 Op386SARWconst 313 Op386SARBconst 314 Op386ROLLconst 315 Op386ROLWconst 316 Op386ROLBconst 317 Op386NEGL 318 Op386NOTL 319 Op386BSFL 320 Op386BSFW 321 Op386BSRL 322 Op386BSRW 323 Op386BSWAPL 324 Op386SQRTSD 325 Op386SBBLcarrymask 326 Op386SETEQ 327 Op386SETNE 328 Op386SETL 329 Op386SETLE 330 Op386SETG 331 Op386SETGE 332 Op386SETB 333 Op386SETBE 334 Op386SETA 335 Op386SETAE 336 Op386SETEQF 337 Op386SETNEF 338 Op386SETORD 339 Op386SETNAN 340 Op386SETGF 341 Op386SETGEF 342 Op386MOVBLSX 343 Op386MOVBLZX 344 Op386MOVWLSX 345 Op386MOVWLZX 346 Op386MOVLconst 347 Op386CVTTSD2SL 348 Op386CVTTSS2SL 349 Op386CVTSL2SS 350 Op386CVTSL2SD 351 Op386CVTSD2SS 352 Op386CVTSS2SD 353 Op386PXOR 354 Op386LEAL 355 Op386LEAL1 356 Op386LEAL2 357 Op386LEAL4 358 Op386LEAL8 359 Op386MOVBload 360 Op386MOVBLSXload 361 Op386MOVWload 362 Op386MOVWLSXload 363 Op386MOVLload 364 Op386MOVBstore 365 Op386MOVWstore 366 Op386MOVLstore 367 Op386MOVBloadidx1 368 Op386MOVWloadidx1 369 Op386MOVWloadidx2 370 Op386MOVLloadidx1 371 Op386MOVLloadidx4 372 Op386MOVBstoreidx1 373 Op386MOVWstoreidx1 374 Op386MOVWstoreidx2 375 Op386MOVLstoreidx1 376 Op386MOVLstoreidx4 377 Op386MOVBstoreconst 378 Op386MOVWstoreconst 379 Op386MOVLstoreconst 380 Op386MOVBstoreconstidx1 381 Op386MOVWstoreconstidx1 382 Op386MOVWstoreconstidx2 383 Op386MOVLstoreconstidx1 384 Op386MOVLstoreconstidx4 385 Op386DUFFZERO 386 Op386REPSTOSL 387 Op386CALLstatic 388 Op386CALLclosure 389 Op386CALLinter 390 Op386DUFFCOPY 391 Op386REPMOVSL 392 Op386InvertFlags 393 Op386LoweredGetG 394 Op386LoweredGetClosurePtr 395 Op386LoweredNilCheck 396 Op386MOVLconvert 397 Op386FlagEQ 398 Op386FlagLT_ULT 399 Op386FlagLT_UGT 400 Op386FlagGT_UGT 401 Op386FlagGT_ULT 402 Op386FCHS 403 Op386MOVSSconst1 404 Op386MOVSDconst1 405 Op386MOVSSconst2 406 Op386MOVSDconst2 407 408 OpAMD64ADDSS 409 OpAMD64ADDSD 410 OpAMD64SUBSS 411 OpAMD64SUBSD 412 OpAMD64MULSS 413 OpAMD64MULSD 414 OpAMD64DIVSS 415 OpAMD64DIVSD 416 OpAMD64MOVSSload 417 OpAMD64MOVSDload 418 OpAMD64MOVSSconst 419 OpAMD64MOVSDconst 420 OpAMD64MOVSSloadidx1 421 OpAMD64MOVSSloadidx4 422 OpAMD64MOVSDloadidx1 423 OpAMD64MOVSDloadidx8 424 OpAMD64MOVSSstore 425 OpAMD64MOVSDstore 426 OpAMD64MOVSSstoreidx1 427 OpAMD64MOVSSstoreidx4 428 OpAMD64MOVSDstoreidx1 429 OpAMD64MOVSDstoreidx8 430 OpAMD64ADDSDmem 431 OpAMD64ADDSSmem 432 OpAMD64SUBSSmem 433 OpAMD64SUBSDmem 434 OpAMD64MULSSmem 435 OpAMD64MULSDmem 436 OpAMD64ADDQ 437 OpAMD64ADDL 438 OpAMD64ADDQconst 439 OpAMD64ADDLconst 440 OpAMD64SUBQ 441 OpAMD64SUBL 442 OpAMD64SUBQconst 443 OpAMD64SUBLconst 444 OpAMD64MULQ 445 OpAMD64MULL 446 OpAMD64MULQconst 447 OpAMD64MULLconst 448 OpAMD64HMULQ 449 OpAMD64HMULL 450 OpAMD64HMULQU 451 OpAMD64HMULLU 452 OpAMD64AVGQU 453 OpAMD64DIVQ 454 OpAMD64DIVL 455 OpAMD64DIVW 456 OpAMD64DIVQU 457 OpAMD64DIVLU 458 OpAMD64DIVWU 459 OpAMD64MULQU2 460 OpAMD64DIVQU2 461 OpAMD64ANDQ 462 OpAMD64ANDL 463 OpAMD64ANDQconst 464 OpAMD64ANDLconst 465 OpAMD64ORQ 466 OpAMD64ORL 467 OpAMD64ORQconst 468 OpAMD64ORLconst 469 OpAMD64XORQ 470 OpAMD64XORL 471 OpAMD64XORQconst 472 OpAMD64XORLconst 473 OpAMD64CMPQ 474 OpAMD64CMPL 475 OpAMD64CMPW 476 OpAMD64CMPB 477 OpAMD64CMPQconst 478 OpAMD64CMPLconst 479 OpAMD64CMPWconst 480 OpAMD64CMPBconst 481 OpAMD64UCOMISS 482 OpAMD64UCOMISD 483 OpAMD64BTL 484 OpAMD64BTQ 485 OpAMD64BTLconst 486 OpAMD64BTQconst 487 OpAMD64TESTQ 488 OpAMD64TESTL 489 OpAMD64TESTW 490 OpAMD64TESTB 491 OpAMD64TESTQconst 492 OpAMD64TESTLconst 493 OpAMD64TESTWconst 494 OpAMD64TESTBconst 495 OpAMD64SHLQ 496 OpAMD64SHLL 497 OpAMD64SHLQconst 498 OpAMD64SHLLconst 499 OpAMD64SHRQ 500 OpAMD64SHRL 501 OpAMD64SHRW 502 OpAMD64SHRB 503 OpAMD64SHRQconst 504 OpAMD64SHRLconst 505 OpAMD64SHRWconst 506 OpAMD64SHRBconst 507 OpAMD64SARQ 508 OpAMD64SARL 509 OpAMD64SARW 510 OpAMD64SARB 511 OpAMD64SARQconst 512 OpAMD64SARLconst 513 OpAMD64SARWconst 514 OpAMD64SARBconst 515 OpAMD64ROLQconst 516 OpAMD64ROLLconst 517 OpAMD64ROLWconst 518 OpAMD64ROLBconst 519 OpAMD64ADDLmem 520 OpAMD64ADDQmem 521 OpAMD64SUBQmem 522 OpAMD64SUBLmem 523 OpAMD64ANDLmem 524 OpAMD64ANDQmem 525 OpAMD64ORQmem 526 OpAMD64ORLmem 527 OpAMD64XORQmem 528 OpAMD64XORLmem 529 OpAMD64NEGQ 530 OpAMD64NEGL 531 OpAMD64NOTQ 532 OpAMD64NOTL 533 OpAMD64BSFQ 534 OpAMD64BSFL 535 OpAMD64BSRQ 536 OpAMD64BSRL 537 OpAMD64CMOVQEQ 538 OpAMD64CMOVLEQ 539 OpAMD64BSWAPQ 540 OpAMD64BSWAPL 541 OpAMD64POPCNTQ 542 OpAMD64POPCNTL 543 OpAMD64SQRTSD 544 OpAMD64SBBQcarrymask 545 OpAMD64SBBLcarrymask 546 OpAMD64SETEQ 547 OpAMD64SETNE 548 OpAMD64SETL 549 OpAMD64SETLE 550 OpAMD64SETG 551 OpAMD64SETGE 552 OpAMD64SETB 553 OpAMD64SETBE 554 OpAMD64SETA 555 OpAMD64SETAE 556 OpAMD64SETEQF 557 OpAMD64SETNEF 558 OpAMD64SETORD 559 OpAMD64SETNAN 560 OpAMD64SETGF 561 OpAMD64SETGEF 562 OpAMD64MOVBQSX 563 OpAMD64MOVBQZX 564 OpAMD64MOVWQSX 565 OpAMD64MOVWQZX 566 OpAMD64MOVLQSX 567 OpAMD64MOVLQZX 568 OpAMD64MOVLconst 569 OpAMD64MOVQconst 570 OpAMD64CVTTSD2SL 571 OpAMD64CVTTSD2SQ 572 OpAMD64CVTTSS2SL 573 OpAMD64CVTTSS2SQ 574 OpAMD64CVTSL2SS 575 OpAMD64CVTSL2SD 576 OpAMD64CVTSQ2SS 577 OpAMD64CVTSQ2SD 578 OpAMD64CVTSD2SS 579 OpAMD64CVTSS2SD 580 OpAMD64PXOR 581 OpAMD64LEAQ 582 OpAMD64LEAQ1 583 OpAMD64LEAQ2 584 OpAMD64LEAQ4 585 OpAMD64LEAQ8 586 OpAMD64LEAL 587 OpAMD64MOVBload 588 OpAMD64MOVBQSXload 589 OpAMD64MOVWload 590 OpAMD64MOVWQSXload 591 OpAMD64MOVLload 592 OpAMD64MOVLQSXload 593 OpAMD64MOVQload 594 OpAMD64MOVBstore 595 OpAMD64MOVWstore 596 OpAMD64MOVLstore 597 OpAMD64MOVQstore 598 OpAMD64MOVOload 599 OpAMD64MOVOstore 600 OpAMD64MOVBloadidx1 601 OpAMD64MOVWloadidx1 602 OpAMD64MOVWloadidx2 603 OpAMD64MOVLloadidx1 604 OpAMD64MOVLloadidx4 605 OpAMD64MOVQloadidx1 606 OpAMD64MOVQloadidx8 607 OpAMD64MOVBstoreidx1 608 OpAMD64MOVWstoreidx1 609 OpAMD64MOVWstoreidx2 610 OpAMD64MOVLstoreidx1 611 OpAMD64MOVLstoreidx4 612 OpAMD64MOVQstoreidx1 613 OpAMD64MOVQstoreidx8 614 OpAMD64MOVBstoreconst 615 OpAMD64MOVWstoreconst 616 OpAMD64MOVLstoreconst 617 OpAMD64MOVQstoreconst 618 OpAMD64MOVBstoreconstidx1 619 OpAMD64MOVWstoreconstidx1 620 OpAMD64MOVWstoreconstidx2 621 OpAMD64MOVLstoreconstidx1 622 OpAMD64MOVLstoreconstidx4 623 OpAMD64MOVQstoreconstidx1 624 OpAMD64MOVQstoreconstidx8 625 OpAMD64DUFFZERO 626 OpAMD64MOVOconst 627 OpAMD64REPSTOSQ 628 OpAMD64CALLstatic 629 OpAMD64CALLclosure 630 OpAMD64CALLinter 631 OpAMD64DUFFCOPY 632 OpAMD64REPMOVSQ 633 OpAMD64InvertFlags 634 OpAMD64LoweredGetG 635 OpAMD64LoweredGetClosurePtr 636 OpAMD64LoweredNilCheck 637 OpAMD64MOVQconvert 638 OpAMD64MOVLconvert 639 OpAMD64FlagEQ 640 OpAMD64FlagLT_ULT 641 OpAMD64FlagLT_UGT 642 OpAMD64FlagGT_UGT 643 OpAMD64FlagGT_ULT 644 OpAMD64MOVLatomicload 645 OpAMD64MOVQatomicload 646 OpAMD64XCHGL 647 OpAMD64XCHGQ 648 OpAMD64XADDLlock 649 OpAMD64XADDQlock 650 OpAMD64AddTupleFirst32 651 OpAMD64AddTupleFirst64 652 OpAMD64CMPXCHGLlock 653 OpAMD64CMPXCHGQlock 654 OpAMD64ANDBlock 655 OpAMD64ORBlock 656 657 OpARMADD 658 OpARMADDconst 659 OpARMSUB 660 OpARMSUBconst 661 OpARMRSB 662 OpARMRSBconst 663 OpARMMUL 664 OpARMHMUL 665 OpARMHMULU 666 OpARMCALLudiv 667 OpARMADDS 668 OpARMADDSconst 669 OpARMADC 670 OpARMADCconst 671 OpARMSUBS 672 OpARMSUBSconst 673 OpARMRSBSconst 674 OpARMSBC 675 OpARMSBCconst 676 OpARMRSCconst 677 OpARMMULLU 678 OpARMMULA 679 OpARMADDF 680 OpARMADDD 681 OpARMSUBF 682 OpARMSUBD 683 OpARMMULF 684 OpARMMULD 685 OpARMDIVF 686 OpARMDIVD 687 OpARMAND 688 OpARMANDconst 689 OpARMOR 690 OpARMORconst 691 OpARMXOR 692 OpARMXORconst 693 OpARMBIC 694 OpARMBICconst 695 OpARMMVN 696 OpARMNEGF 697 OpARMNEGD 698 OpARMSQRTD 699 OpARMCLZ 700 OpARMREV 701 OpARMRBIT 702 OpARMSLL 703 OpARMSLLconst 704 OpARMSRL 705 OpARMSRLconst 706 OpARMSRA 707 OpARMSRAconst 708 OpARMSRRconst 709 OpARMADDshiftLL 710 OpARMADDshiftRL 711 OpARMADDshiftRA 712 OpARMSUBshiftLL 713 OpARMSUBshiftRL 714 OpARMSUBshiftRA 715 OpARMRSBshiftLL 716 OpARMRSBshiftRL 717 OpARMRSBshiftRA 718 OpARMANDshiftLL 719 OpARMANDshiftRL 720 OpARMANDshiftRA 721 OpARMORshiftLL 722 OpARMORshiftRL 723 OpARMORshiftRA 724 OpARMXORshiftLL 725 OpARMXORshiftRL 726 OpARMXORshiftRA 727 OpARMXORshiftRR 728 OpARMBICshiftLL 729 OpARMBICshiftRL 730 OpARMBICshiftRA 731 OpARMMVNshiftLL 732 OpARMMVNshiftRL 733 OpARMMVNshiftRA 734 OpARMADCshiftLL 735 OpARMADCshiftRL 736 OpARMADCshiftRA 737 OpARMSBCshiftLL 738 OpARMSBCshiftRL 739 OpARMSBCshiftRA 740 OpARMRSCshiftLL 741 OpARMRSCshiftRL 742 OpARMRSCshiftRA 743 OpARMADDSshiftLL 744 OpARMADDSshiftRL 745 OpARMADDSshiftRA 746 OpARMSUBSshiftLL 747 OpARMSUBSshiftRL 748 OpARMSUBSshiftRA 749 OpARMRSBSshiftLL 750 OpARMRSBSshiftRL 751 OpARMRSBSshiftRA 752 OpARMADDshiftLLreg 753 OpARMADDshiftRLreg 754 OpARMADDshiftRAreg 755 OpARMSUBshiftLLreg 756 OpARMSUBshiftRLreg 757 OpARMSUBshiftRAreg 758 OpARMRSBshiftLLreg 759 OpARMRSBshiftRLreg 760 OpARMRSBshiftRAreg 761 OpARMANDshiftLLreg 762 OpARMANDshiftRLreg 763 OpARMANDshiftRAreg 764 OpARMORshiftLLreg 765 OpARMORshiftRLreg 766 OpARMORshiftRAreg 767 OpARMXORshiftLLreg 768 OpARMXORshiftRLreg 769 OpARMXORshiftRAreg 770 OpARMBICshiftLLreg 771 OpARMBICshiftRLreg 772 OpARMBICshiftRAreg 773 OpARMMVNshiftLLreg 774 OpARMMVNshiftRLreg 775 OpARMMVNshiftRAreg 776 OpARMADCshiftLLreg 777 OpARMADCshiftRLreg 778 OpARMADCshiftRAreg 779 OpARMSBCshiftLLreg 780 OpARMSBCshiftRLreg 781 OpARMSBCshiftRAreg 782 OpARMRSCshiftLLreg 783 OpARMRSCshiftRLreg 784 OpARMRSCshiftRAreg 785 OpARMADDSshiftLLreg 786 OpARMADDSshiftRLreg 787 OpARMADDSshiftRAreg 788 OpARMSUBSshiftLLreg 789 OpARMSUBSshiftRLreg 790 OpARMSUBSshiftRAreg 791 OpARMRSBSshiftLLreg 792 OpARMRSBSshiftRLreg 793 OpARMRSBSshiftRAreg 794 OpARMCMP 795 OpARMCMPconst 796 OpARMCMN 797 OpARMCMNconst 798 OpARMTST 799 OpARMTSTconst 800 OpARMTEQ 801 OpARMTEQconst 802 OpARMCMPF 803 OpARMCMPD 804 OpARMCMPshiftLL 805 OpARMCMPshiftRL 806 OpARMCMPshiftRA 807 OpARMCMPshiftLLreg 808 OpARMCMPshiftRLreg 809 OpARMCMPshiftRAreg 810 OpARMCMPF0 811 OpARMCMPD0 812 OpARMMOVWconst 813 OpARMMOVFconst 814 OpARMMOVDconst 815 OpARMMOVWaddr 816 OpARMMOVBload 817 OpARMMOVBUload 818 OpARMMOVHload 819 OpARMMOVHUload 820 OpARMMOVWload 821 OpARMMOVFload 822 OpARMMOVDload 823 OpARMMOVBstore 824 OpARMMOVHstore 825 OpARMMOVWstore 826 OpARMMOVFstore 827 OpARMMOVDstore 828 OpARMMOVWloadidx 829 OpARMMOVWloadshiftLL 830 OpARMMOVWloadshiftRL 831 OpARMMOVWloadshiftRA 832 OpARMMOVWstoreidx 833 OpARMMOVWstoreshiftLL 834 OpARMMOVWstoreshiftRL 835 OpARMMOVWstoreshiftRA 836 OpARMMOVBreg 837 OpARMMOVBUreg 838 OpARMMOVHreg 839 OpARMMOVHUreg 840 OpARMMOVWreg 841 OpARMMOVWnop 842 OpARMMOVWF 843 OpARMMOVWD 844 OpARMMOVWUF 845 OpARMMOVWUD 846 OpARMMOVFW 847 OpARMMOVDW 848 OpARMMOVFWU 849 OpARMMOVDWU 850 OpARMMOVFD 851 OpARMMOVDF 852 OpARMCMOVWHSconst 853 OpARMCMOVWLSconst 854 OpARMSRAcond 855 OpARMCALLstatic 856 OpARMCALLclosure 857 OpARMCALLinter 858 OpARMLoweredNilCheck 859 OpARMEqual 860 OpARMNotEqual 861 OpARMLessThan 862 OpARMLessEqual 863 OpARMGreaterThan 864 OpARMGreaterEqual 865 OpARMLessThanU 866 OpARMLessEqualU 867 OpARMGreaterThanU 868 OpARMGreaterEqualU 869 OpARMDUFFZERO 870 OpARMDUFFCOPY 871 OpARMLoweredZero 872 OpARMLoweredMove 873 OpARMLoweredGetClosurePtr 874 OpARMMOVWconvert 875 OpARMFlagEQ 876 OpARMFlagLT_ULT 877 OpARMFlagLT_UGT 878 OpARMFlagGT_UGT 879 OpARMFlagGT_ULT 880 OpARMInvertFlags 881 882 OpARM64ADD 883 OpARM64ADDconst 884 OpARM64SUB 885 OpARM64SUBconst 886 OpARM64MUL 887 OpARM64MULW 888 OpARM64MULH 889 OpARM64UMULH 890 OpARM64MULL 891 OpARM64UMULL 892 OpARM64DIV 893 OpARM64UDIV 894 OpARM64DIVW 895 OpARM64UDIVW 896 OpARM64MOD 897 OpARM64UMOD 898 OpARM64MODW 899 OpARM64UMODW 900 OpARM64FADDS 901 OpARM64FADDD 902 OpARM64FSUBS 903 OpARM64FSUBD 904 OpARM64FMULS 905 OpARM64FMULD 906 OpARM64FDIVS 907 OpARM64FDIVD 908 OpARM64AND 909 OpARM64ANDconst 910 OpARM64OR 911 OpARM64ORconst 912 OpARM64XOR 913 OpARM64XORconst 914 OpARM64BIC 915 OpARM64BICconst 916 OpARM64MVN 917 OpARM64NEG 918 OpARM64FNEGS 919 OpARM64FNEGD 920 OpARM64FSQRTD 921 OpARM64REV 922 OpARM64REVW 923 OpARM64REV16W 924 OpARM64RBIT 925 OpARM64RBITW 926 OpARM64CLZ 927 OpARM64CLZW 928 OpARM64SLL 929 OpARM64SLLconst 930 OpARM64SRL 931 OpARM64SRLconst 932 OpARM64SRA 933 OpARM64SRAconst 934 OpARM64RORconst 935 OpARM64RORWconst 936 OpARM64CMP 937 OpARM64CMPconst 938 OpARM64CMPW 939 OpARM64CMPWconst 940 OpARM64CMN 941 OpARM64CMNconst 942 OpARM64CMNW 943 OpARM64CMNWconst 944 OpARM64FCMPS 945 OpARM64FCMPD 946 OpARM64ADDshiftLL 947 OpARM64ADDshiftRL 948 OpARM64ADDshiftRA 949 OpARM64SUBshiftLL 950 OpARM64SUBshiftRL 951 OpARM64SUBshiftRA 952 OpARM64ANDshiftLL 953 OpARM64ANDshiftRL 954 OpARM64ANDshiftRA 955 OpARM64ORshiftLL 956 OpARM64ORshiftRL 957 OpARM64ORshiftRA 958 OpARM64XORshiftLL 959 OpARM64XORshiftRL 960 OpARM64XORshiftRA 961 OpARM64BICshiftLL 962 OpARM64BICshiftRL 963 OpARM64BICshiftRA 964 OpARM64CMPshiftLL 965 OpARM64CMPshiftRL 966 OpARM64CMPshiftRA 967 OpARM64MOVDconst 968 OpARM64FMOVSconst 969 OpARM64FMOVDconst 970 OpARM64MOVDaddr 971 OpARM64MOVBload 972 OpARM64MOVBUload 973 OpARM64MOVHload 974 OpARM64MOVHUload 975 OpARM64MOVWload 976 OpARM64MOVWUload 977 OpARM64MOVDload 978 OpARM64FMOVSload 979 OpARM64FMOVDload 980 OpARM64MOVBstore 981 OpARM64MOVHstore 982 OpARM64MOVWstore 983 OpARM64MOVDstore 984 OpARM64FMOVSstore 985 OpARM64FMOVDstore 986 OpARM64MOVBstorezero 987 OpARM64MOVHstorezero 988 OpARM64MOVWstorezero 989 OpARM64MOVDstorezero 990 OpARM64MOVBreg 991 OpARM64MOVBUreg 992 OpARM64MOVHreg 993 OpARM64MOVHUreg 994 OpARM64MOVWreg 995 OpARM64MOVWUreg 996 OpARM64MOVDreg 997 OpARM64MOVDnop 998 OpARM64SCVTFWS 999 OpARM64SCVTFWD 1000 OpARM64UCVTFWS 1001 OpARM64UCVTFWD 1002 OpARM64SCVTFS 1003 OpARM64SCVTFD 1004 OpARM64UCVTFS 1005 OpARM64UCVTFD 1006 OpARM64FCVTZSSW 1007 OpARM64FCVTZSDW 1008 OpARM64FCVTZUSW 1009 OpARM64FCVTZUDW 1010 OpARM64FCVTZSS 1011 OpARM64FCVTZSD 1012 OpARM64FCVTZUS 1013 OpARM64FCVTZUD 1014 OpARM64FCVTSD 1015 OpARM64FCVTDS 1016 OpARM64CSELULT 1017 OpARM64CSELULT0 1018 OpARM64CALLstatic 1019 OpARM64CALLclosure 1020 OpARM64CALLinter 1021 OpARM64LoweredNilCheck 1022 OpARM64Equal 1023 OpARM64NotEqual 1024 OpARM64LessThan 1025 OpARM64LessEqual 1026 OpARM64GreaterThan 1027 OpARM64GreaterEqual 1028 OpARM64LessThanU 1029 OpARM64LessEqualU 1030 OpARM64GreaterThanU 1031 OpARM64GreaterEqualU 1032 OpARM64DUFFZERO 1033 OpARM64LoweredZero 1034 OpARM64DUFFCOPY 1035 OpARM64LoweredMove 1036 OpARM64LoweredGetClosurePtr 1037 OpARM64MOVDconvert 1038 OpARM64FlagEQ 1039 OpARM64FlagLT_ULT 1040 OpARM64FlagLT_UGT 1041 OpARM64FlagGT_UGT 1042 OpARM64FlagGT_ULT 1043 OpARM64InvertFlags 1044 OpARM64LDAR 1045 OpARM64LDARW 1046 OpARM64STLR 1047 OpARM64STLRW 1048 OpARM64LoweredAtomicExchange64 1049 OpARM64LoweredAtomicExchange32 1050 OpARM64LoweredAtomicAdd64 1051 OpARM64LoweredAtomicAdd32 1052 OpARM64LoweredAtomicCas64 1053 OpARM64LoweredAtomicCas32 1054 OpARM64LoweredAtomicAnd8 1055 OpARM64LoweredAtomicOr8 1056 1057 OpMIPSADD 1058 OpMIPSADDconst 1059 OpMIPSSUB 1060 OpMIPSSUBconst 1061 OpMIPSMUL 1062 OpMIPSMULT 1063 OpMIPSMULTU 1064 OpMIPSDIV 1065 OpMIPSDIVU 1066 OpMIPSADDF 1067 OpMIPSADDD 1068 OpMIPSSUBF 1069 OpMIPSSUBD 1070 OpMIPSMULF 1071 OpMIPSMULD 1072 OpMIPSDIVF 1073 OpMIPSDIVD 1074 OpMIPSAND 1075 OpMIPSANDconst 1076 OpMIPSOR 1077 OpMIPSORconst 1078 OpMIPSXOR 1079 OpMIPSXORconst 1080 OpMIPSNOR 1081 OpMIPSNORconst 1082 OpMIPSNEG 1083 OpMIPSNEGF 1084 OpMIPSNEGD 1085 OpMIPSSQRTD 1086 OpMIPSSLL 1087 OpMIPSSLLconst 1088 OpMIPSSRL 1089 OpMIPSSRLconst 1090 OpMIPSSRA 1091 OpMIPSSRAconst 1092 OpMIPSCLZ 1093 OpMIPSSGT 1094 OpMIPSSGTconst 1095 OpMIPSSGTzero 1096 OpMIPSSGTU 1097 OpMIPSSGTUconst 1098 OpMIPSSGTUzero 1099 OpMIPSCMPEQF 1100 OpMIPSCMPEQD 1101 OpMIPSCMPGEF 1102 OpMIPSCMPGED 1103 OpMIPSCMPGTF 1104 OpMIPSCMPGTD 1105 OpMIPSMOVWconst 1106 OpMIPSMOVFconst 1107 OpMIPSMOVDconst 1108 OpMIPSMOVWaddr 1109 OpMIPSMOVBload 1110 OpMIPSMOVBUload 1111 OpMIPSMOVHload 1112 OpMIPSMOVHUload 1113 OpMIPSMOVWload 1114 OpMIPSMOVFload 1115 OpMIPSMOVDload 1116 OpMIPSMOVBstore 1117 OpMIPSMOVHstore 1118 OpMIPSMOVWstore 1119 OpMIPSMOVFstore 1120 OpMIPSMOVDstore 1121 OpMIPSMOVBstorezero 1122 OpMIPSMOVHstorezero 1123 OpMIPSMOVWstorezero 1124 OpMIPSMOVBreg 1125 OpMIPSMOVBUreg 1126 OpMIPSMOVHreg 1127 OpMIPSMOVHUreg 1128 OpMIPSMOVWreg 1129 OpMIPSMOVWnop 1130 OpMIPSCMOVZ 1131 OpMIPSCMOVZzero 1132 OpMIPSMOVWF 1133 OpMIPSMOVWD 1134 OpMIPSTRUNCFW 1135 OpMIPSTRUNCDW 1136 OpMIPSMOVFD 1137 OpMIPSMOVDF 1138 OpMIPSCALLstatic 1139 OpMIPSCALLclosure 1140 OpMIPSCALLinter 1141 OpMIPSLoweredAtomicLoad 1142 OpMIPSLoweredAtomicStore 1143 OpMIPSLoweredAtomicStorezero 1144 OpMIPSLoweredAtomicExchange 1145 OpMIPSLoweredAtomicAdd 1146 OpMIPSLoweredAtomicAddconst 1147 OpMIPSLoweredAtomicCas 1148 OpMIPSLoweredAtomicAnd 1149 OpMIPSLoweredAtomicOr 1150 OpMIPSLoweredZero 1151 OpMIPSLoweredMove 1152 OpMIPSLoweredNilCheck 1153 OpMIPSFPFlagTrue 1154 OpMIPSFPFlagFalse 1155 OpMIPSLoweredGetClosurePtr 1156 OpMIPSMOVWconvert 1157 1158 OpMIPS64ADDV 1159 OpMIPS64ADDVconst 1160 OpMIPS64SUBV 1161 OpMIPS64SUBVconst 1162 OpMIPS64MULV 1163 OpMIPS64MULVU 1164 OpMIPS64DIVV 1165 OpMIPS64DIVVU 1166 OpMIPS64ADDF 1167 OpMIPS64ADDD 1168 OpMIPS64SUBF 1169 OpMIPS64SUBD 1170 OpMIPS64MULF 1171 OpMIPS64MULD 1172 OpMIPS64DIVF 1173 OpMIPS64DIVD 1174 OpMIPS64AND 1175 OpMIPS64ANDconst 1176 OpMIPS64OR 1177 OpMIPS64ORconst 1178 OpMIPS64XOR 1179 OpMIPS64XORconst 1180 OpMIPS64NOR 1181 OpMIPS64NORconst 1182 OpMIPS64NEGV 1183 OpMIPS64NEGF 1184 OpMIPS64NEGD 1185 OpMIPS64SLLV 1186 OpMIPS64SLLVconst 1187 OpMIPS64SRLV 1188 OpMIPS64SRLVconst 1189 OpMIPS64SRAV 1190 OpMIPS64SRAVconst 1191 OpMIPS64SGT 1192 OpMIPS64SGTconst 1193 OpMIPS64SGTU 1194 OpMIPS64SGTUconst 1195 OpMIPS64CMPEQF 1196 OpMIPS64CMPEQD 1197 OpMIPS64CMPGEF 1198 OpMIPS64CMPGED 1199 OpMIPS64CMPGTF 1200 OpMIPS64CMPGTD 1201 OpMIPS64MOVVconst 1202 OpMIPS64MOVFconst 1203 OpMIPS64MOVDconst 1204 OpMIPS64MOVVaddr 1205 OpMIPS64MOVBload 1206 OpMIPS64MOVBUload 1207 OpMIPS64MOVHload 1208 OpMIPS64MOVHUload 1209 OpMIPS64MOVWload 1210 OpMIPS64MOVWUload 1211 OpMIPS64MOVVload 1212 OpMIPS64MOVFload 1213 OpMIPS64MOVDload 1214 OpMIPS64MOVBstore 1215 OpMIPS64MOVHstore 1216 OpMIPS64MOVWstore 1217 OpMIPS64MOVVstore 1218 OpMIPS64MOVFstore 1219 OpMIPS64MOVDstore 1220 OpMIPS64MOVBstorezero 1221 OpMIPS64MOVHstorezero 1222 OpMIPS64MOVWstorezero 1223 OpMIPS64MOVVstorezero 1224 OpMIPS64MOVBreg 1225 OpMIPS64MOVBUreg 1226 OpMIPS64MOVHreg 1227 OpMIPS64MOVHUreg 1228 OpMIPS64MOVWreg 1229 OpMIPS64MOVWUreg 1230 OpMIPS64MOVVreg 1231 OpMIPS64MOVVnop 1232 OpMIPS64MOVWF 1233 OpMIPS64MOVWD 1234 OpMIPS64MOVVF 1235 OpMIPS64MOVVD 1236 OpMIPS64TRUNCFW 1237 OpMIPS64TRUNCDW 1238 OpMIPS64TRUNCFV 1239 OpMIPS64TRUNCDV 1240 OpMIPS64MOVFD 1241 OpMIPS64MOVDF 1242 OpMIPS64CALLstatic 1243 OpMIPS64CALLclosure 1244 OpMIPS64CALLinter 1245 OpMIPS64DUFFZERO 1246 OpMIPS64LoweredZero 1247 OpMIPS64LoweredMove 1248 OpMIPS64LoweredNilCheck 1249 OpMIPS64FPFlagTrue 1250 OpMIPS64FPFlagFalse 1251 OpMIPS64LoweredGetClosurePtr 1252 OpMIPS64MOVVconvert 1253 1254 OpPPC64ADD 1255 OpPPC64ADDconst 1256 OpPPC64FADD 1257 OpPPC64FADDS 1258 OpPPC64SUB 1259 OpPPC64FSUB 1260 OpPPC64FSUBS 1261 OpPPC64MULLD 1262 OpPPC64MULLW 1263 OpPPC64MULHD 1264 OpPPC64MULHW 1265 OpPPC64MULHDU 1266 OpPPC64MULHWU 1267 OpPPC64FMUL 1268 OpPPC64FMULS 1269 OpPPC64FMADD 1270 OpPPC64FMADDS 1271 OpPPC64FMSUB 1272 OpPPC64FMSUBS 1273 OpPPC64SRAD 1274 OpPPC64SRAW 1275 OpPPC64SRD 1276 OpPPC64SRW 1277 OpPPC64SLD 1278 OpPPC64SLW 1279 OpPPC64ADDconstForCarry 1280 OpPPC64MaskIfNotCarry 1281 OpPPC64SRADconst 1282 OpPPC64SRAWconst 1283 OpPPC64SRDconst 1284 OpPPC64SRWconst 1285 OpPPC64SLDconst 1286 OpPPC64SLWconst 1287 OpPPC64FDIV 1288 OpPPC64FDIVS 1289 OpPPC64DIVD 1290 OpPPC64DIVW 1291 OpPPC64DIVDU 1292 OpPPC64DIVWU 1293 OpPPC64FCTIDZ 1294 OpPPC64FCTIWZ 1295 OpPPC64FCFID 1296 OpPPC64FRSP 1297 OpPPC64Xf2i64 1298 OpPPC64Xi2f64 1299 OpPPC64AND 1300 OpPPC64ANDN 1301 OpPPC64OR 1302 OpPPC64ORN 1303 OpPPC64NOR 1304 OpPPC64XOR 1305 OpPPC64EQV 1306 OpPPC64NEG 1307 OpPPC64FNEG 1308 OpPPC64FSQRT 1309 OpPPC64FSQRTS 1310 OpPPC64ORconst 1311 OpPPC64XORconst 1312 OpPPC64ANDconst 1313 OpPPC64ANDCCconst 1314 OpPPC64MOVBreg 1315 OpPPC64MOVBZreg 1316 OpPPC64MOVHreg 1317 OpPPC64MOVHZreg 1318 OpPPC64MOVWreg 1319 OpPPC64MOVWZreg 1320 OpPPC64MOVBZload 1321 OpPPC64MOVHload 1322 OpPPC64MOVHZload 1323 OpPPC64MOVWload 1324 OpPPC64MOVWZload 1325 OpPPC64MOVDload 1326 OpPPC64FMOVDload 1327 OpPPC64FMOVSload 1328 OpPPC64MOVBstore 1329 OpPPC64MOVHstore 1330 OpPPC64MOVWstore 1331 OpPPC64MOVDstore 1332 OpPPC64FMOVDstore 1333 OpPPC64FMOVSstore 1334 OpPPC64MOVBstorezero 1335 OpPPC64MOVHstorezero 1336 OpPPC64MOVWstorezero 1337 OpPPC64MOVDstorezero 1338 OpPPC64MOVDaddr 1339 OpPPC64MOVDconst 1340 OpPPC64FMOVDconst 1341 OpPPC64FMOVSconst 1342 OpPPC64FCMPU 1343 OpPPC64CMP 1344 OpPPC64CMPU 1345 OpPPC64CMPW 1346 OpPPC64CMPWU 1347 OpPPC64CMPconst 1348 OpPPC64CMPUconst 1349 OpPPC64CMPWconst 1350 OpPPC64CMPWUconst 1351 OpPPC64Equal 1352 OpPPC64NotEqual 1353 OpPPC64LessThan 1354 OpPPC64FLessThan 1355 OpPPC64LessEqual 1356 OpPPC64FLessEqual 1357 OpPPC64GreaterThan 1358 OpPPC64FGreaterThan 1359 OpPPC64GreaterEqual 1360 OpPPC64FGreaterEqual 1361 OpPPC64LoweredGetClosurePtr 1362 OpPPC64LoweredNilCheck 1363 OpPPC64LoweredRound32F 1364 OpPPC64LoweredRound64F 1365 OpPPC64MOVDconvert 1366 OpPPC64CALLstatic 1367 OpPPC64CALLclosure 1368 OpPPC64CALLinter 1369 OpPPC64LoweredZero 1370 OpPPC64LoweredMove 1371 OpPPC64LoweredAtomicStore32 1372 OpPPC64LoweredAtomicStore64 1373 OpPPC64LoweredAtomicLoad32 1374 OpPPC64LoweredAtomicLoad64 1375 OpPPC64LoweredAtomicLoadPtr 1376 OpPPC64LoweredAtomicAdd32 1377 OpPPC64LoweredAtomicAdd64 1378 OpPPC64LoweredAtomicExchange32 1379 OpPPC64LoweredAtomicExchange64 1380 OpPPC64LoweredAtomicCas64 1381 OpPPC64LoweredAtomicCas32 1382 OpPPC64LoweredAtomicAnd8 1383 OpPPC64LoweredAtomicOr8 1384 OpPPC64InvertFlags 1385 OpPPC64FlagEQ 1386 OpPPC64FlagLT 1387 OpPPC64FlagGT 1388 1389 OpS390XFADDS 1390 OpS390XFADD 1391 OpS390XFSUBS 1392 OpS390XFSUB 1393 OpS390XFMULS 1394 OpS390XFMUL 1395 OpS390XFDIVS 1396 OpS390XFDIV 1397 OpS390XFNEGS 1398 OpS390XFNEG 1399 OpS390XFMADDS 1400 OpS390XFMADD 1401 OpS390XFMSUBS 1402 OpS390XFMSUB 1403 OpS390XFMOVSload 1404 OpS390XFMOVDload 1405 OpS390XFMOVSconst 1406 OpS390XFMOVDconst 1407 OpS390XFMOVSloadidx 1408 OpS390XFMOVDloadidx 1409 OpS390XFMOVSstore 1410 OpS390XFMOVDstore 1411 OpS390XFMOVSstoreidx 1412 OpS390XFMOVDstoreidx 1413 OpS390XADD 1414 OpS390XADDW 1415 OpS390XADDconst 1416 OpS390XADDWconst 1417 OpS390XADDload 1418 OpS390XADDWload 1419 OpS390XSUB 1420 OpS390XSUBW 1421 OpS390XSUBconst 1422 OpS390XSUBWconst 1423 OpS390XSUBload 1424 OpS390XSUBWload 1425 OpS390XMULLD 1426 OpS390XMULLW 1427 OpS390XMULLDconst 1428 OpS390XMULLWconst 1429 OpS390XMULLDload 1430 OpS390XMULLWload 1431 OpS390XMULHD 1432 OpS390XMULHDU 1433 OpS390XDIVD 1434 OpS390XDIVW 1435 OpS390XDIVDU 1436 OpS390XDIVWU 1437 OpS390XMODD 1438 OpS390XMODW 1439 OpS390XMODDU 1440 OpS390XMODWU 1441 OpS390XAND 1442 OpS390XANDW 1443 OpS390XANDconst 1444 OpS390XANDWconst 1445 OpS390XANDload 1446 OpS390XANDWload 1447 OpS390XOR 1448 OpS390XORW 1449 OpS390XORconst 1450 OpS390XORWconst 1451 OpS390XORload 1452 OpS390XORWload 1453 OpS390XXOR 1454 OpS390XXORW 1455 OpS390XXORconst 1456 OpS390XXORWconst 1457 OpS390XXORload 1458 OpS390XXORWload 1459 OpS390XCMP 1460 OpS390XCMPW 1461 OpS390XCMPU 1462 OpS390XCMPWU 1463 OpS390XCMPconst 1464 OpS390XCMPWconst 1465 OpS390XCMPUconst 1466 OpS390XCMPWUconst 1467 OpS390XFCMPS 1468 OpS390XFCMP 1469 OpS390XSLD 1470 OpS390XSLW 1471 OpS390XSLDconst 1472 OpS390XSLWconst 1473 OpS390XSRD 1474 OpS390XSRW 1475 OpS390XSRDconst 1476 OpS390XSRWconst 1477 OpS390XSRAD 1478 OpS390XSRAW 1479 OpS390XSRADconst 1480 OpS390XSRAWconst 1481 OpS390XRLLGconst 1482 OpS390XRLLconst 1483 OpS390XNEG 1484 OpS390XNEGW 1485 OpS390XNOT 1486 OpS390XNOTW 1487 OpS390XFSQRT 1488 OpS390XSUBEcarrymask 1489 OpS390XSUBEWcarrymask 1490 OpS390XMOVDEQ 1491 OpS390XMOVDNE 1492 OpS390XMOVDLT 1493 OpS390XMOVDLE 1494 OpS390XMOVDGT 1495 OpS390XMOVDGE 1496 OpS390XMOVDGTnoinv 1497 OpS390XMOVDGEnoinv 1498 OpS390XMOVBreg 1499 OpS390XMOVBZreg 1500 OpS390XMOVHreg 1501 OpS390XMOVHZreg 1502 OpS390XMOVWreg 1503 OpS390XMOVWZreg 1504 OpS390XMOVDreg 1505 OpS390XMOVDnop 1506 OpS390XMOVDconst 1507 OpS390XCFDBRA 1508 OpS390XCGDBRA 1509 OpS390XCFEBRA 1510 OpS390XCGEBRA 1511 OpS390XCEFBRA 1512 OpS390XCDFBRA 1513 OpS390XCEGBRA 1514 OpS390XCDGBRA 1515 OpS390XLEDBR 1516 OpS390XLDEBR 1517 OpS390XMOVDaddr 1518 OpS390XMOVDaddridx 1519 OpS390XMOVBZload 1520 OpS390XMOVBload 1521 OpS390XMOVHZload 1522 OpS390XMOVHload 1523 OpS390XMOVWZload 1524 OpS390XMOVWload 1525 OpS390XMOVDload 1526 OpS390XMOVWBR 1527 OpS390XMOVDBR 1528 OpS390XMOVHBRload 1529 OpS390XMOVWBRload 1530 OpS390XMOVDBRload 1531 OpS390XMOVBstore 1532 OpS390XMOVHstore 1533 OpS390XMOVWstore 1534 OpS390XMOVDstore 1535 OpS390XMOVHBRstore 1536 OpS390XMOVWBRstore 1537 OpS390XMOVDBRstore 1538 OpS390XMVC 1539 OpS390XMOVBZloadidx 1540 OpS390XMOVHZloadidx 1541 OpS390XMOVWZloadidx 1542 OpS390XMOVDloadidx 1543 OpS390XMOVHBRloadidx 1544 OpS390XMOVWBRloadidx 1545 OpS390XMOVDBRloadidx 1546 OpS390XMOVBstoreidx 1547 OpS390XMOVHstoreidx 1548 OpS390XMOVWstoreidx 1549 OpS390XMOVDstoreidx 1550 OpS390XMOVHBRstoreidx 1551 OpS390XMOVWBRstoreidx 1552 OpS390XMOVDBRstoreidx 1553 OpS390XMOVBstoreconst 1554 OpS390XMOVHstoreconst 1555 OpS390XMOVWstoreconst 1556 OpS390XMOVDstoreconst 1557 OpS390XCLEAR 1558 OpS390XCALLstatic 1559 OpS390XCALLclosure 1560 OpS390XCALLinter 1561 OpS390XInvertFlags 1562 OpS390XLoweredGetG 1563 OpS390XLoweredGetClosurePtr 1564 OpS390XLoweredNilCheck 1565 OpS390XLoweredRound32F 1566 OpS390XLoweredRound64F 1567 OpS390XMOVDconvert 1568 OpS390XFlagEQ 1569 OpS390XFlagLT 1570 OpS390XFlagGT 1571 OpS390XMOVWZatomicload 1572 OpS390XMOVDatomicload 1573 OpS390XMOVWatomicstore 1574 OpS390XMOVDatomicstore 1575 OpS390XLAA 1576 OpS390XLAAG 1577 OpS390XAddTupleFirst32 1578 OpS390XAddTupleFirst64 1579 OpS390XLoweredAtomicCas32 1580 OpS390XLoweredAtomicCas64 1581 OpS390XLoweredAtomicExchange32 1582 OpS390XLoweredAtomicExchange64 1583 OpS390XFLOGR 1584 OpS390XSTMG2 1585 OpS390XSTMG3 1586 OpS390XSTMG4 1587 OpS390XSTM2 1588 OpS390XSTM3 1589 OpS390XSTM4 1590 OpS390XLoweredMove 1591 OpS390XLoweredZero 1592 1593 OpAdd8 1594 OpAdd16 1595 OpAdd32 1596 OpAdd64 1597 OpAddPtr 1598 OpAdd32F 1599 OpAdd64F 1600 OpSub8 1601 OpSub16 1602 OpSub32 1603 OpSub64 1604 OpSubPtr 1605 OpSub32F 1606 OpSub64F 1607 OpMul8 1608 OpMul16 1609 OpMul32 1610 OpMul64 1611 OpMul32F 1612 OpMul64F 1613 OpDiv32F 1614 OpDiv64F 1615 OpHmul32 1616 OpHmul32u 1617 OpHmul64 1618 OpHmul64u 1619 OpMul32uhilo 1620 OpMul64uhilo 1621 OpAvg32u 1622 OpAvg64u 1623 OpDiv8 1624 OpDiv8u 1625 OpDiv16 1626 OpDiv16u 1627 OpDiv32 1628 OpDiv32u 1629 OpDiv64 1630 OpDiv64u 1631 OpDiv128u 1632 OpMod8 1633 OpMod8u 1634 OpMod16 1635 OpMod16u 1636 OpMod32 1637 OpMod32u 1638 OpMod64 1639 OpMod64u 1640 OpAnd8 1641 OpAnd16 1642 OpAnd32 1643 OpAnd64 1644 OpOr8 1645 OpOr16 1646 OpOr32 1647 OpOr64 1648 OpXor8 1649 OpXor16 1650 OpXor32 1651 OpXor64 1652 OpLsh8x8 1653 OpLsh8x16 1654 OpLsh8x32 1655 OpLsh8x64 1656 OpLsh16x8 1657 OpLsh16x16 1658 OpLsh16x32 1659 OpLsh16x64 1660 OpLsh32x8 1661 OpLsh32x16 1662 OpLsh32x32 1663 OpLsh32x64 1664 OpLsh64x8 1665 OpLsh64x16 1666 OpLsh64x32 1667 OpLsh64x64 1668 OpRsh8x8 1669 OpRsh8x16 1670 OpRsh8x32 1671 OpRsh8x64 1672 OpRsh16x8 1673 OpRsh16x16 1674 OpRsh16x32 1675 OpRsh16x64 1676 OpRsh32x8 1677 OpRsh32x16 1678 OpRsh32x32 1679 OpRsh32x64 1680 OpRsh64x8 1681 OpRsh64x16 1682 OpRsh64x32 1683 OpRsh64x64 1684 OpRsh8Ux8 1685 OpRsh8Ux16 1686 OpRsh8Ux32 1687 OpRsh8Ux64 1688 OpRsh16Ux8 1689 OpRsh16Ux16 1690 OpRsh16Ux32 1691 OpRsh16Ux64 1692 OpRsh32Ux8 1693 OpRsh32Ux16 1694 OpRsh32Ux32 1695 OpRsh32Ux64 1696 OpRsh64Ux8 1697 OpRsh64Ux16 1698 OpRsh64Ux32 1699 OpRsh64Ux64 1700 OpEq8 1701 OpEq16 1702 OpEq32 1703 OpEq64 1704 OpEqPtr 1705 OpEqInter 1706 OpEqSlice 1707 OpEq32F 1708 OpEq64F 1709 OpNeq8 1710 OpNeq16 1711 OpNeq32 1712 OpNeq64 1713 OpNeqPtr 1714 OpNeqInter 1715 OpNeqSlice 1716 OpNeq32F 1717 OpNeq64F 1718 OpLess8 1719 OpLess8U 1720 OpLess16 1721 OpLess16U 1722 OpLess32 1723 OpLess32U 1724 OpLess64 1725 OpLess64U 1726 OpLess32F 1727 OpLess64F 1728 OpLeq8 1729 OpLeq8U 1730 OpLeq16 1731 OpLeq16U 1732 OpLeq32 1733 OpLeq32U 1734 OpLeq64 1735 OpLeq64U 1736 OpLeq32F 1737 OpLeq64F 1738 OpGreater8 1739 OpGreater8U 1740 OpGreater16 1741 OpGreater16U 1742 OpGreater32 1743 OpGreater32U 1744 OpGreater64 1745 OpGreater64U 1746 OpGreater32F 1747 OpGreater64F 1748 OpGeq8 1749 OpGeq8U 1750 OpGeq16 1751 OpGeq16U 1752 OpGeq32 1753 OpGeq32U 1754 OpGeq64 1755 OpGeq64U 1756 OpGeq32F 1757 OpGeq64F 1758 OpAndB 1759 OpOrB 1760 OpEqB 1761 OpNeqB 1762 OpNot 1763 OpNeg8 1764 OpNeg16 1765 OpNeg32 1766 OpNeg64 1767 OpNeg32F 1768 OpNeg64F 1769 OpCom8 1770 OpCom16 1771 OpCom32 1772 OpCom64 1773 OpCtz32 1774 OpCtz64 1775 OpBitLen32 1776 OpBitLen64 1777 OpBswap32 1778 OpBswap64 1779 OpBitRev8 1780 OpBitRev16 1781 OpBitRev32 1782 OpBitRev64 1783 OpPopCount8 1784 OpPopCount16 1785 OpPopCount32 1786 OpPopCount64 1787 OpSqrt 1788 OpPhi 1789 OpCopy 1790 OpConvert 1791 OpConstBool 1792 OpConstString 1793 OpConstNil 1794 OpConst8 1795 OpConst16 1796 OpConst32 1797 OpConst64 1798 OpConst32F 1799 OpConst64F 1800 OpConstInterface 1801 OpConstSlice 1802 OpInitMem 1803 OpArg 1804 OpAddr 1805 OpSP 1806 OpSB 1807 OpLoad 1808 OpStore 1809 OpMove 1810 OpZero 1811 OpStoreWB 1812 OpMoveWB 1813 OpZeroWB 1814 OpClosureCall 1815 OpStaticCall 1816 OpInterCall 1817 OpSignExt8to16 1818 OpSignExt8to32 1819 OpSignExt8to64 1820 OpSignExt16to32 1821 OpSignExt16to64 1822 OpSignExt32to64 1823 OpZeroExt8to16 1824 OpZeroExt8to32 1825 OpZeroExt8to64 1826 OpZeroExt16to32 1827 OpZeroExt16to64 1828 OpZeroExt32to64 1829 OpTrunc16to8 1830 OpTrunc32to8 1831 OpTrunc32to16 1832 OpTrunc64to8 1833 OpTrunc64to16 1834 OpTrunc64to32 1835 OpCvt32to32F 1836 OpCvt32to64F 1837 OpCvt64to32F 1838 OpCvt64to64F 1839 OpCvt32Fto32 1840 OpCvt32Fto64 1841 OpCvt64Fto32 1842 OpCvt64Fto64 1843 OpCvt32Fto64F 1844 OpCvt64Fto32F 1845 OpRound32F 1846 OpRound64F 1847 OpIsNonNil 1848 OpIsInBounds 1849 OpIsSliceInBounds 1850 OpNilCheck 1851 OpGetG 1852 OpGetClosurePtr 1853 OpPtrIndex 1854 OpOffPtr 1855 OpSliceMake 1856 OpSlicePtr 1857 OpSliceLen 1858 OpSliceCap 1859 OpComplexMake 1860 OpComplexReal 1861 OpComplexImag 1862 OpStringMake 1863 OpStringPtr 1864 OpStringLen 1865 OpIMake 1866 OpITab 1867 OpIData 1868 OpStructMake0 1869 OpStructMake1 1870 OpStructMake2 1871 OpStructMake3 1872 OpStructMake4 1873 OpStructSelect 1874 OpArrayMake0 1875 OpArrayMake1 1876 OpArraySelect 1877 OpStoreReg 1878 OpLoadReg 1879 OpFwdRef 1880 OpUnknown 1881 OpVarDef 1882 OpVarKill 1883 OpVarLive 1884 OpKeepAlive 1885 OpInt64Make 1886 OpInt64Hi 1887 OpInt64Lo 1888 OpAdd32carry 1889 OpAdd32withcarry 1890 OpSub32carry 1891 OpSub32withcarry 1892 OpSignmask 1893 OpZeromask 1894 OpSlicemask 1895 OpCvt32Uto32F 1896 OpCvt32Uto64F 1897 OpCvt32Fto32U 1898 OpCvt64Fto32U 1899 OpCvt64Uto32F 1900 OpCvt64Uto64F 1901 OpCvt32Fto64U 1902 OpCvt64Fto64U 1903 OpSelect0 1904 OpSelect1 1905 OpAtomicLoad32 1906 OpAtomicLoad64 1907 OpAtomicLoadPtr 1908 OpAtomicStore32 1909 OpAtomicStore64 1910 OpAtomicStorePtrNoWB 1911 OpAtomicExchange32 1912 OpAtomicExchange64 1913 OpAtomicAdd32 1914 OpAtomicAdd64 1915 OpAtomicCompareAndSwap32 1916 OpAtomicCompareAndSwap64 1917 OpAtomicAnd8 1918 OpAtomicOr8 1919 ) 1920 1921 var opcodeTable = [...]opInfo{ 1922 {name: "OpInvalid"}, 1923 1924 { 1925 name: "ADDSS", 1926 argLen: 2, 1927 commutative: true, 1928 resultInArg0: true, 1929 usesScratch: true, 1930 asm: x86.AADDSS, 1931 reg: regInfo{ 1932 inputs: []inputInfo{ 1933 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1934 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1935 }, 1936 outputs: []outputInfo{ 1937 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1938 }, 1939 }, 1940 }, 1941 { 1942 name: "ADDSD", 1943 argLen: 2, 1944 commutative: true, 1945 resultInArg0: true, 1946 asm: x86.AADDSD, 1947 reg: regInfo{ 1948 inputs: []inputInfo{ 1949 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1950 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1951 }, 1952 outputs: []outputInfo{ 1953 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1954 }, 1955 }, 1956 }, 1957 { 1958 name: "SUBSS", 1959 argLen: 2, 1960 resultInArg0: true, 1961 usesScratch: true, 1962 asm: x86.ASUBSS, 1963 reg: regInfo{ 1964 inputs: []inputInfo{ 1965 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1966 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1967 }, 1968 outputs: []outputInfo{ 1969 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1970 }, 1971 }, 1972 }, 1973 { 1974 name: "SUBSD", 1975 argLen: 2, 1976 resultInArg0: true, 1977 asm: x86.ASUBSD, 1978 reg: regInfo{ 1979 inputs: []inputInfo{ 1980 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1981 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1982 }, 1983 outputs: []outputInfo{ 1984 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1985 }, 1986 }, 1987 }, 1988 { 1989 name: "MULSS", 1990 argLen: 2, 1991 commutative: true, 1992 resultInArg0: true, 1993 usesScratch: true, 1994 asm: x86.AMULSS, 1995 reg: regInfo{ 1996 inputs: []inputInfo{ 1997 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1998 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1999 }, 2000 outputs: []outputInfo{ 2001 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2002 }, 2003 }, 2004 }, 2005 { 2006 name: "MULSD", 2007 argLen: 2, 2008 commutative: true, 2009 resultInArg0: true, 2010 asm: x86.AMULSD, 2011 reg: regInfo{ 2012 inputs: []inputInfo{ 2013 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2014 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2015 }, 2016 outputs: []outputInfo{ 2017 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2018 }, 2019 }, 2020 }, 2021 { 2022 name: "DIVSS", 2023 argLen: 2, 2024 resultInArg0: true, 2025 usesScratch: true, 2026 asm: x86.ADIVSS, 2027 reg: regInfo{ 2028 inputs: []inputInfo{ 2029 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2030 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2031 }, 2032 outputs: []outputInfo{ 2033 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2034 }, 2035 }, 2036 }, 2037 { 2038 name: "DIVSD", 2039 argLen: 2, 2040 resultInArg0: true, 2041 asm: x86.ADIVSD, 2042 reg: regInfo{ 2043 inputs: []inputInfo{ 2044 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2045 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2046 }, 2047 outputs: []outputInfo{ 2048 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2049 }, 2050 }, 2051 }, 2052 { 2053 name: "MOVSSload", 2054 auxType: auxSymOff, 2055 argLen: 2, 2056 faultOnNilArg0: true, 2057 symEffect: SymRead, 2058 asm: x86.AMOVSS, 2059 reg: regInfo{ 2060 inputs: []inputInfo{ 2061 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2062 }, 2063 outputs: []outputInfo{ 2064 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2065 }, 2066 }, 2067 }, 2068 { 2069 name: "MOVSDload", 2070 auxType: auxSymOff, 2071 argLen: 2, 2072 faultOnNilArg0: true, 2073 symEffect: SymRead, 2074 asm: x86.AMOVSD, 2075 reg: regInfo{ 2076 inputs: []inputInfo{ 2077 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2078 }, 2079 outputs: []outputInfo{ 2080 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2081 }, 2082 }, 2083 }, 2084 { 2085 name: "MOVSSconst", 2086 auxType: auxFloat32, 2087 argLen: 0, 2088 rematerializeable: true, 2089 asm: x86.AMOVSS, 2090 reg: regInfo{ 2091 outputs: []outputInfo{ 2092 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2093 }, 2094 }, 2095 }, 2096 { 2097 name: "MOVSDconst", 2098 auxType: auxFloat64, 2099 argLen: 0, 2100 rematerializeable: true, 2101 asm: x86.AMOVSD, 2102 reg: regInfo{ 2103 outputs: []outputInfo{ 2104 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2105 }, 2106 }, 2107 }, 2108 { 2109 name: "MOVSSloadidx1", 2110 auxType: auxSymOff, 2111 argLen: 3, 2112 symEffect: SymRead, 2113 asm: x86.AMOVSS, 2114 reg: regInfo{ 2115 inputs: []inputInfo{ 2116 {1, 255}, // AX CX DX BX SP BP SI DI 2117 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2118 }, 2119 outputs: []outputInfo{ 2120 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2121 }, 2122 }, 2123 }, 2124 { 2125 name: "MOVSSloadidx4", 2126 auxType: auxSymOff, 2127 argLen: 3, 2128 symEffect: SymRead, 2129 asm: x86.AMOVSS, 2130 reg: regInfo{ 2131 inputs: []inputInfo{ 2132 {1, 255}, // AX CX DX BX SP BP SI DI 2133 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2134 }, 2135 outputs: []outputInfo{ 2136 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2137 }, 2138 }, 2139 }, 2140 { 2141 name: "MOVSDloadidx1", 2142 auxType: auxSymOff, 2143 argLen: 3, 2144 symEffect: SymRead, 2145 asm: x86.AMOVSD, 2146 reg: regInfo{ 2147 inputs: []inputInfo{ 2148 {1, 255}, // AX CX DX BX SP BP SI DI 2149 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2150 }, 2151 outputs: []outputInfo{ 2152 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2153 }, 2154 }, 2155 }, 2156 { 2157 name: "MOVSDloadidx8", 2158 auxType: auxSymOff, 2159 argLen: 3, 2160 symEffect: SymRead, 2161 asm: x86.AMOVSD, 2162 reg: regInfo{ 2163 inputs: []inputInfo{ 2164 {1, 255}, // AX CX DX BX SP BP SI DI 2165 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2166 }, 2167 outputs: []outputInfo{ 2168 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2169 }, 2170 }, 2171 }, 2172 { 2173 name: "MOVSSstore", 2174 auxType: auxSymOff, 2175 argLen: 3, 2176 faultOnNilArg0: true, 2177 symEffect: SymWrite, 2178 asm: x86.AMOVSS, 2179 reg: regInfo{ 2180 inputs: []inputInfo{ 2181 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2182 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2183 }, 2184 }, 2185 }, 2186 { 2187 name: "MOVSDstore", 2188 auxType: auxSymOff, 2189 argLen: 3, 2190 faultOnNilArg0: true, 2191 symEffect: SymWrite, 2192 asm: x86.AMOVSD, 2193 reg: regInfo{ 2194 inputs: []inputInfo{ 2195 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2196 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2197 }, 2198 }, 2199 }, 2200 { 2201 name: "MOVSSstoreidx1", 2202 auxType: auxSymOff, 2203 argLen: 4, 2204 symEffect: SymWrite, 2205 asm: x86.AMOVSS, 2206 reg: regInfo{ 2207 inputs: []inputInfo{ 2208 {1, 255}, // AX CX DX BX SP BP SI DI 2209 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2210 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2211 }, 2212 }, 2213 }, 2214 { 2215 name: "MOVSSstoreidx4", 2216 auxType: auxSymOff, 2217 argLen: 4, 2218 symEffect: SymWrite, 2219 asm: x86.AMOVSS, 2220 reg: regInfo{ 2221 inputs: []inputInfo{ 2222 {1, 255}, // AX CX DX BX SP BP SI DI 2223 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2224 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2225 }, 2226 }, 2227 }, 2228 { 2229 name: "MOVSDstoreidx1", 2230 auxType: auxSymOff, 2231 argLen: 4, 2232 symEffect: SymWrite, 2233 asm: x86.AMOVSD, 2234 reg: regInfo{ 2235 inputs: []inputInfo{ 2236 {1, 255}, // AX CX DX BX SP BP SI DI 2237 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2238 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2239 }, 2240 }, 2241 }, 2242 { 2243 name: "MOVSDstoreidx8", 2244 auxType: auxSymOff, 2245 argLen: 4, 2246 symEffect: SymWrite, 2247 asm: x86.AMOVSD, 2248 reg: regInfo{ 2249 inputs: []inputInfo{ 2250 {1, 255}, // AX CX DX BX SP BP SI DI 2251 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2252 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2253 }, 2254 }, 2255 }, 2256 { 2257 name: "ADDL", 2258 argLen: 2, 2259 commutative: true, 2260 clobberFlags: true, 2261 asm: x86.AADDL, 2262 reg: regInfo{ 2263 inputs: []inputInfo{ 2264 {1, 239}, // AX CX DX BX BP SI DI 2265 {0, 255}, // AX CX DX BX SP BP SI DI 2266 }, 2267 outputs: []outputInfo{ 2268 {0, 239}, // AX CX DX BX BP SI DI 2269 }, 2270 }, 2271 }, 2272 { 2273 name: "ADDLconst", 2274 auxType: auxInt32, 2275 argLen: 1, 2276 clobberFlags: true, 2277 asm: x86.AADDL, 2278 reg: regInfo{ 2279 inputs: []inputInfo{ 2280 {0, 255}, // AX CX DX BX SP BP SI DI 2281 }, 2282 outputs: []outputInfo{ 2283 {0, 239}, // AX CX DX BX BP SI DI 2284 }, 2285 }, 2286 }, 2287 { 2288 name: "ADDLcarry", 2289 argLen: 2, 2290 commutative: true, 2291 resultInArg0: true, 2292 asm: x86.AADDL, 2293 reg: regInfo{ 2294 inputs: []inputInfo{ 2295 {0, 239}, // AX CX DX BX BP SI DI 2296 {1, 239}, // AX CX DX BX BP SI DI 2297 }, 2298 outputs: []outputInfo{ 2299 {1, 0}, 2300 {0, 239}, // AX CX DX BX BP SI DI 2301 }, 2302 }, 2303 }, 2304 { 2305 name: "ADDLconstcarry", 2306 auxType: auxInt32, 2307 argLen: 1, 2308 resultInArg0: true, 2309 asm: x86.AADDL, 2310 reg: regInfo{ 2311 inputs: []inputInfo{ 2312 {0, 239}, // AX CX DX BX BP SI DI 2313 }, 2314 outputs: []outputInfo{ 2315 {1, 0}, 2316 {0, 239}, // AX CX DX BX BP SI DI 2317 }, 2318 }, 2319 }, 2320 { 2321 name: "ADCL", 2322 argLen: 3, 2323 commutative: true, 2324 resultInArg0: true, 2325 clobberFlags: true, 2326 asm: x86.AADCL, 2327 reg: regInfo{ 2328 inputs: []inputInfo{ 2329 {0, 239}, // AX CX DX BX BP SI DI 2330 {1, 239}, // AX CX DX BX BP SI DI 2331 }, 2332 outputs: []outputInfo{ 2333 {0, 239}, // AX CX DX BX BP SI DI 2334 }, 2335 }, 2336 }, 2337 { 2338 name: "ADCLconst", 2339 auxType: auxInt32, 2340 argLen: 2, 2341 resultInArg0: true, 2342 clobberFlags: true, 2343 asm: x86.AADCL, 2344 reg: regInfo{ 2345 inputs: []inputInfo{ 2346 {0, 239}, // AX CX DX BX BP SI DI 2347 }, 2348 outputs: []outputInfo{ 2349 {0, 239}, // AX CX DX BX BP SI DI 2350 }, 2351 }, 2352 }, 2353 { 2354 name: "SUBL", 2355 argLen: 2, 2356 resultInArg0: true, 2357 clobberFlags: true, 2358 asm: x86.ASUBL, 2359 reg: regInfo{ 2360 inputs: []inputInfo{ 2361 {0, 239}, // AX CX DX BX BP SI DI 2362 {1, 239}, // AX CX DX BX BP SI DI 2363 }, 2364 outputs: []outputInfo{ 2365 {0, 239}, // AX CX DX BX BP SI DI 2366 }, 2367 }, 2368 }, 2369 { 2370 name: "SUBLconst", 2371 auxType: auxInt32, 2372 argLen: 1, 2373 resultInArg0: true, 2374 clobberFlags: true, 2375 asm: x86.ASUBL, 2376 reg: regInfo{ 2377 inputs: []inputInfo{ 2378 {0, 239}, // AX CX DX BX BP SI DI 2379 }, 2380 outputs: []outputInfo{ 2381 {0, 239}, // AX CX DX BX BP SI DI 2382 }, 2383 }, 2384 }, 2385 { 2386 name: "SUBLcarry", 2387 argLen: 2, 2388 resultInArg0: true, 2389 asm: x86.ASUBL, 2390 reg: regInfo{ 2391 inputs: []inputInfo{ 2392 {0, 239}, // AX CX DX BX BP SI DI 2393 {1, 239}, // AX CX DX BX BP SI DI 2394 }, 2395 outputs: []outputInfo{ 2396 {1, 0}, 2397 {0, 239}, // AX CX DX BX BP SI DI 2398 }, 2399 }, 2400 }, 2401 { 2402 name: "SUBLconstcarry", 2403 auxType: auxInt32, 2404 argLen: 1, 2405 resultInArg0: true, 2406 asm: x86.ASUBL, 2407 reg: regInfo{ 2408 inputs: []inputInfo{ 2409 {0, 239}, // AX CX DX BX BP SI DI 2410 }, 2411 outputs: []outputInfo{ 2412 {1, 0}, 2413 {0, 239}, // AX CX DX BX BP SI DI 2414 }, 2415 }, 2416 }, 2417 { 2418 name: "SBBL", 2419 argLen: 3, 2420 resultInArg0: true, 2421 clobberFlags: true, 2422 asm: x86.ASBBL, 2423 reg: regInfo{ 2424 inputs: []inputInfo{ 2425 {0, 239}, // AX CX DX BX BP SI DI 2426 {1, 239}, // AX CX DX BX BP SI DI 2427 }, 2428 outputs: []outputInfo{ 2429 {0, 239}, // AX CX DX BX BP SI DI 2430 }, 2431 }, 2432 }, 2433 { 2434 name: "SBBLconst", 2435 auxType: auxInt32, 2436 argLen: 2, 2437 resultInArg0: true, 2438 clobberFlags: true, 2439 asm: x86.ASBBL, 2440 reg: regInfo{ 2441 inputs: []inputInfo{ 2442 {0, 239}, // AX CX DX BX BP SI DI 2443 }, 2444 outputs: []outputInfo{ 2445 {0, 239}, // AX CX DX BX BP SI DI 2446 }, 2447 }, 2448 }, 2449 { 2450 name: "MULL", 2451 argLen: 2, 2452 commutative: true, 2453 resultInArg0: true, 2454 clobberFlags: true, 2455 asm: x86.AIMULL, 2456 reg: regInfo{ 2457 inputs: []inputInfo{ 2458 {0, 239}, // AX CX DX BX BP SI DI 2459 {1, 239}, // AX CX DX BX BP SI DI 2460 }, 2461 outputs: []outputInfo{ 2462 {0, 239}, // AX CX DX BX BP SI DI 2463 }, 2464 }, 2465 }, 2466 { 2467 name: "MULLconst", 2468 auxType: auxInt32, 2469 argLen: 1, 2470 resultInArg0: true, 2471 clobberFlags: true, 2472 asm: x86.AIMULL, 2473 reg: regInfo{ 2474 inputs: []inputInfo{ 2475 {0, 239}, // AX CX DX BX BP SI DI 2476 }, 2477 outputs: []outputInfo{ 2478 {0, 239}, // AX CX DX BX BP SI DI 2479 }, 2480 }, 2481 }, 2482 { 2483 name: "HMULL", 2484 argLen: 2, 2485 commutative: true, 2486 clobberFlags: true, 2487 asm: x86.AIMULL, 2488 reg: regInfo{ 2489 inputs: []inputInfo{ 2490 {0, 1}, // AX 2491 {1, 255}, // AX CX DX BX SP BP SI DI 2492 }, 2493 clobbers: 1, // AX 2494 outputs: []outputInfo{ 2495 {0, 4}, // DX 2496 }, 2497 }, 2498 }, 2499 { 2500 name: "HMULLU", 2501 argLen: 2, 2502 commutative: true, 2503 clobberFlags: true, 2504 asm: x86.AMULL, 2505 reg: regInfo{ 2506 inputs: []inputInfo{ 2507 {0, 1}, // AX 2508 {1, 255}, // AX CX DX BX SP BP SI DI 2509 }, 2510 clobbers: 1, // AX 2511 outputs: []outputInfo{ 2512 {0, 4}, // DX 2513 }, 2514 }, 2515 }, 2516 { 2517 name: "MULLQU", 2518 argLen: 2, 2519 commutative: true, 2520 clobberFlags: true, 2521 asm: x86.AMULL, 2522 reg: regInfo{ 2523 inputs: []inputInfo{ 2524 {0, 1}, // AX 2525 {1, 255}, // AX CX DX BX SP BP SI DI 2526 }, 2527 outputs: []outputInfo{ 2528 {0, 4}, // DX 2529 {1, 1}, // AX 2530 }, 2531 }, 2532 }, 2533 { 2534 name: "AVGLU", 2535 argLen: 2, 2536 commutative: true, 2537 resultInArg0: true, 2538 clobberFlags: true, 2539 reg: regInfo{ 2540 inputs: []inputInfo{ 2541 {0, 239}, // AX CX DX BX BP SI DI 2542 {1, 239}, // AX CX DX BX BP SI DI 2543 }, 2544 outputs: []outputInfo{ 2545 {0, 239}, // AX CX DX BX BP SI DI 2546 }, 2547 }, 2548 }, 2549 { 2550 name: "DIVL", 2551 argLen: 2, 2552 clobberFlags: true, 2553 asm: x86.AIDIVL, 2554 reg: regInfo{ 2555 inputs: []inputInfo{ 2556 {0, 1}, // AX 2557 {1, 251}, // AX CX BX SP BP SI DI 2558 }, 2559 clobbers: 4, // DX 2560 outputs: []outputInfo{ 2561 {0, 1}, // AX 2562 }, 2563 }, 2564 }, 2565 { 2566 name: "DIVW", 2567 argLen: 2, 2568 clobberFlags: true, 2569 asm: x86.AIDIVW, 2570 reg: regInfo{ 2571 inputs: []inputInfo{ 2572 {0, 1}, // AX 2573 {1, 251}, // AX CX BX SP BP SI DI 2574 }, 2575 clobbers: 4, // DX 2576 outputs: []outputInfo{ 2577 {0, 1}, // AX 2578 }, 2579 }, 2580 }, 2581 { 2582 name: "DIVLU", 2583 argLen: 2, 2584 clobberFlags: true, 2585 asm: x86.ADIVL, 2586 reg: regInfo{ 2587 inputs: []inputInfo{ 2588 {0, 1}, // AX 2589 {1, 251}, // AX CX BX SP BP SI DI 2590 }, 2591 clobbers: 4, // DX 2592 outputs: []outputInfo{ 2593 {0, 1}, // AX 2594 }, 2595 }, 2596 }, 2597 { 2598 name: "DIVWU", 2599 argLen: 2, 2600 clobberFlags: true, 2601 asm: x86.ADIVW, 2602 reg: regInfo{ 2603 inputs: []inputInfo{ 2604 {0, 1}, // AX 2605 {1, 251}, // AX CX BX SP BP SI DI 2606 }, 2607 clobbers: 4, // DX 2608 outputs: []outputInfo{ 2609 {0, 1}, // AX 2610 }, 2611 }, 2612 }, 2613 { 2614 name: "MODL", 2615 argLen: 2, 2616 clobberFlags: true, 2617 asm: x86.AIDIVL, 2618 reg: regInfo{ 2619 inputs: []inputInfo{ 2620 {0, 1}, // AX 2621 {1, 251}, // AX CX BX SP BP SI DI 2622 }, 2623 clobbers: 1, // AX 2624 outputs: []outputInfo{ 2625 {0, 4}, // DX 2626 }, 2627 }, 2628 }, 2629 { 2630 name: "MODW", 2631 argLen: 2, 2632 clobberFlags: true, 2633 asm: x86.AIDIVW, 2634 reg: regInfo{ 2635 inputs: []inputInfo{ 2636 {0, 1}, // AX 2637 {1, 251}, // AX CX BX SP BP SI DI 2638 }, 2639 clobbers: 1, // AX 2640 outputs: []outputInfo{ 2641 {0, 4}, // DX 2642 }, 2643 }, 2644 }, 2645 { 2646 name: "MODLU", 2647 argLen: 2, 2648 clobberFlags: true, 2649 asm: x86.ADIVL, 2650 reg: regInfo{ 2651 inputs: []inputInfo{ 2652 {0, 1}, // AX 2653 {1, 251}, // AX CX BX SP BP SI DI 2654 }, 2655 clobbers: 1, // AX 2656 outputs: []outputInfo{ 2657 {0, 4}, // DX 2658 }, 2659 }, 2660 }, 2661 { 2662 name: "MODWU", 2663 argLen: 2, 2664 clobberFlags: true, 2665 asm: x86.ADIVW, 2666 reg: regInfo{ 2667 inputs: []inputInfo{ 2668 {0, 1}, // AX 2669 {1, 251}, // AX CX BX SP BP SI DI 2670 }, 2671 clobbers: 1, // AX 2672 outputs: []outputInfo{ 2673 {0, 4}, // DX 2674 }, 2675 }, 2676 }, 2677 { 2678 name: "ANDL", 2679 argLen: 2, 2680 commutative: true, 2681 resultInArg0: true, 2682 clobberFlags: true, 2683 asm: x86.AANDL, 2684 reg: regInfo{ 2685 inputs: []inputInfo{ 2686 {0, 239}, // AX CX DX BX BP SI DI 2687 {1, 239}, // AX CX DX BX BP SI DI 2688 }, 2689 outputs: []outputInfo{ 2690 {0, 239}, // AX CX DX BX BP SI DI 2691 }, 2692 }, 2693 }, 2694 { 2695 name: "ANDLconst", 2696 auxType: auxInt32, 2697 argLen: 1, 2698 resultInArg0: true, 2699 clobberFlags: true, 2700 asm: x86.AANDL, 2701 reg: regInfo{ 2702 inputs: []inputInfo{ 2703 {0, 239}, // AX CX DX BX BP SI DI 2704 }, 2705 outputs: []outputInfo{ 2706 {0, 239}, // AX CX DX BX BP SI DI 2707 }, 2708 }, 2709 }, 2710 { 2711 name: "ORL", 2712 argLen: 2, 2713 commutative: true, 2714 resultInArg0: true, 2715 clobberFlags: true, 2716 asm: x86.AORL, 2717 reg: regInfo{ 2718 inputs: []inputInfo{ 2719 {0, 239}, // AX CX DX BX BP SI DI 2720 {1, 239}, // AX CX DX BX BP SI DI 2721 }, 2722 outputs: []outputInfo{ 2723 {0, 239}, // AX CX DX BX BP SI DI 2724 }, 2725 }, 2726 }, 2727 { 2728 name: "ORLconst", 2729 auxType: auxInt32, 2730 argLen: 1, 2731 resultInArg0: true, 2732 clobberFlags: true, 2733 asm: x86.AORL, 2734 reg: regInfo{ 2735 inputs: []inputInfo{ 2736 {0, 239}, // AX CX DX BX BP SI DI 2737 }, 2738 outputs: []outputInfo{ 2739 {0, 239}, // AX CX DX BX BP SI DI 2740 }, 2741 }, 2742 }, 2743 { 2744 name: "XORL", 2745 argLen: 2, 2746 commutative: true, 2747 resultInArg0: true, 2748 clobberFlags: true, 2749 asm: x86.AXORL, 2750 reg: regInfo{ 2751 inputs: []inputInfo{ 2752 {0, 239}, // AX CX DX BX BP SI DI 2753 {1, 239}, // AX CX DX BX BP SI DI 2754 }, 2755 outputs: []outputInfo{ 2756 {0, 239}, // AX CX DX BX BP SI DI 2757 }, 2758 }, 2759 }, 2760 { 2761 name: "XORLconst", 2762 auxType: auxInt32, 2763 argLen: 1, 2764 resultInArg0: true, 2765 clobberFlags: true, 2766 asm: x86.AXORL, 2767 reg: regInfo{ 2768 inputs: []inputInfo{ 2769 {0, 239}, // AX CX DX BX BP SI DI 2770 }, 2771 outputs: []outputInfo{ 2772 {0, 239}, // AX CX DX BX BP SI DI 2773 }, 2774 }, 2775 }, 2776 { 2777 name: "CMPL", 2778 argLen: 2, 2779 asm: x86.ACMPL, 2780 reg: regInfo{ 2781 inputs: []inputInfo{ 2782 {0, 255}, // AX CX DX BX SP BP SI DI 2783 {1, 255}, // AX CX DX BX SP BP SI DI 2784 }, 2785 }, 2786 }, 2787 { 2788 name: "CMPW", 2789 argLen: 2, 2790 asm: x86.ACMPW, 2791 reg: regInfo{ 2792 inputs: []inputInfo{ 2793 {0, 255}, // AX CX DX BX SP BP SI DI 2794 {1, 255}, // AX CX DX BX SP BP SI DI 2795 }, 2796 }, 2797 }, 2798 { 2799 name: "CMPB", 2800 argLen: 2, 2801 asm: x86.ACMPB, 2802 reg: regInfo{ 2803 inputs: []inputInfo{ 2804 {0, 255}, // AX CX DX BX SP BP SI DI 2805 {1, 255}, // AX CX DX BX SP BP SI DI 2806 }, 2807 }, 2808 }, 2809 { 2810 name: "CMPLconst", 2811 auxType: auxInt32, 2812 argLen: 1, 2813 asm: x86.ACMPL, 2814 reg: regInfo{ 2815 inputs: []inputInfo{ 2816 {0, 255}, // AX CX DX BX SP BP SI DI 2817 }, 2818 }, 2819 }, 2820 { 2821 name: "CMPWconst", 2822 auxType: auxInt16, 2823 argLen: 1, 2824 asm: x86.ACMPW, 2825 reg: regInfo{ 2826 inputs: []inputInfo{ 2827 {0, 255}, // AX CX DX BX SP BP SI DI 2828 }, 2829 }, 2830 }, 2831 { 2832 name: "CMPBconst", 2833 auxType: auxInt8, 2834 argLen: 1, 2835 asm: x86.ACMPB, 2836 reg: regInfo{ 2837 inputs: []inputInfo{ 2838 {0, 255}, // AX CX DX BX SP BP SI DI 2839 }, 2840 }, 2841 }, 2842 { 2843 name: "UCOMISS", 2844 argLen: 2, 2845 usesScratch: true, 2846 asm: x86.AUCOMISS, 2847 reg: regInfo{ 2848 inputs: []inputInfo{ 2849 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2850 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2851 }, 2852 }, 2853 }, 2854 { 2855 name: "UCOMISD", 2856 argLen: 2, 2857 usesScratch: true, 2858 asm: x86.AUCOMISD, 2859 reg: regInfo{ 2860 inputs: []inputInfo{ 2861 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2862 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2863 }, 2864 }, 2865 }, 2866 { 2867 name: "TESTL", 2868 argLen: 2, 2869 commutative: true, 2870 asm: x86.ATESTL, 2871 reg: regInfo{ 2872 inputs: []inputInfo{ 2873 {0, 255}, // AX CX DX BX SP BP SI DI 2874 {1, 255}, // AX CX DX BX SP BP SI DI 2875 }, 2876 }, 2877 }, 2878 { 2879 name: "TESTW", 2880 argLen: 2, 2881 commutative: true, 2882 asm: x86.ATESTW, 2883 reg: regInfo{ 2884 inputs: []inputInfo{ 2885 {0, 255}, // AX CX DX BX SP BP SI DI 2886 {1, 255}, // AX CX DX BX SP BP SI DI 2887 }, 2888 }, 2889 }, 2890 { 2891 name: "TESTB", 2892 argLen: 2, 2893 commutative: true, 2894 asm: x86.ATESTB, 2895 reg: regInfo{ 2896 inputs: []inputInfo{ 2897 {0, 255}, // AX CX DX BX SP BP SI DI 2898 {1, 255}, // AX CX DX BX SP BP SI DI 2899 }, 2900 }, 2901 }, 2902 { 2903 name: "TESTLconst", 2904 auxType: auxInt32, 2905 argLen: 1, 2906 asm: x86.ATESTL, 2907 reg: regInfo{ 2908 inputs: []inputInfo{ 2909 {0, 255}, // AX CX DX BX SP BP SI DI 2910 }, 2911 }, 2912 }, 2913 { 2914 name: "TESTWconst", 2915 auxType: auxInt16, 2916 argLen: 1, 2917 asm: x86.ATESTW, 2918 reg: regInfo{ 2919 inputs: []inputInfo{ 2920 {0, 255}, // AX CX DX BX SP BP SI DI 2921 }, 2922 }, 2923 }, 2924 { 2925 name: "TESTBconst", 2926 auxType: auxInt8, 2927 argLen: 1, 2928 asm: x86.ATESTB, 2929 reg: regInfo{ 2930 inputs: []inputInfo{ 2931 {0, 255}, // AX CX DX BX SP BP SI DI 2932 }, 2933 }, 2934 }, 2935 { 2936 name: "SHLL", 2937 argLen: 2, 2938 resultInArg0: true, 2939 clobberFlags: true, 2940 asm: x86.ASHLL, 2941 reg: regInfo{ 2942 inputs: []inputInfo{ 2943 {1, 2}, // CX 2944 {0, 239}, // AX CX DX BX BP SI DI 2945 }, 2946 outputs: []outputInfo{ 2947 {0, 239}, // AX CX DX BX BP SI DI 2948 }, 2949 }, 2950 }, 2951 { 2952 name: "SHLLconst", 2953 auxType: auxInt32, 2954 argLen: 1, 2955 resultInArg0: true, 2956 clobberFlags: true, 2957 asm: x86.ASHLL, 2958 reg: regInfo{ 2959 inputs: []inputInfo{ 2960 {0, 239}, // AX CX DX BX BP SI DI 2961 }, 2962 outputs: []outputInfo{ 2963 {0, 239}, // AX CX DX BX BP SI DI 2964 }, 2965 }, 2966 }, 2967 { 2968 name: "SHRL", 2969 argLen: 2, 2970 resultInArg0: true, 2971 clobberFlags: true, 2972 asm: x86.ASHRL, 2973 reg: regInfo{ 2974 inputs: []inputInfo{ 2975 {1, 2}, // CX 2976 {0, 239}, // AX CX DX BX BP SI DI 2977 }, 2978 outputs: []outputInfo{ 2979 {0, 239}, // AX CX DX BX BP SI DI 2980 }, 2981 }, 2982 }, 2983 { 2984 name: "SHRW", 2985 argLen: 2, 2986 resultInArg0: true, 2987 clobberFlags: true, 2988 asm: x86.ASHRW, 2989 reg: regInfo{ 2990 inputs: []inputInfo{ 2991 {1, 2}, // CX 2992 {0, 239}, // AX CX DX BX BP SI DI 2993 }, 2994 outputs: []outputInfo{ 2995 {0, 239}, // AX CX DX BX BP SI DI 2996 }, 2997 }, 2998 }, 2999 { 3000 name: "SHRB", 3001 argLen: 2, 3002 resultInArg0: true, 3003 clobberFlags: true, 3004 asm: x86.ASHRB, 3005 reg: regInfo{ 3006 inputs: []inputInfo{ 3007 {1, 2}, // CX 3008 {0, 239}, // AX CX DX BX BP SI DI 3009 }, 3010 outputs: []outputInfo{ 3011 {0, 239}, // AX CX DX BX BP SI DI 3012 }, 3013 }, 3014 }, 3015 { 3016 name: "SHRLconst", 3017 auxType: auxInt32, 3018 argLen: 1, 3019 resultInArg0: true, 3020 clobberFlags: true, 3021 asm: x86.ASHRL, 3022 reg: regInfo{ 3023 inputs: []inputInfo{ 3024 {0, 239}, // AX CX DX BX BP SI DI 3025 }, 3026 outputs: []outputInfo{ 3027 {0, 239}, // AX CX DX BX BP SI DI 3028 }, 3029 }, 3030 }, 3031 { 3032 name: "SHRWconst", 3033 auxType: auxInt16, 3034 argLen: 1, 3035 resultInArg0: true, 3036 clobberFlags: true, 3037 asm: x86.ASHRW, 3038 reg: regInfo{ 3039 inputs: []inputInfo{ 3040 {0, 239}, // AX CX DX BX BP SI DI 3041 }, 3042 outputs: []outputInfo{ 3043 {0, 239}, // AX CX DX BX BP SI DI 3044 }, 3045 }, 3046 }, 3047 { 3048 name: "SHRBconst", 3049 auxType: auxInt8, 3050 argLen: 1, 3051 resultInArg0: true, 3052 clobberFlags: true, 3053 asm: x86.ASHRB, 3054 reg: regInfo{ 3055 inputs: []inputInfo{ 3056 {0, 239}, // AX CX DX BX BP SI DI 3057 }, 3058 outputs: []outputInfo{ 3059 {0, 239}, // AX CX DX BX BP SI DI 3060 }, 3061 }, 3062 }, 3063 { 3064 name: "SARL", 3065 argLen: 2, 3066 resultInArg0: true, 3067 clobberFlags: true, 3068 asm: x86.ASARL, 3069 reg: regInfo{ 3070 inputs: []inputInfo{ 3071 {1, 2}, // CX 3072 {0, 239}, // AX CX DX BX BP SI DI 3073 }, 3074 outputs: []outputInfo{ 3075 {0, 239}, // AX CX DX BX BP SI DI 3076 }, 3077 }, 3078 }, 3079 { 3080 name: "SARW", 3081 argLen: 2, 3082 resultInArg0: true, 3083 clobberFlags: true, 3084 asm: x86.ASARW, 3085 reg: regInfo{ 3086 inputs: []inputInfo{ 3087 {1, 2}, // CX 3088 {0, 239}, // AX CX DX BX BP SI DI 3089 }, 3090 outputs: []outputInfo{ 3091 {0, 239}, // AX CX DX BX BP SI DI 3092 }, 3093 }, 3094 }, 3095 { 3096 name: "SARB", 3097 argLen: 2, 3098 resultInArg0: true, 3099 clobberFlags: true, 3100 asm: x86.ASARB, 3101 reg: regInfo{ 3102 inputs: []inputInfo{ 3103 {1, 2}, // CX 3104 {0, 239}, // AX CX DX BX BP SI DI 3105 }, 3106 outputs: []outputInfo{ 3107 {0, 239}, // AX CX DX BX BP SI DI 3108 }, 3109 }, 3110 }, 3111 { 3112 name: "SARLconst", 3113 auxType: auxInt32, 3114 argLen: 1, 3115 resultInArg0: true, 3116 clobberFlags: true, 3117 asm: x86.ASARL, 3118 reg: regInfo{ 3119 inputs: []inputInfo{ 3120 {0, 239}, // AX CX DX BX BP SI DI 3121 }, 3122 outputs: []outputInfo{ 3123 {0, 239}, // AX CX DX BX BP SI DI 3124 }, 3125 }, 3126 }, 3127 { 3128 name: "SARWconst", 3129 auxType: auxInt16, 3130 argLen: 1, 3131 resultInArg0: true, 3132 clobberFlags: true, 3133 asm: x86.ASARW, 3134 reg: regInfo{ 3135 inputs: []inputInfo{ 3136 {0, 239}, // AX CX DX BX BP SI DI 3137 }, 3138 outputs: []outputInfo{ 3139 {0, 239}, // AX CX DX BX BP SI DI 3140 }, 3141 }, 3142 }, 3143 { 3144 name: "SARBconst", 3145 auxType: auxInt8, 3146 argLen: 1, 3147 resultInArg0: true, 3148 clobberFlags: true, 3149 asm: x86.ASARB, 3150 reg: regInfo{ 3151 inputs: []inputInfo{ 3152 {0, 239}, // AX CX DX BX BP SI DI 3153 }, 3154 outputs: []outputInfo{ 3155 {0, 239}, // AX CX DX BX BP SI DI 3156 }, 3157 }, 3158 }, 3159 { 3160 name: "ROLLconst", 3161 auxType: auxInt32, 3162 argLen: 1, 3163 resultInArg0: true, 3164 clobberFlags: true, 3165 asm: x86.AROLL, 3166 reg: regInfo{ 3167 inputs: []inputInfo{ 3168 {0, 239}, // AX CX DX BX BP SI DI 3169 }, 3170 outputs: []outputInfo{ 3171 {0, 239}, // AX CX DX BX BP SI DI 3172 }, 3173 }, 3174 }, 3175 { 3176 name: "ROLWconst", 3177 auxType: auxInt16, 3178 argLen: 1, 3179 resultInArg0: true, 3180 clobberFlags: true, 3181 asm: x86.AROLW, 3182 reg: regInfo{ 3183 inputs: []inputInfo{ 3184 {0, 239}, // AX CX DX BX BP SI DI 3185 }, 3186 outputs: []outputInfo{ 3187 {0, 239}, // AX CX DX BX BP SI DI 3188 }, 3189 }, 3190 }, 3191 { 3192 name: "ROLBconst", 3193 auxType: auxInt8, 3194 argLen: 1, 3195 resultInArg0: true, 3196 clobberFlags: true, 3197 asm: x86.AROLB, 3198 reg: regInfo{ 3199 inputs: []inputInfo{ 3200 {0, 239}, // AX CX DX BX BP SI DI 3201 }, 3202 outputs: []outputInfo{ 3203 {0, 239}, // AX CX DX BX BP SI DI 3204 }, 3205 }, 3206 }, 3207 { 3208 name: "NEGL", 3209 argLen: 1, 3210 resultInArg0: true, 3211 clobberFlags: true, 3212 asm: x86.ANEGL, 3213 reg: regInfo{ 3214 inputs: []inputInfo{ 3215 {0, 239}, // AX CX DX BX BP SI DI 3216 }, 3217 outputs: []outputInfo{ 3218 {0, 239}, // AX CX DX BX BP SI DI 3219 }, 3220 }, 3221 }, 3222 { 3223 name: "NOTL", 3224 argLen: 1, 3225 resultInArg0: true, 3226 clobberFlags: true, 3227 asm: x86.ANOTL, 3228 reg: regInfo{ 3229 inputs: []inputInfo{ 3230 {0, 239}, // AX CX DX BX BP SI DI 3231 }, 3232 outputs: []outputInfo{ 3233 {0, 239}, // AX CX DX BX BP SI DI 3234 }, 3235 }, 3236 }, 3237 { 3238 name: "BSFL", 3239 argLen: 1, 3240 clobberFlags: true, 3241 asm: x86.ABSFL, 3242 reg: regInfo{ 3243 inputs: []inputInfo{ 3244 {0, 239}, // AX CX DX BX BP SI DI 3245 }, 3246 outputs: []outputInfo{ 3247 {0, 239}, // AX CX DX BX BP SI DI 3248 }, 3249 }, 3250 }, 3251 { 3252 name: "BSFW", 3253 argLen: 1, 3254 clobberFlags: true, 3255 asm: x86.ABSFW, 3256 reg: regInfo{ 3257 inputs: []inputInfo{ 3258 {0, 239}, // AX CX DX BX BP SI DI 3259 }, 3260 outputs: []outputInfo{ 3261 {0, 239}, // AX CX DX BX BP SI DI 3262 }, 3263 }, 3264 }, 3265 { 3266 name: "BSRL", 3267 argLen: 1, 3268 clobberFlags: true, 3269 asm: x86.ABSRL, 3270 reg: regInfo{ 3271 inputs: []inputInfo{ 3272 {0, 239}, // AX CX DX BX BP SI DI 3273 }, 3274 outputs: []outputInfo{ 3275 {0, 239}, // AX CX DX BX BP SI DI 3276 }, 3277 }, 3278 }, 3279 { 3280 name: "BSRW", 3281 argLen: 1, 3282 clobberFlags: true, 3283 asm: x86.ABSRW, 3284 reg: regInfo{ 3285 inputs: []inputInfo{ 3286 {0, 239}, // AX CX DX BX BP SI DI 3287 }, 3288 outputs: []outputInfo{ 3289 {0, 239}, // AX CX DX BX BP SI DI 3290 }, 3291 }, 3292 }, 3293 { 3294 name: "BSWAPL", 3295 argLen: 1, 3296 resultInArg0: true, 3297 clobberFlags: true, 3298 asm: x86.ABSWAPL, 3299 reg: regInfo{ 3300 inputs: []inputInfo{ 3301 {0, 239}, // AX CX DX BX BP SI DI 3302 }, 3303 outputs: []outputInfo{ 3304 {0, 239}, // AX CX DX BX BP SI DI 3305 }, 3306 }, 3307 }, 3308 { 3309 name: "SQRTSD", 3310 argLen: 1, 3311 asm: x86.ASQRTSD, 3312 reg: regInfo{ 3313 inputs: []inputInfo{ 3314 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3315 }, 3316 outputs: []outputInfo{ 3317 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3318 }, 3319 }, 3320 }, 3321 { 3322 name: "SBBLcarrymask", 3323 argLen: 1, 3324 asm: x86.ASBBL, 3325 reg: regInfo{ 3326 outputs: []outputInfo{ 3327 {0, 239}, // AX CX DX BX BP SI DI 3328 }, 3329 }, 3330 }, 3331 { 3332 name: "SETEQ", 3333 argLen: 1, 3334 asm: x86.ASETEQ, 3335 reg: regInfo{ 3336 outputs: []outputInfo{ 3337 {0, 239}, // AX CX DX BX BP SI DI 3338 }, 3339 }, 3340 }, 3341 { 3342 name: "SETNE", 3343 argLen: 1, 3344 asm: x86.ASETNE, 3345 reg: regInfo{ 3346 outputs: []outputInfo{ 3347 {0, 239}, // AX CX DX BX BP SI DI 3348 }, 3349 }, 3350 }, 3351 { 3352 name: "SETL", 3353 argLen: 1, 3354 asm: x86.ASETLT, 3355 reg: regInfo{ 3356 outputs: []outputInfo{ 3357 {0, 239}, // AX CX DX BX BP SI DI 3358 }, 3359 }, 3360 }, 3361 { 3362 name: "SETLE", 3363 argLen: 1, 3364 asm: x86.ASETLE, 3365 reg: regInfo{ 3366 outputs: []outputInfo{ 3367 {0, 239}, // AX CX DX BX BP SI DI 3368 }, 3369 }, 3370 }, 3371 { 3372 name: "SETG", 3373 argLen: 1, 3374 asm: x86.ASETGT, 3375 reg: regInfo{ 3376 outputs: []outputInfo{ 3377 {0, 239}, // AX CX DX BX BP SI DI 3378 }, 3379 }, 3380 }, 3381 { 3382 name: "SETGE", 3383 argLen: 1, 3384 asm: x86.ASETGE, 3385 reg: regInfo{ 3386 outputs: []outputInfo{ 3387 {0, 239}, // AX CX DX BX BP SI DI 3388 }, 3389 }, 3390 }, 3391 { 3392 name: "SETB", 3393 argLen: 1, 3394 asm: x86.ASETCS, 3395 reg: regInfo{ 3396 outputs: []outputInfo{ 3397 {0, 239}, // AX CX DX BX BP SI DI 3398 }, 3399 }, 3400 }, 3401 { 3402 name: "SETBE", 3403 argLen: 1, 3404 asm: x86.ASETLS, 3405 reg: regInfo{ 3406 outputs: []outputInfo{ 3407 {0, 239}, // AX CX DX BX BP SI DI 3408 }, 3409 }, 3410 }, 3411 { 3412 name: "SETA", 3413 argLen: 1, 3414 asm: x86.ASETHI, 3415 reg: regInfo{ 3416 outputs: []outputInfo{ 3417 {0, 239}, // AX CX DX BX BP SI DI 3418 }, 3419 }, 3420 }, 3421 { 3422 name: "SETAE", 3423 argLen: 1, 3424 asm: x86.ASETCC, 3425 reg: regInfo{ 3426 outputs: []outputInfo{ 3427 {0, 239}, // AX CX DX BX BP SI DI 3428 }, 3429 }, 3430 }, 3431 { 3432 name: "SETEQF", 3433 argLen: 1, 3434 clobberFlags: true, 3435 asm: x86.ASETEQ, 3436 reg: regInfo{ 3437 clobbers: 1, // AX 3438 outputs: []outputInfo{ 3439 {0, 238}, // CX DX BX BP SI DI 3440 }, 3441 }, 3442 }, 3443 { 3444 name: "SETNEF", 3445 argLen: 1, 3446 clobberFlags: true, 3447 asm: x86.ASETNE, 3448 reg: regInfo{ 3449 clobbers: 1, // AX 3450 outputs: []outputInfo{ 3451 {0, 238}, // CX DX BX BP SI DI 3452 }, 3453 }, 3454 }, 3455 { 3456 name: "SETORD", 3457 argLen: 1, 3458 asm: x86.ASETPC, 3459 reg: regInfo{ 3460 outputs: []outputInfo{ 3461 {0, 239}, // AX CX DX BX BP SI DI 3462 }, 3463 }, 3464 }, 3465 { 3466 name: "SETNAN", 3467 argLen: 1, 3468 asm: x86.ASETPS, 3469 reg: regInfo{ 3470 outputs: []outputInfo{ 3471 {0, 239}, // AX CX DX BX BP SI DI 3472 }, 3473 }, 3474 }, 3475 { 3476 name: "SETGF", 3477 argLen: 1, 3478 asm: x86.ASETHI, 3479 reg: regInfo{ 3480 outputs: []outputInfo{ 3481 {0, 239}, // AX CX DX BX BP SI DI 3482 }, 3483 }, 3484 }, 3485 { 3486 name: "SETGEF", 3487 argLen: 1, 3488 asm: x86.ASETCC, 3489 reg: regInfo{ 3490 outputs: []outputInfo{ 3491 {0, 239}, // AX CX DX BX BP SI DI 3492 }, 3493 }, 3494 }, 3495 { 3496 name: "MOVBLSX", 3497 argLen: 1, 3498 asm: x86.AMOVBLSX, 3499 reg: regInfo{ 3500 inputs: []inputInfo{ 3501 {0, 239}, // AX CX DX BX BP SI DI 3502 }, 3503 outputs: []outputInfo{ 3504 {0, 239}, // AX CX DX BX BP SI DI 3505 }, 3506 }, 3507 }, 3508 { 3509 name: "MOVBLZX", 3510 argLen: 1, 3511 asm: x86.AMOVBLZX, 3512 reg: regInfo{ 3513 inputs: []inputInfo{ 3514 {0, 239}, // AX CX DX BX BP SI DI 3515 }, 3516 outputs: []outputInfo{ 3517 {0, 239}, // AX CX DX BX BP SI DI 3518 }, 3519 }, 3520 }, 3521 { 3522 name: "MOVWLSX", 3523 argLen: 1, 3524 asm: x86.AMOVWLSX, 3525 reg: regInfo{ 3526 inputs: []inputInfo{ 3527 {0, 239}, // AX CX DX BX BP SI DI 3528 }, 3529 outputs: []outputInfo{ 3530 {0, 239}, // AX CX DX BX BP SI DI 3531 }, 3532 }, 3533 }, 3534 { 3535 name: "MOVWLZX", 3536 argLen: 1, 3537 asm: x86.AMOVWLZX, 3538 reg: regInfo{ 3539 inputs: []inputInfo{ 3540 {0, 239}, // AX CX DX BX BP SI DI 3541 }, 3542 outputs: []outputInfo{ 3543 {0, 239}, // AX CX DX BX BP SI DI 3544 }, 3545 }, 3546 }, 3547 { 3548 name: "MOVLconst", 3549 auxType: auxInt32, 3550 argLen: 0, 3551 rematerializeable: true, 3552 asm: x86.AMOVL, 3553 reg: regInfo{ 3554 outputs: []outputInfo{ 3555 {0, 239}, // AX CX DX BX BP SI DI 3556 }, 3557 }, 3558 }, 3559 { 3560 name: "CVTTSD2SL", 3561 argLen: 1, 3562 usesScratch: true, 3563 asm: x86.ACVTTSD2SL, 3564 reg: regInfo{ 3565 inputs: []inputInfo{ 3566 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3567 }, 3568 outputs: []outputInfo{ 3569 {0, 239}, // AX CX DX BX BP SI DI 3570 }, 3571 }, 3572 }, 3573 { 3574 name: "CVTTSS2SL", 3575 argLen: 1, 3576 usesScratch: true, 3577 asm: x86.ACVTTSS2SL, 3578 reg: regInfo{ 3579 inputs: []inputInfo{ 3580 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3581 }, 3582 outputs: []outputInfo{ 3583 {0, 239}, // AX CX DX BX BP SI DI 3584 }, 3585 }, 3586 }, 3587 { 3588 name: "CVTSL2SS", 3589 argLen: 1, 3590 usesScratch: true, 3591 asm: x86.ACVTSL2SS, 3592 reg: regInfo{ 3593 inputs: []inputInfo{ 3594 {0, 239}, // AX CX DX BX BP SI DI 3595 }, 3596 outputs: []outputInfo{ 3597 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3598 }, 3599 }, 3600 }, 3601 { 3602 name: "CVTSL2SD", 3603 argLen: 1, 3604 usesScratch: true, 3605 asm: x86.ACVTSL2SD, 3606 reg: regInfo{ 3607 inputs: []inputInfo{ 3608 {0, 239}, // AX CX DX BX BP SI DI 3609 }, 3610 outputs: []outputInfo{ 3611 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3612 }, 3613 }, 3614 }, 3615 { 3616 name: "CVTSD2SS", 3617 argLen: 1, 3618 usesScratch: true, 3619 asm: x86.ACVTSD2SS, 3620 reg: regInfo{ 3621 inputs: []inputInfo{ 3622 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3623 }, 3624 outputs: []outputInfo{ 3625 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3626 }, 3627 }, 3628 }, 3629 { 3630 name: "CVTSS2SD", 3631 argLen: 1, 3632 asm: x86.ACVTSS2SD, 3633 reg: regInfo{ 3634 inputs: []inputInfo{ 3635 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3636 }, 3637 outputs: []outputInfo{ 3638 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3639 }, 3640 }, 3641 }, 3642 { 3643 name: "PXOR", 3644 argLen: 2, 3645 commutative: true, 3646 resultInArg0: true, 3647 asm: x86.APXOR, 3648 reg: regInfo{ 3649 inputs: []inputInfo{ 3650 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3651 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3652 }, 3653 outputs: []outputInfo{ 3654 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3655 }, 3656 }, 3657 }, 3658 { 3659 name: "LEAL", 3660 auxType: auxSymOff, 3661 argLen: 1, 3662 rematerializeable: true, 3663 symEffect: SymAddr, 3664 reg: regInfo{ 3665 inputs: []inputInfo{ 3666 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3667 }, 3668 outputs: []outputInfo{ 3669 {0, 239}, // AX CX DX BX BP SI DI 3670 }, 3671 }, 3672 }, 3673 { 3674 name: "LEAL1", 3675 auxType: auxSymOff, 3676 argLen: 2, 3677 commutative: true, 3678 symEffect: SymAddr, 3679 reg: regInfo{ 3680 inputs: []inputInfo{ 3681 {1, 255}, // AX CX DX BX SP BP SI DI 3682 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3683 }, 3684 outputs: []outputInfo{ 3685 {0, 239}, // AX CX DX BX BP SI DI 3686 }, 3687 }, 3688 }, 3689 { 3690 name: "LEAL2", 3691 auxType: auxSymOff, 3692 argLen: 2, 3693 symEffect: SymAddr, 3694 reg: regInfo{ 3695 inputs: []inputInfo{ 3696 {1, 255}, // AX CX DX BX SP BP SI DI 3697 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3698 }, 3699 outputs: []outputInfo{ 3700 {0, 239}, // AX CX DX BX BP SI DI 3701 }, 3702 }, 3703 }, 3704 { 3705 name: "LEAL4", 3706 auxType: auxSymOff, 3707 argLen: 2, 3708 symEffect: SymAddr, 3709 reg: regInfo{ 3710 inputs: []inputInfo{ 3711 {1, 255}, // AX CX DX BX SP BP SI DI 3712 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3713 }, 3714 outputs: []outputInfo{ 3715 {0, 239}, // AX CX DX BX BP SI DI 3716 }, 3717 }, 3718 }, 3719 { 3720 name: "LEAL8", 3721 auxType: auxSymOff, 3722 argLen: 2, 3723 symEffect: SymAddr, 3724 reg: regInfo{ 3725 inputs: []inputInfo{ 3726 {1, 255}, // AX CX DX BX SP BP SI DI 3727 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3728 }, 3729 outputs: []outputInfo{ 3730 {0, 239}, // AX CX DX BX BP SI DI 3731 }, 3732 }, 3733 }, 3734 { 3735 name: "MOVBload", 3736 auxType: auxSymOff, 3737 argLen: 2, 3738 faultOnNilArg0: true, 3739 symEffect: SymRead, 3740 asm: x86.AMOVBLZX, 3741 reg: regInfo{ 3742 inputs: []inputInfo{ 3743 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3744 }, 3745 outputs: []outputInfo{ 3746 {0, 239}, // AX CX DX BX BP SI DI 3747 }, 3748 }, 3749 }, 3750 { 3751 name: "MOVBLSXload", 3752 auxType: auxSymOff, 3753 argLen: 2, 3754 faultOnNilArg0: true, 3755 symEffect: SymRead, 3756 asm: x86.AMOVBLSX, 3757 reg: regInfo{ 3758 inputs: []inputInfo{ 3759 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3760 }, 3761 outputs: []outputInfo{ 3762 {0, 239}, // AX CX DX BX BP SI DI 3763 }, 3764 }, 3765 }, 3766 { 3767 name: "MOVWload", 3768 auxType: auxSymOff, 3769 argLen: 2, 3770 faultOnNilArg0: true, 3771 symEffect: SymRead, 3772 asm: x86.AMOVWLZX, 3773 reg: regInfo{ 3774 inputs: []inputInfo{ 3775 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3776 }, 3777 outputs: []outputInfo{ 3778 {0, 239}, // AX CX DX BX BP SI DI 3779 }, 3780 }, 3781 }, 3782 { 3783 name: "MOVWLSXload", 3784 auxType: auxSymOff, 3785 argLen: 2, 3786 faultOnNilArg0: true, 3787 symEffect: SymRead, 3788 asm: x86.AMOVWLSX, 3789 reg: regInfo{ 3790 inputs: []inputInfo{ 3791 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3792 }, 3793 outputs: []outputInfo{ 3794 {0, 239}, // AX CX DX BX BP SI DI 3795 }, 3796 }, 3797 }, 3798 { 3799 name: "MOVLload", 3800 auxType: auxSymOff, 3801 argLen: 2, 3802 faultOnNilArg0: true, 3803 symEffect: SymRead, 3804 asm: x86.AMOVL, 3805 reg: regInfo{ 3806 inputs: []inputInfo{ 3807 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3808 }, 3809 outputs: []outputInfo{ 3810 {0, 239}, // AX CX DX BX BP SI DI 3811 }, 3812 }, 3813 }, 3814 { 3815 name: "MOVBstore", 3816 auxType: auxSymOff, 3817 argLen: 3, 3818 faultOnNilArg0: true, 3819 symEffect: SymWrite, 3820 asm: x86.AMOVB, 3821 reg: regInfo{ 3822 inputs: []inputInfo{ 3823 {1, 255}, // AX CX DX BX SP BP SI DI 3824 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3825 }, 3826 }, 3827 }, 3828 { 3829 name: "MOVWstore", 3830 auxType: auxSymOff, 3831 argLen: 3, 3832 faultOnNilArg0: true, 3833 symEffect: SymWrite, 3834 asm: x86.AMOVW, 3835 reg: regInfo{ 3836 inputs: []inputInfo{ 3837 {1, 255}, // AX CX DX BX SP BP SI DI 3838 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3839 }, 3840 }, 3841 }, 3842 { 3843 name: "MOVLstore", 3844 auxType: auxSymOff, 3845 argLen: 3, 3846 faultOnNilArg0: true, 3847 symEffect: SymWrite, 3848 asm: x86.AMOVL, 3849 reg: regInfo{ 3850 inputs: []inputInfo{ 3851 {1, 255}, // AX CX DX BX SP BP SI DI 3852 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3853 }, 3854 }, 3855 }, 3856 { 3857 name: "MOVBloadidx1", 3858 auxType: auxSymOff, 3859 argLen: 3, 3860 commutative: true, 3861 symEffect: SymRead, 3862 asm: x86.AMOVBLZX, 3863 reg: regInfo{ 3864 inputs: []inputInfo{ 3865 {1, 255}, // AX CX DX BX SP BP SI DI 3866 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3867 }, 3868 outputs: []outputInfo{ 3869 {0, 239}, // AX CX DX BX BP SI DI 3870 }, 3871 }, 3872 }, 3873 { 3874 name: "MOVWloadidx1", 3875 auxType: auxSymOff, 3876 argLen: 3, 3877 commutative: true, 3878 symEffect: SymRead, 3879 asm: x86.AMOVWLZX, 3880 reg: regInfo{ 3881 inputs: []inputInfo{ 3882 {1, 255}, // AX CX DX BX SP BP SI DI 3883 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3884 }, 3885 outputs: []outputInfo{ 3886 {0, 239}, // AX CX DX BX BP SI DI 3887 }, 3888 }, 3889 }, 3890 { 3891 name: "MOVWloadidx2", 3892 auxType: auxSymOff, 3893 argLen: 3, 3894 symEffect: SymRead, 3895 asm: x86.AMOVWLZX, 3896 reg: regInfo{ 3897 inputs: []inputInfo{ 3898 {1, 255}, // AX CX DX BX SP BP SI DI 3899 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3900 }, 3901 outputs: []outputInfo{ 3902 {0, 239}, // AX CX DX BX BP SI DI 3903 }, 3904 }, 3905 }, 3906 { 3907 name: "MOVLloadidx1", 3908 auxType: auxSymOff, 3909 argLen: 3, 3910 commutative: true, 3911 symEffect: SymRead, 3912 asm: x86.AMOVL, 3913 reg: regInfo{ 3914 inputs: []inputInfo{ 3915 {1, 255}, // AX CX DX BX SP BP SI DI 3916 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3917 }, 3918 outputs: []outputInfo{ 3919 {0, 239}, // AX CX DX BX BP SI DI 3920 }, 3921 }, 3922 }, 3923 { 3924 name: "MOVLloadidx4", 3925 auxType: auxSymOff, 3926 argLen: 3, 3927 symEffect: SymRead, 3928 asm: x86.AMOVL, 3929 reg: regInfo{ 3930 inputs: []inputInfo{ 3931 {1, 255}, // AX CX DX BX SP BP SI DI 3932 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3933 }, 3934 outputs: []outputInfo{ 3935 {0, 239}, // AX CX DX BX BP SI DI 3936 }, 3937 }, 3938 }, 3939 { 3940 name: "MOVBstoreidx1", 3941 auxType: auxSymOff, 3942 argLen: 4, 3943 commutative: true, 3944 symEffect: SymWrite, 3945 asm: x86.AMOVB, 3946 reg: regInfo{ 3947 inputs: []inputInfo{ 3948 {1, 255}, // AX CX DX BX SP BP SI DI 3949 {2, 255}, // AX CX DX BX SP BP SI DI 3950 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3951 }, 3952 }, 3953 }, 3954 { 3955 name: "MOVWstoreidx1", 3956 auxType: auxSymOff, 3957 argLen: 4, 3958 commutative: true, 3959 symEffect: SymWrite, 3960 asm: x86.AMOVW, 3961 reg: regInfo{ 3962 inputs: []inputInfo{ 3963 {1, 255}, // AX CX DX BX SP BP SI DI 3964 {2, 255}, // AX CX DX BX SP BP SI DI 3965 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3966 }, 3967 }, 3968 }, 3969 { 3970 name: "MOVWstoreidx2", 3971 auxType: auxSymOff, 3972 argLen: 4, 3973 symEffect: SymWrite, 3974 asm: x86.AMOVW, 3975 reg: regInfo{ 3976 inputs: []inputInfo{ 3977 {1, 255}, // AX CX DX BX SP BP SI DI 3978 {2, 255}, // AX CX DX BX SP BP SI DI 3979 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3980 }, 3981 }, 3982 }, 3983 { 3984 name: "MOVLstoreidx1", 3985 auxType: auxSymOff, 3986 argLen: 4, 3987 commutative: true, 3988 symEffect: SymWrite, 3989 asm: x86.AMOVL, 3990 reg: regInfo{ 3991 inputs: []inputInfo{ 3992 {1, 255}, // AX CX DX BX SP BP SI DI 3993 {2, 255}, // AX CX DX BX SP BP SI DI 3994 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3995 }, 3996 }, 3997 }, 3998 { 3999 name: "MOVLstoreidx4", 4000 auxType: auxSymOff, 4001 argLen: 4, 4002 symEffect: SymWrite, 4003 asm: x86.AMOVL, 4004 reg: regInfo{ 4005 inputs: []inputInfo{ 4006 {1, 255}, // AX CX DX BX SP BP SI DI 4007 {2, 255}, // AX CX DX BX SP BP SI DI 4008 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4009 }, 4010 }, 4011 }, 4012 { 4013 name: "MOVBstoreconst", 4014 auxType: auxSymValAndOff, 4015 argLen: 2, 4016 faultOnNilArg0: true, 4017 symEffect: SymWrite, 4018 asm: x86.AMOVB, 4019 reg: regInfo{ 4020 inputs: []inputInfo{ 4021 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4022 }, 4023 }, 4024 }, 4025 { 4026 name: "MOVWstoreconst", 4027 auxType: auxSymValAndOff, 4028 argLen: 2, 4029 faultOnNilArg0: true, 4030 symEffect: SymWrite, 4031 asm: x86.AMOVW, 4032 reg: regInfo{ 4033 inputs: []inputInfo{ 4034 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4035 }, 4036 }, 4037 }, 4038 { 4039 name: "MOVLstoreconst", 4040 auxType: auxSymValAndOff, 4041 argLen: 2, 4042 faultOnNilArg0: true, 4043 symEffect: SymWrite, 4044 asm: x86.AMOVL, 4045 reg: regInfo{ 4046 inputs: []inputInfo{ 4047 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4048 }, 4049 }, 4050 }, 4051 { 4052 name: "MOVBstoreconstidx1", 4053 auxType: auxSymValAndOff, 4054 argLen: 3, 4055 symEffect: SymWrite, 4056 asm: x86.AMOVB, 4057 reg: regInfo{ 4058 inputs: []inputInfo{ 4059 {1, 255}, // AX CX DX BX SP BP SI DI 4060 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4061 }, 4062 }, 4063 }, 4064 { 4065 name: "MOVWstoreconstidx1", 4066 auxType: auxSymValAndOff, 4067 argLen: 3, 4068 symEffect: SymWrite, 4069 asm: x86.AMOVW, 4070 reg: regInfo{ 4071 inputs: []inputInfo{ 4072 {1, 255}, // AX CX DX BX SP BP SI DI 4073 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4074 }, 4075 }, 4076 }, 4077 { 4078 name: "MOVWstoreconstidx2", 4079 auxType: auxSymValAndOff, 4080 argLen: 3, 4081 symEffect: SymWrite, 4082 asm: x86.AMOVW, 4083 reg: regInfo{ 4084 inputs: []inputInfo{ 4085 {1, 255}, // AX CX DX BX SP BP SI DI 4086 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4087 }, 4088 }, 4089 }, 4090 { 4091 name: "MOVLstoreconstidx1", 4092 auxType: auxSymValAndOff, 4093 argLen: 3, 4094 symEffect: SymWrite, 4095 asm: x86.AMOVL, 4096 reg: regInfo{ 4097 inputs: []inputInfo{ 4098 {1, 255}, // AX CX DX BX SP BP SI DI 4099 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4100 }, 4101 }, 4102 }, 4103 { 4104 name: "MOVLstoreconstidx4", 4105 auxType: auxSymValAndOff, 4106 argLen: 3, 4107 symEffect: SymWrite, 4108 asm: x86.AMOVL, 4109 reg: regInfo{ 4110 inputs: []inputInfo{ 4111 {1, 255}, // AX CX DX BX SP BP SI DI 4112 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4113 }, 4114 }, 4115 }, 4116 { 4117 name: "DUFFZERO", 4118 auxType: auxInt64, 4119 argLen: 3, 4120 faultOnNilArg0: true, 4121 reg: regInfo{ 4122 inputs: []inputInfo{ 4123 {0, 128}, // DI 4124 {1, 1}, // AX 4125 }, 4126 clobbers: 130, // CX DI 4127 }, 4128 }, 4129 { 4130 name: "REPSTOSL", 4131 argLen: 4, 4132 faultOnNilArg0: true, 4133 reg: regInfo{ 4134 inputs: []inputInfo{ 4135 {0, 128}, // DI 4136 {1, 2}, // CX 4137 {2, 1}, // AX 4138 }, 4139 clobbers: 130, // CX DI 4140 }, 4141 }, 4142 { 4143 name: "CALLstatic", 4144 auxType: auxSymOff, 4145 argLen: 1, 4146 clobberFlags: true, 4147 call: true, 4148 symEffect: SymNone, 4149 reg: regInfo{ 4150 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4151 }, 4152 }, 4153 { 4154 name: "CALLclosure", 4155 auxType: auxInt64, 4156 argLen: 3, 4157 clobberFlags: true, 4158 call: true, 4159 reg: regInfo{ 4160 inputs: []inputInfo{ 4161 {1, 4}, // DX 4162 {0, 255}, // AX CX DX BX SP BP SI DI 4163 }, 4164 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4165 }, 4166 }, 4167 { 4168 name: "CALLinter", 4169 auxType: auxInt64, 4170 argLen: 2, 4171 clobberFlags: true, 4172 call: true, 4173 reg: regInfo{ 4174 inputs: []inputInfo{ 4175 {0, 239}, // AX CX DX BX BP SI DI 4176 }, 4177 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4178 }, 4179 }, 4180 { 4181 name: "DUFFCOPY", 4182 auxType: auxInt64, 4183 argLen: 3, 4184 clobberFlags: true, 4185 faultOnNilArg0: true, 4186 faultOnNilArg1: true, 4187 reg: regInfo{ 4188 inputs: []inputInfo{ 4189 {0, 128}, // DI 4190 {1, 64}, // SI 4191 }, 4192 clobbers: 194, // CX SI DI 4193 }, 4194 }, 4195 { 4196 name: "REPMOVSL", 4197 argLen: 4, 4198 faultOnNilArg0: true, 4199 faultOnNilArg1: true, 4200 reg: regInfo{ 4201 inputs: []inputInfo{ 4202 {0, 128}, // DI 4203 {1, 64}, // SI 4204 {2, 2}, // CX 4205 }, 4206 clobbers: 194, // CX SI DI 4207 }, 4208 }, 4209 { 4210 name: "InvertFlags", 4211 argLen: 1, 4212 reg: regInfo{}, 4213 }, 4214 { 4215 name: "LoweredGetG", 4216 argLen: 1, 4217 reg: regInfo{ 4218 outputs: []outputInfo{ 4219 {0, 239}, // AX CX DX BX BP SI DI 4220 }, 4221 }, 4222 }, 4223 { 4224 name: "LoweredGetClosurePtr", 4225 argLen: 0, 4226 reg: regInfo{ 4227 outputs: []outputInfo{ 4228 {0, 4}, // DX 4229 }, 4230 }, 4231 }, 4232 { 4233 name: "LoweredNilCheck", 4234 argLen: 2, 4235 clobberFlags: true, 4236 nilCheck: true, 4237 faultOnNilArg0: true, 4238 reg: regInfo{ 4239 inputs: []inputInfo{ 4240 {0, 255}, // AX CX DX BX SP BP SI DI 4241 }, 4242 }, 4243 }, 4244 { 4245 name: "MOVLconvert", 4246 argLen: 2, 4247 asm: x86.AMOVL, 4248 reg: regInfo{ 4249 inputs: []inputInfo{ 4250 {0, 239}, // AX CX DX BX BP SI DI 4251 }, 4252 outputs: []outputInfo{ 4253 {0, 239}, // AX CX DX BX BP SI DI 4254 }, 4255 }, 4256 }, 4257 { 4258 name: "FlagEQ", 4259 argLen: 0, 4260 reg: regInfo{}, 4261 }, 4262 { 4263 name: "FlagLT_ULT", 4264 argLen: 0, 4265 reg: regInfo{}, 4266 }, 4267 { 4268 name: "FlagLT_UGT", 4269 argLen: 0, 4270 reg: regInfo{}, 4271 }, 4272 { 4273 name: "FlagGT_UGT", 4274 argLen: 0, 4275 reg: regInfo{}, 4276 }, 4277 { 4278 name: "FlagGT_ULT", 4279 argLen: 0, 4280 reg: regInfo{}, 4281 }, 4282 { 4283 name: "FCHS", 4284 argLen: 1, 4285 reg: regInfo{ 4286 inputs: []inputInfo{ 4287 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4288 }, 4289 outputs: []outputInfo{ 4290 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4291 }, 4292 }, 4293 }, 4294 { 4295 name: "MOVSSconst1", 4296 auxType: auxFloat32, 4297 argLen: 0, 4298 reg: regInfo{ 4299 outputs: []outputInfo{ 4300 {0, 239}, // AX CX DX BX BP SI DI 4301 }, 4302 }, 4303 }, 4304 { 4305 name: "MOVSDconst1", 4306 auxType: auxFloat64, 4307 argLen: 0, 4308 reg: regInfo{ 4309 outputs: []outputInfo{ 4310 {0, 239}, // AX CX DX BX BP SI DI 4311 }, 4312 }, 4313 }, 4314 { 4315 name: "MOVSSconst2", 4316 argLen: 1, 4317 asm: x86.AMOVSS, 4318 reg: regInfo{ 4319 inputs: []inputInfo{ 4320 {0, 239}, // AX CX DX BX BP SI DI 4321 }, 4322 outputs: []outputInfo{ 4323 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4324 }, 4325 }, 4326 }, 4327 { 4328 name: "MOVSDconst2", 4329 argLen: 1, 4330 asm: x86.AMOVSD, 4331 reg: regInfo{ 4332 inputs: []inputInfo{ 4333 {0, 239}, // AX CX DX BX BP SI DI 4334 }, 4335 outputs: []outputInfo{ 4336 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4337 }, 4338 }, 4339 }, 4340 4341 { 4342 name: "ADDSS", 4343 argLen: 2, 4344 commutative: true, 4345 resultInArg0: true, 4346 asm: x86.AADDSS, 4347 reg: regInfo{ 4348 inputs: []inputInfo{ 4349 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4350 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4351 }, 4352 outputs: []outputInfo{ 4353 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4354 }, 4355 }, 4356 }, 4357 { 4358 name: "ADDSD", 4359 argLen: 2, 4360 commutative: true, 4361 resultInArg0: true, 4362 asm: x86.AADDSD, 4363 reg: regInfo{ 4364 inputs: []inputInfo{ 4365 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4366 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4367 }, 4368 outputs: []outputInfo{ 4369 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4370 }, 4371 }, 4372 }, 4373 { 4374 name: "SUBSS", 4375 argLen: 2, 4376 resultInArg0: true, 4377 asm: x86.ASUBSS, 4378 reg: regInfo{ 4379 inputs: []inputInfo{ 4380 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4381 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4382 }, 4383 outputs: []outputInfo{ 4384 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4385 }, 4386 }, 4387 }, 4388 { 4389 name: "SUBSD", 4390 argLen: 2, 4391 resultInArg0: true, 4392 asm: x86.ASUBSD, 4393 reg: regInfo{ 4394 inputs: []inputInfo{ 4395 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4396 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4397 }, 4398 outputs: []outputInfo{ 4399 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4400 }, 4401 }, 4402 }, 4403 { 4404 name: "MULSS", 4405 argLen: 2, 4406 commutative: true, 4407 resultInArg0: true, 4408 asm: x86.AMULSS, 4409 reg: regInfo{ 4410 inputs: []inputInfo{ 4411 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4412 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4413 }, 4414 outputs: []outputInfo{ 4415 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4416 }, 4417 }, 4418 }, 4419 { 4420 name: "MULSD", 4421 argLen: 2, 4422 commutative: true, 4423 resultInArg0: true, 4424 asm: x86.AMULSD, 4425 reg: regInfo{ 4426 inputs: []inputInfo{ 4427 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4428 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4429 }, 4430 outputs: []outputInfo{ 4431 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4432 }, 4433 }, 4434 }, 4435 { 4436 name: "DIVSS", 4437 argLen: 2, 4438 resultInArg0: true, 4439 asm: x86.ADIVSS, 4440 reg: regInfo{ 4441 inputs: []inputInfo{ 4442 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4443 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4444 }, 4445 outputs: []outputInfo{ 4446 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4447 }, 4448 }, 4449 }, 4450 { 4451 name: "DIVSD", 4452 argLen: 2, 4453 resultInArg0: true, 4454 asm: x86.ADIVSD, 4455 reg: regInfo{ 4456 inputs: []inputInfo{ 4457 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4458 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4459 }, 4460 outputs: []outputInfo{ 4461 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4462 }, 4463 }, 4464 }, 4465 { 4466 name: "MOVSSload", 4467 auxType: auxSymOff, 4468 argLen: 2, 4469 faultOnNilArg0: true, 4470 symEffect: SymRead, 4471 asm: x86.AMOVSS, 4472 reg: regInfo{ 4473 inputs: []inputInfo{ 4474 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4475 }, 4476 outputs: []outputInfo{ 4477 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4478 }, 4479 }, 4480 }, 4481 { 4482 name: "MOVSDload", 4483 auxType: auxSymOff, 4484 argLen: 2, 4485 faultOnNilArg0: true, 4486 symEffect: SymRead, 4487 asm: x86.AMOVSD, 4488 reg: regInfo{ 4489 inputs: []inputInfo{ 4490 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4491 }, 4492 outputs: []outputInfo{ 4493 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4494 }, 4495 }, 4496 }, 4497 { 4498 name: "MOVSSconst", 4499 auxType: auxFloat32, 4500 argLen: 0, 4501 rematerializeable: true, 4502 asm: x86.AMOVSS, 4503 reg: regInfo{ 4504 outputs: []outputInfo{ 4505 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4506 }, 4507 }, 4508 }, 4509 { 4510 name: "MOVSDconst", 4511 auxType: auxFloat64, 4512 argLen: 0, 4513 rematerializeable: true, 4514 asm: x86.AMOVSD, 4515 reg: regInfo{ 4516 outputs: []outputInfo{ 4517 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4518 }, 4519 }, 4520 }, 4521 { 4522 name: "MOVSSloadidx1", 4523 auxType: auxSymOff, 4524 argLen: 3, 4525 symEffect: SymRead, 4526 asm: x86.AMOVSS, 4527 reg: regInfo{ 4528 inputs: []inputInfo{ 4529 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4530 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4531 }, 4532 outputs: []outputInfo{ 4533 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4534 }, 4535 }, 4536 }, 4537 { 4538 name: "MOVSSloadidx4", 4539 auxType: auxSymOff, 4540 argLen: 3, 4541 symEffect: SymRead, 4542 asm: x86.AMOVSS, 4543 reg: regInfo{ 4544 inputs: []inputInfo{ 4545 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4546 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4547 }, 4548 outputs: []outputInfo{ 4549 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4550 }, 4551 }, 4552 }, 4553 { 4554 name: "MOVSDloadidx1", 4555 auxType: auxSymOff, 4556 argLen: 3, 4557 symEffect: SymRead, 4558 asm: x86.AMOVSD, 4559 reg: regInfo{ 4560 inputs: []inputInfo{ 4561 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4562 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4563 }, 4564 outputs: []outputInfo{ 4565 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4566 }, 4567 }, 4568 }, 4569 { 4570 name: "MOVSDloadidx8", 4571 auxType: auxSymOff, 4572 argLen: 3, 4573 symEffect: SymRead, 4574 asm: x86.AMOVSD, 4575 reg: regInfo{ 4576 inputs: []inputInfo{ 4577 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4578 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4579 }, 4580 outputs: []outputInfo{ 4581 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4582 }, 4583 }, 4584 }, 4585 { 4586 name: "MOVSSstore", 4587 auxType: auxSymOff, 4588 argLen: 3, 4589 faultOnNilArg0: true, 4590 symEffect: SymWrite, 4591 asm: x86.AMOVSS, 4592 reg: regInfo{ 4593 inputs: []inputInfo{ 4594 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4595 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4596 }, 4597 }, 4598 }, 4599 { 4600 name: "MOVSDstore", 4601 auxType: auxSymOff, 4602 argLen: 3, 4603 faultOnNilArg0: true, 4604 symEffect: SymWrite, 4605 asm: x86.AMOVSD, 4606 reg: regInfo{ 4607 inputs: []inputInfo{ 4608 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4609 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4610 }, 4611 }, 4612 }, 4613 { 4614 name: "MOVSSstoreidx1", 4615 auxType: auxSymOff, 4616 argLen: 4, 4617 symEffect: SymWrite, 4618 asm: x86.AMOVSS, 4619 reg: regInfo{ 4620 inputs: []inputInfo{ 4621 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4622 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4623 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4624 }, 4625 }, 4626 }, 4627 { 4628 name: "MOVSSstoreidx4", 4629 auxType: auxSymOff, 4630 argLen: 4, 4631 symEffect: SymWrite, 4632 asm: x86.AMOVSS, 4633 reg: regInfo{ 4634 inputs: []inputInfo{ 4635 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4636 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4637 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4638 }, 4639 }, 4640 }, 4641 { 4642 name: "MOVSDstoreidx1", 4643 auxType: auxSymOff, 4644 argLen: 4, 4645 symEffect: SymWrite, 4646 asm: x86.AMOVSD, 4647 reg: regInfo{ 4648 inputs: []inputInfo{ 4649 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4650 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4651 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4652 }, 4653 }, 4654 }, 4655 { 4656 name: "MOVSDstoreidx8", 4657 auxType: auxSymOff, 4658 argLen: 4, 4659 symEffect: SymWrite, 4660 asm: x86.AMOVSD, 4661 reg: regInfo{ 4662 inputs: []inputInfo{ 4663 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4664 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4665 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4666 }, 4667 }, 4668 }, 4669 { 4670 name: "ADDSDmem", 4671 auxType: auxSymOff, 4672 argLen: 3, 4673 resultInArg0: true, 4674 faultOnNilArg1: true, 4675 symEffect: SymRead, 4676 asm: x86.AADDSD, 4677 reg: regInfo{ 4678 inputs: []inputInfo{ 4679 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4680 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4681 }, 4682 outputs: []outputInfo{ 4683 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4684 }, 4685 }, 4686 }, 4687 { 4688 name: "ADDSSmem", 4689 auxType: auxSymOff, 4690 argLen: 3, 4691 resultInArg0: true, 4692 faultOnNilArg1: true, 4693 symEffect: SymRead, 4694 asm: x86.AADDSS, 4695 reg: regInfo{ 4696 inputs: []inputInfo{ 4697 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4698 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4699 }, 4700 outputs: []outputInfo{ 4701 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4702 }, 4703 }, 4704 }, 4705 { 4706 name: "SUBSSmem", 4707 auxType: auxSymOff, 4708 argLen: 3, 4709 resultInArg0: true, 4710 faultOnNilArg1: true, 4711 symEffect: SymRead, 4712 asm: x86.ASUBSS, 4713 reg: regInfo{ 4714 inputs: []inputInfo{ 4715 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4716 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4717 }, 4718 outputs: []outputInfo{ 4719 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4720 }, 4721 }, 4722 }, 4723 { 4724 name: "SUBSDmem", 4725 auxType: auxSymOff, 4726 argLen: 3, 4727 resultInArg0: true, 4728 faultOnNilArg1: true, 4729 symEffect: SymRead, 4730 asm: x86.ASUBSD, 4731 reg: regInfo{ 4732 inputs: []inputInfo{ 4733 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4734 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4735 }, 4736 outputs: []outputInfo{ 4737 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4738 }, 4739 }, 4740 }, 4741 { 4742 name: "MULSSmem", 4743 auxType: auxSymOff, 4744 argLen: 3, 4745 resultInArg0: true, 4746 faultOnNilArg1: true, 4747 symEffect: SymRead, 4748 asm: x86.AMULSS, 4749 reg: regInfo{ 4750 inputs: []inputInfo{ 4751 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4752 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4753 }, 4754 outputs: []outputInfo{ 4755 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4756 }, 4757 }, 4758 }, 4759 { 4760 name: "MULSDmem", 4761 auxType: auxSymOff, 4762 argLen: 3, 4763 resultInArg0: true, 4764 faultOnNilArg1: true, 4765 symEffect: SymRead, 4766 asm: x86.AMULSD, 4767 reg: regInfo{ 4768 inputs: []inputInfo{ 4769 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4770 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4771 }, 4772 outputs: []outputInfo{ 4773 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4774 }, 4775 }, 4776 }, 4777 { 4778 name: "ADDQ", 4779 argLen: 2, 4780 commutative: true, 4781 clobberFlags: true, 4782 asm: x86.AADDQ, 4783 reg: regInfo{ 4784 inputs: []inputInfo{ 4785 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4786 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4787 }, 4788 outputs: []outputInfo{ 4789 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4790 }, 4791 }, 4792 }, 4793 { 4794 name: "ADDL", 4795 argLen: 2, 4796 commutative: true, 4797 clobberFlags: true, 4798 asm: x86.AADDL, 4799 reg: regInfo{ 4800 inputs: []inputInfo{ 4801 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4802 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4803 }, 4804 outputs: []outputInfo{ 4805 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4806 }, 4807 }, 4808 }, 4809 { 4810 name: "ADDQconst", 4811 auxType: auxInt64, 4812 argLen: 1, 4813 clobberFlags: true, 4814 asm: x86.AADDQ, 4815 reg: regInfo{ 4816 inputs: []inputInfo{ 4817 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4818 }, 4819 outputs: []outputInfo{ 4820 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4821 }, 4822 }, 4823 }, 4824 { 4825 name: "ADDLconst", 4826 auxType: auxInt32, 4827 argLen: 1, 4828 clobberFlags: true, 4829 asm: x86.AADDL, 4830 reg: regInfo{ 4831 inputs: []inputInfo{ 4832 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4833 }, 4834 outputs: []outputInfo{ 4835 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4836 }, 4837 }, 4838 }, 4839 { 4840 name: "SUBQ", 4841 argLen: 2, 4842 resultInArg0: true, 4843 clobberFlags: true, 4844 asm: x86.ASUBQ, 4845 reg: regInfo{ 4846 inputs: []inputInfo{ 4847 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4848 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4849 }, 4850 outputs: []outputInfo{ 4851 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4852 }, 4853 }, 4854 }, 4855 { 4856 name: "SUBL", 4857 argLen: 2, 4858 resultInArg0: true, 4859 clobberFlags: true, 4860 asm: x86.ASUBL, 4861 reg: regInfo{ 4862 inputs: []inputInfo{ 4863 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4864 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4865 }, 4866 outputs: []outputInfo{ 4867 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4868 }, 4869 }, 4870 }, 4871 { 4872 name: "SUBQconst", 4873 auxType: auxInt64, 4874 argLen: 1, 4875 resultInArg0: true, 4876 clobberFlags: true, 4877 asm: x86.ASUBQ, 4878 reg: regInfo{ 4879 inputs: []inputInfo{ 4880 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4881 }, 4882 outputs: []outputInfo{ 4883 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4884 }, 4885 }, 4886 }, 4887 { 4888 name: "SUBLconst", 4889 auxType: auxInt32, 4890 argLen: 1, 4891 resultInArg0: true, 4892 clobberFlags: true, 4893 asm: x86.ASUBL, 4894 reg: regInfo{ 4895 inputs: []inputInfo{ 4896 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4897 }, 4898 outputs: []outputInfo{ 4899 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4900 }, 4901 }, 4902 }, 4903 { 4904 name: "MULQ", 4905 argLen: 2, 4906 commutative: true, 4907 resultInArg0: true, 4908 clobberFlags: true, 4909 asm: x86.AIMULQ, 4910 reg: regInfo{ 4911 inputs: []inputInfo{ 4912 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4913 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4914 }, 4915 outputs: []outputInfo{ 4916 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4917 }, 4918 }, 4919 }, 4920 { 4921 name: "MULL", 4922 argLen: 2, 4923 commutative: true, 4924 resultInArg0: true, 4925 clobberFlags: true, 4926 asm: x86.AIMULL, 4927 reg: regInfo{ 4928 inputs: []inputInfo{ 4929 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4930 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4931 }, 4932 outputs: []outputInfo{ 4933 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4934 }, 4935 }, 4936 }, 4937 { 4938 name: "MULQconst", 4939 auxType: auxInt64, 4940 argLen: 1, 4941 resultInArg0: true, 4942 clobberFlags: true, 4943 asm: x86.AIMULQ, 4944 reg: regInfo{ 4945 inputs: []inputInfo{ 4946 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4947 }, 4948 outputs: []outputInfo{ 4949 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4950 }, 4951 }, 4952 }, 4953 { 4954 name: "MULLconst", 4955 auxType: auxInt32, 4956 argLen: 1, 4957 resultInArg0: true, 4958 clobberFlags: true, 4959 asm: x86.AIMULL, 4960 reg: regInfo{ 4961 inputs: []inputInfo{ 4962 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4963 }, 4964 outputs: []outputInfo{ 4965 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4966 }, 4967 }, 4968 }, 4969 { 4970 name: "HMULQ", 4971 argLen: 2, 4972 commutative: true, 4973 clobberFlags: true, 4974 asm: x86.AIMULQ, 4975 reg: regInfo{ 4976 inputs: []inputInfo{ 4977 {0, 1}, // AX 4978 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4979 }, 4980 clobbers: 1, // AX 4981 outputs: []outputInfo{ 4982 {0, 4}, // DX 4983 }, 4984 }, 4985 }, 4986 { 4987 name: "HMULL", 4988 argLen: 2, 4989 commutative: true, 4990 clobberFlags: true, 4991 asm: x86.AIMULL, 4992 reg: regInfo{ 4993 inputs: []inputInfo{ 4994 {0, 1}, // AX 4995 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4996 }, 4997 clobbers: 1, // AX 4998 outputs: []outputInfo{ 4999 {0, 4}, // DX 5000 }, 5001 }, 5002 }, 5003 { 5004 name: "HMULQU", 5005 argLen: 2, 5006 commutative: true, 5007 clobberFlags: true, 5008 asm: x86.AMULQ, 5009 reg: regInfo{ 5010 inputs: []inputInfo{ 5011 {0, 1}, // AX 5012 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5013 }, 5014 clobbers: 1, // AX 5015 outputs: []outputInfo{ 5016 {0, 4}, // DX 5017 }, 5018 }, 5019 }, 5020 { 5021 name: "HMULLU", 5022 argLen: 2, 5023 commutative: true, 5024 clobberFlags: true, 5025 asm: x86.AMULL, 5026 reg: regInfo{ 5027 inputs: []inputInfo{ 5028 {0, 1}, // AX 5029 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5030 }, 5031 clobbers: 1, // AX 5032 outputs: []outputInfo{ 5033 {0, 4}, // DX 5034 }, 5035 }, 5036 }, 5037 { 5038 name: "AVGQU", 5039 argLen: 2, 5040 commutative: true, 5041 resultInArg0: true, 5042 clobberFlags: true, 5043 reg: regInfo{ 5044 inputs: []inputInfo{ 5045 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5046 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5047 }, 5048 outputs: []outputInfo{ 5049 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5050 }, 5051 }, 5052 }, 5053 { 5054 name: "DIVQ", 5055 argLen: 2, 5056 clobberFlags: true, 5057 asm: x86.AIDIVQ, 5058 reg: regInfo{ 5059 inputs: []inputInfo{ 5060 {0, 1}, // AX 5061 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5062 }, 5063 outputs: []outputInfo{ 5064 {0, 1}, // AX 5065 {1, 4}, // DX 5066 }, 5067 }, 5068 }, 5069 { 5070 name: "DIVL", 5071 argLen: 2, 5072 clobberFlags: true, 5073 asm: x86.AIDIVL, 5074 reg: regInfo{ 5075 inputs: []inputInfo{ 5076 {0, 1}, // AX 5077 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5078 }, 5079 outputs: []outputInfo{ 5080 {0, 1}, // AX 5081 {1, 4}, // DX 5082 }, 5083 }, 5084 }, 5085 { 5086 name: "DIVW", 5087 argLen: 2, 5088 clobberFlags: true, 5089 asm: x86.AIDIVW, 5090 reg: regInfo{ 5091 inputs: []inputInfo{ 5092 {0, 1}, // AX 5093 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5094 }, 5095 outputs: []outputInfo{ 5096 {0, 1}, // AX 5097 {1, 4}, // DX 5098 }, 5099 }, 5100 }, 5101 { 5102 name: "DIVQU", 5103 argLen: 2, 5104 clobberFlags: true, 5105 asm: x86.ADIVQ, 5106 reg: regInfo{ 5107 inputs: []inputInfo{ 5108 {0, 1}, // AX 5109 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5110 }, 5111 outputs: []outputInfo{ 5112 {0, 1}, // AX 5113 {1, 4}, // DX 5114 }, 5115 }, 5116 }, 5117 { 5118 name: "DIVLU", 5119 argLen: 2, 5120 clobberFlags: true, 5121 asm: x86.ADIVL, 5122 reg: regInfo{ 5123 inputs: []inputInfo{ 5124 {0, 1}, // AX 5125 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5126 }, 5127 outputs: []outputInfo{ 5128 {0, 1}, // AX 5129 {1, 4}, // DX 5130 }, 5131 }, 5132 }, 5133 { 5134 name: "DIVWU", 5135 argLen: 2, 5136 clobberFlags: true, 5137 asm: x86.ADIVW, 5138 reg: regInfo{ 5139 inputs: []inputInfo{ 5140 {0, 1}, // AX 5141 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5142 }, 5143 outputs: []outputInfo{ 5144 {0, 1}, // AX 5145 {1, 4}, // DX 5146 }, 5147 }, 5148 }, 5149 { 5150 name: "MULQU2", 5151 argLen: 2, 5152 commutative: true, 5153 clobberFlags: true, 5154 asm: x86.AMULQ, 5155 reg: regInfo{ 5156 inputs: []inputInfo{ 5157 {0, 1}, // AX 5158 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5159 }, 5160 outputs: []outputInfo{ 5161 {0, 4}, // DX 5162 {1, 1}, // AX 5163 }, 5164 }, 5165 }, 5166 { 5167 name: "DIVQU2", 5168 argLen: 3, 5169 clobberFlags: true, 5170 asm: x86.ADIVQ, 5171 reg: regInfo{ 5172 inputs: []inputInfo{ 5173 {0, 4}, // DX 5174 {1, 1}, // AX 5175 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5176 }, 5177 outputs: []outputInfo{ 5178 {0, 1}, // AX 5179 {1, 4}, // DX 5180 }, 5181 }, 5182 }, 5183 { 5184 name: "ANDQ", 5185 argLen: 2, 5186 commutative: true, 5187 resultInArg0: true, 5188 clobberFlags: true, 5189 asm: x86.AANDQ, 5190 reg: regInfo{ 5191 inputs: []inputInfo{ 5192 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5193 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5194 }, 5195 outputs: []outputInfo{ 5196 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5197 }, 5198 }, 5199 }, 5200 { 5201 name: "ANDL", 5202 argLen: 2, 5203 commutative: true, 5204 resultInArg0: true, 5205 clobberFlags: true, 5206 asm: x86.AANDL, 5207 reg: regInfo{ 5208 inputs: []inputInfo{ 5209 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5210 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5211 }, 5212 outputs: []outputInfo{ 5213 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5214 }, 5215 }, 5216 }, 5217 { 5218 name: "ANDQconst", 5219 auxType: auxInt64, 5220 argLen: 1, 5221 resultInArg0: true, 5222 clobberFlags: true, 5223 asm: x86.AANDQ, 5224 reg: regInfo{ 5225 inputs: []inputInfo{ 5226 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5227 }, 5228 outputs: []outputInfo{ 5229 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5230 }, 5231 }, 5232 }, 5233 { 5234 name: "ANDLconst", 5235 auxType: auxInt32, 5236 argLen: 1, 5237 resultInArg0: true, 5238 clobberFlags: true, 5239 asm: x86.AANDL, 5240 reg: regInfo{ 5241 inputs: []inputInfo{ 5242 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5243 }, 5244 outputs: []outputInfo{ 5245 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5246 }, 5247 }, 5248 }, 5249 { 5250 name: "ORQ", 5251 argLen: 2, 5252 commutative: true, 5253 resultInArg0: true, 5254 clobberFlags: true, 5255 asm: x86.AORQ, 5256 reg: regInfo{ 5257 inputs: []inputInfo{ 5258 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5259 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5260 }, 5261 outputs: []outputInfo{ 5262 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5263 }, 5264 }, 5265 }, 5266 { 5267 name: "ORL", 5268 argLen: 2, 5269 commutative: true, 5270 resultInArg0: true, 5271 clobberFlags: true, 5272 asm: x86.AORL, 5273 reg: regInfo{ 5274 inputs: []inputInfo{ 5275 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5276 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5277 }, 5278 outputs: []outputInfo{ 5279 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5280 }, 5281 }, 5282 }, 5283 { 5284 name: "ORQconst", 5285 auxType: auxInt64, 5286 argLen: 1, 5287 resultInArg0: true, 5288 clobberFlags: true, 5289 asm: x86.AORQ, 5290 reg: regInfo{ 5291 inputs: []inputInfo{ 5292 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5293 }, 5294 outputs: []outputInfo{ 5295 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5296 }, 5297 }, 5298 }, 5299 { 5300 name: "ORLconst", 5301 auxType: auxInt32, 5302 argLen: 1, 5303 resultInArg0: true, 5304 clobberFlags: true, 5305 asm: x86.AORL, 5306 reg: regInfo{ 5307 inputs: []inputInfo{ 5308 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5309 }, 5310 outputs: []outputInfo{ 5311 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5312 }, 5313 }, 5314 }, 5315 { 5316 name: "XORQ", 5317 argLen: 2, 5318 commutative: true, 5319 resultInArg0: true, 5320 clobberFlags: true, 5321 asm: x86.AXORQ, 5322 reg: regInfo{ 5323 inputs: []inputInfo{ 5324 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5325 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5326 }, 5327 outputs: []outputInfo{ 5328 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5329 }, 5330 }, 5331 }, 5332 { 5333 name: "XORL", 5334 argLen: 2, 5335 commutative: true, 5336 resultInArg0: true, 5337 clobberFlags: true, 5338 asm: x86.AXORL, 5339 reg: regInfo{ 5340 inputs: []inputInfo{ 5341 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5342 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5343 }, 5344 outputs: []outputInfo{ 5345 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5346 }, 5347 }, 5348 }, 5349 { 5350 name: "XORQconst", 5351 auxType: auxInt64, 5352 argLen: 1, 5353 resultInArg0: true, 5354 clobberFlags: true, 5355 asm: x86.AXORQ, 5356 reg: regInfo{ 5357 inputs: []inputInfo{ 5358 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5359 }, 5360 outputs: []outputInfo{ 5361 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5362 }, 5363 }, 5364 }, 5365 { 5366 name: "XORLconst", 5367 auxType: auxInt32, 5368 argLen: 1, 5369 resultInArg0: true, 5370 clobberFlags: true, 5371 asm: x86.AXORL, 5372 reg: regInfo{ 5373 inputs: []inputInfo{ 5374 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5375 }, 5376 outputs: []outputInfo{ 5377 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5378 }, 5379 }, 5380 }, 5381 { 5382 name: "CMPQ", 5383 argLen: 2, 5384 asm: x86.ACMPQ, 5385 reg: regInfo{ 5386 inputs: []inputInfo{ 5387 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5388 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5389 }, 5390 }, 5391 }, 5392 { 5393 name: "CMPL", 5394 argLen: 2, 5395 asm: x86.ACMPL, 5396 reg: regInfo{ 5397 inputs: []inputInfo{ 5398 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5399 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5400 }, 5401 }, 5402 }, 5403 { 5404 name: "CMPW", 5405 argLen: 2, 5406 asm: x86.ACMPW, 5407 reg: regInfo{ 5408 inputs: []inputInfo{ 5409 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5410 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5411 }, 5412 }, 5413 }, 5414 { 5415 name: "CMPB", 5416 argLen: 2, 5417 asm: x86.ACMPB, 5418 reg: regInfo{ 5419 inputs: []inputInfo{ 5420 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5421 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5422 }, 5423 }, 5424 }, 5425 { 5426 name: "CMPQconst", 5427 auxType: auxInt64, 5428 argLen: 1, 5429 asm: x86.ACMPQ, 5430 reg: regInfo{ 5431 inputs: []inputInfo{ 5432 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5433 }, 5434 }, 5435 }, 5436 { 5437 name: "CMPLconst", 5438 auxType: auxInt32, 5439 argLen: 1, 5440 asm: x86.ACMPL, 5441 reg: regInfo{ 5442 inputs: []inputInfo{ 5443 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5444 }, 5445 }, 5446 }, 5447 { 5448 name: "CMPWconst", 5449 auxType: auxInt16, 5450 argLen: 1, 5451 asm: x86.ACMPW, 5452 reg: regInfo{ 5453 inputs: []inputInfo{ 5454 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5455 }, 5456 }, 5457 }, 5458 { 5459 name: "CMPBconst", 5460 auxType: auxInt8, 5461 argLen: 1, 5462 asm: x86.ACMPB, 5463 reg: regInfo{ 5464 inputs: []inputInfo{ 5465 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5466 }, 5467 }, 5468 }, 5469 { 5470 name: "UCOMISS", 5471 argLen: 2, 5472 asm: x86.AUCOMISS, 5473 reg: regInfo{ 5474 inputs: []inputInfo{ 5475 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5476 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5477 }, 5478 }, 5479 }, 5480 { 5481 name: "UCOMISD", 5482 argLen: 2, 5483 asm: x86.AUCOMISD, 5484 reg: regInfo{ 5485 inputs: []inputInfo{ 5486 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5487 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5488 }, 5489 }, 5490 }, 5491 { 5492 name: "BTL", 5493 argLen: 2, 5494 asm: x86.ABTL, 5495 reg: regInfo{ 5496 inputs: []inputInfo{ 5497 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5498 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5499 }, 5500 }, 5501 }, 5502 { 5503 name: "BTQ", 5504 argLen: 2, 5505 asm: x86.ABTQ, 5506 reg: regInfo{ 5507 inputs: []inputInfo{ 5508 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5509 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5510 }, 5511 }, 5512 }, 5513 { 5514 name: "BTLconst", 5515 auxType: auxInt8, 5516 argLen: 1, 5517 asm: x86.ABTL, 5518 reg: regInfo{ 5519 inputs: []inputInfo{ 5520 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5521 }, 5522 }, 5523 }, 5524 { 5525 name: "BTQconst", 5526 auxType: auxInt8, 5527 argLen: 1, 5528 asm: x86.ABTQ, 5529 reg: regInfo{ 5530 inputs: []inputInfo{ 5531 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5532 }, 5533 }, 5534 }, 5535 { 5536 name: "TESTQ", 5537 argLen: 2, 5538 commutative: true, 5539 asm: x86.ATESTQ, 5540 reg: regInfo{ 5541 inputs: []inputInfo{ 5542 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5543 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5544 }, 5545 }, 5546 }, 5547 { 5548 name: "TESTL", 5549 argLen: 2, 5550 commutative: true, 5551 asm: x86.ATESTL, 5552 reg: regInfo{ 5553 inputs: []inputInfo{ 5554 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5555 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5556 }, 5557 }, 5558 }, 5559 { 5560 name: "TESTW", 5561 argLen: 2, 5562 commutative: true, 5563 asm: x86.ATESTW, 5564 reg: regInfo{ 5565 inputs: []inputInfo{ 5566 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5567 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5568 }, 5569 }, 5570 }, 5571 { 5572 name: "TESTB", 5573 argLen: 2, 5574 commutative: true, 5575 asm: x86.ATESTB, 5576 reg: regInfo{ 5577 inputs: []inputInfo{ 5578 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5579 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5580 }, 5581 }, 5582 }, 5583 { 5584 name: "TESTQconst", 5585 auxType: auxInt64, 5586 argLen: 1, 5587 asm: x86.ATESTQ, 5588 reg: regInfo{ 5589 inputs: []inputInfo{ 5590 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5591 }, 5592 }, 5593 }, 5594 { 5595 name: "TESTLconst", 5596 auxType: auxInt32, 5597 argLen: 1, 5598 asm: x86.ATESTL, 5599 reg: regInfo{ 5600 inputs: []inputInfo{ 5601 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5602 }, 5603 }, 5604 }, 5605 { 5606 name: "TESTWconst", 5607 auxType: auxInt16, 5608 argLen: 1, 5609 asm: x86.ATESTW, 5610 reg: regInfo{ 5611 inputs: []inputInfo{ 5612 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5613 }, 5614 }, 5615 }, 5616 { 5617 name: "TESTBconst", 5618 auxType: auxInt8, 5619 argLen: 1, 5620 asm: x86.ATESTB, 5621 reg: regInfo{ 5622 inputs: []inputInfo{ 5623 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5624 }, 5625 }, 5626 }, 5627 { 5628 name: "SHLQ", 5629 argLen: 2, 5630 resultInArg0: true, 5631 clobberFlags: true, 5632 asm: x86.ASHLQ, 5633 reg: regInfo{ 5634 inputs: []inputInfo{ 5635 {1, 2}, // CX 5636 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5637 }, 5638 outputs: []outputInfo{ 5639 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5640 }, 5641 }, 5642 }, 5643 { 5644 name: "SHLL", 5645 argLen: 2, 5646 resultInArg0: true, 5647 clobberFlags: true, 5648 asm: x86.ASHLL, 5649 reg: regInfo{ 5650 inputs: []inputInfo{ 5651 {1, 2}, // CX 5652 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5653 }, 5654 outputs: []outputInfo{ 5655 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5656 }, 5657 }, 5658 }, 5659 { 5660 name: "SHLQconst", 5661 auxType: auxInt8, 5662 argLen: 1, 5663 resultInArg0: true, 5664 clobberFlags: true, 5665 asm: x86.ASHLQ, 5666 reg: regInfo{ 5667 inputs: []inputInfo{ 5668 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5669 }, 5670 outputs: []outputInfo{ 5671 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5672 }, 5673 }, 5674 }, 5675 { 5676 name: "SHLLconst", 5677 auxType: auxInt8, 5678 argLen: 1, 5679 resultInArg0: true, 5680 clobberFlags: true, 5681 asm: x86.ASHLL, 5682 reg: regInfo{ 5683 inputs: []inputInfo{ 5684 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5685 }, 5686 outputs: []outputInfo{ 5687 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5688 }, 5689 }, 5690 }, 5691 { 5692 name: "SHRQ", 5693 argLen: 2, 5694 resultInArg0: true, 5695 clobberFlags: true, 5696 asm: x86.ASHRQ, 5697 reg: regInfo{ 5698 inputs: []inputInfo{ 5699 {1, 2}, // CX 5700 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5701 }, 5702 outputs: []outputInfo{ 5703 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5704 }, 5705 }, 5706 }, 5707 { 5708 name: "SHRL", 5709 argLen: 2, 5710 resultInArg0: true, 5711 clobberFlags: true, 5712 asm: x86.ASHRL, 5713 reg: regInfo{ 5714 inputs: []inputInfo{ 5715 {1, 2}, // CX 5716 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5717 }, 5718 outputs: []outputInfo{ 5719 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5720 }, 5721 }, 5722 }, 5723 { 5724 name: "SHRW", 5725 argLen: 2, 5726 resultInArg0: true, 5727 clobberFlags: true, 5728 asm: x86.ASHRW, 5729 reg: regInfo{ 5730 inputs: []inputInfo{ 5731 {1, 2}, // CX 5732 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5733 }, 5734 outputs: []outputInfo{ 5735 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5736 }, 5737 }, 5738 }, 5739 { 5740 name: "SHRB", 5741 argLen: 2, 5742 resultInArg0: true, 5743 clobberFlags: true, 5744 asm: x86.ASHRB, 5745 reg: regInfo{ 5746 inputs: []inputInfo{ 5747 {1, 2}, // CX 5748 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5749 }, 5750 outputs: []outputInfo{ 5751 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5752 }, 5753 }, 5754 }, 5755 { 5756 name: "SHRQconst", 5757 auxType: auxInt8, 5758 argLen: 1, 5759 resultInArg0: true, 5760 clobberFlags: true, 5761 asm: x86.ASHRQ, 5762 reg: regInfo{ 5763 inputs: []inputInfo{ 5764 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5765 }, 5766 outputs: []outputInfo{ 5767 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5768 }, 5769 }, 5770 }, 5771 { 5772 name: "SHRLconst", 5773 auxType: auxInt8, 5774 argLen: 1, 5775 resultInArg0: true, 5776 clobberFlags: true, 5777 asm: x86.ASHRL, 5778 reg: regInfo{ 5779 inputs: []inputInfo{ 5780 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5781 }, 5782 outputs: []outputInfo{ 5783 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5784 }, 5785 }, 5786 }, 5787 { 5788 name: "SHRWconst", 5789 auxType: auxInt8, 5790 argLen: 1, 5791 resultInArg0: true, 5792 clobberFlags: true, 5793 asm: x86.ASHRW, 5794 reg: regInfo{ 5795 inputs: []inputInfo{ 5796 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5797 }, 5798 outputs: []outputInfo{ 5799 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5800 }, 5801 }, 5802 }, 5803 { 5804 name: "SHRBconst", 5805 auxType: auxInt8, 5806 argLen: 1, 5807 resultInArg0: true, 5808 clobberFlags: true, 5809 asm: x86.ASHRB, 5810 reg: regInfo{ 5811 inputs: []inputInfo{ 5812 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5813 }, 5814 outputs: []outputInfo{ 5815 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5816 }, 5817 }, 5818 }, 5819 { 5820 name: "SARQ", 5821 argLen: 2, 5822 resultInArg0: true, 5823 clobberFlags: true, 5824 asm: x86.ASARQ, 5825 reg: regInfo{ 5826 inputs: []inputInfo{ 5827 {1, 2}, // CX 5828 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5829 }, 5830 outputs: []outputInfo{ 5831 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5832 }, 5833 }, 5834 }, 5835 { 5836 name: "SARL", 5837 argLen: 2, 5838 resultInArg0: true, 5839 clobberFlags: true, 5840 asm: x86.ASARL, 5841 reg: regInfo{ 5842 inputs: []inputInfo{ 5843 {1, 2}, // CX 5844 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5845 }, 5846 outputs: []outputInfo{ 5847 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5848 }, 5849 }, 5850 }, 5851 { 5852 name: "SARW", 5853 argLen: 2, 5854 resultInArg0: true, 5855 clobberFlags: true, 5856 asm: x86.ASARW, 5857 reg: regInfo{ 5858 inputs: []inputInfo{ 5859 {1, 2}, // CX 5860 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5861 }, 5862 outputs: []outputInfo{ 5863 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5864 }, 5865 }, 5866 }, 5867 { 5868 name: "SARB", 5869 argLen: 2, 5870 resultInArg0: true, 5871 clobberFlags: true, 5872 asm: x86.ASARB, 5873 reg: regInfo{ 5874 inputs: []inputInfo{ 5875 {1, 2}, // CX 5876 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5877 }, 5878 outputs: []outputInfo{ 5879 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5880 }, 5881 }, 5882 }, 5883 { 5884 name: "SARQconst", 5885 auxType: auxInt8, 5886 argLen: 1, 5887 resultInArg0: true, 5888 clobberFlags: true, 5889 asm: x86.ASARQ, 5890 reg: regInfo{ 5891 inputs: []inputInfo{ 5892 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5893 }, 5894 outputs: []outputInfo{ 5895 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5896 }, 5897 }, 5898 }, 5899 { 5900 name: "SARLconst", 5901 auxType: auxInt8, 5902 argLen: 1, 5903 resultInArg0: true, 5904 clobberFlags: true, 5905 asm: x86.ASARL, 5906 reg: regInfo{ 5907 inputs: []inputInfo{ 5908 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5909 }, 5910 outputs: []outputInfo{ 5911 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5912 }, 5913 }, 5914 }, 5915 { 5916 name: "SARWconst", 5917 auxType: auxInt8, 5918 argLen: 1, 5919 resultInArg0: true, 5920 clobberFlags: true, 5921 asm: x86.ASARW, 5922 reg: regInfo{ 5923 inputs: []inputInfo{ 5924 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5925 }, 5926 outputs: []outputInfo{ 5927 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5928 }, 5929 }, 5930 }, 5931 { 5932 name: "SARBconst", 5933 auxType: auxInt8, 5934 argLen: 1, 5935 resultInArg0: true, 5936 clobberFlags: true, 5937 asm: x86.ASARB, 5938 reg: regInfo{ 5939 inputs: []inputInfo{ 5940 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5941 }, 5942 outputs: []outputInfo{ 5943 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5944 }, 5945 }, 5946 }, 5947 { 5948 name: "ROLQconst", 5949 auxType: auxInt8, 5950 argLen: 1, 5951 resultInArg0: true, 5952 clobberFlags: true, 5953 asm: x86.AROLQ, 5954 reg: regInfo{ 5955 inputs: []inputInfo{ 5956 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5957 }, 5958 outputs: []outputInfo{ 5959 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5960 }, 5961 }, 5962 }, 5963 { 5964 name: "ROLLconst", 5965 auxType: auxInt8, 5966 argLen: 1, 5967 resultInArg0: true, 5968 clobberFlags: true, 5969 asm: x86.AROLL, 5970 reg: regInfo{ 5971 inputs: []inputInfo{ 5972 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5973 }, 5974 outputs: []outputInfo{ 5975 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5976 }, 5977 }, 5978 }, 5979 { 5980 name: "ROLWconst", 5981 auxType: auxInt8, 5982 argLen: 1, 5983 resultInArg0: true, 5984 clobberFlags: true, 5985 asm: x86.AROLW, 5986 reg: regInfo{ 5987 inputs: []inputInfo{ 5988 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5989 }, 5990 outputs: []outputInfo{ 5991 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5992 }, 5993 }, 5994 }, 5995 { 5996 name: "ROLBconst", 5997 auxType: auxInt8, 5998 argLen: 1, 5999 resultInArg0: true, 6000 clobberFlags: true, 6001 asm: x86.AROLB, 6002 reg: regInfo{ 6003 inputs: []inputInfo{ 6004 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6005 }, 6006 outputs: []outputInfo{ 6007 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6008 }, 6009 }, 6010 }, 6011 { 6012 name: "ADDLmem", 6013 auxType: auxSymOff, 6014 argLen: 3, 6015 resultInArg0: true, 6016 clobberFlags: true, 6017 faultOnNilArg1: true, 6018 symEffect: SymRead, 6019 asm: x86.AADDL, 6020 reg: regInfo{ 6021 inputs: []inputInfo{ 6022 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6023 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6024 }, 6025 outputs: []outputInfo{ 6026 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6027 }, 6028 }, 6029 }, 6030 { 6031 name: "ADDQmem", 6032 auxType: auxSymOff, 6033 argLen: 3, 6034 resultInArg0: true, 6035 clobberFlags: true, 6036 faultOnNilArg1: true, 6037 symEffect: SymRead, 6038 asm: x86.AADDQ, 6039 reg: regInfo{ 6040 inputs: []inputInfo{ 6041 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6042 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6043 }, 6044 outputs: []outputInfo{ 6045 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6046 }, 6047 }, 6048 }, 6049 { 6050 name: "SUBQmem", 6051 auxType: auxSymOff, 6052 argLen: 3, 6053 resultInArg0: true, 6054 clobberFlags: true, 6055 faultOnNilArg1: true, 6056 symEffect: SymRead, 6057 asm: x86.ASUBQ, 6058 reg: regInfo{ 6059 inputs: []inputInfo{ 6060 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6061 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6062 }, 6063 outputs: []outputInfo{ 6064 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6065 }, 6066 }, 6067 }, 6068 { 6069 name: "SUBLmem", 6070 auxType: auxSymOff, 6071 argLen: 3, 6072 resultInArg0: true, 6073 clobberFlags: true, 6074 faultOnNilArg1: true, 6075 symEffect: SymRead, 6076 asm: x86.ASUBL, 6077 reg: regInfo{ 6078 inputs: []inputInfo{ 6079 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6080 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6081 }, 6082 outputs: []outputInfo{ 6083 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6084 }, 6085 }, 6086 }, 6087 { 6088 name: "ANDLmem", 6089 auxType: auxSymOff, 6090 argLen: 3, 6091 resultInArg0: true, 6092 clobberFlags: true, 6093 faultOnNilArg1: true, 6094 symEffect: SymRead, 6095 asm: x86.AANDL, 6096 reg: regInfo{ 6097 inputs: []inputInfo{ 6098 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6099 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6100 }, 6101 outputs: []outputInfo{ 6102 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6103 }, 6104 }, 6105 }, 6106 { 6107 name: "ANDQmem", 6108 auxType: auxSymOff, 6109 argLen: 3, 6110 resultInArg0: true, 6111 clobberFlags: true, 6112 faultOnNilArg1: true, 6113 symEffect: SymRead, 6114 asm: x86.AANDQ, 6115 reg: regInfo{ 6116 inputs: []inputInfo{ 6117 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6118 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6119 }, 6120 outputs: []outputInfo{ 6121 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6122 }, 6123 }, 6124 }, 6125 { 6126 name: "ORQmem", 6127 auxType: auxSymOff, 6128 argLen: 3, 6129 resultInArg0: true, 6130 clobberFlags: true, 6131 faultOnNilArg1: true, 6132 symEffect: SymRead, 6133 asm: x86.AORQ, 6134 reg: regInfo{ 6135 inputs: []inputInfo{ 6136 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6137 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6138 }, 6139 outputs: []outputInfo{ 6140 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6141 }, 6142 }, 6143 }, 6144 { 6145 name: "ORLmem", 6146 auxType: auxSymOff, 6147 argLen: 3, 6148 resultInArg0: true, 6149 clobberFlags: true, 6150 faultOnNilArg1: true, 6151 symEffect: SymRead, 6152 asm: x86.AORL, 6153 reg: regInfo{ 6154 inputs: []inputInfo{ 6155 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6156 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6157 }, 6158 outputs: []outputInfo{ 6159 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6160 }, 6161 }, 6162 }, 6163 { 6164 name: "XORQmem", 6165 auxType: auxSymOff, 6166 argLen: 3, 6167 resultInArg0: true, 6168 clobberFlags: true, 6169 faultOnNilArg1: true, 6170 symEffect: SymRead, 6171 asm: x86.AXORQ, 6172 reg: regInfo{ 6173 inputs: []inputInfo{ 6174 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6175 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6176 }, 6177 outputs: []outputInfo{ 6178 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6179 }, 6180 }, 6181 }, 6182 { 6183 name: "XORLmem", 6184 auxType: auxSymOff, 6185 argLen: 3, 6186 resultInArg0: true, 6187 clobberFlags: true, 6188 faultOnNilArg1: true, 6189 symEffect: SymRead, 6190 asm: x86.AXORL, 6191 reg: regInfo{ 6192 inputs: []inputInfo{ 6193 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6194 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6195 }, 6196 outputs: []outputInfo{ 6197 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6198 }, 6199 }, 6200 }, 6201 { 6202 name: "NEGQ", 6203 argLen: 1, 6204 resultInArg0: true, 6205 clobberFlags: true, 6206 asm: x86.ANEGQ, 6207 reg: regInfo{ 6208 inputs: []inputInfo{ 6209 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6210 }, 6211 outputs: []outputInfo{ 6212 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6213 }, 6214 }, 6215 }, 6216 { 6217 name: "NEGL", 6218 argLen: 1, 6219 resultInArg0: true, 6220 clobberFlags: true, 6221 asm: x86.ANEGL, 6222 reg: regInfo{ 6223 inputs: []inputInfo{ 6224 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6225 }, 6226 outputs: []outputInfo{ 6227 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6228 }, 6229 }, 6230 }, 6231 { 6232 name: "NOTQ", 6233 argLen: 1, 6234 resultInArg0: true, 6235 clobberFlags: true, 6236 asm: x86.ANOTQ, 6237 reg: regInfo{ 6238 inputs: []inputInfo{ 6239 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6240 }, 6241 outputs: []outputInfo{ 6242 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6243 }, 6244 }, 6245 }, 6246 { 6247 name: "NOTL", 6248 argLen: 1, 6249 resultInArg0: true, 6250 clobberFlags: true, 6251 asm: x86.ANOTL, 6252 reg: regInfo{ 6253 inputs: []inputInfo{ 6254 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6255 }, 6256 outputs: []outputInfo{ 6257 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6258 }, 6259 }, 6260 }, 6261 { 6262 name: "BSFQ", 6263 argLen: 1, 6264 asm: x86.ABSFQ, 6265 reg: regInfo{ 6266 inputs: []inputInfo{ 6267 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6268 }, 6269 outputs: []outputInfo{ 6270 {1, 0}, 6271 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6272 }, 6273 }, 6274 }, 6275 { 6276 name: "BSFL", 6277 argLen: 1, 6278 asm: x86.ABSFL, 6279 reg: regInfo{ 6280 inputs: []inputInfo{ 6281 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6282 }, 6283 outputs: []outputInfo{ 6284 {1, 0}, 6285 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6286 }, 6287 }, 6288 }, 6289 { 6290 name: "BSRQ", 6291 argLen: 1, 6292 asm: x86.ABSRQ, 6293 reg: regInfo{ 6294 inputs: []inputInfo{ 6295 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6296 }, 6297 outputs: []outputInfo{ 6298 {1, 0}, 6299 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6300 }, 6301 }, 6302 }, 6303 { 6304 name: "BSRL", 6305 argLen: 1, 6306 asm: x86.ABSRL, 6307 reg: regInfo{ 6308 inputs: []inputInfo{ 6309 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6310 }, 6311 outputs: []outputInfo{ 6312 {1, 0}, 6313 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6314 }, 6315 }, 6316 }, 6317 { 6318 name: "CMOVQEQ", 6319 argLen: 3, 6320 resultInArg0: true, 6321 asm: x86.ACMOVQEQ, 6322 reg: regInfo{ 6323 inputs: []inputInfo{ 6324 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6325 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6326 }, 6327 outputs: []outputInfo{ 6328 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6329 }, 6330 }, 6331 }, 6332 { 6333 name: "CMOVLEQ", 6334 argLen: 3, 6335 resultInArg0: true, 6336 asm: x86.ACMOVLEQ, 6337 reg: regInfo{ 6338 inputs: []inputInfo{ 6339 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6340 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6341 }, 6342 outputs: []outputInfo{ 6343 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6344 }, 6345 }, 6346 }, 6347 { 6348 name: "BSWAPQ", 6349 argLen: 1, 6350 resultInArg0: true, 6351 clobberFlags: true, 6352 asm: x86.ABSWAPQ, 6353 reg: regInfo{ 6354 inputs: []inputInfo{ 6355 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6356 }, 6357 outputs: []outputInfo{ 6358 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6359 }, 6360 }, 6361 }, 6362 { 6363 name: "BSWAPL", 6364 argLen: 1, 6365 resultInArg0: true, 6366 clobberFlags: true, 6367 asm: x86.ABSWAPL, 6368 reg: regInfo{ 6369 inputs: []inputInfo{ 6370 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6371 }, 6372 outputs: []outputInfo{ 6373 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6374 }, 6375 }, 6376 }, 6377 { 6378 name: "POPCNTQ", 6379 argLen: 1, 6380 clobberFlags: true, 6381 asm: x86.APOPCNTQ, 6382 reg: regInfo{ 6383 inputs: []inputInfo{ 6384 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6385 }, 6386 outputs: []outputInfo{ 6387 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6388 }, 6389 }, 6390 }, 6391 { 6392 name: "POPCNTL", 6393 argLen: 1, 6394 clobberFlags: true, 6395 asm: x86.APOPCNTL, 6396 reg: regInfo{ 6397 inputs: []inputInfo{ 6398 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6399 }, 6400 outputs: []outputInfo{ 6401 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6402 }, 6403 }, 6404 }, 6405 { 6406 name: "SQRTSD", 6407 argLen: 1, 6408 asm: x86.ASQRTSD, 6409 reg: regInfo{ 6410 inputs: []inputInfo{ 6411 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6412 }, 6413 outputs: []outputInfo{ 6414 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6415 }, 6416 }, 6417 }, 6418 { 6419 name: "SBBQcarrymask", 6420 argLen: 1, 6421 asm: x86.ASBBQ, 6422 reg: regInfo{ 6423 outputs: []outputInfo{ 6424 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6425 }, 6426 }, 6427 }, 6428 { 6429 name: "SBBLcarrymask", 6430 argLen: 1, 6431 asm: x86.ASBBL, 6432 reg: regInfo{ 6433 outputs: []outputInfo{ 6434 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6435 }, 6436 }, 6437 }, 6438 { 6439 name: "SETEQ", 6440 argLen: 1, 6441 asm: x86.ASETEQ, 6442 reg: regInfo{ 6443 outputs: []outputInfo{ 6444 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6445 }, 6446 }, 6447 }, 6448 { 6449 name: "SETNE", 6450 argLen: 1, 6451 asm: x86.ASETNE, 6452 reg: regInfo{ 6453 outputs: []outputInfo{ 6454 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6455 }, 6456 }, 6457 }, 6458 { 6459 name: "SETL", 6460 argLen: 1, 6461 asm: x86.ASETLT, 6462 reg: regInfo{ 6463 outputs: []outputInfo{ 6464 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6465 }, 6466 }, 6467 }, 6468 { 6469 name: "SETLE", 6470 argLen: 1, 6471 asm: x86.ASETLE, 6472 reg: regInfo{ 6473 outputs: []outputInfo{ 6474 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6475 }, 6476 }, 6477 }, 6478 { 6479 name: "SETG", 6480 argLen: 1, 6481 asm: x86.ASETGT, 6482 reg: regInfo{ 6483 outputs: []outputInfo{ 6484 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6485 }, 6486 }, 6487 }, 6488 { 6489 name: "SETGE", 6490 argLen: 1, 6491 asm: x86.ASETGE, 6492 reg: regInfo{ 6493 outputs: []outputInfo{ 6494 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6495 }, 6496 }, 6497 }, 6498 { 6499 name: "SETB", 6500 argLen: 1, 6501 asm: x86.ASETCS, 6502 reg: regInfo{ 6503 outputs: []outputInfo{ 6504 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6505 }, 6506 }, 6507 }, 6508 { 6509 name: "SETBE", 6510 argLen: 1, 6511 asm: x86.ASETLS, 6512 reg: regInfo{ 6513 outputs: []outputInfo{ 6514 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6515 }, 6516 }, 6517 }, 6518 { 6519 name: "SETA", 6520 argLen: 1, 6521 asm: x86.ASETHI, 6522 reg: regInfo{ 6523 outputs: []outputInfo{ 6524 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6525 }, 6526 }, 6527 }, 6528 { 6529 name: "SETAE", 6530 argLen: 1, 6531 asm: x86.ASETCC, 6532 reg: regInfo{ 6533 outputs: []outputInfo{ 6534 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6535 }, 6536 }, 6537 }, 6538 { 6539 name: "SETEQF", 6540 argLen: 1, 6541 clobberFlags: true, 6542 asm: x86.ASETEQ, 6543 reg: regInfo{ 6544 clobbers: 1, // AX 6545 outputs: []outputInfo{ 6546 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6547 }, 6548 }, 6549 }, 6550 { 6551 name: "SETNEF", 6552 argLen: 1, 6553 clobberFlags: true, 6554 asm: x86.ASETNE, 6555 reg: regInfo{ 6556 clobbers: 1, // AX 6557 outputs: []outputInfo{ 6558 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6559 }, 6560 }, 6561 }, 6562 { 6563 name: "SETORD", 6564 argLen: 1, 6565 asm: x86.ASETPC, 6566 reg: regInfo{ 6567 outputs: []outputInfo{ 6568 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6569 }, 6570 }, 6571 }, 6572 { 6573 name: "SETNAN", 6574 argLen: 1, 6575 asm: x86.ASETPS, 6576 reg: regInfo{ 6577 outputs: []outputInfo{ 6578 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6579 }, 6580 }, 6581 }, 6582 { 6583 name: "SETGF", 6584 argLen: 1, 6585 asm: x86.ASETHI, 6586 reg: regInfo{ 6587 outputs: []outputInfo{ 6588 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6589 }, 6590 }, 6591 }, 6592 { 6593 name: "SETGEF", 6594 argLen: 1, 6595 asm: x86.ASETCC, 6596 reg: regInfo{ 6597 outputs: []outputInfo{ 6598 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6599 }, 6600 }, 6601 }, 6602 { 6603 name: "MOVBQSX", 6604 argLen: 1, 6605 asm: x86.AMOVBQSX, 6606 reg: regInfo{ 6607 inputs: []inputInfo{ 6608 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6609 }, 6610 outputs: []outputInfo{ 6611 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6612 }, 6613 }, 6614 }, 6615 { 6616 name: "MOVBQZX", 6617 argLen: 1, 6618 asm: x86.AMOVBLZX, 6619 reg: regInfo{ 6620 inputs: []inputInfo{ 6621 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6622 }, 6623 outputs: []outputInfo{ 6624 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6625 }, 6626 }, 6627 }, 6628 { 6629 name: "MOVWQSX", 6630 argLen: 1, 6631 asm: x86.AMOVWQSX, 6632 reg: regInfo{ 6633 inputs: []inputInfo{ 6634 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6635 }, 6636 outputs: []outputInfo{ 6637 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6638 }, 6639 }, 6640 }, 6641 { 6642 name: "MOVWQZX", 6643 argLen: 1, 6644 asm: x86.AMOVWLZX, 6645 reg: regInfo{ 6646 inputs: []inputInfo{ 6647 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6648 }, 6649 outputs: []outputInfo{ 6650 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6651 }, 6652 }, 6653 }, 6654 { 6655 name: "MOVLQSX", 6656 argLen: 1, 6657 asm: x86.AMOVLQSX, 6658 reg: regInfo{ 6659 inputs: []inputInfo{ 6660 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6661 }, 6662 outputs: []outputInfo{ 6663 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6664 }, 6665 }, 6666 }, 6667 { 6668 name: "MOVLQZX", 6669 argLen: 1, 6670 asm: x86.AMOVL, 6671 reg: regInfo{ 6672 inputs: []inputInfo{ 6673 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6674 }, 6675 outputs: []outputInfo{ 6676 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6677 }, 6678 }, 6679 }, 6680 { 6681 name: "MOVLconst", 6682 auxType: auxInt32, 6683 argLen: 0, 6684 rematerializeable: true, 6685 asm: x86.AMOVL, 6686 reg: regInfo{ 6687 outputs: []outputInfo{ 6688 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6689 }, 6690 }, 6691 }, 6692 { 6693 name: "MOVQconst", 6694 auxType: auxInt64, 6695 argLen: 0, 6696 rematerializeable: true, 6697 asm: x86.AMOVQ, 6698 reg: regInfo{ 6699 outputs: []outputInfo{ 6700 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6701 }, 6702 }, 6703 }, 6704 { 6705 name: "CVTTSD2SL", 6706 argLen: 1, 6707 asm: x86.ACVTTSD2SL, 6708 reg: regInfo{ 6709 inputs: []inputInfo{ 6710 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6711 }, 6712 outputs: []outputInfo{ 6713 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6714 }, 6715 }, 6716 }, 6717 { 6718 name: "CVTTSD2SQ", 6719 argLen: 1, 6720 asm: x86.ACVTTSD2SQ, 6721 reg: regInfo{ 6722 inputs: []inputInfo{ 6723 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6724 }, 6725 outputs: []outputInfo{ 6726 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6727 }, 6728 }, 6729 }, 6730 { 6731 name: "CVTTSS2SL", 6732 argLen: 1, 6733 asm: x86.ACVTTSS2SL, 6734 reg: regInfo{ 6735 inputs: []inputInfo{ 6736 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6737 }, 6738 outputs: []outputInfo{ 6739 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6740 }, 6741 }, 6742 }, 6743 { 6744 name: "CVTTSS2SQ", 6745 argLen: 1, 6746 asm: x86.ACVTTSS2SQ, 6747 reg: regInfo{ 6748 inputs: []inputInfo{ 6749 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6750 }, 6751 outputs: []outputInfo{ 6752 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6753 }, 6754 }, 6755 }, 6756 { 6757 name: "CVTSL2SS", 6758 argLen: 1, 6759 asm: x86.ACVTSL2SS, 6760 reg: regInfo{ 6761 inputs: []inputInfo{ 6762 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6763 }, 6764 outputs: []outputInfo{ 6765 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6766 }, 6767 }, 6768 }, 6769 { 6770 name: "CVTSL2SD", 6771 argLen: 1, 6772 asm: x86.ACVTSL2SD, 6773 reg: regInfo{ 6774 inputs: []inputInfo{ 6775 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6776 }, 6777 outputs: []outputInfo{ 6778 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6779 }, 6780 }, 6781 }, 6782 { 6783 name: "CVTSQ2SS", 6784 argLen: 1, 6785 asm: x86.ACVTSQ2SS, 6786 reg: regInfo{ 6787 inputs: []inputInfo{ 6788 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6789 }, 6790 outputs: []outputInfo{ 6791 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6792 }, 6793 }, 6794 }, 6795 { 6796 name: "CVTSQ2SD", 6797 argLen: 1, 6798 asm: x86.ACVTSQ2SD, 6799 reg: regInfo{ 6800 inputs: []inputInfo{ 6801 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6802 }, 6803 outputs: []outputInfo{ 6804 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6805 }, 6806 }, 6807 }, 6808 { 6809 name: "CVTSD2SS", 6810 argLen: 1, 6811 asm: x86.ACVTSD2SS, 6812 reg: regInfo{ 6813 inputs: []inputInfo{ 6814 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6815 }, 6816 outputs: []outputInfo{ 6817 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6818 }, 6819 }, 6820 }, 6821 { 6822 name: "CVTSS2SD", 6823 argLen: 1, 6824 asm: x86.ACVTSS2SD, 6825 reg: regInfo{ 6826 inputs: []inputInfo{ 6827 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6828 }, 6829 outputs: []outputInfo{ 6830 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6831 }, 6832 }, 6833 }, 6834 { 6835 name: "PXOR", 6836 argLen: 2, 6837 commutative: true, 6838 resultInArg0: true, 6839 asm: x86.APXOR, 6840 reg: regInfo{ 6841 inputs: []inputInfo{ 6842 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6843 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6844 }, 6845 outputs: []outputInfo{ 6846 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6847 }, 6848 }, 6849 }, 6850 { 6851 name: "LEAQ", 6852 auxType: auxSymOff, 6853 argLen: 1, 6854 rematerializeable: true, 6855 symEffect: SymAddr, 6856 asm: x86.ALEAQ, 6857 reg: regInfo{ 6858 inputs: []inputInfo{ 6859 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6860 }, 6861 outputs: []outputInfo{ 6862 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6863 }, 6864 }, 6865 }, 6866 { 6867 name: "LEAQ1", 6868 auxType: auxSymOff, 6869 argLen: 2, 6870 commutative: true, 6871 symEffect: SymAddr, 6872 reg: regInfo{ 6873 inputs: []inputInfo{ 6874 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6875 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6876 }, 6877 outputs: []outputInfo{ 6878 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6879 }, 6880 }, 6881 }, 6882 { 6883 name: "LEAQ2", 6884 auxType: auxSymOff, 6885 argLen: 2, 6886 symEffect: SymAddr, 6887 reg: regInfo{ 6888 inputs: []inputInfo{ 6889 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6890 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6891 }, 6892 outputs: []outputInfo{ 6893 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6894 }, 6895 }, 6896 }, 6897 { 6898 name: "LEAQ4", 6899 auxType: auxSymOff, 6900 argLen: 2, 6901 symEffect: SymAddr, 6902 reg: regInfo{ 6903 inputs: []inputInfo{ 6904 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6905 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6906 }, 6907 outputs: []outputInfo{ 6908 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6909 }, 6910 }, 6911 }, 6912 { 6913 name: "LEAQ8", 6914 auxType: auxSymOff, 6915 argLen: 2, 6916 symEffect: SymAddr, 6917 reg: regInfo{ 6918 inputs: []inputInfo{ 6919 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6920 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6921 }, 6922 outputs: []outputInfo{ 6923 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6924 }, 6925 }, 6926 }, 6927 { 6928 name: "LEAL", 6929 auxType: auxSymOff, 6930 argLen: 1, 6931 rematerializeable: true, 6932 symEffect: SymAddr, 6933 asm: x86.ALEAL, 6934 reg: regInfo{ 6935 inputs: []inputInfo{ 6936 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6937 }, 6938 outputs: []outputInfo{ 6939 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6940 }, 6941 }, 6942 }, 6943 { 6944 name: "MOVBload", 6945 auxType: auxSymOff, 6946 argLen: 2, 6947 faultOnNilArg0: true, 6948 symEffect: SymRead, 6949 asm: x86.AMOVBLZX, 6950 reg: regInfo{ 6951 inputs: []inputInfo{ 6952 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6953 }, 6954 outputs: []outputInfo{ 6955 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6956 }, 6957 }, 6958 }, 6959 { 6960 name: "MOVBQSXload", 6961 auxType: auxSymOff, 6962 argLen: 2, 6963 faultOnNilArg0: true, 6964 symEffect: SymRead, 6965 asm: x86.AMOVBQSX, 6966 reg: regInfo{ 6967 inputs: []inputInfo{ 6968 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6969 }, 6970 outputs: []outputInfo{ 6971 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6972 }, 6973 }, 6974 }, 6975 { 6976 name: "MOVWload", 6977 auxType: auxSymOff, 6978 argLen: 2, 6979 faultOnNilArg0: true, 6980 symEffect: SymRead, 6981 asm: x86.AMOVWLZX, 6982 reg: regInfo{ 6983 inputs: []inputInfo{ 6984 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6985 }, 6986 outputs: []outputInfo{ 6987 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6988 }, 6989 }, 6990 }, 6991 { 6992 name: "MOVWQSXload", 6993 auxType: auxSymOff, 6994 argLen: 2, 6995 faultOnNilArg0: true, 6996 symEffect: SymRead, 6997 asm: x86.AMOVWQSX, 6998 reg: regInfo{ 6999 inputs: []inputInfo{ 7000 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7001 }, 7002 outputs: []outputInfo{ 7003 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7004 }, 7005 }, 7006 }, 7007 { 7008 name: "MOVLload", 7009 auxType: auxSymOff, 7010 argLen: 2, 7011 faultOnNilArg0: true, 7012 symEffect: SymRead, 7013 asm: x86.AMOVL, 7014 reg: regInfo{ 7015 inputs: []inputInfo{ 7016 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7017 }, 7018 outputs: []outputInfo{ 7019 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7020 }, 7021 }, 7022 }, 7023 { 7024 name: "MOVLQSXload", 7025 auxType: auxSymOff, 7026 argLen: 2, 7027 faultOnNilArg0: true, 7028 symEffect: SymRead, 7029 asm: x86.AMOVLQSX, 7030 reg: regInfo{ 7031 inputs: []inputInfo{ 7032 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7033 }, 7034 outputs: []outputInfo{ 7035 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7036 }, 7037 }, 7038 }, 7039 { 7040 name: "MOVQload", 7041 auxType: auxSymOff, 7042 argLen: 2, 7043 faultOnNilArg0: true, 7044 symEffect: SymRead, 7045 asm: x86.AMOVQ, 7046 reg: regInfo{ 7047 inputs: []inputInfo{ 7048 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7049 }, 7050 outputs: []outputInfo{ 7051 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7052 }, 7053 }, 7054 }, 7055 { 7056 name: "MOVBstore", 7057 auxType: auxSymOff, 7058 argLen: 3, 7059 faultOnNilArg0: true, 7060 symEffect: SymWrite, 7061 asm: x86.AMOVB, 7062 reg: regInfo{ 7063 inputs: []inputInfo{ 7064 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7065 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7066 }, 7067 }, 7068 }, 7069 { 7070 name: "MOVWstore", 7071 auxType: auxSymOff, 7072 argLen: 3, 7073 faultOnNilArg0: true, 7074 symEffect: SymWrite, 7075 asm: x86.AMOVW, 7076 reg: regInfo{ 7077 inputs: []inputInfo{ 7078 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7079 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7080 }, 7081 }, 7082 }, 7083 { 7084 name: "MOVLstore", 7085 auxType: auxSymOff, 7086 argLen: 3, 7087 faultOnNilArg0: true, 7088 symEffect: SymWrite, 7089 asm: x86.AMOVL, 7090 reg: regInfo{ 7091 inputs: []inputInfo{ 7092 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7093 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7094 }, 7095 }, 7096 }, 7097 { 7098 name: "MOVQstore", 7099 auxType: auxSymOff, 7100 argLen: 3, 7101 faultOnNilArg0: true, 7102 symEffect: SymWrite, 7103 asm: x86.AMOVQ, 7104 reg: regInfo{ 7105 inputs: []inputInfo{ 7106 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7107 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7108 }, 7109 }, 7110 }, 7111 { 7112 name: "MOVOload", 7113 auxType: auxSymOff, 7114 argLen: 2, 7115 faultOnNilArg0: true, 7116 symEffect: SymRead, 7117 asm: x86.AMOVUPS, 7118 reg: regInfo{ 7119 inputs: []inputInfo{ 7120 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7121 }, 7122 outputs: []outputInfo{ 7123 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7124 }, 7125 }, 7126 }, 7127 { 7128 name: "MOVOstore", 7129 auxType: auxSymOff, 7130 argLen: 3, 7131 faultOnNilArg0: true, 7132 symEffect: SymWrite, 7133 asm: x86.AMOVUPS, 7134 reg: regInfo{ 7135 inputs: []inputInfo{ 7136 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7137 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7138 }, 7139 }, 7140 }, 7141 { 7142 name: "MOVBloadidx1", 7143 auxType: auxSymOff, 7144 argLen: 3, 7145 commutative: true, 7146 symEffect: SymRead, 7147 asm: x86.AMOVBLZX, 7148 reg: regInfo{ 7149 inputs: []inputInfo{ 7150 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7151 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7152 }, 7153 outputs: []outputInfo{ 7154 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7155 }, 7156 }, 7157 }, 7158 { 7159 name: "MOVWloadidx1", 7160 auxType: auxSymOff, 7161 argLen: 3, 7162 commutative: true, 7163 symEffect: SymRead, 7164 asm: x86.AMOVWLZX, 7165 reg: regInfo{ 7166 inputs: []inputInfo{ 7167 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7168 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7169 }, 7170 outputs: []outputInfo{ 7171 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7172 }, 7173 }, 7174 }, 7175 { 7176 name: "MOVWloadidx2", 7177 auxType: auxSymOff, 7178 argLen: 3, 7179 symEffect: SymRead, 7180 asm: x86.AMOVWLZX, 7181 reg: regInfo{ 7182 inputs: []inputInfo{ 7183 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7184 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7185 }, 7186 outputs: []outputInfo{ 7187 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7188 }, 7189 }, 7190 }, 7191 { 7192 name: "MOVLloadidx1", 7193 auxType: auxSymOff, 7194 argLen: 3, 7195 commutative: true, 7196 symEffect: SymRead, 7197 asm: x86.AMOVL, 7198 reg: regInfo{ 7199 inputs: []inputInfo{ 7200 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7201 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7202 }, 7203 outputs: []outputInfo{ 7204 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7205 }, 7206 }, 7207 }, 7208 { 7209 name: "MOVLloadidx4", 7210 auxType: auxSymOff, 7211 argLen: 3, 7212 symEffect: SymRead, 7213 asm: x86.AMOVL, 7214 reg: regInfo{ 7215 inputs: []inputInfo{ 7216 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7217 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7218 }, 7219 outputs: []outputInfo{ 7220 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7221 }, 7222 }, 7223 }, 7224 { 7225 name: "MOVQloadidx1", 7226 auxType: auxSymOff, 7227 argLen: 3, 7228 commutative: true, 7229 symEffect: SymRead, 7230 asm: x86.AMOVQ, 7231 reg: regInfo{ 7232 inputs: []inputInfo{ 7233 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7234 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7235 }, 7236 outputs: []outputInfo{ 7237 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7238 }, 7239 }, 7240 }, 7241 { 7242 name: "MOVQloadidx8", 7243 auxType: auxSymOff, 7244 argLen: 3, 7245 symEffect: SymRead, 7246 asm: x86.AMOVQ, 7247 reg: regInfo{ 7248 inputs: []inputInfo{ 7249 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7250 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7251 }, 7252 outputs: []outputInfo{ 7253 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7254 }, 7255 }, 7256 }, 7257 { 7258 name: "MOVBstoreidx1", 7259 auxType: auxSymOff, 7260 argLen: 4, 7261 symEffect: SymWrite, 7262 asm: x86.AMOVB, 7263 reg: regInfo{ 7264 inputs: []inputInfo{ 7265 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7266 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7267 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7268 }, 7269 }, 7270 }, 7271 { 7272 name: "MOVWstoreidx1", 7273 auxType: auxSymOff, 7274 argLen: 4, 7275 symEffect: SymWrite, 7276 asm: x86.AMOVW, 7277 reg: regInfo{ 7278 inputs: []inputInfo{ 7279 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7280 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7281 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7282 }, 7283 }, 7284 }, 7285 { 7286 name: "MOVWstoreidx2", 7287 auxType: auxSymOff, 7288 argLen: 4, 7289 symEffect: SymWrite, 7290 asm: x86.AMOVW, 7291 reg: regInfo{ 7292 inputs: []inputInfo{ 7293 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7294 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7295 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7296 }, 7297 }, 7298 }, 7299 { 7300 name: "MOVLstoreidx1", 7301 auxType: auxSymOff, 7302 argLen: 4, 7303 symEffect: SymWrite, 7304 asm: x86.AMOVL, 7305 reg: regInfo{ 7306 inputs: []inputInfo{ 7307 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7308 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7309 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7310 }, 7311 }, 7312 }, 7313 { 7314 name: "MOVLstoreidx4", 7315 auxType: auxSymOff, 7316 argLen: 4, 7317 symEffect: SymWrite, 7318 asm: x86.AMOVL, 7319 reg: regInfo{ 7320 inputs: []inputInfo{ 7321 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7322 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7323 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7324 }, 7325 }, 7326 }, 7327 { 7328 name: "MOVQstoreidx1", 7329 auxType: auxSymOff, 7330 argLen: 4, 7331 symEffect: SymWrite, 7332 asm: x86.AMOVQ, 7333 reg: regInfo{ 7334 inputs: []inputInfo{ 7335 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7336 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7337 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7338 }, 7339 }, 7340 }, 7341 { 7342 name: "MOVQstoreidx8", 7343 auxType: auxSymOff, 7344 argLen: 4, 7345 symEffect: SymWrite, 7346 asm: x86.AMOVQ, 7347 reg: regInfo{ 7348 inputs: []inputInfo{ 7349 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7350 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7351 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7352 }, 7353 }, 7354 }, 7355 { 7356 name: "MOVBstoreconst", 7357 auxType: auxSymValAndOff, 7358 argLen: 2, 7359 faultOnNilArg0: true, 7360 symEffect: SymWrite, 7361 asm: x86.AMOVB, 7362 reg: regInfo{ 7363 inputs: []inputInfo{ 7364 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7365 }, 7366 }, 7367 }, 7368 { 7369 name: "MOVWstoreconst", 7370 auxType: auxSymValAndOff, 7371 argLen: 2, 7372 faultOnNilArg0: true, 7373 symEffect: SymWrite, 7374 asm: x86.AMOVW, 7375 reg: regInfo{ 7376 inputs: []inputInfo{ 7377 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7378 }, 7379 }, 7380 }, 7381 { 7382 name: "MOVLstoreconst", 7383 auxType: auxSymValAndOff, 7384 argLen: 2, 7385 faultOnNilArg0: true, 7386 symEffect: SymWrite, 7387 asm: x86.AMOVL, 7388 reg: regInfo{ 7389 inputs: []inputInfo{ 7390 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7391 }, 7392 }, 7393 }, 7394 { 7395 name: "MOVQstoreconst", 7396 auxType: auxSymValAndOff, 7397 argLen: 2, 7398 faultOnNilArg0: true, 7399 symEffect: SymWrite, 7400 asm: x86.AMOVQ, 7401 reg: regInfo{ 7402 inputs: []inputInfo{ 7403 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7404 }, 7405 }, 7406 }, 7407 { 7408 name: "MOVBstoreconstidx1", 7409 auxType: auxSymValAndOff, 7410 argLen: 3, 7411 symEffect: SymWrite, 7412 asm: x86.AMOVB, 7413 reg: regInfo{ 7414 inputs: []inputInfo{ 7415 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7416 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7417 }, 7418 }, 7419 }, 7420 { 7421 name: "MOVWstoreconstidx1", 7422 auxType: auxSymValAndOff, 7423 argLen: 3, 7424 symEffect: SymWrite, 7425 asm: x86.AMOVW, 7426 reg: regInfo{ 7427 inputs: []inputInfo{ 7428 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7429 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7430 }, 7431 }, 7432 }, 7433 { 7434 name: "MOVWstoreconstidx2", 7435 auxType: auxSymValAndOff, 7436 argLen: 3, 7437 symEffect: SymWrite, 7438 asm: x86.AMOVW, 7439 reg: regInfo{ 7440 inputs: []inputInfo{ 7441 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7442 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7443 }, 7444 }, 7445 }, 7446 { 7447 name: "MOVLstoreconstidx1", 7448 auxType: auxSymValAndOff, 7449 argLen: 3, 7450 symEffect: SymWrite, 7451 asm: x86.AMOVL, 7452 reg: regInfo{ 7453 inputs: []inputInfo{ 7454 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7455 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7456 }, 7457 }, 7458 }, 7459 { 7460 name: "MOVLstoreconstidx4", 7461 auxType: auxSymValAndOff, 7462 argLen: 3, 7463 symEffect: SymWrite, 7464 asm: x86.AMOVL, 7465 reg: regInfo{ 7466 inputs: []inputInfo{ 7467 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7468 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7469 }, 7470 }, 7471 }, 7472 { 7473 name: "MOVQstoreconstidx1", 7474 auxType: auxSymValAndOff, 7475 argLen: 3, 7476 symEffect: SymWrite, 7477 asm: x86.AMOVQ, 7478 reg: regInfo{ 7479 inputs: []inputInfo{ 7480 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7481 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7482 }, 7483 }, 7484 }, 7485 { 7486 name: "MOVQstoreconstidx8", 7487 auxType: auxSymValAndOff, 7488 argLen: 3, 7489 symEffect: SymWrite, 7490 asm: x86.AMOVQ, 7491 reg: regInfo{ 7492 inputs: []inputInfo{ 7493 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7494 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7495 }, 7496 }, 7497 }, 7498 { 7499 name: "DUFFZERO", 7500 auxType: auxInt64, 7501 argLen: 3, 7502 clobberFlags: true, 7503 faultOnNilArg0: true, 7504 reg: regInfo{ 7505 inputs: []inputInfo{ 7506 {0, 128}, // DI 7507 {1, 65536}, // X0 7508 }, 7509 clobbers: 128, // DI 7510 }, 7511 }, 7512 { 7513 name: "MOVOconst", 7514 auxType: auxInt128, 7515 argLen: 0, 7516 rematerializeable: true, 7517 reg: regInfo{ 7518 outputs: []outputInfo{ 7519 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7520 }, 7521 }, 7522 }, 7523 { 7524 name: "REPSTOSQ", 7525 argLen: 4, 7526 faultOnNilArg0: true, 7527 reg: regInfo{ 7528 inputs: []inputInfo{ 7529 {0, 128}, // DI 7530 {1, 2}, // CX 7531 {2, 1}, // AX 7532 }, 7533 clobbers: 130, // CX DI 7534 }, 7535 }, 7536 { 7537 name: "CALLstatic", 7538 auxType: auxSymOff, 7539 argLen: 1, 7540 clobberFlags: true, 7541 call: true, 7542 symEffect: SymNone, 7543 reg: regInfo{ 7544 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7545 }, 7546 }, 7547 { 7548 name: "CALLclosure", 7549 auxType: auxInt64, 7550 argLen: 3, 7551 clobberFlags: true, 7552 call: true, 7553 reg: regInfo{ 7554 inputs: []inputInfo{ 7555 {1, 4}, // DX 7556 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7557 }, 7558 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7559 }, 7560 }, 7561 { 7562 name: "CALLinter", 7563 auxType: auxInt64, 7564 argLen: 2, 7565 clobberFlags: true, 7566 call: true, 7567 reg: regInfo{ 7568 inputs: []inputInfo{ 7569 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7570 }, 7571 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7572 }, 7573 }, 7574 { 7575 name: "DUFFCOPY", 7576 auxType: auxInt64, 7577 argLen: 3, 7578 clobberFlags: true, 7579 faultOnNilArg0: true, 7580 faultOnNilArg1: true, 7581 reg: regInfo{ 7582 inputs: []inputInfo{ 7583 {0, 128}, // DI 7584 {1, 64}, // SI 7585 }, 7586 clobbers: 65728, // SI DI X0 7587 }, 7588 }, 7589 { 7590 name: "REPMOVSQ", 7591 argLen: 4, 7592 faultOnNilArg0: true, 7593 faultOnNilArg1: true, 7594 reg: regInfo{ 7595 inputs: []inputInfo{ 7596 {0, 128}, // DI 7597 {1, 64}, // SI 7598 {2, 2}, // CX 7599 }, 7600 clobbers: 194, // CX SI DI 7601 }, 7602 }, 7603 { 7604 name: "InvertFlags", 7605 argLen: 1, 7606 reg: regInfo{}, 7607 }, 7608 { 7609 name: "LoweredGetG", 7610 argLen: 1, 7611 reg: regInfo{ 7612 outputs: []outputInfo{ 7613 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7614 }, 7615 }, 7616 }, 7617 { 7618 name: "LoweredGetClosurePtr", 7619 argLen: 0, 7620 reg: regInfo{ 7621 outputs: []outputInfo{ 7622 {0, 4}, // DX 7623 }, 7624 }, 7625 }, 7626 { 7627 name: "LoweredNilCheck", 7628 argLen: 2, 7629 clobberFlags: true, 7630 nilCheck: true, 7631 faultOnNilArg0: true, 7632 reg: regInfo{ 7633 inputs: []inputInfo{ 7634 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7635 }, 7636 }, 7637 }, 7638 { 7639 name: "MOVQconvert", 7640 argLen: 2, 7641 asm: x86.AMOVQ, 7642 reg: regInfo{ 7643 inputs: []inputInfo{ 7644 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7645 }, 7646 outputs: []outputInfo{ 7647 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7648 }, 7649 }, 7650 }, 7651 { 7652 name: "MOVLconvert", 7653 argLen: 2, 7654 asm: x86.AMOVL, 7655 reg: regInfo{ 7656 inputs: []inputInfo{ 7657 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7658 }, 7659 outputs: []outputInfo{ 7660 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7661 }, 7662 }, 7663 }, 7664 { 7665 name: "FlagEQ", 7666 argLen: 0, 7667 reg: regInfo{}, 7668 }, 7669 { 7670 name: "FlagLT_ULT", 7671 argLen: 0, 7672 reg: regInfo{}, 7673 }, 7674 { 7675 name: "FlagLT_UGT", 7676 argLen: 0, 7677 reg: regInfo{}, 7678 }, 7679 { 7680 name: "FlagGT_UGT", 7681 argLen: 0, 7682 reg: regInfo{}, 7683 }, 7684 { 7685 name: "FlagGT_ULT", 7686 argLen: 0, 7687 reg: regInfo{}, 7688 }, 7689 { 7690 name: "MOVLatomicload", 7691 auxType: auxSymOff, 7692 argLen: 2, 7693 faultOnNilArg0: true, 7694 symEffect: SymRead, 7695 asm: x86.AMOVL, 7696 reg: regInfo{ 7697 inputs: []inputInfo{ 7698 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7699 }, 7700 outputs: []outputInfo{ 7701 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7702 }, 7703 }, 7704 }, 7705 { 7706 name: "MOVQatomicload", 7707 auxType: auxSymOff, 7708 argLen: 2, 7709 faultOnNilArg0: true, 7710 symEffect: SymRead, 7711 asm: x86.AMOVQ, 7712 reg: regInfo{ 7713 inputs: []inputInfo{ 7714 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7715 }, 7716 outputs: []outputInfo{ 7717 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7718 }, 7719 }, 7720 }, 7721 { 7722 name: "XCHGL", 7723 auxType: auxSymOff, 7724 argLen: 3, 7725 resultInArg0: true, 7726 faultOnNilArg1: true, 7727 hasSideEffects: true, 7728 symEffect: SymRdWr, 7729 asm: x86.AXCHGL, 7730 reg: regInfo{ 7731 inputs: []inputInfo{ 7732 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7733 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7734 }, 7735 outputs: []outputInfo{ 7736 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7737 }, 7738 }, 7739 }, 7740 { 7741 name: "XCHGQ", 7742 auxType: auxSymOff, 7743 argLen: 3, 7744 resultInArg0: true, 7745 faultOnNilArg1: true, 7746 hasSideEffects: true, 7747 symEffect: SymRdWr, 7748 asm: x86.AXCHGQ, 7749 reg: regInfo{ 7750 inputs: []inputInfo{ 7751 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7752 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7753 }, 7754 outputs: []outputInfo{ 7755 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7756 }, 7757 }, 7758 }, 7759 { 7760 name: "XADDLlock", 7761 auxType: auxSymOff, 7762 argLen: 3, 7763 resultInArg0: true, 7764 clobberFlags: true, 7765 faultOnNilArg1: true, 7766 hasSideEffects: true, 7767 symEffect: SymRdWr, 7768 asm: x86.AXADDL, 7769 reg: regInfo{ 7770 inputs: []inputInfo{ 7771 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7772 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7773 }, 7774 outputs: []outputInfo{ 7775 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7776 }, 7777 }, 7778 }, 7779 { 7780 name: "XADDQlock", 7781 auxType: auxSymOff, 7782 argLen: 3, 7783 resultInArg0: true, 7784 clobberFlags: true, 7785 faultOnNilArg1: true, 7786 hasSideEffects: true, 7787 symEffect: SymRdWr, 7788 asm: x86.AXADDQ, 7789 reg: regInfo{ 7790 inputs: []inputInfo{ 7791 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7792 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7793 }, 7794 outputs: []outputInfo{ 7795 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7796 }, 7797 }, 7798 }, 7799 { 7800 name: "AddTupleFirst32", 7801 argLen: 2, 7802 reg: regInfo{}, 7803 }, 7804 { 7805 name: "AddTupleFirst64", 7806 argLen: 2, 7807 reg: regInfo{}, 7808 }, 7809 { 7810 name: "CMPXCHGLlock", 7811 auxType: auxSymOff, 7812 argLen: 4, 7813 clobberFlags: true, 7814 faultOnNilArg0: true, 7815 hasSideEffects: true, 7816 symEffect: SymRdWr, 7817 asm: x86.ACMPXCHGL, 7818 reg: regInfo{ 7819 inputs: []inputInfo{ 7820 {1, 1}, // AX 7821 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7822 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7823 }, 7824 clobbers: 1, // AX 7825 outputs: []outputInfo{ 7826 {1, 0}, 7827 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7828 }, 7829 }, 7830 }, 7831 { 7832 name: "CMPXCHGQlock", 7833 auxType: auxSymOff, 7834 argLen: 4, 7835 clobberFlags: true, 7836 faultOnNilArg0: true, 7837 hasSideEffects: true, 7838 symEffect: SymRdWr, 7839 asm: x86.ACMPXCHGQ, 7840 reg: regInfo{ 7841 inputs: []inputInfo{ 7842 {1, 1}, // AX 7843 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7844 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7845 }, 7846 clobbers: 1, // AX 7847 outputs: []outputInfo{ 7848 {1, 0}, 7849 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7850 }, 7851 }, 7852 }, 7853 { 7854 name: "ANDBlock", 7855 auxType: auxSymOff, 7856 argLen: 3, 7857 clobberFlags: true, 7858 faultOnNilArg0: true, 7859 hasSideEffects: true, 7860 symEffect: SymRdWr, 7861 asm: x86.AANDB, 7862 reg: regInfo{ 7863 inputs: []inputInfo{ 7864 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7865 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7866 }, 7867 }, 7868 }, 7869 { 7870 name: "ORBlock", 7871 auxType: auxSymOff, 7872 argLen: 3, 7873 clobberFlags: true, 7874 faultOnNilArg0: true, 7875 hasSideEffects: true, 7876 symEffect: SymRdWr, 7877 asm: x86.AORB, 7878 reg: regInfo{ 7879 inputs: []inputInfo{ 7880 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7881 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7882 }, 7883 }, 7884 }, 7885 7886 { 7887 name: "ADD", 7888 argLen: 2, 7889 commutative: true, 7890 asm: arm.AADD, 7891 reg: regInfo{ 7892 inputs: []inputInfo{ 7893 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7894 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7895 }, 7896 outputs: []outputInfo{ 7897 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7898 }, 7899 }, 7900 }, 7901 { 7902 name: "ADDconst", 7903 auxType: auxInt32, 7904 argLen: 1, 7905 asm: arm.AADD, 7906 reg: regInfo{ 7907 inputs: []inputInfo{ 7908 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 7909 }, 7910 outputs: []outputInfo{ 7911 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7912 }, 7913 }, 7914 }, 7915 { 7916 name: "SUB", 7917 argLen: 2, 7918 asm: arm.ASUB, 7919 reg: regInfo{ 7920 inputs: []inputInfo{ 7921 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7922 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7923 }, 7924 outputs: []outputInfo{ 7925 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7926 }, 7927 }, 7928 }, 7929 { 7930 name: "SUBconst", 7931 auxType: auxInt32, 7932 argLen: 1, 7933 asm: arm.ASUB, 7934 reg: regInfo{ 7935 inputs: []inputInfo{ 7936 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7937 }, 7938 outputs: []outputInfo{ 7939 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7940 }, 7941 }, 7942 }, 7943 { 7944 name: "RSB", 7945 argLen: 2, 7946 asm: arm.ARSB, 7947 reg: regInfo{ 7948 inputs: []inputInfo{ 7949 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7950 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7951 }, 7952 outputs: []outputInfo{ 7953 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7954 }, 7955 }, 7956 }, 7957 { 7958 name: "RSBconst", 7959 auxType: auxInt32, 7960 argLen: 1, 7961 asm: arm.ARSB, 7962 reg: regInfo{ 7963 inputs: []inputInfo{ 7964 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7965 }, 7966 outputs: []outputInfo{ 7967 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7968 }, 7969 }, 7970 }, 7971 { 7972 name: "MUL", 7973 argLen: 2, 7974 commutative: true, 7975 asm: arm.AMUL, 7976 reg: regInfo{ 7977 inputs: []inputInfo{ 7978 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7979 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7980 }, 7981 outputs: []outputInfo{ 7982 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7983 }, 7984 }, 7985 }, 7986 { 7987 name: "HMUL", 7988 argLen: 2, 7989 commutative: true, 7990 asm: arm.AMULL, 7991 reg: regInfo{ 7992 inputs: []inputInfo{ 7993 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7994 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7995 }, 7996 outputs: []outputInfo{ 7997 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7998 }, 7999 }, 8000 }, 8001 { 8002 name: "HMULU", 8003 argLen: 2, 8004 commutative: true, 8005 asm: arm.AMULLU, 8006 reg: regInfo{ 8007 inputs: []inputInfo{ 8008 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8009 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8010 }, 8011 outputs: []outputInfo{ 8012 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8013 }, 8014 }, 8015 }, 8016 { 8017 name: "CALLudiv", 8018 auxType: auxSymOff, 8019 argLen: 2, 8020 clobberFlags: true, 8021 symEffect: SymNone, 8022 reg: regInfo{ 8023 inputs: []inputInfo{ 8024 {0, 2}, // R1 8025 {1, 1}, // R0 8026 }, 8027 clobbers: 16396, // R2 R3 R14 8028 outputs: []outputInfo{ 8029 {0, 1}, // R0 8030 {1, 2}, // R1 8031 }, 8032 }, 8033 }, 8034 { 8035 name: "ADDS", 8036 argLen: 2, 8037 commutative: true, 8038 asm: arm.AADD, 8039 reg: regInfo{ 8040 inputs: []inputInfo{ 8041 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8042 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8043 }, 8044 outputs: []outputInfo{ 8045 {1, 0}, 8046 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8047 }, 8048 }, 8049 }, 8050 { 8051 name: "ADDSconst", 8052 auxType: auxInt32, 8053 argLen: 1, 8054 asm: arm.AADD, 8055 reg: regInfo{ 8056 inputs: []inputInfo{ 8057 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8058 }, 8059 outputs: []outputInfo{ 8060 {1, 0}, 8061 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8062 }, 8063 }, 8064 }, 8065 { 8066 name: "ADC", 8067 argLen: 3, 8068 commutative: true, 8069 asm: arm.AADC, 8070 reg: regInfo{ 8071 inputs: []inputInfo{ 8072 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8073 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8074 }, 8075 outputs: []outputInfo{ 8076 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8077 }, 8078 }, 8079 }, 8080 { 8081 name: "ADCconst", 8082 auxType: auxInt32, 8083 argLen: 2, 8084 asm: arm.AADC, 8085 reg: regInfo{ 8086 inputs: []inputInfo{ 8087 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8088 }, 8089 outputs: []outputInfo{ 8090 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8091 }, 8092 }, 8093 }, 8094 { 8095 name: "SUBS", 8096 argLen: 2, 8097 asm: arm.ASUB, 8098 reg: regInfo{ 8099 inputs: []inputInfo{ 8100 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8101 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8102 }, 8103 outputs: []outputInfo{ 8104 {1, 0}, 8105 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8106 }, 8107 }, 8108 }, 8109 { 8110 name: "SUBSconst", 8111 auxType: auxInt32, 8112 argLen: 1, 8113 asm: arm.ASUB, 8114 reg: regInfo{ 8115 inputs: []inputInfo{ 8116 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8117 }, 8118 outputs: []outputInfo{ 8119 {1, 0}, 8120 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8121 }, 8122 }, 8123 }, 8124 { 8125 name: "RSBSconst", 8126 auxType: auxInt32, 8127 argLen: 1, 8128 asm: arm.ARSB, 8129 reg: regInfo{ 8130 inputs: []inputInfo{ 8131 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8132 }, 8133 outputs: []outputInfo{ 8134 {1, 0}, 8135 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8136 }, 8137 }, 8138 }, 8139 { 8140 name: "SBC", 8141 argLen: 3, 8142 asm: arm.ASBC, 8143 reg: regInfo{ 8144 inputs: []inputInfo{ 8145 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8146 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8147 }, 8148 outputs: []outputInfo{ 8149 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8150 }, 8151 }, 8152 }, 8153 { 8154 name: "SBCconst", 8155 auxType: auxInt32, 8156 argLen: 2, 8157 asm: arm.ASBC, 8158 reg: regInfo{ 8159 inputs: []inputInfo{ 8160 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8161 }, 8162 outputs: []outputInfo{ 8163 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8164 }, 8165 }, 8166 }, 8167 { 8168 name: "RSCconst", 8169 auxType: auxInt32, 8170 argLen: 2, 8171 asm: arm.ARSC, 8172 reg: regInfo{ 8173 inputs: []inputInfo{ 8174 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8175 }, 8176 outputs: []outputInfo{ 8177 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8178 }, 8179 }, 8180 }, 8181 { 8182 name: "MULLU", 8183 argLen: 2, 8184 commutative: true, 8185 asm: arm.AMULLU, 8186 reg: regInfo{ 8187 inputs: []inputInfo{ 8188 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8189 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8190 }, 8191 outputs: []outputInfo{ 8192 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8193 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8194 }, 8195 }, 8196 }, 8197 { 8198 name: "MULA", 8199 argLen: 3, 8200 asm: arm.AMULA, 8201 reg: regInfo{ 8202 inputs: []inputInfo{ 8203 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8204 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8205 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8206 }, 8207 outputs: []outputInfo{ 8208 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8209 }, 8210 }, 8211 }, 8212 { 8213 name: "ADDF", 8214 argLen: 2, 8215 commutative: true, 8216 asm: arm.AADDF, 8217 reg: regInfo{ 8218 inputs: []inputInfo{ 8219 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8220 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8221 }, 8222 outputs: []outputInfo{ 8223 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8224 }, 8225 }, 8226 }, 8227 { 8228 name: "ADDD", 8229 argLen: 2, 8230 commutative: true, 8231 asm: arm.AADDD, 8232 reg: regInfo{ 8233 inputs: []inputInfo{ 8234 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8235 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8236 }, 8237 outputs: []outputInfo{ 8238 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8239 }, 8240 }, 8241 }, 8242 { 8243 name: "SUBF", 8244 argLen: 2, 8245 asm: arm.ASUBF, 8246 reg: regInfo{ 8247 inputs: []inputInfo{ 8248 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8249 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8250 }, 8251 outputs: []outputInfo{ 8252 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8253 }, 8254 }, 8255 }, 8256 { 8257 name: "SUBD", 8258 argLen: 2, 8259 asm: arm.ASUBD, 8260 reg: regInfo{ 8261 inputs: []inputInfo{ 8262 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8263 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8264 }, 8265 outputs: []outputInfo{ 8266 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8267 }, 8268 }, 8269 }, 8270 { 8271 name: "MULF", 8272 argLen: 2, 8273 commutative: true, 8274 asm: arm.AMULF, 8275 reg: regInfo{ 8276 inputs: []inputInfo{ 8277 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8278 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8279 }, 8280 outputs: []outputInfo{ 8281 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8282 }, 8283 }, 8284 }, 8285 { 8286 name: "MULD", 8287 argLen: 2, 8288 commutative: true, 8289 asm: arm.AMULD, 8290 reg: regInfo{ 8291 inputs: []inputInfo{ 8292 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8293 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8294 }, 8295 outputs: []outputInfo{ 8296 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8297 }, 8298 }, 8299 }, 8300 { 8301 name: "DIVF", 8302 argLen: 2, 8303 asm: arm.ADIVF, 8304 reg: regInfo{ 8305 inputs: []inputInfo{ 8306 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8307 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8308 }, 8309 outputs: []outputInfo{ 8310 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8311 }, 8312 }, 8313 }, 8314 { 8315 name: "DIVD", 8316 argLen: 2, 8317 asm: arm.ADIVD, 8318 reg: regInfo{ 8319 inputs: []inputInfo{ 8320 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8321 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8322 }, 8323 outputs: []outputInfo{ 8324 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8325 }, 8326 }, 8327 }, 8328 { 8329 name: "AND", 8330 argLen: 2, 8331 commutative: true, 8332 asm: arm.AAND, 8333 reg: regInfo{ 8334 inputs: []inputInfo{ 8335 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8336 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8337 }, 8338 outputs: []outputInfo{ 8339 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8340 }, 8341 }, 8342 }, 8343 { 8344 name: "ANDconst", 8345 auxType: auxInt32, 8346 argLen: 1, 8347 asm: arm.AAND, 8348 reg: regInfo{ 8349 inputs: []inputInfo{ 8350 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8351 }, 8352 outputs: []outputInfo{ 8353 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8354 }, 8355 }, 8356 }, 8357 { 8358 name: "OR", 8359 argLen: 2, 8360 commutative: true, 8361 asm: arm.AORR, 8362 reg: regInfo{ 8363 inputs: []inputInfo{ 8364 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8365 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8366 }, 8367 outputs: []outputInfo{ 8368 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8369 }, 8370 }, 8371 }, 8372 { 8373 name: "ORconst", 8374 auxType: auxInt32, 8375 argLen: 1, 8376 asm: arm.AORR, 8377 reg: regInfo{ 8378 inputs: []inputInfo{ 8379 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8380 }, 8381 outputs: []outputInfo{ 8382 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8383 }, 8384 }, 8385 }, 8386 { 8387 name: "XOR", 8388 argLen: 2, 8389 commutative: true, 8390 asm: arm.AEOR, 8391 reg: regInfo{ 8392 inputs: []inputInfo{ 8393 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8394 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8395 }, 8396 outputs: []outputInfo{ 8397 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8398 }, 8399 }, 8400 }, 8401 { 8402 name: "XORconst", 8403 auxType: auxInt32, 8404 argLen: 1, 8405 asm: arm.AEOR, 8406 reg: regInfo{ 8407 inputs: []inputInfo{ 8408 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8409 }, 8410 outputs: []outputInfo{ 8411 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8412 }, 8413 }, 8414 }, 8415 { 8416 name: "BIC", 8417 argLen: 2, 8418 asm: arm.ABIC, 8419 reg: regInfo{ 8420 inputs: []inputInfo{ 8421 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8422 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8423 }, 8424 outputs: []outputInfo{ 8425 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8426 }, 8427 }, 8428 }, 8429 { 8430 name: "BICconst", 8431 auxType: auxInt32, 8432 argLen: 1, 8433 asm: arm.ABIC, 8434 reg: regInfo{ 8435 inputs: []inputInfo{ 8436 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8437 }, 8438 outputs: []outputInfo{ 8439 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8440 }, 8441 }, 8442 }, 8443 { 8444 name: "MVN", 8445 argLen: 1, 8446 asm: arm.AMVN, 8447 reg: regInfo{ 8448 inputs: []inputInfo{ 8449 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8450 }, 8451 outputs: []outputInfo{ 8452 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8453 }, 8454 }, 8455 }, 8456 { 8457 name: "NEGF", 8458 argLen: 1, 8459 asm: arm.ANEGF, 8460 reg: regInfo{ 8461 inputs: []inputInfo{ 8462 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8463 }, 8464 outputs: []outputInfo{ 8465 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8466 }, 8467 }, 8468 }, 8469 { 8470 name: "NEGD", 8471 argLen: 1, 8472 asm: arm.ANEGD, 8473 reg: regInfo{ 8474 inputs: []inputInfo{ 8475 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8476 }, 8477 outputs: []outputInfo{ 8478 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8479 }, 8480 }, 8481 }, 8482 { 8483 name: "SQRTD", 8484 argLen: 1, 8485 asm: arm.ASQRTD, 8486 reg: regInfo{ 8487 inputs: []inputInfo{ 8488 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8489 }, 8490 outputs: []outputInfo{ 8491 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8492 }, 8493 }, 8494 }, 8495 { 8496 name: "CLZ", 8497 argLen: 1, 8498 asm: arm.ACLZ, 8499 reg: regInfo{ 8500 inputs: []inputInfo{ 8501 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8502 }, 8503 outputs: []outputInfo{ 8504 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8505 }, 8506 }, 8507 }, 8508 { 8509 name: "REV", 8510 argLen: 1, 8511 asm: arm.AREV, 8512 reg: regInfo{ 8513 inputs: []inputInfo{ 8514 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8515 }, 8516 outputs: []outputInfo{ 8517 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8518 }, 8519 }, 8520 }, 8521 { 8522 name: "RBIT", 8523 argLen: 1, 8524 asm: arm.ARBIT, 8525 reg: regInfo{ 8526 inputs: []inputInfo{ 8527 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8528 }, 8529 outputs: []outputInfo{ 8530 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8531 }, 8532 }, 8533 }, 8534 { 8535 name: "SLL", 8536 argLen: 2, 8537 asm: arm.ASLL, 8538 reg: regInfo{ 8539 inputs: []inputInfo{ 8540 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8541 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8542 }, 8543 outputs: []outputInfo{ 8544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8545 }, 8546 }, 8547 }, 8548 { 8549 name: "SLLconst", 8550 auxType: auxInt32, 8551 argLen: 1, 8552 asm: arm.ASLL, 8553 reg: regInfo{ 8554 inputs: []inputInfo{ 8555 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8556 }, 8557 outputs: []outputInfo{ 8558 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8559 }, 8560 }, 8561 }, 8562 { 8563 name: "SRL", 8564 argLen: 2, 8565 asm: arm.ASRL, 8566 reg: regInfo{ 8567 inputs: []inputInfo{ 8568 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8569 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8570 }, 8571 outputs: []outputInfo{ 8572 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8573 }, 8574 }, 8575 }, 8576 { 8577 name: "SRLconst", 8578 auxType: auxInt32, 8579 argLen: 1, 8580 asm: arm.ASRL, 8581 reg: regInfo{ 8582 inputs: []inputInfo{ 8583 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8584 }, 8585 outputs: []outputInfo{ 8586 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8587 }, 8588 }, 8589 }, 8590 { 8591 name: "SRA", 8592 argLen: 2, 8593 asm: arm.ASRA, 8594 reg: regInfo{ 8595 inputs: []inputInfo{ 8596 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8597 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8598 }, 8599 outputs: []outputInfo{ 8600 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8601 }, 8602 }, 8603 }, 8604 { 8605 name: "SRAconst", 8606 auxType: auxInt32, 8607 argLen: 1, 8608 asm: arm.ASRA, 8609 reg: regInfo{ 8610 inputs: []inputInfo{ 8611 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8612 }, 8613 outputs: []outputInfo{ 8614 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8615 }, 8616 }, 8617 }, 8618 { 8619 name: "SRRconst", 8620 auxType: auxInt32, 8621 argLen: 1, 8622 reg: regInfo{ 8623 inputs: []inputInfo{ 8624 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8625 }, 8626 outputs: []outputInfo{ 8627 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8628 }, 8629 }, 8630 }, 8631 { 8632 name: "ADDshiftLL", 8633 auxType: auxInt32, 8634 argLen: 2, 8635 asm: arm.AADD, 8636 reg: regInfo{ 8637 inputs: []inputInfo{ 8638 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8639 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8640 }, 8641 outputs: []outputInfo{ 8642 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8643 }, 8644 }, 8645 }, 8646 { 8647 name: "ADDshiftRL", 8648 auxType: auxInt32, 8649 argLen: 2, 8650 asm: arm.AADD, 8651 reg: regInfo{ 8652 inputs: []inputInfo{ 8653 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8654 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8655 }, 8656 outputs: []outputInfo{ 8657 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8658 }, 8659 }, 8660 }, 8661 { 8662 name: "ADDshiftRA", 8663 auxType: auxInt32, 8664 argLen: 2, 8665 asm: arm.AADD, 8666 reg: regInfo{ 8667 inputs: []inputInfo{ 8668 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8669 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8670 }, 8671 outputs: []outputInfo{ 8672 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8673 }, 8674 }, 8675 }, 8676 { 8677 name: "SUBshiftLL", 8678 auxType: auxInt32, 8679 argLen: 2, 8680 asm: arm.ASUB, 8681 reg: regInfo{ 8682 inputs: []inputInfo{ 8683 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8684 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8685 }, 8686 outputs: []outputInfo{ 8687 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8688 }, 8689 }, 8690 }, 8691 { 8692 name: "SUBshiftRL", 8693 auxType: auxInt32, 8694 argLen: 2, 8695 asm: arm.ASUB, 8696 reg: regInfo{ 8697 inputs: []inputInfo{ 8698 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8699 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8700 }, 8701 outputs: []outputInfo{ 8702 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8703 }, 8704 }, 8705 }, 8706 { 8707 name: "SUBshiftRA", 8708 auxType: auxInt32, 8709 argLen: 2, 8710 asm: arm.ASUB, 8711 reg: regInfo{ 8712 inputs: []inputInfo{ 8713 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8714 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8715 }, 8716 outputs: []outputInfo{ 8717 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8718 }, 8719 }, 8720 }, 8721 { 8722 name: "RSBshiftLL", 8723 auxType: auxInt32, 8724 argLen: 2, 8725 asm: arm.ARSB, 8726 reg: regInfo{ 8727 inputs: []inputInfo{ 8728 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8729 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8730 }, 8731 outputs: []outputInfo{ 8732 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8733 }, 8734 }, 8735 }, 8736 { 8737 name: "RSBshiftRL", 8738 auxType: auxInt32, 8739 argLen: 2, 8740 asm: arm.ARSB, 8741 reg: regInfo{ 8742 inputs: []inputInfo{ 8743 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8744 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8745 }, 8746 outputs: []outputInfo{ 8747 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8748 }, 8749 }, 8750 }, 8751 { 8752 name: "RSBshiftRA", 8753 auxType: auxInt32, 8754 argLen: 2, 8755 asm: arm.ARSB, 8756 reg: regInfo{ 8757 inputs: []inputInfo{ 8758 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8759 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8760 }, 8761 outputs: []outputInfo{ 8762 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8763 }, 8764 }, 8765 }, 8766 { 8767 name: "ANDshiftLL", 8768 auxType: auxInt32, 8769 argLen: 2, 8770 asm: arm.AAND, 8771 reg: regInfo{ 8772 inputs: []inputInfo{ 8773 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8774 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8775 }, 8776 outputs: []outputInfo{ 8777 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8778 }, 8779 }, 8780 }, 8781 { 8782 name: "ANDshiftRL", 8783 auxType: auxInt32, 8784 argLen: 2, 8785 asm: arm.AAND, 8786 reg: regInfo{ 8787 inputs: []inputInfo{ 8788 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8789 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8790 }, 8791 outputs: []outputInfo{ 8792 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8793 }, 8794 }, 8795 }, 8796 { 8797 name: "ANDshiftRA", 8798 auxType: auxInt32, 8799 argLen: 2, 8800 asm: arm.AAND, 8801 reg: regInfo{ 8802 inputs: []inputInfo{ 8803 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8804 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8805 }, 8806 outputs: []outputInfo{ 8807 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8808 }, 8809 }, 8810 }, 8811 { 8812 name: "ORshiftLL", 8813 auxType: auxInt32, 8814 argLen: 2, 8815 asm: arm.AORR, 8816 reg: regInfo{ 8817 inputs: []inputInfo{ 8818 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8819 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8820 }, 8821 outputs: []outputInfo{ 8822 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8823 }, 8824 }, 8825 }, 8826 { 8827 name: "ORshiftRL", 8828 auxType: auxInt32, 8829 argLen: 2, 8830 asm: arm.AORR, 8831 reg: regInfo{ 8832 inputs: []inputInfo{ 8833 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8834 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8835 }, 8836 outputs: []outputInfo{ 8837 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8838 }, 8839 }, 8840 }, 8841 { 8842 name: "ORshiftRA", 8843 auxType: auxInt32, 8844 argLen: 2, 8845 asm: arm.AORR, 8846 reg: regInfo{ 8847 inputs: []inputInfo{ 8848 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8849 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8850 }, 8851 outputs: []outputInfo{ 8852 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8853 }, 8854 }, 8855 }, 8856 { 8857 name: "XORshiftLL", 8858 auxType: auxInt32, 8859 argLen: 2, 8860 asm: arm.AEOR, 8861 reg: regInfo{ 8862 inputs: []inputInfo{ 8863 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8864 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8865 }, 8866 outputs: []outputInfo{ 8867 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8868 }, 8869 }, 8870 }, 8871 { 8872 name: "XORshiftRL", 8873 auxType: auxInt32, 8874 argLen: 2, 8875 asm: arm.AEOR, 8876 reg: regInfo{ 8877 inputs: []inputInfo{ 8878 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8879 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8880 }, 8881 outputs: []outputInfo{ 8882 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8883 }, 8884 }, 8885 }, 8886 { 8887 name: "XORshiftRA", 8888 auxType: auxInt32, 8889 argLen: 2, 8890 asm: arm.AEOR, 8891 reg: regInfo{ 8892 inputs: []inputInfo{ 8893 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8894 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8895 }, 8896 outputs: []outputInfo{ 8897 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8898 }, 8899 }, 8900 }, 8901 { 8902 name: "XORshiftRR", 8903 auxType: auxInt32, 8904 argLen: 2, 8905 asm: arm.AEOR, 8906 reg: regInfo{ 8907 inputs: []inputInfo{ 8908 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8909 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8910 }, 8911 outputs: []outputInfo{ 8912 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8913 }, 8914 }, 8915 }, 8916 { 8917 name: "BICshiftLL", 8918 auxType: auxInt32, 8919 argLen: 2, 8920 asm: arm.ABIC, 8921 reg: regInfo{ 8922 inputs: []inputInfo{ 8923 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8924 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8925 }, 8926 outputs: []outputInfo{ 8927 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8928 }, 8929 }, 8930 }, 8931 { 8932 name: "BICshiftRL", 8933 auxType: auxInt32, 8934 argLen: 2, 8935 asm: arm.ABIC, 8936 reg: regInfo{ 8937 inputs: []inputInfo{ 8938 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8939 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8940 }, 8941 outputs: []outputInfo{ 8942 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8943 }, 8944 }, 8945 }, 8946 { 8947 name: "BICshiftRA", 8948 auxType: auxInt32, 8949 argLen: 2, 8950 asm: arm.ABIC, 8951 reg: regInfo{ 8952 inputs: []inputInfo{ 8953 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8954 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8955 }, 8956 outputs: []outputInfo{ 8957 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8958 }, 8959 }, 8960 }, 8961 { 8962 name: "MVNshiftLL", 8963 auxType: auxInt32, 8964 argLen: 1, 8965 asm: arm.AMVN, 8966 reg: regInfo{ 8967 inputs: []inputInfo{ 8968 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8969 }, 8970 outputs: []outputInfo{ 8971 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8972 }, 8973 }, 8974 }, 8975 { 8976 name: "MVNshiftRL", 8977 auxType: auxInt32, 8978 argLen: 1, 8979 asm: arm.AMVN, 8980 reg: regInfo{ 8981 inputs: []inputInfo{ 8982 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8983 }, 8984 outputs: []outputInfo{ 8985 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8986 }, 8987 }, 8988 }, 8989 { 8990 name: "MVNshiftRA", 8991 auxType: auxInt32, 8992 argLen: 1, 8993 asm: arm.AMVN, 8994 reg: regInfo{ 8995 inputs: []inputInfo{ 8996 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8997 }, 8998 outputs: []outputInfo{ 8999 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9000 }, 9001 }, 9002 }, 9003 { 9004 name: "ADCshiftLL", 9005 auxType: auxInt32, 9006 argLen: 3, 9007 asm: arm.AADC, 9008 reg: regInfo{ 9009 inputs: []inputInfo{ 9010 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9011 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9012 }, 9013 outputs: []outputInfo{ 9014 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9015 }, 9016 }, 9017 }, 9018 { 9019 name: "ADCshiftRL", 9020 auxType: auxInt32, 9021 argLen: 3, 9022 asm: arm.AADC, 9023 reg: regInfo{ 9024 inputs: []inputInfo{ 9025 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9026 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9027 }, 9028 outputs: []outputInfo{ 9029 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9030 }, 9031 }, 9032 }, 9033 { 9034 name: "ADCshiftRA", 9035 auxType: auxInt32, 9036 argLen: 3, 9037 asm: arm.AADC, 9038 reg: regInfo{ 9039 inputs: []inputInfo{ 9040 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9041 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9042 }, 9043 outputs: []outputInfo{ 9044 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9045 }, 9046 }, 9047 }, 9048 { 9049 name: "SBCshiftLL", 9050 auxType: auxInt32, 9051 argLen: 3, 9052 asm: arm.ASBC, 9053 reg: regInfo{ 9054 inputs: []inputInfo{ 9055 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9056 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9057 }, 9058 outputs: []outputInfo{ 9059 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9060 }, 9061 }, 9062 }, 9063 { 9064 name: "SBCshiftRL", 9065 auxType: auxInt32, 9066 argLen: 3, 9067 asm: arm.ASBC, 9068 reg: regInfo{ 9069 inputs: []inputInfo{ 9070 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9071 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9072 }, 9073 outputs: []outputInfo{ 9074 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9075 }, 9076 }, 9077 }, 9078 { 9079 name: "SBCshiftRA", 9080 auxType: auxInt32, 9081 argLen: 3, 9082 asm: arm.ASBC, 9083 reg: regInfo{ 9084 inputs: []inputInfo{ 9085 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9086 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9087 }, 9088 outputs: []outputInfo{ 9089 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9090 }, 9091 }, 9092 }, 9093 { 9094 name: "RSCshiftLL", 9095 auxType: auxInt32, 9096 argLen: 3, 9097 asm: arm.ARSC, 9098 reg: regInfo{ 9099 inputs: []inputInfo{ 9100 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9101 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9102 }, 9103 outputs: []outputInfo{ 9104 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9105 }, 9106 }, 9107 }, 9108 { 9109 name: "RSCshiftRL", 9110 auxType: auxInt32, 9111 argLen: 3, 9112 asm: arm.ARSC, 9113 reg: regInfo{ 9114 inputs: []inputInfo{ 9115 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9116 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9117 }, 9118 outputs: []outputInfo{ 9119 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9120 }, 9121 }, 9122 }, 9123 { 9124 name: "RSCshiftRA", 9125 auxType: auxInt32, 9126 argLen: 3, 9127 asm: arm.ARSC, 9128 reg: regInfo{ 9129 inputs: []inputInfo{ 9130 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9131 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9132 }, 9133 outputs: []outputInfo{ 9134 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9135 }, 9136 }, 9137 }, 9138 { 9139 name: "ADDSshiftLL", 9140 auxType: auxInt32, 9141 argLen: 2, 9142 asm: arm.AADD, 9143 reg: regInfo{ 9144 inputs: []inputInfo{ 9145 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9146 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9147 }, 9148 outputs: []outputInfo{ 9149 {1, 0}, 9150 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9151 }, 9152 }, 9153 }, 9154 { 9155 name: "ADDSshiftRL", 9156 auxType: auxInt32, 9157 argLen: 2, 9158 asm: arm.AADD, 9159 reg: regInfo{ 9160 inputs: []inputInfo{ 9161 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9162 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9163 }, 9164 outputs: []outputInfo{ 9165 {1, 0}, 9166 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9167 }, 9168 }, 9169 }, 9170 { 9171 name: "ADDSshiftRA", 9172 auxType: auxInt32, 9173 argLen: 2, 9174 asm: arm.AADD, 9175 reg: regInfo{ 9176 inputs: []inputInfo{ 9177 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9178 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9179 }, 9180 outputs: []outputInfo{ 9181 {1, 0}, 9182 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9183 }, 9184 }, 9185 }, 9186 { 9187 name: "SUBSshiftLL", 9188 auxType: auxInt32, 9189 argLen: 2, 9190 asm: arm.ASUB, 9191 reg: regInfo{ 9192 inputs: []inputInfo{ 9193 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9194 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9195 }, 9196 outputs: []outputInfo{ 9197 {1, 0}, 9198 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9199 }, 9200 }, 9201 }, 9202 { 9203 name: "SUBSshiftRL", 9204 auxType: auxInt32, 9205 argLen: 2, 9206 asm: arm.ASUB, 9207 reg: regInfo{ 9208 inputs: []inputInfo{ 9209 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9210 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9211 }, 9212 outputs: []outputInfo{ 9213 {1, 0}, 9214 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9215 }, 9216 }, 9217 }, 9218 { 9219 name: "SUBSshiftRA", 9220 auxType: auxInt32, 9221 argLen: 2, 9222 asm: arm.ASUB, 9223 reg: regInfo{ 9224 inputs: []inputInfo{ 9225 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9226 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9227 }, 9228 outputs: []outputInfo{ 9229 {1, 0}, 9230 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9231 }, 9232 }, 9233 }, 9234 { 9235 name: "RSBSshiftLL", 9236 auxType: auxInt32, 9237 argLen: 2, 9238 asm: arm.ARSB, 9239 reg: regInfo{ 9240 inputs: []inputInfo{ 9241 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9242 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9243 }, 9244 outputs: []outputInfo{ 9245 {1, 0}, 9246 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9247 }, 9248 }, 9249 }, 9250 { 9251 name: "RSBSshiftRL", 9252 auxType: auxInt32, 9253 argLen: 2, 9254 asm: arm.ARSB, 9255 reg: regInfo{ 9256 inputs: []inputInfo{ 9257 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9258 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9259 }, 9260 outputs: []outputInfo{ 9261 {1, 0}, 9262 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9263 }, 9264 }, 9265 }, 9266 { 9267 name: "RSBSshiftRA", 9268 auxType: auxInt32, 9269 argLen: 2, 9270 asm: arm.ARSB, 9271 reg: regInfo{ 9272 inputs: []inputInfo{ 9273 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9274 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9275 }, 9276 outputs: []outputInfo{ 9277 {1, 0}, 9278 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9279 }, 9280 }, 9281 }, 9282 { 9283 name: "ADDshiftLLreg", 9284 argLen: 3, 9285 asm: arm.AADD, 9286 reg: regInfo{ 9287 inputs: []inputInfo{ 9288 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9289 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9290 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9291 }, 9292 outputs: []outputInfo{ 9293 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9294 }, 9295 }, 9296 }, 9297 { 9298 name: "ADDshiftRLreg", 9299 argLen: 3, 9300 asm: arm.AADD, 9301 reg: regInfo{ 9302 inputs: []inputInfo{ 9303 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9304 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9305 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9306 }, 9307 outputs: []outputInfo{ 9308 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9309 }, 9310 }, 9311 }, 9312 { 9313 name: "ADDshiftRAreg", 9314 argLen: 3, 9315 asm: arm.AADD, 9316 reg: regInfo{ 9317 inputs: []inputInfo{ 9318 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9319 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9320 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9321 }, 9322 outputs: []outputInfo{ 9323 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9324 }, 9325 }, 9326 }, 9327 { 9328 name: "SUBshiftLLreg", 9329 argLen: 3, 9330 asm: arm.ASUB, 9331 reg: regInfo{ 9332 inputs: []inputInfo{ 9333 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9334 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9335 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9336 }, 9337 outputs: []outputInfo{ 9338 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9339 }, 9340 }, 9341 }, 9342 { 9343 name: "SUBshiftRLreg", 9344 argLen: 3, 9345 asm: arm.ASUB, 9346 reg: regInfo{ 9347 inputs: []inputInfo{ 9348 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9349 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9350 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9351 }, 9352 outputs: []outputInfo{ 9353 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9354 }, 9355 }, 9356 }, 9357 { 9358 name: "SUBshiftRAreg", 9359 argLen: 3, 9360 asm: arm.ASUB, 9361 reg: regInfo{ 9362 inputs: []inputInfo{ 9363 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9364 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9365 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9366 }, 9367 outputs: []outputInfo{ 9368 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9369 }, 9370 }, 9371 }, 9372 { 9373 name: "RSBshiftLLreg", 9374 argLen: 3, 9375 asm: arm.ARSB, 9376 reg: regInfo{ 9377 inputs: []inputInfo{ 9378 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9379 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9380 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9381 }, 9382 outputs: []outputInfo{ 9383 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9384 }, 9385 }, 9386 }, 9387 { 9388 name: "RSBshiftRLreg", 9389 argLen: 3, 9390 asm: arm.ARSB, 9391 reg: regInfo{ 9392 inputs: []inputInfo{ 9393 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9394 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9395 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9396 }, 9397 outputs: []outputInfo{ 9398 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9399 }, 9400 }, 9401 }, 9402 { 9403 name: "RSBshiftRAreg", 9404 argLen: 3, 9405 asm: arm.ARSB, 9406 reg: regInfo{ 9407 inputs: []inputInfo{ 9408 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9409 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9410 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9411 }, 9412 outputs: []outputInfo{ 9413 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9414 }, 9415 }, 9416 }, 9417 { 9418 name: "ANDshiftLLreg", 9419 argLen: 3, 9420 asm: arm.AAND, 9421 reg: regInfo{ 9422 inputs: []inputInfo{ 9423 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9424 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9425 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9426 }, 9427 outputs: []outputInfo{ 9428 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9429 }, 9430 }, 9431 }, 9432 { 9433 name: "ANDshiftRLreg", 9434 argLen: 3, 9435 asm: arm.AAND, 9436 reg: regInfo{ 9437 inputs: []inputInfo{ 9438 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9439 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9440 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9441 }, 9442 outputs: []outputInfo{ 9443 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9444 }, 9445 }, 9446 }, 9447 { 9448 name: "ANDshiftRAreg", 9449 argLen: 3, 9450 asm: arm.AAND, 9451 reg: regInfo{ 9452 inputs: []inputInfo{ 9453 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9454 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9455 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9456 }, 9457 outputs: []outputInfo{ 9458 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9459 }, 9460 }, 9461 }, 9462 { 9463 name: "ORshiftLLreg", 9464 argLen: 3, 9465 asm: arm.AORR, 9466 reg: regInfo{ 9467 inputs: []inputInfo{ 9468 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9469 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9470 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9471 }, 9472 outputs: []outputInfo{ 9473 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9474 }, 9475 }, 9476 }, 9477 { 9478 name: "ORshiftRLreg", 9479 argLen: 3, 9480 asm: arm.AORR, 9481 reg: regInfo{ 9482 inputs: []inputInfo{ 9483 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9484 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9485 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9486 }, 9487 outputs: []outputInfo{ 9488 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9489 }, 9490 }, 9491 }, 9492 { 9493 name: "ORshiftRAreg", 9494 argLen: 3, 9495 asm: arm.AORR, 9496 reg: regInfo{ 9497 inputs: []inputInfo{ 9498 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9499 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9500 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9501 }, 9502 outputs: []outputInfo{ 9503 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9504 }, 9505 }, 9506 }, 9507 { 9508 name: "XORshiftLLreg", 9509 argLen: 3, 9510 asm: arm.AEOR, 9511 reg: regInfo{ 9512 inputs: []inputInfo{ 9513 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9514 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9515 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9516 }, 9517 outputs: []outputInfo{ 9518 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9519 }, 9520 }, 9521 }, 9522 { 9523 name: "XORshiftRLreg", 9524 argLen: 3, 9525 asm: arm.AEOR, 9526 reg: regInfo{ 9527 inputs: []inputInfo{ 9528 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9529 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9530 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9531 }, 9532 outputs: []outputInfo{ 9533 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9534 }, 9535 }, 9536 }, 9537 { 9538 name: "XORshiftRAreg", 9539 argLen: 3, 9540 asm: arm.AEOR, 9541 reg: regInfo{ 9542 inputs: []inputInfo{ 9543 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9544 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9545 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9546 }, 9547 outputs: []outputInfo{ 9548 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9549 }, 9550 }, 9551 }, 9552 { 9553 name: "BICshiftLLreg", 9554 argLen: 3, 9555 asm: arm.ABIC, 9556 reg: regInfo{ 9557 inputs: []inputInfo{ 9558 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9559 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9560 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9561 }, 9562 outputs: []outputInfo{ 9563 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9564 }, 9565 }, 9566 }, 9567 { 9568 name: "BICshiftRLreg", 9569 argLen: 3, 9570 asm: arm.ABIC, 9571 reg: regInfo{ 9572 inputs: []inputInfo{ 9573 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9574 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9575 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9576 }, 9577 outputs: []outputInfo{ 9578 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9579 }, 9580 }, 9581 }, 9582 { 9583 name: "BICshiftRAreg", 9584 argLen: 3, 9585 asm: arm.ABIC, 9586 reg: regInfo{ 9587 inputs: []inputInfo{ 9588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9589 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9590 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9591 }, 9592 outputs: []outputInfo{ 9593 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9594 }, 9595 }, 9596 }, 9597 { 9598 name: "MVNshiftLLreg", 9599 argLen: 2, 9600 asm: arm.AMVN, 9601 reg: regInfo{ 9602 inputs: []inputInfo{ 9603 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9604 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9605 }, 9606 outputs: []outputInfo{ 9607 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9608 }, 9609 }, 9610 }, 9611 { 9612 name: "MVNshiftRLreg", 9613 argLen: 2, 9614 asm: arm.AMVN, 9615 reg: regInfo{ 9616 inputs: []inputInfo{ 9617 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9618 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9619 }, 9620 outputs: []outputInfo{ 9621 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9622 }, 9623 }, 9624 }, 9625 { 9626 name: "MVNshiftRAreg", 9627 argLen: 2, 9628 asm: arm.AMVN, 9629 reg: regInfo{ 9630 inputs: []inputInfo{ 9631 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9632 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9633 }, 9634 outputs: []outputInfo{ 9635 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9636 }, 9637 }, 9638 }, 9639 { 9640 name: "ADCshiftLLreg", 9641 argLen: 4, 9642 asm: arm.AADC, 9643 reg: regInfo{ 9644 inputs: []inputInfo{ 9645 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9646 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9647 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9648 }, 9649 outputs: []outputInfo{ 9650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9651 }, 9652 }, 9653 }, 9654 { 9655 name: "ADCshiftRLreg", 9656 argLen: 4, 9657 asm: arm.AADC, 9658 reg: regInfo{ 9659 inputs: []inputInfo{ 9660 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9661 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9662 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9663 }, 9664 outputs: []outputInfo{ 9665 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9666 }, 9667 }, 9668 }, 9669 { 9670 name: "ADCshiftRAreg", 9671 argLen: 4, 9672 asm: arm.AADC, 9673 reg: regInfo{ 9674 inputs: []inputInfo{ 9675 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9676 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9677 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9678 }, 9679 outputs: []outputInfo{ 9680 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9681 }, 9682 }, 9683 }, 9684 { 9685 name: "SBCshiftLLreg", 9686 argLen: 4, 9687 asm: arm.ASBC, 9688 reg: regInfo{ 9689 inputs: []inputInfo{ 9690 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9691 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9692 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9693 }, 9694 outputs: []outputInfo{ 9695 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9696 }, 9697 }, 9698 }, 9699 { 9700 name: "SBCshiftRLreg", 9701 argLen: 4, 9702 asm: arm.ASBC, 9703 reg: regInfo{ 9704 inputs: []inputInfo{ 9705 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9706 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9707 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9708 }, 9709 outputs: []outputInfo{ 9710 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9711 }, 9712 }, 9713 }, 9714 { 9715 name: "SBCshiftRAreg", 9716 argLen: 4, 9717 asm: arm.ASBC, 9718 reg: regInfo{ 9719 inputs: []inputInfo{ 9720 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9721 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9722 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9723 }, 9724 outputs: []outputInfo{ 9725 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9726 }, 9727 }, 9728 }, 9729 { 9730 name: "RSCshiftLLreg", 9731 argLen: 4, 9732 asm: arm.ARSC, 9733 reg: regInfo{ 9734 inputs: []inputInfo{ 9735 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9736 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9737 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9738 }, 9739 outputs: []outputInfo{ 9740 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9741 }, 9742 }, 9743 }, 9744 { 9745 name: "RSCshiftRLreg", 9746 argLen: 4, 9747 asm: arm.ARSC, 9748 reg: regInfo{ 9749 inputs: []inputInfo{ 9750 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9751 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9752 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9753 }, 9754 outputs: []outputInfo{ 9755 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9756 }, 9757 }, 9758 }, 9759 { 9760 name: "RSCshiftRAreg", 9761 argLen: 4, 9762 asm: arm.ARSC, 9763 reg: regInfo{ 9764 inputs: []inputInfo{ 9765 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9766 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9767 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9768 }, 9769 outputs: []outputInfo{ 9770 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9771 }, 9772 }, 9773 }, 9774 { 9775 name: "ADDSshiftLLreg", 9776 argLen: 3, 9777 asm: arm.AADD, 9778 reg: regInfo{ 9779 inputs: []inputInfo{ 9780 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9781 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9782 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9783 }, 9784 outputs: []outputInfo{ 9785 {1, 0}, 9786 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9787 }, 9788 }, 9789 }, 9790 { 9791 name: "ADDSshiftRLreg", 9792 argLen: 3, 9793 asm: arm.AADD, 9794 reg: regInfo{ 9795 inputs: []inputInfo{ 9796 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9797 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9798 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9799 }, 9800 outputs: []outputInfo{ 9801 {1, 0}, 9802 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9803 }, 9804 }, 9805 }, 9806 { 9807 name: "ADDSshiftRAreg", 9808 argLen: 3, 9809 asm: arm.AADD, 9810 reg: regInfo{ 9811 inputs: []inputInfo{ 9812 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9813 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9814 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9815 }, 9816 outputs: []outputInfo{ 9817 {1, 0}, 9818 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9819 }, 9820 }, 9821 }, 9822 { 9823 name: "SUBSshiftLLreg", 9824 argLen: 3, 9825 asm: arm.ASUB, 9826 reg: regInfo{ 9827 inputs: []inputInfo{ 9828 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9829 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9830 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9831 }, 9832 outputs: []outputInfo{ 9833 {1, 0}, 9834 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9835 }, 9836 }, 9837 }, 9838 { 9839 name: "SUBSshiftRLreg", 9840 argLen: 3, 9841 asm: arm.ASUB, 9842 reg: regInfo{ 9843 inputs: []inputInfo{ 9844 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9845 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9846 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9847 }, 9848 outputs: []outputInfo{ 9849 {1, 0}, 9850 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9851 }, 9852 }, 9853 }, 9854 { 9855 name: "SUBSshiftRAreg", 9856 argLen: 3, 9857 asm: arm.ASUB, 9858 reg: regInfo{ 9859 inputs: []inputInfo{ 9860 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9861 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9862 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9863 }, 9864 outputs: []outputInfo{ 9865 {1, 0}, 9866 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9867 }, 9868 }, 9869 }, 9870 { 9871 name: "RSBSshiftLLreg", 9872 argLen: 3, 9873 asm: arm.ARSB, 9874 reg: regInfo{ 9875 inputs: []inputInfo{ 9876 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9877 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9878 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9879 }, 9880 outputs: []outputInfo{ 9881 {1, 0}, 9882 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9883 }, 9884 }, 9885 }, 9886 { 9887 name: "RSBSshiftRLreg", 9888 argLen: 3, 9889 asm: arm.ARSB, 9890 reg: regInfo{ 9891 inputs: []inputInfo{ 9892 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9893 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9894 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9895 }, 9896 outputs: []outputInfo{ 9897 {1, 0}, 9898 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9899 }, 9900 }, 9901 }, 9902 { 9903 name: "RSBSshiftRAreg", 9904 argLen: 3, 9905 asm: arm.ARSB, 9906 reg: regInfo{ 9907 inputs: []inputInfo{ 9908 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9909 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9910 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9911 }, 9912 outputs: []outputInfo{ 9913 {1, 0}, 9914 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9915 }, 9916 }, 9917 }, 9918 { 9919 name: "CMP", 9920 argLen: 2, 9921 asm: arm.ACMP, 9922 reg: regInfo{ 9923 inputs: []inputInfo{ 9924 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9925 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9926 }, 9927 }, 9928 }, 9929 { 9930 name: "CMPconst", 9931 auxType: auxInt32, 9932 argLen: 1, 9933 asm: arm.ACMP, 9934 reg: regInfo{ 9935 inputs: []inputInfo{ 9936 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9937 }, 9938 }, 9939 }, 9940 { 9941 name: "CMN", 9942 argLen: 2, 9943 asm: arm.ACMN, 9944 reg: regInfo{ 9945 inputs: []inputInfo{ 9946 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9947 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9948 }, 9949 }, 9950 }, 9951 { 9952 name: "CMNconst", 9953 auxType: auxInt32, 9954 argLen: 1, 9955 asm: arm.ACMN, 9956 reg: regInfo{ 9957 inputs: []inputInfo{ 9958 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9959 }, 9960 }, 9961 }, 9962 { 9963 name: "TST", 9964 argLen: 2, 9965 commutative: true, 9966 asm: arm.ATST, 9967 reg: regInfo{ 9968 inputs: []inputInfo{ 9969 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9970 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9971 }, 9972 }, 9973 }, 9974 { 9975 name: "TSTconst", 9976 auxType: auxInt32, 9977 argLen: 1, 9978 asm: arm.ATST, 9979 reg: regInfo{ 9980 inputs: []inputInfo{ 9981 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9982 }, 9983 }, 9984 }, 9985 { 9986 name: "TEQ", 9987 argLen: 2, 9988 commutative: true, 9989 asm: arm.ATEQ, 9990 reg: regInfo{ 9991 inputs: []inputInfo{ 9992 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9993 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9994 }, 9995 }, 9996 }, 9997 { 9998 name: "TEQconst", 9999 auxType: auxInt32, 10000 argLen: 1, 10001 asm: arm.ATEQ, 10002 reg: regInfo{ 10003 inputs: []inputInfo{ 10004 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10005 }, 10006 }, 10007 }, 10008 { 10009 name: "CMPF", 10010 argLen: 2, 10011 asm: arm.ACMPF, 10012 reg: regInfo{ 10013 inputs: []inputInfo{ 10014 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10015 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10016 }, 10017 }, 10018 }, 10019 { 10020 name: "CMPD", 10021 argLen: 2, 10022 asm: arm.ACMPD, 10023 reg: regInfo{ 10024 inputs: []inputInfo{ 10025 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10026 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10027 }, 10028 }, 10029 }, 10030 { 10031 name: "CMPshiftLL", 10032 auxType: auxInt32, 10033 argLen: 2, 10034 asm: arm.ACMP, 10035 reg: regInfo{ 10036 inputs: []inputInfo{ 10037 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10038 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10039 }, 10040 }, 10041 }, 10042 { 10043 name: "CMPshiftRL", 10044 auxType: auxInt32, 10045 argLen: 2, 10046 asm: arm.ACMP, 10047 reg: regInfo{ 10048 inputs: []inputInfo{ 10049 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10050 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10051 }, 10052 }, 10053 }, 10054 { 10055 name: "CMPshiftRA", 10056 auxType: auxInt32, 10057 argLen: 2, 10058 asm: arm.ACMP, 10059 reg: regInfo{ 10060 inputs: []inputInfo{ 10061 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10062 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10063 }, 10064 }, 10065 }, 10066 { 10067 name: "CMPshiftLLreg", 10068 argLen: 3, 10069 asm: arm.ACMP, 10070 reg: regInfo{ 10071 inputs: []inputInfo{ 10072 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10073 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10074 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10075 }, 10076 }, 10077 }, 10078 { 10079 name: "CMPshiftRLreg", 10080 argLen: 3, 10081 asm: arm.ACMP, 10082 reg: regInfo{ 10083 inputs: []inputInfo{ 10084 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10085 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10086 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10087 }, 10088 }, 10089 }, 10090 { 10091 name: "CMPshiftRAreg", 10092 argLen: 3, 10093 asm: arm.ACMP, 10094 reg: regInfo{ 10095 inputs: []inputInfo{ 10096 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10097 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10098 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10099 }, 10100 }, 10101 }, 10102 { 10103 name: "CMPF0", 10104 argLen: 1, 10105 asm: arm.ACMPF, 10106 reg: regInfo{ 10107 inputs: []inputInfo{ 10108 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10109 }, 10110 }, 10111 }, 10112 { 10113 name: "CMPD0", 10114 argLen: 1, 10115 asm: arm.ACMPD, 10116 reg: regInfo{ 10117 inputs: []inputInfo{ 10118 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10119 }, 10120 }, 10121 }, 10122 { 10123 name: "MOVWconst", 10124 auxType: auxInt32, 10125 argLen: 0, 10126 rematerializeable: true, 10127 asm: arm.AMOVW, 10128 reg: regInfo{ 10129 outputs: []outputInfo{ 10130 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10131 }, 10132 }, 10133 }, 10134 { 10135 name: "MOVFconst", 10136 auxType: auxFloat64, 10137 argLen: 0, 10138 rematerializeable: true, 10139 asm: arm.AMOVF, 10140 reg: regInfo{ 10141 outputs: []outputInfo{ 10142 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10143 }, 10144 }, 10145 }, 10146 { 10147 name: "MOVDconst", 10148 auxType: auxFloat64, 10149 argLen: 0, 10150 rematerializeable: true, 10151 asm: arm.AMOVD, 10152 reg: regInfo{ 10153 outputs: []outputInfo{ 10154 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10155 }, 10156 }, 10157 }, 10158 { 10159 name: "MOVWaddr", 10160 auxType: auxSymOff, 10161 argLen: 1, 10162 rematerializeable: true, 10163 symEffect: SymAddr, 10164 asm: arm.AMOVW, 10165 reg: regInfo{ 10166 inputs: []inputInfo{ 10167 {0, 4294975488}, // SP SB 10168 }, 10169 outputs: []outputInfo{ 10170 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10171 }, 10172 }, 10173 }, 10174 { 10175 name: "MOVBload", 10176 auxType: auxSymOff, 10177 argLen: 2, 10178 faultOnNilArg0: true, 10179 symEffect: SymRead, 10180 asm: arm.AMOVB, 10181 reg: regInfo{ 10182 inputs: []inputInfo{ 10183 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10184 }, 10185 outputs: []outputInfo{ 10186 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10187 }, 10188 }, 10189 }, 10190 { 10191 name: "MOVBUload", 10192 auxType: auxSymOff, 10193 argLen: 2, 10194 faultOnNilArg0: true, 10195 symEffect: SymRead, 10196 asm: arm.AMOVBU, 10197 reg: regInfo{ 10198 inputs: []inputInfo{ 10199 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10200 }, 10201 outputs: []outputInfo{ 10202 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10203 }, 10204 }, 10205 }, 10206 { 10207 name: "MOVHload", 10208 auxType: auxSymOff, 10209 argLen: 2, 10210 faultOnNilArg0: true, 10211 symEffect: SymRead, 10212 asm: arm.AMOVH, 10213 reg: regInfo{ 10214 inputs: []inputInfo{ 10215 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10216 }, 10217 outputs: []outputInfo{ 10218 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10219 }, 10220 }, 10221 }, 10222 { 10223 name: "MOVHUload", 10224 auxType: auxSymOff, 10225 argLen: 2, 10226 faultOnNilArg0: true, 10227 symEffect: SymRead, 10228 asm: arm.AMOVHU, 10229 reg: regInfo{ 10230 inputs: []inputInfo{ 10231 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10232 }, 10233 outputs: []outputInfo{ 10234 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10235 }, 10236 }, 10237 }, 10238 { 10239 name: "MOVWload", 10240 auxType: auxSymOff, 10241 argLen: 2, 10242 faultOnNilArg0: true, 10243 symEffect: SymRead, 10244 asm: arm.AMOVW, 10245 reg: regInfo{ 10246 inputs: []inputInfo{ 10247 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10248 }, 10249 outputs: []outputInfo{ 10250 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10251 }, 10252 }, 10253 }, 10254 { 10255 name: "MOVFload", 10256 auxType: auxSymOff, 10257 argLen: 2, 10258 faultOnNilArg0: true, 10259 symEffect: SymRead, 10260 asm: arm.AMOVF, 10261 reg: regInfo{ 10262 inputs: []inputInfo{ 10263 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10264 }, 10265 outputs: []outputInfo{ 10266 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10267 }, 10268 }, 10269 }, 10270 { 10271 name: "MOVDload", 10272 auxType: auxSymOff, 10273 argLen: 2, 10274 faultOnNilArg0: true, 10275 symEffect: SymRead, 10276 asm: arm.AMOVD, 10277 reg: regInfo{ 10278 inputs: []inputInfo{ 10279 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10280 }, 10281 outputs: []outputInfo{ 10282 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10283 }, 10284 }, 10285 }, 10286 { 10287 name: "MOVBstore", 10288 auxType: auxSymOff, 10289 argLen: 3, 10290 faultOnNilArg0: true, 10291 symEffect: SymWrite, 10292 asm: arm.AMOVB, 10293 reg: regInfo{ 10294 inputs: []inputInfo{ 10295 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10296 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10297 }, 10298 }, 10299 }, 10300 { 10301 name: "MOVHstore", 10302 auxType: auxSymOff, 10303 argLen: 3, 10304 faultOnNilArg0: true, 10305 symEffect: SymWrite, 10306 asm: arm.AMOVH, 10307 reg: regInfo{ 10308 inputs: []inputInfo{ 10309 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10310 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10311 }, 10312 }, 10313 }, 10314 { 10315 name: "MOVWstore", 10316 auxType: auxSymOff, 10317 argLen: 3, 10318 faultOnNilArg0: true, 10319 symEffect: SymWrite, 10320 asm: arm.AMOVW, 10321 reg: regInfo{ 10322 inputs: []inputInfo{ 10323 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10324 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10325 }, 10326 }, 10327 }, 10328 { 10329 name: "MOVFstore", 10330 auxType: auxSymOff, 10331 argLen: 3, 10332 faultOnNilArg0: true, 10333 symEffect: SymWrite, 10334 asm: arm.AMOVF, 10335 reg: regInfo{ 10336 inputs: []inputInfo{ 10337 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10338 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10339 }, 10340 }, 10341 }, 10342 { 10343 name: "MOVDstore", 10344 auxType: auxSymOff, 10345 argLen: 3, 10346 faultOnNilArg0: true, 10347 symEffect: SymWrite, 10348 asm: arm.AMOVD, 10349 reg: regInfo{ 10350 inputs: []inputInfo{ 10351 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10352 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10353 }, 10354 }, 10355 }, 10356 { 10357 name: "MOVWloadidx", 10358 argLen: 3, 10359 asm: arm.AMOVW, 10360 reg: regInfo{ 10361 inputs: []inputInfo{ 10362 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10363 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10364 }, 10365 outputs: []outputInfo{ 10366 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10367 }, 10368 }, 10369 }, 10370 { 10371 name: "MOVWloadshiftLL", 10372 auxType: auxInt32, 10373 argLen: 3, 10374 asm: arm.AMOVW, 10375 reg: regInfo{ 10376 inputs: []inputInfo{ 10377 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10378 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10379 }, 10380 outputs: []outputInfo{ 10381 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10382 }, 10383 }, 10384 }, 10385 { 10386 name: "MOVWloadshiftRL", 10387 auxType: auxInt32, 10388 argLen: 3, 10389 asm: arm.AMOVW, 10390 reg: regInfo{ 10391 inputs: []inputInfo{ 10392 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10393 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10394 }, 10395 outputs: []outputInfo{ 10396 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10397 }, 10398 }, 10399 }, 10400 { 10401 name: "MOVWloadshiftRA", 10402 auxType: auxInt32, 10403 argLen: 3, 10404 asm: arm.AMOVW, 10405 reg: regInfo{ 10406 inputs: []inputInfo{ 10407 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10408 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10409 }, 10410 outputs: []outputInfo{ 10411 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10412 }, 10413 }, 10414 }, 10415 { 10416 name: "MOVWstoreidx", 10417 argLen: 4, 10418 asm: arm.AMOVW, 10419 reg: regInfo{ 10420 inputs: []inputInfo{ 10421 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10422 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10423 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10424 }, 10425 }, 10426 }, 10427 { 10428 name: "MOVWstoreshiftLL", 10429 auxType: auxInt32, 10430 argLen: 4, 10431 asm: arm.AMOVW, 10432 reg: regInfo{ 10433 inputs: []inputInfo{ 10434 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10435 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10436 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10437 }, 10438 }, 10439 }, 10440 { 10441 name: "MOVWstoreshiftRL", 10442 auxType: auxInt32, 10443 argLen: 4, 10444 asm: arm.AMOVW, 10445 reg: regInfo{ 10446 inputs: []inputInfo{ 10447 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10448 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10449 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10450 }, 10451 }, 10452 }, 10453 { 10454 name: "MOVWstoreshiftRA", 10455 auxType: auxInt32, 10456 argLen: 4, 10457 asm: arm.AMOVW, 10458 reg: regInfo{ 10459 inputs: []inputInfo{ 10460 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10461 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10462 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10463 }, 10464 }, 10465 }, 10466 { 10467 name: "MOVBreg", 10468 argLen: 1, 10469 asm: arm.AMOVBS, 10470 reg: regInfo{ 10471 inputs: []inputInfo{ 10472 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10473 }, 10474 outputs: []outputInfo{ 10475 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10476 }, 10477 }, 10478 }, 10479 { 10480 name: "MOVBUreg", 10481 argLen: 1, 10482 asm: arm.AMOVBU, 10483 reg: regInfo{ 10484 inputs: []inputInfo{ 10485 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10486 }, 10487 outputs: []outputInfo{ 10488 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10489 }, 10490 }, 10491 }, 10492 { 10493 name: "MOVHreg", 10494 argLen: 1, 10495 asm: arm.AMOVHS, 10496 reg: regInfo{ 10497 inputs: []inputInfo{ 10498 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10499 }, 10500 outputs: []outputInfo{ 10501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10502 }, 10503 }, 10504 }, 10505 { 10506 name: "MOVHUreg", 10507 argLen: 1, 10508 asm: arm.AMOVHU, 10509 reg: regInfo{ 10510 inputs: []inputInfo{ 10511 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10512 }, 10513 outputs: []outputInfo{ 10514 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10515 }, 10516 }, 10517 }, 10518 { 10519 name: "MOVWreg", 10520 argLen: 1, 10521 asm: arm.AMOVW, 10522 reg: regInfo{ 10523 inputs: []inputInfo{ 10524 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10525 }, 10526 outputs: []outputInfo{ 10527 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10528 }, 10529 }, 10530 }, 10531 { 10532 name: "MOVWnop", 10533 argLen: 1, 10534 resultInArg0: true, 10535 reg: regInfo{ 10536 inputs: []inputInfo{ 10537 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10538 }, 10539 outputs: []outputInfo{ 10540 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10541 }, 10542 }, 10543 }, 10544 { 10545 name: "MOVWF", 10546 argLen: 1, 10547 asm: arm.AMOVWF, 10548 reg: regInfo{ 10549 inputs: []inputInfo{ 10550 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10551 }, 10552 clobbers: 2147483648, // F15 10553 outputs: []outputInfo{ 10554 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10555 }, 10556 }, 10557 }, 10558 { 10559 name: "MOVWD", 10560 argLen: 1, 10561 asm: arm.AMOVWD, 10562 reg: regInfo{ 10563 inputs: []inputInfo{ 10564 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10565 }, 10566 clobbers: 2147483648, // F15 10567 outputs: []outputInfo{ 10568 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10569 }, 10570 }, 10571 }, 10572 { 10573 name: "MOVWUF", 10574 argLen: 1, 10575 asm: arm.AMOVWF, 10576 reg: regInfo{ 10577 inputs: []inputInfo{ 10578 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10579 }, 10580 clobbers: 2147483648, // F15 10581 outputs: []outputInfo{ 10582 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10583 }, 10584 }, 10585 }, 10586 { 10587 name: "MOVWUD", 10588 argLen: 1, 10589 asm: arm.AMOVWD, 10590 reg: regInfo{ 10591 inputs: []inputInfo{ 10592 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10593 }, 10594 clobbers: 2147483648, // F15 10595 outputs: []outputInfo{ 10596 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10597 }, 10598 }, 10599 }, 10600 { 10601 name: "MOVFW", 10602 argLen: 1, 10603 asm: arm.AMOVFW, 10604 reg: regInfo{ 10605 inputs: []inputInfo{ 10606 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10607 }, 10608 clobbers: 2147483648, // F15 10609 outputs: []outputInfo{ 10610 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10611 }, 10612 }, 10613 }, 10614 { 10615 name: "MOVDW", 10616 argLen: 1, 10617 asm: arm.AMOVDW, 10618 reg: regInfo{ 10619 inputs: []inputInfo{ 10620 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10621 }, 10622 clobbers: 2147483648, // F15 10623 outputs: []outputInfo{ 10624 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10625 }, 10626 }, 10627 }, 10628 { 10629 name: "MOVFWU", 10630 argLen: 1, 10631 asm: arm.AMOVFW, 10632 reg: regInfo{ 10633 inputs: []inputInfo{ 10634 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10635 }, 10636 clobbers: 2147483648, // F15 10637 outputs: []outputInfo{ 10638 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10639 }, 10640 }, 10641 }, 10642 { 10643 name: "MOVDWU", 10644 argLen: 1, 10645 asm: arm.AMOVDW, 10646 reg: regInfo{ 10647 inputs: []inputInfo{ 10648 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10649 }, 10650 clobbers: 2147483648, // F15 10651 outputs: []outputInfo{ 10652 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10653 }, 10654 }, 10655 }, 10656 { 10657 name: "MOVFD", 10658 argLen: 1, 10659 asm: arm.AMOVFD, 10660 reg: regInfo{ 10661 inputs: []inputInfo{ 10662 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10663 }, 10664 outputs: []outputInfo{ 10665 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10666 }, 10667 }, 10668 }, 10669 { 10670 name: "MOVDF", 10671 argLen: 1, 10672 asm: arm.AMOVDF, 10673 reg: regInfo{ 10674 inputs: []inputInfo{ 10675 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10676 }, 10677 outputs: []outputInfo{ 10678 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10679 }, 10680 }, 10681 }, 10682 { 10683 name: "CMOVWHSconst", 10684 auxType: auxInt32, 10685 argLen: 2, 10686 resultInArg0: true, 10687 asm: arm.AMOVW, 10688 reg: regInfo{ 10689 inputs: []inputInfo{ 10690 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10691 }, 10692 outputs: []outputInfo{ 10693 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10694 }, 10695 }, 10696 }, 10697 { 10698 name: "CMOVWLSconst", 10699 auxType: auxInt32, 10700 argLen: 2, 10701 resultInArg0: true, 10702 asm: arm.AMOVW, 10703 reg: regInfo{ 10704 inputs: []inputInfo{ 10705 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10706 }, 10707 outputs: []outputInfo{ 10708 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10709 }, 10710 }, 10711 }, 10712 { 10713 name: "SRAcond", 10714 argLen: 3, 10715 asm: arm.ASRA, 10716 reg: regInfo{ 10717 inputs: []inputInfo{ 10718 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10719 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10720 }, 10721 outputs: []outputInfo{ 10722 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10723 }, 10724 }, 10725 }, 10726 { 10727 name: "CALLstatic", 10728 auxType: auxSymOff, 10729 argLen: 1, 10730 clobberFlags: true, 10731 call: true, 10732 symEffect: SymNone, 10733 reg: regInfo{ 10734 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10735 }, 10736 }, 10737 { 10738 name: "CALLclosure", 10739 auxType: auxInt64, 10740 argLen: 3, 10741 clobberFlags: true, 10742 call: true, 10743 reg: regInfo{ 10744 inputs: []inputInfo{ 10745 {1, 128}, // R7 10746 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 10747 }, 10748 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10749 }, 10750 }, 10751 { 10752 name: "CALLinter", 10753 auxType: auxInt64, 10754 argLen: 2, 10755 clobberFlags: true, 10756 call: true, 10757 reg: regInfo{ 10758 inputs: []inputInfo{ 10759 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10760 }, 10761 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10762 }, 10763 }, 10764 { 10765 name: "LoweredNilCheck", 10766 argLen: 2, 10767 nilCheck: true, 10768 faultOnNilArg0: true, 10769 reg: regInfo{ 10770 inputs: []inputInfo{ 10771 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10772 }, 10773 }, 10774 }, 10775 { 10776 name: "Equal", 10777 argLen: 1, 10778 reg: regInfo{ 10779 outputs: []outputInfo{ 10780 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10781 }, 10782 }, 10783 }, 10784 { 10785 name: "NotEqual", 10786 argLen: 1, 10787 reg: regInfo{ 10788 outputs: []outputInfo{ 10789 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10790 }, 10791 }, 10792 }, 10793 { 10794 name: "LessThan", 10795 argLen: 1, 10796 reg: regInfo{ 10797 outputs: []outputInfo{ 10798 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10799 }, 10800 }, 10801 }, 10802 { 10803 name: "LessEqual", 10804 argLen: 1, 10805 reg: regInfo{ 10806 outputs: []outputInfo{ 10807 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10808 }, 10809 }, 10810 }, 10811 { 10812 name: "GreaterThan", 10813 argLen: 1, 10814 reg: regInfo{ 10815 outputs: []outputInfo{ 10816 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10817 }, 10818 }, 10819 }, 10820 { 10821 name: "GreaterEqual", 10822 argLen: 1, 10823 reg: regInfo{ 10824 outputs: []outputInfo{ 10825 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10826 }, 10827 }, 10828 }, 10829 { 10830 name: "LessThanU", 10831 argLen: 1, 10832 reg: regInfo{ 10833 outputs: []outputInfo{ 10834 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10835 }, 10836 }, 10837 }, 10838 { 10839 name: "LessEqualU", 10840 argLen: 1, 10841 reg: regInfo{ 10842 outputs: []outputInfo{ 10843 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10844 }, 10845 }, 10846 }, 10847 { 10848 name: "GreaterThanU", 10849 argLen: 1, 10850 reg: regInfo{ 10851 outputs: []outputInfo{ 10852 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10853 }, 10854 }, 10855 }, 10856 { 10857 name: "GreaterEqualU", 10858 argLen: 1, 10859 reg: regInfo{ 10860 outputs: []outputInfo{ 10861 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10862 }, 10863 }, 10864 }, 10865 { 10866 name: "DUFFZERO", 10867 auxType: auxInt64, 10868 argLen: 3, 10869 faultOnNilArg0: true, 10870 reg: regInfo{ 10871 inputs: []inputInfo{ 10872 {0, 2}, // R1 10873 {1, 1}, // R0 10874 }, 10875 clobbers: 16386, // R1 R14 10876 }, 10877 }, 10878 { 10879 name: "DUFFCOPY", 10880 auxType: auxInt64, 10881 argLen: 3, 10882 faultOnNilArg0: true, 10883 faultOnNilArg1: true, 10884 reg: regInfo{ 10885 inputs: []inputInfo{ 10886 {0, 4}, // R2 10887 {1, 2}, // R1 10888 }, 10889 clobbers: 16391, // R0 R1 R2 R14 10890 }, 10891 }, 10892 { 10893 name: "LoweredZero", 10894 auxType: auxInt64, 10895 argLen: 4, 10896 clobberFlags: true, 10897 faultOnNilArg0: true, 10898 reg: regInfo{ 10899 inputs: []inputInfo{ 10900 {0, 2}, // R1 10901 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10902 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10903 }, 10904 clobbers: 2, // R1 10905 }, 10906 }, 10907 { 10908 name: "LoweredMove", 10909 auxType: auxInt64, 10910 argLen: 4, 10911 clobberFlags: true, 10912 faultOnNilArg0: true, 10913 faultOnNilArg1: true, 10914 reg: regInfo{ 10915 inputs: []inputInfo{ 10916 {0, 4}, // R2 10917 {1, 2}, // R1 10918 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10919 }, 10920 clobbers: 6, // R1 R2 10921 }, 10922 }, 10923 { 10924 name: "LoweredGetClosurePtr", 10925 argLen: 0, 10926 reg: regInfo{ 10927 outputs: []outputInfo{ 10928 {0, 128}, // R7 10929 }, 10930 }, 10931 }, 10932 { 10933 name: "MOVWconvert", 10934 argLen: 2, 10935 asm: arm.AMOVW, 10936 reg: regInfo{ 10937 inputs: []inputInfo{ 10938 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10939 }, 10940 outputs: []outputInfo{ 10941 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10942 }, 10943 }, 10944 }, 10945 { 10946 name: "FlagEQ", 10947 argLen: 0, 10948 reg: regInfo{}, 10949 }, 10950 { 10951 name: "FlagLT_ULT", 10952 argLen: 0, 10953 reg: regInfo{}, 10954 }, 10955 { 10956 name: "FlagLT_UGT", 10957 argLen: 0, 10958 reg: regInfo{}, 10959 }, 10960 { 10961 name: "FlagGT_UGT", 10962 argLen: 0, 10963 reg: regInfo{}, 10964 }, 10965 { 10966 name: "FlagGT_ULT", 10967 argLen: 0, 10968 reg: regInfo{}, 10969 }, 10970 { 10971 name: "InvertFlags", 10972 argLen: 1, 10973 reg: regInfo{}, 10974 }, 10975 10976 { 10977 name: "ADD", 10978 argLen: 2, 10979 commutative: true, 10980 asm: arm64.AADD, 10981 reg: regInfo{ 10982 inputs: []inputInfo{ 10983 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10984 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10985 }, 10986 outputs: []outputInfo{ 10987 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10988 }, 10989 }, 10990 }, 10991 { 10992 name: "ADDconst", 10993 auxType: auxInt64, 10994 argLen: 1, 10995 asm: arm64.AADD, 10996 reg: regInfo{ 10997 inputs: []inputInfo{ 10998 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 10999 }, 11000 outputs: []outputInfo{ 11001 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11002 }, 11003 }, 11004 }, 11005 { 11006 name: "SUB", 11007 argLen: 2, 11008 asm: arm64.ASUB, 11009 reg: regInfo{ 11010 inputs: []inputInfo{ 11011 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11012 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11013 }, 11014 outputs: []outputInfo{ 11015 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11016 }, 11017 }, 11018 }, 11019 { 11020 name: "SUBconst", 11021 auxType: auxInt64, 11022 argLen: 1, 11023 asm: arm64.ASUB, 11024 reg: regInfo{ 11025 inputs: []inputInfo{ 11026 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11027 }, 11028 outputs: []outputInfo{ 11029 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11030 }, 11031 }, 11032 }, 11033 { 11034 name: "MUL", 11035 argLen: 2, 11036 commutative: true, 11037 asm: arm64.AMUL, 11038 reg: regInfo{ 11039 inputs: []inputInfo{ 11040 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11041 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11042 }, 11043 outputs: []outputInfo{ 11044 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11045 }, 11046 }, 11047 }, 11048 { 11049 name: "MULW", 11050 argLen: 2, 11051 commutative: true, 11052 asm: arm64.AMULW, 11053 reg: regInfo{ 11054 inputs: []inputInfo{ 11055 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11056 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11057 }, 11058 outputs: []outputInfo{ 11059 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11060 }, 11061 }, 11062 }, 11063 { 11064 name: "MULH", 11065 argLen: 2, 11066 commutative: true, 11067 asm: arm64.ASMULH, 11068 reg: regInfo{ 11069 inputs: []inputInfo{ 11070 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11071 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11072 }, 11073 outputs: []outputInfo{ 11074 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11075 }, 11076 }, 11077 }, 11078 { 11079 name: "UMULH", 11080 argLen: 2, 11081 commutative: true, 11082 asm: arm64.AUMULH, 11083 reg: regInfo{ 11084 inputs: []inputInfo{ 11085 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11086 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11087 }, 11088 outputs: []outputInfo{ 11089 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11090 }, 11091 }, 11092 }, 11093 { 11094 name: "MULL", 11095 argLen: 2, 11096 commutative: true, 11097 asm: arm64.ASMULL, 11098 reg: regInfo{ 11099 inputs: []inputInfo{ 11100 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11101 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11102 }, 11103 outputs: []outputInfo{ 11104 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11105 }, 11106 }, 11107 }, 11108 { 11109 name: "UMULL", 11110 argLen: 2, 11111 commutative: true, 11112 asm: arm64.AUMULL, 11113 reg: regInfo{ 11114 inputs: []inputInfo{ 11115 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11116 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11117 }, 11118 outputs: []outputInfo{ 11119 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11120 }, 11121 }, 11122 }, 11123 { 11124 name: "DIV", 11125 argLen: 2, 11126 asm: arm64.ASDIV, 11127 reg: regInfo{ 11128 inputs: []inputInfo{ 11129 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11130 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11131 }, 11132 outputs: []outputInfo{ 11133 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11134 }, 11135 }, 11136 }, 11137 { 11138 name: "UDIV", 11139 argLen: 2, 11140 asm: arm64.AUDIV, 11141 reg: regInfo{ 11142 inputs: []inputInfo{ 11143 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11144 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11145 }, 11146 outputs: []outputInfo{ 11147 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11148 }, 11149 }, 11150 }, 11151 { 11152 name: "DIVW", 11153 argLen: 2, 11154 asm: arm64.ASDIVW, 11155 reg: regInfo{ 11156 inputs: []inputInfo{ 11157 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11158 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11159 }, 11160 outputs: []outputInfo{ 11161 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11162 }, 11163 }, 11164 }, 11165 { 11166 name: "UDIVW", 11167 argLen: 2, 11168 asm: arm64.AUDIVW, 11169 reg: regInfo{ 11170 inputs: []inputInfo{ 11171 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11172 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11173 }, 11174 outputs: []outputInfo{ 11175 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11176 }, 11177 }, 11178 }, 11179 { 11180 name: "MOD", 11181 argLen: 2, 11182 asm: arm64.AREM, 11183 reg: regInfo{ 11184 inputs: []inputInfo{ 11185 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11186 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11187 }, 11188 outputs: []outputInfo{ 11189 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11190 }, 11191 }, 11192 }, 11193 { 11194 name: "UMOD", 11195 argLen: 2, 11196 asm: arm64.AUREM, 11197 reg: regInfo{ 11198 inputs: []inputInfo{ 11199 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11200 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11201 }, 11202 outputs: []outputInfo{ 11203 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11204 }, 11205 }, 11206 }, 11207 { 11208 name: "MODW", 11209 argLen: 2, 11210 asm: arm64.AREMW, 11211 reg: regInfo{ 11212 inputs: []inputInfo{ 11213 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11214 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11215 }, 11216 outputs: []outputInfo{ 11217 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11218 }, 11219 }, 11220 }, 11221 { 11222 name: "UMODW", 11223 argLen: 2, 11224 asm: arm64.AUREMW, 11225 reg: regInfo{ 11226 inputs: []inputInfo{ 11227 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11228 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11229 }, 11230 outputs: []outputInfo{ 11231 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11232 }, 11233 }, 11234 }, 11235 { 11236 name: "FADDS", 11237 argLen: 2, 11238 commutative: true, 11239 asm: arm64.AFADDS, 11240 reg: regInfo{ 11241 inputs: []inputInfo{ 11242 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11243 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11244 }, 11245 outputs: []outputInfo{ 11246 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11247 }, 11248 }, 11249 }, 11250 { 11251 name: "FADDD", 11252 argLen: 2, 11253 commutative: true, 11254 asm: arm64.AFADDD, 11255 reg: regInfo{ 11256 inputs: []inputInfo{ 11257 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11258 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11259 }, 11260 outputs: []outputInfo{ 11261 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11262 }, 11263 }, 11264 }, 11265 { 11266 name: "FSUBS", 11267 argLen: 2, 11268 asm: arm64.AFSUBS, 11269 reg: regInfo{ 11270 inputs: []inputInfo{ 11271 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11272 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11273 }, 11274 outputs: []outputInfo{ 11275 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11276 }, 11277 }, 11278 }, 11279 { 11280 name: "FSUBD", 11281 argLen: 2, 11282 asm: arm64.AFSUBD, 11283 reg: regInfo{ 11284 inputs: []inputInfo{ 11285 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11286 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11287 }, 11288 outputs: []outputInfo{ 11289 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11290 }, 11291 }, 11292 }, 11293 { 11294 name: "FMULS", 11295 argLen: 2, 11296 commutative: true, 11297 asm: arm64.AFMULS, 11298 reg: regInfo{ 11299 inputs: []inputInfo{ 11300 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11301 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11302 }, 11303 outputs: []outputInfo{ 11304 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11305 }, 11306 }, 11307 }, 11308 { 11309 name: "FMULD", 11310 argLen: 2, 11311 commutative: true, 11312 asm: arm64.AFMULD, 11313 reg: regInfo{ 11314 inputs: []inputInfo{ 11315 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11316 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11317 }, 11318 outputs: []outputInfo{ 11319 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11320 }, 11321 }, 11322 }, 11323 { 11324 name: "FDIVS", 11325 argLen: 2, 11326 asm: arm64.AFDIVS, 11327 reg: regInfo{ 11328 inputs: []inputInfo{ 11329 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11330 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11331 }, 11332 outputs: []outputInfo{ 11333 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11334 }, 11335 }, 11336 }, 11337 { 11338 name: "FDIVD", 11339 argLen: 2, 11340 asm: arm64.AFDIVD, 11341 reg: regInfo{ 11342 inputs: []inputInfo{ 11343 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11344 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11345 }, 11346 outputs: []outputInfo{ 11347 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11348 }, 11349 }, 11350 }, 11351 { 11352 name: "AND", 11353 argLen: 2, 11354 commutative: true, 11355 asm: arm64.AAND, 11356 reg: regInfo{ 11357 inputs: []inputInfo{ 11358 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11359 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11360 }, 11361 outputs: []outputInfo{ 11362 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11363 }, 11364 }, 11365 }, 11366 { 11367 name: "ANDconst", 11368 auxType: auxInt64, 11369 argLen: 1, 11370 asm: arm64.AAND, 11371 reg: regInfo{ 11372 inputs: []inputInfo{ 11373 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11374 }, 11375 outputs: []outputInfo{ 11376 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11377 }, 11378 }, 11379 }, 11380 { 11381 name: "OR", 11382 argLen: 2, 11383 commutative: true, 11384 asm: arm64.AORR, 11385 reg: regInfo{ 11386 inputs: []inputInfo{ 11387 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11388 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11389 }, 11390 outputs: []outputInfo{ 11391 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11392 }, 11393 }, 11394 }, 11395 { 11396 name: "ORconst", 11397 auxType: auxInt64, 11398 argLen: 1, 11399 asm: arm64.AORR, 11400 reg: regInfo{ 11401 inputs: []inputInfo{ 11402 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11403 }, 11404 outputs: []outputInfo{ 11405 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11406 }, 11407 }, 11408 }, 11409 { 11410 name: "XOR", 11411 argLen: 2, 11412 commutative: true, 11413 asm: arm64.AEOR, 11414 reg: regInfo{ 11415 inputs: []inputInfo{ 11416 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11417 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11418 }, 11419 outputs: []outputInfo{ 11420 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11421 }, 11422 }, 11423 }, 11424 { 11425 name: "XORconst", 11426 auxType: auxInt64, 11427 argLen: 1, 11428 asm: arm64.AEOR, 11429 reg: regInfo{ 11430 inputs: []inputInfo{ 11431 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11432 }, 11433 outputs: []outputInfo{ 11434 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11435 }, 11436 }, 11437 }, 11438 { 11439 name: "BIC", 11440 argLen: 2, 11441 asm: arm64.ABIC, 11442 reg: regInfo{ 11443 inputs: []inputInfo{ 11444 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11445 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11446 }, 11447 outputs: []outputInfo{ 11448 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11449 }, 11450 }, 11451 }, 11452 { 11453 name: "BICconst", 11454 auxType: auxInt64, 11455 argLen: 1, 11456 asm: arm64.ABIC, 11457 reg: regInfo{ 11458 inputs: []inputInfo{ 11459 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11460 }, 11461 outputs: []outputInfo{ 11462 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11463 }, 11464 }, 11465 }, 11466 { 11467 name: "MVN", 11468 argLen: 1, 11469 asm: arm64.AMVN, 11470 reg: regInfo{ 11471 inputs: []inputInfo{ 11472 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11473 }, 11474 outputs: []outputInfo{ 11475 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11476 }, 11477 }, 11478 }, 11479 { 11480 name: "NEG", 11481 argLen: 1, 11482 asm: arm64.ANEG, 11483 reg: regInfo{ 11484 inputs: []inputInfo{ 11485 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11486 }, 11487 outputs: []outputInfo{ 11488 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11489 }, 11490 }, 11491 }, 11492 { 11493 name: "FNEGS", 11494 argLen: 1, 11495 asm: arm64.AFNEGS, 11496 reg: regInfo{ 11497 inputs: []inputInfo{ 11498 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11499 }, 11500 outputs: []outputInfo{ 11501 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11502 }, 11503 }, 11504 }, 11505 { 11506 name: "FNEGD", 11507 argLen: 1, 11508 asm: arm64.AFNEGD, 11509 reg: regInfo{ 11510 inputs: []inputInfo{ 11511 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11512 }, 11513 outputs: []outputInfo{ 11514 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11515 }, 11516 }, 11517 }, 11518 { 11519 name: "FSQRTD", 11520 argLen: 1, 11521 asm: arm64.AFSQRTD, 11522 reg: regInfo{ 11523 inputs: []inputInfo{ 11524 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11525 }, 11526 outputs: []outputInfo{ 11527 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11528 }, 11529 }, 11530 }, 11531 { 11532 name: "REV", 11533 argLen: 1, 11534 asm: arm64.AREV, 11535 reg: regInfo{ 11536 inputs: []inputInfo{ 11537 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11538 }, 11539 outputs: []outputInfo{ 11540 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11541 }, 11542 }, 11543 }, 11544 { 11545 name: "REVW", 11546 argLen: 1, 11547 asm: arm64.AREVW, 11548 reg: regInfo{ 11549 inputs: []inputInfo{ 11550 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11551 }, 11552 outputs: []outputInfo{ 11553 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11554 }, 11555 }, 11556 }, 11557 { 11558 name: "REV16W", 11559 argLen: 1, 11560 asm: arm64.AREV16W, 11561 reg: regInfo{ 11562 inputs: []inputInfo{ 11563 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11564 }, 11565 outputs: []outputInfo{ 11566 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11567 }, 11568 }, 11569 }, 11570 { 11571 name: "RBIT", 11572 argLen: 1, 11573 asm: arm64.ARBIT, 11574 reg: regInfo{ 11575 inputs: []inputInfo{ 11576 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11577 }, 11578 outputs: []outputInfo{ 11579 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11580 }, 11581 }, 11582 }, 11583 { 11584 name: "RBITW", 11585 argLen: 1, 11586 asm: arm64.ARBITW, 11587 reg: regInfo{ 11588 inputs: []inputInfo{ 11589 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11590 }, 11591 outputs: []outputInfo{ 11592 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11593 }, 11594 }, 11595 }, 11596 { 11597 name: "CLZ", 11598 argLen: 1, 11599 asm: arm64.ACLZ, 11600 reg: regInfo{ 11601 inputs: []inputInfo{ 11602 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11603 }, 11604 outputs: []outputInfo{ 11605 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11606 }, 11607 }, 11608 }, 11609 { 11610 name: "CLZW", 11611 argLen: 1, 11612 asm: arm64.ACLZW, 11613 reg: regInfo{ 11614 inputs: []inputInfo{ 11615 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11616 }, 11617 outputs: []outputInfo{ 11618 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11619 }, 11620 }, 11621 }, 11622 { 11623 name: "SLL", 11624 argLen: 2, 11625 asm: arm64.ALSL, 11626 reg: regInfo{ 11627 inputs: []inputInfo{ 11628 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11629 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11630 }, 11631 outputs: []outputInfo{ 11632 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11633 }, 11634 }, 11635 }, 11636 { 11637 name: "SLLconst", 11638 auxType: auxInt64, 11639 argLen: 1, 11640 asm: arm64.ALSL, 11641 reg: regInfo{ 11642 inputs: []inputInfo{ 11643 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11644 }, 11645 outputs: []outputInfo{ 11646 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11647 }, 11648 }, 11649 }, 11650 { 11651 name: "SRL", 11652 argLen: 2, 11653 asm: arm64.ALSR, 11654 reg: regInfo{ 11655 inputs: []inputInfo{ 11656 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11657 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11658 }, 11659 outputs: []outputInfo{ 11660 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11661 }, 11662 }, 11663 }, 11664 { 11665 name: "SRLconst", 11666 auxType: auxInt64, 11667 argLen: 1, 11668 asm: arm64.ALSR, 11669 reg: regInfo{ 11670 inputs: []inputInfo{ 11671 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11672 }, 11673 outputs: []outputInfo{ 11674 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11675 }, 11676 }, 11677 }, 11678 { 11679 name: "SRA", 11680 argLen: 2, 11681 asm: arm64.AASR, 11682 reg: regInfo{ 11683 inputs: []inputInfo{ 11684 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11685 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11686 }, 11687 outputs: []outputInfo{ 11688 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11689 }, 11690 }, 11691 }, 11692 { 11693 name: "SRAconst", 11694 auxType: auxInt64, 11695 argLen: 1, 11696 asm: arm64.AASR, 11697 reg: regInfo{ 11698 inputs: []inputInfo{ 11699 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11700 }, 11701 outputs: []outputInfo{ 11702 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11703 }, 11704 }, 11705 }, 11706 { 11707 name: "RORconst", 11708 auxType: auxInt64, 11709 argLen: 1, 11710 asm: arm64.AROR, 11711 reg: regInfo{ 11712 inputs: []inputInfo{ 11713 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11714 }, 11715 outputs: []outputInfo{ 11716 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11717 }, 11718 }, 11719 }, 11720 { 11721 name: "RORWconst", 11722 auxType: auxInt64, 11723 argLen: 1, 11724 asm: arm64.ARORW, 11725 reg: regInfo{ 11726 inputs: []inputInfo{ 11727 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11728 }, 11729 outputs: []outputInfo{ 11730 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11731 }, 11732 }, 11733 }, 11734 { 11735 name: "CMP", 11736 argLen: 2, 11737 asm: arm64.ACMP, 11738 reg: regInfo{ 11739 inputs: []inputInfo{ 11740 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11741 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11742 }, 11743 }, 11744 }, 11745 { 11746 name: "CMPconst", 11747 auxType: auxInt64, 11748 argLen: 1, 11749 asm: arm64.ACMP, 11750 reg: regInfo{ 11751 inputs: []inputInfo{ 11752 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11753 }, 11754 }, 11755 }, 11756 { 11757 name: "CMPW", 11758 argLen: 2, 11759 asm: arm64.ACMPW, 11760 reg: regInfo{ 11761 inputs: []inputInfo{ 11762 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11763 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11764 }, 11765 }, 11766 }, 11767 { 11768 name: "CMPWconst", 11769 auxType: auxInt32, 11770 argLen: 1, 11771 asm: arm64.ACMPW, 11772 reg: regInfo{ 11773 inputs: []inputInfo{ 11774 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11775 }, 11776 }, 11777 }, 11778 { 11779 name: "CMN", 11780 argLen: 2, 11781 asm: arm64.ACMN, 11782 reg: regInfo{ 11783 inputs: []inputInfo{ 11784 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11785 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11786 }, 11787 }, 11788 }, 11789 { 11790 name: "CMNconst", 11791 auxType: auxInt64, 11792 argLen: 1, 11793 asm: arm64.ACMN, 11794 reg: regInfo{ 11795 inputs: []inputInfo{ 11796 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11797 }, 11798 }, 11799 }, 11800 { 11801 name: "CMNW", 11802 argLen: 2, 11803 asm: arm64.ACMNW, 11804 reg: regInfo{ 11805 inputs: []inputInfo{ 11806 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11807 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11808 }, 11809 }, 11810 }, 11811 { 11812 name: "CMNWconst", 11813 auxType: auxInt32, 11814 argLen: 1, 11815 asm: arm64.ACMNW, 11816 reg: regInfo{ 11817 inputs: []inputInfo{ 11818 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11819 }, 11820 }, 11821 }, 11822 { 11823 name: "FCMPS", 11824 argLen: 2, 11825 asm: arm64.AFCMPS, 11826 reg: regInfo{ 11827 inputs: []inputInfo{ 11828 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11829 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11830 }, 11831 }, 11832 }, 11833 { 11834 name: "FCMPD", 11835 argLen: 2, 11836 asm: arm64.AFCMPD, 11837 reg: regInfo{ 11838 inputs: []inputInfo{ 11839 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11840 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11841 }, 11842 }, 11843 }, 11844 { 11845 name: "ADDshiftLL", 11846 auxType: auxInt64, 11847 argLen: 2, 11848 asm: arm64.AADD, 11849 reg: regInfo{ 11850 inputs: []inputInfo{ 11851 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11852 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11853 }, 11854 outputs: []outputInfo{ 11855 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11856 }, 11857 }, 11858 }, 11859 { 11860 name: "ADDshiftRL", 11861 auxType: auxInt64, 11862 argLen: 2, 11863 asm: arm64.AADD, 11864 reg: regInfo{ 11865 inputs: []inputInfo{ 11866 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11867 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11868 }, 11869 outputs: []outputInfo{ 11870 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11871 }, 11872 }, 11873 }, 11874 { 11875 name: "ADDshiftRA", 11876 auxType: auxInt64, 11877 argLen: 2, 11878 asm: arm64.AADD, 11879 reg: regInfo{ 11880 inputs: []inputInfo{ 11881 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11882 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11883 }, 11884 outputs: []outputInfo{ 11885 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11886 }, 11887 }, 11888 }, 11889 { 11890 name: "SUBshiftLL", 11891 auxType: auxInt64, 11892 argLen: 2, 11893 asm: arm64.ASUB, 11894 reg: regInfo{ 11895 inputs: []inputInfo{ 11896 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11897 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11898 }, 11899 outputs: []outputInfo{ 11900 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11901 }, 11902 }, 11903 }, 11904 { 11905 name: "SUBshiftRL", 11906 auxType: auxInt64, 11907 argLen: 2, 11908 asm: arm64.ASUB, 11909 reg: regInfo{ 11910 inputs: []inputInfo{ 11911 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11912 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11913 }, 11914 outputs: []outputInfo{ 11915 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11916 }, 11917 }, 11918 }, 11919 { 11920 name: "SUBshiftRA", 11921 auxType: auxInt64, 11922 argLen: 2, 11923 asm: arm64.ASUB, 11924 reg: regInfo{ 11925 inputs: []inputInfo{ 11926 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11927 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11928 }, 11929 outputs: []outputInfo{ 11930 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11931 }, 11932 }, 11933 }, 11934 { 11935 name: "ANDshiftLL", 11936 auxType: auxInt64, 11937 argLen: 2, 11938 asm: arm64.AAND, 11939 reg: regInfo{ 11940 inputs: []inputInfo{ 11941 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11942 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11943 }, 11944 outputs: []outputInfo{ 11945 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11946 }, 11947 }, 11948 }, 11949 { 11950 name: "ANDshiftRL", 11951 auxType: auxInt64, 11952 argLen: 2, 11953 asm: arm64.AAND, 11954 reg: regInfo{ 11955 inputs: []inputInfo{ 11956 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11957 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11958 }, 11959 outputs: []outputInfo{ 11960 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11961 }, 11962 }, 11963 }, 11964 { 11965 name: "ANDshiftRA", 11966 auxType: auxInt64, 11967 argLen: 2, 11968 asm: arm64.AAND, 11969 reg: regInfo{ 11970 inputs: []inputInfo{ 11971 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11972 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11973 }, 11974 outputs: []outputInfo{ 11975 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11976 }, 11977 }, 11978 }, 11979 { 11980 name: "ORshiftLL", 11981 auxType: auxInt64, 11982 argLen: 2, 11983 asm: arm64.AORR, 11984 reg: regInfo{ 11985 inputs: []inputInfo{ 11986 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11987 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11988 }, 11989 outputs: []outputInfo{ 11990 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11991 }, 11992 }, 11993 }, 11994 { 11995 name: "ORshiftRL", 11996 auxType: auxInt64, 11997 argLen: 2, 11998 asm: arm64.AORR, 11999 reg: regInfo{ 12000 inputs: []inputInfo{ 12001 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12002 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12003 }, 12004 outputs: []outputInfo{ 12005 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12006 }, 12007 }, 12008 }, 12009 { 12010 name: "ORshiftRA", 12011 auxType: auxInt64, 12012 argLen: 2, 12013 asm: arm64.AORR, 12014 reg: regInfo{ 12015 inputs: []inputInfo{ 12016 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12017 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12018 }, 12019 outputs: []outputInfo{ 12020 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12021 }, 12022 }, 12023 }, 12024 { 12025 name: "XORshiftLL", 12026 auxType: auxInt64, 12027 argLen: 2, 12028 asm: arm64.AEOR, 12029 reg: regInfo{ 12030 inputs: []inputInfo{ 12031 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12032 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12033 }, 12034 outputs: []outputInfo{ 12035 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12036 }, 12037 }, 12038 }, 12039 { 12040 name: "XORshiftRL", 12041 auxType: auxInt64, 12042 argLen: 2, 12043 asm: arm64.AEOR, 12044 reg: regInfo{ 12045 inputs: []inputInfo{ 12046 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12047 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12048 }, 12049 outputs: []outputInfo{ 12050 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12051 }, 12052 }, 12053 }, 12054 { 12055 name: "XORshiftRA", 12056 auxType: auxInt64, 12057 argLen: 2, 12058 asm: arm64.AEOR, 12059 reg: regInfo{ 12060 inputs: []inputInfo{ 12061 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12062 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12063 }, 12064 outputs: []outputInfo{ 12065 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12066 }, 12067 }, 12068 }, 12069 { 12070 name: "BICshiftLL", 12071 auxType: auxInt64, 12072 argLen: 2, 12073 asm: arm64.ABIC, 12074 reg: regInfo{ 12075 inputs: []inputInfo{ 12076 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12077 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12078 }, 12079 outputs: []outputInfo{ 12080 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12081 }, 12082 }, 12083 }, 12084 { 12085 name: "BICshiftRL", 12086 auxType: auxInt64, 12087 argLen: 2, 12088 asm: arm64.ABIC, 12089 reg: regInfo{ 12090 inputs: []inputInfo{ 12091 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12092 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12093 }, 12094 outputs: []outputInfo{ 12095 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12096 }, 12097 }, 12098 }, 12099 { 12100 name: "BICshiftRA", 12101 auxType: auxInt64, 12102 argLen: 2, 12103 asm: arm64.ABIC, 12104 reg: regInfo{ 12105 inputs: []inputInfo{ 12106 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12107 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12108 }, 12109 outputs: []outputInfo{ 12110 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12111 }, 12112 }, 12113 }, 12114 { 12115 name: "CMPshiftLL", 12116 auxType: auxInt64, 12117 argLen: 2, 12118 asm: arm64.ACMP, 12119 reg: regInfo{ 12120 inputs: []inputInfo{ 12121 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12122 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12123 }, 12124 }, 12125 }, 12126 { 12127 name: "CMPshiftRL", 12128 auxType: auxInt64, 12129 argLen: 2, 12130 asm: arm64.ACMP, 12131 reg: regInfo{ 12132 inputs: []inputInfo{ 12133 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12134 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12135 }, 12136 }, 12137 }, 12138 { 12139 name: "CMPshiftRA", 12140 auxType: auxInt64, 12141 argLen: 2, 12142 asm: arm64.ACMP, 12143 reg: regInfo{ 12144 inputs: []inputInfo{ 12145 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12146 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12147 }, 12148 }, 12149 }, 12150 { 12151 name: "MOVDconst", 12152 auxType: auxInt64, 12153 argLen: 0, 12154 rematerializeable: true, 12155 asm: arm64.AMOVD, 12156 reg: regInfo{ 12157 outputs: []outputInfo{ 12158 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12159 }, 12160 }, 12161 }, 12162 { 12163 name: "FMOVSconst", 12164 auxType: auxFloat64, 12165 argLen: 0, 12166 rematerializeable: true, 12167 asm: arm64.AFMOVS, 12168 reg: regInfo{ 12169 outputs: []outputInfo{ 12170 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12171 }, 12172 }, 12173 }, 12174 { 12175 name: "FMOVDconst", 12176 auxType: auxFloat64, 12177 argLen: 0, 12178 rematerializeable: true, 12179 asm: arm64.AFMOVD, 12180 reg: regInfo{ 12181 outputs: []outputInfo{ 12182 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12183 }, 12184 }, 12185 }, 12186 { 12187 name: "MOVDaddr", 12188 auxType: auxSymOff, 12189 argLen: 1, 12190 rematerializeable: true, 12191 symEffect: SymAddr, 12192 asm: arm64.AMOVD, 12193 reg: regInfo{ 12194 inputs: []inputInfo{ 12195 {0, 9223372037928517632}, // SP SB 12196 }, 12197 outputs: []outputInfo{ 12198 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12199 }, 12200 }, 12201 }, 12202 { 12203 name: "MOVBload", 12204 auxType: auxSymOff, 12205 argLen: 2, 12206 faultOnNilArg0: true, 12207 symEffect: SymRead, 12208 asm: arm64.AMOVB, 12209 reg: regInfo{ 12210 inputs: []inputInfo{ 12211 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12212 }, 12213 outputs: []outputInfo{ 12214 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12215 }, 12216 }, 12217 }, 12218 { 12219 name: "MOVBUload", 12220 auxType: auxSymOff, 12221 argLen: 2, 12222 faultOnNilArg0: true, 12223 symEffect: SymRead, 12224 asm: arm64.AMOVBU, 12225 reg: regInfo{ 12226 inputs: []inputInfo{ 12227 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12228 }, 12229 outputs: []outputInfo{ 12230 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12231 }, 12232 }, 12233 }, 12234 { 12235 name: "MOVHload", 12236 auxType: auxSymOff, 12237 argLen: 2, 12238 faultOnNilArg0: true, 12239 symEffect: SymRead, 12240 asm: arm64.AMOVH, 12241 reg: regInfo{ 12242 inputs: []inputInfo{ 12243 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12244 }, 12245 outputs: []outputInfo{ 12246 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12247 }, 12248 }, 12249 }, 12250 { 12251 name: "MOVHUload", 12252 auxType: auxSymOff, 12253 argLen: 2, 12254 faultOnNilArg0: true, 12255 symEffect: SymRead, 12256 asm: arm64.AMOVHU, 12257 reg: regInfo{ 12258 inputs: []inputInfo{ 12259 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12260 }, 12261 outputs: []outputInfo{ 12262 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12263 }, 12264 }, 12265 }, 12266 { 12267 name: "MOVWload", 12268 auxType: auxSymOff, 12269 argLen: 2, 12270 faultOnNilArg0: true, 12271 symEffect: SymRead, 12272 asm: arm64.AMOVW, 12273 reg: regInfo{ 12274 inputs: []inputInfo{ 12275 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12276 }, 12277 outputs: []outputInfo{ 12278 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12279 }, 12280 }, 12281 }, 12282 { 12283 name: "MOVWUload", 12284 auxType: auxSymOff, 12285 argLen: 2, 12286 faultOnNilArg0: true, 12287 symEffect: SymRead, 12288 asm: arm64.AMOVWU, 12289 reg: regInfo{ 12290 inputs: []inputInfo{ 12291 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12292 }, 12293 outputs: []outputInfo{ 12294 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12295 }, 12296 }, 12297 }, 12298 { 12299 name: "MOVDload", 12300 auxType: auxSymOff, 12301 argLen: 2, 12302 faultOnNilArg0: true, 12303 symEffect: SymRead, 12304 asm: arm64.AMOVD, 12305 reg: regInfo{ 12306 inputs: []inputInfo{ 12307 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12308 }, 12309 outputs: []outputInfo{ 12310 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12311 }, 12312 }, 12313 }, 12314 { 12315 name: "FMOVSload", 12316 auxType: auxSymOff, 12317 argLen: 2, 12318 faultOnNilArg0: true, 12319 symEffect: SymRead, 12320 asm: arm64.AFMOVS, 12321 reg: regInfo{ 12322 inputs: []inputInfo{ 12323 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12324 }, 12325 outputs: []outputInfo{ 12326 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12327 }, 12328 }, 12329 }, 12330 { 12331 name: "FMOVDload", 12332 auxType: auxSymOff, 12333 argLen: 2, 12334 faultOnNilArg0: true, 12335 symEffect: SymRead, 12336 asm: arm64.AFMOVD, 12337 reg: regInfo{ 12338 inputs: []inputInfo{ 12339 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12340 }, 12341 outputs: []outputInfo{ 12342 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12343 }, 12344 }, 12345 }, 12346 { 12347 name: "MOVBstore", 12348 auxType: auxSymOff, 12349 argLen: 3, 12350 faultOnNilArg0: true, 12351 symEffect: SymWrite, 12352 asm: arm64.AMOVB, 12353 reg: regInfo{ 12354 inputs: []inputInfo{ 12355 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12356 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12357 }, 12358 }, 12359 }, 12360 { 12361 name: "MOVHstore", 12362 auxType: auxSymOff, 12363 argLen: 3, 12364 faultOnNilArg0: true, 12365 symEffect: SymWrite, 12366 asm: arm64.AMOVH, 12367 reg: regInfo{ 12368 inputs: []inputInfo{ 12369 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12370 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12371 }, 12372 }, 12373 }, 12374 { 12375 name: "MOVWstore", 12376 auxType: auxSymOff, 12377 argLen: 3, 12378 faultOnNilArg0: true, 12379 symEffect: SymWrite, 12380 asm: arm64.AMOVW, 12381 reg: regInfo{ 12382 inputs: []inputInfo{ 12383 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12384 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12385 }, 12386 }, 12387 }, 12388 { 12389 name: "MOVDstore", 12390 auxType: auxSymOff, 12391 argLen: 3, 12392 faultOnNilArg0: true, 12393 symEffect: SymWrite, 12394 asm: arm64.AMOVD, 12395 reg: regInfo{ 12396 inputs: []inputInfo{ 12397 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12398 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12399 }, 12400 }, 12401 }, 12402 { 12403 name: "FMOVSstore", 12404 auxType: auxSymOff, 12405 argLen: 3, 12406 faultOnNilArg0: true, 12407 symEffect: SymWrite, 12408 asm: arm64.AFMOVS, 12409 reg: regInfo{ 12410 inputs: []inputInfo{ 12411 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12412 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12413 }, 12414 }, 12415 }, 12416 { 12417 name: "FMOVDstore", 12418 auxType: auxSymOff, 12419 argLen: 3, 12420 faultOnNilArg0: true, 12421 symEffect: SymWrite, 12422 asm: arm64.AFMOVD, 12423 reg: regInfo{ 12424 inputs: []inputInfo{ 12425 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12426 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12427 }, 12428 }, 12429 }, 12430 { 12431 name: "MOVBstorezero", 12432 auxType: auxSymOff, 12433 argLen: 2, 12434 faultOnNilArg0: true, 12435 symEffect: SymWrite, 12436 asm: arm64.AMOVB, 12437 reg: regInfo{ 12438 inputs: []inputInfo{ 12439 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12440 }, 12441 }, 12442 }, 12443 { 12444 name: "MOVHstorezero", 12445 auxType: auxSymOff, 12446 argLen: 2, 12447 faultOnNilArg0: true, 12448 symEffect: SymWrite, 12449 asm: arm64.AMOVH, 12450 reg: regInfo{ 12451 inputs: []inputInfo{ 12452 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12453 }, 12454 }, 12455 }, 12456 { 12457 name: "MOVWstorezero", 12458 auxType: auxSymOff, 12459 argLen: 2, 12460 faultOnNilArg0: true, 12461 symEffect: SymWrite, 12462 asm: arm64.AMOVW, 12463 reg: regInfo{ 12464 inputs: []inputInfo{ 12465 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12466 }, 12467 }, 12468 }, 12469 { 12470 name: "MOVDstorezero", 12471 auxType: auxSymOff, 12472 argLen: 2, 12473 faultOnNilArg0: true, 12474 symEffect: SymWrite, 12475 asm: arm64.AMOVD, 12476 reg: regInfo{ 12477 inputs: []inputInfo{ 12478 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12479 }, 12480 }, 12481 }, 12482 { 12483 name: "MOVBreg", 12484 argLen: 1, 12485 asm: arm64.AMOVB, 12486 reg: regInfo{ 12487 inputs: []inputInfo{ 12488 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12489 }, 12490 outputs: []outputInfo{ 12491 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12492 }, 12493 }, 12494 }, 12495 { 12496 name: "MOVBUreg", 12497 argLen: 1, 12498 asm: arm64.AMOVBU, 12499 reg: regInfo{ 12500 inputs: []inputInfo{ 12501 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12502 }, 12503 outputs: []outputInfo{ 12504 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12505 }, 12506 }, 12507 }, 12508 { 12509 name: "MOVHreg", 12510 argLen: 1, 12511 asm: arm64.AMOVH, 12512 reg: regInfo{ 12513 inputs: []inputInfo{ 12514 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12515 }, 12516 outputs: []outputInfo{ 12517 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12518 }, 12519 }, 12520 }, 12521 { 12522 name: "MOVHUreg", 12523 argLen: 1, 12524 asm: arm64.AMOVHU, 12525 reg: regInfo{ 12526 inputs: []inputInfo{ 12527 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12528 }, 12529 outputs: []outputInfo{ 12530 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12531 }, 12532 }, 12533 }, 12534 { 12535 name: "MOVWreg", 12536 argLen: 1, 12537 asm: arm64.AMOVW, 12538 reg: regInfo{ 12539 inputs: []inputInfo{ 12540 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12541 }, 12542 outputs: []outputInfo{ 12543 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12544 }, 12545 }, 12546 }, 12547 { 12548 name: "MOVWUreg", 12549 argLen: 1, 12550 asm: arm64.AMOVWU, 12551 reg: regInfo{ 12552 inputs: []inputInfo{ 12553 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12554 }, 12555 outputs: []outputInfo{ 12556 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12557 }, 12558 }, 12559 }, 12560 { 12561 name: "MOVDreg", 12562 argLen: 1, 12563 asm: arm64.AMOVD, 12564 reg: regInfo{ 12565 inputs: []inputInfo{ 12566 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12567 }, 12568 outputs: []outputInfo{ 12569 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12570 }, 12571 }, 12572 }, 12573 { 12574 name: "MOVDnop", 12575 argLen: 1, 12576 resultInArg0: true, 12577 reg: regInfo{ 12578 inputs: []inputInfo{ 12579 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12580 }, 12581 outputs: []outputInfo{ 12582 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12583 }, 12584 }, 12585 }, 12586 { 12587 name: "SCVTFWS", 12588 argLen: 1, 12589 asm: arm64.ASCVTFWS, 12590 reg: regInfo{ 12591 inputs: []inputInfo{ 12592 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12593 }, 12594 outputs: []outputInfo{ 12595 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12596 }, 12597 }, 12598 }, 12599 { 12600 name: "SCVTFWD", 12601 argLen: 1, 12602 asm: arm64.ASCVTFWD, 12603 reg: regInfo{ 12604 inputs: []inputInfo{ 12605 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12606 }, 12607 outputs: []outputInfo{ 12608 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12609 }, 12610 }, 12611 }, 12612 { 12613 name: "UCVTFWS", 12614 argLen: 1, 12615 asm: arm64.AUCVTFWS, 12616 reg: regInfo{ 12617 inputs: []inputInfo{ 12618 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12619 }, 12620 outputs: []outputInfo{ 12621 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12622 }, 12623 }, 12624 }, 12625 { 12626 name: "UCVTFWD", 12627 argLen: 1, 12628 asm: arm64.AUCVTFWD, 12629 reg: regInfo{ 12630 inputs: []inputInfo{ 12631 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12632 }, 12633 outputs: []outputInfo{ 12634 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12635 }, 12636 }, 12637 }, 12638 { 12639 name: "SCVTFS", 12640 argLen: 1, 12641 asm: arm64.ASCVTFS, 12642 reg: regInfo{ 12643 inputs: []inputInfo{ 12644 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12645 }, 12646 outputs: []outputInfo{ 12647 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12648 }, 12649 }, 12650 }, 12651 { 12652 name: "SCVTFD", 12653 argLen: 1, 12654 asm: arm64.ASCVTFD, 12655 reg: regInfo{ 12656 inputs: []inputInfo{ 12657 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12658 }, 12659 outputs: []outputInfo{ 12660 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12661 }, 12662 }, 12663 }, 12664 { 12665 name: "UCVTFS", 12666 argLen: 1, 12667 asm: arm64.AUCVTFS, 12668 reg: regInfo{ 12669 inputs: []inputInfo{ 12670 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12671 }, 12672 outputs: []outputInfo{ 12673 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12674 }, 12675 }, 12676 }, 12677 { 12678 name: "UCVTFD", 12679 argLen: 1, 12680 asm: arm64.AUCVTFD, 12681 reg: regInfo{ 12682 inputs: []inputInfo{ 12683 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12684 }, 12685 outputs: []outputInfo{ 12686 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12687 }, 12688 }, 12689 }, 12690 { 12691 name: "FCVTZSSW", 12692 argLen: 1, 12693 asm: arm64.AFCVTZSSW, 12694 reg: regInfo{ 12695 inputs: []inputInfo{ 12696 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12697 }, 12698 outputs: []outputInfo{ 12699 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12700 }, 12701 }, 12702 }, 12703 { 12704 name: "FCVTZSDW", 12705 argLen: 1, 12706 asm: arm64.AFCVTZSDW, 12707 reg: regInfo{ 12708 inputs: []inputInfo{ 12709 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12710 }, 12711 outputs: []outputInfo{ 12712 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12713 }, 12714 }, 12715 }, 12716 { 12717 name: "FCVTZUSW", 12718 argLen: 1, 12719 asm: arm64.AFCVTZUSW, 12720 reg: regInfo{ 12721 inputs: []inputInfo{ 12722 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12723 }, 12724 outputs: []outputInfo{ 12725 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12726 }, 12727 }, 12728 }, 12729 { 12730 name: "FCVTZUDW", 12731 argLen: 1, 12732 asm: arm64.AFCVTZUDW, 12733 reg: regInfo{ 12734 inputs: []inputInfo{ 12735 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12736 }, 12737 outputs: []outputInfo{ 12738 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12739 }, 12740 }, 12741 }, 12742 { 12743 name: "FCVTZSS", 12744 argLen: 1, 12745 asm: arm64.AFCVTZSS, 12746 reg: regInfo{ 12747 inputs: []inputInfo{ 12748 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12749 }, 12750 outputs: []outputInfo{ 12751 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12752 }, 12753 }, 12754 }, 12755 { 12756 name: "FCVTZSD", 12757 argLen: 1, 12758 asm: arm64.AFCVTZSD, 12759 reg: regInfo{ 12760 inputs: []inputInfo{ 12761 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12762 }, 12763 outputs: []outputInfo{ 12764 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12765 }, 12766 }, 12767 }, 12768 { 12769 name: "FCVTZUS", 12770 argLen: 1, 12771 asm: arm64.AFCVTZUS, 12772 reg: regInfo{ 12773 inputs: []inputInfo{ 12774 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12775 }, 12776 outputs: []outputInfo{ 12777 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12778 }, 12779 }, 12780 }, 12781 { 12782 name: "FCVTZUD", 12783 argLen: 1, 12784 asm: arm64.AFCVTZUD, 12785 reg: regInfo{ 12786 inputs: []inputInfo{ 12787 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12788 }, 12789 outputs: []outputInfo{ 12790 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12791 }, 12792 }, 12793 }, 12794 { 12795 name: "FCVTSD", 12796 argLen: 1, 12797 asm: arm64.AFCVTSD, 12798 reg: regInfo{ 12799 inputs: []inputInfo{ 12800 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12801 }, 12802 outputs: []outputInfo{ 12803 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12804 }, 12805 }, 12806 }, 12807 { 12808 name: "FCVTDS", 12809 argLen: 1, 12810 asm: arm64.AFCVTDS, 12811 reg: regInfo{ 12812 inputs: []inputInfo{ 12813 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12814 }, 12815 outputs: []outputInfo{ 12816 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12817 }, 12818 }, 12819 }, 12820 { 12821 name: "CSELULT", 12822 argLen: 3, 12823 asm: arm64.ACSEL, 12824 reg: regInfo{ 12825 inputs: []inputInfo{ 12826 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12827 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12828 }, 12829 outputs: []outputInfo{ 12830 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12831 }, 12832 }, 12833 }, 12834 { 12835 name: "CSELULT0", 12836 argLen: 2, 12837 asm: arm64.ACSEL, 12838 reg: regInfo{ 12839 inputs: []inputInfo{ 12840 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12841 }, 12842 outputs: []outputInfo{ 12843 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12844 }, 12845 }, 12846 }, 12847 { 12848 name: "CALLstatic", 12849 auxType: auxSymOff, 12850 argLen: 1, 12851 clobberFlags: true, 12852 call: true, 12853 symEffect: SymNone, 12854 reg: regInfo{ 12855 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12856 }, 12857 }, 12858 { 12859 name: "CALLclosure", 12860 auxType: auxInt64, 12861 argLen: 3, 12862 clobberFlags: true, 12863 call: true, 12864 reg: regInfo{ 12865 inputs: []inputInfo{ 12866 {1, 67108864}, // R26 12867 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 12868 }, 12869 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12870 }, 12871 }, 12872 { 12873 name: "CALLinter", 12874 auxType: auxInt64, 12875 argLen: 2, 12876 clobberFlags: true, 12877 call: true, 12878 reg: regInfo{ 12879 inputs: []inputInfo{ 12880 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12881 }, 12882 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12883 }, 12884 }, 12885 { 12886 name: "LoweredNilCheck", 12887 argLen: 2, 12888 nilCheck: true, 12889 faultOnNilArg0: true, 12890 reg: regInfo{ 12891 inputs: []inputInfo{ 12892 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12893 }, 12894 }, 12895 }, 12896 { 12897 name: "Equal", 12898 argLen: 1, 12899 reg: regInfo{ 12900 outputs: []outputInfo{ 12901 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12902 }, 12903 }, 12904 }, 12905 { 12906 name: "NotEqual", 12907 argLen: 1, 12908 reg: regInfo{ 12909 outputs: []outputInfo{ 12910 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12911 }, 12912 }, 12913 }, 12914 { 12915 name: "LessThan", 12916 argLen: 1, 12917 reg: regInfo{ 12918 outputs: []outputInfo{ 12919 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12920 }, 12921 }, 12922 }, 12923 { 12924 name: "LessEqual", 12925 argLen: 1, 12926 reg: regInfo{ 12927 outputs: []outputInfo{ 12928 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12929 }, 12930 }, 12931 }, 12932 { 12933 name: "GreaterThan", 12934 argLen: 1, 12935 reg: regInfo{ 12936 outputs: []outputInfo{ 12937 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12938 }, 12939 }, 12940 }, 12941 { 12942 name: "GreaterEqual", 12943 argLen: 1, 12944 reg: regInfo{ 12945 outputs: []outputInfo{ 12946 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12947 }, 12948 }, 12949 }, 12950 { 12951 name: "LessThanU", 12952 argLen: 1, 12953 reg: regInfo{ 12954 outputs: []outputInfo{ 12955 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12956 }, 12957 }, 12958 }, 12959 { 12960 name: "LessEqualU", 12961 argLen: 1, 12962 reg: regInfo{ 12963 outputs: []outputInfo{ 12964 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12965 }, 12966 }, 12967 }, 12968 { 12969 name: "GreaterThanU", 12970 argLen: 1, 12971 reg: regInfo{ 12972 outputs: []outputInfo{ 12973 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12974 }, 12975 }, 12976 }, 12977 { 12978 name: "GreaterEqualU", 12979 argLen: 1, 12980 reg: regInfo{ 12981 outputs: []outputInfo{ 12982 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12983 }, 12984 }, 12985 }, 12986 { 12987 name: "DUFFZERO", 12988 auxType: auxInt64, 12989 argLen: 2, 12990 faultOnNilArg0: true, 12991 reg: regInfo{ 12992 inputs: []inputInfo{ 12993 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12994 }, 12995 clobbers: 536936448, // R16 R30 12996 }, 12997 }, 12998 { 12999 name: "LoweredZero", 13000 argLen: 3, 13001 clobberFlags: true, 13002 faultOnNilArg0: true, 13003 reg: regInfo{ 13004 inputs: []inputInfo{ 13005 {0, 65536}, // R16 13006 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13007 }, 13008 clobbers: 65536, // R16 13009 }, 13010 }, 13011 { 13012 name: "DUFFCOPY", 13013 auxType: auxInt64, 13014 argLen: 3, 13015 faultOnNilArg0: true, 13016 faultOnNilArg1: true, 13017 reg: regInfo{ 13018 inputs: []inputInfo{ 13019 {0, 131072}, // R17 13020 {1, 65536}, // R16 13021 }, 13022 clobbers: 537067520, // R16 R17 R30 13023 }, 13024 }, 13025 { 13026 name: "LoweredMove", 13027 argLen: 4, 13028 clobberFlags: true, 13029 faultOnNilArg0: true, 13030 faultOnNilArg1: true, 13031 reg: regInfo{ 13032 inputs: []inputInfo{ 13033 {0, 131072}, // R17 13034 {1, 65536}, // R16 13035 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13036 }, 13037 clobbers: 196608, // R16 R17 13038 }, 13039 }, 13040 { 13041 name: "LoweredGetClosurePtr", 13042 argLen: 0, 13043 reg: regInfo{ 13044 outputs: []outputInfo{ 13045 {0, 67108864}, // R26 13046 }, 13047 }, 13048 }, 13049 { 13050 name: "MOVDconvert", 13051 argLen: 2, 13052 asm: arm64.AMOVD, 13053 reg: regInfo{ 13054 inputs: []inputInfo{ 13055 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13056 }, 13057 outputs: []outputInfo{ 13058 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13059 }, 13060 }, 13061 }, 13062 { 13063 name: "FlagEQ", 13064 argLen: 0, 13065 reg: regInfo{}, 13066 }, 13067 { 13068 name: "FlagLT_ULT", 13069 argLen: 0, 13070 reg: regInfo{}, 13071 }, 13072 { 13073 name: "FlagLT_UGT", 13074 argLen: 0, 13075 reg: regInfo{}, 13076 }, 13077 { 13078 name: "FlagGT_UGT", 13079 argLen: 0, 13080 reg: regInfo{}, 13081 }, 13082 { 13083 name: "FlagGT_ULT", 13084 argLen: 0, 13085 reg: regInfo{}, 13086 }, 13087 { 13088 name: "InvertFlags", 13089 argLen: 1, 13090 reg: regInfo{}, 13091 }, 13092 { 13093 name: "LDAR", 13094 argLen: 2, 13095 faultOnNilArg0: true, 13096 asm: arm64.ALDAR, 13097 reg: regInfo{ 13098 inputs: []inputInfo{ 13099 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13100 }, 13101 outputs: []outputInfo{ 13102 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13103 }, 13104 }, 13105 }, 13106 { 13107 name: "LDARW", 13108 argLen: 2, 13109 faultOnNilArg0: true, 13110 asm: arm64.ALDARW, 13111 reg: regInfo{ 13112 inputs: []inputInfo{ 13113 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13114 }, 13115 outputs: []outputInfo{ 13116 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13117 }, 13118 }, 13119 }, 13120 { 13121 name: "STLR", 13122 argLen: 3, 13123 faultOnNilArg0: true, 13124 hasSideEffects: true, 13125 asm: arm64.ASTLR, 13126 reg: regInfo{ 13127 inputs: []inputInfo{ 13128 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13129 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13130 }, 13131 }, 13132 }, 13133 { 13134 name: "STLRW", 13135 argLen: 3, 13136 faultOnNilArg0: true, 13137 hasSideEffects: true, 13138 asm: arm64.ASTLRW, 13139 reg: regInfo{ 13140 inputs: []inputInfo{ 13141 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13142 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13143 }, 13144 }, 13145 }, 13146 { 13147 name: "LoweredAtomicExchange64", 13148 argLen: 3, 13149 resultNotInArgs: true, 13150 faultOnNilArg0: true, 13151 hasSideEffects: true, 13152 reg: regInfo{ 13153 inputs: []inputInfo{ 13154 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13155 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13156 }, 13157 outputs: []outputInfo{ 13158 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13159 }, 13160 }, 13161 }, 13162 { 13163 name: "LoweredAtomicExchange32", 13164 argLen: 3, 13165 resultNotInArgs: true, 13166 faultOnNilArg0: true, 13167 hasSideEffects: true, 13168 reg: regInfo{ 13169 inputs: []inputInfo{ 13170 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13171 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13172 }, 13173 outputs: []outputInfo{ 13174 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13175 }, 13176 }, 13177 }, 13178 { 13179 name: "LoweredAtomicAdd64", 13180 argLen: 3, 13181 resultNotInArgs: true, 13182 faultOnNilArg0: true, 13183 hasSideEffects: true, 13184 reg: regInfo{ 13185 inputs: []inputInfo{ 13186 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13187 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13188 }, 13189 outputs: []outputInfo{ 13190 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13191 }, 13192 }, 13193 }, 13194 { 13195 name: "LoweredAtomicAdd32", 13196 argLen: 3, 13197 resultNotInArgs: true, 13198 faultOnNilArg0: true, 13199 hasSideEffects: true, 13200 reg: regInfo{ 13201 inputs: []inputInfo{ 13202 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13203 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13204 }, 13205 outputs: []outputInfo{ 13206 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13207 }, 13208 }, 13209 }, 13210 { 13211 name: "LoweredAtomicCas64", 13212 argLen: 4, 13213 resultNotInArgs: true, 13214 clobberFlags: true, 13215 faultOnNilArg0: true, 13216 hasSideEffects: true, 13217 reg: regInfo{ 13218 inputs: []inputInfo{ 13219 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13220 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13221 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13222 }, 13223 outputs: []outputInfo{ 13224 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13225 }, 13226 }, 13227 }, 13228 { 13229 name: "LoweredAtomicCas32", 13230 argLen: 4, 13231 resultNotInArgs: true, 13232 clobberFlags: true, 13233 faultOnNilArg0: true, 13234 hasSideEffects: true, 13235 reg: regInfo{ 13236 inputs: []inputInfo{ 13237 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13238 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13239 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13240 }, 13241 outputs: []outputInfo{ 13242 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13243 }, 13244 }, 13245 }, 13246 { 13247 name: "LoweredAtomicAnd8", 13248 argLen: 3, 13249 faultOnNilArg0: true, 13250 hasSideEffects: true, 13251 asm: arm64.AAND, 13252 reg: regInfo{ 13253 inputs: []inputInfo{ 13254 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13255 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13256 }, 13257 }, 13258 }, 13259 { 13260 name: "LoweredAtomicOr8", 13261 argLen: 3, 13262 faultOnNilArg0: true, 13263 hasSideEffects: true, 13264 asm: arm64.AORR, 13265 reg: regInfo{ 13266 inputs: []inputInfo{ 13267 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13268 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13269 }, 13270 }, 13271 }, 13272 13273 { 13274 name: "ADD", 13275 argLen: 2, 13276 commutative: true, 13277 asm: mips.AADDU, 13278 reg: regInfo{ 13279 inputs: []inputInfo{ 13280 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13281 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13282 }, 13283 outputs: []outputInfo{ 13284 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13285 }, 13286 }, 13287 }, 13288 { 13289 name: "ADDconst", 13290 auxType: auxInt32, 13291 argLen: 1, 13292 asm: mips.AADDU, 13293 reg: regInfo{ 13294 inputs: []inputInfo{ 13295 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 13296 }, 13297 outputs: []outputInfo{ 13298 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13299 }, 13300 }, 13301 }, 13302 { 13303 name: "SUB", 13304 argLen: 2, 13305 asm: mips.ASUBU, 13306 reg: regInfo{ 13307 inputs: []inputInfo{ 13308 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13309 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13310 }, 13311 outputs: []outputInfo{ 13312 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13313 }, 13314 }, 13315 }, 13316 { 13317 name: "SUBconst", 13318 auxType: auxInt32, 13319 argLen: 1, 13320 asm: mips.ASUBU, 13321 reg: regInfo{ 13322 inputs: []inputInfo{ 13323 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13324 }, 13325 outputs: []outputInfo{ 13326 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13327 }, 13328 }, 13329 }, 13330 { 13331 name: "MUL", 13332 argLen: 2, 13333 commutative: true, 13334 asm: mips.AMUL, 13335 reg: regInfo{ 13336 inputs: []inputInfo{ 13337 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13338 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13339 }, 13340 clobbers: 105553116266496, // HI LO 13341 outputs: []outputInfo{ 13342 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13343 }, 13344 }, 13345 }, 13346 { 13347 name: "MULT", 13348 argLen: 2, 13349 commutative: true, 13350 asm: mips.AMUL, 13351 reg: regInfo{ 13352 inputs: []inputInfo{ 13353 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13354 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13355 }, 13356 outputs: []outputInfo{ 13357 {0, 35184372088832}, // HI 13358 {1, 70368744177664}, // LO 13359 }, 13360 }, 13361 }, 13362 { 13363 name: "MULTU", 13364 argLen: 2, 13365 commutative: true, 13366 asm: mips.AMULU, 13367 reg: regInfo{ 13368 inputs: []inputInfo{ 13369 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13370 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13371 }, 13372 outputs: []outputInfo{ 13373 {0, 35184372088832}, // HI 13374 {1, 70368744177664}, // LO 13375 }, 13376 }, 13377 }, 13378 { 13379 name: "DIV", 13380 argLen: 2, 13381 asm: mips.ADIV, 13382 reg: regInfo{ 13383 inputs: []inputInfo{ 13384 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13385 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13386 }, 13387 outputs: []outputInfo{ 13388 {0, 35184372088832}, // HI 13389 {1, 70368744177664}, // LO 13390 }, 13391 }, 13392 }, 13393 { 13394 name: "DIVU", 13395 argLen: 2, 13396 asm: mips.ADIVU, 13397 reg: regInfo{ 13398 inputs: []inputInfo{ 13399 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13400 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13401 }, 13402 outputs: []outputInfo{ 13403 {0, 35184372088832}, // HI 13404 {1, 70368744177664}, // LO 13405 }, 13406 }, 13407 }, 13408 { 13409 name: "ADDF", 13410 argLen: 2, 13411 commutative: true, 13412 asm: mips.AADDF, 13413 reg: regInfo{ 13414 inputs: []inputInfo{ 13415 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13416 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13417 }, 13418 outputs: []outputInfo{ 13419 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13420 }, 13421 }, 13422 }, 13423 { 13424 name: "ADDD", 13425 argLen: 2, 13426 commutative: true, 13427 asm: mips.AADDD, 13428 reg: regInfo{ 13429 inputs: []inputInfo{ 13430 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13431 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13432 }, 13433 outputs: []outputInfo{ 13434 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13435 }, 13436 }, 13437 }, 13438 { 13439 name: "SUBF", 13440 argLen: 2, 13441 asm: mips.ASUBF, 13442 reg: regInfo{ 13443 inputs: []inputInfo{ 13444 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13445 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13446 }, 13447 outputs: []outputInfo{ 13448 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13449 }, 13450 }, 13451 }, 13452 { 13453 name: "SUBD", 13454 argLen: 2, 13455 asm: mips.ASUBD, 13456 reg: regInfo{ 13457 inputs: []inputInfo{ 13458 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13459 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13460 }, 13461 outputs: []outputInfo{ 13462 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13463 }, 13464 }, 13465 }, 13466 { 13467 name: "MULF", 13468 argLen: 2, 13469 commutative: true, 13470 asm: mips.AMULF, 13471 reg: regInfo{ 13472 inputs: []inputInfo{ 13473 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13474 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13475 }, 13476 outputs: []outputInfo{ 13477 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13478 }, 13479 }, 13480 }, 13481 { 13482 name: "MULD", 13483 argLen: 2, 13484 commutative: true, 13485 asm: mips.AMULD, 13486 reg: regInfo{ 13487 inputs: []inputInfo{ 13488 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13489 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13490 }, 13491 outputs: []outputInfo{ 13492 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13493 }, 13494 }, 13495 }, 13496 { 13497 name: "DIVF", 13498 argLen: 2, 13499 asm: mips.ADIVF, 13500 reg: regInfo{ 13501 inputs: []inputInfo{ 13502 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13503 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13504 }, 13505 outputs: []outputInfo{ 13506 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13507 }, 13508 }, 13509 }, 13510 { 13511 name: "DIVD", 13512 argLen: 2, 13513 asm: mips.ADIVD, 13514 reg: regInfo{ 13515 inputs: []inputInfo{ 13516 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13517 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13518 }, 13519 outputs: []outputInfo{ 13520 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13521 }, 13522 }, 13523 }, 13524 { 13525 name: "AND", 13526 argLen: 2, 13527 commutative: true, 13528 asm: mips.AAND, 13529 reg: regInfo{ 13530 inputs: []inputInfo{ 13531 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13532 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13533 }, 13534 outputs: []outputInfo{ 13535 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13536 }, 13537 }, 13538 }, 13539 { 13540 name: "ANDconst", 13541 auxType: auxInt32, 13542 argLen: 1, 13543 asm: mips.AAND, 13544 reg: regInfo{ 13545 inputs: []inputInfo{ 13546 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13547 }, 13548 outputs: []outputInfo{ 13549 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13550 }, 13551 }, 13552 }, 13553 { 13554 name: "OR", 13555 argLen: 2, 13556 commutative: true, 13557 asm: mips.AOR, 13558 reg: regInfo{ 13559 inputs: []inputInfo{ 13560 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13561 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13562 }, 13563 outputs: []outputInfo{ 13564 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13565 }, 13566 }, 13567 }, 13568 { 13569 name: "ORconst", 13570 auxType: auxInt32, 13571 argLen: 1, 13572 asm: mips.AOR, 13573 reg: regInfo{ 13574 inputs: []inputInfo{ 13575 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13576 }, 13577 outputs: []outputInfo{ 13578 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13579 }, 13580 }, 13581 }, 13582 { 13583 name: "XOR", 13584 argLen: 2, 13585 commutative: true, 13586 asm: mips.AXOR, 13587 reg: regInfo{ 13588 inputs: []inputInfo{ 13589 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13590 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13591 }, 13592 outputs: []outputInfo{ 13593 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13594 }, 13595 }, 13596 }, 13597 { 13598 name: "XORconst", 13599 auxType: auxInt32, 13600 argLen: 1, 13601 asm: mips.AXOR, 13602 reg: regInfo{ 13603 inputs: []inputInfo{ 13604 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13605 }, 13606 outputs: []outputInfo{ 13607 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13608 }, 13609 }, 13610 }, 13611 { 13612 name: "NOR", 13613 argLen: 2, 13614 commutative: true, 13615 asm: mips.ANOR, 13616 reg: regInfo{ 13617 inputs: []inputInfo{ 13618 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13619 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13620 }, 13621 outputs: []outputInfo{ 13622 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13623 }, 13624 }, 13625 }, 13626 { 13627 name: "NORconst", 13628 auxType: auxInt32, 13629 argLen: 1, 13630 asm: mips.ANOR, 13631 reg: regInfo{ 13632 inputs: []inputInfo{ 13633 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13634 }, 13635 outputs: []outputInfo{ 13636 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13637 }, 13638 }, 13639 }, 13640 { 13641 name: "NEG", 13642 argLen: 1, 13643 reg: regInfo{ 13644 inputs: []inputInfo{ 13645 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13646 }, 13647 outputs: []outputInfo{ 13648 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13649 }, 13650 }, 13651 }, 13652 { 13653 name: "NEGF", 13654 argLen: 1, 13655 asm: mips.ANEGF, 13656 reg: regInfo{ 13657 inputs: []inputInfo{ 13658 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13659 }, 13660 outputs: []outputInfo{ 13661 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13662 }, 13663 }, 13664 }, 13665 { 13666 name: "NEGD", 13667 argLen: 1, 13668 asm: mips.ANEGD, 13669 reg: regInfo{ 13670 inputs: []inputInfo{ 13671 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13672 }, 13673 outputs: []outputInfo{ 13674 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13675 }, 13676 }, 13677 }, 13678 { 13679 name: "SQRTD", 13680 argLen: 1, 13681 asm: mips.ASQRTD, 13682 reg: regInfo{ 13683 inputs: []inputInfo{ 13684 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13685 }, 13686 outputs: []outputInfo{ 13687 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13688 }, 13689 }, 13690 }, 13691 { 13692 name: "SLL", 13693 argLen: 2, 13694 asm: mips.ASLL, 13695 reg: regInfo{ 13696 inputs: []inputInfo{ 13697 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13698 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13699 }, 13700 outputs: []outputInfo{ 13701 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13702 }, 13703 }, 13704 }, 13705 { 13706 name: "SLLconst", 13707 auxType: auxInt32, 13708 argLen: 1, 13709 asm: mips.ASLL, 13710 reg: regInfo{ 13711 inputs: []inputInfo{ 13712 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13713 }, 13714 outputs: []outputInfo{ 13715 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13716 }, 13717 }, 13718 }, 13719 { 13720 name: "SRL", 13721 argLen: 2, 13722 asm: mips.ASRL, 13723 reg: regInfo{ 13724 inputs: []inputInfo{ 13725 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13726 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13727 }, 13728 outputs: []outputInfo{ 13729 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13730 }, 13731 }, 13732 }, 13733 { 13734 name: "SRLconst", 13735 auxType: auxInt32, 13736 argLen: 1, 13737 asm: mips.ASRL, 13738 reg: regInfo{ 13739 inputs: []inputInfo{ 13740 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13741 }, 13742 outputs: []outputInfo{ 13743 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13744 }, 13745 }, 13746 }, 13747 { 13748 name: "SRA", 13749 argLen: 2, 13750 asm: mips.ASRA, 13751 reg: regInfo{ 13752 inputs: []inputInfo{ 13753 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13754 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13755 }, 13756 outputs: []outputInfo{ 13757 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13758 }, 13759 }, 13760 }, 13761 { 13762 name: "SRAconst", 13763 auxType: auxInt32, 13764 argLen: 1, 13765 asm: mips.ASRA, 13766 reg: regInfo{ 13767 inputs: []inputInfo{ 13768 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13769 }, 13770 outputs: []outputInfo{ 13771 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13772 }, 13773 }, 13774 }, 13775 { 13776 name: "CLZ", 13777 argLen: 1, 13778 asm: mips.ACLZ, 13779 reg: regInfo{ 13780 inputs: []inputInfo{ 13781 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13782 }, 13783 outputs: []outputInfo{ 13784 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13785 }, 13786 }, 13787 }, 13788 { 13789 name: "SGT", 13790 argLen: 2, 13791 asm: mips.ASGT, 13792 reg: regInfo{ 13793 inputs: []inputInfo{ 13794 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13795 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13796 }, 13797 outputs: []outputInfo{ 13798 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13799 }, 13800 }, 13801 }, 13802 { 13803 name: "SGTconst", 13804 auxType: auxInt32, 13805 argLen: 1, 13806 asm: mips.ASGT, 13807 reg: regInfo{ 13808 inputs: []inputInfo{ 13809 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13810 }, 13811 outputs: []outputInfo{ 13812 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13813 }, 13814 }, 13815 }, 13816 { 13817 name: "SGTzero", 13818 argLen: 1, 13819 asm: mips.ASGT, 13820 reg: regInfo{ 13821 inputs: []inputInfo{ 13822 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13823 }, 13824 outputs: []outputInfo{ 13825 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13826 }, 13827 }, 13828 }, 13829 { 13830 name: "SGTU", 13831 argLen: 2, 13832 asm: mips.ASGTU, 13833 reg: regInfo{ 13834 inputs: []inputInfo{ 13835 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13836 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13837 }, 13838 outputs: []outputInfo{ 13839 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13840 }, 13841 }, 13842 }, 13843 { 13844 name: "SGTUconst", 13845 auxType: auxInt32, 13846 argLen: 1, 13847 asm: mips.ASGTU, 13848 reg: regInfo{ 13849 inputs: []inputInfo{ 13850 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13851 }, 13852 outputs: []outputInfo{ 13853 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13854 }, 13855 }, 13856 }, 13857 { 13858 name: "SGTUzero", 13859 argLen: 1, 13860 asm: mips.ASGTU, 13861 reg: regInfo{ 13862 inputs: []inputInfo{ 13863 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13864 }, 13865 outputs: []outputInfo{ 13866 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13867 }, 13868 }, 13869 }, 13870 { 13871 name: "CMPEQF", 13872 argLen: 2, 13873 asm: mips.ACMPEQF, 13874 reg: regInfo{ 13875 inputs: []inputInfo{ 13876 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13877 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13878 }, 13879 }, 13880 }, 13881 { 13882 name: "CMPEQD", 13883 argLen: 2, 13884 asm: mips.ACMPEQD, 13885 reg: regInfo{ 13886 inputs: []inputInfo{ 13887 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13888 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13889 }, 13890 }, 13891 }, 13892 { 13893 name: "CMPGEF", 13894 argLen: 2, 13895 asm: mips.ACMPGEF, 13896 reg: regInfo{ 13897 inputs: []inputInfo{ 13898 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13899 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13900 }, 13901 }, 13902 }, 13903 { 13904 name: "CMPGED", 13905 argLen: 2, 13906 asm: mips.ACMPGED, 13907 reg: regInfo{ 13908 inputs: []inputInfo{ 13909 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13910 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13911 }, 13912 }, 13913 }, 13914 { 13915 name: "CMPGTF", 13916 argLen: 2, 13917 asm: mips.ACMPGTF, 13918 reg: regInfo{ 13919 inputs: []inputInfo{ 13920 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13921 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13922 }, 13923 }, 13924 }, 13925 { 13926 name: "CMPGTD", 13927 argLen: 2, 13928 asm: mips.ACMPGTD, 13929 reg: regInfo{ 13930 inputs: []inputInfo{ 13931 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13932 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13933 }, 13934 }, 13935 }, 13936 { 13937 name: "MOVWconst", 13938 auxType: auxInt32, 13939 argLen: 0, 13940 rematerializeable: true, 13941 asm: mips.AMOVW, 13942 reg: regInfo{ 13943 outputs: []outputInfo{ 13944 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13945 }, 13946 }, 13947 }, 13948 { 13949 name: "MOVFconst", 13950 auxType: auxFloat32, 13951 argLen: 0, 13952 rematerializeable: true, 13953 asm: mips.AMOVF, 13954 reg: regInfo{ 13955 outputs: []outputInfo{ 13956 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13957 }, 13958 }, 13959 }, 13960 { 13961 name: "MOVDconst", 13962 auxType: auxFloat64, 13963 argLen: 0, 13964 rematerializeable: true, 13965 asm: mips.AMOVD, 13966 reg: regInfo{ 13967 outputs: []outputInfo{ 13968 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13969 }, 13970 }, 13971 }, 13972 { 13973 name: "MOVWaddr", 13974 auxType: auxSymOff, 13975 argLen: 1, 13976 rematerializeable: true, 13977 symEffect: SymAddr, 13978 asm: mips.AMOVW, 13979 reg: regInfo{ 13980 inputs: []inputInfo{ 13981 {0, 140737555464192}, // SP SB 13982 }, 13983 outputs: []outputInfo{ 13984 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13985 }, 13986 }, 13987 }, 13988 { 13989 name: "MOVBload", 13990 auxType: auxSymOff, 13991 argLen: 2, 13992 faultOnNilArg0: true, 13993 symEffect: SymRead, 13994 asm: mips.AMOVB, 13995 reg: regInfo{ 13996 inputs: []inputInfo{ 13997 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13998 }, 13999 outputs: []outputInfo{ 14000 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14001 }, 14002 }, 14003 }, 14004 { 14005 name: "MOVBUload", 14006 auxType: auxSymOff, 14007 argLen: 2, 14008 faultOnNilArg0: true, 14009 symEffect: SymRead, 14010 asm: mips.AMOVBU, 14011 reg: regInfo{ 14012 inputs: []inputInfo{ 14013 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14014 }, 14015 outputs: []outputInfo{ 14016 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14017 }, 14018 }, 14019 }, 14020 { 14021 name: "MOVHload", 14022 auxType: auxSymOff, 14023 argLen: 2, 14024 faultOnNilArg0: true, 14025 symEffect: SymRead, 14026 asm: mips.AMOVH, 14027 reg: regInfo{ 14028 inputs: []inputInfo{ 14029 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14030 }, 14031 outputs: []outputInfo{ 14032 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14033 }, 14034 }, 14035 }, 14036 { 14037 name: "MOVHUload", 14038 auxType: auxSymOff, 14039 argLen: 2, 14040 faultOnNilArg0: true, 14041 symEffect: SymRead, 14042 asm: mips.AMOVHU, 14043 reg: regInfo{ 14044 inputs: []inputInfo{ 14045 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14046 }, 14047 outputs: []outputInfo{ 14048 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14049 }, 14050 }, 14051 }, 14052 { 14053 name: "MOVWload", 14054 auxType: auxSymOff, 14055 argLen: 2, 14056 faultOnNilArg0: true, 14057 symEffect: SymRead, 14058 asm: mips.AMOVW, 14059 reg: regInfo{ 14060 inputs: []inputInfo{ 14061 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14062 }, 14063 outputs: []outputInfo{ 14064 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14065 }, 14066 }, 14067 }, 14068 { 14069 name: "MOVFload", 14070 auxType: auxSymOff, 14071 argLen: 2, 14072 faultOnNilArg0: true, 14073 symEffect: SymRead, 14074 asm: mips.AMOVF, 14075 reg: regInfo{ 14076 inputs: []inputInfo{ 14077 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14078 }, 14079 outputs: []outputInfo{ 14080 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14081 }, 14082 }, 14083 }, 14084 { 14085 name: "MOVDload", 14086 auxType: auxSymOff, 14087 argLen: 2, 14088 faultOnNilArg0: true, 14089 symEffect: SymRead, 14090 asm: mips.AMOVD, 14091 reg: regInfo{ 14092 inputs: []inputInfo{ 14093 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14094 }, 14095 outputs: []outputInfo{ 14096 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14097 }, 14098 }, 14099 }, 14100 { 14101 name: "MOVBstore", 14102 auxType: auxSymOff, 14103 argLen: 3, 14104 faultOnNilArg0: true, 14105 symEffect: SymWrite, 14106 asm: mips.AMOVB, 14107 reg: regInfo{ 14108 inputs: []inputInfo{ 14109 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14110 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14111 }, 14112 }, 14113 }, 14114 { 14115 name: "MOVHstore", 14116 auxType: auxSymOff, 14117 argLen: 3, 14118 faultOnNilArg0: true, 14119 symEffect: SymWrite, 14120 asm: mips.AMOVH, 14121 reg: regInfo{ 14122 inputs: []inputInfo{ 14123 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14124 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14125 }, 14126 }, 14127 }, 14128 { 14129 name: "MOVWstore", 14130 auxType: auxSymOff, 14131 argLen: 3, 14132 faultOnNilArg0: true, 14133 symEffect: SymWrite, 14134 asm: mips.AMOVW, 14135 reg: regInfo{ 14136 inputs: []inputInfo{ 14137 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14138 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14139 }, 14140 }, 14141 }, 14142 { 14143 name: "MOVFstore", 14144 auxType: auxSymOff, 14145 argLen: 3, 14146 faultOnNilArg0: true, 14147 symEffect: SymWrite, 14148 asm: mips.AMOVF, 14149 reg: regInfo{ 14150 inputs: []inputInfo{ 14151 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14152 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14153 }, 14154 }, 14155 }, 14156 { 14157 name: "MOVDstore", 14158 auxType: auxSymOff, 14159 argLen: 3, 14160 faultOnNilArg0: true, 14161 symEffect: SymWrite, 14162 asm: mips.AMOVD, 14163 reg: regInfo{ 14164 inputs: []inputInfo{ 14165 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14166 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14167 }, 14168 }, 14169 }, 14170 { 14171 name: "MOVBstorezero", 14172 auxType: auxSymOff, 14173 argLen: 2, 14174 faultOnNilArg0: true, 14175 symEffect: SymWrite, 14176 asm: mips.AMOVB, 14177 reg: regInfo{ 14178 inputs: []inputInfo{ 14179 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14180 }, 14181 }, 14182 }, 14183 { 14184 name: "MOVHstorezero", 14185 auxType: auxSymOff, 14186 argLen: 2, 14187 faultOnNilArg0: true, 14188 symEffect: SymWrite, 14189 asm: mips.AMOVH, 14190 reg: regInfo{ 14191 inputs: []inputInfo{ 14192 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14193 }, 14194 }, 14195 }, 14196 { 14197 name: "MOVWstorezero", 14198 auxType: auxSymOff, 14199 argLen: 2, 14200 faultOnNilArg0: true, 14201 symEffect: SymWrite, 14202 asm: mips.AMOVW, 14203 reg: regInfo{ 14204 inputs: []inputInfo{ 14205 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14206 }, 14207 }, 14208 }, 14209 { 14210 name: "MOVBreg", 14211 argLen: 1, 14212 asm: mips.AMOVB, 14213 reg: regInfo{ 14214 inputs: []inputInfo{ 14215 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14216 }, 14217 outputs: []outputInfo{ 14218 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14219 }, 14220 }, 14221 }, 14222 { 14223 name: "MOVBUreg", 14224 argLen: 1, 14225 asm: mips.AMOVBU, 14226 reg: regInfo{ 14227 inputs: []inputInfo{ 14228 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14229 }, 14230 outputs: []outputInfo{ 14231 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14232 }, 14233 }, 14234 }, 14235 { 14236 name: "MOVHreg", 14237 argLen: 1, 14238 asm: mips.AMOVH, 14239 reg: regInfo{ 14240 inputs: []inputInfo{ 14241 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14242 }, 14243 outputs: []outputInfo{ 14244 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14245 }, 14246 }, 14247 }, 14248 { 14249 name: "MOVHUreg", 14250 argLen: 1, 14251 asm: mips.AMOVHU, 14252 reg: regInfo{ 14253 inputs: []inputInfo{ 14254 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14255 }, 14256 outputs: []outputInfo{ 14257 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14258 }, 14259 }, 14260 }, 14261 { 14262 name: "MOVWreg", 14263 argLen: 1, 14264 asm: mips.AMOVW, 14265 reg: regInfo{ 14266 inputs: []inputInfo{ 14267 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14268 }, 14269 outputs: []outputInfo{ 14270 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14271 }, 14272 }, 14273 }, 14274 { 14275 name: "MOVWnop", 14276 argLen: 1, 14277 resultInArg0: true, 14278 reg: regInfo{ 14279 inputs: []inputInfo{ 14280 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14281 }, 14282 outputs: []outputInfo{ 14283 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14284 }, 14285 }, 14286 }, 14287 { 14288 name: "CMOVZ", 14289 argLen: 3, 14290 resultInArg0: true, 14291 asm: mips.ACMOVZ, 14292 reg: regInfo{ 14293 inputs: []inputInfo{ 14294 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14295 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14296 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14297 }, 14298 outputs: []outputInfo{ 14299 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14300 }, 14301 }, 14302 }, 14303 { 14304 name: "CMOVZzero", 14305 argLen: 2, 14306 resultInArg0: true, 14307 asm: mips.ACMOVZ, 14308 reg: regInfo{ 14309 inputs: []inputInfo{ 14310 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14311 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14312 }, 14313 outputs: []outputInfo{ 14314 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14315 }, 14316 }, 14317 }, 14318 { 14319 name: "MOVWF", 14320 argLen: 1, 14321 asm: mips.AMOVWF, 14322 reg: regInfo{ 14323 inputs: []inputInfo{ 14324 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14325 }, 14326 outputs: []outputInfo{ 14327 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14328 }, 14329 }, 14330 }, 14331 { 14332 name: "MOVWD", 14333 argLen: 1, 14334 asm: mips.AMOVWD, 14335 reg: regInfo{ 14336 inputs: []inputInfo{ 14337 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14338 }, 14339 outputs: []outputInfo{ 14340 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14341 }, 14342 }, 14343 }, 14344 { 14345 name: "TRUNCFW", 14346 argLen: 1, 14347 asm: mips.ATRUNCFW, 14348 reg: regInfo{ 14349 inputs: []inputInfo{ 14350 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14351 }, 14352 outputs: []outputInfo{ 14353 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14354 }, 14355 }, 14356 }, 14357 { 14358 name: "TRUNCDW", 14359 argLen: 1, 14360 asm: mips.ATRUNCDW, 14361 reg: regInfo{ 14362 inputs: []inputInfo{ 14363 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14364 }, 14365 outputs: []outputInfo{ 14366 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14367 }, 14368 }, 14369 }, 14370 { 14371 name: "MOVFD", 14372 argLen: 1, 14373 asm: mips.AMOVFD, 14374 reg: regInfo{ 14375 inputs: []inputInfo{ 14376 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14377 }, 14378 outputs: []outputInfo{ 14379 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14380 }, 14381 }, 14382 }, 14383 { 14384 name: "MOVDF", 14385 argLen: 1, 14386 asm: mips.AMOVDF, 14387 reg: regInfo{ 14388 inputs: []inputInfo{ 14389 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14390 }, 14391 outputs: []outputInfo{ 14392 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14393 }, 14394 }, 14395 }, 14396 { 14397 name: "CALLstatic", 14398 auxType: auxSymOff, 14399 argLen: 1, 14400 clobberFlags: true, 14401 call: true, 14402 symEffect: SymNone, 14403 reg: regInfo{ 14404 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14405 }, 14406 }, 14407 { 14408 name: "CALLclosure", 14409 auxType: auxInt64, 14410 argLen: 3, 14411 clobberFlags: true, 14412 call: true, 14413 reg: regInfo{ 14414 inputs: []inputInfo{ 14415 {1, 4194304}, // R22 14416 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 14417 }, 14418 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14419 }, 14420 }, 14421 { 14422 name: "CALLinter", 14423 auxType: auxInt64, 14424 argLen: 2, 14425 clobberFlags: true, 14426 call: true, 14427 reg: regInfo{ 14428 inputs: []inputInfo{ 14429 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14430 }, 14431 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14432 }, 14433 }, 14434 { 14435 name: "LoweredAtomicLoad", 14436 argLen: 2, 14437 faultOnNilArg0: true, 14438 reg: regInfo{ 14439 inputs: []inputInfo{ 14440 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14441 }, 14442 outputs: []outputInfo{ 14443 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14444 }, 14445 }, 14446 }, 14447 { 14448 name: "LoweredAtomicStore", 14449 argLen: 3, 14450 faultOnNilArg0: true, 14451 hasSideEffects: true, 14452 reg: regInfo{ 14453 inputs: []inputInfo{ 14454 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14455 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14456 }, 14457 }, 14458 }, 14459 { 14460 name: "LoweredAtomicStorezero", 14461 argLen: 2, 14462 faultOnNilArg0: true, 14463 hasSideEffects: true, 14464 reg: regInfo{ 14465 inputs: []inputInfo{ 14466 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14467 }, 14468 }, 14469 }, 14470 { 14471 name: "LoweredAtomicExchange", 14472 argLen: 3, 14473 resultNotInArgs: true, 14474 faultOnNilArg0: true, 14475 hasSideEffects: true, 14476 reg: regInfo{ 14477 inputs: []inputInfo{ 14478 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14479 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14480 }, 14481 outputs: []outputInfo{ 14482 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14483 }, 14484 }, 14485 }, 14486 { 14487 name: "LoweredAtomicAdd", 14488 argLen: 3, 14489 resultNotInArgs: true, 14490 faultOnNilArg0: true, 14491 hasSideEffects: true, 14492 reg: regInfo{ 14493 inputs: []inputInfo{ 14494 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14495 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14496 }, 14497 outputs: []outputInfo{ 14498 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14499 }, 14500 }, 14501 }, 14502 { 14503 name: "LoweredAtomicAddconst", 14504 auxType: auxInt32, 14505 argLen: 2, 14506 resultNotInArgs: true, 14507 faultOnNilArg0: true, 14508 hasSideEffects: true, 14509 reg: regInfo{ 14510 inputs: []inputInfo{ 14511 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14512 }, 14513 outputs: []outputInfo{ 14514 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14515 }, 14516 }, 14517 }, 14518 { 14519 name: "LoweredAtomicCas", 14520 argLen: 4, 14521 resultNotInArgs: true, 14522 faultOnNilArg0: true, 14523 hasSideEffects: true, 14524 reg: regInfo{ 14525 inputs: []inputInfo{ 14526 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14527 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14528 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14529 }, 14530 outputs: []outputInfo{ 14531 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14532 }, 14533 }, 14534 }, 14535 { 14536 name: "LoweredAtomicAnd", 14537 argLen: 3, 14538 faultOnNilArg0: true, 14539 hasSideEffects: true, 14540 asm: mips.AAND, 14541 reg: regInfo{ 14542 inputs: []inputInfo{ 14543 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14544 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14545 }, 14546 }, 14547 }, 14548 { 14549 name: "LoweredAtomicOr", 14550 argLen: 3, 14551 faultOnNilArg0: true, 14552 hasSideEffects: true, 14553 asm: mips.AOR, 14554 reg: regInfo{ 14555 inputs: []inputInfo{ 14556 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14557 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14558 }, 14559 }, 14560 }, 14561 { 14562 name: "LoweredZero", 14563 auxType: auxInt32, 14564 argLen: 3, 14565 faultOnNilArg0: true, 14566 reg: regInfo{ 14567 inputs: []inputInfo{ 14568 {0, 2}, // R1 14569 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14570 }, 14571 clobbers: 2, // R1 14572 }, 14573 }, 14574 { 14575 name: "LoweredMove", 14576 auxType: auxInt32, 14577 argLen: 4, 14578 faultOnNilArg0: true, 14579 faultOnNilArg1: true, 14580 reg: regInfo{ 14581 inputs: []inputInfo{ 14582 {0, 4}, // R2 14583 {1, 2}, // R1 14584 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14585 }, 14586 clobbers: 6, // R1 R2 14587 }, 14588 }, 14589 { 14590 name: "LoweredNilCheck", 14591 argLen: 2, 14592 nilCheck: true, 14593 faultOnNilArg0: true, 14594 reg: regInfo{ 14595 inputs: []inputInfo{ 14596 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14597 }, 14598 }, 14599 }, 14600 { 14601 name: "FPFlagTrue", 14602 argLen: 1, 14603 reg: regInfo{ 14604 outputs: []outputInfo{ 14605 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14606 }, 14607 }, 14608 }, 14609 { 14610 name: "FPFlagFalse", 14611 argLen: 1, 14612 reg: regInfo{ 14613 outputs: []outputInfo{ 14614 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14615 }, 14616 }, 14617 }, 14618 { 14619 name: "LoweredGetClosurePtr", 14620 argLen: 0, 14621 reg: regInfo{ 14622 outputs: []outputInfo{ 14623 {0, 4194304}, // R22 14624 }, 14625 }, 14626 }, 14627 { 14628 name: "MOVWconvert", 14629 argLen: 2, 14630 asm: mips.AMOVW, 14631 reg: regInfo{ 14632 inputs: []inputInfo{ 14633 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14634 }, 14635 outputs: []outputInfo{ 14636 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14637 }, 14638 }, 14639 }, 14640 14641 { 14642 name: "ADDV", 14643 argLen: 2, 14644 commutative: true, 14645 asm: mips.AADDVU, 14646 reg: regInfo{ 14647 inputs: []inputInfo{ 14648 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14649 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14650 }, 14651 outputs: []outputInfo{ 14652 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14653 }, 14654 }, 14655 }, 14656 { 14657 name: "ADDVconst", 14658 auxType: auxInt64, 14659 argLen: 1, 14660 asm: mips.AADDVU, 14661 reg: regInfo{ 14662 inputs: []inputInfo{ 14663 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 14664 }, 14665 outputs: []outputInfo{ 14666 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14667 }, 14668 }, 14669 }, 14670 { 14671 name: "SUBV", 14672 argLen: 2, 14673 asm: mips.ASUBVU, 14674 reg: regInfo{ 14675 inputs: []inputInfo{ 14676 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14677 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14678 }, 14679 outputs: []outputInfo{ 14680 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14681 }, 14682 }, 14683 }, 14684 { 14685 name: "SUBVconst", 14686 auxType: auxInt64, 14687 argLen: 1, 14688 asm: mips.ASUBVU, 14689 reg: regInfo{ 14690 inputs: []inputInfo{ 14691 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14692 }, 14693 outputs: []outputInfo{ 14694 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14695 }, 14696 }, 14697 }, 14698 { 14699 name: "MULV", 14700 argLen: 2, 14701 commutative: true, 14702 asm: mips.AMULV, 14703 reg: regInfo{ 14704 inputs: []inputInfo{ 14705 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14706 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14707 }, 14708 outputs: []outputInfo{ 14709 {0, 1152921504606846976}, // HI 14710 {1, 2305843009213693952}, // LO 14711 }, 14712 }, 14713 }, 14714 { 14715 name: "MULVU", 14716 argLen: 2, 14717 commutative: true, 14718 asm: mips.AMULVU, 14719 reg: regInfo{ 14720 inputs: []inputInfo{ 14721 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14722 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14723 }, 14724 outputs: []outputInfo{ 14725 {0, 1152921504606846976}, // HI 14726 {1, 2305843009213693952}, // LO 14727 }, 14728 }, 14729 }, 14730 { 14731 name: "DIVV", 14732 argLen: 2, 14733 asm: mips.ADIVV, 14734 reg: regInfo{ 14735 inputs: []inputInfo{ 14736 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14737 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14738 }, 14739 outputs: []outputInfo{ 14740 {0, 1152921504606846976}, // HI 14741 {1, 2305843009213693952}, // LO 14742 }, 14743 }, 14744 }, 14745 { 14746 name: "DIVVU", 14747 argLen: 2, 14748 asm: mips.ADIVVU, 14749 reg: regInfo{ 14750 inputs: []inputInfo{ 14751 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14752 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14753 }, 14754 outputs: []outputInfo{ 14755 {0, 1152921504606846976}, // HI 14756 {1, 2305843009213693952}, // LO 14757 }, 14758 }, 14759 }, 14760 { 14761 name: "ADDF", 14762 argLen: 2, 14763 commutative: true, 14764 asm: mips.AADDF, 14765 reg: regInfo{ 14766 inputs: []inputInfo{ 14767 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14768 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14769 }, 14770 outputs: []outputInfo{ 14771 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14772 }, 14773 }, 14774 }, 14775 { 14776 name: "ADDD", 14777 argLen: 2, 14778 commutative: true, 14779 asm: mips.AADDD, 14780 reg: regInfo{ 14781 inputs: []inputInfo{ 14782 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14783 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14784 }, 14785 outputs: []outputInfo{ 14786 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14787 }, 14788 }, 14789 }, 14790 { 14791 name: "SUBF", 14792 argLen: 2, 14793 asm: mips.ASUBF, 14794 reg: regInfo{ 14795 inputs: []inputInfo{ 14796 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14797 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14798 }, 14799 outputs: []outputInfo{ 14800 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14801 }, 14802 }, 14803 }, 14804 { 14805 name: "SUBD", 14806 argLen: 2, 14807 asm: mips.ASUBD, 14808 reg: regInfo{ 14809 inputs: []inputInfo{ 14810 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14811 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14812 }, 14813 outputs: []outputInfo{ 14814 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14815 }, 14816 }, 14817 }, 14818 { 14819 name: "MULF", 14820 argLen: 2, 14821 commutative: true, 14822 asm: mips.AMULF, 14823 reg: regInfo{ 14824 inputs: []inputInfo{ 14825 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14826 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14827 }, 14828 outputs: []outputInfo{ 14829 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14830 }, 14831 }, 14832 }, 14833 { 14834 name: "MULD", 14835 argLen: 2, 14836 commutative: true, 14837 asm: mips.AMULD, 14838 reg: regInfo{ 14839 inputs: []inputInfo{ 14840 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14841 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14842 }, 14843 outputs: []outputInfo{ 14844 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14845 }, 14846 }, 14847 }, 14848 { 14849 name: "DIVF", 14850 argLen: 2, 14851 asm: mips.ADIVF, 14852 reg: regInfo{ 14853 inputs: []inputInfo{ 14854 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14855 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14856 }, 14857 outputs: []outputInfo{ 14858 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14859 }, 14860 }, 14861 }, 14862 { 14863 name: "DIVD", 14864 argLen: 2, 14865 asm: mips.ADIVD, 14866 reg: regInfo{ 14867 inputs: []inputInfo{ 14868 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14869 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14870 }, 14871 outputs: []outputInfo{ 14872 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14873 }, 14874 }, 14875 }, 14876 { 14877 name: "AND", 14878 argLen: 2, 14879 commutative: true, 14880 asm: mips.AAND, 14881 reg: regInfo{ 14882 inputs: []inputInfo{ 14883 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14884 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14885 }, 14886 outputs: []outputInfo{ 14887 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14888 }, 14889 }, 14890 }, 14891 { 14892 name: "ANDconst", 14893 auxType: auxInt64, 14894 argLen: 1, 14895 asm: mips.AAND, 14896 reg: regInfo{ 14897 inputs: []inputInfo{ 14898 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14899 }, 14900 outputs: []outputInfo{ 14901 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14902 }, 14903 }, 14904 }, 14905 { 14906 name: "OR", 14907 argLen: 2, 14908 commutative: true, 14909 asm: mips.AOR, 14910 reg: regInfo{ 14911 inputs: []inputInfo{ 14912 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14913 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14914 }, 14915 outputs: []outputInfo{ 14916 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14917 }, 14918 }, 14919 }, 14920 { 14921 name: "ORconst", 14922 auxType: auxInt64, 14923 argLen: 1, 14924 asm: mips.AOR, 14925 reg: regInfo{ 14926 inputs: []inputInfo{ 14927 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14928 }, 14929 outputs: []outputInfo{ 14930 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14931 }, 14932 }, 14933 }, 14934 { 14935 name: "XOR", 14936 argLen: 2, 14937 commutative: true, 14938 asm: mips.AXOR, 14939 reg: regInfo{ 14940 inputs: []inputInfo{ 14941 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14942 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14943 }, 14944 outputs: []outputInfo{ 14945 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14946 }, 14947 }, 14948 }, 14949 { 14950 name: "XORconst", 14951 auxType: auxInt64, 14952 argLen: 1, 14953 asm: mips.AXOR, 14954 reg: regInfo{ 14955 inputs: []inputInfo{ 14956 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14957 }, 14958 outputs: []outputInfo{ 14959 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14960 }, 14961 }, 14962 }, 14963 { 14964 name: "NOR", 14965 argLen: 2, 14966 commutative: true, 14967 asm: mips.ANOR, 14968 reg: regInfo{ 14969 inputs: []inputInfo{ 14970 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14971 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14972 }, 14973 outputs: []outputInfo{ 14974 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14975 }, 14976 }, 14977 }, 14978 { 14979 name: "NORconst", 14980 auxType: auxInt64, 14981 argLen: 1, 14982 asm: mips.ANOR, 14983 reg: regInfo{ 14984 inputs: []inputInfo{ 14985 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14986 }, 14987 outputs: []outputInfo{ 14988 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14989 }, 14990 }, 14991 }, 14992 { 14993 name: "NEGV", 14994 argLen: 1, 14995 reg: regInfo{ 14996 inputs: []inputInfo{ 14997 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14998 }, 14999 outputs: []outputInfo{ 15000 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15001 }, 15002 }, 15003 }, 15004 { 15005 name: "NEGF", 15006 argLen: 1, 15007 asm: mips.ANEGF, 15008 reg: regInfo{ 15009 inputs: []inputInfo{ 15010 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15011 }, 15012 outputs: []outputInfo{ 15013 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15014 }, 15015 }, 15016 }, 15017 { 15018 name: "NEGD", 15019 argLen: 1, 15020 asm: mips.ANEGD, 15021 reg: regInfo{ 15022 inputs: []inputInfo{ 15023 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15024 }, 15025 outputs: []outputInfo{ 15026 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15027 }, 15028 }, 15029 }, 15030 { 15031 name: "SLLV", 15032 argLen: 2, 15033 asm: mips.ASLLV, 15034 reg: regInfo{ 15035 inputs: []inputInfo{ 15036 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15037 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15038 }, 15039 outputs: []outputInfo{ 15040 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15041 }, 15042 }, 15043 }, 15044 { 15045 name: "SLLVconst", 15046 auxType: auxInt64, 15047 argLen: 1, 15048 asm: mips.ASLLV, 15049 reg: regInfo{ 15050 inputs: []inputInfo{ 15051 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15052 }, 15053 outputs: []outputInfo{ 15054 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15055 }, 15056 }, 15057 }, 15058 { 15059 name: "SRLV", 15060 argLen: 2, 15061 asm: mips.ASRLV, 15062 reg: regInfo{ 15063 inputs: []inputInfo{ 15064 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15065 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15066 }, 15067 outputs: []outputInfo{ 15068 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15069 }, 15070 }, 15071 }, 15072 { 15073 name: "SRLVconst", 15074 auxType: auxInt64, 15075 argLen: 1, 15076 asm: mips.ASRLV, 15077 reg: regInfo{ 15078 inputs: []inputInfo{ 15079 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15080 }, 15081 outputs: []outputInfo{ 15082 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15083 }, 15084 }, 15085 }, 15086 { 15087 name: "SRAV", 15088 argLen: 2, 15089 asm: mips.ASRAV, 15090 reg: regInfo{ 15091 inputs: []inputInfo{ 15092 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15093 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15094 }, 15095 outputs: []outputInfo{ 15096 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15097 }, 15098 }, 15099 }, 15100 { 15101 name: "SRAVconst", 15102 auxType: auxInt64, 15103 argLen: 1, 15104 asm: mips.ASRAV, 15105 reg: regInfo{ 15106 inputs: []inputInfo{ 15107 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15108 }, 15109 outputs: []outputInfo{ 15110 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15111 }, 15112 }, 15113 }, 15114 { 15115 name: "SGT", 15116 argLen: 2, 15117 asm: mips.ASGT, 15118 reg: regInfo{ 15119 inputs: []inputInfo{ 15120 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15121 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15122 }, 15123 outputs: []outputInfo{ 15124 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15125 }, 15126 }, 15127 }, 15128 { 15129 name: "SGTconst", 15130 auxType: auxInt64, 15131 argLen: 1, 15132 asm: mips.ASGT, 15133 reg: regInfo{ 15134 inputs: []inputInfo{ 15135 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15136 }, 15137 outputs: []outputInfo{ 15138 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15139 }, 15140 }, 15141 }, 15142 { 15143 name: "SGTU", 15144 argLen: 2, 15145 asm: mips.ASGTU, 15146 reg: regInfo{ 15147 inputs: []inputInfo{ 15148 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15149 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15150 }, 15151 outputs: []outputInfo{ 15152 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15153 }, 15154 }, 15155 }, 15156 { 15157 name: "SGTUconst", 15158 auxType: auxInt64, 15159 argLen: 1, 15160 asm: mips.ASGTU, 15161 reg: regInfo{ 15162 inputs: []inputInfo{ 15163 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15164 }, 15165 outputs: []outputInfo{ 15166 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15167 }, 15168 }, 15169 }, 15170 { 15171 name: "CMPEQF", 15172 argLen: 2, 15173 asm: mips.ACMPEQF, 15174 reg: regInfo{ 15175 inputs: []inputInfo{ 15176 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15177 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15178 }, 15179 }, 15180 }, 15181 { 15182 name: "CMPEQD", 15183 argLen: 2, 15184 asm: mips.ACMPEQD, 15185 reg: regInfo{ 15186 inputs: []inputInfo{ 15187 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15188 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15189 }, 15190 }, 15191 }, 15192 { 15193 name: "CMPGEF", 15194 argLen: 2, 15195 asm: mips.ACMPGEF, 15196 reg: regInfo{ 15197 inputs: []inputInfo{ 15198 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15199 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15200 }, 15201 }, 15202 }, 15203 { 15204 name: "CMPGED", 15205 argLen: 2, 15206 asm: mips.ACMPGED, 15207 reg: regInfo{ 15208 inputs: []inputInfo{ 15209 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15210 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15211 }, 15212 }, 15213 }, 15214 { 15215 name: "CMPGTF", 15216 argLen: 2, 15217 asm: mips.ACMPGTF, 15218 reg: regInfo{ 15219 inputs: []inputInfo{ 15220 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15221 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15222 }, 15223 }, 15224 }, 15225 { 15226 name: "CMPGTD", 15227 argLen: 2, 15228 asm: mips.ACMPGTD, 15229 reg: regInfo{ 15230 inputs: []inputInfo{ 15231 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15232 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15233 }, 15234 }, 15235 }, 15236 { 15237 name: "MOVVconst", 15238 auxType: auxInt64, 15239 argLen: 0, 15240 rematerializeable: true, 15241 asm: mips.AMOVV, 15242 reg: regInfo{ 15243 outputs: []outputInfo{ 15244 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15245 }, 15246 }, 15247 }, 15248 { 15249 name: "MOVFconst", 15250 auxType: auxFloat64, 15251 argLen: 0, 15252 rematerializeable: true, 15253 asm: mips.AMOVF, 15254 reg: regInfo{ 15255 outputs: []outputInfo{ 15256 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15257 }, 15258 }, 15259 }, 15260 { 15261 name: "MOVDconst", 15262 auxType: auxFloat64, 15263 argLen: 0, 15264 rematerializeable: true, 15265 asm: mips.AMOVD, 15266 reg: regInfo{ 15267 outputs: []outputInfo{ 15268 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15269 }, 15270 }, 15271 }, 15272 { 15273 name: "MOVVaddr", 15274 auxType: auxSymOff, 15275 argLen: 1, 15276 rematerializeable: true, 15277 symEffect: SymAddr, 15278 asm: mips.AMOVV, 15279 reg: regInfo{ 15280 inputs: []inputInfo{ 15281 {0, 4611686018460942336}, // SP SB 15282 }, 15283 outputs: []outputInfo{ 15284 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15285 }, 15286 }, 15287 }, 15288 { 15289 name: "MOVBload", 15290 auxType: auxSymOff, 15291 argLen: 2, 15292 faultOnNilArg0: true, 15293 symEffect: SymRead, 15294 asm: mips.AMOVB, 15295 reg: regInfo{ 15296 inputs: []inputInfo{ 15297 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15298 }, 15299 outputs: []outputInfo{ 15300 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15301 }, 15302 }, 15303 }, 15304 { 15305 name: "MOVBUload", 15306 auxType: auxSymOff, 15307 argLen: 2, 15308 faultOnNilArg0: true, 15309 symEffect: SymRead, 15310 asm: mips.AMOVBU, 15311 reg: regInfo{ 15312 inputs: []inputInfo{ 15313 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15314 }, 15315 outputs: []outputInfo{ 15316 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15317 }, 15318 }, 15319 }, 15320 { 15321 name: "MOVHload", 15322 auxType: auxSymOff, 15323 argLen: 2, 15324 faultOnNilArg0: true, 15325 symEffect: SymRead, 15326 asm: mips.AMOVH, 15327 reg: regInfo{ 15328 inputs: []inputInfo{ 15329 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15330 }, 15331 outputs: []outputInfo{ 15332 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15333 }, 15334 }, 15335 }, 15336 { 15337 name: "MOVHUload", 15338 auxType: auxSymOff, 15339 argLen: 2, 15340 faultOnNilArg0: true, 15341 symEffect: SymRead, 15342 asm: mips.AMOVHU, 15343 reg: regInfo{ 15344 inputs: []inputInfo{ 15345 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15346 }, 15347 outputs: []outputInfo{ 15348 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15349 }, 15350 }, 15351 }, 15352 { 15353 name: "MOVWload", 15354 auxType: auxSymOff, 15355 argLen: 2, 15356 faultOnNilArg0: true, 15357 symEffect: SymRead, 15358 asm: mips.AMOVW, 15359 reg: regInfo{ 15360 inputs: []inputInfo{ 15361 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15362 }, 15363 outputs: []outputInfo{ 15364 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15365 }, 15366 }, 15367 }, 15368 { 15369 name: "MOVWUload", 15370 auxType: auxSymOff, 15371 argLen: 2, 15372 faultOnNilArg0: true, 15373 symEffect: SymRead, 15374 asm: mips.AMOVWU, 15375 reg: regInfo{ 15376 inputs: []inputInfo{ 15377 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15378 }, 15379 outputs: []outputInfo{ 15380 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15381 }, 15382 }, 15383 }, 15384 { 15385 name: "MOVVload", 15386 auxType: auxSymOff, 15387 argLen: 2, 15388 faultOnNilArg0: true, 15389 symEffect: SymRead, 15390 asm: mips.AMOVV, 15391 reg: regInfo{ 15392 inputs: []inputInfo{ 15393 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15394 }, 15395 outputs: []outputInfo{ 15396 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15397 }, 15398 }, 15399 }, 15400 { 15401 name: "MOVFload", 15402 auxType: auxSymOff, 15403 argLen: 2, 15404 faultOnNilArg0: true, 15405 symEffect: SymRead, 15406 asm: mips.AMOVF, 15407 reg: regInfo{ 15408 inputs: []inputInfo{ 15409 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15410 }, 15411 outputs: []outputInfo{ 15412 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15413 }, 15414 }, 15415 }, 15416 { 15417 name: "MOVDload", 15418 auxType: auxSymOff, 15419 argLen: 2, 15420 faultOnNilArg0: true, 15421 symEffect: SymRead, 15422 asm: mips.AMOVD, 15423 reg: regInfo{ 15424 inputs: []inputInfo{ 15425 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15426 }, 15427 outputs: []outputInfo{ 15428 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15429 }, 15430 }, 15431 }, 15432 { 15433 name: "MOVBstore", 15434 auxType: auxSymOff, 15435 argLen: 3, 15436 faultOnNilArg0: true, 15437 symEffect: SymWrite, 15438 asm: mips.AMOVB, 15439 reg: regInfo{ 15440 inputs: []inputInfo{ 15441 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15442 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15443 }, 15444 }, 15445 }, 15446 { 15447 name: "MOVHstore", 15448 auxType: auxSymOff, 15449 argLen: 3, 15450 faultOnNilArg0: true, 15451 symEffect: SymWrite, 15452 asm: mips.AMOVH, 15453 reg: regInfo{ 15454 inputs: []inputInfo{ 15455 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15456 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15457 }, 15458 }, 15459 }, 15460 { 15461 name: "MOVWstore", 15462 auxType: auxSymOff, 15463 argLen: 3, 15464 faultOnNilArg0: true, 15465 symEffect: SymWrite, 15466 asm: mips.AMOVW, 15467 reg: regInfo{ 15468 inputs: []inputInfo{ 15469 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15470 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15471 }, 15472 }, 15473 }, 15474 { 15475 name: "MOVVstore", 15476 auxType: auxSymOff, 15477 argLen: 3, 15478 faultOnNilArg0: true, 15479 symEffect: SymWrite, 15480 asm: mips.AMOVV, 15481 reg: regInfo{ 15482 inputs: []inputInfo{ 15483 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15484 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15485 }, 15486 }, 15487 }, 15488 { 15489 name: "MOVFstore", 15490 auxType: auxSymOff, 15491 argLen: 3, 15492 faultOnNilArg0: true, 15493 symEffect: SymWrite, 15494 asm: mips.AMOVF, 15495 reg: regInfo{ 15496 inputs: []inputInfo{ 15497 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15498 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15499 }, 15500 }, 15501 }, 15502 { 15503 name: "MOVDstore", 15504 auxType: auxSymOff, 15505 argLen: 3, 15506 faultOnNilArg0: true, 15507 symEffect: SymWrite, 15508 asm: mips.AMOVD, 15509 reg: regInfo{ 15510 inputs: []inputInfo{ 15511 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15512 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15513 }, 15514 }, 15515 }, 15516 { 15517 name: "MOVBstorezero", 15518 auxType: auxSymOff, 15519 argLen: 2, 15520 faultOnNilArg0: true, 15521 symEffect: SymWrite, 15522 asm: mips.AMOVB, 15523 reg: regInfo{ 15524 inputs: []inputInfo{ 15525 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15526 }, 15527 }, 15528 }, 15529 { 15530 name: "MOVHstorezero", 15531 auxType: auxSymOff, 15532 argLen: 2, 15533 faultOnNilArg0: true, 15534 symEffect: SymWrite, 15535 asm: mips.AMOVH, 15536 reg: regInfo{ 15537 inputs: []inputInfo{ 15538 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15539 }, 15540 }, 15541 }, 15542 { 15543 name: "MOVWstorezero", 15544 auxType: auxSymOff, 15545 argLen: 2, 15546 faultOnNilArg0: true, 15547 symEffect: SymWrite, 15548 asm: mips.AMOVW, 15549 reg: regInfo{ 15550 inputs: []inputInfo{ 15551 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15552 }, 15553 }, 15554 }, 15555 { 15556 name: "MOVVstorezero", 15557 auxType: auxSymOff, 15558 argLen: 2, 15559 faultOnNilArg0: true, 15560 symEffect: SymWrite, 15561 asm: mips.AMOVV, 15562 reg: regInfo{ 15563 inputs: []inputInfo{ 15564 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15565 }, 15566 }, 15567 }, 15568 { 15569 name: "MOVBreg", 15570 argLen: 1, 15571 asm: mips.AMOVB, 15572 reg: regInfo{ 15573 inputs: []inputInfo{ 15574 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15575 }, 15576 outputs: []outputInfo{ 15577 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15578 }, 15579 }, 15580 }, 15581 { 15582 name: "MOVBUreg", 15583 argLen: 1, 15584 asm: mips.AMOVBU, 15585 reg: regInfo{ 15586 inputs: []inputInfo{ 15587 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15588 }, 15589 outputs: []outputInfo{ 15590 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15591 }, 15592 }, 15593 }, 15594 { 15595 name: "MOVHreg", 15596 argLen: 1, 15597 asm: mips.AMOVH, 15598 reg: regInfo{ 15599 inputs: []inputInfo{ 15600 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15601 }, 15602 outputs: []outputInfo{ 15603 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15604 }, 15605 }, 15606 }, 15607 { 15608 name: "MOVHUreg", 15609 argLen: 1, 15610 asm: mips.AMOVHU, 15611 reg: regInfo{ 15612 inputs: []inputInfo{ 15613 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15614 }, 15615 outputs: []outputInfo{ 15616 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15617 }, 15618 }, 15619 }, 15620 { 15621 name: "MOVWreg", 15622 argLen: 1, 15623 asm: mips.AMOVW, 15624 reg: regInfo{ 15625 inputs: []inputInfo{ 15626 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15627 }, 15628 outputs: []outputInfo{ 15629 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15630 }, 15631 }, 15632 }, 15633 { 15634 name: "MOVWUreg", 15635 argLen: 1, 15636 asm: mips.AMOVWU, 15637 reg: regInfo{ 15638 inputs: []inputInfo{ 15639 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15640 }, 15641 outputs: []outputInfo{ 15642 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15643 }, 15644 }, 15645 }, 15646 { 15647 name: "MOVVreg", 15648 argLen: 1, 15649 asm: mips.AMOVV, 15650 reg: regInfo{ 15651 inputs: []inputInfo{ 15652 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15653 }, 15654 outputs: []outputInfo{ 15655 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15656 }, 15657 }, 15658 }, 15659 { 15660 name: "MOVVnop", 15661 argLen: 1, 15662 resultInArg0: true, 15663 reg: regInfo{ 15664 inputs: []inputInfo{ 15665 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15666 }, 15667 outputs: []outputInfo{ 15668 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15669 }, 15670 }, 15671 }, 15672 { 15673 name: "MOVWF", 15674 argLen: 1, 15675 asm: mips.AMOVWF, 15676 reg: regInfo{ 15677 inputs: []inputInfo{ 15678 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15679 }, 15680 outputs: []outputInfo{ 15681 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15682 }, 15683 }, 15684 }, 15685 { 15686 name: "MOVWD", 15687 argLen: 1, 15688 asm: mips.AMOVWD, 15689 reg: regInfo{ 15690 inputs: []inputInfo{ 15691 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15692 }, 15693 outputs: []outputInfo{ 15694 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15695 }, 15696 }, 15697 }, 15698 { 15699 name: "MOVVF", 15700 argLen: 1, 15701 asm: mips.AMOVVF, 15702 reg: regInfo{ 15703 inputs: []inputInfo{ 15704 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15705 }, 15706 outputs: []outputInfo{ 15707 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15708 }, 15709 }, 15710 }, 15711 { 15712 name: "MOVVD", 15713 argLen: 1, 15714 asm: mips.AMOVVD, 15715 reg: regInfo{ 15716 inputs: []inputInfo{ 15717 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15718 }, 15719 outputs: []outputInfo{ 15720 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15721 }, 15722 }, 15723 }, 15724 { 15725 name: "TRUNCFW", 15726 argLen: 1, 15727 asm: mips.ATRUNCFW, 15728 reg: regInfo{ 15729 inputs: []inputInfo{ 15730 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15731 }, 15732 outputs: []outputInfo{ 15733 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15734 }, 15735 }, 15736 }, 15737 { 15738 name: "TRUNCDW", 15739 argLen: 1, 15740 asm: mips.ATRUNCDW, 15741 reg: regInfo{ 15742 inputs: []inputInfo{ 15743 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15744 }, 15745 outputs: []outputInfo{ 15746 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15747 }, 15748 }, 15749 }, 15750 { 15751 name: "TRUNCFV", 15752 argLen: 1, 15753 asm: mips.ATRUNCFV, 15754 reg: regInfo{ 15755 inputs: []inputInfo{ 15756 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15757 }, 15758 outputs: []outputInfo{ 15759 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15760 }, 15761 }, 15762 }, 15763 { 15764 name: "TRUNCDV", 15765 argLen: 1, 15766 asm: mips.ATRUNCDV, 15767 reg: regInfo{ 15768 inputs: []inputInfo{ 15769 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15770 }, 15771 outputs: []outputInfo{ 15772 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15773 }, 15774 }, 15775 }, 15776 { 15777 name: "MOVFD", 15778 argLen: 1, 15779 asm: mips.AMOVFD, 15780 reg: regInfo{ 15781 inputs: []inputInfo{ 15782 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15783 }, 15784 outputs: []outputInfo{ 15785 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15786 }, 15787 }, 15788 }, 15789 { 15790 name: "MOVDF", 15791 argLen: 1, 15792 asm: mips.AMOVDF, 15793 reg: regInfo{ 15794 inputs: []inputInfo{ 15795 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15796 }, 15797 outputs: []outputInfo{ 15798 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15799 }, 15800 }, 15801 }, 15802 { 15803 name: "CALLstatic", 15804 auxType: auxSymOff, 15805 argLen: 1, 15806 clobberFlags: true, 15807 call: true, 15808 symEffect: SymNone, 15809 reg: regInfo{ 15810 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15811 }, 15812 }, 15813 { 15814 name: "CALLclosure", 15815 auxType: auxInt64, 15816 argLen: 3, 15817 clobberFlags: true, 15818 call: true, 15819 reg: regInfo{ 15820 inputs: []inputInfo{ 15821 {1, 4194304}, // R22 15822 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 15823 }, 15824 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15825 }, 15826 }, 15827 { 15828 name: "CALLinter", 15829 auxType: auxInt64, 15830 argLen: 2, 15831 clobberFlags: true, 15832 call: true, 15833 reg: regInfo{ 15834 inputs: []inputInfo{ 15835 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15836 }, 15837 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15838 }, 15839 }, 15840 { 15841 name: "DUFFZERO", 15842 auxType: auxInt64, 15843 argLen: 2, 15844 faultOnNilArg0: true, 15845 reg: regInfo{ 15846 inputs: []inputInfo{ 15847 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15848 }, 15849 clobbers: 134217730, // R1 R31 15850 }, 15851 }, 15852 { 15853 name: "LoweredZero", 15854 auxType: auxInt64, 15855 argLen: 3, 15856 clobberFlags: true, 15857 faultOnNilArg0: true, 15858 reg: regInfo{ 15859 inputs: []inputInfo{ 15860 {0, 2}, // R1 15861 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15862 }, 15863 clobbers: 2, // R1 15864 }, 15865 }, 15866 { 15867 name: "LoweredMove", 15868 auxType: auxInt64, 15869 argLen: 4, 15870 clobberFlags: true, 15871 faultOnNilArg0: true, 15872 faultOnNilArg1: true, 15873 reg: regInfo{ 15874 inputs: []inputInfo{ 15875 {0, 4}, // R2 15876 {1, 2}, // R1 15877 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15878 }, 15879 clobbers: 6, // R1 R2 15880 }, 15881 }, 15882 { 15883 name: "LoweredNilCheck", 15884 argLen: 2, 15885 nilCheck: true, 15886 faultOnNilArg0: true, 15887 reg: regInfo{ 15888 inputs: []inputInfo{ 15889 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15890 }, 15891 }, 15892 }, 15893 { 15894 name: "FPFlagTrue", 15895 argLen: 1, 15896 reg: regInfo{ 15897 outputs: []outputInfo{ 15898 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15899 }, 15900 }, 15901 }, 15902 { 15903 name: "FPFlagFalse", 15904 argLen: 1, 15905 reg: regInfo{ 15906 outputs: []outputInfo{ 15907 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15908 }, 15909 }, 15910 }, 15911 { 15912 name: "LoweredGetClosurePtr", 15913 argLen: 0, 15914 reg: regInfo{ 15915 outputs: []outputInfo{ 15916 {0, 4194304}, // R22 15917 }, 15918 }, 15919 }, 15920 { 15921 name: "MOVVconvert", 15922 argLen: 2, 15923 asm: mips.AMOVV, 15924 reg: regInfo{ 15925 inputs: []inputInfo{ 15926 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15927 }, 15928 outputs: []outputInfo{ 15929 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15930 }, 15931 }, 15932 }, 15933 15934 { 15935 name: "ADD", 15936 argLen: 2, 15937 commutative: true, 15938 asm: ppc64.AADD, 15939 reg: regInfo{ 15940 inputs: []inputInfo{ 15941 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15942 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15943 }, 15944 outputs: []outputInfo{ 15945 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15946 }, 15947 }, 15948 }, 15949 { 15950 name: "ADDconst", 15951 auxType: auxSymOff, 15952 argLen: 1, 15953 symEffect: SymAddr, 15954 asm: ppc64.AADD, 15955 reg: regInfo{ 15956 inputs: []inputInfo{ 15957 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15958 }, 15959 outputs: []outputInfo{ 15960 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15961 }, 15962 }, 15963 }, 15964 { 15965 name: "FADD", 15966 argLen: 2, 15967 commutative: true, 15968 asm: ppc64.AFADD, 15969 reg: regInfo{ 15970 inputs: []inputInfo{ 15971 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15972 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15973 }, 15974 outputs: []outputInfo{ 15975 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15976 }, 15977 }, 15978 }, 15979 { 15980 name: "FADDS", 15981 argLen: 2, 15982 commutative: true, 15983 asm: ppc64.AFADDS, 15984 reg: regInfo{ 15985 inputs: []inputInfo{ 15986 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15987 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15988 }, 15989 outputs: []outputInfo{ 15990 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15991 }, 15992 }, 15993 }, 15994 { 15995 name: "SUB", 15996 argLen: 2, 15997 asm: ppc64.ASUB, 15998 reg: regInfo{ 15999 inputs: []inputInfo{ 16000 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16001 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16002 }, 16003 outputs: []outputInfo{ 16004 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16005 }, 16006 }, 16007 }, 16008 { 16009 name: "FSUB", 16010 argLen: 2, 16011 asm: ppc64.AFSUB, 16012 reg: regInfo{ 16013 inputs: []inputInfo{ 16014 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16015 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16016 }, 16017 outputs: []outputInfo{ 16018 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16019 }, 16020 }, 16021 }, 16022 { 16023 name: "FSUBS", 16024 argLen: 2, 16025 asm: ppc64.AFSUBS, 16026 reg: regInfo{ 16027 inputs: []inputInfo{ 16028 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16029 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16030 }, 16031 outputs: []outputInfo{ 16032 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16033 }, 16034 }, 16035 }, 16036 { 16037 name: "MULLD", 16038 argLen: 2, 16039 commutative: true, 16040 asm: ppc64.AMULLD, 16041 reg: regInfo{ 16042 inputs: []inputInfo{ 16043 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16044 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16045 }, 16046 outputs: []outputInfo{ 16047 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16048 }, 16049 }, 16050 }, 16051 { 16052 name: "MULLW", 16053 argLen: 2, 16054 commutative: true, 16055 asm: ppc64.AMULLW, 16056 reg: regInfo{ 16057 inputs: []inputInfo{ 16058 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16059 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16060 }, 16061 outputs: []outputInfo{ 16062 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16063 }, 16064 }, 16065 }, 16066 { 16067 name: "MULHD", 16068 argLen: 2, 16069 commutative: true, 16070 asm: ppc64.AMULHD, 16071 reg: regInfo{ 16072 inputs: []inputInfo{ 16073 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16074 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16075 }, 16076 outputs: []outputInfo{ 16077 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16078 }, 16079 }, 16080 }, 16081 { 16082 name: "MULHW", 16083 argLen: 2, 16084 commutative: true, 16085 asm: ppc64.AMULHW, 16086 reg: regInfo{ 16087 inputs: []inputInfo{ 16088 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16089 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16090 }, 16091 outputs: []outputInfo{ 16092 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16093 }, 16094 }, 16095 }, 16096 { 16097 name: "MULHDU", 16098 argLen: 2, 16099 commutative: true, 16100 asm: ppc64.AMULHDU, 16101 reg: regInfo{ 16102 inputs: []inputInfo{ 16103 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16104 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16105 }, 16106 outputs: []outputInfo{ 16107 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16108 }, 16109 }, 16110 }, 16111 { 16112 name: "MULHWU", 16113 argLen: 2, 16114 commutative: true, 16115 asm: ppc64.AMULHWU, 16116 reg: regInfo{ 16117 inputs: []inputInfo{ 16118 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16119 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16120 }, 16121 outputs: []outputInfo{ 16122 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16123 }, 16124 }, 16125 }, 16126 { 16127 name: "FMUL", 16128 argLen: 2, 16129 commutative: true, 16130 asm: ppc64.AFMUL, 16131 reg: regInfo{ 16132 inputs: []inputInfo{ 16133 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16134 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16135 }, 16136 outputs: []outputInfo{ 16137 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16138 }, 16139 }, 16140 }, 16141 { 16142 name: "FMULS", 16143 argLen: 2, 16144 commutative: true, 16145 asm: ppc64.AFMULS, 16146 reg: regInfo{ 16147 inputs: []inputInfo{ 16148 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16149 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16150 }, 16151 outputs: []outputInfo{ 16152 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16153 }, 16154 }, 16155 }, 16156 { 16157 name: "FMADD", 16158 argLen: 3, 16159 asm: ppc64.AFMADD, 16160 reg: regInfo{ 16161 inputs: []inputInfo{ 16162 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16163 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16164 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16165 }, 16166 outputs: []outputInfo{ 16167 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16168 }, 16169 }, 16170 }, 16171 { 16172 name: "FMADDS", 16173 argLen: 3, 16174 asm: ppc64.AFMADDS, 16175 reg: regInfo{ 16176 inputs: []inputInfo{ 16177 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16178 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16179 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16180 }, 16181 outputs: []outputInfo{ 16182 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16183 }, 16184 }, 16185 }, 16186 { 16187 name: "FMSUB", 16188 argLen: 3, 16189 asm: ppc64.AFMSUB, 16190 reg: regInfo{ 16191 inputs: []inputInfo{ 16192 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16193 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16194 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16195 }, 16196 outputs: []outputInfo{ 16197 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16198 }, 16199 }, 16200 }, 16201 { 16202 name: "FMSUBS", 16203 argLen: 3, 16204 asm: ppc64.AFMSUBS, 16205 reg: regInfo{ 16206 inputs: []inputInfo{ 16207 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16208 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16209 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16210 }, 16211 outputs: []outputInfo{ 16212 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16213 }, 16214 }, 16215 }, 16216 { 16217 name: "SRAD", 16218 argLen: 2, 16219 asm: ppc64.ASRAD, 16220 reg: regInfo{ 16221 inputs: []inputInfo{ 16222 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16223 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16224 }, 16225 outputs: []outputInfo{ 16226 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16227 }, 16228 }, 16229 }, 16230 { 16231 name: "SRAW", 16232 argLen: 2, 16233 asm: ppc64.ASRAW, 16234 reg: regInfo{ 16235 inputs: []inputInfo{ 16236 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16237 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16238 }, 16239 outputs: []outputInfo{ 16240 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16241 }, 16242 }, 16243 }, 16244 { 16245 name: "SRD", 16246 argLen: 2, 16247 asm: ppc64.ASRD, 16248 reg: regInfo{ 16249 inputs: []inputInfo{ 16250 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16251 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16252 }, 16253 outputs: []outputInfo{ 16254 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16255 }, 16256 }, 16257 }, 16258 { 16259 name: "SRW", 16260 argLen: 2, 16261 asm: ppc64.ASRW, 16262 reg: regInfo{ 16263 inputs: []inputInfo{ 16264 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16265 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16266 }, 16267 outputs: []outputInfo{ 16268 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16269 }, 16270 }, 16271 }, 16272 { 16273 name: "SLD", 16274 argLen: 2, 16275 asm: ppc64.ASLD, 16276 reg: regInfo{ 16277 inputs: []inputInfo{ 16278 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16279 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16280 }, 16281 outputs: []outputInfo{ 16282 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16283 }, 16284 }, 16285 }, 16286 { 16287 name: "SLW", 16288 argLen: 2, 16289 asm: ppc64.ASLW, 16290 reg: regInfo{ 16291 inputs: []inputInfo{ 16292 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16293 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16294 }, 16295 outputs: []outputInfo{ 16296 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16297 }, 16298 }, 16299 }, 16300 { 16301 name: "ADDconstForCarry", 16302 auxType: auxInt16, 16303 argLen: 1, 16304 asm: ppc64.AADDC, 16305 reg: regInfo{ 16306 inputs: []inputInfo{ 16307 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16308 }, 16309 clobbers: 2147483648, // R31 16310 }, 16311 }, 16312 { 16313 name: "MaskIfNotCarry", 16314 argLen: 1, 16315 asm: ppc64.AADDME, 16316 reg: regInfo{ 16317 outputs: []outputInfo{ 16318 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16319 }, 16320 }, 16321 }, 16322 { 16323 name: "SRADconst", 16324 auxType: auxInt64, 16325 argLen: 1, 16326 asm: ppc64.ASRAD, 16327 reg: regInfo{ 16328 inputs: []inputInfo{ 16329 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16330 }, 16331 outputs: []outputInfo{ 16332 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16333 }, 16334 }, 16335 }, 16336 { 16337 name: "SRAWconst", 16338 auxType: auxInt64, 16339 argLen: 1, 16340 asm: ppc64.ASRAW, 16341 reg: regInfo{ 16342 inputs: []inputInfo{ 16343 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16344 }, 16345 outputs: []outputInfo{ 16346 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16347 }, 16348 }, 16349 }, 16350 { 16351 name: "SRDconst", 16352 auxType: auxInt64, 16353 argLen: 1, 16354 asm: ppc64.ASRD, 16355 reg: regInfo{ 16356 inputs: []inputInfo{ 16357 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16358 }, 16359 outputs: []outputInfo{ 16360 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16361 }, 16362 }, 16363 }, 16364 { 16365 name: "SRWconst", 16366 auxType: auxInt64, 16367 argLen: 1, 16368 asm: ppc64.ASRW, 16369 reg: regInfo{ 16370 inputs: []inputInfo{ 16371 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16372 }, 16373 outputs: []outputInfo{ 16374 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16375 }, 16376 }, 16377 }, 16378 { 16379 name: "SLDconst", 16380 auxType: auxInt64, 16381 argLen: 1, 16382 asm: ppc64.ASLD, 16383 reg: regInfo{ 16384 inputs: []inputInfo{ 16385 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16386 }, 16387 outputs: []outputInfo{ 16388 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16389 }, 16390 }, 16391 }, 16392 { 16393 name: "SLWconst", 16394 auxType: auxInt64, 16395 argLen: 1, 16396 asm: ppc64.ASLW, 16397 reg: regInfo{ 16398 inputs: []inputInfo{ 16399 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16400 }, 16401 outputs: []outputInfo{ 16402 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16403 }, 16404 }, 16405 }, 16406 { 16407 name: "FDIV", 16408 argLen: 2, 16409 asm: ppc64.AFDIV, 16410 reg: regInfo{ 16411 inputs: []inputInfo{ 16412 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16413 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16414 }, 16415 outputs: []outputInfo{ 16416 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16417 }, 16418 }, 16419 }, 16420 { 16421 name: "FDIVS", 16422 argLen: 2, 16423 asm: ppc64.AFDIVS, 16424 reg: regInfo{ 16425 inputs: []inputInfo{ 16426 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16427 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16428 }, 16429 outputs: []outputInfo{ 16430 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16431 }, 16432 }, 16433 }, 16434 { 16435 name: "DIVD", 16436 argLen: 2, 16437 asm: ppc64.ADIVD, 16438 reg: regInfo{ 16439 inputs: []inputInfo{ 16440 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16441 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16442 }, 16443 outputs: []outputInfo{ 16444 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16445 }, 16446 }, 16447 }, 16448 { 16449 name: "DIVW", 16450 argLen: 2, 16451 asm: ppc64.ADIVW, 16452 reg: regInfo{ 16453 inputs: []inputInfo{ 16454 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16455 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16456 }, 16457 outputs: []outputInfo{ 16458 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16459 }, 16460 }, 16461 }, 16462 { 16463 name: "DIVDU", 16464 argLen: 2, 16465 asm: ppc64.ADIVDU, 16466 reg: regInfo{ 16467 inputs: []inputInfo{ 16468 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16469 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16470 }, 16471 outputs: []outputInfo{ 16472 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16473 }, 16474 }, 16475 }, 16476 { 16477 name: "DIVWU", 16478 argLen: 2, 16479 asm: ppc64.ADIVWU, 16480 reg: regInfo{ 16481 inputs: []inputInfo{ 16482 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16483 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16484 }, 16485 outputs: []outputInfo{ 16486 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16487 }, 16488 }, 16489 }, 16490 { 16491 name: "FCTIDZ", 16492 argLen: 1, 16493 asm: ppc64.AFCTIDZ, 16494 reg: regInfo{ 16495 inputs: []inputInfo{ 16496 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16497 }, 16498 outputs: []outputInfo{ 16499 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16500 }, 16501 }, 16502 }, 16503 { 16504 name: "FCTIWZ", 16505 argLen: 1, 16506 asm: ppc64.AFCTIWZ, 16507 reg: regInfo{ 16508 inputs: []inputInfo{ 16509 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16510 }, 16511 outputs: []outputInfo{ 16512 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16513 }, 16514 }, 16515 }, 16516 { 16517 name: "FCFID", 16518 argLen: 1, 16519 asm: ppc64.AFCFID, 16520 reg: regInfo{ 16521 inputs: []inputInfo{ 16522 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16523 }, 16524 outputs: []outputInfo{ 16525 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16526 }, 16527 }, 16528 }, 16529 { 16530 name: "FRSP", 16531 argLen: 1, 16532 asm: ppc64.AFRSP, 16533 reg: regInfo{ 16534 inputs: []inputInfo{ 16535 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16536 }, 16537 outputs: []outputInfo{ 16538 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16539 }, 16540 }, 16541 }, 16542 { 16543 name: "Xf2i64", 16544 argLen: 1, 16545 reg: regInfo{ 16546 inputs: []inputInfo{ 16547 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16548 }, 16549 outputs: []outputInfo{ 16550 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16551 }, 16552 }, 16553 }, 16554 { 16555 name: "Xi2f64", 16556 argLen: 1, 16557 reg: regInfo{ 16558 inputs: []inputInfo{ 16559 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16560 }, 16561 outputs: []outputInfo{ 16562 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16563 }, 16564 }, 16565 }, 16566 { 16567 name: "AND", 16568 argLen: 2, 16569 commutative: true, 16570 asm: ppc64.AAND, 16571 reg: regInfo{ 16572 inputs: []inputInfo{ 16573 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16574 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16575 }, 16576 outputs: []outputInfo{ 16577 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16578 }, 16579 }, 16580 }, 16581 { 16582 name: "ANDN", 16583 argLen: 2, 16584 asm: ppc64.AANDN, 16585 reg: regInfo{ 16586 inputs: []inputInfo{ 16587 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16588 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16589 }, 16590 outputs: []outputInfo{ 16591 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16592 }, 16593 }, 16594 }, 16595 { 16596 name: "OR", 16597 argLen: 2, 16598 commutative: true, 16599 asm: ppc64.AOR, 16600 reg: regInfo{ 16601 inputs: []inputInfo{ 16602 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16603 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16604 }, 16605 outputs: []outputInfo{ 16606 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16607 }, 16608 }, 16609 }, 16610 { 16611 name: "ORN", 16612 argLen: 2, 16613 asm: ppc64.AORN, 16614 reg: regInfo{ 16615 inputs: []inputInfo{ 16616 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16617 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16618 }, 16619 outputs: []outputInfo{ 16620 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16621 }, 16622 }, 16623 }, 16624 { 16625 name: "NOR", 16626 argLen: 2, 16627 commutative: true, 16628 asm: ppc64.ANOR, 16629 reg: regInfo{ 16630 inputs: []inputInfo{ 16631 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16632 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16633 }, 16634 outputs: []outputInfo{ 16635 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16636 }, 16637 }, 16638 }, 16639 { 16640 name: "XOR", 16641 argLen: 2, 16642 commutative: true, 16643 asm: ppc64.AXOR, 16644 reg: regInfo{ 16645 inputs: []inputInfo{ 16646 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16647 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16648 }, 16649 outputs: []outputInfo{ 16650 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16651 }, 16652 }, 16653 }, 16654 { 16655 name: "EQV", 16656 argLen: 2, 16657 commutative: true, 16658 asm: ppc64.AEQV, 16659 reg: regInfo{ 16660 inputs: []inputInfo{ 16661 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16662 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16663 }, 16664 outputs: []outputInfo{ 16665 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16666 }, 16667 }, 16668 }, 16669 { 16670 name: "NEG", 16671 argLen: 1, 16672 asm: ppc64.ANEG, 16673 reg: regInfo{ 16674 inputs: []inputInfo{ 16675 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16676 }, 16677 outputs: []outputInfo{ 16678 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16679 }, 16680 }, 16681 }, 16682 { 16683 name: "FNEG", 16684 argLen: 1, 16685 asm: ppc64.AFNEG, 16686 reg: regInfo{ 16687 inputs: []inputInfo{ 16688 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16689 }, 16690 outputs: []outputInfo{ 16691 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16692 }, 16693 }, 16694 }, 16695 { 16696 name: "FSQRT", 16697 argLen: 1, 16698 asm: ppc64.AFSQRT, 16699 reg: regInfo{ 16700 inputs: []inputInfo{ 16701 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16702 }, 16703 outputs: []outputInfo{ 16704 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16705 }, 16706 }, 16707 }, 16708 { 16709 name: "FSQRTS", 16710 argLen: 1, 16711 asm: ppc64.AFSQRTS, 16712 reg: regInfo{ 16713 inputs: []inputInfo{ 16714 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16715 }, 16716 outputs: []outputInfo{ 16717 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16718 }, 16719 }, 16720 }, 16721 { 16722 name: "ORconst", 16723 auxType: auxInt64, 16724 argLen: 1, 16725 asm: ppc64.AOR, 16726 reg: regInfo{ 16727 inputs: []inputInfo{ 16728 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16729 }, 16730 outputs: []outputInfo{ 16731 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16732 }, 16733 }, 16734 }, 16735 { 16736 name: "XORconst", 16737 auxType: auxInt64, 16738 argLen: 1, 16739 asm: ppc64.AXOR, 16740 reg: regInfo{ 16741 inputs: []inputInfo{ 16742 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16743 }, 16744 outputs: []outputInfo{ 16745 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16746 }, 16747 }, 16748 }, 16749 { 16750 name: "ANDconst", 16751 auxType: auxInt64, 16752 argLen: 1, 16753 clobberFlags: true, 16754 asm: ppc64.AANDCC, 16755 reg: regInfo{ 16756 inputs: []inputInfo{ 16757 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16758 }, 16759 outputs: []outputInfo{ 16760 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16761 }, 16762 }, 16763 }, 16764 { 16765 name: "ANDCCconst", 16766 auxType: auxInt64, 16767 argLen: 1, 16768 asm: ppc64.AANDCC, 16769 reg: regInfo{ 16770 inputs: []inputInfo{ 16771 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16772 }, 16773 }, 16774 }, 16775 { 16776 name: "MOVBreg", 16777 argLen: 1, 16778 asm: ppc64.AMOVB, 16779 reg: regInfo{ 16780 inputs: []inputInfo{ 16781 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16782 }, 16783 outputs: []outputInfo{ 16784 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16785 }, 16786 }, 16787 }, 16788 { 16789 name: "MOVBZreg", 16790 argLen: 1, 16791 asm: ppc64.AMOVBZ, 16792 reg: regInfo{ 16793 inputs: []inputInfo{ 16794 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16795 }, 16796 outputs: []outputInfo{ 16797 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16798 }, 16799 }, 16800 }, 16801 { 16802 name: "MOVHreg", 16803 argLen: 1, 16804 asm: ppc64.AMOVH, 16805 reg: regInfo{ 16806 inputs: []inputInfo{ 16807 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16808 }, 16809 outputs: []outputInfo{ 16810 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16811 }, 16812 }, 16813 }, 16814 { 16815 name: "MOVHZreg", 16816 argLen: 1, 16817 asm: ppc64.AMOVHZ, 16818 reg: regInfo{ 16819 inputs: []inputInfo{ 16820 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16821 }, 16822 outputs: []outputInfo{ 16823 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16824 }, 16825 }, 16826 }, 16827 { 16828 name: "MOVWreg", 16829 argLen: 1, 16830 asm: ppc64.AMOVW, 16831 reg: regInfo{ 16832 inputs: []inputInfo{ 16833 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16834 }, 16835 outputs: []outputInfo{ 16836 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16837 }, 16838 }, 16839 }, 16840 { 16841 name: "MOVWZreg", 16842 argLen: 1, 16843 asm: ppc64.AMOVWZ, 16844 reg: regInfo{ 16845 inputs: []inputInfo{ 16846 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16847 }, 16848 outputs: []outputInfo{ 16849 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16850 }, 16851 }, 16852 }, 16853 { 16854 name: "MOVBZload", 16855 auxType: auxSymOff, 16856 argLen: 2, 16857 faultOnNilArg0: true, 16858 symEffect: SymRead, 16859 asm: ppc64.AMOVBZ, 16860 reg: regInfo{ 16861 inputs: []inputInfo{ 16862 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16863 }, 16864 outputs: []outputInfo{ 16865 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16866 }, 16867 }, 16868 }, 16869 { 16870 name: "MOVHload", 16871 auxType: auxSymOff, 16872 argLen: 2, 16873 faultOnNilArg0: true, 16874 symEffect: SymRead, 16875 asm: ppc64.AMOVH, 16876 reg: regInfo{ 16877 inputs: []inputInfo{ 16878 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16879 }, 16880 outputs: []outputInfo{ 16881 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16882 }, 16883 }, 16884 }, 16885 { 16886 name: "MOVHZload", 16887 auxType: auxSymOff, 16888 argLen: 2, 16889 faultOnNilArg0: true, 16890 symEffect: SymRead, 16891 asm: ppc64.AMOVHZ, 16892 reg: regInfo{ 16893 inputs: []inputInfo{ 16894 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16895 }, 16896 outputs: []outputInfo{ 16897 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16898 }, 16899 }, 16900 }, 16901 { 16902 name: "MOVWload", 16903 auxType: auxSymOff, 16904 argLen: 2, 16905 faultOnNilArg0: true, 16906 symEffect: SymRead, 16907 asm: ppc64.AMOVW, 16908 reg: regInfo{ 16909 inputs: []inputInfo{ 16910 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16911 }, 16912 outputs: []outputInfo{ 16913 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16914 }, 16915 }, 16916 }, 16917 { 16918 name: "MOVWZload", 16919 auxType: auxSymOff, 16920 argLen: 2, 16921 faultOnNilArg0: true, 16922 symEffect: SymRead, 16923 asm: ppc64.AMOVWZ, 16924 reg: regInfo{ 16925 inputs: []inputInfo{ 16926 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16927 }, 16928 outputs: []outputInfo{ 16929 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16930 }, 16931 }, 16932 }, 16933 { 16934 name: "MOVDload", 16935 auxType: auxSymOff, 16936 argLen: 2, 16937 faultOnNilArg0: true, 16938 symEffect: SymRead, 16939 asm: ppc64.AMOVD, 16940 reg: regInfo{ 16941 inputs: []inputInfo{ 16942 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16943 }, 16944 outputs: []outputInfo{ 16945 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16946 }, 16947 }, 16948 }, 16949 { 16950 name: "FMOVDload", 16951 auxType: auxSymOff, 16952 argLen: 2, 16953 faultOnNilArg0: true, 16954 symEffect: SymRead, 16955 asm: ppc64.AFMOVD, 16956 reg: regInfo{ 16957 inputs: []inputInfo{ 16958 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16959 }, 16960 outputs: []outputInfo{ 16961 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16962 }, 16963 }, 16964 }, 16965 { 16966 name: "FMOVSload", 16967 auxType: auxSymOff, 16968 argLen: 2, 16969 faultOnNilArg0: true, 16970 symEffect: SymRead, 16971 asm: ppc64.AFMOVS, 16972 reg: regInfo{ 16973 inputs: []inputInfo{ 16974 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16975 }, 16976 outputs: []outputInfo{ 16977 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16978 }, 16979 }, 16980 }, 16981 { 16982 name: "MOVBstore", 16983 auxType: auxSymOff, 16984 argLen: 3, 16985 faultOnNilArg0: true, 16986 symEffect: SymWrite, 16987 asm: ppc64.AMOVB, 16988 reg: regInfo{ 16989 inputs: []inputInfo{ 16990 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16991 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16992 }, 16993 }, 16994 }, 16995 { 16996 name: "MOVHstore", 16997 auxType: auxSymOff, 16998 argLen: 3, 16999 faultOnNilArg0: true, 17000 symEffect: SymWrite, 17001 asm: ppc64.AMOVH, 17002 reg: regInfo{ 17003 inputs: []inputInfo{ 17004 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17005 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17006 }, 17007 }, 17008 }, 17009 { 17010 name: "MOVWstore", 17011 auxType: auxSymOff, 17012 argLen: 3, 17013 faultOnNilArg0: true, 17014 symEffect: SymWrite, 17015 asm: ppc64.AMOVW, 17016 reg: regInfo{ 17017 inputs: []inputInfo{ 17018 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17019 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17020 }, 17021 }, 17022 }, 17023 { 17024 name: "MOVDstore", 17025 auxType: auxSymOff, 17026 argLen: 3, 17027 faultOnNilArg0: true, 17028 symEffect: SymWrite, 17029 asm: ppc64.AMOVD, 17030 reg: regInfo{ 17031 inputs: []inputInfo{ 17032 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17033 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17034 }, 17035 }, 17036 }, 17037 { 17038 name: "FMOVDstore", 17039 auxType: auxSymOff, 17040 argLen: 3, 17041 faultOnNilArg0: true, 17042 symEffect: SymWrite, 17043 asm: ppc64.AFMOVD, 17044 reg: regInfo{ 17045 inputs: []inputInfo{ 17046 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17047 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17048 }, 17049 }, 17050 }, 17051 { 17052 name: "FMOVSstore", 17053 auxType: auxSymOff, 17054 argLen: 3, 17055 faultOnNilArg0: true, 17056 symEffect: SymWrite, 17057 asm: ppc64.AFMOVS, 17058 reg: regInfo{ 17059 inputs: []inputInfo{ 17060 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17061 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17062 }, 17063 }, 17064 }, 17065 { 17066 name: "MOVBstorezero", 17067 auxType: auxSymOff, 17068 argLen: 2, 17069 faultOnNilArg0: true, 17070 symEffect: SymWrite, 17071 asm: ppc64.AMOVB, 17072 reg: regInfo{ 17073 inputs: []inputInfo{ 17074 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17075 }, 17076 }, 17077 }, 17078 { 17079 name: "MOVHstorezero", 17080 auxType: auxSymOff, 17081 argLen: 2, 17082 faultOnNilArg0: true, 17083 symEffect: SymWrite, 17084 asm: ppc64.AMOVH, 17085 reg: regInfo{ 17086 inputs: []inputInfo{ 17087 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17088 }, 17089 }, 17090 }, 17091 { 17092 name: "MOVWstorezero", 17093 auxType: auxSymOff, 17094 argLen: 2, 17095 faultOnNilArg0: true, 17096 symEffect: SymWrite, 17097 asm: ppc64.AMOVW, 17098 reg: regInfo{ 17099 inputs: []inputInfo{ 17100 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17101 }, 17102 }, 17103 }, 17104 { 17105 name: "MOVDstorezero", 17106 auxType: auxSymOff, 17107 argLen: 2, 17108 faultOnNilArg0: true, 17109 symEffect: SymWrite, 17110 asm: ppc64.AMOVD, 17111 reg: regInfo{ 17112 inputs: []inputInfo{ 17113 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17114 }, 17115 }, 17116 }, 17117 { 17118 name: "MOVDaddr", 17119 auxType: auxSymOff, 17120 argLen: 1, 17121 rematerializeable: true, 17122 symEffect: SymAddr, 17123 asm: ppc64.AMOVD, 17124 reg: regInfo{ 17125 inputs: []inputInfo{ 17126 {0, 6}, // SP SB 17127 }, 17128 outputs: []outputInfo{ 17129 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17130 }, 17131 }, 17132 }, 17133 { 17134 name: "MOVDconst", 17135 auxType: auxInt64, 17136 argLen: 0, 17137 rematerializeable: true, 17138 asm: ppc64.AMOVD, 17139 reg: regInfo{ 17140 outputs: []outputInfo{ 17141 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17142 }, 17143 }, 17144 }, 17145 { 17146 name: "FMOVDconst", 17147 auxType: auxFloat64, 17148 argLen: 0, 17149 rematerializeable: true, 17150 asm: ppc64.AFMOVD, 17151 reg: regInfo{ 17152 outputs: []outputInfo{ 17153 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17154 }, 17155 }, 17156 }, 17157 { 17158 name: "FMOVSconst", 17159 auxType: auxFloat32, 17160 argLen: 0, 17161 rematerializeable: true, 17162 asm: ppc64.AFMOVS, 17163 reg: regInfo{ 17164 outputs: []outputInfo{ 17165 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17166 }, 17167 }, 17168 }, 17169 { 17170 name: "FCMPU", 17171 argLen: 2, 17172 asm: ppc64.AFCMPU, 17173 reg: regInfo{ 17174 inputs: []inputInfo{ 17175 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17176 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17177 }, 17178 }, 17179 }, 17180 { 17181 name: "CMP", 17182 argLen: 2, 17183 asm: ppc64.ACMP, 17184 reg: regInfo{ 17185 inputs: []inputInfo{ 17186 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17187 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17188 }, 17189 }, 17190 }, 17191 { 17192 name: "CMPU", 17193 argLen: 2, 17194 asm: ppc64.ACMPU, 17195 reg: regInfo{ 17196 inputs: []inputInfo{ 17197 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17198 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17199 }, 17200 }, 17201 }, 17202 { 17203 name: "CMPW", 17204 argLen: 2, 17205 asm: ppc64.ACMPW, 17206 reg: regInfo{ 17207 inputs: []inputInfo{ 17208 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17209 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17210 }, 17211 }, 17212 }, 17213 { 17214 name: "CMPWU", 17215 argLen: 2, 17216 asm: ppc64.ACMPWU, 17217 reg: regInfo{ 17218 inputs: []inputInfo{ 17219 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17220 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17221 }, 17222 }, 17223 }, 17224 { 17225 name: "CMPconst", 17226 auxType: auxInt64, 17227 argLen: 1, 17228 asm: ppc64.ACMP, 17229 reg: regInfo{ 17230 inputs: []inputInfo{ 17231 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17232 }, 17233 }, 17234 }, 17235 { 17236 name: "CMPUconst", 17237 auxType: auxInt64, 17238 argLen: 1, 17239 asm: ppc64.ACMPU, 17240 reg: regInfo{ 17241 inputs: []inputInfo{ 17242 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17243 }, 17244 }, 17245 }, 17246 { 17247 name: "CMPWconst", 17248 auxType: auxInt32, 17249 argLen: 1, 17250 asm: ppc64.ACMPW, 17251 reg: regInfo{ 17252 inputs: []inputInfo{ 17253 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17254 }, 17255 }, 17256 }, 17257 { 17258 name: "CMPWUconst", 17259 auxType: auxInt32, 17260 argLen: 1, 17261 asm: ppc64.ACMPWU, 17262 reg: regInfo{ 17263 inputs: []inputInfo{ 17264 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17265 }, 17266 }, 17267 }, 17268 { 17269 name: "Equal", 17270 argLen: 1, 17271 reg: regInfo{ 17272 outputs: []outputInfo{ 17273 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17274 }, 17275 }, 17276 }, 17277 { 17278 name: "NotEqual", 17279 argLen: 1, 17280 reg: regInfo{ 17281 outputs: []outputInfo{ 17282 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17283 }, 17284 }, 17285 }, 17286 { 17287 name: "LessThan", 17288 argLen: 1, 17289 reg: regInfo{ 17290 outputs: []outputInfo{ 17291 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17292 }, 17293 }, 17294 }, 17295 { 17296 name: "FLessThan", 17297 argLen: 1, 17298 reg: regInfo{ 17299 outputs: []outputInfo{ 17300 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17301 }, 17302 }, 17303 }, 17304 { 17305 name: "LessEqual", 17306 argLen: 1, 17307 reg: regInfo{ 17308 outputs: []outputInfo{ 17309 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17310 }, 17311 }, 17312 }, 17313 { 17314 name: "FLessEqual", 17315 argLen: 1, 17316 reg: regInfo{ 17317 outputs: []outputInfo{ 17318 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17319 }, 17320 }, 17321 }, 17322 { 17323 name: "GreaterThan", 17324 argLen: 1, 17325 reg: regInfo{ 17326 outputs: []outputInfo{ 17327 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17328 }, 17329 }, 17330 }, 17331 { 17332 name: "FGreaterThan", 17333 argLen: 1, 17334 reg: regInfo{ 17335 outputs: []outputInfo{ 17336 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17337 }, 17338 }, 17339 }, 17340 { 17341 name: "GreaterEqual", 17342 argLen: 1, 17343 reg: regInfo{ 17344 outputs: []outputInfo{ 17345 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17346 }, 17347 }, 17348 }, 17349 { 17350 name: "FGreaterEqual", 17351 argLen: 1, 17352 reg: regInfo{ 17353 outputs: []outputInfo{ 17354 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17355 }, 17356 }, 17357 }, 17358 { 17359 name: "LoweredGetClosurePtr", 17360 argLen: 0, 17361 reg: regInfo{ 17362 outputs: []outputInfo{ 17363 {0, 2048}, // R11 17364 }, 17365 }, 17366 }, 17367 { 17368 name: "LoweredNilCheck", 17369 argLen: 2, 17370 clobberFlags: true, 17371 nilCheck: true, 17372 faultOnNilArg0: true, 17373 reg: regInfo{ 17374 inputs: []inputInfo{ 17375 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17376 }, 17377 clobbers: 2147483648, // R31 17378 }, 17379 }, 17380 { 17381 name: "LoweredRound32F", 17382 argLen: 1, 17383 resultInArg0: true, 17384 reg: regInfo{ 17385 inputs: []inputInfo{ 17386 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17387 }, 17388 outputs: []outputInfo{ 17389 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17390 }, 17391 }, 17392 }, 17393 { 17394 name: "LoweredRound64F", 17395 argLen: 1, 17396 resultInArg0: true, 17397 reg: regInfo{ 17398 inputs: []inputInfo{ 17399 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17400 }, 17401 outputs: []outputInfo{ 17402 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17403 }, 17404 }, 17405 }, 17406 { 17407 name: "MOVDconvert", 17408 argLen: 2, 17409 asm: ppc64.AMOVD, 17410 reg: regInfo{ 17411 inputs: []inputInfo{ 17412 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17413 }, 17414 outputs: []outputInfo{ 17415 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17416 }, 17417 }, 17418 }, 17419 { 17420 name: "CALLstatic", 17421 auxType: auxSymOff, 17422 argLen: 1, 17423 clobberFlags: true, 17424 call: true, 17425 symEffect: SymNone, 17426 reg: regInfo{ 17427 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17428 }, 17429 }, 17430 { 17431 name: "CALLclosure", 17432 auxType: auxInt64, 17433 argLen: 3, 17434 clobberFlags: true, 17435 call: true, 17436 reg: regInfo{ 17437 inputs: []inputInfo{ 17438 {1, 2048}, // R11 17439 {0, 1073733626}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17440 }, 17441 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17442 }, 17443 }, 17444 { 17445 name: "CALLinter", 17446 auxType: auxInt64, 17447 argLen: 2, 17448 clobberFlags: true, 17449 call: true, 17450 reg: regInfo{ 17451 inputs: []inputInfo{ 17452 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17453 }, 17454 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17455 }, 17456 }, 17457 { 17458 name: "LoweredZero", 17459 auxType: auxInt64, 17460 argLen: 2, 17461 clobberFlags: true, 17462 faultOnNilArg0: true, 17463 reg: regInfo{ 17464 inputs: []inputInfo{ 17465 {0, 8}, // R3 17466 }, 17467 clobbers: 8, // R3 17468 }, 17469 }, 17470 { 17471 name: "LoweredMove", 17472 auxType: auxInt64, 17473 argLen: 3, 17474 clobberFlags: true, 17475 faultOnNilArg0: true, 17476 faultOnNilArg1: true, 17477 reg: regInfo{ 17478 inputs: []inputInfo{ 17479 {0, 8}, // R3 17480 {1, 16}, // R4 17481 }, 17482 clobbers: 1944, // R3 R4 R7 R8 R9 R10 17483 }, 17484 }, 17485 { 17486 name: "LoweredAtomicStore32", 17487 argLen: 3, 17488 faultOnNilArg0: true, 17489 hasSideEffects: true, 17490 reg: regInfo{ 17491 inputs: []inputInfo{ 17492 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17493 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17494 }, 17495 }, 17496 }, 17497 { 17498 name: "LoweredAtomicStore64", 17499 argLen: 3, 17500 faultOnNilArg0: true, 17501 hasSideEffects: true, 17502 reg: regInfo{ 17503 inputs: []inputInfo{ 17504 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17505 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17506 }, 17507 }, 17508 }, 17509 { 17510 name: "LoweredAtomicLoad32", 17511 argLen: 2, 17512 clobberFlags: true, 17513 faultOnNilArg0: true, 17514 reg: regInfo{ 17515 inputs: []inputInfo{ 17516 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17517 }, 17518 outputs: []outputInfo{ 17519 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17520 }, 17521 }, 17522 }, 17523 { 17524 name: "LoweredAtomicLoad64", 17525 argLen: 2, 17526 clobberFlags: true, 17527 faultOnNilArg0: true, 17528 reg: regInfo{ 17529 inputs: []inputInfo{ 17530 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17531 }, 17532 outputs: []outputInfo{ 17533 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17534 }, 17535 }, 17536 }, 17537 { 17538 name: "LoweredAtomicLoadPtr", 17539 argLen: 2, 17540 clobberFlags: true, 17541 faultOnNilArg0: true, 17542 reg: regInfo{ 17543 inputs: []inputInfo{ 17544 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17545 }, 17546 outputs: []outputInfo{ 17547 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17548 }, 17549 }, 17550 }, 17551 { 17552 name: "LoweredAtomicAdd32", 17553 argLen: 3, 17554 resultNotInArgs: true, 17555 clobberFlags: true, 17556 faultOnNilArg0: true, 17557 hasSideEffects: true, 17558 reg: regInfo{ 17559 inputs: []inputInfo{ 17560 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17561 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17562 }, 17563 outputs: []outputInfo{ 17564 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17565 }, 17566 }, 17567 }, 17568 { 17569 name: "LoweredAtomicAdd64", 17570 argLen: 3, 17571 resultNotInArgs: true, 17572 clobberFlags: true, 17573 faultOnNilArg0: true, 17574 hasSideEffects: true, 17575 reg: regInfo{ 17576 inputs: []inputInfo{ 17577 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17578 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17579 }, 17580 outputs: []outputInfo{ 17581 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17582 }, 17583 }, 17584 }, 17585 { 17586 name: "LoweredAtomicExchange32", 17587 argLen: 3, 17588 resultNotInArgs: true, 17589 clobberFlags: true, 17590 faultOnNilArg0: true, 17591 hasSideEffects: true, 17592 reg: regInfo{ 17593 inputs: []inputInfo{ 17594 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17595 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17596 }, 17597 outputs: []outputInfo{ 17598 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17599 }, 17600 }, 17601 }, 17602 { 17603 name: "LoweredAtomicExchange64", 17604 argLen: 3, 17605 resultNotInArgs: true, 17606 clobberFlags: true, 17607 faultOnNilArg0: true, 17608 hasSideEffects: true, 17609 reg: regInfo{ 17610 inputs: []inputInfo{ 17611 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17612 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17613 }, 17614 outputs: []outputInfo{ 17615 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17616 }, 17617 }, 17618 }, 17619 { 17620 name: "LoweredAtomicCas64", 17621 argLen: 4, 17622 resultNotInArgs: true, 17623 clobberFlags: true, 17624 faultOnNilArg0: true, 17625 hasSideEffects: true, 17626 reg: regInfo{ 17627 inputs: []inputInfo{ 17628 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17629 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17630 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17631 }, 17632 outputs: []outputInfo{ 17633 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17634 }, 17635 }, 17636 }, 17637 { 17638 name: "LoweredAtomicCas32", 17639 argLen: 4, 17640 resultNotInArgs: true, 17641 clobberFlags: true, 17642 faultOnNilArg0: true, 17643 hasSideEffects: true, 17644 reg: regInfo{ 17645 inputs: []inputInfo{ 17646 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17647 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17648 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17649 }, 17650 outputs: []outputInfo{ 17651 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17652 }, 17653 }, 17654 }, 17655 { 17656 name: "LoweredAtomicAnd8", 17657 argLen: 3, 17658 faultOnNilArg0: true, 17659 hasSideEffects: true, 17660 asm: ppc64.AAND, 17661 reg: regInfo{ 17662 inputs: []inputInfo{ 17663 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17664 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17665 }, 17666 }, 17667 }, 17668 { 17669 name: "LoweredAtomicOr8", 17670 argLen: 3, 17671 faultOnNilArg0: true, 17672 hasSideEffects: true, 17673 asm: ppc64.AOR, 17674 reg: regInfo{ 17675 inputs: []inputInfo{ 17676 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17677 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17678 }, 17679 }, 17680 }, 17681 { 17682 name: "InvertFlags", 17683 argLen: 1, 17684 reg: regInfo{}, 17685 }, 17686 { 17687 name: "FlagEQ", 17688 argLen: 0, 17689 reg: regInfo{}, 17690 }, 17691 { 17692 name: "FlagLT", 17693 argLen: 0, 17694 reg: regInfo{}, 17695 }, 17696 { 17697 name: "FlagGT", 17698 argLen: 0, 17699 reg: regInfo{}, 17700 }, 17701 17702 { 17703 name: "FADDS", 17704 argLen: 2, 17705 commutative: true, 17706 resultInArg0: true, 17707 clobberFlags: true, 17708 asm: s390x.AFADDS, 17709 reg: regInfo{ 17710 inputs: []inputInfo{ 17711 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17712 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17713 }, 17714 outputs: []outputInfo{ 17715 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17716 }, 17717 }, 17718 }, 17719 { 17720 name: "FADD", 17721 argLen: 2, 17722 commutative: true, 17723 resultInArg0: true, 17724 clobberFlags: true, 17725 asm: s390x.AFADD, 17726 reg: regInfo{ 17727 inputs: []inputInfo{ 17728 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17729 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17730 }, 17731 outputs: []outputInfo{ 17732 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17733 }, 17734 }, 17735 }, 17736 { 17737 name: "FSUBS", 17738 argLen: 2, 17739 resultInArg0: true, 17740 clobberFlags: true, 17741 asm: s390x.AFSUBS, 17742 reg: regInfo{ 17743 inputs: []inputInfo{ 17744 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17745 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17746 }, 17747 outputs: []outputInfo{ 17748 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17749 }, 17750 }, 17751 }, 17752 { 17753 name: "FSUB", 17754 argLen: 2, 17755 resultInArg0: true, 17756 clobberFlags: true, 17757 asm: s390x.AFSUB, 17758 reg: regInfo{ 17759 inputs: []inputInfo{ 17760 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17761 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17762 }, 17763 outputs: []outputInfo{ 17764 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17765 }, 17766 }, 17767 }, 17768 { 17769 name: "FMULS", 17770 argLen: 2, 17771 commutative: true, 17772 resultInArg0: true, 17773 asm: s390x.AFMULS, 17774 reg: regInfo{ 17775 inputs: []inputInfo{ 17776 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17777 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17778 }, 17779 outputs: []outputInfo{ 17780 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17781 }, 17782 }, 17783 }, 17784 { 17785 name: "FMUL", 17786 argLen: 2, 17787 commutative: true, 17788 resultInArg0: true, 17789 asm: s390x.AFMUL, 17790 reg: regInfo{ 17791 inputs: []inputInfo{ 17792 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17793 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17794 }, 17795 outputs: []outputInfo{ 17796 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17797 }, 17798 }, 17799 }, 17800 { 17801 name: "FDIVS", 17802 argLen: 2, 17803 resultInArg0: true, 17804 asm: s390x.AFDIVS, 17805 reg: regInfo{ 17806 inputs: []inputInfo{ 17807 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17808 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17809 }, 17810 outputs: []outputInfo{ 17811 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17812 }, 17813 }, 17814 }, 17815 { 17816 name: "FDIV", 17817 argLen: 2, 17818 resultInArg0: true, 17819 asm: s390x.AFDIV, 17820 reg: regInfo{ 17821 inputs: []inputInfo{ 17822 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17823 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17824 }, 17825 outputs: []outputInfo{ 17826 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17827 }, 17828 }, 17829 }, 17830 { 17831 name: "FNEGS", 17832 argLen: 1, 17833 clobberFlags: true, 17834 asm: s390x.AFNEGS, 17835 reg: regInfo{ 17836 inputs: []inputInfo{ 17837 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17838 }, 17839 outputs: []outputInfo{ 17840 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17841 }, 17842 }, 17843 }, 17844 { 17845 name: "FNEG", 17846 argLen: 1, 17847 clobberFlags: true, 17848 asm: s390x.AFNEG, 17849 reg: regInfo{ 17850 inputs: []inputInfo{ 17851 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17852 }, 17853 outputs: []outputInfo{ 17854 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17855 }, 17856 }, 17857 }, 17858 { 17859 name: "FMADDS", 17860 argLen: 3, 17861 resultInArg0: true, 17862 asm: s390x.AFMADDS, 17863 reg: regInfo{ 17864 inputs: []inputInfo{ 17865 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17866 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17867 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17868 }, 17869 outputs: []outputInfo{ 17870 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17871 }, 17872 }, 17873 }, 17874 { 17875 name: "FMADD", 17876 argLen: 3, 17877 resultInArg0: true, 17878 asm: s390x.AFMADD, 17879 reg: regInfo{ 17880 inputs: []inputInfo{ 17881 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17882 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17883 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17884 }, 17885 outputs: []outputInfo{ 17886 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17887 }, 17888 }, 17889 }, 17890 { 17891 name: "FMSUBS", 17892 argLen: 3, 17893 resultInArg0: true, 17894 asm: s390x.AFMSUBS, 17895 reg: regInfo{ 17896 inputs: []inputInfo{ 17897 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17898 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17899 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17900 }, 17901 outputs: []outputInfo{ 17902 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17903 }, 17904 }, 17905 }, 17906 { 17907 name: "FMSUB", 17908 argLen: 3, 17909 resultInArg0: true, 17910 asm: s390x.AFMSUB, 17911 reg: regInfo{ 17912 inputs: []inputInfo{ 17913 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17914 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17915 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17916 }, 17917 outputs: []outputInfo{ 17918 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17919 }, 17920 }, 17921 }, 17922 { 17923 name: "FMOVSload", 17924 auxType: auxSymOff, 17925 argLen: 2, 17926 faultOnNilArg0: true, 17927 symEffect: SymRead, 17928 asm: s390x.AFMOVS, 17929 reg: regInfo{ 17930 inputs: []inputInfo{ 17931 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17932 }, 17933 outputs: []outputInfo{ 17934 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17935 }, 17936 }, 17937 }, 17938 { 17939 name: "FMOVDload", 17940 auxType: auxSymOff, 17941 argLen: 2, 17942 faultOnNilArg0: true, 17943 symEffect: SymRead, 17944 asm: s390x.AFMOVD, 17945 reg: regInfo{ 17946 inputs: []inputInfo{ 17947 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17948 }, 17949 outputs: []outputInfo{ 17950 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17951 }, 17952 }, 17953 }, 17954 { 17955 name: "FMOVSconst", 17956 auxType: auxFloat32, 17957 argLen: 0, 17958 rematerializeable: true, 17959 asm: s390x.AFMOVS, 17960 reg: regInfo{ 17961 outputs: []outputInfo{ 17962 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17963 }, 17964 }, 17965 }, 17966 { 17967 name: "FMOVDconst", 17968 auxType: auxFloat64, 17969 argLen: 0, 17970 rematerializeable: true, 17971 asm: s390x.AFMOVD, 17972 reg: regInfo{ 17973 outputs: []outputInfo{ 17974 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17975 }, 17976 }, 17977 }, 17978 { 17979 name: "FMOVSloadidx", 17980 auxType: auxSymOff, 17981 argLen: 3, 17982 symEffect: SymRead, 17983 asm: s390x.AFMOVS, 17984 reg: regInfo{ 17985 inputs: []inputInfo{ 17986 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17987 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17988 }, 17989 outputs: []outputInfo{ 17990 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17991 }, 17992 }, 17993 }, 17994 { 17995 name: "FMOVDloadidx", 17996 auxType: auxSymOff, 17997 argLen: 3, 17998 symEffect: SymRead, 17999 asm: s390x.AFMOVD, 18000 reg: regInfo{ 18001 inputs: []inputInfo{ 18002 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18003 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18004 }, 18005 outputs: []outputInfo{ 18006 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18007 }, 18008 }, 18009 }, 18010 { 18011 name: "FMOVSstore", 18012 auxType: auxSymOff, 18013 argLen: 3, 18014 faultOnNilArg0: true, 18015 symEffect: SymWrite, 18016 asm: s390x.AFMOVS, 18017 reg: regInfo{ 18018 inputs: []inputInfo{ 18019 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18020 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18021 }, 18022 }, 18023 }, 18024 { 18025 name: "FMOVDstore", 18026 auxType: auxSymOff, 18027 argLen: 3, 18028 faultOnNilArg0: true, 18029 symEffect: SymWrite, 18030 asm: s390x.AFMOVD, 18031 reg: regInfo{ 18032 inputs: []inputInfo{ 18033 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18034 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18035 }, 18036 }, 18037 }, 18038 { 18039 name: "FMOVSstoreidx", 18040 auxType: auxSymOff, 18041 argLen: 4, 18042 symEffect: SymWrite, 18043 asm: s390x.AFMOVS, 18044 reg: regInfo{ 18045 inputs: []inputInfo{ 18046 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18047 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18048 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18049 }, 18050 }, 18051 }, 18052 { 18053 name: "FMOVDstoreidx", 18054 auxType: auxSymOff, 18055 argLen: 4, 18056 symEffect: SymWrite, 18057 asm: s390x.AFMOVD, 18058 reg: regInfo{ 18059 inputs: []inputInfo{ 18060 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18061 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18062 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18063 }, 18064 }, 18065 }, 18066 { 18067 name: "ADD", 18068 argLen: 2, 18069 commutative: true, 18070 clobberFlags: true, 18071 asm: s390x.AADD, 18072 reg: regInfo{ 18073 inputs: []inputInfo{ 18074 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18075 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18076 }, 18077 outputs: []outputInfo{ 18078 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18079 }, 18080 }, 18081 }, 18082 { 18083 name: "ADDW", 18084 argLen: 2, 18085 commutative: true, 18086 clobberFlags: true, 18087 asm: s390x.AADDW, 18088 reg: regInfo{ 18089 inputs: []inputInfo{ 18090 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18091 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18092 }, 18093 outputs: []outputInfo{ 18094 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18095 }, 18096 }, 18097 }, 18098 { 18099 name: "ADDconst", 18100 auxType: auxInt64, 18101 argLen: 1, 18102 clobberFlags: true, 18103 asm: s390x.AADD, 18104 reg: regInfo{ 18105 inputs: []inputInfo{ 18106 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18107 }, 18108 outputs: []outputInfo{ 18109 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18110 }, 18111 }, 18112 }, 18113 { 18114 name: "ADDWconst", 18115 auxType: auxInt32, 18116 argLen: 1, 18117 clobberFlags: true, 18118 asm: s390x.AADDW, 18119 reg: regInfo{ 18120 inputs: []inputInfo{ 18121 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18122 }, 18123 outputs: []outputInfo{ 18124 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18125 }, 18126 }, 18127 }, 18128 { 18129 name: "ADDload", 18130 auxType: auxSymOff, 18131 argLen: 3, 18132 resultInArg0: true, 18133 clobberFlags: true, 18134 faultOnNilArg1: true, 18135 symEffect: SymRead, 18136 asm: s390x.AADD, 18137 reg: regInfo{ 18138 inputs: []inputInfo{ 18139 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18140 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18141 }, 18142 outputs: []outputInfo{ 18143 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18144 }, 18145 }, 18146 }, 18147 { 18148 name: "ADDWload", 18149 auxType: auxSymOff, 18150 argLen: 3, 18151 resultInArg0: true, 18152 clobberFlags: true, 18153 faultOnNilArg1: true, 18154 symEffect: SymRead, 18155 asm: s390x.AADDW, 18156 reg: regInfo{ 18157 inputs: []inputInfo{ 18158 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18159 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18160 }, 18161 outputs: []outputInfo{ 18162 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18163 }, 18164 }, 18165 }, 18166 { 18167 name: "SUB", 18168 argLen: 2, 18169 clobberFlags: true, 18170 asm: s390x.ASUB, 18171 reg: regInfo{ 18172 inputs: []inputInfo{ 18173 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18174 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18175 }, 18176 outputs: []outputInfo{ 18177 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18178 }, 18179 }, 18180 }, 18181 { 18182 name: "SUBW", 18183 argLen: 2, 18184 clobberFlags: true, 18185 asm: s390x.ASUBW, 18186 reg: regInfo{ 18187 inputs: []inputInfo{ 18188 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18189 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18190 }, 18191 outputs: []outputInfo{ 18192 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18193 }, 18194 }, 18195 }, 18196 { 18197 name: "SUBconst", 18198 auxType: auxInt64, 18199 argLen: 1, 18200 resultInArg0: true, 18201 clobberFlags: true, 18202 asm: s390x.ASUB, 18203 reg: regInfo{ 18204 inputs: []inputInfo{ 18205 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18206 }, 18207 outputs: []outputInfo{ 18208 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18209 }, 18210 }, 18211 }, 18212 { 18213 name: "SUBWconst", 18214 auxType: auxInt32, 18215 argLen: 1, 18216 resultInArg0: true, 18217 clobberFlags: true, 18218 asm: s390x.ASUBW, 18219 reg: regInfo{ 18220 inputs: []inputInfo{ 18221 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18222 }, 18223 outputs: []outputInfo{ 18224 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18225 }, 18226 }, 18227 }, 18228 { 18229 name: "SUBload", 18230 auxType: auxSymOff, 18231 argLen: 3, 18232 resultInArg0: true, 18233 clobberFlags: true, 18234 faultOnNilArg1: true, 18235 symEffect: SymRead, 18236 asm: s390x.ASUB, 18237 reg: regInfo{ 18238 inputs: []inputInfo{ 18239 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18240 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18241 }, 18242 outputs: []outputInfo{ 18243 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18244 }, 18245 }, 18246 }, 18247 { 18248 name: "SUBWload", 18249 auxType: auxSymOff, 18250 argLen: 3, 18251 resultInArg0: true, 18252 clobberFlags: true, 18253 faultOnNilArg1: true, 18254 symEffect: SymRead, 18255 asm: s390x.ASUBW, 18256 reg: regInfo{ 18257 inputs: []inputInfo{ 18258 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18259 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18260 }, 18261 outputs: []outputInfo{ 18262 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18263 }, 18264 }, 18265 }, 18266 { 18267 name: "MULLD", 18268 argLen: 2, 18269 commutative: true, 18270 resultInArg0: true, 18271 clobberFlags: true, 18272 asm: s390x.AMULLD, 18273 reg: regInfo{ 18274 inputs: []inputInfo{ 18275 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18276 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18277 }, 18278 outputs: []outputInfo{ 18279 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18280 }, 18281 }, 18282 }, 18283 { 18284 name: "MULLW", 18285 argLen: 2, 18286 commutative: true, 18287 resultInArg0: true, 18288 clobberFlags: true, 18289 asm: s390x.AMULLW, 18290 reg: regInfo{ 18291 inputs: []inputInfo{ 18292 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18293 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18294 }, 18295 outputs: []outputInfo{ 18296 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18297 }, 18298 }, 18299 }, 18300 { 18301 name: "MULLDconst", 18302 auxType: auxInt64, 18303 argLen: 1, 18304 resultInArg0: true, 18305 clobberFlags: true, 18306 asm: s390x.AMULLD, 18307 reg: regInfo{ 18308 inputs: []inputInfo{ 18309 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18310 }, 18311 outputs: []outputInfo{ 18312 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18313 }, 18314 }, 18315 }, 18316 { 18317 name: "MULLWconst", 18318 auxType: auxInt32, 18319 argLen: 1, 18320 resultInArg0: true, 18321 clobberFlags: true, 18322 asm: s390x.AMULLW, 18323 reg: regInfo{ 18324 inputs: []inputInfo{ 18325 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18326 }, 18327 outputs: []outputInfo{ 18328 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18329 }, 18330 }, 18331 }, 18332 { 18333 name: "MULLDload", 18334 auxType: auxSymOff, 18335 argLen: 3, 18336 resultInArg0: true, 18337 clobberFlags: true, 18338 faultOnNilArg1: true, 18339 symEffect: SymRead, 18340 asm: s390x.AMULLD, 18341 reg: regInfo{ 18342 inputs: []inputInfo{ 18343 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18344 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18345 }, 18346 outputs: []outputInfo{ 18347 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18348 }, 18349 }, 18350 }, 18351 { 18352 name: "MULLWload", 18353 auxType: auxSymOff, 18354 argLen: 3, 18355 resultInArg0: true, 18356 clobberFlags: true, 18357 faultOnNilArg1: true, 18358 symEffect: SymRead, 18359 asm: s390x.AMULLW, 18360 reg: regInfo{ 18361 inputs: []inputInfo{ 18362 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18363 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18364 }, 18365 outputs: []outputInfo{ 18366 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18367 }, 18368 }, 18369 }, 18370 { 18371 name: "MULHD", 18372 argLen: 2, 18373 commutative: true, 18374 resultInArg0: true, 18375 clobberFlags: true, 18376 asm: s390x.AMULHD, 18377 reg: regInfo{ 18378 inputs: []inputInfo{ 18379 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18380 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18381 }, 18382 outputs: []outputInfo{ 18383 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18384 }, 18385 }, 18386 }, 18387 { 18388 name: "MULHDU", 18389 argLen: 2, 18390 commutative: true, 18391 resultInArg0: true, 18392 clobberFlags: true, 18393 asm: s390x.AMULHDU, 18394 reg: regInfo{ 18395 inputs: []inputInfo{ 18396 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18397 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18398 }, 18399 outputs: []outputInfo{ 18400 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18401 }, 18402 }, 18403 }, 18404 { 18405 name: "DIVD", 18406 argLen: 2, 18407 resultInArg0: true, 18408 clobberFlags: true, 18409 asm: s390x.ADIVD, 18410 reg: regInfo{ 18411 inputs: []inputInfo{ 18412 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18413 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18414 }, 18415 outputs: []outputInfo{ 18416 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18417 }, 18418 }, 18419 }, 18420 { 18421 name: "DIVW", 18422 argLen: 2, 18423 resultInArg0: true, 18424 clobberFlags: true, 18425 asm: s390x.ADIVW, 18426 reg: regInfo{ 18427 inputs: []inputInfo{ 18428 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18429 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18430 }, 18431 outputs: []outputInfo{ 18432 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18433 }, 18434 }, 18435 }, 18436 { 18437 name: "DIVDU", 18438 argLen: 2, 18439 resultInArg0: true, 18440 clobberFlags: true, 18441 asm: s390x.ADIVDU, 18442 reg: regInfo{ 18443 inputs: []inputInfo{ 18444 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18445 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18446 }, 18447 outputs: []outputInfo{ 18448 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18449 }, 18450 }, 18451 }, 18452 { 18453 name: "DIVWU", 18454 argLen: 2, 18455 resultInArg0: true, 18456 clobberFlags: true, 18457 asm: s390x.ADIVWU, 18458 reg: regInfo{ 18459 inputs: []inputInfo{ 18460 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18461 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18462 }, 18463 outputs: []outputInfo{ 18464 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18465 }, 18466 }, 18467 }, 18468 { 18469 name: "MODD", 18470 argLen: 2, 18471 resultInArg0: true, 18472 clobberFlags: true, 18473 asm: s390x.AMODD, 18474 reg: regInfo{ 18475 inputs: []inputInfo{ 18476 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18477 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18478 }, 18479 outputs: []outputInfo{ 18480 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18481 }, 18482 }, 18483 }, 18484 { 18485 name: "MODW", 18486 argLen: 2, 18487 resultInArg0: true, 18488 clobberFlags: true, 18489 asm: s390x.AMODW, 18490 reg: regInfo{ 18491 inputs: []inputInfo{ 18492 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18493 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18494 }, 18495 outputs: []outputInfo{ 18496 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18497 }, 18498 }, 18499 }, 18500 { 18501 name: "MODDU", 18502 argLen: 2, 18503 resultInArg0: true, 18504 clobberFlags: true, 18505 asm: s390x.AMODDU, 18506 reg: regInfo{ 18507 inputs: []inputInfo{ 18508 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18509 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18510 }, 18511 outputs: []outputInfo{ 18512 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18513 }, 18514 }, 18515 }, 18516 { 18517 name: "MODWU", 18518 argLen: 2, 18519 resultInArg0: true, 18520 clobberFlags: true, 18521 asm: s390x.AMODWU, 18522 reg: regInfo{ 18523 inputs: []inputInfo{ 18524 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18525 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18526 }, 18527 outputs: []outputInfo{ 18528 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18529 }, 18530 }, 18531 }, 18532 { 18533 name: "AND", 18534 argLen: 2, 18535 commutative: true, 18536 clobberFlags: true, 18537 asm: s390x.AAND, 18538 reg: regInfo{ 18539 inputs: []inputInfo{ 18540 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18541 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18542 }, 18543 outputs: []outputInfo{ 18544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18545 }, 18546 }, 18547 }, 18548 { 18549 name: "ANDW", 18550 argLen: 2, 18551 commutative: true, 18552 clobberFlags: true, 18553 asm: s390x.AANDW, 18554 reg: regInfo{ 18555 inputs: []inputInfo{ 18556 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18557 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18558 }, 18559 outputs: []outputInfo{ 18560 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18561 }, 18562 }, 18563 }, 18564 { 18565 name: "ANDconst", 18566 auxType: auxInt64, 18567 argLen: 1, 18568 resultInArg0: true, 18569 clobberFlags: true, 18570 asm: s390x.AAND, 18571 reg: regInfo{ 18572 inputs: []inputInfo{ 18573 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18574 }, 18575 outputs: []outputInfo{ 18576 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18577 }, 18578 }, 18579 }, 18580 { 18581 name: "ANDWconst", 18582 auxType: auxInt32, 18583 argLen: 1, 18584 resultInArg0: true, 18585 clobberFlags: true, 18586 asm: s390x.AANDW, 18587 reg: regInfo{ 18588 inputs: []inputInfo{ 18589 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18590 }, 18591 outputs: []outputInfo{ 18592 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18593 }, 18594 }, 18595 }, 18596 { 18597 name: "ANDload", 18598 auxType: auxSymOff, 18599 argLen: 3, 18600 resultInArg0: true, 18601 clobberFlags: true, 18602 faultOnNilArg1: true, 18603 symEffect: SymRead, 18604 asm: s390x.AAND, 18605 reg: regInfo{ 18606 inputs: []inputInfo{ 18607 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18608 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18609 }, 18610 outputs: []outputInfo{ 18611 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18612 }, 18613 }, 18614 }, 18615 { 18616 name: "ANDWload", 18617 auxType: auxSymOff, 18618 argLen: 3, 18619 resultInArg0: true, 18620 clobberFlags: true, 18621 faultOnNilArg1: true, 18622 symEffect: SymRead, 18623 asm: s390x.AANDW, 18624 reg: regInfo{ 18625 inputs: []inputInfo{ 18626 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18627 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18628 }, 18629 outputs: []outputInfo{ 18630 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18631 }, 18632 }, 18633 }, 18634 { 18635 name: "OR", 18636 argLen: 2, 18637 commutative: true, 18638 clobberFlags: true, 18639 asm: s390x.AOR, 18640 reg: regInfo{ 18641 inputs: []inputInfo{ 18642 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18643 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18644 }, 18645 outputs: []outputInfo{ 18646 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18647 }, 18648 }, 18649 }, 18650 { 18651 name: "ORW", 18652 argLen: 2, 18653 commutative: true, 18654 clobberFlags: true, 18655 asm: s390x.AORW, 18656 reg: regInfo{ 18657 inputs: []inputInfo{ 18658 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18659 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18660 }, 18661 outputs: []outputInfo{ 18662 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18663 }, 18664 }, 18665 }, 18666 { 18667 name: "ORconst", 18668 auxType: auxInt64, 18669 argLen: 1, 18670 resultInArg0: true, 18671 clobberFlags: true, 18672 asm: s390x.AOR, 18673 reg: regInfo{ 18674 inputs: []inputInfo{ 18675 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18676 }, 18677 outputs: []outputInfo{ 18678 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18679 }, 18680 }, 18681 }, 18682 { 18683 name: "ORWconst", 18684 auxType: auxInt32, 18685 argLen: 1, 18686 resultInArg0: true, 18687 clobberFlags: true, 18688 asm: s390x.AORW, 18689 reg: regInfo{ 18690 inputs: []inputInfo{ 18691 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18692 }, 18693 outputs: []outputInfo{ 18694 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18695 }, 18696 }, 18697 }, 18698 { 18699 name: "ORload", 18700 auxType: auxSymOff, 18701 argLen: 3, 18702 resultInArg0: true, 18703 clobberFlags: true, 18704 faultOnNilArg1: true, 18705 symEffect: SymRead, 18706 asm: s390x.AOR, 18707 reg: regInfo{ 18708 inputs: []inputInfo{ 18709 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18710 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18711 }, 18712 outputs: []outputInfo{ 18713 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18714 }, 18715 }, 18716 }, 18717 { 18718 name: "ORWload", 18719 auxType: auxSymOff, 18720 argLen: 3, 18721 resultInArg0: true, 18722 clobberFlags: true, 18723 faultOnNilArg1: true, 18724 symEffect: SymRead, 18725 asm: s390x.AORW, 18726 reg: regInfo{ 18727 inputs: []inputInfo{ 18728 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18729 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18730 }, 18731 outputs: []outputInfo{ 18732 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18733 }, 18734 }, 18735 }, 18736 { 18737 name: "XOR", 18738 argLen: 2, 18739 commutative: true, 18740 clobberFlags: true, 18741 asm: s390x.AXOR, 18742 reg: regInfo{ 18743 inputs: []inputInfo{ 18744 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18745 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18746 }, 18747 outputs: []outputInfo{ 18748 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18749 }, 18750 }, 18751 }, 18752 { 18753 name: "XORW", 18754 argLen: 2, 18755 commutative: true, 18756 clobberFlags: true, 18757 asm: s390x.AXORW, 18758 reg: regInfo{ 18759 inputs: []inputInfo{ 18760 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18761 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18762 }, 18763 outputs: []outputInfo{ 18764 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18765 }, 18766 }, 18767 }, 18768 { 18769 name: "XORconst", 18770 auxType: auxInt64, 18771 argLen: 1, 18772 resultInArg0: true, 18773 clobberFlags: true, 18774 asm: s390x.AXOR, 18775 reg: regInfo{ 18776 inputs: []inputInfo{ 18777 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18778 }, 18779 outputs: []outputInfo{ 18780 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18781 }, 18782 }, 18783 }, 18784 { 18785 name: "XORWconst", 18786 auxType: auxInt32, 18787 argLen: 1, 18788 resultInArg0: true, 18789 clobberFlags: true, 18790 asm: s390x.AXORW, 18791 reg: regInfo{ 18792 inputs: []inputInfo{ 18793 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18794 }, 18795 outputs: []outputInfo{ 18796 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18797 }, 18798 }, 18799 }, 18800 { 18801 name: "XORload", 18802 auxType: auxSymOff, 18803 argLen: 3, 18804 resultInArg0: true, 18805 clobberFlags: true, 18806 faultOnNilArg1: true, 18807 symEffect: SymRead, 18808 asm: s390x.AXOR, 18809 reg: regInfo{ 18810 inputs: []inputInfo{ 18811 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18812 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18813 }, 18814 outputs: []outputInfo{ 18815 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18816 }, 18817 }, 18818 }, 18819 { 18820 name: "XORWload", 18821 auxType: auxSymOff, 18822 argLen: 3, 18823 resultInArg0: true, 18824 clobberFlags: true, 18825 faultOnNilArg1: true, 18826 symEffect: SymRead, 18827 asm: s390x.AXORW, 18828 reg: regInfo{ 18829 inputs: []inputInfo{ 18830 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18831 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18832 }, 18833 outputs: []outputInfo{ 18834 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18835 }, 18836 }, 18837 }, 18838 { 18839 name: "CMP", 18840 argLen: 2, 18841 asm: s390x.ACMP, 18842 reg: regInfo{ 18843 inputs: []inputInfo{ 18844 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18845 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18846 }, 18847 }, 18848 }, 18849 { 18850 name: "CMPW", 18851 argLen: 2, 18852 asm: s390x.ACMPW, 18853 reg: regInfo{ 18854 inputs: []inputInfo{ 18855 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18856 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18857 }, 18858 }, 18859 }, 18860 { 18861 name: "CMPU", 18862 argLen: 2, 18863 asm: s390x.ACMPU, 18864 reg: regInfo{ 18865 inputs: []inputInfo{ 18866 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18867 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18868 }, 18869 }, 18870 }, 18871 { 18872 name: "CMPWU", 18873 argLen: 2, 18874 asm: s390x.ACMPWU, 18875 reg: regInfo{ 18876 inputs: []inputInfo{ 18877 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18878 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18879 }, 18880 }, 18881 }, 18882 { 18883 name: "CMPconst", 18884 auxType: auxInt64, 18885 argLen: 1, 18886 asm: s390x.ACMP, 18887 reg: regInfo{ 18888 inputs: []inputInfo{ 18889 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18890 }, 18891 }, 18892 }, 18893 { 18894 name: "CMPWconst", 18895 auxType: auxInt32, 18896 argLen: 1, 18897 asm: s390x.ACMPW, 18898 reg: regInfo{ 18899 inputs: []inputInfo{ 18900 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18901 }, 18902 }, 18903 }, 18904 { 18905 name: "CMPUconst", 18906 auxType: auxInt64, 18907 argLen: 1, 18908 asm: s390x.ACMPU, 18909 reg: regInfo{ 18910 inputs: []inputInfo{ 18911 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18912 }, 18913 }, 18914 }, 18915 { 18916 name: "CMPWUconst", 18917 auxType: auxInt32, 18918 argLen: 1, 18919 asm: s390x.ACMPWU, 18920 reg: regInfo{ 18921 inputs: []inputInfo{ 18922 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18923 }, 18924 }, 18925 }, 18926 { 18927 name: "FCMPS", 18928 argLen: 2, 18929 asm: s390x.ACEBR, 18930 reg: regInfo{ 18931 inputs: []inputInfo{ 18932 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18933 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18934 }, 18935 }, 18936 }, 18937 { 18938 name: "FCMP", 18939 argLen: 2, 18940 asm: s390x.AFCMPU, 18941 reg: regInfo{ 18942 inputs: []inputInfo{ 18943 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18944 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18945 }, 18946 }, 18947 }, 18948 { 18949 name: "SLD", 18950 argLen: 2, 18951 asm: s390x.ASLD, 18952 reg: regInfo{ 18953 inputs: []inputInfo{ 18954 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18955 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18956 }, 18957 outputs: []outputInfo{ 18958 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18959 }, 18960 }, 18961 }, 18962 { 18963 name: "SLW", 18964 argLen: 2, 18965 asm: s390x.ASLW, 18966 reg: regInfo{ 18967 inputs: []inputInfo{ 18968 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18969 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18970 }, 18971 outputs: []outputInfo{ 18972 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18973 }, 18974 }, 18975 }, 18976 { 18977 name: "SLDconst", 18978 auxType: auxInt8, 18979 argLen: 1, 18980 asm: s390x.ASLD, 18981 reg: regInfo{ 18982 inputs: []inputInfo{ 18983 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18984 }, 18985 outputs: []outputInfo{ 18986 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18987 }, 18988 }, 18989 }, 18990 { 18991 name: "SLWconst", 18992 auxType: auxInt8, 18993 argLen: 1, 18994 asm: s390x.ASLW, 18995 reg: regInfo{ 18996 inputs: []inputInfo{ 18997 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18998 }, 18999 outputs: []outputInfo{ 19000 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19001 }, 19002 }, 19003 }, 19004 { 19005 name: "SRD", 19006 argLen: 2, 19007 asm: s390x.ASRD, 19008 reg: regInfo{ 19009 inputs: []inputInfo{ 19010 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19011 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19012 }, 19013 outputs: []outputInfo{ 19014 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19015 }, 19016 }, 19017 }, 19018 { 19019 name: "SRW", 19020 argLen: 2, 19021 asm: s390x.ASRW, 19022 reg: regInfo{ 19023 inputs: []inputInfo{ 19024 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19025 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19026 }, 19027 outputs: []outputInfo{ 19028 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19029 }, 19030 }, 19031 }, 19032 { 19033 name: "SRDconst", 19034 auxType: auxInt8, 19035 argLen: 1, 19036 asm: s390x.ASRD, 19037 reg: regInfo{ 19038 inputs: []inputInfo{ 19039 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19040 }, 19041 outputs: []outputInfo{ 19042 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19043 }, 19044 }, 19045 }, 19046 { 19047 name: "SRWconst", 19048 auxType: auxInt8, 19049 argLen: 1, 19050 asm: s390x.ASRW, 19051 reg: regInfo{ 19052 inputs: []inputInfo{ 19053 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19054 }, 19055 outputs: []outputInfo{ 19056 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19057 }, 19058 }, 19059 }, 19060 { 19061 name: "SRAD", 19062 argLen: 2, 19063 clobberFlags: true, 19064 asm: s390x.ASRAD, 19065 reg: regInfo{ 19066 inputs: []inputInfo{ 19067 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19068 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19069 }, 19070 outputs: []outputInfo{ 19071 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19072 }, 19073 }, 19074 }, 19075 { 19076 name: "SRAW", 19077 argLen: 2, 19078 clobberFlags: true, 19079 asm: s390x.ASRAW, 19080 reg: regInfo{ 19081 inputs: []inputInfo{ 19082 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19083 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19084 }, 19085 outputs: []outputInfo{ 19086 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19087 }, 19088 }, 19089 }, 19090 { 19091 name: "SRADconst", 19092 auxType: auxInt8, 19093 argLen: 1, 19094 clobberFlags: true, 19095 asm: s390x.ASRAD, 19096 reg: regInfo{ 19097 inputs: []inputInfo{ 19098 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19099 }, 19100 outputs: []outputInfo{ 19101 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19102 }, 19103 }, 19104 }, 19105 { 19106 name: "SRAWconst", 19107 auxType: auxInt8, 19108 argLen: 1, 19109 clobberFlags: true, 19110 asm: s390x.ASRAW, 19111 reg: regInfo{ 19112 inputs: []inputInfo{ 19113 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19114 }, 19115 outputs: []outputInfo{ 19116 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19117 }, 19118 }, 19119 }, 19120 { 19121 name: "RLLGconst", 19122 auxType: auxInt8, 19123 argLen: 1, 19124 asm: s390x.ARLLG, 19125 reg: regInfo{ 19126 inputs: []inputInfo{ 19127 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19128 }, 19129 outputs: []outputInfo{ 19130 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19131 }, 19132 }, 19133 }, 19134 { 19135 name: "RLLconst", 19136 auxType: auxInt8, 19137 argLen: 1, 19138 asm: s390x.ARLL, 19139 reg: regInfo{ 19140 inputs: []inputInfo{ 19141 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19142 }, 19143 outputs: []outputInfo{ 19144 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19145 }, 19146 }, 19147 }, 19148 { 19149 name: "NEG", 19150 argLen: 1, 19151 clobberFlags: true, 19152 asm: s390x.ANEG, 19153 reg: regInfo{ 19154 inputs: []inputInfo{ 19155 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19156 }, 19157 outputs: []outputInfo{ 19158 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19159 }, 19160 }, 19161 }, 19162 { 19163 name: "NEGW", 19164 argLen: 1, 19165 clobberFlags: true, 19166 asm: s390x.ANEGW, 19167 reg: regInfo{ 19168 inputs: []inputInfo{ 19169 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19170 }, 19171 outputs: []outputInfo{ 19172 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19173 }, 19174 }, 19175 }, 19176 { 19177 name: "NOT", 19178 argLen: 1, 19179 resultInArg0: true, 19180 clobberFlags: true, 19181 reg: regInfo{ 19182 inputs: []inputInfo{ 19183 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19184 }, 19185 outputs: []outputInfo{ 19186 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19187 }, 19188 }, 19189 }, 19190 { 19191 name: "NOTW", 19192 argLen: 1, 19193 resultInArg0: true, 19194 clobberFlags: true, 19195 reg: regInfo{ 19196 inputs: []inputInfo{ 19197 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19198 }, 19199 outputs: []outputInfo{ 19200 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19201 }, 19202 }, 19203 }, 19204 { 19205 name: "FSQRT", 19206 argLen: 1, 19207 asm: s390x.AFSQRT, 19208 reg: regInfo{ 19209 inputs: []inputInfo{ 19210 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19211 }, 19212 outputs: []outputInfo{ 19213 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19214 }, 19215 }, 19216 }, 19217 { 19218 name: "SUBEcarrymask", 19219 argLen: 1, 19220 asm: s390x.ASUBE, 19221 reg: regInfo{ 19222 outputs: []outputInfo{ 19223 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19224 }, 19225 }, 19226 }, 19227 { 19228 name: "SUBEWcarrymask", 19229 argLen: 1, 19230 asm: s390x.ASUBE, 19231 reg: regInfo{ 19232 outputs: []outputInfo{ 19233 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19234 }, 19235 }, 19236 }, 19237 { 19238 name: "MOVDEQ", 19239 argLen: 3, 19240 resultInArg0: true, 19241 asm: s390x.AMOVDEQ, 19242 reg: regInfo{ 19243 inputs: []inputInfo{ 19244 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19245 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19246 }, 19247 outputs: []outputInfo{ 19248 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19249 }, 19250 }, 19251 }, 19252 { 19253 name: "MOVDNE", 19254 argLen: 3, 19255 resultInArg0: true, 19256 asm: s390x.AMOVDNE, 19257 reg: regInfo{ 19258 inputs: []inputInfo{ 19259 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19260 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19261 }, 19262 outputs: []outputInfo{ 19263 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19264 }, 19265 }, 19266 }, 19267 { 19268 name: "MOVDLT", 19269 argLen: 3, 19270 resultInArg0: true, 19271 asm: s390x.AMOVDLT, 19272 reg: regInfo{ 19273 inputs: []inputInfo{ 19274 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19275 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19276 }, 19277 outputs: []outputInfo{ 19278 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19279 }, 19280 }, 19281 }, 19282 { 19283 name: "MOVDLE", 19284 argLen: 3, 19285 resultInArg0: true, 19286 asm: s390x.AMOVDLE, 19287 reg: regInfo{ 19288 inputs: []inputInfo{ 19289 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19290 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19291 }, 19292 outputs: []outputInfo{ 19293 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19294 }, 19295 }, 19296 }, 19297 { 19298 name: "MOVDGT", 19299 argLen: 3, 19300 resultInArg0: true, 19301 asm: s390x.AMOVDGT, 19302 reg: regInfo{ 19303 inputs: []inputInfo{ 19304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19305 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19306 }, 19307 outputs: []outputInfo{ 19308 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19309 }, 19310 }, 19311 }, 19312 { 19313 name: "MOVDGE", 19314 argLen: 3, 19315 resultInArg0: true, 19316 asm: s390x.AMOVDGE, 19317 reg: regInfo{ 19318 inputs: []inputInfo{ 19319 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19320 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19321 }, 19322 outputs: []outputInfo{ 19323 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19324 }, 19325 }, 19326 }, 19327 { 19328 name: "MOVDGTnoinv", 19329 argLen: 3, 19330 resultInArg0: true, 19331 asm: s390x.AMOVDGT, 19332 reg: regInfo{ 19333 inputs: []inputInfo{ 19334 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19335 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19336 }, 19337 outputs: []outputInfo{ 19338 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19339 }, 19340 }, 19341 }, 19342 { 19343 name: "MOVDGEnoinv", 19344 argLen: 3, 19345 resultInArg0: true, 19346 asm: s390x.AMOVDGE, 19347 reg: regInfo{ 19348 inputs: []inputInfo{ 19349 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19350 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19351 }, 19352 outputs: []outputInfo{ 19353 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19354 }, 19355 }, 19356 }, 19357 { 19358 name: "MOVBreg", 19359 argLen: 1, 19360 asm: s390x.AMOVB, 19361 reg: regInfo{ 19362 inputs: []inputInfo{ 19363 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19364 }, 19365 outputs: []outputInfo{ 19366 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19367 }, 19368 }, 19369 }, 19370 { 19371 name: "MOVBZreg", 19372 argLen: 1, 19373 asm: s390x.AMOVBZ, 19374 reg: regInfo{ 19375 inputs: []inputInfo{ 19376 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19377 }, 19378 outputs: []outputInfo{ 19379 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19380 }, 19381 }, 19382 }, 19383 { 19384 name: "MOVHreg", 19385 argLen: 1, 19386 asm: s390x.AMOVH, 19387 reg: regInfo{ 19388 inputs: []inputInfo{ 19389 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19390 }, 19391 outputs: []outputInfo{ 19392 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19393 }, 19394 }, 19395 }, 19396 { 19397 name: "MOVHZreg", 19398 argLen: 1, 19399 asm: s390x.AMOVHZ, 19400 reg: regInfo{ 19401 inputs: []inputInfo{ 19402 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19403 }, 19404 outputs: []outputInfo{ 19405 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19406 }, 19407 }, 19408 }, 19409 { 19410 name: "MOVWreg", 19411 argLen: 1, 19412 asm: s390x.AMOVW, 19413 reg: regInfo{ 19414 inputs: []inputInfo{ 19415 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19416 }, 19417 outputs: []outputInfo{ 19418 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19419 }, 19420 }, 19421 }, 19422 { 19423 name: "MOVWZreg", 19424 argLen: 1, 19425 asm: s390x.AMOVWZ, 19426 reg: regInfo{ 19427 inputs: []inputInfo{ 19428 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19429 }, 19430 outputs: []outputInfo{ 19431 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19432 }, 19433 }, 19434 }, 19435 { 19436 name: "MOVDreg", 19437 argLen: 1, 19438 asm: s390x.AMOVD, 19439 reg: regInfo{ 19440 inputs: []inputInfo{ 19441 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19442 }, 19443 outputs: []outputInfo{ 19444 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19445 }, 19446 }, 19447 }, 19448 { 19449 name: "MOVDnop", 19450 argLen: 1, 19451 resultInArg0: true, 19452 reg: regInfo{ 19453 inputs: []inputInfo{ 19454 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19455 }, 19456 outputs: []outputInfo{ 19457 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19458 }, 19459 }, 19460 }, 19461 { 19462 name: "MOVDconst", 19463 auxType: auxInt64, 19464 argLen: 0, 19465 rematerializeable: true, 19466 asm: s390x.AMOVD, 19467 reg: regInfo{ 19468 outputs: []outputInfo{ 19469 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19470 }, 19471 }, 19472 }, 19473 { 19474 name: "CFDBRA", 19475 argLen: 1, 19476 asm: s390x.ACFDBRA, 19477 reg: regInfo{ 19478 inputs: []inputInfo{ 19479 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19480 }, 19481 outputs: []outputInfo{ 19482 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19483 }, 19484 }, 19485 }, 19486 { 19487 name: "CGDBRA", 19488 argLen: 1, 19489 asm: s390x.ACGDBRA, 19490 reg: regInfo{ 19491 inputs: []inputInfo{ 19492 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19493 }, 19494 outputs: []outputInfo{ 19495 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19496 }, 19497 }, 19498 }, 19499 { 19500 name: "CFEBRA", 19501 argLen: 1, 19502 asm: s390x.ACFEBRA, 19503 reg: regInfo{ 19504 inputs: []inputInfo{ 19505 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19506 }, 19507 outputs: []outputInfo{ 19508 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19509 }, 19510 }, 19511 }, 19512 { 19513 name: "CGEBRA", 19514 argLen: 1, 19515 asm: s390x.ACGEBRA, 19516 reg: regInfo{ 19517 inputs: []inputInfo{ 19518 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19519 }, 19520 outputs: []outputInfo{ 19521 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19522 }, 19523 }, 19524 }, 19525 { 19526 name: "CEFBRA", 19527 argLen: 1, 19528 asm: s390x.ACEFBRA, 19529 reg: regInfo{ 19530 inputs: []inputInfo{ 19531 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19532 }, 19533 outputs: []outputInfo{ 19534 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19535 }, 19536 }, 19537 }, 19538 { 19539 name: "CDFBRA", 19540 argLen: 1, 19541 asm: s390x.ACDFBRA, 19542 reg: regInfo{ 19543 inputs: []inputInfo{ 19544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19545 }, 19546 outputs: []outputInfo{ 19547 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19548 }, 19549 }, 19550 }, 19551 { 19552 name: "CEGBRA", 19553 argLen: 1, 19554 asm: s390x.ACEGBRA, 19555 reg: regInfo{ 19556 inputs: []inputInfo{ 19557 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19558 }, 19559 outputs: []outputInfo{ 19560 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19561 }, 19562 }, 19563 }, 19564 { 19565 name: "CDGBRA", 19566 argLen: 1, 19567 asm: s390x.ACDGBRA, 19568 reg: regInfo{ 19569 inputs: []inputInfo{ 19570 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19571 }, 19572 outputs: []outputInfo{ 19573 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19574 }, 19575 }, 19576 }, 19577 { 19578 name: "LEDBR", 19579 argLen: 1, 19580 asm: s390x.ALEDBR, 19581 reg: regInfo{ 19582 inputs: []inputInfo{ 19583 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19584 }, 19585 outputs: []outputInfo{ 19586 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19587 }, 19588 }, 19589 }, 19590 { 19591 name: "LDEBR", 19592 argLen: 1, 19593 asm: s390x.ALDEBR, 19594 reg: regInfo{ 19595 inputs: []inputInfo{ 19596 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19597 }, 19598 outputs: []outputInfo{ 19599 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19600 }, 19601 }, 19602 }, 19603 { 19604 name: "MOVDaddr", 19605 auxType: auxSymOff, 19606 argLen: 1, 19607 rematerializeable: true, 19608 clobberFlags: true, 19609 symEffect: SymRead, 19610 reg: regInfo{ 19611 inputs: []inputInfo{ 19612 {0, 4295000064}, // SP SB 19613 }, 19614 outputs: []outputInfo{ 19615 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19616 }, 19617 }, 19618 }, 19619 { 19620 name: "MOVDaddridx", 19621 auxType: auxSymOff, 19622 argLen: 2, 19623 clobberFlags: true, 19624 symEffect: SymRead, 19625 reg: regInfo{ 19626 inputs: []inputInfo{ 19627 {0, 4295000064}, // SP SB 19628 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19629 }, 19630 outputs: []outputInfo{ 19631 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19632 }, 19633 }, 19634 }, 19635 { 19636 name: "MOVBZload", 19637 auxType: auxSymOff, 19638 argLen: 2, 19639 clobberFlags: true, 19640 faultOnNilArg0: true, 19641 symEffect: SymRead, 19642 asm: s390x.AMOVBZ, 19643 reg: regInfo{ 19644 inputs: []inputInfo{ 19645 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19646 }, 19647 outputs: []outputInfo{ 19648 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19649 }, 19650 }, 19651 }, 19652 { 19653 name: "MOVBload", 19654 auxType: auxSymOff, 19655 argLen: 2, 19656 clobberFlags: true, 19657 faultOnNilArg0: true, 19658 symEffect: SymRead, 19659 asm: s390x.AMOVB, 19660 reg: regInfo{ 19661 inputs: []inputInfo{ 19662 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19663 }, 19664 outputs: []outputInfo{ 19665 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19666 }, 19667 }, 19668 }, 19669 { 19670 name: "MOVHZload", 19671 auxType: auxSymOff, 19672 argLen: 2, 19673 clobberFlags: true, 19674 faultOnNilArg0: true, 19675 symEffect: SymRead, 19676 asm: s390x.AMOVHZ, 19677 reg: regInfo{ 19678 inputs: []inputInfo{ 19679 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19680 }, 19681 outputs: []outputInfo{ 19682 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19683 }, 19684 }, 19685 }, 19686 { 19687 name: "MOVHload", 19688 auxType: auxSymOff, 19689 argLen: 2, 19690 clobberFlags: true, 19691 faultOnNilArg0: true, 19692 symEffect: SymRead, 19693 asm: s390x.AMOVH, 19694 reg: regInfo{ 19695 inputs: []inputInfo{ 19696 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19697 }, 19698 outputs: []outputInfo{ 19699 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19700 }, 19701 }, 19702 }, 19703 { 19704 name: "MOVWZload", 19705 auxType: auxSymOff, 19706 argLen: 2, 19707 clobberFlags: true, 19708 faultOnNilArg0: true, 19709 symEffect: SymRead, 19710 asm: s390x.AMOVWZ, 19711 reg: regInfo{ 19712 inputs: []inputInfo{ 19713 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19714 }, 19715 outputs: []outputInfo{ 19716 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19717 }, 19718 }, 19719 }, 19720 { 19721 name: "MOVWload", 19722 auxType: auxSymOff, 19723 argLen: 2, 19724 clobberFlags: true, 19725 faultOnNilArg0: true, 19726 symEffect: SymRead, 19727 asm: s390x.AMOVW, 19728 reg: regInfo{ 19729 inputs: []inputInfo{ 19730 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19731 }, 19732 outputs: []outputInfo{ 19733 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19734 }, 19735 }, 19736 }, 19737 { 19738 name: "MOVDload", 19739 auxType: auxSymOff, 19740 argLen: 2, 19741 clobberFlags: true, 19742 faultOnNilArg0: true, 19743 symEffect: SymRead, 19744 asm: s390x.AMOVD, 19745 reg: regInfo{ 19746 inputs: []inputInfo{ 19747 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19748 }, 19749 outputs: []outputInfo{ 19750 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19751 }, 19752 }, 19753 }, 19754 { 19755 name: "MOVWBR", 19756 argLen: 1, 19757 asm: s390x.AMOVWBR, 19758 reg: regInfo{ 19759 inputs: []inputInfo{ 19760 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19761 }, 19762 outputs: []outputInfo{ 19763 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19764 }, 19765 }, 19766 }, 19767 { 19768 name: "MOVDBR", 19769 argLen: 1, 19770 asm: s390x.AMOVDBR, 19771 reg: regInfo{ 19772 inputs: []inputInfo{ 19773 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19774 }, 19775 outputs: []outputInfo{ 19776 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19777 }, 19778 }, 19779 }, 19780 { 19781 name: "MOVHBRload", 19782 auxType: auxSymOff, 19783 argLen: 2, 19784 clobberFlags: true, 19785 faultOnNilArg0: true, 19786 symEffect: SymRead, 19787 asm: s390x.AMOVHBR, 19788 reg: regInfo{ 19789 inputs: []inputInfo{ 19790 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19791 }, 19792 outputs: []outputInfo{ 19793 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19794 }, 19795 }, 19796 }, 19797 { 19798 name: "MOVWBRload", 19799 auxType: auxSymOff, 19800 argLen: 2, 19801 clobberFlags: true, 19802 faultOnNilArg0: true, 19803 symEffect: SymRead, 19804 asm: s390x.AMOVWBR, 19805 reg: regInfo{ 19806 inputs: []inputInfo{ 19807 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19808 }, 19809 outputs: []outputInfo{ 19810 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19811 }, 19812 }, 19813 }, 19814 { 19815 name: "MOVDBRload", 19816 auxType: auxSymOff, 19817 argLen: 2, 19818 clobberFlags: true, 19819 faultOnNilArg0: true, 19820 symEffect: SymRead, 19821 asm: s390x.AMOVDBR, 19822 reg: regInfo{ 19823 inputs: []inputInfo{ 19824 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19825 }, 19826 outputs: []outputInfo{ 19827 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19828 }, 19829 }, 19830 }, 19831 { 19832 name: "MOVBstore", 19833 auxType: auxSymOff, 19834 argLen: 3, 19835 clobberFlags: true, 19836 faultOnNilArg0: true, 19837 symEffect: SymWrite, 19838 asm: s390x.AMOVB, 19839 reg: regInfo{ 19840 inputs: []inputInfo{ 19841 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19842 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19843 }, 19844 }, 19845 }, 19846 { 19847 name: "MOVHstore", 19848 auxType: auxSymOff, 19849 argLen: 3, 19850 clobberFlags: true, 19851 faultOnNilArg0: true, 19852 symEffect: SymWrite, 19853 asm: s390x.AMOVH, 19854 reg: regInfo{ 19855 inputs: []inputInfo{ 19856 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19857 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19858 }, 19859 }, 19860 }, 19861 { 19862 name: "MOVWstore", 19863 auxType: auxSymOff, 19864 argLen: 3, 19865 clobberFlags: true, 19866 faultOnNilArg0: true, 19867 symEffect: SymWrite, 19868 asm: s390x.AMOVW, 19869 reg: regInfo{ 19870 inputs: []inputInfo{ 19871 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19872 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19873 }, 19874 }, 19875 }, 19876 { 19877 name: "MOVDstore", 19878 auxType: auxSymOff, 19879 argLen: 3, 19880 clobberFlags: true, 19881 faultOnNilArg0: true, 19882 symEffect: SymWrite, 19883 asm: s390x.AMOVD, 19884 reg: regInfo{ 19885 inputs: []inputInfo{ 19886 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19887 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19888 }, 19889 }, 19890 }, 19891 { 19892 name: "MOVHBRstore", 19893 auxType: auxSymOff, 19894 argLen: 3, 19895 clobberFlags: true, 19896 faultOnNilArg0: true, 19897 symEffect: SymWrite, 19898 asm: s390x.AMOVHBR, 19899 reg: regInfo{ 19900 inputs: []inputInfo{ 19901 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19902 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19903 }, 19904 }, 19905 }, 19906 { 19907 name: "MOVWBRstore", 19908 auxType: auxSymOff, 19909 argLen: 3, 19910 clobberFlags: true, 19911 faultOnNilArg0: true, 19912 symEffect: SymWrite, 19913 asm: s390x.AMOVWBR, 19914 reg: regInfo{ 19915 inputs: []inputInfo{ 19916 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19917 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19918 }, 19919 }, 19920 }, 19921 { 19922 name: "MOVDBRstore", 19923 auxType: auxSymOff, 19924 argLen: 3, 19925 clobberFlags: true, 19926 faultOnNilArg0: true, 19927 symEffect: SymWrite, 19928 asm: s390x.AMOVDBR, 19929 reg: regInfo{ 19930 inputs: []inputInfo{ 19931 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19932 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19933 }, 19934 }, 19935 }, 19936 { 19937 name: "MVC", 19938 auxType: auxSymValAndOff, 19939 argLen: 3, 19940 clobberFlags: true, 19941 faultOnNilArg0: true, 19942 faultOnNilArg1: true, 19943 symEffect: SymNone, 19944 asm: s390x.AMVC, 19945 reg: regInfo{ 19946 inputs: []inputInfo{ 19947 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19948 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19949 }, 19950 }, 19951 }, 19952 { 19953 name: "MOVBZloadidx", 19954 auxType: auxSymOff, 19955 argLen: 3, 19956 commutative: true, 19957 clobberFlags: true, 19958 symEffect: SymRead, 19959 asm: s390x.AMOVBZ, 19960 reg: regInfo{ 19961 inputs: []inputInfo{ 19962 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19963 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19964 }, 19965 outputs: []outputInfo{ 19966 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19967 }, 19968 }, 19969 }, 19970 { 19971 name: "MOVHZloadidx", 19972 auxType: auxSymOff, 19973 argLen: 3, 19974 commutative: true, 19975 clobberFlags: true, 19976 symEffect: SymRead, 19977 asm: s390x.AMOVHZ, 19978 reg: regInfo{ 19979 inputs: []inputInfo{ 19980 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19981 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19982 }, 19983 outputs: []outputInfo{ 19984 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19985 }, 19986 }, 19987 }, 19988 { 19989 name: "MOVWZloadidx", 19990 auxType: auxSymOff, 19991 argLen: 3, 19992 commutative: true, 19993 clobberFlags: true, 19994 symEffect: SymRead, 19995 asm: s390x.AMOVWZ, 19996 reg: regInfo{ 19997 inputs: []inputInfo{ 19998 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19999 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20000 }, 20001 outputs: []outputInfo{ 20002 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20003 }, 20004 }, 20005 }, 20006 { 20007 name: "MOVDloadidx", 20008 auxType: auxSymOff, 20009 argLen: 3, 20010 commutative: true, 20011 clobberFlags: true, 20012 symEffect: SymRead, 20013 asm: s390x.AMOVD, 20014 reg: regInfo{ 20015 inputs: []inputInfo{ 20016 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20017 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20018 }, 20019 outputs: []outputInfo{ 20020 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20021 }, 20022 }, 20023 }, 20024 { 20025 name: "MOVHBRloadidx", 20026 auxType: auxSymOff, 20027 argLen: 3, 20028 commutative: true, 20029 clobberFlags: true, 20030 symEffect: SymRead, 20031 asm: s390x.AMOVHBR, 20032 reg: regInfo{ 20033 inputs: []inputInfo{ 20034 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20035 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20036 }, 20037 outputs: []outputInfo{ 20038 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20039 }, 20040 }, 20041 }, 20042 { 20043 name: "MOVWBRloadidx", 20044 auxType: auxSymOff, 20045 argLen: 3, 20046 commutative: true, 20047 clobberFlags: true, 20048 symEffect: SymRead, 20049 asm: s390x.AMOVWBR, 20050 reg: regInfo{ 20051 inputs: []inputInfo{ 20052 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20053 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20054 }, 20055 outputs: []outputInfo{ 20056 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20057 }, 20058 }, 20059 }, 20060 { 20061 name: "MOVDBRloadidx", 20062 auxType: auxSymOff, 20063 argLen: 3, 20064 commutative: true, 20065 clobberFlags: true, 20066 symEffect: SymRead, 20067 asm: s390x.AMOVDBR, 20068 reg: regInfo{ 20069 inputs: []inputInfo{ 20070 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20071 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20072 }, 20073 outputs: []outputInfo{ 20074 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20075 }, 20076 }, 20077 }, 20078 { 20079 name: "MOVBstoreidx", 20080 auxType: auxSymOff, 20081 argLen: 4, 20082 commutative: true, 20083 clobberFlags: true, 20084 symEffect: SymWrite, 20085 asm: s390x.AMOVB, 20086 reg: regInfo{ 20087 inputs: []inputInfo{ 20088 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20089 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20090 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20091 }, 20092 }, 20093 }, 20094 { 20095 name: "MOVHstoreidx", 20096 auxType: auxSymOff, 20097 argLen: 4, 20098 commutative: true, 20099 clobberFlags: true, 20100 symEffect: SymWrite, 20101 asm: s390x.AMOVH, 20102 reg: regInfo{ 20103 inputs: []inputInfo{ 20104 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20105 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20106 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20107 }, 20108 }, 20109 }, 20110 { 20111 name: "MOVWstoreidx", 20112 auxType: auxSymOff, 20113 argLen: 4, 20114 commutative: true, 20115 clobberFlags: true, 20116 symEffect: SymWrite, 20117 asm: s390x.AMOVW, 20118 reg: regInfo{ 20119 inputs: []inputInfo{ 20120 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20121 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20122 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20123 }, 20124 }, 20125 }, 20126 { 20127 name: "MOVDstoreidx", 20128 auxType: auxSymOff, 20129 argLen: 4, 20130 commutative: true, 20131 clobberFlags: true, 20132 symEffect: SymWrite, 20133 asm: s390x.AMOVD, 20134 reg: regInfo{ 20135 inputs: []inputInfo{ 20136 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20137 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20138 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20139 }, 20140 }, 20141 }, 20142 { 20143 name: "MOVHBRstoreidx", 20144 auxType: auxSymOff, 20145 argLen: 4, 20146 commutative: true, 20147 clobberFlags: true, 20148 symEffect: SymWrite, 20149 asm: s390x.AMOVHBR, 20150 reg: regInfo{ 20151 inputs: []inputInfo{ 20152 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20153 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20154 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20155 }, 20156 }, 20157 }, 20158 { 20159 name: "MOVWBRstoreidx", 20160 auxType: auxSymOff, 20161 argLen: 4, 20162 commutative: true, 20163 clobberFlags: true, 20164 symEffect: SymWrite, 20165 asm: s390x.AMOVWBR, 20166 reg: regInfo{ 20167 inputs: []inputInfo{ 20168 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20169 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20170 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20171 }, 20172 }, 20173 }, 20174 { 20175 name: "MOVDBRstoreidx", 20176 auxType: auxSymOff, 20177 argLen: 4, 20178 commutative: true, 20179 clobberFlags: true, 20180 symEffect: SymWrite, 20181 asm: s390x.AMOVDBR, 20182 reg: regInfo{ 20183 inputs: []inputInfo{ 20184 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20185 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20186 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20187 }, 20188 }, 20189 }, 20190 { 20191 name: "MOVBstoreconst", 20192 auxType: auxSymValAndOff, 20193 argLen: 2, 20194 clobberFlags: true, 20195 faultOnNilArg0: true, 20196 symEffect: SymWrite, 20197 asm: s390x.AMOVB, 20198 reg: regInfo{ 20199 inputs: []inputInfo{ 20200 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20201 }, 20202 }, 20203 }, 20204 { 20205 name: "MOVHstoreconst", 20206 auxType: auxSymValAndOff, 20207 argLen: 2, 20208 clobberFlags: true, 20209 faultOnNilArg0: true, 20210 symEffect: SymWrite, 20211 asm: s390x.AMOVH, 20212 reg: regInfo{ 20213 inputs: []inputInfo{ 20214 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20215 }, 20216 }, 20217 }, 20218 { 20219 name: "MOVWstoreconst", 20220 auxType: auxSymValAndOff, 20221 argLen: 2, 20222 clobberFlags: true, 20223 faultOnNilArg0: true, 20224 symEffect: SymWrite, 20225 asm: s390x.AMOVW, 20226 reg: regInfo{ 20227 inputs: []inputInfo{ 20228 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20229 }, 20230 }, 20231 }, 20232 { 20233 name: "MOVDstoreconst", 20234 auxType: auxSymValAndOff, 20235 argLen: 2, 20236 clobberFlags: true, 20237 faultOnNilArg0: true, 20238 symEffect: SymWrite, 20239 asm: s390x.AMOVD, 20240 reg: regInfo{ 20241 inputs: []inputInfo{ 20242 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20243 }, 20244 }, 20245 }, 20246 { 20247 name: "CLEAR", 20248 auxType: auxSymValAndOff, 20249 argLen: 2, 20250 clobberFlags: true, 20251 faultOnNilArg0: true, 20252 symEffect: SymWrite, 20253 asm: s390x.ACLEAR, 20254 reg: regInfo{ 20255 inputs: []inputInfo{ 20256 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20257 }, 20258 }, 20259 }, 20260 { 20261 name: "CALLstatic", 20262 auxType: auxSymOff, 20263 argLen: 1, 20264 clobberFlags: true, 20265 call: true, 20266 symEffect: SymNone, 20267 reg: regInfo{ 20268 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20269 }, 20270 }, 20271 { 20272 name: "CALLclosure", 20273 auxType: auxInt64, 20274 argLen: 3, 20275 clobberFlags: true, 20276 call: true, 20277 reg: regInfo{ 20278 inputs: []inputInfo{ 20279 {1, 4096}, // R12 20280 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20281 }, 20282 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20283 }, 20284 }, 20285 { 20286 name: "CALLinter", 20287 auxType: auxInt64, 20288 argLen: 2, 20289 clobberFlags: true, 20290 call: true, 20291 reg: regInfo{ 20292 inputs: []inputInfo{ 20293 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20294 }, 20295 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20296 }, 20297 }, 20298 { 20299 name: "InvertFlags", 20300 argLen: 1, 20301 reg: regInfo{}, 20302 }, 20303 { 20304 name: "LoweredGetG", 20305 argLen: 1, 20306 reg: regInfo{ 20307 outputs: []outputInfo{ 20308 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20309 }, 20310 }, 20311 }, 20312 { 20313 name: "LoweredGetClosurePtr", 20314 argLen: 0, 20315 reg: regInfo{ 20316 outputs: []outputInfo{ 20317 {0, 4096}, // R12 20318 }, 20319 }, 20320 }, 20321 { 20322 name: "LoweredNilCheck", 20323 argLen: 2, 20324 clobberFlags: true, 20325 nilCheck: true, 20326 faultOnNilArg0: true, 20327 reg: regInfo{ 20328 inputs: []inputInfo{ 20329 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20330 }, 20331 }, 20332 }, 20333 { 20334 name: "LoweredRound32F", 20335 argLen: 1, 20336 resultInArg0: true, 20337 reg: regInfo{ 20338 inputs: []inputInfo{ 20339 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20340 }, 20341 outputs: []outputInfo{ 20342 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20343 }, 20344 }, 20345 }, 20346 { 20347 name: "LoweredRound64F", 20348 argLen: 1, 20349 resultInArg0: true, 20350 reg: regInfo{ 20351 inputs: []inputInfo{ 20352 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20353 }, 20354 outputs: []outputInfo{ 20355 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20356 }, 20357 }, 20358 }, 20359 { 20360 name: "MOVDconvert", 20361 argLen: 2, 20362 asm: s390x.AMOVD, 20363 reg: regInfo{ 20364 inputs: []inputInfo{ 20365 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20366 }, 20367 outputs: []outputInfo{ 20368 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20369 }, 20370 }, 20371 }, 20372 { 20373 name: "FlagEQ", 20374 argLen: 0, 20375 reg: regInfo{}, 20376 }, 20377 { 20378 name: "FlagLT", 20379 argLen: 0, 20380 reg: regInfo{}, 20381 }, 20382 { 20383 name: "FlagGT", 20384 argLen: 0, 20385 reg: regInfo{}, 20386 }, 20387 { 20388 name: "MOVWZatomicload", 20389 auxType: auxSymOff, 20390 argLen: 2, 20391 faultOnNilArg0: true, 20392 symEffect: SymRead, 20393 asm: s390x.AMOVWZ, 20394 reg: regInfo{ 20395 inputs: []inputInfo{ 20396 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20397 }, 20398 outputs: []outputInfo{ 20399 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20400 }, 20401 }, 20402 }, 20403 { 20404 name: "MOVDatomicload", 20405 auxType: auxSymOff, 20406 argLen: 2, 20407 faultOnNilArg0: true, 20408 symEffect: SymRead, 20409 asm: s390x.AMOVD, 20410 reg: regInfo{ 20411 inputs: []inputInfo{ 20412 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20413 }, 20414 outputs: []outputInfo{ 20415 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20416 }, 20417 }, 20418 }, 20419 { 20420 name: "MOVWatomicstore", 20421 auxType: auxSymOff, 20422 argLen: 3, 20423 clobberFlags: true, 20424 faultOnNilArg0: true, 20425 hasSideEffects: true, 20426 symEffect: SymWrite, 20427 asm: s390x.AMOVW, 20428 reg: regInfo{ 20429 inputs: []inputInfo{ 20430 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20431 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20432 }, 20433 }, 20434 }, 20435 { 20436 name: "MOVDatomicstore", 20437 auxType: auxSymOff, 20438 argLen: 3, 20439 clobberFlags: true, 20440 faultOnNilArg0: true, 20441 hasSideEffects: true, 20442 symEffect: SymWrite, 20443 asm: s390x.AMOVD, 20444 reg: regInfo{ 20445 inputs: []inputInfo{ 20446 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20447 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20448 }, 20449 }, 20450 }, 20451 { 20452 name: "LAA", 20453 auxType: auxSymOff, 20454 argLen: 3, 20455 faultOnNilArg0: true, 20456 hasSideEffects: true, 20457 symEffect: SymRdWr, 20458 asm: s390x.ALAA, 20459 reg: regInfo{ 20460 inputs: []inputInfo{ 20461 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20462 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20463 }, 20464 outputs: []outputInfo{ 20465 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20466 }, 20467 }, 20468 }, 20469 { 20470 name: "LAAG", 20471 auxType: auxSymOff, 20472 argLen: 3, 20473 faultOnNilArg0: true, 20474 hasSideEffects: true, 20475 symEffect: SymRdWr, 20476 asm: s390x.ALAAG, 20477 reg: regInfo{ 20478 inputs: []inputInfo{ 20479 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20480 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20481 }, 20482 outputs: []outputInfo{ 20483 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20484 }, 20485 }, 20486 }, 20487 { 20488 name: "AddTupleFirst32", 20489 argLen: 2, 20490 reg: regInfo{}, 20491 }, 20492 { 20493 name: "AddTupleFirst64", 20494 argLen: 2, 20495 reg: regInfo{}, 20496 }, 20497 { 20498 name: "LoweredAtomicCas32", 20499 auxType: auxSymOff, 20500 argLen: 4, 20501 clobberFlags: true, 20502 faultOnNilArg0: true, 20503 hasSideEffects: true, 20504 symEffect: SymRdWr, 20505 asm: s390x.ACS, 20506 reg: regInfo{ 20507 inputs: []inputInfo{ 20508 {1, 1}, // R0 20509 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20510 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20511 }, 20512 clobbers: 1, // R0 20513 outputs: []outputInfo{ 20514 {1, 0}, 20515 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20516 }, 20517 }, 20518 }, 20519 { 20520 name: "LoweredAtomicCas64", 20521 auxType: auxSymOff, 20522 argLen: 4, 20523 clobberFlags: true, 20524 faultOnNilArg0: true, 20525 hasSideEffects: true, 20526 symEffect: SymRdWr, 20527 asm: s390x.ACSG, 20528 reg: regInfo{ 20529 inputs: []inputInfo{ 20530 {1, 1}, // R0 20531 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20532 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20533 }, 20534 clobbers: 1, // R0 20535 outputs: []outputInfo{ 20536 {1, 0}, 20537 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20538 }, 20539 }, 20540 }, 20541 { 20542 name: "LoweredAtomicExchange32", 20543 auxType: auxSymOff, 20544 argLen: 3, 20545 clobberFlags: true, 20546 faultOnNilArg0: true, 20547 hasSideEffects: true, 20548 symEffect: SymRdWr, 20549 asm: s390x.ACS, 20550 reg: regInfo{ 20551 inputs: []inputInfo{ 20552 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20553 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20554 }, 20555 outputs: []outputInfo{ 20556 {1, 0}, 20557 {0, 1}, // R0 20558 }, 20559 }, 20560 }, 20561 { 20562 name: "LoweredAtomicExchange64", 20563 auxType: auxSymOff, 20564 argLen: 3, 20565 clobberFlags: true, 20566 faultOnNilArg0: true, 20567 hasSideEffects: true, 20568 symEffect: SymRdWr, 20569 asm: s390x.ACSG, 20570 reg: regInfo{ 20571 inputs: []inputInfo{ 20572 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20573 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20574 }, 20575 outputs: []outputInfo{ 20576 {1, 0}, 20577 {0, 1}, // R0 20578 }, 20579 }, 20580 }, 20581 { 20582 name: "FLOGR", 20583 argLen: 1, 20584 clobberFlags: true, 20585 asm: s390x.AFLOGR, 20586 reg: regInfo{ 20587 inputs: []inputInfo{ 20588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20589 }, 20590 clobbers: 2, // R1 20591 outputs: []outputInfo{ 20592 {0, 1}, // R0 20593 }, 20594 }, 20595 }, 20596 { 20597 name: "STMG2", 20598 auxType: auxSymOff, 20599 argLen: 4, 20600 faultOnNilArg0: true, 20601 symEffect: SymWrite, 20602 asm: s390x.ASTMG, 20603 reg: regInfo{ 20604 inputs: []inputInfo{ 20605 {1, 2}, // R1 20606 {2, 4}, // R2 20607 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20608 }, 20609 }, 20610 }, 20611 { 20612 name: "STMG3", 20613 auxType: auxSymOff, 20614 argLen: 5, 20615 faultOnNilArg0: true, 20616 symEffect: SymWrite, 20617 asm: s390x.ASTMG, 20618 reg: regInfo{ 20619 inputs: []inputInfo{ 20620 {1, 2}, // R1 20621 {2, 4}, // R2 20622 {3, 8}, // R3 20623 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20624 }, 20625 }, 20626 }, 20627 { 20628 name: "STMG4", 20629 auxType: auxSymOff, 20630 argLen: 6, 20631 faultOnNilArg0: true, 20632 symEffect: SymWrite, 20633 asm: s390x.ASTMG, 20634 reg: regInfo{ 20635 inputs: []inputInfo{ 20636 {1, 2}, // R1 20637 {2, 4}, // R2 20638 {3, 8}, // R3 20639 {4, 16}, // R4 20640 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20641 }, 20642 }, 20643 }, 20644 { 20645 name: "STM2", 20646 auxType: auxSymOff, 20647 argLen: 4, 20648 faultOnNilArg0: true, 20649 symEffect: SymWrite, 20650 asm: s390x.ASTMY, 20651 reg: regInfo{ 20652 inputs: []inputInfo{ 20653 {1, 2}, // R1 20654 {2, 4}, // R2 20655 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20656 }, 20657 }, 20658 }, 20659 { 20660 name: "STM3", 20661 auxType: auxSymOff, 20662 argLen: 5, 20663 faultOnNilArg0: true, 20664 symEffect: SymWrite, 20665 asm: s390x.ASTMY, 20666 reg: regInfo{ 20667 inputs: []inputInfo{ 20668 {1, 2}, // R1 20669 {2, 4}, // R2 20670 {3, 8}, // R3 20671 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20672 }, 20673 }, 20674 }, 20675 { 20676 name: "STM4", 20677 auxType: auxSymOff, 20678 argLen: 6, 20679 faultOnNilArg0: true, 20680 symEffect: SymWrite, 20681 asm: s390x.ASTMY, 20682 reg: regInfo{ 20683 inputs: []inputInfo{ 20684 {1, 2}, // R1 20685 {2, 4}, // R2 20686 {3, 8}, // R3 20687 {4, 16}, // R4 20688 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20689 }, 20690 }, 20691 }, 20692 { 20693 name: "LoweredMove", 20694 auxType: auxInt64, 20695 argLen: 4, 20696 clobberFlags: true, 20697 faultOnNilArg0: true, 20698 faultOnNilArg1: true, 20699 reg: regInfo{ 20700 inputs: []inputInfo{ 20701 {0, 2}, // R1 20702 {1, 4}, // R2 20703 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20704 }, 20705 clobbers: 6, // R1 R2 20706 }, 20707 }, 20708 { 20709 name: "LoweredZero", 20710 auxType: auxInt64, 20711 argLen: 3, 20712 clobberFlags: true, 20713 faultOnNilArg0: true, 20714 reg: regInfo{ 20715 inputs: []inputInfo{ 20716 {0, 2}, // R1 20717 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20718 }, 20719 clobbers: 2, // R1 20720 }, 20721 }, 20722 20723 { 20724 name: "Add8", 20725 argLen: 2, 20726 commutative: true, 20727 generic: true, 20728 }, 20729 { 20730 name: "Add16", 20731 argLen: 2, 20732 commutative: true, 20733 generic: true, 20734 }, 20735 { 20736 name: "Add32", 20737 argLen: 2, 20738 commutative: true, 20739 generic: true, 20740 }, 20741 { 20742 name: "Add64", 20743 argLen: 2, 20744 commutative: true, 20745 generic: true, 20746 }, 20747 { 20748 name: "AddPtr", 20749 argLen: 2, 20750 generic: true, 20751 }, 20752 { 20753 name: "Add32F", 20754 argLen: 2, 20755 commutative: true, 20756 generic: true, 20757 }, 20758 { 20759 name: "Add64F", 20760 argLen: 2, 20761 commutative: true, 20762 generic: true, 20763 }, 20764 { 20765 name: "Sub8", 20766 argLen: 2, 20767 generic: true, 20768 }, 20769 { 20770 name: "Sub16", 20771 argLen: 2, 20772 generic: true, 20773 }, 20774 { 20775 name: "Sub32", 20776 argLen: 2, 20777 generic: true, 20778 }, 20779 { 20780 name: "Sub64", 20781 argLen: 2, 20782 generic: true, 20783 }, 20784 { 20785 name: "SubPtr", 20786 argLen: 2, 20787 generic: true, 20788 }, 20789 { 20790 name: "Sub32F", 20791 argLen: 2, 20792 generic: true, 20793 }, 20794 { 20795 name: "Sub64F", 20796 argLen: 2, 20797 generic: true, 20798 }, 20799 { 20800 name: "Mul8", 20801 argLen: 2, 20802 commutative: true, 20803 generic: true, 20804 }, 20805 { 20806 name: "Mul16", 20807 argLen: 2, 20808 commutative: true, 20809 generic: true, 20810 }, 20811 { 20812 name: "Mul32", 20813 argLen: 2, 20814 commutative: true, 20815 generic: true, 20816 }, 20817 { 20818 name: "Mul64", 20819 argLen: 2, 20820 commutative: true, 20821 generic: true, 20822 }, 20823 { 20824 name: "Mul32F", 20825 argLen: 2, 20826 commutative: true, 20827 generic: true, 20828 }, 20829 { 20830 name: "Mul64F", 20831 argLen: 2, 20832 commutative: true, 20833 generic: true, 20834 }, 20835 { 20836 name: "Div32F", 20837 argLen: 2, 20838 generic: true, 20839 }, 20840 { 20841 name: "Div64F", 20842 argLen: 2, 20843 generic: true, 20844 }, 20845 { 20846 name: "Hmul32", 20847 argLen: 2, 20848 commutative: true, 20849 generic: true, 20850 }, 20851 { 20852 name: "Hmul32u", 20853 argLen: 2, 20854 commutative: true, 20855 generic: true, 20856 }, 20857 { 20858 name: "Hmul64", 20859 argLen: 2, 20860 commutative: true, 20861 generic: true, 20862 }, 20863 { 20864 name: "Hmul64u", 20865 argLen: 2, 20866 commutative: true, 20867 generic: true, 20868 }, 20869 { 20870 name: "Mul32uhilo", 20871 argLen: 2, 20872 commutative: true, 20873 generic: true, 20874 }, 20875 { 20876 name: "Mul64uhilo", 20877 argLen: 2, 20878 commutative: true, 20879 generic: true, 20880 }, 20881 { 20882 name: "Avg32u", 20883 argLen: 2, 20884 generic: true, 20885 }, 20886 { 20887 name: "Avg64u", 20888 argLen: 2, 20889 generic: true, 20890 }, 20891 { 20892 name: "Div8", 20893 argLen: 2, 20894 generic: true, 20895 }, 20896 { 20897 name: "Div8u", 20898 argLen: 2, 20899 generic: true, 20900 }, 20901 { 20902 name: "Div16", 20903 argLen: 2, 20904 generic: true, 20905 }, 20906 { 20907 name: "Div16u", 20908 argLen: 2, 20909 generic: true, 20910 }, 20911 { 20912 name: "Div32", 20913 argLen: 2, 20914 generic: true, 20915 }, 20916 { 20917 name: "Div32u", 20918 argLen: 2, 20919 generic: true, 20920 }, 20921 { 20922 name: "Div64", 20923 argLen: 2, 20924 generic: true, 20925 }, 20926 { 20927 name: "Div64u", 20928 argLen: 2, 20929 generic: true, 20930 }, 20931 { 20932 name: "Div128u", 20933 argLen: 3, 20934 generic: true, 20935 }, 20936 { 20937 name: "Mod8", 20938 argLen: 2, 20939 generic: true, 20940 }, 20941 { 20942 name: "Mod8u", 20943 argLen: 2, 20944 generic: true, 20945 }, 20946 { 20947 name: "Mod16", 20948 argLen: 2, 20949 generic: true, 20950 }, 20951 { 20952 name: "Mod16u", 20953 argLen: 2, 20954 generic: true, 20955 }, 20956 { 20957 name: "Mod32", 20958 argLen: 2, 20959 generic: true, 20960 }, 20961 { 20962 name: "Mod32u", 20963 argLen: 2, 20964 generic: true, 20965 }, 20966 { 20967 name: "Mod64", 20968 argLen: 2, 20969 generic: true, 20970 }, 20971 { 20972 name: "Mod64u", 20973 argLen: 2, 20974 generic: true, 20975 }, 20976 { 20977 name: "And8", 20978 argLen: 2, 20979 commutative: true, 20980 generic: true, 20981 }, 20982 { 20983 name: "And16", 20984 argLen: 2, 20985 commutative: true, 20986 generic: true, 20987 }, 20988 { 20989 name: "And32", 20990 argLen: 2, 20991 commutative: true, 20992 generic: true, 20993 }, 20994 { 20995 name: "And64", 20996 argLen: 2, 20997 commutative: true, 20998 generic: true, 20999 }, 21000 { 21001 name: "Or8", 21002 argLen: 2, 21003 commutative: true, 21004 generic: true, 21005 }, 21006 { 21007 name: "Or16", 21008 argLen: 2, 21009 commutative: true, 21010 generic: true, 21011 }, 21012 { 21013 name: "Or32", 21014 argLen: 2, 21015 commutative: true, 21016 generic: true, 21017 }, 21018 { 21019 name: "Or64", 21020 argLen: 2, 21021 commutative: true, 21022 generic: true, 21023 }, 21024 { 21025 name: "Xor8", 21026 argLen: 2, 21027 commutative: true, 21028 generic: true, 21029 }, 21030 { 21031 name: "Xor16", 21032 argLen: 2, 21033 commutative: true, 21034 generic: true, 21035 }, 21036 { 21037 name: "Xor32", 21038 argLen: 2, 21039 commutative: true, 21040 generic: true, 21041 }, 21042 { 21043 name: "Xor64", 21044 argLen: 2, 21045 commutative: true, 21046 generic: true, 21047 }, 21048 { 21049 name: "Lsh8x8", 21050 argLen: 2, 21051 generic: true, 21052 }, 21053 { 21054 name: "Lsh8x16", 21055 argLen: 2, 21056 generic: true, 21057 }, 21058 { 21059 name: "Lsh8x32", 21060 argLen: 2, 21061 generic: true, 21062 }, 21063 { 21064 name: "Lsh8x64", 21065 argLen: 2, 21066 generic: true, 21067 }, 21068 { 21069 name: "Lsh16x8", 21070 argLen: 2, 21071 generic: true, 21072 }, 21073 { 21074 name: "Lsh16x16", 21075 argLen: 2, 21076 generic: true, 21077 }, 21078 { 21079 name: "Lsh16x32", 21080 argLen: 2, 21081 generic: true, 21082 }, 21083 { 21084 name: "Lsh16x64", 21085 argLen: 2, 21086 generic: true, 21087 }, 21088 { 21089 name: "Lsh32x8", 21090 argLen: 2, 21091 generic: true, 21092 }, 21093 { 21094 name: "Lsh32x16", 21095 argLen: 2, 21096 generic: true, 21097 }, 21098 { 21099 name: "Lsh32x32", 21100 argLen: 2, 21101 generic: true, 21102 }, 21103 { 21104 name: "Lsh32x64", 21105 argLen: 2, 21106 generic: true, 21107 }, 21108 { 21109 name: "Lsh64x8", 21110 argLen: 2, 21111 generic: true, 21112 }, 21113 { 21114 name: "Lsh64x16", 21115 argLen: 2, 21116 generic: true, 21117 }, 21118 { 21119 name: "Lsh64x32", 21120 argLen: 2, 21121 generic: true, 21122 }, 21123 { 21124 name: "Lsh64x64", 21125 argLen: 2, 21126 generic: true, 21127 }, 21128 { 21129 name: "Rsh8x8", 21130 argLen: 2, 21131 generic: true, 21132 }, 21133 { 21134 name: "Rsh8x16", 21135 argLen: 2, 21136 generic: true, 21137 }, 21138 { 21139 name: "Rsh8x32", 21140 argLen: 2, 21141 generic: true, 21142 }, 21143 { 21144 name: "Rsh8x64", 21145 argLen: 2, 21146 generic: true, 21147 }, 21148 { 21149 name: "Rsh16x8", 21150 argLen: 2, 21151 generic: true, 21152 }, 21153 { 21154 name: "Rsh16x16", 21155 argLen: 2, 21156 generic: true, 21157 }, 21158 { 21159 name: "Rsh16x32", 21160 argLen: 2, 21161 generic: true, 21162 }, 21163 { 21164 name: "Rsh16x64", 21165 argLen: 2, 21166 generic: true, 21167 }, 21168 { 21169 name: "Rsh32x8", 21170 argLen: 2, 21171 generic: true, 21172 }, 21173 { 21174 name: "Rsh32x16", 21175 argLen: 2, 21176 generic: true, 21177 }, 21178 { 21179 name: "Rsh32x32", 21180 argLen: 2, 21181 generic: true, 21182 }, 21183 { 21184 name: "Rsh32x64", 21185 argLen: 2, 21186 generic: true, 21187 }, 21188 { 21189 name: "Rsh64x8", 21190 argLen: 2, 21191 generic: true, 21192 }, 21193 { 21194 name: "Rsh64x16", 21195 argLen: 2, 21196 generic: true, 21197 }, 21198 { 21199 name: "Rsh64x32", 21200 argLen: 2, 21201 generic: true, 21202 }, 21203 { 21204 name: "Rsh64x64", 21205 argLen: 2, 21206 generic: true, 21207 }, 21208 { 21209 name: "Rsh8Ux8", 21210 argLen: 2, 21211 generic: true, 21212 }, 21213 { 21214 name: "Rsh8Ux16", 21215 argLen: 2, 21216 generic: true, 21217 }, 21218 { 21219 name: "Rsh8Ux32", 21220 argLen: 2, 21221 generic: true, 21222 }, 21223 { 21224 name: "Rsh8Ux64", 21225 argLen: 2, 21226 generic: true, 21227 }, 21228 { 21229 name: "Rsh16Ux8", 21230 argLen: 2, 21231 generic: true, 21232 }, 21233 { 21234 name: "Rsh16Ux16", 21235 argLen: 2, 21236 generic: true, 21237 }, 21238 { 21239 name: "Rsh16Ux32", 21240 argLen: 2, 21241 generic: true, 21242 }, 21243 { 21244 name: "Rsh16Ux64", 21245 argLen: 2, 21246 generic: true, 21247 }, 21248 { 21249 name: "Rsh32Ux8", 21250 argLen: 2, 21251 generic: true, 21252 }, 21253 { 21254 name: "Rsh32Ux16", 21255 argLen: 2, 21256 generic: true, 21257 }, 21258 { 21259 name: "Rsh32Ux32", 21260 argLen: 2, 21261 generic: true, 21262 }, 21263 { 21264 name: "Rsh32Ux64", 21265 argLen: 2, 21266 generic: true, 21267 }, 21268 { 21269 name: "Rsh64Ux8", 21270 argLen: 2, 21271 generic: true, 21272 }, 21273 { 21274 name: "Rsh64Ux16", 21275 argLen: 2, 21276 generic: true, 21277 }, 21278 { 21279 name: "Rsh64Ux32", 21280 argLen: 2, 21281 generic: true, 21282 }, 21283 { 21284 name: "Rsh64Ux64", 21285 argLen: 2, 21286 generic: true, 21287 }, 21288 { 21289 name: "Eq8", 21290 argLen: 2, 21291 commutative: true, 21292 generic: true, 21293 }, 21294 { 21295 name: "Eq16", 21296 argLen: 2, 21297 commutative: true, 21298 generic: true, 21299 }, 21300 { 21301 name: "Eq32", 21302 argLen: 2, 21303 commutative: true, 21304 generic: true, 21305 }, 21306 { 21307 name: "Eq64", 21308 argLen: 2, 21309 commutative: true, 21310 generic: true, 21311 }, 21312 { 21313 name: "EqPtr", 21314 argLen: 2, 21315 commutative: true, 21316 generic: true, 21317 }, 21318 { 21319 name: "EqInter", 21320 argLen: 2, 21321 generic: true, 21322 }, 21323 { 21324 name: "EqSlice", 21325 argLen: 2, 21326 generic: true, 21327 }, 21328 { 21329 name: "Eq32F", 21330 argLen: 2, 21331 commutative: true, 21332 generic: true, 21333 }, 21334 { 21335 name: "Eq64F", 21336 argLen: 2, 21337 commutative: true, 21338 generic: true, 21339 }, 21340 { 21341 name: "Neq8", 21342 argLen: 2, 21343 commutative: true, 21344 generic: true, 21345 }, 21346 { 21347 name: "Neq16", 21348 argLen: 2, 21349 commutative: true, 21350 generic: true, 21351 }, 21352 { 21353 name: "Neq32", 21354 argLen: 2, 21355 commutative: true, 21356 generic: true, 21357 }, 21358 { 21359 name: "Neq64", 21360 argLen: 2, 21361 commutative: true, 21362 generic: true, 21363 }, 21364 { 21365 name: "NeqPtr", 21366 argLen: 2, 21367 commutative: true, 21368 generic: true, 21369 }, 21370 { 21371 name: "NeqInter", 21372 argLen: 2, 21373 generic: true, 21374 }, 21375 { 21376 name: "NeqSlice", 21377 argLen: 2, 21378 generic: true, 21379 }, 21380 { 21381 name: "Neq32F", 21382 argLen: 2, 21383 commutative: true, 21384 generic: true, 21385 }, 21386 { 21387 name: "Neq64F", 21388 argLen: 2, 21389 commutative: true, 21390 generic: true, 21391 }, 21392 { 21393 name: "Less8", 21394 argLen: 2, 21395 generic: true, 21396 }, 21397 { 21398 name: "Less8U", 21399 argLen: 2, 21400 generic: true, 21401 }, 21402 { 21403 name: "Less16", 21404 argLen: 2, 21405 generic: true, 21406 }, 21407 { 21408 name: "Less16U", 21409 argLen: 2, 21410 generic: true, 21411 }, 21412 { 21413 name: "Less32", 21414 argLen: 2, 21415 generic: true, 21416 }, 21417 { 21418 name: "Less32U", 21419 argLen: 2, 21420 generic: true, 21421 }, 21422 { 21423 name: "Less64", 21424 argLen: 2, 21425 generic: true, 21426 }, 21427 { 21428 name: "Less64U", 21429 argLen: 2, 21430 generic: true, 21431 }, 21432 { 21433 name: "Less32F", 21434 argLen: 2, 21435 generic: true, 21436 }, 21437 { 21438 name: "Less64F", 21439 argLen: 2, 21440 generic: true, 21441 }, 21442 { 21443 name: "Leq8", 21444 argLen: 2, 21445 generic: true, 21446 }, 21447 { 21448 name: "Leq8U", 21449 argLen: 2, 21450 generic: true, 21451 }, 21452 { 21453 name: "Leq16", 21454 argLen: 2, 21455 generic: true, 21456 }, 21457 { 21458 name: "Leq16U", 21459 argLen: 2, 21460 generic: true, 21461 }, 21462 { 21463 name: "Leq32", 21464 argLen: 2, 21465 generic: true, 21466 }, 21467 { 21468 name: "Leq32U", 21469 argLen: 2, 21470 generic: true, 21471 }, 21472 { 21473 name: "Leq64", 21474 argLen: 2, 21475 generic: true, 21476 }, 21477 { 21478 name: "Leq64U", 21479 argLen: 2, 21480 generic: true, 21481 }, 21482 { 21483 name: "Leq32F", 21484 argLen: 2, 21485 generic: true, 21486 }, 21487 { 21488 name: "Leq64F", 21489 argLen: 2, 21490 generic: true, 21491 }, 21492 { 21493 name: "Greater8", 21494 argLen: 2, 21495 generic: true, 21496 }, 21497 { 21498 name: "Greater8U", 21499 argLen: 2, 21500 generic: true, 21501 }, 21502 { 21503 name: "Greater16", 21504 argLen: 2, 21505 generic: true, 21506 }, 21507 { 21508 name: "Greater16U", 21509 argLen: 2, 21510 generic: true, 21511 }, 21512 { 21513 name: "Greater32", 21514 argLen: 2, 21515 generic: true, 21516 }, 21517 { 21518 name: "Greater32U", 21519 argLen: 2, 21520 generic: true, 21521 }, 21522 { 21523 name: "Greater64", 21524 argLen: 2, 21525 generic: true, 21526 }, 21527 { 21528 name: "Greater64U", 21529 argLen: 2, 21530 generic: true, 21531 }, 21532 { 21533 name: "Greater32F", 21534 argLen: 2, 21535 generic: true, 21536 }, 21537 { 21538 name: "Greater64F", 21539 argLen: 2, 21540 generic: true, 21541 }, 21542 { 21543 name: "Geq8", 21544 argLen: 2, 21545 generic: true, 21546 }, 21547 { 21548 name: "Geq8U", 21549 argLen: 2, 21550 generic: true, 21551 }, 21552 { 21553 name: "Geq16", 21554 argLen: 2, 21555 generic: true, 21556 }, 21557 { 21558 name: "Geq16U", 21559 argLen: 2, 21560 generic: true, 21561 }, 21562 { 21563 name: "Geq32", 21564 argLen: 2, 21565 generic: true, 21566 }, 21567 { 21568 name: "Geq32U", 21569 argLen: 2, 21570 generic: true, 21571 }, 21572 { 21573 name: "Geq64", 21574 argLen: 2, 21575 generic: true, 21576 }, 21577 { 21578 name: "Geq64U", 21579 argLen: 2, 21580 generic: true, 21581 }, 21582 { 21583 name: "Geq32F", 21584 argLen: 2, 21585 generic: true, 21586 }, 21587 { 21588 name: "Geq64F", 21589 argLen: 2, 21590 generic: true, 21591 }, 21592 { 21593 name: "AndB", 21594 argLen: 2, 21595 generic: true, 21596 }, 21597 { 21598 name: "OrB", 21599 argLen: 2, 21600 generic: true, 21601 }, 21602 { 21603 name: "EqB", 21604 argLen: 2, 21605 generic: true, 21606 }, 21607 { 21608 name: "NeqB", 21609 argLen: 2, 21610 generic: true, 21611 }, 21612 { 21613 name: "Not", 21614 argLen: 1, 21615 generic: true, 21616 }, 21617 { 21618 name: "Neg8", 21619 argLen: 1, 21620 generic: true, 21621 }, 21622 { 21623 name: "Neg16", 21624 argLen: 1, 21625 generic: true, 21626 }, 21627 { 21628 name: "Neg32", 21629 argLen: 1, 21630 generic: true, 21631 }, 21632 { 21633 name: "Neg64", 21634 argLen: 1, 21635 generic: true, 21636 }, 21637 { 21638 name: "Neg32F", 21639 argLen: 1, 21640 generic: true, 21641 }, 21642 { 21643 name: "Neg64F", 21644 argLen: 1, 21645 generic: true, 21646 }, 21647 { 21648 name: "Com8", 21649 argLen: 1, 21650 generic: true, 21651 }, 21652 { 21653 name: "Com16", 21654 argLen: 1, 21655 generic: true, 21656 }, 21657 { 21658 name: "Com32", 21659 argLen: 1, 21660 generic: true, 21661 }, 21662 { 21663 name: "Com64", 21664 argLen: 1, 21665 generic: true, 21666 }, 21667 { 21668 name: "Ctz32", 21669 argLen: 1, 21670 generic: true, 21671 }, 21672 { 21673 name: "Ctz64", 21674 argLen: 1, 21675 generic: true, 21676 }, 21677 { 21678 name: "BitLen32", 21679 argLen: 1, 21680 generic: true, 21681 }, 21682 { 21683 name: "BitLen64", 21684 argLen: 1, 21685 generic: true, 21686 }, 21687 { 21688 name: "Bswap32", 21689 argLen: 1, 21690 generic: true, 21691 }, 21692 { 21693 name: "Bswap64", 21694 argLen: 1, 21695 generic: true, 21696 }, 21697 { 21698 name: "BitRev8", 21699 argLen: 1, 21700 generic: true, 21701 }, 21702 { 21703 name: "BitRev16", 21704 argLen: 1, 21705 generic: true, 21706 }, 21707 { 21708 name: "BitRev32", 21709 argLen: 1, 21710 generic: true, 21711 }, 21712 { 21713 name: "BitRev64", 21714 argLen: 1, 21715 generic: true, 21716 }, 21717 { 21718 name: "PopCount8", 21719 argLen: 1, 21720 generic: true, 21721 }, 21722 { 21723 name: "PopCount16", 21724 argLen: 1, 21725 generic: true, 21726 }, 21727 { 21728 name: "PopCount32", 21729 argLen: 1, 21730 generic: true, 21731 }, 21732 { 21733 name: "PopCount64", 21734 argLen: 1, 21735 generic: true, 21736 }, 21737 { 21738 name: "Sqrt", 21739 argLen: 1, 21740 generic: true, 21741 }, 21742 { 21743 name: "Phi", 21744 argLen: -1, 21745 generic: true, 21746 }, 21747 { 21748 name: "Copy", 21749 argLen: 1, 21750 generic: true, 21751 }, 21752 { 21753 name: "Convert", 21754 argLen: 2, 21755 generic: true, 21756 }, 21757 { 21758 name: "ConstBool", 21759 auxType: auxBool, 21760 argLen: 0, 21761 generic: true, 21762 }, 21763 { 21764 name: "ConstString", 21765 auxType: auxString, 21766 argLen: 0, 21767 generic: true, 21768 }, 21769 { 21770 name: "ConstNil", 21771 argLen: 0, 21772 generic: true, 21773 }, 21774 { 21775 name: "Const8", 21776 auxType: auxInt8, 21777 argLen: 0, 21778 generic: true, 21779 }, 21780 { 21781 name: "Const16", 21782 auxType: auxInt16, 21783 argLen: 0, 21784 generic: true, 21785 }, 21786 { 21787 name: "Const32", 21788 auxType: auxInt32, 21789 argLen: 0, 21790 generic: true, 21791 }, 21792 { 21793 name: "Const64", 21794 auxType: auxInt64, 21795 argLen: 0, 21796 generic: true, 21797 }, 21798 { 21799 name: "Const32F", 21800 auxType: auxFloat32, 21801 argLen: 0, 21802 generic: true, 21803 }, 21804 { 21805 name: "Const64F", 21806 auxType: auxFloat64, 21807 argLen: 0, 21808 generic: true, 21809 }, 21810 { 21811 name: "ConstInterface", 21812 argLen: 0, 21813 generic: true, 21814 }, 21815 { 21816 name: "ConstSlice", 21817 argLen: 0, 21818 generic: true, 21819 }, 21820 { 21821 name: "InitMem", 21822 argLen: 0, 21823 generic: true, 21824 }, 21825 { 21826 name: "Arg", 21827 auxType: auxSymOff, 21828 argLen: 0, 21829 symEffect: SymNone, 21830 generic: true, 21831 }, 21832 { 21833 name: "Addr", 21834 auxType: auxSym, 21835 argLen: 1, 21836 symEffect: SymAddr, 21837 generic: true, 21838 }, 21839 { 21840 name: "SP", 21841 argLen: 0, 21842 generic: true, 21843 }, 21844 { 21845 name: "SB", 21846 argLen: 0, 21847 generic: true, 21848 }, 21849 { 21850 name: "Load", 21851 argLen: 2, 21852 generic: true, 21853 }, 21854 { 21855 name: "Store", 21856 auxType: auxTyp, 21857 argLen: 3, 21858 generic: true, 21859 }, 21860 { 21861 name: "Move", 21862 auxType: auxTypSize, 21863 argLen: 3, 21864 generic: true, 21865 }, 21866 { 21867 name: "Zero", 21868 auxType: auxTypSize, 21869 argLen: 2, 21870 generic: true, 21871 }, 21872 { 21873 name: "StoreWB", 21874 auxType: auxTyp, 21875 argLen: 3, 21876 generic: true, 21877 }, 21878 { 21879 name: "MoveWB", 21880 auxType: auxTypSize, 21881 argLen: 3, 21882 generic: true, 21883 }, 21884 { 21885 name: "ZeroWB", 21886 auxType: auxTypSize, 21887 argLen: 2, 21888 generic: true, 21889 }, 21890 { 21891 name: "ClosureCall", 21892 auxType: auxInt64, 21893 argLen: 3, 21894 call: true, 21895 generic: true, 21896 }, 21897 { 21898 name: "StaticCall", 21899 auxType: auxSymOff, 21900 argLen: 1, 21901 call: true, 21902 symEffect: SymNone, 21903 generic: true, 21904 }, 21905 { 21906 name: "InterCall", 21907 auxType: auxInt64, 21908 argLen: 2, 21909 call: true, 21910 generic: true, 21911 }, 21912 { 21913 name: "SignExt8to16", 21914 argLen: 1, 21915 generic: true, 21916 }, 21917 { 21918 name: "SignExt8to32", 21919 argLen: 1, 21920 generic: true, 21921 }, 21922 { 21923 name: "SignExt8to64", 21924 argLen: 1, 21925 generic: true, 21926 }, 21927 { 21928 name: "SignExt16to32", 21929 argLen: 1, 21930 generic: true, 21931 }, 21932 { 21933 name: "SignExt16to64", 21934 argLen: 1, 21935 generic: true, 21936 }, 21937 { 21938 name: "SignExt32to64", 21939 argLen: 1, 21940 generic: true, 21941 }, 21942 { 21943 name: "ZeroExt8to16", 21944 argLen: 1, 21945 generic: true, 21946 }, 21947 { 21948 name: "ZeroExt8to32", 21949 argLen: 1, 21950 generic: true, 21951 }, 21952 { 21953 name: "ZeroExt8to64", 21954 argLen: 1, 21955 generic: true, 21956 }, 21957 { 21958 name: "ZeroExt16to32", 21959 argLen: 1, 21960 generic: true, 21961 }, 21962 { 21963 name: "ZeroExt16to64", 21964 argLen: 1, 21965 generic: true, 21966 }, 21967 { 21968 name: "ZeroExt32to64", 21969 argLen: 1, 21970 generic: true, 21971 }, 21972 { 21973 name: "Trunc16to8", 21974 argLen: 1, 21975 generic: true, 21976 }, 21977 { 21978 name: "Trunc32to8", 21979 argLen: 1, 21980 generic: true, 21981 }, 21982 { 21983 name: "Trunc32to16", 21984 argLen: 1, 21985 generic: true, 21986 }, 21987 { 21988 name: "Trunc64to8", 21989 argLen: 1, 21990 generic: true, 21991 }, 21992 { 21993 name: "Trunc64to16", 21994 argLen: 1, 21995 generic: true, 21996 }, 21997 { 21998 name: "Trunc64to32", 21999 argLen: 1, 22000 generic: true, 22001 }, 22002 { 22003 name: "Cvt32to32F", 22004 argLen: 1, 22005 generic: true, 22006 }, 22007 { 22008 name: "Cvt32to64F", 22009 argLen: 1, 22010 generic: true, 22011 }, 22012 { 22013 name: "Cvt64to32F", 22014 argLen: 1, 22015 generic: true, 22016 }, 22017 { 22018 name: "Cvt64to64F", 22019 argLen: 1, 22020 generic: true, 22021 }, 22022 { 22023 name: "Cvt32Fto32", 22024 argLen: 1, 22025 generic: true, 22026 }, 22027 { 22028 name: "Cvt32Fto64", 22029 argLen: 1, 22030 generic: true, 22031 }, 22032 { 22033 name: "Cvt64Fto32", 22034 argLen: 1, 22035 generic: true, 22036 }, 22037 { 22038 name: "Cvt64Fto64", 22039 argLen: 1, 22040 generic: true, 22041 }, 22042 { 22043 name: "Cvt32Fto64F", 22044 argLen: 1, 22045 generic: true, 22046 }, 22047 { 22048 name: "Cvt64Fto32F", 22049 argLen: 1, 22050 generic: true, 22051 }, 22052 { 22053 name: "Round32F", 22054 argLen: 1, 22055 generic: true, 22056 }, 22057 { 22058 name: "Round64F", 22059 argLen: 1, 22060 generic: true, 22061 }, 22062 { 22063 name: "IsNonNil", 22064 argLen: 1, 22065 generic: true, 22066 }, 22067 { 22068 name: "IsInBounds", 22069 argLen: 2, 22070 generic: true, 22071 }, 22072 { 22073 name: "IsSliceInBounds", 22074 argLen: 2, 22075 generic: true, 22076 }, 22077 { 22078 name: "NilCheck", 22079 argLen: 2, 22080 generic: true, 22081 }, 22082 { 22083 name: "GetG", 22084 argLen: 1, 22085 generic: true, 22086 }, 22087 { 22088 name: "GetClosurePtr", 22089 argLen: 0, 22090 generic: true, 22091 }, 22092 { 22093 name: "PtrIndex", 22094 argLen: 2, 22095 generic: true, 22096 }, 22097 { 22098 name: "OffPtr", 22099 auxType: auxInt64, 22100 argLen: 1, 22101 generic: true, 22102 }, 22103 { 22104 name: "SliceMake", 22105 argLen: 3, 22106 generic: true, 22107 }, 22108 { 22109 name: "SlicePtr", 22110 argLen: 1, 22111 generic: true, 22112 }, 22113 { 22114 name: "SliceLen", 22115 argLen: 1, 22116 generic: true, 22117 }, 22118 { 22119 name: "SliceCap", 22120 argLen: 1, 22121 generic: true, 22122 }, 22123 { 22124 name: "ComplexMake", 22125 argLen: 2, 22126 generic: true, 22127 }, 22128 { 22129 name: "ComplexReal", 22130 argLen: 1, 22131 generic: true, 22132 }, 22133 { 22134 name: "ComplexImag", 22135 argLen: 1, 22136 generic: true, 22137 }, 22138 { 22139 name: "StringMake", 22140 argLen: 2, 22141 generic: true, 22142 }, 22143 { 22144 name: "StringPtr", 22145 argLen: 1, 22146 generic: true, 22147 }, 22148 { 22149 name: "StringLen", 22150 argLen: 1, 22151 generic: true, 22152 }, 22153 { 22154 name: "IMake", 22155 argLen: 2, 22156 generic: true, 22157 }, 22158 { 22159 name: "ITab", 22160 argLen: 1, 22161 generic: true, 22162 }, 22163 { 22164 name: "IData", 22165 argLen: 1, 22166 generic: true, 22167 }, 22168 { 22169 name: "StructMake0", 22170 argLen: 0, 22171 generic: true, 22172 }, 22173 { 22174 name: "StructMake1", 22175 argLen: 1, 22176 generic: true, 22177 }, 22178 { 22179 name: "StructMake2", 22180 argLen: 2, 22181 generic: true, 22182 }, 22183 { 22184 name: "StructMake3", 22185 argLen: 3, 22186 generic: true, 22187 }, 22188 { 22189 name: "StructMake4", 22190 argLen: 4, 22191 generic: true, 22192 }, 22193 { 22194 name: "StructSelect", 22195 auxType: auxInt64, 22196 argLen: 1, 22197 generic: true, 22198 }, 22199 { 22200 name: "ArrayMake0", 22201 argLen: 0, 22202 generic: true, 22203 }, 22204 { 22205 name: "ArrayMake1", 22206 argLen: 1, 22207 generic: true, 22208 }, 22209 { 22210 name: "ArraySelect", 22211 auxType: auxInt64, 22212 argLen: 1, 22213 generic: true, 22214 }, 22215 { 22216 name: "StoreReg", 22217 argLen: 1, 22218 generic: true, 22219 }, 22220 { 22221 name: "LoadReg", 22222 argLen: 1, 22223 generic: true, 22224 }, 22225 { 22226 name: "FwdRef", 22227 auxType: auxSym, 22228 argLen: 0, 22229 symEffect: SymNone, 22230 generic: true, 22231 }, 22232 { 22233 name: "Unknown", 22234 argLen: 0, 22235 generic: true, 22236 }, 22237 { 22238 name: "VarDef", 22239 auxType: auxSym, 22240 argLen: 1, 22241 symEffect: SymNone, 22242 generic: true, 22243 }, 22244 { 22245 name: "VarKill", 22246 auxType: auxSym, 22247 argLen: 1, 22248 symEffect: SymNone, 22249 generic: true, 22250 }, 22251 { 22252 name: "VarLive", 22253 auxType: auxSym, 22254 argLen: 1, 22255 symEffect: SymNone, 22256 generic: true, 22257 }, 22258 { 22259 name: "KeepAlive", 22260 argLen: 2, 22261 generic: true, 22262 }, 22263 { 22264 name: "Int64Make", 22265 argLen: 2, 22266 generic: true, 22267 }, 22268 { 22269 name: "Int64Hi", 22270 argLen: 1, 22271 generic: true, 22272 }, 22273 { 22274 name: "Int64Lo", 22275 argLen: 1, 22276 generic: true, 22277 }, 22278 { 22279 name: "Add32carry", 22280 argLen: 2, 22281 commutative: true, 22282 generic: true, 22283 }, 22284 { 22285 name: "Add32withcarry", 22286 argLen: 3, 22287 commutative: true, 22288 generic: true, 22289 }, 22290 { 22291 name: "Sub32carry", 22292 argLen: 2, 22293 generic: true, 22294 }, 22295 { 22296 name: "Sub32withcarry", 22297 argLen: 3, 22298 generic: true, 22299 }, 22300 { 22301 name: "Signmask", 22302 argLen: 1, 22303 generic: true, 22304 }, 22305 { 22306 name: "Zeromask", 22307 argLen: 1, 22308 generic: true, 22309 }, 22310 { 22311 name: "Slicemask", 22312 argLen: 1, 22313 generic: true, 22314 }, 22315 { 22316 name: "Cvt32Uto32F", 22317 argLen: 1, 22318 generic: true, 22319 }, 22320 { 22321 name: "Cvt32Uto64F", 22322 argLen: 1, 22323 generic: true, 22324 }, 22325 { 22326 name: "Cvt32Fto32U", 22327 argLen: 1, 22328 generic: true, 22329 }, 22330 { 22331 name: "Cvt64Fto32U", 22332 argLen: 1, 22333 generic: true, 22334 }, 22335 { 22336 name: "Cvt64Uto32F", 22337 argLen: 1, 22338 generic: true, 22339 }, 22340 { 22341 name: "Cvt64Uto64F", 22342 argLen: 1, 22343 generic: true, 22344 }, 22345 { 22346 name: "Cvt32Fto64U", 22347 argLen: 1, 22348 generic: true, 22349 }, 22350 { 22351 name: "Cvt64Fto64U", 22352 argLen: 1, 22353 generic: true, 22354 }, 22355 { 22356 name: "Select0", 22357 argLen: 1, 22358 generic: true, 22359 }, 22360 { 22361 name: "Select1", 22362 argLen: 1, 22363 generic: true, 22364 }, 22365 { 22366 name: "AtomicLoad32", 22367 argLen: 2, 22368 generic: true, 22369 }, 22370 { 22371 name: "AtomicLoad64", 22372 argLen: 2, 22373 generic: true, 22374 }, 22375 { 22376 name: "AtomicLoadPtr", 22377 argLen: 2, 22378 generic: true, 22379 }, 22380 { 22381 name: "AtomicStore32", 22382 argLen: 3, 22383 hasSideEffects: true, 22384 generic: true, 22385 }, 22386 { 22387 name: "AtomicStore64", 22388 argLen: 3, 22389 hasSideEffects: true, 22390 generic: true, 22391 }, 22392 { 22393 name: "AtomicStorePtrNoWB", 22394 argLen: 3, 22395 hasSideEffects: true, 22396 generic: true, 22397 }, 22398 { 22399 name: "AtomicExchange32", 22400 argLen: 3, 22401 hasSideEffects: true, 22402 generic: true, 22403 }, 22404 { 22405 name: "AtomicExchange64", 22406 argLen: 3, 22407 hasSideEffects: true, 22408 generic: true, 22409 }, 22410 { 22411 name: "AtomicAdd32", 22412 argLen: 3, 22413 hasSideEffects: true, 22414 generic: true, 22415 }, 22416 { 22417 name: "AtomicAdd64", 22418 argLen: 3, 22419 hasSideEffects: true, 22420 generic: true, 22421 }, 22422 { 22423 name: "AtomicCompareAndSwap32", 22424 argLen: 4, 22425 hasSideEffects: true, 22426 generic: true, 22427 }, 22428 { 22429 name: "AtomicCompareAndSwap64", 22430 argLen: 4, 22431 hasSideEffects: true, 22432 generic: true, 22433 }, 22434 { 22435 name: "AtomicAnd8", 22436 argLen: 3, 22437 hasSideEffects: true, 22438 generic: true, 22439 }, 22440 { 22441 name: "AtomicOr8", 22442 argLen: 3, 22443 hasSideEffects: true, 22444 generic: true, 22445 }, 22446 } 22447 22448 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 22449 func (o Op) String() string { return opcodeTable[o].name } 22450 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 22451 func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } 22452 func (o Op) IsCall() bool { return opcodeTable[o].call } 22453 22454 var registers386 = [...]Register{ 22455 {0, x86.REG_AX, "AX"}, 22456 {1, x86.REG_CX, "CX"}, 22457 {2, x86.REG_DX, "DX"}, 22458 {3, x86.REG_BX, "BX"}, 22459 {4, x86.REGSP, "SP"}, 22460 {5, x86.REG_BP, "BP"}, 22461 {6, x86.REG_SI, "SI"}, 22462 {7, x86.REG_DI, "DI"}, 22463 {8, x86.REG_X0, "X0"}, 22464 {9, x86.REG_X1, "X1"}, 22465 {10, x86.REG_X2, "X2"}, 22466 {11, x86.REG_X3, "X3"}, 22467 {12, x86.REG_X4, "X4"}, 22468 {13, x86.REG_X5, "X5"}, 22469 {14, x86.REG_X6, "X6"}, 22470 {15, x86.REG_X7, "X7"}, 22471 {16, 0, "SB"}, 22472 } 22473 var gpRegMask386 = regMask(239) 22474 var fpRegMask386 = regMask(65280) 22475 var specialRegMask386 = regMask(0) 22476 var framepointerReg386 = int8(5) 22477 var linkReg386 = int8(-1) 22478 var registersAMD64 = [...]Register{ 22479 {0, x86.REG_AX, "AX"}, 22480 {1, x86.REG_CX, "CX"}, 22481 {2, x86.REG_DX, "DX"}, 22482 {3, x86.REG_BX, "BX"}, 22483 {4, x86.REGSP, "SP"}, 22484 {5, x86.REG_BP, "BP"}, 22485 {6, x86.REG_SI, "SI"}, 22486 {7, x86.REG_DI, "DI"}, 22487 {8, x86.REG_R8, "R8"}, 22488 {9, x86.REG_R9, "R9"}, 22489 {10, x86.REG_R10, "R10"}, 22490 {11, x86.REG_R11, "R11"}, 22491 {12, x86.REG_R12, "R12"}, 22492 {13, x86.REG_R13, "R13"}, 22493 {14, x86.REG_R14, "R14"}, 22494 {15, x86.REG_R15, "R15"}, 22495 {16, x86.REG_X0, "X0"}, 22496 {17, x86.REG_X1, "X1"}, 22497 {18, x86.REG_X2, "X2"}, 22498 {19, x86.REG_X3, "X3"}, 22499 {20, x86.REG_X4, "X4"}, 22500 {21, x86.REG_X5, "X5"}, 22501 {22, x86.REG_X6, "X6"}, 22502 {23, x86.REG_X7, "X7"}, 22503 {24, x86.REG_X8, "X8"}, 22504 {25, x86.REG_X9, "X9"}, 22505 {26, x86.REG_X10, "X10"}, 22506 {27, x86.REG_X11, "X11"}, 22507 {28, x86.REG_X12, "X12"}, 22508 {29, x86.REG_X13, "X13"}, 22509 {30, x86.REG_X14, "X14"}, 22510 {31, x86.REG_X15, "X15"}, 22511 {32, 0, "SB"}, 22512 } 22513 var gpRegMaskAMD64 = regMask(65519) 22514 var fpRegMaskAMD64 = regMask(4294901760) 22515 var specialRegMaskAMD64 = regMask(0) 22516 var framepointerRegAMD64 = int8(5) 22517 var linkRegAMD64 = int8(-1) 22518 var registersARM = [...]Register{ 22519 {0, arm.REG_R0, "R0"}, 22520 {1, arm.REG_R1, "R1"}, 22521 {2, arm.REG_R2, "R2"}, 22522 {3, arm.REG_R3, "R3"}, 22523 {4, arm.REG_R4, "R4"}, 22524 {5, arm.REG_R5, "R5"}, 22525 {6, arm.REG_R6, "R6"}, 22526 {7, arm.REG_R7, "R7"}, 22527 {8, arm.REG_R8, "R8"}, 22528 {9, arm.REG_R9, "R9"}, 22529 {10, arm.REGG, "g"}, 22530 {11, arm.REG_R11, "R11"}, 22531 {12, arm.REG_R12, "R12"}, 22532 {13, arm.REGSP, "SP"}, 22533 {14, arm.REG_R14, "R14"}, 22534 {15, arm.REG_R15, "R15"}, 22535 {16, arm.REG_F0, "F0"}, 22536 {17, arm.REG_F1, "F1"}, 22537 {18, arm.REG_F2, "F2"}, 22538 {19, arm.REG_F3, "F3"}, 22539 {20, arm.REG_F4, "F4"}, 22540 {21, arm.REG_F5, "F5"}, 22541 {22, arm.REG_F6, "F6"}, 22542 {23, arm.REG_F7, "F7"}, 22543 {24, arm.REG_F8, "F8"}, 22544 {25, arm.REG_F9, "F9"}, 22545 {26, arm.REG_F10, "F10"}, 22546 {27, arm.REG_F11, "F11"}, 22547 {28, arm.REG_F12, "F12"}, 22548 {29, arm.REG_F13, "F13"}, 22549 {30, arm.REG_F14, "F14"}, 22550 {31, arm.REG_F15, "F15"}, 22551 {32, 0, "SB"}, 22552 } 22553 var gpRegMaskARM = regMask(21503) 22554 var fpRegMaskARM = regMask(4294901760) 22555 var specialRegMaskARM = regMask(0) 22556 var framepointerRegARM = int8(-1) 22557 var linkRegARM = int8(14) 22558 var registersARM64 = [...]Register{ 22559 {0, arm64.REG_R0, "R0"}, 22560 {1, arm64.REG_R1, "R1"}, 22561 {2, arm64.REG_R2, "R2"}, 22562 {3, arm64.REG_R3, "R3"}, 22563 {4, arm64.REG_R4, "R4"}, 22564 {5, arm64.REG_R5, "R5"}, 22565 {6, arm64.REG_R6, "R6"}, 22566 {7, arm64.REG_R7, "R7"}, 22567 {8, arm64.REG_R8, "R8"}, 22568 {9, arm64.REG_R9, "R9"}, 22569 {10, arm64.REG_R10, "R10"}, 22570 {11, arm64.REG_R11, "R11"}, 22571 {12, arm64.REG_R12, "R12"}, 22572 {13, arm64.REG_R13, "R13"}, 22573 {14, arm64.REG_R14, "R14"}, 22574 {15, arm64.REG_R15, "R15"}, 22575 {16, arm64.REG_R16, "R16"}, 22576 {17, arm64.REG_R17, "R17"}, 22577 {18, arm64.REG_R18, "R18"}, 22578 {19, arm64.REG_R19, "R19"}, 22579 {20, arm64.REG_R20, "R20"}, 22580 {21, arm64.REG_R21, "R21"}, 22581 {22, arm64.REG_R22, "R22"}, 22582 {23, arm64.REG_R23, "R23"}, 22583 {24, arm64.REG_R24, "R24"}, 22584 {25, arm64.REG_R25, "R25"}, 22585 {26, arm64.REG_R26, "R26"}, 22586 {27, arm64.REGG, "g"}, 22587 {28, arm64.REG_R29, "R29"}, 22588 {29, arm64.REG_R30, "R30"}, 22589 {30, arm64.REGSP, "SP"}, 22590 {31, arm64.REG_F0, "F0"}, 22591 {32, arm64.REG_F1, "F1"}, 22592 {33, arm64.REG_F2, "F2"}, 22593 {34, arm64.REG_F3, "F3"}, 22594 {35, arm64.REG_F4, "F4"}, 22595 {36, arm64.REG_F5, "F5"}, 22596 {37, arm64.REG_F6, "F6"}, 22597 {38, arm64.REG_F7, "F7"}, 22598 {39, arm64.REG_F8, "F8"}, 22599 {40, arm64.REG_F9, "F9"}, 22600 {41, arm64.REG_F10, "F10"}, 22601 {42, arm64.REG_F11, "F11"}, 22602 {43, arm64.REG_F12, "F12"}, 22603 {44, arm64.REG_F13, "F13"}, 22604 {45, arm64.REG_F14, "F14"}, 22605 {46, arm64.REG_F15, "F15"}, 22606 {47, arm64.REG_F16, "F16"}, 22607 {48, arm64.REG_F17, "F17"}, 22608 {49, arm64.REG_F18, "F18"}, 22609 {50, arm64.REG_F19, "F19"}, 22610 {51, arm64.REG_F20, "F20"}, 22611 {52, arm64.REG_F21, "F21"}, 22612 {53, arm64.REG_F22, "F22"}, 22613 {54, arm64.REG_F23, "F23"}, 22614 {55, arm64.REG_F24, "F24"}, 22615 {56, arm64.REG_F25, "F25"}, 22616 {57, arm64.REG_F26, "F26"}, 22617 {58, arm64.REG_F27, "F27"}, 22618 {59, arm64.REG_F28, "F28"}, 22619 {60, arm64.REG_F29, "F29"}, 22620 {61, arm64.REG_F30, "F30"}, 22621 {62, arm64.REG_F31, "F31"}, 22622 {63, 0, "SB"}, 22623 } 22624 var gpRegMaskARM64 = regMask(670826495) 22625 var fpRegMaskARM64 = regMask(9223372034707292160) 22626 var specialRegMaskARM64 = regMask(0) 22627 var framepointerRegARM64 = int8(-1) 22628 var linkRegARM64 = int8(29) 22629 var registersMIPS = [...]Register{ 22630 {0, mips.REG_R0, "R0"}, 22631 {1, mips.REG_R1, "R1"}, 22632 {2, mips.REG_R2, "R2"}, 22633 {3, mips.REG_R3, "R3"}, 22634 {4, mips.REG_R4, "R4"}, 22635 {5, mips.REG_R5, "R5"}, 22636 {6, mips.REG_R6, "R6"}, 22637 {7, mips.REG_R7, "R7"}, 22638 {8, mips.REG_R8, "R8"}, 22639 {9, mips.REG_R9, "R9"}, 22640 {10, mips.REG_R10, "R10"}, 22641 {11, mips.REG_R11, "R11"}, 22642 {12, mips.REG_R12, "R12"}, 22643 {13, mips.REG_R13, "R13"}, 22644 {14, mips.REG_R14, "R14"}, 22645 {15, mips.REG_R15, "R15"}, 22646 {16, mips.REG_R16, "R16"}, 22647 {17, mips.REG_R17, "R17"}, 22648 {18, mips.REG_R18, "R18"}, 22649 {19, mips.REG_R19, "R19"}, 22650 {20, mips.REG_R20, "R20"}, 22651 {21, mips.REG_R21, "R21"}, 22652 {22, mips.REG_R22, "R22"}, 22653 {23, mips.REG_R24, "R24"}, 22654 {24, mips.REG_R25, "R25"}, 22655 {25, mips.REG_R28, "R28"}, 22656 {26, mips.REGSP, "SP"}, 22657 {27, mips.REGG, "g"}, 22658 {28, mips.REG_R31, "R31"}, 22659 {29, mips.REG_F0, "F0"}, 22660 {30, mips.REG_F2, "F2"}, 22661 {31, mips.REG_F4, "F4"}, 22662 {32, mips.REG_F6, "F6"}, 22663 {33, mips.REG_F8, "F8"}, 22664 {34, mips.REG_F10, "F10"}, 22665 {35, mips.REG_F12, "F12"}, 22666 {36, mips.REG_F14, "F14"}, 22667 {37, mips.REG_F16, "F16"}, 22668 {38, mips.REG_F18, "F18"}, 22669 {39, mips.REG_F20, "F20"}, 22670 {40, mips.REG_F22, "F22"}, 22671 {41, mips.REG_F24, "F24"}, 22672 {42, mips.REG_F26, "F26"}, 22673 {43, mips.REG_F28, "F28"}, 22674 {44, mips.REG_F30, "F30"}, 22675 {45, mips.REG_HI, "HI"}, 22676 {46, mips.REG_LO, "LO"}, 22677 {47, 0, "SB"}, 22678 } 22679 var gpRegMaskMIPS = regMask(335544318) 22680 var fpRegMaskMIPS = regMask(35183835217920) 22681 var specialRegMaskMIPS = regMask(105553116266496) 22682 var framepointerRegMIPS = int8(-1) 22683 var linkRegMIPS = int8(28) 22684 var registersMIPS64 = [...]Register{ 22685 {0, mips.REG_R0, "R0"}, 22686 {1, mips.REG_R1, "R1"}, 22687 {2, mips.REG_R2, "R2"}, 22688 {3, mips.REG_R3, "R3"}, 22689 {4, mips.REG_R4, "R4"}, 22690 {5, mips.REG_R5, "R5"}, 22691 {6, mips.REG_R6, "R6"}, 22692 {7, mips.REG_R7, "R7"}, 22693 {8, mips.REG_R8, "R8"}, 22694 {9, mips.REG_R9, "R9"}, 22695 {10, mips.REG_R10, "R10"}, 22696 {11, mips.REG_R11, "R11"}, 22697 {12, mips.REG_R12, "R12"}, 22698 {13, mips.REG_R13, "R13"}, 22699 {14, mips.REG_R14, "R14"}, 22700 {15, mips.REG_R15, "R15"}, 22701 {16, mips.REG_R16, "R16"}, 22702 {17, mips.REG_R17, "R17"}, 22703 {18, mips.REG_R18, "R18"}, 22704 {19, mips.REG_R19, "R19"}, 22705 {20, mips.REG_R20, "R20"}, 22706 {21, mips.REG_R21, "R21"}, 22707 {22, mips.REG_R22, "R22"}, 22708 {23, mips.REG_R24, "R24"}, 22709 {24, mips.REG_R25, "R25"}, 22710 {25, mips.REGSP, "SP"}, 22711 {26, mips.REGG, "g"}, 22712 {27, mips.REG_R31, "R31"}, 22713 {28, mips.REG_F0, "F0"}, 22714 {29, mips.REG_F1, "F1"}, 22715 {30, mips.REG_F2, "F2"}, 22716 {31, mips.REG_F3, "F3"}, 22717 {32, mips.REG_F4, "F4"}, 22718 {33, mips.REG_F5, "F5"}, 22719 {34, mips.REG_F6, "F6"}, 22720 {35, mips.REG_F7, "F7"}, 22721 {36, mips.REG_F8, "F8"}, 22722 {37, mips.REG_F9, "F9"}, 22723 {38, mips.REG_F10, "F10"}, 22724 {39, mips.REG_F11, "F11"}, 22725 {40, mips.REG_F12, "F12"}, 22726 {41, mips.REG_F13, "F13"}, 22727 {42, mips.REG_F14, "F14"}, 22728 {43, mips.REG_F15, "F15"}, 22729 {44, mips.REG_F16, "F16"}, 22730 {45, mips.REG_F17, "F17"}, 22731 {46, mips.REG_F18, "F18"}, 22732 {47, mips.REG_F19, "F19"}, 22733 {48, mips.REG_F20, "F20"}, 22734 {49, mips.REG_F21, "F21"}, 22735 {50, mips.REG_F22, "F22"}, 22736 {51, mips.REG_F23, "F23"}, 22737 {52, mips.REG_F24, "F24"}, 22738 {53, mips.REG_F25, "F25"}, 22739 {54, mips.REG_F26, "F26"}, 22740 {55, mips.REG_F27, "F27"}, 22741 {56, mips.REG_F28, "F28"}, 22742 {57, mips.REG_F29, "F29"}, 22743 {58, mips.REG_F30, "F30"}, 22744 {59, mips.REG_F31, "F31"}, 22745 {60, mips.REG_HI, "HI"}, 22746 {61, mips.REG_LO, "LO"}, 22747 {62, 0, "SB"}, 22748 } 22749 var gpRegMaskMIPS64 = regMask(167772158) 22750 var fpRegMaskMIPS64 = regMask(1152921504338411520) 22751 var specialRegMaskMIPS64 = regMask(3458764513820540928) 22752 var framepointerRegMIPS64 = int8(-1) 22753 var linkRegMIPS64 = int8(27) 22754 var registersPPC64 = [...]Register{ 22755 {0, ppc64.REG_R0, "R0"}, 22756 {1, ppc64.REGSP, "SP"}, 22757 {2, 0, "SB"}, 22758 {3, ppc64.REG_R3, "R3"}, 22759 {4, ppc64.REG_R4, "R4"}, 22760 {5, ppc64.REG_R5, "R5"}, 22761 {6, ppc64.REG_R6, "R6"}, 22762 {7, ppc64.REG_R7, "R7"}, 22763 {8, ppc64.REG_R8, "R8"}, 22764 {9, ppc64.REG_R9, "R9"}, 22765 {10, ppc64.REG_R10, "R10"}, 22766 {11, ppc64.REG_R11, "R11"}, 22767 {12, ppc64.REG_R12, "R12"}, 22768 {13, ppc64.REG_R13, "R13"}, 22769 {14, ppc64.REG_R14, "R14"}, 22770 {15, ppc64.REG_R15, "R15"}, 22771 {16, ppc64.REG_R16, "R16"}, 22772 {17, ppc64.REG_R17, "R17"}, 22773 {18, ppc64.REG_R18, "R18"}, 22774 {19, ppc64.REG_R19, "R19"}, 22775 {20, ppc64.REG_R20, "R20"}, 22776 {21, ppc64.REG_R21, "R21"}, 22777 {22, ppc64.REG_R22, "R22"}, 22778 {23, ppc64.REG_R23, "R23"}, 22779 {24, ppc64.REG_R24, "R24"}, 22780 {25, ppc64.REG_R25, "R25"}, 22781 {26, ppc64.REG_R26, "R26"}, 22782 {27, ppc64.REG_R27, "R27"}, 22783 {28, ppc64.REG_R28, "R28"}, 22784 {29, ppc64.REG_R29, "R29"}, 22785 {30, ppc64.REGG, "g"}, 22786 {31, ppc64.REG_R31, "R31"}, 22787 {32, ppc64.REG_F0, "F0"}, 22788 {33, ppc64.REG_F1, "F1"}, 22789 {34, ppc64.REG_F2, "F2"}, 22790 {35, ppc64.REG_F3, "F3"}, 22791 {36, ppc64.REG_F4, "F4"}, 22792 {37, ppc64.REG_F5, "F5"}, 22793 {38, ppc64.REG_F6, "F6"}, 22794 {39, ppc64.REG_F7, "F7"}, 22795 {40, ppc64.REG_F8, "F8"}, 22796 {41, ppc64.REG_F9, "F9"}, 22797 {42, ppc64.REG_F10, "F10"}, 22798 {43, ppc64.REG_F11, "F11"}, 22799 {44, ppc64.REG_F12, "F12"}, 22800 {45, ppc64.REG_F13, "F13"}, 22801 {46, ppc64.REG_F14, "F14"}, 22802 {47, ppc64.REG_F15, "F15"}, 22803 {48, ppc64.REG_F16, "F16"}, 22804 {49, ppc64.REG_F17, "F17"}, 22805 {50, ppc64.REG_F18, "F18"}, 22806 {51, ppc64.REG_F19, "F19"}, 22807 {52, ppc64.REG_F20, "F20"}, 22808 {53, ppc64.REG_F21, "F21"}, 22809 {54, ppc64.REG_F22, "F22"}, 22810 {55, ppc64.REG_F23, "F23"}, 22811 {56, ppc64.REG_F24, "F24"}, 22812 {57, ppc64.REG_F25, "F25"}, 22813 {58, ppc64.REG_F26, "F26"}, 22814 {59, ppc64.REG_F27, "F27"}, 22815 {60, ppc64.REG_F28, "F28"}, 22816 {61, ppc64.REG_F29, "F29"}, 22817 {62, ppc64.REG_F30, "F30"}, 22818 {63, ppc64.REG_F31, "F31"}, 22819 } 22820 var gpRegMaskPPC64 = regMask(1073733624) 22821 var fpRegMaskPPC64 = regMask(576460743713488896) 22822 var specialRegMaskPPC64 = regMask(0) 22823 var framepointerRegPPC64 = int8(1) 22824 var linkRegPPC64 = int8(-1) 22825 var registersS390X = [...]Register{ 22826 {0, s390x.REG_R0, "R0"}, 22827 {1, s390x.REG_R1, "R1"}, 22828 {2, s390x.REG_R2, "R2"}, 22829 {3, s390x.REG_R3, "R3"}, 22830 {4, s390x.REG_R4, "R4"}, 22831 {5, s390x.REG_R5, "R5"}, 22832 {6, s390x.REG_R6, "R6"}, 22833 {7, s390x.REG_R7, "R7"}, 22834 {8, s390x.REG_R8, "R8"}, 22835 {9, s390x.REG_R9, "R9"}, 22836 {10, s390x.REG_R10, "R10"}, 22837 {11, s390x.REG_R11, "R11"}, 22838 {12, s390x.REG_R12, "R12"}, 22839 {13, s390x.REGG, "g"}, 22840 {14, s390x.REG_R14, "R14"}, 22841 {15, s390x.REGSP, "SP"}, 22842 {16, s390x.REG_F0, "F0"}, 22843 {17, s390x.REG_F1, "F1"}, 22844 {18, s390x.REG_F2, "F2"}, 22845 {19, s390x.REG_F3, "F3"}, 22846 {20, s390x.REG_F4, "F4"}, 22847 {21, s390x.REG_F5, "F5"}, 22848 {22, s390x.REG_F6, "F6"}, 22849 {23, s390x.REG_F7, "F7"}, 22850 {24, s390x.REG_F8, "F8"}, 22851 {25, s390x.REG_F9, "F9"}, 22852 {26, s390x.REG_F10, "F10"}, 22853 {27, s390x.REG_F11, "F11"}, 22854 {28, s390x.REG_F12, "F12"}, 22855 {29, s390x.REG_F13, "F13"}, 22856 {30, s390x.REG_F14, "F14"}, 22857 {31, s390x.REG_F15, "F15"}, 22858 {32, 0, "SB"}, 22859 } 22860 var gpRegMaskS390X = regMask(21503) 22861 var fpRegMaskS390X = regMask(4294901760) 22862 var specialRegMaskS390X = regMask(0) 22863 var framepointerRegS390X = int8(-1) 22864 var linkRegS390X = int8(14)