github.com/tidwall/go@v0.0.0-20170415222209-6694a6888b7d/src/cmd/internal/obj/s390x/asmz.go (about) 1 // Based on cmd/internal/obj/ppc64/asm9.go. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package s390x 31 32 import ( 33 "cmd/internal/obj" 34 "log" 35 "math" 36 "sort" 37 ) 38 39 // ctxtz holds state while assembling a single function. 40 // Each function gets a fresh ctxtz. 41 // This allows for multiple functions to be safely concurrently assembled. 42 type ctxtz struct { 43 ctxt *obj.Link 44 newprog obj.ProgAlloc 45 cursym *obj.LSym 46 autosize int32 47 instoffset int64 48 pc int64 49 } 50 51 // instruction layout. 52 const ( 53 funcAlign = 16 54 ) 55 56 type Optab struct { 57 as obj.As // opcode 58 a1 uint8 // From 59 a2 uint8 // Reg 60 a3 uint8 // From3 61 a4 uint8 // To 62 type_ int8 63 param int16 // REGSP for auto variables 64 } 65 66 var optab = []Optab{ 67 // instruction, From, Reg, From3, To, type, param 68 Optab{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0}, 69 Optab{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0}, 70 71 // move register 72 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 73 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 74 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 75 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 76 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 77 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 1, 0}, 78 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 79 80 // load constant 81 Optab{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 82 Optab{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 83 Optab{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 84 Optab{AMOVD, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 85 Optab{AMOVW, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 86 Optab{AMOVWZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 87 Optab{AMOVB, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 88 Optab{AMOVBZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 89 90 // store constant 91 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 92 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 93 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 94 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 95 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 96 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 97 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 98 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 99 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 100 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 101 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 102 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 103 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 104 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 105 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 106 107 // store 108 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 109 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 110 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 111 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 112 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 113 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 114 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 115 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 116 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 117 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 118 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 119 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 120 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 121 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 122 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 123 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 124 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 125 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 126 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 127 128 // load 129 Optab{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 130 Optab{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 131 Optab{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 132 Optab{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 133 Optab{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 134 Optab{AMOVDBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 135 Optab{AMOVHBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 136 Optab{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 137 Optab{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 138 Optab{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 139 Optab{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 140 Optab{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 141 Optab{AMOVDBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 142 Optab{AMOVHBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 143 Optab{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 144 Optab{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 145 Optab{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 146 Optab{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 147 Optab{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 148 149 // interlocked load and op 150 Optab{ALAAG, C_REG, C_REG, C_NONE, C_LOREG, 99, 0}, 151 152 // integer arithmetic 153 Optab{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 154 Optab{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 155 Optab{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 0}, 156 Optab{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 0}, 157 Optab{AADD, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 158 Optab{AADD, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 159 Optab{ASUB, C_LCON, C_REG, C_NONE, C_REG, 21, 0}, 160 Optab{ASUB, C_LCON, C_NONE, C_NONE, C_REG, 21, 0}, 161 Optab{ASUB, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 162 Optab{ASUB, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 163 Optab{AMULHD, C_REG, C_NONE, C_NONE, C_REG, 4, 0}, 164 Optab{AMULHD, C_REG, C_REG, C_NONE, C_REG, 4, 0}, 165 Optab{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 166 Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 167 Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0}, 168 Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0}, 169 Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0}, 170 Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0}, 171 172 // integer logical 173 Optab{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 174 Optab{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 175 Optab{AAND, C_LCON, C_NONE, C_NONE, C_REG, 23, 0}, 176 Optab{AAND, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 177 Optab{AAND, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 178 Optab{AANDW, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 179 Optab{AANDW, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 180 Optab{AANDW, C_LCON, C_NONE, C_NONE, C_REG, 24, 0}, 181 Optab{AANDW, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 182 Optab{AANDW, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 183 Optab{ASLD, C_REG, C_NONE, C_NONE, C_REG, 7, 0}, 184 Optab{ASLD, C_REG, C_REG, C_NONE, C_REG, 7, 0}, 185 Optab{ASLD, C_SCON, C_REG, C_NONE, C_REG, 7, 0}, 186 Optab{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 7, 0}, 187 188 // compare and swap 189 Optab{ACSG, C_REG, C_REG, C_NONE, C_SOREG, 79, 0}, 190 191 // floating point 192 Optab{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 193 Optab{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 0}, 194 Optab{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 0}, 195 Optab{AFMADD, C_FREG, C_FREG, C_NONE, C_FREG, 34, 0}, 196 Optab{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 197 Optab{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, REGSP}, 198 Optab{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 0}, 199 Optab{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 0}, 200 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 201 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 0}, 202 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 0}, 203 Optab{AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 67, 0}, 204 Optab{ACEFBRA, C_REG, C_NONE, C_NONE, C_FREG, 82, 0}, 205 Optab{ACFEBRA, C_FREG, C_NONE, C_NONE, C_REG, 83, 0}, 206 Optab{AFIEBR, C_SCON, C_FREG, C_NONE, C_FREG, 48, 0}, 207 208 // load symbol address (plus offset) 209 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_REG, 19, 0}, 210 Optab{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 93, 0}, 211 Optab{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 94, 0}, 212 Optab{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 95, 0}, 213 214 // system call 215 Optab{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 0}, 216 Optab{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 0}, 217 218 // branch 219 Optab{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 0}, 220 Optab{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 0}, 221 Optab{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 16, 0}, 222 Optab{ABR, C_NONE, C_NONE, C_NONE, C_REG, 18, 0}, 223 Optab{ABR, C_REG, C_NONE, C_NONE, C_REG, 18, 0}, 224 Optab{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 225 Optab{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 226 Optab{ACMPBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 227 Optab{ACMPBEQ, C_REG, C_NONE, C_ADDCON, C_SBRA, 90, 0}, 228 Optab{ACMPBEQ, C_REG, C_NONE, C_SCON, C_SBRA, 90, 0}, 229 Optab{ACMPUBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 230 Optab{ACMPUBEQ, C_REG, C_NONE, C_ANDCON, C_SBRA, 90, 0}, 231 232 // move on condition 233 Optab{AMOVDEQ, C_REG, C_NONE, C_NONE, C_REG, 17, 0}, 234 235 // find leftmost one 236 Optab{AFLOGR, C_REG, C_NONE, C_NONE, C_REG, 8, 0}, 237 238 // compare 239 Optab{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 240 Optab{ACMP, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 241 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 242 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 243 Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0}, 244 Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0}, 245 246 // 32-bit access registers 247 Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 248 Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 249 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 250 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 251 252 // macros 253 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LOREG, 96, 0}, 254 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LAUTO, 96, REGSP}, 255 256 // load/store multiple 257 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LOREG, 97, 0}, 258 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LAUTO, 97, REGSP}, 259 Optab{ALMG, C_LOREG, C_REG, C_NONE, C_REG, 98, 0}, 260 Optab{ALMG, C_LAUTO, C_REG, C_NONE, C_REG, 98, REGSP}, 261 262 // bytes 263 Optab{ABYTE, C_SCON, C_NONE, C_NONE, C_NONE, 40, 0}, 264 Optab{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 0}, 265 Optab{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 0}, 266 Optab{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 0}, 267 268 // fast synchronization 269 Optab{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 81, 0}, 270 271 // store clock 272 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SAUTO, 88, REGSP}, 273 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SOREG, 88, 0}, 274 275 // storage and storage 276 Optab{AMVC, C_LOREG, C_NONE, C_SCON, C_LOREG, 84, 0}, 277 Optab{AMVC, C_LOREG, C_NONE, C_SCON, C_LAUTO, 84, REGSP}, 278 Optab{AMVC, C_LAUTO, C_NONE, C_SCON, C_LAUTO, 84, REGSP}, 279 280 // address 281 Optab{ALARL, C_LCON, C_NONE, C_NONE, C_REG, 85, 0}, 282 Optab{ALARL, C_SYMADDR, C_NONE, C_NONE, C_REG, 85, 0}, 283 Optab{ALA, C_SOREG, C_NONE, C_NONE, C_REG, 86, 0}, 284 Optab{ALA, C_SAUTO, C_NONE, C_NONE, C_REG, 86, REGSP}, 285 Optab{AEXRL, C_SYMADDR, C_NONE, C_NONE, C_REG, 87, 0}, 286 287 // misc 288 Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 0}, 289 Optab{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0}, 290 Optab{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0}, 291 Optab{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0}, 292 Optab{obj.ANOP, C_SAUTO, C_NONE, C_NONE, C_NONE, 0, 0}, 293 294 // vector instructions 295 296 // VRX store 297 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SOREG, 100, 0}, 298 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SAUTO, 100, REGSP}, 299 Optab{AVSTEG, C_VREG, C_NONE, C_SCON, C_SOREG, 100, 0}, 300 Optab{AVSTEG, C_VREG, C_NONE, C_SCON, C_SAUTO, 100, REGSP}, 301 302 // VRX load 303 Optab{AVL, C_SOREG, C_NONE, C_NONE, C_VREG, 101, 0}, 304 Optab{AVL, C_SAUTO, C_NONE, C_NONE, C_VREG, 101, REGSP}, 305 Optab{AVLEG, C_SOREG, C_NONE, C_SCON, C_VREG, 101, 0}, 306 Optab{AVLEG, C_SAUTO, C_NONE, C_SCON, C_VREG, 101, REGSP}, 307 308 // VRV scatter 309 Optab{AVSCEG, C_VREG, C_NONE, C_SCON, C_SOREG, 102, 0}, 310 Optab{AVSCEG, C_VREG, C_NONE, C_SCON, C_SAUTO, 102, REGSP}, 311 312 // VRV gather 313 Optab{AVGEG, C_SOREG, C_NONE, C_SCON, C_VREG, 103, 0}, 314 Optab{AVGEG, C_SAUTO, C_NONE, C_SCON, C_VREG, 103, REGSP}, 315 316 // VRS element shift/rotate and load gr to/from vr element 317 Optab{AVESLG, C_SCON, C_VREG, C_NONE, C_VREG, 104, 0}, 318 Optab{AVESLG, C_REG, C_VREG, C_NONE, C_VREG, 104, 0}, 319 Optab{AVESLG, C_SCON, C_NONE, C_NONE, C_VREG, 104, 0}, 320 Optab{AVESLG, C_REG, C_NONE, C_NONE, C_VREG, 104, 0}, 321 Optab{AVLGVG, C_SCON, C_VREG, C_NONE, C_REG, 104, 0}, 322 Optab{AVLGVG, C_REG, C_VREG, C_NONE, C_REG, 104, 0}, 323 Optab{AVLVGG, C_SCON, C_REG, C_NONE, C_VREG, 104, 0}, 324 Optab{AVLVGG, C_REG, C_REG, C_NONE, C_VREG, 104, 0}, 325 326 // VRS store multiple 327 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SOREG, 105, 0}, 328 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SAUTO, 105, REGSP}, 329 330 // VRS load multiple 331 Optab{AVLM, C_SOREG, C_VREG, C_NONE, C_VREG, 106, 0}, 332 Optab{AVLM, C_SAUTO, C_VREG, C_NONE, C_VREG, 106, REGSP}, 333 334 // VRS store with length 335 Optab{AVSTL, C_VREG, C_NONE, C_REG, C_SOREG, 107, 0}, 336 Optab{AVSTL, C_VREG, C_NONE, C_REG, C_SAUTO, 107, REGSP}, 337 338 // VRS load with length 339 Optab{AVLL, C_SOREG, C_NONE, C_REG, C_VREG, 108, 0}, 340 Optab{AVLL, C_SAUTO, C_NONE, C_REG, C_VREG, 108, REGSP}, 341 342 // VRI-a 343 Optab{AVGBM, C_ANDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 344 Optab{AVZERO, C_NONE, C_NONE, C_NONE, C_VREG, 109, 0}, 345 Optab{AVREPIG, C_ADDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 346 Optab{AVREPIG, C_SCON, C_NONE, C_NONE, C_VREG, 109, 0}, 347 Optab{AVLEIG, C_ADDCON, C_NONE, C_SCON, C_VREG, 109, 0}, 348 Optab{AVLEIG, C_SCON, C_NONE, C_SCON, C_VREG, 109, 0}, 349 350 // VRI-b generate mask 351 Optab{AVGMG, C_SCON, C_NONE, C_SCON, C_VREG, 110, 0}, 352 353 // VRI-c replicate 354 Optab{AVREPG, C_UCON, C_VREG, C_NONE, C_VREG, 111, 0}, 355 356 // VRI-d element rotate and insert under mask and 357 // shift left double by byte 358 Optab{AVERIMG, C_VREG, C_VREG, C_SCON, C_VREG, 112, 0}, 359 Optab{AVSLDB, C_VREG, C_VREG, C_SCON, C_VREG, 112, 0}, 360 361 // VRI-d fp test data class immediate 362 Optab{AVFTCIDB, C_SCON, C_VREG, C_NONE, C_VREG, 113, 0}, 363 364 // VRR-a load reg 365 Optab{AVLR, C_VREG, C_NONE, C_NONE, C_VREG, 114, 0}, 366 367 // VRR-a compare 368 Optab{AVECG, C_VREG, C_NONE, C_NONE, C_VREG, 115, 0}, 369 370 // VRR-b 371 Optab{AVCEQG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 372 Optab{AVFAEF, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 373 Optab{AVPKSG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 374 375 // VRR-c 376 Optab{AVAQ, C_VREG, C_VREG, C_NONE, C_VREG, 118, 0}, 377 Optab{AVAQ, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 378 Optab{AVNOT, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 379 Optab{AVPDI, C_VREG, C_VREG, C_SCON, C_VREG, 123, 0}, 380 381 // VRR-c shifts 382 Optab{AVERLLVG, C_VREG, C_VREG, C_NONE, C_VREG, 119, 0}, 383 Optab{AVERLLVG, C_VREG, C_NONE, C_NONE, C_VREG, 119, 0}, 384 385 // VRR-d 386 // 2 3 1 4 387 Optab{AVACQ, C_VREG, C_VREG, C_VREG, C_VREG, 120, 0}, 388 389 // VRR-e 390 Optab{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 121, 0}, 391 392 // VRR-f 393 Optab{AVLVGP, C_REG, C_REG, C_NONE, C_VREG, 122, 0}, 394 } 395 396 var oprange [ALAST & obj.AMask][]Optab 397 398 var xcmp [C_NCLASS][C_NCLASS]bool 399 400 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 401 p := cursym.Text 402 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 403 return 404 } 405 406 if oprange[AORW&obj.AMask] == nil { 407 ctxt.Diag("s390x ops not initialized, call s390x.buildop first") 408 } 409 410 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 411 412 buffer := make([]byte, 0) 413 changed := true 414 loop := 0 415 for changed { 416 if loop > 10 { 417 c.ctxt.Diag("stuck in spanz loop") 418 break 419 } 420 changed = false 421 buffer = buffer[:0] 422 c.cursym.R = make([]obj.Reloc, 0) 423 for p := c.cursym.Text; p != nil; p = p.Link { 424 pc := int64(len(buffer)) 425 if pc != p.Pc { 426 changed = true 427 } 428 p.Pc = pc 429 c.pc = p.Pc 430 c.asmout(p, &buffer) 431 if pc == int64(len(buffer)) { 432 switch p.As { 433 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 434 // ok 435 default: 436 c.ctxt.Diag("zero-width instruction\n%v", p) 437 } 438 } 439 } 440 loop++ 441 } 442 443 c.cursym.Size = int64(len(buffer)) 444 if c.cursym.Size%funcAlign != 0 { 445 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign) 446 } 447 c.cursym.Grow(c.cursym.Size) 448 copy(c.cursym.P, buffer) 449 } 450 451 func isint32(v int64) bool { 452 return int64(int32(v)) == v 453 } 454 455 func isuint32(v uint64) bool { 456 return uint64(uint32(v)) == v 457 } 458 459 func (c *ctxtz) aclass(a *obj.Addr) int { 460 switch a.Type { 461 case obj.TYPE_NONE: 462 return C_NONE 463 464 case obj.TYPE_REG: 465 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 466 return C_REG 467 } 468 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 469 return C_FREG 470 } 471 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 472 return C_AREG 473 } 474 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 475 return C_VREG 476 } 477 return C_GOK 478 479 case obj.TYPE_MEM: 480 switch a.Name { 481 case obj.NAME_EXTERN, 482 obj.NAME_STATIC: 483 if a.Sym == nil { 484 // must have a symbol 485 break 486 } 487 c.instoffset = a.Offset 488 if a.Sym.Type == obj.STLSBSS { 489 if c.ctxt.Flag_shared { 490 return C_TLS_IE // initial exec model 491 } 492 return C_TLS_LE // local exec model 493 } 494 return C_ADDR 495 496 case obj.NAME_GOTREF: 497 return C_GOTADDR 498 499 case obj.NAME_AUTO: 500 c.instoffset = int64(c.autosize) + a.Offset 501 if c.instoffset >= -BIG && c.instoffset < BIG { 502 return C_SAUTO 503 } 504 return C_LAUTO 505 506 case obj.NAME_PARAM: 507 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 508 if c.instoffset >= -BIG && c.instoffset < BIG { 509 return C_SAUTO 510 } 511 return C_LAUTO 512 513 case obj.NAME_NONE: 514 c.instoffset = a.Offset 515 if c.instoffset == 0 { 516 return C_ZOREG 517 } 518 if c.instoffset >= -BIG && c.instoffset < BIG { 519 return C_SOREG 520 } 521 return C_LOREG 522 } 523 524 return C_GOK 525 526 case obj.TYPE_TEXTSIZE: 527 return C_TEXTSIZE 528 529 case obj.TYPE_FCONST: 530 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 531 return C_ZCON 532 } 533 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val) 534 535 case obj.TYPE_CONST, 536 obj.TYPE_ADDR: 537 switch a.Name { 538 case obj.NAME_NONE: 539 c.instoffset = a.Offset 540 if a.Reg != 0 { 541 if -BIG <= c.instoffset && c.instoffset <= BIG { 542 return C_SACON 543 } 544 if isint32(c.instoffset) { 545 return C_LACON 546 } 547 return C_DACON 548 } 549 goto consize 550 551 case obj.NAME_EXTERN, 552 obj.NAME_STATIC: 553 s := a.Sym 554 if s == nil { 555 break 556 } 557 c.instoffset = a.Offset 558 if s.Type == obj.SCONST { 559 goto consize 560 } 561 562 return C_SYMADDR 563 564 case obj.NAME_AUTO: 565 c.instoffset = int64(c.autosize) + a.Offset 566 if c.instoffset >= -BIG && c.instoffset < BIG { 567 return C_SACON 568 } 569 return C_LACON 570 571 case obj.NAME_PARAM: 572 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 573 if c.instoffset >= -BIG && c.instoffset < BIG { 574 return C_SACON 575 } 576 return C_LACON 577 } 578 579 return C_GOK 580 581 consize: 582 if c.instoffset == 0 { 583 return C_ZCON 584 } 585 if c.instoffset >= 0 { 586 if c.instoffset <= 0x7fff { 587 return C_SCON 588 } 589 if c.instoffset <= 0xffff { 590 return C_ANDCON 591 } 592 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 593 return C_UCON 594 } 595 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 596 return C_LCON 597 } 598 return C_DCON 599 } 600 601 if c.instoffset >= -0x8000 { 602 return C_ADDCON 603 } 604 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 605 return C_UCON 606 } 607 if isint32(c.instoffset) { 608 return C_LCON 609 } 610 return C_DCON 611 612 case obj.TYPE_BRANCH: 613 return C_SBRA 614 } 615 616 return C_GOK 617 } 618 619 func (c *ctxtz) oplook(p *obj.Prog) *Optab { 620 a1 := int(p.Optab) 621 if a1 != 0 { 622 return &optab[a1-1] 623 } 624 a1 = int(p.From.Class) 625 if a1 == 0 { 626 a1 = c.aclass(&p.From) + 1 627 p.From.Class = int8(a1) 628 } 629 630 a1-- 631 a3 := C_NONE + 1 632 if p.From3 != nil { 633 a3 = int(p.From3.Class) 634 if a3 == 0 { 635 a3 = c.aclass(p.From3) + 1 636 p.From3.Class = int8(a3) 637 } 638 } 639 640 a3-- 641 a4 := int(p.To.Class) 642 if a4 == 0 { 643 a4 = c.aclass(&p.To) + 1 644 p.To.Class = int8(a4) 645 } 646 647 a4-- 648 a2 := C_NONE 649 if p.Reg != 0 { 650 if REG_R0 <= p.Reg && p.Reg <= REG_R15 { 651 a2 = C_REG 652 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 653 a2 = C_VREG 654 } else if REG_F0 <= p.Reg && p.Reg <= REG_F15 { 655 a2 = C_FREG 656 } else if REG_AR0 <= p.Reg && p.Reg <= REG_AR15 { 657 a2 = C_AREG 658 } 659 } 660 661 ops := oprange[p.As&obj.AMask] 662 c1 := &xcmp[a1] 663 c2 := &xcmp[a2] 664 c3 := &xcmp[a3] 665 c4 := &xcmp[a4] 666 for i := range ops { 667 op := &ops[i] 668 if (int(op.a2) == a2 || c2[op.a2]) && c4[op.a4] && c1[op.a1] && c3[op.a3] { 669 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 670 return op 671 } 672 } 673 674 // cannot find a case; abort 675 c.ctxt.Diag("illegal combination %v %v %v %v %v\n", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 676 c.ctxt.Diag("prog: %v\n", p) 677 return nil 678 } 679 680 func cmp(a int, b int) bool { 681 if a == b { 682 return true 683 } 684 switch a { 685 case C_DCON: 686 if b == C_LCON { 687 return true 688 } 689 fallthrough 690 case C_LCON: 691 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 692 return true 693 } 694 695 case C_ADDCON: 696 if b == C_ZCON || b == C_SCON { 697 return true 698 } 699 700 case C_ANDCON: 701 if b == C_ZCON || b == C_SCON { 702 return true 703 } 704 705 case C_UCON: 706 if b == C_ZCON || b == C_SCON { 707 return true 708 } 709 710 case C_SCON: 711 if b == C_ZCON { 712 return true 713 } 714 715 case C_LACON: 716 if b == C_SACON { 717 return true 718 } 719 720 case C_LBRA: 721 if b == C_SBRA { 722 return true 723 } 724 725 case C_LAUTO: 726 if b == C_SAUTO { 727 return true 728 } 729 730 case C_LOREG: 731 if b == C_ZOREG || b == C_SOREG { 732 return true 733 } 734 735 case C_SOREG: 736 if b == C_ZOREG { 737 return true 738 } 739 740 case C_ANY: 741 return true 742 } 743 744 return false 745 } 746 747 type ocmp []Optab 748 749 func (x ocmp) Len() int { 750 return len(x) 751 } 752 753 func (x ocmp) Swap(i, j int) { 754 x[i], x[j] = x[j], x[i] 755 } 756 757 func (x ocmp) Less(i, j int) bool { 758 p1 := &x[i] 759 p2 := &x[j] 760 n := int(p1.as) - int(p2.as) 761 if n != 0 { 762 return n < 0 763 } 764 n = int(p1.a1) - int(p2.a1) 765 if n != 0 { 766 return n < 0 767 } 768 n = int(p1.a2) - int(p2.a2) 769 if n != 0 { 770 return n < 0 771 } 772 n = int(p1.a3) - int(p2.a3) 773 if n != 0 { 774 return n < 0 775 } 776 n = int(p1.a4) - int(p2.a4) 777 if n != 0 { 778 return n < 0 779 } 780 return false 781 } 782 func opset(a, b obj.As) { 783 oprange[a&obj.AMask] = oprange[b&obj.AMask] 784 } 785 786 func buildop(ctxt *obj.Link) { 787 if oprange[AORW&obj.AMask] != nil { 788 // Already initialized; stop now. 789 // This happens in the cmd/asm tests, 790 // each of which re-initializes the arch. 791 return 792 } 793 794 for i := 0; i < C_NCLASS; i++ { 795 for n := 0; n < C_NCLASS; n++ { 796 if cmp(n, i) { 797 xcmp[i][n] = true 798 } 799 } 800 } 801 sort.Sort(ocmp(optab)) 802 for i := 0; i < len(optab); i++ { 803 r := optab[i].as 804 start := i 805 for ; i+1 < len(optab); i++ { 806 if optab[i+1].as != r { 807 break 808 } 809 } 810 oprange[r&obj.AMask] = optab[start : i+1] 811 812 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 813 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 814 switch r { 815 case AADD: 816 opset(AADDC, r) 817 opset(AADDW, r) 818 opset(AMULLD, r) 819 opset(AMULLW, r) 820 case ADIVW: 821 opset(AADDE, r) 822 opset(ADIVD, r) 823 opset(ADIVDU, r) 824 opset(ADIVWU, r) 825 opset(AMODD, r) 826 opset(AMODDU, r) 827 opset(AMODW, r) 828 opset(AMODWU, r) 829 case AMULHD: 830 opset(AMULHDU, r) 831 case AMOVBZ: 832 opset(AMOVH, r) 833 opset(AMOVHZ, r) 834 case ALA: 835 opset(ALAY, r) 836 case AMVC: 837 opset(ACLC, r) 838 opset(AXC, r) 839 opset(AOC, r) 840 opset(ANC, r) 841 case ASTCK: 842 opset(ASTCKC, r) 843 opset(ASTCKE, r) 844 opset(ASTCKF, r) 845 case ALAAG: 846 opset(ALAA, r) 847 opset(ALAAL, r) 848 opset(ALAALG, r) 849 opset(ALAN, r) 850 opset(ALANG, r) 851 opset(ALAX, r) 852 opset(ALAXG, r) 853 opset(ALAO, r) 854 opset(ALAOG, r) 855 case ASTMG: 856 opset(ASTMY, r) 857 case ALMG: 858 opset(ALMY, r) 859 case ABEQ: 860 opset(ABGE, r) 861 opset(ABGT, r) 862 opset(ABLE, r) 863 opset(ABLT, r) 864 opset(ABNE, r) 865 opset(ABVC, r) 866 opset(ABVS, r) 867 opset(ABLEU, r) 868 opset(ABLTU, r) 869 case ABR: 870 opset(ABL, r) 871 case ABC: 872 opset(ABCL, r) 873 case AFABS: 874 opset(AFNABS, r) 875 opset(AFNEG, r) 876 opset(AFNEGS, r) 877 opset(ALEDBR, r) 878 opset(ALDEBR, r) 879 opset(AFSQRT, r) 880 opset(AFSQRTS, r) 881 case AFADD: 882 opset(AFADDS, r) 883 opset(AFDIV, r) 884 opset(AFDIVS, r) 885 opset(AFSUB, r) 886 opset(AFSUBS, r) 887 case AFMADD: 888 opset(AFMADDS, r) 889 opset(AFMSUB, r) 890 opset(AFMSUBS, r) 891 case AFMUL: 892 opset(AFMULS, r) 893 case AFCMPO: 894 opset(AFCMPU, r) 895 opset(ACEBR, r) 896 case AAND: 897 opset(AOR, r) 898 opset(AXOR, r) 899 case AANDW: 900 opset(AORW, r) 901 opset(AXORW, r) 902 case ASLD: 903 opset(ASRD, r) 904 opset(ASLW, r) 905 opset(ASRW, r) 906 opset(ASRAD, r) 907 opset(ASRAW, r) 908 opset(ARLL, r) 909 opset(ARLLG, r) 910 case ACSG: 911 opset(ACS, r) 912 case ASUB: 913 opset(ASUBC, r) 914 opset(ASUBE, r) 915 opset(ASUBW, r) 916 case ANEG: 917 opset(ANEGW, r) 918 case AFMOVD: 919 opset(AFMOVS, r) 920 case AMOVDBR: 921 opset(AMOVWBR, r) 922 case ACMP: 923 opset(ACMPW, r) 924 case ACMPU: 925 opset(ACMPWU, r) 926 case ACEFBRA: 927 opset(ACDFBRA, r) 928 opset(ACEGBRA, r) 929 opset(ACDGBRA, r) 930 opset(ACELFBR, r) 931 opset(ACDLFBR, r) 932 opset(ACELGBR, r) 933 opset(ACDLGBR, r) 934 case ACFEBRA: 935 opset(ACFDBRA, r) 936 opset(ACGEBRA, r) 937 opset(ACGDBRA, r) 938 opset(ACLFEBR, r) 939 opset(ACLFDBR, r) 940 opset(ACLGEBR, r) 941 opset(ACLGDBR, r) 942 case AFIEBR: 943 opset(AFIDBR, r) 944 case ACMPBEQ: 945 opset(ACMPBGE, r) 946 opset(ACMPBGT, r) 947 opset(ACMPBLE, r) 948 opset(ACMPBLT, r) 949 opset(ACMPBNE, r) 950 case ACMPUBEQ: 951 opset(ACMPUBGE, r) 952 opset(ACMPUBGT, r) 953 opset(ACMPUBLE, r) 954 opset(ACMPUBLT, r) 955 opset(ACMPUBNE, r) 956 case AMOVDEQ: 957 opset(AMOVDGE, r) 958 opset(AMOVDGT, r) 959 opset(AMOVDLE, r) 960 opset(AMOVDLT, r) 961 opset(AMOVDNE, r) 962 case AVL: 963 opset(AVLLEZB, r) 964 opset(AVLLEZH, r) 965 opset(AVLLEZF, r) 966 opset(AVLLEZG, r) 967 opset(AVLREPB, r) 968 opset(AVLREPH, r) 969 opset(AVLREPF, r) 970 opset(AVLREPG, r) 971 case AVLEG: 972 opset(AVLBB, r) 973 opset(AVLEB, r) 974 opset(AVLEH, r) 975 opset(AVLEF, r) 976 opset(AVLEG, r) 977 opset(AVLREP, r) 978 case AVSTEG: 979 opset(AVSTEB, r) 980 opset(AVSTEH, r) 981 opset(AVSTEF, r) 982 case AVSCEG: 983 opset(AVSCEF, r) 984 case AVGEG: 985 opset(AVGEF, r) 986 case AVESLG: 987 opset(AVESLB, r) 988 opset(AVESLH, r) 989 opset(AVESLF, r) 990 opset(AVERLLB, r) 991 opset(AVERLLH, r) 992 opset(AVERLLF, r) 993 opset(AVERLLG, r) 994 opset(AVESRAB, r) 995 opset(AVESRAH, r) 996 opset(AVESRAF, r) 997 opset(AVESRAG, r) 998 opset(AVESRLB, r) 999 opset(AVESRLH, r) 1000 opset(AVESRLF, r) 1001 opset(AVESRLG, r) 1002 case AVLGVG: 1003 opset(AVLGVB, r) 1004 opset(AVLGVH, r) 1005 opset(AVLGVF, r) 1006 case AVLVGG: 1007 opset(AVLVGB, r) 1008 opset(AVLVGH, r) 1009 opset(AVLVGF, r) 1010 case AVZERO: 1011 opset(AVONE, r) 1012 case AVREPIG: 1013 opset(AVREPIB, r) 1014 opset(AVREPIH, r) 1015 opset(AVREPIF, r) 1016 case AVLEIG: 1017 opset(AVLEIB, r) 1018 opset(AVLEIH, r) 1019 opset(AVLEIF, r) 1020 case AVGMG: 1021 opset(AVGMB, r) 1022 opset(AVGMH, r) 1023 opset(AVGMF, r) 1024 case AVREPG: 1025 opset(AVREPB, r) 1026 opset(AVREPH, r) 1027 opset(AVREPF, r) 1028 case AVERIMG: 1029 opset(AVERIMB, r) 1030 opset(AVERIMH, r) 1031 opset(AVERIMF, r) 1032 case AVFTCIDB: 1033 opset(AWFTCIDB, r) 1034 case AVLR: 1035 opset(AVUPHB, r) 1036 opset(AVUPHH, r) 1037 opset(AVUPHF, r) 1038 opset(AVUPLHB, r) 1039 opset(AVUPLHH, r) 1040 opset(AVUPLHF, r) 1041 opset(AVUPLB, r) 1042 opset(AVUPLHW, r) 1043 opset(AVUPLF, r) 1044 opset(AVUPLLB, r) 1045 opset(AVUPLLH, r) 1046 opset(AVUPLLF, r) 1047 opset(AVCLZB, r) 1048 opset(AVCLZH, r) 1049 opset(AVCLZF, r) 1050 opset(AVCLZG, r) 1051 opset(AVCTZB, r) 1052 opset(AVCTZH, r) 1053 opset(AVCTZF, r) 1054 opset(AVCTZG, r) 1055 opset(AVLDEB, r) 1056 opset(AWLDEB, r) 1057 opset(AVFLCDB, r) 1058 opset(AWFLCDB, r) 1059 opset(AVFLNDB, r) 1060 opset(AWFLNDB, r) 1061 opset(AVFLPDB, r) 1062 opset(AWFLPDB, r) 1063 opset(AVFSQDB, r) 1064 opset(AWFSQDB, r) 1065 opset(AVISTRB, r) 1066 opset(AVISTRH, r) 1067 opset(AVISTRF, r) 1068 opset(AVISTRBS, r) 1069 opset(AVISTRHS, r) 1070 opset(AVISTRFS, r) 1071 opset(AVLCB, r) 1072 opset(AVLCH, r) 1073 opset(AVLCF, r) 1074 opset(AVLCG, r) 1075 opset(AVLPB, r) 1076 opset(AVLPH, r) 1077 opset(AVLPF, r) 1078 opset(AVLPG, r) 1079 opset(AVPOPCT, r) 1080 opset(AVSEGB, r) 1081 opset(AVSEGH, r) 1082 opset(AVSEGF, r) 1083 case AVECG: 1084 opset(AVECB, r) 1085 opset(AVECH, r) 1086 opset(AVECF, r) 1087 opset(AVECLB, r) 1088 opset(AVECLH, r) 1089 opset(AVECLF, r) 1090 opset(AVECLG, r) 1091 opset(AWFCDB, r) 1092 opset(AWFKDB, r) 1093 case AVCEQG: 1094 opset(AVCEQB, r) 1095 opset(AVCEQH, r) 1096 opset(AVCEQF, r) 1097 opset(AVCEQBS, r) 1098 opset(AVCEQHS, r) 1099 opset(AVCEQFS, r) 1100 opset(AVCEQGS, r) 1101 opset(AVCHB, r) 1102 opset(AVCHH, r) 1103 opset(AVCHF, r) 1104 opset(AVCHG, r) 1105 opset(AVCHBS, r) 1106 opset(AVCHHS, r) 1107 opset(AVCHFS, r) 1108 opset(AVCHGS, r) 1109 opset(AVCHLB, r) 1110 opset(AVCHLH, r) 1111 opset(AVCHLF, r) 1112 opset(AVCHLG, r) 1113 opset(AVCHLBS, r) 1114 opset(AVCHLHS, r) 1115 opset(AVCHLFS, r) 1116 opset(AVCHLGS, r) 1117 case AVFAEF: 1118 opset(AVFAEB, r) 1119 opset(AVFAEH, r) 1120 opset(AVFAEBS, r) 1121 opset(AVFAEHS, r) 1122 opset(AVFAEFS, r) 1123 opset(AVFAEZB, r) 1124 opset(AVFAEZH, r) 1125 opset(AVFAEZF, r) 1126 opset(AVFAEZBS, r) 1127 opset(AVFAEZHS, r) 1128 opset(AVFAEZFS, r) 1129 opset(AVFEEB, r) 1130 opset(AVFEEH, r) 1131 opset(AVFEEF, r) 1132 opset(AVFEEBS, r) 1133 opset(AVFEEHS, r) 1134 opset(AVFEEFS, r) 1135 opset(AVFEEZB, r) 1136 opset(AVFEEZH, r) 1137 opset(AVFEEZF, r) 1138 opset(AVFEEZBS, r) 1139 opset(AVFEEZHS, r) 1140 opset(AVFEEZFS, r) 1141 opset(AVFENEB, r) 1142 opset(AVFENEH, r) 1143 opset(AVFENEF, r) 1144 opset(AVFENEBS, r) 1145 opset(AVFENEHS, r) 1146 opset(AVFENEFS, r) 1147 opset(AVFENEZB, r) 1148 opset(AVFENEZH, r) 1149 opset(AVFENEZF, r) 1150 opset(AVFENEZBS, r) 1151 opset(AVFENEZHS, r) 1152 opset(AVFENEZFS, r) 1153 case AVPKSG: 1154 opset(AVPKSH, r) 1155 opset(AVPKSF, r) 1156 opset(AVPKSHS, r) 1157 opset(AVPKSFS, r) 1158 opset(AVPKSGS, r) 1159 opset(AVPKLSH, r) 1160 opset(AVPKLSF, r) 1161 opset(AVPKLSG, r) 1162 opset(AVPKLSHS, r) 1163 opset(AVPKLSFS, r) 1164 opset(AVPKLSGS, r) 1165 case AVAQ: 1166 opset(AVAB, r) 1167 opset(AVAH, r) 1168 opset(AVAF, r) 1169 opset(AVAG, r) 1170 opset(AVACCB, r) 1171 opset(AVACCH, r) 1172 opset(AVACCF, r) 1173 opset(AVACCG, r) 1174 opset(AVACCQ, r) 1175 opset(AVN, r) 1176 opset(AVNC, r) 1177 opset(AVAVGB, r) 1178 opset(AVAVGH, r) 1179 opset(AVAVGF, r) 1180 opset(AVAVGG, r) 1181 opset(AVAVGLB, r) 1182 opset(AVAVGLH, r) 1183 opset(AVAVGLF, r) 1184 opset(AVAVGLG, r) 1185 opset(AVCKSM, r) 1186 opset(AVX, r) 1187 opset(AVFADB, r) 1188 opset(AWFADB, r) 1189 opset(AVFCEDB, r) 1190 opset(AVFCEDBS, r) 1191 opset(AWFCEDB, r) 1192 opset(AWFCEDBS, r) 1193 opset(AVFCHDB, r) 1194 opset(AVFCHDBS, r) 1195 opset(AWFCHDB, r) 1196 opset(AWFCHDBS, r) 1197 opset(AVFCHEDB, r) 1198 opset(AVFCHEDBS, r) 1199 opset(AWFCHEDB, r) 1200 opset(AWFCHEDBS, r) 1201 opset(AVFMDB, r) 1202 opset(AWFMDB, r) 1203 opset(AVGFMB, r) 1204 opset(AVGFMH, r) 1205 opset(AVGFMF, r) 1206 opset(AVGFMG, r) 1207 opset(AVMXB, r) 1208 opset(AVMXH, r) 1209 opset(AVMXF, r) 1210 opset(AVMXG, r) 1211 opset(AVMXLB, r) 1212 opset(AVMXLH, r) 1213 opset(AVMXLF, r) 1214 opset(AVMXLG, r) 1215 opset(AVMNB, r) 1216 opset(AVMNH, r) 1217 opset(AVMNF, r) 1218 opset(AVMNG, r) 1219 opset(AVMNLB, r) 1220 opset(AVMNLH, r) 1221 opset(AVMNLF, r) 1222 opset(AVMNLG, r) 1223 opset(AVMRHB, r) 1224 opset(AVMRHH, r) 1225 opset(AVMRHF, r) 1226 opset(AVMRHG, r) 1227 opset(AVMRLB, r) 1228 opset(AVMRLH, r) 1229 opset(AVMRLF, r) 1230 opset(AVMRLG, r) 1231 opset(AVMEB, r) 1232 opset(AVMEH, r) 1233 opset(AVMEF, r) 1234 opset(AVMLEB, r) 1235 opset(AVMLEH, r) 1236 opset(AVMLEF, r) 1237 opset(AVMOB, r) 1238 opset(AVMOH, r) 1239 opset(AVMOF, r) 1240 opset(AVMLOB, r) 1241 opset(AVMLOH, r) 1242 opset(AVMLOF, r) 1243 opset(AVMHB, r) 1244 opset(AVMHH, r) 1245 opset(AVMHF, r) 1246 opset(AVMLHB, r) 1247 opset(AVMLHH, r) 1248 opset(AVMLHF, r) 1249 opset(AVMLH, r) 1250 opset(AVMLHW, r) 1251 opset(AVMLF, r) 1252 opset(AVNO, r) 1253 opset(AVO, r) 1254 opset(AVPKH, r) 1255 opset(AVPKF, r) 1256 opset(AVPKG, r) 1257 opset(AVSUMGH, r) 1258 opset(AVSUMGF, r) 1259 opset(AVSUMQF, r) 1260 opset(AVSUMQG, r) 1261 opset(AVSUMB, r) 1262 opset(AVSUMH, r) 1263 case AVERLLVG: 1264 opset(AVERLLVB, r) 1265 opset(AVERLLVH, r) 1266 opset(AVERLLVF, r) 1267 opset(AVESLVB, r) 1268 opset(AVESLVH, r) 1269 opset(AVESLVF, r) 1270 opset(AVESLVG, r) 1271 opset(AVESRAVB, r) 1272 opset(AVESRAVH, r) 1273 opset(AVESRAVF, r) 1274 opset(AVESRAVG, r) 1275 opset(AVESRLVB, r) 1276 opset(AVESRLVH, r) 1277 opset(AVESRLVF, r) 1278 opset(AVESRLVG, r) 1279 opset(AVFDDB, r) 1280 opset(AWFDDB, r) 1281 opset(AVFSDB, r) 1282 opset(AWFSDB, r) 1283 opset(AVSL, r) 1284 opset(AVSLB, r) 1285 opset(AVSRA, r) 1286 opset(AVSRAB, r) 1287 opset(AVSRL, r) 1288 opset(AVSRLB, r) 1289 opset(AVSF, r) 1290 opset(AVSG, r) 1291 opset(AVSQ, r) 1292 opset(AVSCBIB, r) 1293 opset(AVSCBIH, r) 1294 opset(AVSCBIF, r) 1295 opset(AVSCBIG, r) 1296 opset(AVSCBIQ, r) 1297 case AVACQ: 1298 opset(AVACCCQ, r) 1299 opset(AVGFMAB, r) 1300 opset(AVGFMAH, r) 1301 opset(AVGFMAF, r) 1302 opset(AVGFMAG, r) 1303 opset(AVMALB, r) 1304 opset(AVMALHW, r) 1305 opset(AVMALF, r) 1306 opset(AVMAHB, r) 1307 opset(AVMAHH, r) 1308 opset(AVMAHF, r) 1309 opset(AVMALHB, r) 1310 opset(AVMALHH, r) 1311 opset(AVMALHF, r) 1312 opset(AVMAEB, r) 1313 opset(AVMAEH, r) 1314 opset(AVMAEF, r) 1315 opset(AVMALEB, r) 1316 opset(AVMALEH, r) 1317 opset(AVMALEF, r) 1318 opset(AVMAOB, r) 1319 opset(AVMAOH, r) 1320 opset(AVMAOF, r) 1321 opset(AVMALOB, r) 1322 opset(AVMALOH, r) 1323 opset(AVMALOF, r) 1324 opset(AVSTRCB, r) 1325 opset(AVSTRCH, r) 1326 opset(AVSTRCF, r) 1327 opset(AVSTRCBS, r) 1328 opset(AVSTRCHS, r) 1329 opset(AVSTRCFS, r) 1330 opset(AVSTRCZB, r) 1331 opset(AVSTRCZH, r) 1332 opset(AVSTRCZF, r) 1333 opset(AVSTRCZBS, r) 1334 opset(AVSTRCZHS, r) 1335 opset(AVSTRCZFS, r) 1336 opset(AVSBCBIQ, r) 1337 opset(AVSBIQ, r) 1338 case AVSEL: 1339 opset(AVFMADB, r) 1340 opset(AWFMADB, r) 1341 opset(AVFMSDB, r) 1342 opset(AWFMSDB, r) 1343 opset(AVPERM, r) 1344 } 1345 } 1346 } 1347 1348 const ( 1349 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1350 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1351 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1352 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1353 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1354 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1355 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1356 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1357 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1358 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1359 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1360 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1361 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1362 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1363 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1364 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1365 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1366 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1367 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1368 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1369 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1370 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1371 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1372 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1373 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1374 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1375 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1376 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1377 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1378 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1379 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1380 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1381 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1382 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1383 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1384 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1385 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1386 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1387 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1388 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1389 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1390 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1391 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1392 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1393 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1394 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1395 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1396 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1397 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1398 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1399 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1400 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1401 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1402 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1403 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1404 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1405 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1406 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1407 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1408 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1409 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1410 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1411 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1412 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1413 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1414 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1415 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1416 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1417 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1418 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1419 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1420 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1421 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1422 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1423 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1424 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1425 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1426 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1427 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1428 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1429 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1430 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1431 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1432 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1433 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1434 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1435 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1436 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1437 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1438 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1439 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1440 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1441 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1442 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1443 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1444 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1445 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1446 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1447 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1448 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1449 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1450 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1451 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1452 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1453 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1454 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1455 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1456 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1457 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1458 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1459 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1460 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1461 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1462 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1463 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1464 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1465 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1466 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1467 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1468 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1469 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1470 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1471 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1472 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1473 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1474 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1475 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1476 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1477 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1478 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1479 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1480 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1481 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1482 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1483 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1484 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1485 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1486 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1487 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1488 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1489 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1490 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1491 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1492 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1493 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1494 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1495 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1496 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1497 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1498 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1499 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1500 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1501 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1502 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1503 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1504 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1505 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1506 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1507 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1508 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1509 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1510 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1511 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1512 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1513 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1514 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1515 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1516 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1517 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1518 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1519 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1520 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1521 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1522 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1523 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1524 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1525 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1526 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1527 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1528 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1529 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1530 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1531 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1532 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1533 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1534 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1535 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1536 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1537 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1538 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1539 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1540 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1541 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1542 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1543 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1544 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1545 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1546 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1547 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1548 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1549 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1550 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1551 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1552 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1553 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1554 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1555 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1556 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1557 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1558 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1559 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1560 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1561 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1562 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1563 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1564 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1565 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1566 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1567 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1568 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1569 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1570 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1571 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1572 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1573 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1574 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1575 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1576 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1577 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1578 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1579 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1580 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1581 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1582 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1583 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1584 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1585 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1586 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1587 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1588 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1589 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1590 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1591 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1592 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1593 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1594 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1595 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1596 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1597 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1598 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1599 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1600 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1601 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1602 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1603 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1604 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1605 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1606 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1607 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1608 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1609 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1610 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1611 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1612 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1613 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1614 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1615 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1616 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1617 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1618 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1619 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1620 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1621 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1622 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1623 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1624 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1625 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1626 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1627 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1628 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1629 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1630 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1631 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1632 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1633 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1634 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1635 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1636 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1637 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1638 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1639 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1640 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1641 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1642 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1643 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1644 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1645 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1646 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1647 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1648 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1649 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1650 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1651 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1652 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1653 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1654 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1655 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1656 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1657 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1658 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1659 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1660 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1661 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1662 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1663 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1664 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1665 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1666 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1667 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1668 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1669 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1670 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1671 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1672 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1673 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1674 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1675 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1676 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1677 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1678 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1679 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1680 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1681 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1682 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1683 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1684 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1685 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1686 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1687 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1688 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1689 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1690 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1691 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1692 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1693 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1694 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1695 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1696 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1697 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1698 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1699 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1700 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1701 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1702 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1703 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1704 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1705 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1706 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1707 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1708 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1709 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1710 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1711 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1712 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1713 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1714 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1715 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1716 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1717 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1718 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1719 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1720 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1721 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1722 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1723 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1724 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1725 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1726 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1727 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1728 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1729 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1730 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1731 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1732 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1733 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1734 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1735 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1736 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1737 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1738 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1739 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1740 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1741 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1742 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1743 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1744 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1745 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1746 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1747 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1748 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1749 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1750 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1751 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1752 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1753 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1754 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1755 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1756 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1757 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1758 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1759 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1760 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1761 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1762 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1763 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1764 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1765 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1766 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1767 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1768 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1769 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1770 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1771 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1772 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1773 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1774 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1775 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1776 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1777 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1778 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1779 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1780 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1781 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1782 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1783 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1784 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1785 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1786 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1787 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1788 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1789 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1790 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1791 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1792 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1793 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1794 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1795 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1796 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1797 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1798 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1799 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1800 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1801 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1802 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1803 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1804 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1805 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1806 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1807 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1808 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1809 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1810 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1811 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1812 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1813 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1814 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1815 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1816 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1817 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1818 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1819 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1820 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1821 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1822 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1823 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1824 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1825 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1826 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1827 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1828 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1829 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1830 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1831 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1832 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1833 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1834 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1835 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1836 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1837 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1838 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1839 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1840 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1841 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 1842 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 1843 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 1844 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 1845 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 1846 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 1847 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 1848 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 1849 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 1850 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 1851 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 1852 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 1853 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 1854 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 1855 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 1856 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 1857 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 1858 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 1859 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 1860 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 1861 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 1862 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 1863 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 1864 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 1865 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 1866 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 1867 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 1868 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 1869 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 1870 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 1871 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 1872 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 1873 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 1874 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 1875 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 1876 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 1877 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 1878 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 1879 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 1880 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 1881 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 1882 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 1883 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 1884 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 1885 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 1886 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 1887 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 1888 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 1889 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 1890 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 1891 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 1892 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 1893 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 1894 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 1895 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 1896 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 1897 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 1898 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 1899 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 1900 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1901 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1902 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 1903 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 1904 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 1905 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 1906 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 1907 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 1908 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 1909 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 1910 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 1911 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 1912 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 1913 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 1914 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 1915 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 1916 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 1917 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 1918 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 1919 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 1920 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 1921 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 1922 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 1923 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 1924 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 1925 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 1926 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 1927 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 1928 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 1929 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 1930 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 1931 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 1932 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 1933 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 1934 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 1935 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 1936 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 1937 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 1938 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 1939 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 1940 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 1941 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 1942 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 1943 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 1944 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 1945 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 1946 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 1947 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1948 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1949 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1950 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1951 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1952 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1953 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 1954 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 1955 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 1956 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 1957 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1958 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 1959 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 1960 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1961 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 1962 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1963 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1964 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1965 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 1966 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 1967 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 1968 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 1969 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1970 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 1971 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 1972 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 1973 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 1974 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 1975 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 1976 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 1977 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 1978 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 1979 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 1980 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 1981 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 1982 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 1983 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 1984 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 1985 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 1986 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 1987 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 1988 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 1989 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 1990 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 1991 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 1992 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 1993 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 1994 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 1995 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 1996 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 1997 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 1998 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 1999 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 2000 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 2001 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 2002 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 2003 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 2004 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 2005 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 2006 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 2007 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 2008 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 2009 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 2010 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 2011 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 2012 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 2013 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 2014 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 2015 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 2016 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 2017 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 2018 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 2019 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 2020 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 2021 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 2022 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 2023 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 2024 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 2025 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 2026 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 2027 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2028 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2029 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 2030 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 2031 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 2032 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 2033 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 2034 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 2035 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 2036 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 2037 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 2038 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 2039 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 2040 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 2041 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 2042 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 2043 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 2044 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 2045 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2046 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2047 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2048 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2049 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2050 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2051 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2052 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2053 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2054 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2055 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2056 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2057 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2058 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2059 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2060 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2061 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2062 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2063 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2064 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2065 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2066 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2067 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2068 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2069 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2070 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2071 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2072 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2073 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2074 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2075 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2076 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2077 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2078 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2079 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2080 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2081 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2082 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2083 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2084 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2085 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2086 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2087 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2088 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2089 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2090 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2091 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2092 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2093 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2094 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2095 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2096 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2097 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2098 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2099 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2100 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2101 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2102 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2103 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2104 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2105 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2106 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2107 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2108 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2109 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2110 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2111 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2112 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2113 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2114 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2115 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2116 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2117 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2118 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2119 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2120 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2121 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2122 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2123 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2124 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2125 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2126 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2127 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2128 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2129 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2130 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2131 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2132 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2133 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2134 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2135 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2136 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2137 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2138 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2139 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2140 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2141 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2142 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2143 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2144 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2145 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2146 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2147 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2148 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2149 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2150 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2151 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2152 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2153 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2154 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2155 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2156 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2157 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2158 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2159 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2160 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2161 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2162 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2163 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2164 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2165 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2166 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2167 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2168 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2169 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2170 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2171 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2172 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2173 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2174 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2175 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2176 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2177 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2178 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2179 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2180 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2181 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2182 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2183 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2184 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2185 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2186 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2187 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2188 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2189 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2190 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2191 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2192 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2193 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2194 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2195 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2196 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2197 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2198 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2199 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2200 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2201 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2202 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2203 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2204 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2205 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2206 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2207 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2208 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2209 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2210 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2211 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2212 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2213 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2214 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2215 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2216 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2217 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2218 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2219 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2220 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2221 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2222 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2223 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2224 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2225 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2226 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2227 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2228 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2229 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2230 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2231 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2232 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2233 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2234 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2235 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2236 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2237 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2238 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2239 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2240 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2241 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2242 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2243 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2244 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2245 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2246 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2247 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2248 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2249 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2250 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2251 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2252 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2253 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2254 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2255 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2256 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2257 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2258 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2259 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2260 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2261 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2262 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2263 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2264 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2265 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2266 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2267 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2268 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2269 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2270 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2271 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2272 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2273 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2274 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2275 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2276 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2277 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2278 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2279 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2280 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2281 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2282 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2283 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2284 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2285 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2286 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2287 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2288 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2289 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2290 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2291 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2292 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2293 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2294 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2295 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2296 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2297 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2298 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2299 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2300 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2301 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2302 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2303 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2304 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2305 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2306 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2307 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2308 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2309 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2310 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2311 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2312 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2313 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2314 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2315 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2316 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2317 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2318 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2319 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2320 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2321 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2322 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2323 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2324 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2325 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2326 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2327 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2328 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2329 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2330 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2331 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2332 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2333 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2334 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2335 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2336 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2337 2338 // added in z13 2339 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2340 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2341 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2342 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2343 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2344 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2345 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2346 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2347 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2348 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2349 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2350 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2351 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2352 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2353 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2354 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2355 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2356 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2357 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2358 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2359 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2360 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2361 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2362 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2363 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2364 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2365 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2366 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2367 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2368 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2369 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2370 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2371 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2372 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2373 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2374 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2375 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2376 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2377 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2378 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2379 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2380 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2381 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2382 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2383 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2384 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2385 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2386 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2387 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2388 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2389 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2390 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2391 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2392 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2393 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2394 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2395 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2396 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2397 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2398 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2399 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2400 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2401 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2402 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2403 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2404 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2405 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2406 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2407 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2408 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2409 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2410 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2411 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2412 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2413 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2414 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2415 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2416 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2417 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2418 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2419 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2420 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2421 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2422 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2423 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2424 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2425 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2426 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2427 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2428 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2429 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2430 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2431 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2432 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2433 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2434 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2435 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2436 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2437 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2438 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2439 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2440 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2441 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2442 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2443 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2444 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2445 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2446 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2447 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2448 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2449 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2450 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2451 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2452 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2453 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2454 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2455 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2456 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2457 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2458 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2459 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2460 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2461 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2462 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2463 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2464 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2465 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2466 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2467 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2468 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2469 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2470 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2471 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2472 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2473 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2474 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2475 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2476 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2477 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2478 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2479 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2480 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2481 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2482 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2483 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2484 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2485 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2486 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2487 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2488 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2489 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2490 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2491 ) 2492 2493 func oclass(a *obj.Addr) int { 2494 return int(a.Class) - 1 2495 } 2496 2497 // Add a relocation for the immediate in a RIL style instruction. 2498 // The addend will be adjusted as required. 2499 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) *obj.Reloc { 2500 if sym == nil { 2501 c.ctxt.Diag("require symbol to apply relocation") 2502 } 2503 offset := int64(2) // relocation offset from start of instruction 2504 rel := obj.Addrel(c.cursym) 2505 rel.Off = int32(c.pc + offset) 2506 rel.Siz = 4 2507 rel.Sym = sym 2508 rel.Add = add + offset + int64(rel.Siz) 2509 rel.Type = obj.R_PCRELDBL 2510 return rel 2511 } 2512 2513 func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) *obj.Reloc { 2514 if sym == nil { 2515 c.ctxt.Diag("require symbol to apply relocation") 2516 } 2517 offset += int64(2) // relocation offset from start of instruction 2518 rel := obj.Addrel(c.cursym) 2519 rel.Off = int32(c.pc + offset) 2520 rel.Siz = 4 2521 rel.Sym = sym 2522 rel.Add = add + offset + int64(rel.Siz) 2523 rel.Type = obj.R_PCRELDBL 2524 return rel 2525 } 2526 2527 // Add a CALL relocation for the immediate in a RIL style instruction. 2528 // The addend will be adjusted as required. 2529 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) *obj.Reloc { 2530 if sym == nil { 2531 c.ctxt.Diag("require symbol to apply relocation") 2532 } 2533 offset := int64(2) // relocation offset from start of instruction 2534 rel := obj.Addrel(c.cursym) 2535 rel.Off = int32(c.pc + offset) 2536 rel.Siz = 4 2537 rel.Sym = sym 2538 rel.Add = add + offset + int64(rel.Siz) 2539 rel.Type = obj.R_CALL 2540 return rel 2541 } 2542 2543 func (c *ctxtz) branchMask(p *obj.Prog) uint32 { 2544 switch p.As { 2545 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ: 2546 return 0x8 2547 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE: 2548 return 0xA 2549 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT: 2550 return 0x2 2551 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE: 2552 return 0xC 2553 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT: 2554 return 0x4 2555 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE: 2556 return 0x7 2557 case ABLEU: // LE or unordered 2558 return 0xD 2559 case ABLTU: // LT or unordered 2560 return 0x5 2561 case ABVC: 2562 return 0x0 // needs extra instruction 2563 case ABVS: 2564 return 0x1 // unordered 2565 } 2566 c.ctxt.Diag("unknown conditional branch %v", p.As) 2567 return 0xF 2568 } 2569 2570 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) { 2571 o := c.oplook(p) 2572 2573 switch o.type_ { 2574 default: 2575 c.ctxt.Diag("unknown type %d", o.type_) 2576 2577 case 0: // PSEUDO OPS 2578 break 2579 2580 case 1: // mov reg reg 2581 switch p.As { 2582 default: 2583 c.ctxt.Diag("unhandled operation: %v", p.As) 2584 case AMOVD: 2585 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2586 // sign extend 2587 case AMOVW: 2588 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2589 case AMOVH: 2590 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2591 case AMOVB: 2592 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2593 // zero extend 2594 case AMOVWZ: 2595 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2596 case AMOVHZ: 2597 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2598 case AMOVBZ: 2599 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2600 // reverse bytes 2601 case AMOVDBR: 2602 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2603 case AMOVWBR: 2604 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2605 // floating point 2606 case AFMOVD, AFMOVS: 2607 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2608 } 2609 2610 case 2: // arithmetic op reg [reg] reg 2611 r := p.Reg 2612 if r == 0 { 2613 r = p.To.Reg 2614 } 2615 2616 var opcode uint32 2617 2618 switch p.As { 2619 default: 2620 c.ctxt.Diag("invalid opcode") 2621 case AADD: 2622 opcode = op_AGRK 2623 case AADDC: 2624 opcode = op_ALGRK 2625 case AADDE: 2626 opcode = op_ALCGR 2627 case AADDW: 2628 opcode = op_ARK 2629 case AMULLW: 2630 opcode = op_MSGFR 2631 case AMULLD: 2632 opcode = op_MSGR 2633 case ADIVW, AMODW: 2634 opcode = op_DSGFR 2635 case ADIVWU, AMODWU: 2636 opcode = op_DLR 2637 case ADIVD, AMODD: 2638 opcode = op_DSGR 2639 case ADIVDU, AMODDU: 2640 opcode = op_DLGR 2641 } 2642 2643 switch p.As { 2644 default: 2645 2646 case AADD, AADDC, AADDW: 2647 if p.As == AADDW && r == p.To.Reg { 2648 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2649 } else { 2650 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2651 } 2652 2653 case AADDE, AMULLW, AMULLD: 2654 if r == p.To.Reg { 2655 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2656 } else if p.From.Reg == p.To.Reg { 2657 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2658 } else { 2659 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2660 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2661 } 2662 2663 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2664 if p.As == ADIVWU || p.As == ADIVDU { 2665 zRI(op_LGHI, REGTMP, 0, asm) 2666 } 2667 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2668 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2669 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2670 2671 case AMODW, AMODWU, AMODD, AMODDU: 2672 if p.As == AMODWU || p.As == AMODDU { 2673 zRI(op_LGHI, REGTMP, 0, asm) 2674 } 2675 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2676 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2677 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2678 2679 } 2680 2681 case 3: // mov $constant reg 2682 v := c.vregoff(&p.From) 2683 switch p.As { 2684 case AMOVBZ: 2685 v = int64(uint8(v)) 2686 case AMOVHZ: 2687 v = int64(uint16(v)) 2688 case AMOVWZ: 2689 v = int64(uint32(v)) 2690 case AMOVB: 2691 v = int64(int8(v)) 2692 case AMOVH: 2693 v = int64(int16(v)) 2694 case AMOVW: 2695 v = int64(int32(v)) 2696 } 2697 if int64(int16(v)) == v { 2698 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2699 } else if v&0xffff0000 == v { 2700 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2701 } else if v&0xffff00000000 == v { 2702 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2703 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2704 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2705 } else if int64(int32(v)) == v { 2706 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2707 } else if int64(uint32(v)) == v { 2708 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2709 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2710 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2711 } else { 2712 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2713 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2714 } 2715 2716 case 4: // multiply high (a*b)>>64 2717 r := p.Reg 2718 if r == 0 { 2719 r = p.To.Reg 2720 } 2721 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2722 zRRE(op_MLGR, REGTMP, uint32(p.From.Reg), asm) 2723 switch p.As { 2724 case AMULHDU: 2725 // Unsigned: move result into correct register. 2726 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2727 case AMULHD: 2728 // Signed: need to convert result. 2729 // See Hacker's Delight 8-3. 2730 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm) 2731 zRRE(op_NGR, REGTMP2, uint32(r), asm) 2732 zRRE(op_SGR, REGTMP, REGTMP2, asm) 2733 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm) 2734 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm) 2735 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), REGTMP, asm) 2736 } 2737 2738 case 5: // syscall 2739 zI(op_SVC, 0, asm) 2740 2741 case 6: // logical op reg [reg] reg 2742 var oprr, oprre, oprrf uint32 2743 switch p.As { 2744 case AAND: 2745 oprre = op_NGR 2746 oprrf = op_NGRK 2747 case AANDW: 2748 oprr = op_NR 2749 oprrf = op_NRK 2750 case AOR: 2751 oprre = op_OGR 2752 oprrf = op_OGRK 2753 case AORW: 2754 oprr = op_OR 2755 oprrf = op_ORK 2756 case AXOR: 2757 oprre = op_XGR 2758 oprrf = op_XGRK 2759 case AXORW: 2760 oprr = op_XR 2761 oprrf = op_XRK 2762 } 2763 if p.Reg == 0 { 2764 if oprr != 0 { 2765 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2766 } else { 2767 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2768 } 2769 } else { 2770 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2771 } 2772 2773 case 7: // shift/rotate reg [reg] reg 2774 d2 := c.vregoff(&p.From) 2775 b2 := p.From.Reg 2776 r3 := p.Reg 2777 if r3 == 0 { 2778 r3 = p.To.Reg 2779 } 2780 r1 := p.To.Reg 2781 var opcode uint32 2782 switch p.As { 2783 default: 2784 case ASLD: 2785 opcode = op_SLLG 2786 case ASRD: 2787 opcode = op_SRLG 2788 case ASLW: 2789 opcode = op_SLLK 2790 case ASRW: 2791 opcode = op_SRLK 2792 case ARLL: 2793 opcode = op_RLL 2794 case ARLLG: 2795 opcode = op_RLLG 2796 case ASRAW: 2797 opcode = op_SRAK 2798 case ASRAD: 2799 opcode = op_SRAG 2800 } 2801 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2802 2803 case 8: // find leftmost one 2804 if p.To.Reg&1 != 0 { 2805 c.ctxt.Diag("target must be an even-numbered register") 2806 } 2807 // FLOGR also writes a mask to p.To.Reg+1. 2808 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2809 2810 case 10: // subtract reg [reg] reg 2811 r := int(p.Reg) 2812 2813 switch p.As { 2814 default: 2815 case ASUB: 2816 if r == 0 { 2817 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2818 } else { 2819 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2820 } 2821 case ASUBC: 2822 if r == 0 { 2823 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2824 } else { 2825 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2826 } 2827 case ASUBE: 2828 if r == 0 { 2829 r = int(p.To.Reg) 2830 } 2831 if r == int(p.To.Reg) { 2832 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2833 } else if p.From.Reg == p.To.Reg { 2834 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 2835 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2836 zRRE(op_SLBGR, uint32(p.To.Reg), REGTMP, asm) 2837 } else { 2838 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2839 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2840 } 2841 case ASUBW: 2842 if r == 0 { 2843 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2844 } else { 2845 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2846 } 2847 } 2848 2849 case 11: // br/bl 2850 v := int32(0) 2851 2852 if p.Pcond != nil { 2853 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2854 } 2855 2856 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 2857 zRI(op_BRC, 0xF, uint32(v), asm) 2858 } else { 2859 if p.As == ABL { 2860 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 2861 } else { 2862 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 2863 } 2864 if p.To.Sym != nil { 2865 c.addcallreloc(p.To.Sym, p.To.Offset) 2866 } 2867 } 2868 2869 case 12: 2870 r1 := p.To.Reg 2871 d2 := c.vregoff(&p.From) 2872 b2 := p.From.Reg 2873 if b2 == 0 { 2874 b2 = o.param 2875 } 2876 x2 := p.From.Index 2877 if -DISP20/2 > d2 || d2 >= DISP20/2 { 2878 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 2879 if x2 != 0 { 2880 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 2881 } 2882 x2 = REGTMP 2883 d2 = 0 2884 } 2885 var opx, opxy uint32 2886 switch p.As { 2887 case AADD: 2888 opxy = op_AG 2889 case AADDC: 2890 opxy = op_ALG 2891 case AADDW: 2892 opx = op_A 2893 opxy = op_AY 2894 case AMULLW: 2895 opx = op_MS 2896 opxy = op_MSY 2897 case AMULLD: 2898 opxy = op_MSG 2899 case ASUB: 2900 opxy = op_SG 2901 case ASUBC: 2902 opxy = op_SLG 2903 case ASUBE: 2904 opxy = op_SLBG 2905 case ASUBW: 2906 opx = op_S 2907 opxy = op_SY 2908 case AAND: 2909 opxy = op_NG 2910 case AANDW: 2911 opx = op_N 2912 opxy = op_NY 2913 case AOR: 2914 opxy = op_OG 2915 case AORW: 2916 opx = op_O 2917 opxy = op_OY 2918 case AXOR: 2919 opxy = op_XG 2920 case AXORW: 2921 opx = op_X 2922 opxy = op_XY 2923 } 2924 if opx != 0 && 0 <= d2 && d2 < DISP12 { 2925 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2926 } else { 2927 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2928 } 2929 2930 case 15: // br/bl (reg) 2931 r := p.To.Reg 2932 if p.As == ABCL || p.As == ABL { 2933 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 2934 } else { 2935 zRR(op_BCR, 0xF, uint32(r), asm) 2936 } 2937 2938 case 16: // conditional branch 2939 v := int32(0) 2940 if p.Pcond != nil { 2941 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2942 } 2943 mask := c.branchMask(p) 2944 if p.To.Sym == nil && int32(int16(v)) == v { 2945 zRI(op_BRC, mask, uint32(v), asm) 2946 } else { 2947 zRIL(_c, op_BRCL, mask, uint32(v), asm) 2948 } 2949 if p.To.Sym != nil { 2950 c.addrilreloc(p.To.Sym, p.To.Offset) 2951 } 2952 2953 case 17: // move on condition 2954 m3 := c.branchMask(p) 2955 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2956 2957 case 18: // br/bl reg 2958 if p.As == ABL { 2959 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 2960 } else { 2961 zRR(op_BCR, 0xF, uint32(p.To.Reg), asm) 2962 } 2963 2964 case 19: // mov $sym+n(SB) reg 2965 d := c.vregoff(&p.From) 2966 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 2967 if d&1 != 0 { 2968 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 2969 d -= 1 2970 } 2971 c.addrilreloc(p.From.Sym, d) 2972 2973 case 21: // subtract $constant [reg] reg 2974 v := c.vregoff(&p.From) 2975 r := p.Reg 2976 if r == 0 { 2977 r = p.To.Reg 2978 } 2979 switch p.As { 2980 case ASUB: 2981 zRIL(_a, op_LGFI, uint32(REGTMP), uint32(v), asm) 2982 zRRF(op_SLGRK, uint32(REGTMP), 0, uint32(p.To.Reg), uint32(r), asm) 2983 case ASUBC: 2984 if r != p.To.Reg { 2985 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2986 } 2987 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm) 2988 case ASUBW: 2989 if r != p.To.Reg { 2990 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 2991 } 2992 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm) 2993 } 2994 2995 case 22: // add/multiply $constant [reg] reg 2996 v := c.vregoff(&p.From) 2997 r := p.Reg 2998 if r == 0 { 2999 r = p.To.Reg 3000 } 3001 var opri, opril, oprie uint32 3002 switch p.As { 3003 case AADD: 3004 opri = op_AGHI 3005 opril = op_AGFI 3006 oprie = op_AGHIK 3007 case AADDC: 3008 opril = op_ALGFI 3009 oprie = op_ALGHSIK 3010 case AADDW: 3011 opri = op_AHI 3012 opril = op_AFI 3013 oprie = op_AHIK 3014 case AMULLW: 3015 opri = op_MHI 3016 opril = op_MSFI 3017 case AMULLD: 3018 opri = op_MGHI 3019 opril = op_MSGFI 3020 } 3021 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) { 3022 switch p.As { 3023 case AADD, AADDC, AMULLD: 3024 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3025 case AADDW, AMULLW: 3026 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3027 } 3028 r = p.To.Reg 3029 } 3030 if r == p.To.Reg { 3031 if opri != 0 && int64(int16(v)) == v { 3032 zRI(opri, uint32(p.To.Reg), uint32(v), asm) 3033 } else { 3034 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm) 3035 } 3036 } else { 3037 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 3038 } 3039 3040 case 23: // 64-bit logical op $constant reg 3041 // TODO(mundaym): merge with case 24. 3042 v := c.vregoff(&p.From) 3043 switch p.As { 3044 default: 3045 c.ctxt.Diag("%v is not supported", p) 3046 case AAND: 3047 if v >= 0 { // needs zero extend 3048 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3049 zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm) 3050 } else if int64(int16(v)) == v { 3051 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3052 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 3053 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3054 } 3055 case AOR: 3056 if int64(uint32(v)) != v { // needs sign extend 3057 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3058 zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm) 3059 } else if int64(uint16(v)) == v { 3060 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3061 } else { 3062 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3063 } 3064 case AXOR: 3065 if int64(uint32(v)) != v { // needs sign extend 3066 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3067 zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm) 3068 } else { 3069 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3070 } 3071 } 3072 3073 case 24: // 32-bit logical op $constant reg 3074 v := c.vregoff(&p.From) 3075 switch p.As { 3076 case AANDW: 3077 if uint32(v&0xffff0000) == 0xffff0000 { 3078 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3079 } else if uint32(v&0x0000ffff) == 0x0000ffff { 3080 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3081 } else { 3082 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3083 } 3084 case AORW: 3085 if uint32(v&0xffff0000) == 0 { 3086 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3087 } else if uint32(v&0x0000ffff) == 0 { 3088 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3089 } else { 3090 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3091 } 3092 case AXORW: 3093 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3094 } 3095 3096 case 26: // MOVD $offset(base)(index), reg 3097 v := c.regoff(&p.From) 3098 r := p.From.Reg 3099 if r == 0 { 3100 r = o.param 3101 } 3102 i := p.From.Index 3103 if v >= 0 && v < DISP12 { 3104 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3105 } else if v >= -DISP20/2 && v < DISP20/2 { 3106 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3107 } else { 3108 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3109 zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, uint32(i), asm) 3110 } 3111 3112 case 31: // dword 3113 wd := uint64(c.vregoff(&p.From)) 3114 *asm = append(*asm, 3115 uint8(wd>>56), 3116 uint8(wd>>48), 3117 uint8(wd>>40), 3118 uint8(wd>>32), 3119 uint8(wd>>24), 3120 uint8(wd>>16), 3121 uint8(wd>>8), 3122 uint8(wd)) 3123 3124 case 32: // float op freg freg 3125 var opcode uint32 3126 switch p.As { 3127 default: 3128 c.ctxt.Diag("invalid opcode") 3129 case AFADD: 3130 opcode = op_ADBR 3131 case AFADDS: 3132 opcode = op_AEBR 3133 case AFDIV: 3134 opcode = op_DDBR 3135 case AFDIVS: 3136 opcode = op_DEBR 3137 case AFMUL: 3138 opcode = op_MDBR 3139 case AFMULS: 3140 opcode = op_MEEBR 3141 case AFSUB: 3142 opcode = op_SDBR 3143 case AFSUBS: 3144 opcode = op_SEBR 3145 } 3146 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3147 3148 case 33: // float op [freg] freg 3149 r := p.From.Reg 3150 if oclass(&p.From) == C_NONE { 3151 r = p.To.Reg 3152 } 3153 var opcode uint32 3154 switch p.As { 3155 default: 3156 case AFABS: 3157 opcode = op_LPDBR 3158 case AFNABS: 3159 opcode = op_LNDBR 3160 case AFNEG: 3161 opcode = op_LCDFR 3162 case AFNEGS: 3163 opcode = op_LCEBR 3164 case ALEDBR: 3165 opcode = op_LEDBR 3166 case ALDEBR: 3167 opcode = op_LDEBR 3168 case AFSQRT: 3169 opcode = op_SQDBR 3170 case AFSQRTS: 3171 opcode = op_SQEBR 3172 } 3173 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3174 3175 case 34: // float multiply-add freg freg freg 3176 var opcode uint32 3177 switch p.As { 3178 default: 3179 c.ctxt.Diag("invalid opcode") 3180 case AFMADD: 3181 opcode = op_MADBR 3182 case AFMADDS: 3183 opcode = op_MAEBR 3184 case AFMSUB: 3185 opcode = op_MSDBR 3186 case AFMSUBS: 3187 opcode = op_MSEBR 3188 } 3189 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 3190 3191 case 35: // mov reg mem (no relocation) 3192 d2 := c.regoff(&p.To) 3193 b2 := p.To.Reg 3194 if b2 == 0 { 3195 b2 = o.param 3196 } 3197 x2 := p.To.Index 3198 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3199 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3200 if x2 != 0 { 3201 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3202 } 3203 x2 = REGTMP 3204 d2 = 0 3205 } 3206 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3207 3208 case 36: // mov mem reg (no relocation) 3209 d2 := c.regoff(&p.From) 3210 b2 := p.From.Reg 3211 if b2 == 0 { 3212 b2 = o.param 3213 } 3214 x2 := p.From.Index 3215 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3216 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3217 if x2 != 0 { 3218 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3219 } 3220 x2 = REGTMP 3221 d2 = 0 3222 } 3223 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3224 3225 case 40: // word/byte 3226 wd := uint32(c.regoff(&p.From)) 3227 if p.As == AWORD { //WORD 3228 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3229 } else { //BYTE 3230 *asm = append(*asm, uint8(wd)) 3231 } 3232 3233 case 47: // negate [reg] reg 3234 r := p.From.Reg 3235 if r == 0 { 3236 r = p.To.Reg 3237 } 3238 switch p.As { 3239 case ANEG: 3240 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3241 case ANEGW: 3242 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm) 3243 } 3244 3245 case 48: // floating-point round to integer 3246 m3 := c.vregoff(&p.From) 3247 if 0 > m3 || m3 > 7 { 3248 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3) 3249 } 3250 var opcode uint32 3251 switch p.As { 3252 case AFIEBR: 3253 opcode = op_FIEBR 3254 case AFIDBR: 3255 opcode = op_FIDBR 3256 } 3257 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3258 3259 case 67: // fmov $0 freg 3260 var opcode uint32 3261 switch p.As { 3262 case AFMOVS: 3263 opcode = op_LZER 3264 case AFMOVD: 3265 opcode = op_LZDR 3266 } 3267 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3268 3269 case 68: // movw areg reg 3270 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3271 3272 case 69: // movw reg areg 3273 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3274 3275 case 70: // cmp reg reg 3276 if p.As == ACMPW || p.As == ACMPWU { 3277 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3278 } else { 3279 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3280 } 3281 3282 case 71: // cmp reg $constant 3283 v := c.vregoff(&p.To) 3284 switch p.As { 3285 case ACMP, ACMPW: 3286 if int64(int32(v)) != v { 3287 c.ctxt.Diag("%v overflows an int32", v) 3288 } 3289 case ACMPU, ACMPWU: 3290 if int64(uint32(v)) != v { 3291 c.ctxt.Diag("%v overflows a uint32", v) 3292 } 3293 } 3294 if p.As == ACMP && int64(int16(v)) == v { 3295 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm) 3296 } else if p.As == ACMPW && int64(int16(v)) == v { 3297 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm) 3298 } else { 3299 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm) 3300 } 3301 3302 case 72: // mov $constant mem 3303 v := c.regoff(&p.From) 3304 d := c.regoff(&p.To) 3305 r := p.To.Reg 3306 x := p.To.Index 3307 if r == 0 { 3308 r = o.param 3309 } 3310 if int32(int16(v)) == v && x == 0 { 3311 if d < 0 || d >= DISP12 { 3312 if r == REGTMP || r == REGTMP2 { 3313 zRIL(_a, op_AGFI, uint32(r), uint32(d), asm) 3314 } else { 3315 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3316 zRRE(op_AGR, REGTMP, uint32(r), asm) 3317 r = REGTMP 3318 } 3319 d = 0 3320 } 3321 var opcode uint32 3322 switch p.As { 3323 case AMOVD: 3324 opcode = op_MVGHI 3325 case AMOVW, AMOVWZ: 3326 opcode = op_MVHI 3327 case AMOVH, AMOVHZ: 3328 opcode = op_MVHHI 3329 case AMOVB, AMOVBZ: 3330 opcode = op_MVI 3331 } 3332 if opcode == op_MVI { 3333 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3334 } else { 3335 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3336 } 3337 } else { 3338 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm) 3339 if d < -DISP20/2 || d >= DISP20/2 { 3340 if r == REGTMP { 3341 zRIL(_a, op_AGFI, REGTMP, uint32(d), asm) 3342 } else { 3343 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3344 if x != 0 { 3345 zRRE(op_AGR, REGTMP, uint32(x), asm) 3346 } 3347 x = REGTMP 3348 } 3349 d = 0 3350 } 3351 zRXY(c.zopstore(p.As), REGTMP2, uint32(x), uint32(r), uint32(d), asm) 3352 } 3353 3354 case 73: // mov $constant addr (including relocation) 3355 v := c.regoff(&p.From) 3356 d := c.regoff(&p.To) 3357 a := uint32(0) 3358 if d&1 != 0 { 3359 d -= 1 3360 a = 1 3361 } 3362 zRIL(_b, op_LARL, REGTMP, uint32(d), asm) 3363 c.addrilreloc(p.To.Sym, int64(d)) 3364 if int32(int16(v)) == v { 3365 var opcode uint32 3366 switch p.As { 3367 case AMOVD: 3368 opcode = op_MVGHI 3369 case AMOVW, AMOVWZ: 3370 opcode = op_MVHI 3371 case AMOVH, AMOVHZ: 3372 opcode = op_MVHHI 3373 case AMOVB, AMOVBZ: 3374 opcode = op_MVI 3375 } 3376 if opcode == op_MVI { 3377 zSI(opcode, uint32(v), REGTMP, a, asm) 3378 } else { 3379 zSIL(opcode, REGTMP, a, uint32(v), asm) 3380 } 3381 } else { 3382 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm) 3383 zRXY(c.zopstore(p.As), REGTMP2, 0, REGTMP, a, asm) 3384 } 3385 3386 case 74: // mov reg addr (including relocation) 3387 i2 := c.regoff(&p.To) 3388 switch p.As { 3389 case AMOVD: 3390 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3391 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3392 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3393 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3394 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3395 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3396 zRIL(_b, op_LARL, REGTMP, 0, asm) 3397 adj := uint32(0) // adjustment needed for odd addresses 3398 if i2&1 != 0 { 3399 i2 -= 1 3400 adj = 1 3401 } 3402 zRX(op_STC, uint32(p.From.Reg), 0, REGTMP, adj, asm) 3403 case AFMOVD: 3404 zRIL(_b, op_LARL, REGTMP, 0, asm) 3405 zRX(op_STD, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3406 case AFMOVS: 3407 zRIL(_b, op_LARL, REGTMP, 0, asm) 3408 zRX(op_STE, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3409 } 3410 c.addrilreloc(p.To.Sym, int64(i2)) 3411 3412 case 75: // mov addr reg (including relocation) 3413 i2 := c.regoff(&p.From) 3414 switch p.As { 3415 case AMOVD: 3416 if i2&1 != 0 { 3417 zRIL(_b, op_LARL, REGTMP, 0, asm) 3418 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 1, asm) 3419 i2 -= 1 3420 } else { 3421 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3422 } 3423 case AMOVW: 3424 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3425 case AMOVWZ: 3426 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3427 case AMOVH: 3428 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3429 case AMOVHZ: 3430 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3431 case AMOVB, AMOVBZ: 3432 zRIL(_b, op_LARL, REGTMP, 0, asm) 3433 adj := uint32(0) // adjustment needed for odd addresses 3434 if i2&1 != 0 { 3435 i2 -= 1 3436 adj = 1 3437 } 3438 switch p.As { 3439 case AMOVB: 3440 zRXY(op_LGB, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3441 case AMOVBZ: 3442 zRXY(op_LLGC, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3443 } 3444 case AFMOVD: 3445 zRIL(_a, op_LARL, REGTMP, 0, asm) 3446 zRX(op_LD, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3447 case AFMOVS: 3448 zRIL(_a, op_LARL, REGTMP, 0, asm) 3449 zRX(op_LE, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3450 } 3451 c.addrilreloc(p.From.Sym, int64(i2)) 3452 3453 case 77: // syscall $constant 3454 if p.From.Offset > 255 || p.From.Offset < 1 { 3455 c.ctxt.Diag("illegal system call; system call number out of range: %v", p) 3456 zE(op_TRAP2, asm) // trap always 3457 } else { 3458 zI(op_SVC, uint32(p.From.Offset), asm) 3459 } 3460 3461 case 78: // undef 3462 // "An instruction consisting entirely of binary 0s is guaranteed 3463 // always to be an illegal instruction." 3464 *asm = append(*asm, 0, 0, 0, 0) 3465 3466 case 79: // compare and swap reg reg reg 3467 v := c.regoff(&p.To) 3468 if v < 0 { 3469 v = 0 3470 } 3471 if p.As == ACS { 3472 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3473 } else if p.As == ACSG { 3474 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3475 } 3476 3477 case 81: // sync 3478 zRR(op_BCR, 0xE, 0, asm) 3479 3480 case 82: // fixed to float conversion 3481 var opcode uint32 3482 switch p.As { 3483 default: 3484 log.Fatalf("unexpected opcode %v", p.As) 3485 case ACEFBRA: 3486 opcode = op_CEFBRA 3487 case ACDFBRA: 3488 opcode = op_CDFBRA 3489 case ACEGBRA: 3490 opcode = op_CEGBRA 3491 case ACDGBRA: 3492 opcode = op_CDGBRA 3493 case ACELFBR: 3494 opcode = op_CELFBR 3495 case ACDLFBR: 3496 opcode = op_CDLFBR 3497 case ACELGBR: 3498 opcode = op_CELGBR 3499 case ACDLGBR: 3500 opcode = op_CDLGBR 3501 } 3502 // set immediate operand M3 to 0 to use the default BFP rounding mode 3503 // (usually round to nearest, ties to even) 3504 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3505 // M4 is reserved and must be 0 3506 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3507 3508 case 83: // float to fixed conversion 3509 var opcode uint32 3510 switch p.As { 3511 default: 3512 log.Fatalf("unexpected opcode %v", p.As) 3513 case ACFEBRA: 3514 opcode = op_CFEBRA 3515 case ACFDBRA: 3516 opcode = op_CFDBRA 3517 case ACGEBRA: 3518 opcode = op_CGEBRA 3519 case ACGDBRA: 3520 opcode = op_CGDBRA 3521 case ACLFEBR: 3522 opcode = op_CLFEBR 3523 case ACLFDBR: 3524 opcode = op_CLFDBR 3525 case ACLGEBR: 3526 opcode = op_CLGEBR 3527 case ACLGDBR: 3528 opcode = op_CLGDBR 3529 } 3530 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3531 // M4 is reserved and must be 0 3532 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3533 3534 case 84: // storage-and-storage operations $length mem mem (length in From3) 3535 l := c.regoff(p.From3) 3536 if l < 1 || l > 256 { 3537 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3538 } 3539 if p.From.Index != 0 || p.To.Index != 0 { 3540 c.ctxt.Diag("cannot use index reg") 3541 } 3542 b1 := p.To.Reg 3543 b2 := p.From.Reg 3544 if b1 == 0 { 3545 b1 = o.param 3546 } 3547 if b2 == 0 { 3548 b2 = o.param 3549 } 3550 d1 := c.regoff(&p.To) 3551 d2 := c.regoff(&p.From) 3552 if d1 < 0 || d1 >= DISP12 { 3553 if b2 == REGTMP { 3554 c.ctxt.Diag("REGTMP conflict") 3555 } 3556 if b1 != REGTMP { 3557 zRRE(op_LGR, REGTMP, uint32(b1), asm) 3558 } 3559 zRIL(_a, op_AGFI, REGTMP, uint32(d1), asm) 3560 if d1 == d2 && b1 == b2 { 3561 d2 = 0 3562 b2 = REGTMP 3563 } 3564 d1 = 0 3565 b1 = REGTMP 3566 } 3567 if d2 < 0 || d2 >= DISP12 { 3568 if b1 == REGTMP2 { 3569 c.ctxt.Diag("REGTMP2 conflict") 3570 } 3571 if b2 != REGTMP2 { 3572 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3573 } 3574 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3575 d2 = 0 3576 b2 = REGTMP2 3577 } 3578 var opcode uint32 3579 switch p.As { 3580 default: 3581 c.ctxt.Diag("unexpected opcode %v", p.As) 3582 case AMVC: 3583 opcode = op_MVC 3584 case ACLC: 3585 opcode = op_CLC 3586 // swap operand order for CLC so that it matches CMP 3587 b1, b2 = b2, b1 3588 d1, d2 = d2, d1 3589 case AXC: 3590 opcode = op_XC 3591 case AOC: 3592 opcode = op_OC 3593 case ANC: 3594 opcode = op_NC 3595 } 3596 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3597 3598 case 85: // load address relative long 3599 v := c.regoff(&p.From) 3600 if p.From.Sym == nil { 3601 if (v & 1) != 0 { 3602 c.ctxt.Diag("cannot use LARL with odd offset: %v", v) 3603 } 3604 } else { 3605 c.addrilreloc(p.From.Sym, int64(v)) 3606 v = 0 3607 } 3608 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3609 3610 case 86: // load address 3611 d := c.vregoff(&p.From) 3612 x := p.From.Index 3613 b := p.From.Reg 3614 if b == 0 { 3615 b = o.param 3616 } 3617 switch p.As { 3618 case ALA: 3619 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3620 case ALAY: 3621 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3622 } 3623 3624 case 87: // execute relative long 3625 v := c.vregoff(&p.From) 3626 if p.From.Sym == nil { 3627 if v&1 != 0 { 3628 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3629 } 3630 } else { 3631 c.addrilreloc(p.From.Sym, v) 3632 v = 0 3633 } 3634 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3635 3636 case 88: // store clock 3637 var opcode uint32 3638 switch p.As { 3639 case ASTCK: 3640 opcode = op_STCK 3641 case ASTCKC: 3642 opcode = op_STCKC 3643 case ASTCKE: 3644 opcode = op_STCKE 3645 case ASTCKF: 3646 opcode = op_STCKF 3647 } 3648 v := c.vregoff(&p.To) 3649 r := int(p.To.Reg) 3650 if r == 0 { 3651 r = int(o.param) 3652 } 3653 zS(opcode, uint32(r), uint32(v), asm) 3654 3655 case 89: // compare and branch reg reg 3656 var v int32 3657 if p.Pcond != nil { 3658 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3659 } 3660 var opcode, opcode2 uint32 3661 switch p.As { 3662 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3663 opcode = op_CGRJ 3664 opcode2 = op_CGR 3665 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3666 opcode = op_CLGRJ 3667 opcode2 = op_CLGR 3668 } 3669 mask := c.branchMask(p) 3670 if int32(int16(v)) != v { 3671 zRRE(opcode2, uint32(p.From.Reg), uint32(p.Reg), asm) 3672 zRIL(_c, op_BRCL, mask, uint32(v-sizeRRE/2), asm) 3673 } else { 3674 zRIE(_b, opcode, uint32(p.From.Reg), uint32(p.Reg), uint32(v), 0, 0, mask, 0, asm) 3675 } 3676 3677 case 90: // compare and branch reg $constant 3678 var v int32 3679 if p.Pcond != nil { 3680 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3681 } 3682 var opcode, opcode2 uint32 3683 switch p.As { 3684 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3685 opcode = op_CGIJ 3686 opcode2 = op_CGFI 3687 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3688 opcode = op_CLGIJ 3689 opcode2 = op_CLGFI 3690 } 3691 mask := c.branchMask(p) 3692 if int32(int16(v)) != v { 3693 zRIL(_a, opcode2, uint32(p.From.Reg), uint32(c.regoff(p.From3)), asm) 3694 zRIL(_c, op_BRCL, mask, uint32(v-sizeRIL/2), asm) 3695 } else { 3696 zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(c.regoff(p.From3)), asm) 3697 } 3698 3699 case 93: // GOT lookup 3700 v := c.vregoff(&p.To) 3701 if v != 0 { 3702 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3703 } 3704 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3705 rel := obj.Addrel(c.cursym) 3706 rel.Off = int32(c.pc + 2) 3707 rel.Siz = 4 3708 rel.Sym = p.From.Sym 3709 rel.Type = obj.R_GOTPCREL 3710 rel.Add = 2 + int64(rel.Siz) 3711 3712 case 94: // TLS local exec model 3713 zRIL(_b, op_LARL, REGTMP, (sizeRIL+sizeRXY+sizeRI)>>1, asm) 3714 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3715 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 3716 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 3717 rel := obj.Addrel(c.cursym) 3718 rel.Off = int32(c.pc + sizeRIL + sizeRXY + sizeRI) 3719 rel.Siz = 8 3720 rel.Sym = p.From.Sym 3721 rel.Type = obj.R_TLS_LE 3722 rel.Add = 0 3723 3724 case 95: // TLS initial exec model 3725 // Assembly | Relocation symbol | Done Here? 3726 // -------------------------------------------------------------- 3727 // ear %r11, %a0 | | 3728 // sllg %r11, %r11, 32 | | 3729 // ear %r11, %a1 | | 3730 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 3731 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 3732 // la %r10, 0(%r10, %r11) | | 3733 // -------------------------------------------------------------- 3734 3735 // R_390_TLS_IEENT 3736 zRIL(_b, op_LARL, REGTMP, 0, asm) 3737 ieent := obj.Addrel(c.cursym) 3738 ieent.Off = int32(c.pc + 2) 3739 ieent.Siz = 4 3740 ieent.Sym = p.From.Sym 3741 ieent.Type = obj.R_TLS_IE 3742 ieent.Add = 2 + int64(ieent.Siz) 3743 3744 // R_390_TLS_LOAD 3745 zRXY(op_LGF, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3746 // TODO(mundaym): add R_390_TLS_LOAD relocation here 3747 // not strictly required but might allow the linker to optimize 3748 3749 case 96: // clear macro 3750 length := c.vregoff(&p.From) 3751 offset := c.vregoff(&p.To) 3752 reg := p.To.Reg 3753 if reg == 0 { 3754 reg = o.param 3755 } 3756 if length <= 0 { 3757 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 3758 } 3759 for length > 0 { 3760 if offset < 0 || offset >= DISP12 { 3761 if offset >= -DISP20/2 && offset < DISP20/2 { 3762 zRXY(op_LAY, REGTMP, uint32(reg), 0, uint32(offset), asm) 3763 } else { 3764 if reg != REGTMP { 3765 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3766 } 3767 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3768 } 3769 reg = REGTMP 3770 offset = 0 3771 } 3772 size := length 3773 if size > 256 { 3774 size = 256 3775 } 3776 3777 switch size { 3778 case 1: 3779 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 3780 case 2: 3781 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 3782 case 4: 3783 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 3784 case 8: 3785 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 3786 default: 3787 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 3788 } 3789 3790 length -= size 3791 offset += size 3792 } 3793 3794 case 97: // store multiple 3795 rstart := p.From.Reg 3796 rend := p.Reg 3797 offset := c.regoff(&p.To) 3798 reg := p.To.Reg 3799 if reg == 0 { 3800 reg = o.param 3801 } 3802 if offset < -DISP20/2 || offset >= DISP20/2 { 3803 if reg != REGTMP { 3804 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3805 } 3806 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3807 reg = REGTMP 3808 offset = 0 3809 } 3810 switch p.As { 3811 case ASTMY: 3812 if offset >= 0 && offset < DISP12 { 3813 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3814 } else { 3815 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3816 } 3817 case ASTMG: 3818 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3819 } 3820 3821 case 98: // load multiple 3822 rstart := p.Reg 3823 rend := p.To.Reg 3824 offset := c.regoff(&p.From) 3825 reg := p.From.Reg 3826 if reg == 0 { 3827 reg = o.param 3828 } 3829 if offset < -DISP20/2 || offset >= DISP20/2 { 3830 if reg != REGTMP { 3831 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3832 } 3833 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3834 reg = REGTMP 3835 offset = 0 3836 } 3837 switch p.As { 3838 case ALMY: 3839 if offset >= 0 && offset < DISP12 { 3840 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3841 } else { 3842 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3843 } 3844 case ALMG: 3845 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3846 } 3847 3848 case 99: // interlocked load and op 3849 if p.To.Index != 0 { 3850 c.ctxt.Diag("cannot use indexed address") 3851 } 3852 offset := c.regoff(&p.To) 3853 if offset < -DISP20/2 || offset >= DISP20/2 { 3854 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset) 3855 } 3856 var opcode uint32 3857 switch p.As { 3858 case ALAA: 3859 opcode = op_LAA 3860 case ALAAG: 3861 opcode = op_LAAG 3862 case ALAAL: 3863 opcode = op_LAAL 3864 case ALAALG: 3865 opcode = op_LAALG 3866 case ALAN: 3867 opcode = op_LAN 3868 case ALANG: 3869 opcode = op_LANG 3870 case ALAX: 3871 opcode = op_LAX 3872 case ALAXG: 3873 opcode = op_LAXG 3874 case ALAO: 3875 opcode = op_LAO 3876 case ALAOG: 3877 opcode = op_LAOG 3878 } 3879 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm) 3880 3881 case 100: // VRX STORE 3882 op, m3, _ := vop(p.As) 3883 if p.From3 != nil { 3884 m3 = uint32(c.vregoff(p.From3)) 3885 } 3886 b2 := p.To.Reg 3887 if b2 == 0 { 3888 b2 = o.param 3889 } 3890 d2 := uint32(c.vregoff(&p.To)) 3891 zVRX(op, uint32(p.From.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3892 3893 case 101: // VRX LOAD 3894 op, m3, _ := vop(p.As) 3895 if p.From3 != nil { 3896 m3 = uint32(c.vregoff(p.From3)) 3897 } 3898 b2 := p.From.Reg 3899 if b2 == 0 { 3900 b2 = o.param 3901 } 3902 d2 := uint32(c.vregoff(&p.From)) 3903 zVRX(op, uint32(p.To.Reg), uint32(p.From.Index), uint32(b2), d2, m3, asm) 3904 3905 case 102: // VRV SCATTER 3906 op, m3, _ := vop(p.As) 3907 if p.From3 != nil { 3908 m3 = uint32(c.vregoff(p.From3)) 3909 } 3910 b2 := p.To.Reg 3911 if b2 == 0 { 3912 b2 = o.param 3913 } 3914 d2 := uint32(c.vregoff(&p.To)) 3915 zVRV(op, uint32(p.From.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3916 3917 case 103: // VRV GATHER 3918 op, m3, _ := vop(p.As) 3919 if p.From3 != nil { 3920 m3 = uint32(c.vregoff(p.From3)) 3921 } 3922 b2 := p.From.Reg 3923 if b2 == 0 { 3924 b2 = o.param 3925 } 3926 d2 := uint32(c.vregoff(&p.From)) 3927 zVRV(op, uint32(p.To.Reg), uint32(p.From.Index), uint32(b2), d2, m3, asm) 3928 3929 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 3930 op, m4, _ := vop(p.As) 3931 fr := p.Reg 3932 if fr == 0 { 3933 fr = p.To.Reg 3934 } 3935 bits := uint32(c.vregoff(&p.From)) 3936 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 3937 3938 case 105: // VRS STORE MULTIPLE 3939 op, _, _ := vop(p.As) 3940 offset := uint32(c.vregoff(&p.To)) 3941 reg := p.To.Reg 3942 if reg == 0 { 3943 reg = o.param 3944 } 3945 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 3946 3947 case 106: // VRS LOAD MULTIPLE 3948 op, _, _ := vop(p.As) 3949 offset := uint32(c.vregoff(&p.From)) 3950 reg := p.From.Reg 3951 if reg == 0 { 3952 reg = o.param 3953 } 3954 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 3955 3956 case 107: // VRS STORE WITH LENGTH 3957 op, _, _ := vop(p.As) 3958 offset := uint32(c.vregoff(&p.To)) 3959 reg := p.To.Reg 3960 if reg == 0 { 3961 reg = o.param 3962 } 3963 zVRS(op, uint32(p.From.Reg), uint32(p.From3.Reg), uint32(reg), offset, 0, asm) 3964 3965 case 108: // VRS LOAD WITH LENGTH 3966 op, _, _ := vop(p.As) 3967 offset := uint32(c.vregoff(&p.From)) 3968 reg := p.From.Reg 3969 if reg == 0 { 3970 reg = o.param 3971 } 3972 zVRS(op, uint32(p.To.Reg), uint32(p.From3.Reg), uint32(reg), offset, 0, asm) 3973 3974 case 109: // VRI-a 3975 op, m3, _ := vop(p.As) 3976 i2 := uint32(c.vregoff(&p.From)) 3977 switch p.As { 3978 case AVZERO: 3979 i2 = 0 3980 case AVONE: 3981 i2 = 0xffff 3982 } 3983 if p.From3 != nil { 3984 m3 = uint32(c.vregoff(p.From3)) 3985 } 3986 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 3987 3988 case 110: 3989 op, m4, _ := vop(p.As) 3990 i2 := uint32(c.vregoff(p.From3)) 3991 i3 := uint32(c.vregoff(&p.From)) 3992 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 3993 3994 case 111: 3995 op, m4, _ := vop(p.As) 3996 i2 := uint32(c.vregoff(&p.From)) 3997 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 3998 3999 case 112: 4000 op, m5, _ := vop(p.As) 4001 i4 := uint32(c.vregoff(p.From3)) 4002 zVRId(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), i4, m5, asm) 4003 4004 case 113: 4005 op, m4, _ := vop(p.As) 4006 m5 := singleElementMask(p.As) 4007 i3 := uint32(c.vregoff(&p.From)) 4008 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 4009 4010 case 114: // VRR-a 4011 op, m3, m5 := vop(p.As) 4012 m4 := singleElementMask(p.As) 4013 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 4014 4015 case 115: // VRR-a COMPARE 4016 op, m3, m5 := vop(p.As) 4017 m4 := singleElementMask(p.As) 4018 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 4019 4020 case 116: // VRR-a 4021 4022 case 117: // VRR-b 4023 op, m4, m5 := vop(p.As) 4024 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 4025 4026 case 118: // VRR-c 4027 op, m4, m6 := vop(p.As) 4028 m5 := singleElementMask(p.As) 4029 v3 := p.Reg 4030 if v3 == 0 { 4031 v3 = p.To.Reg 4032 } 4033 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 4034 4035 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 4036 op, m4, m6 := vop(p.As) 4037 m5 := singleElementMask(p.As) 4038 v2 := p.Reg 4039 if v2 == 0 { 4040 v2 = p.To.Reg 4041 } 4042 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 4043 4044 case 120: // VRR-d 4045 op, m6, _ := vop(p.As) 4046 m5 := singleElementMask(p.As) 4047 v1 := uint32(p.To.Reg) 4048 v2 := uint32(p.From3.Reg) 4049 v3 := uint32(p.From.Reg) 4050 v4 := uint32(p.Reg) 4051 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 4052 4053 case 121: // VRR-e 4054 op, m6, _ := vop(p.As) 4055 m5 := singleElementMask(p.As) 4056 v1 := uint32(p.To.Reg) 4057 v2 := uint32(p.From3.Reg) 4058 v3 := uint32(p.From.Reg) 4059 v4 := uint32(p.Reg) 4060 zVRRe(op, v1, v2, v3, m6, m5, v4, asm) 4061 4062 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 4063 op, _, _ := vop(p.As) 4064 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 4065 4066 case 123: // VPDI $m4, V2, V3, V1 4067 op, _, _ := vop(p.As) 4068 m4 := c.regoff(p.From3) 4069 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), 0, 0, uint32(m4), asm) 4070 } 4071 } 4072 4073 func (c *ctxtz) vregoff(a *obj.Addr) int64 { 4074 c.instoffset = 0 4075 if a != nil { 4076 c.aclass(a) 4077 } 4078 return c.instoffset 4079 } 4080 4081 func (c *ctxtz) regoff(a *obj.Addr) int32 { 4082 return int32(c.vregoff(a)) 4083 } 4084 4085 // zopload returns the RXY op for the given load 4086 func (c *ctxtz) zopload(a obj.As) uint32 { 4087 switch a { 4088 // fixed point load 4089 case AMOVD: 4090 return op_LG 4091 case AMOVW: 4092 return op_LGF 4093 case AMOVWZ: 4094 return op_LLGF 4095 case AMOVH: 4096 return op_LGH 4097 case AMOVHZ: 4098 return op_LLGH 4099 case AMOVB: 4100 return op_LGB 4101 case AMOVBZ: 4102 return op_LLGC 4103 4104 // floating point load 4105 case AFMOVD: 4106 return op_LDY 4107 case AFMOVS: 4108 return op_LEY 4109 4110 // byte reversed load 4111 case AMOVDBR: 4112 return op_LRVG 4113 case AMOVWBR: 4114 return op_LRV 4115 case AMOVHBR: 4116 return op_LRVH 4117 } 4118 4119 c.ctxt.Diag("unknown store opcode %v", a) 4120 return 0 4121 } 4122 4123 // zopstore returns the RXY op for the given store 4124 func (c *ctxtz) zopstore(a obj.As) uint32 { 4125 switch a { 4126 // fixed point store 4127 case AMOVD: 4128 return op_STG 4129 case AMOVW, AMOVWZ: 4130 return op_STY 4131 case AMOVH, AMOVHZ: 4132 return op_STHY 4133 case AMOVB, AMOVBZ: 4134 return op_STCY 4135 4136 // floating point store 4137 case AFMOVD: 4138 return op_STDY 4139 case AFMOVS: 4140 return op_STEY 4141 4142 // byte reversed store 4143 case AMOVDBR: 4144 return op_STRVG 4145 case AMOVWBR: 4146 return op_STRV 4147 case AMOVHBR: 4148 return op_STRVH 4149 } 4150 4151 c.ctxt.Diag("unknown store opcode %v", a) 4152 return 0 4153 } 4154 4155 // zoprre returns the RRE op for the given a 4156 func (c *ctxtz) zoprre(a obj.As) uint32 { 4157 switch a { 4158 case ACMP: 4159 return op_CGR 4160 case ACMPU: 4161 return op_CLGR 4162 case AFCMPO: //ordered 4163 return op_KDBR 4164 case AFCMPU: //unordered 4165 return op_CDBR 4166 case ACEBR: 4167 return op_CEBR 4168 } 4169 c.ctxt.Diag("unknown rre opcode %v", a) 4170 return 0 4171 } 4172 4173 // zoprr returns the RR op for the given a 4174 func (c *ctxtz) zoprr(a obj.As) uint32 { 4175 switch a { 4176 case ACMPW: 4177 return op_CR 4178 case ACMPWU: 4179 return op_CLR 4180 } 4181 c.ctxt.Diag("unknown rr opcode %v", a) 4182 return 0 4183 } 4184 4185 // zopril returns the RIL op for the given a 4186 func (c *ctxtz) zopril(a obj.As) uint32 { 4187 switch a { 4188 case ACMP: 4189 return op_CGFI 4190 case ACMPU: 4191 return op_CLGFI 4192 case ACMPW: 4193 return op_CFI 4194 case ACMPWU: 4195 return op_CLFI 4196 } 4197 c.ctxt.Diag("unknown ril opcode %v", a) 4198 return 0 4199 } 4200 4201 // z instructions sizes 4202 const ( 4203 sizeE = 2 4204 sizeI = 2 4205 sizeIE = 4 4206 sizeMII = 6 4207 sizeRI = 4 4208 sizeRI1 = 4 4209 sizeRI2 = 4 4210 sizeRI3 = 4 4211 sizeRIE = 6 4212 sizeRIE1 = 6 4213 sizeRIE2 = 6 4214 sizeRIE3 = 6 4215 sizeRIE4 = 6 4216 sizeRIE5 = 6 4217 sizeRIE6 = 6 4218 sizeRIL = 6 4219 sizeRIL1 = 6 4220 sizeRIL2 = 6 4221 sizeRIL3 = 6 4222 sizeRIS = 6 4223 sizeRR = 2 4224 sizeRRD = 4 4225 sizeRRE = 4 4226 sizeRRF = 4 4227 sizeRRF1 = 4 4228 sizeRRF2 = 4 4229 sizeRRF3 = 4 4230 sizeRRF4 = 4 4231 sizeRRF5 = 4 4232 sizeRRR = 2 4233 sizeRRS = 6 4234 sizeRS = 4 4235 sizeRS1 = 4 4236 sizeRS2 = 4 4237 sizeRSI = 4 4238 sizeRSL = 6 4239 sizeRSY = 6 4240 sizeRSY1 = 6 4241 sizeRSY2 = 6 4242 sizeRX = 4 4243 sizeRX1 = 4 4244 sizeRX2 = 4 4245 sizeRXE = 6 4246 sizeRXF = 6 4247 sizeRXY = 6 4248 sizeRXY1 = 6 4249 sizeRXY2 = 6 4250 sizeS = 4 4251 sizeSI = 4 4252 sizeSIL = 6 4253 sizeSIY = 6 4254 sizeSMI = 6 4255 sizeSS = 6 4256 sizeSS1 = 6 4257 sizeSS2 = 6 4258 sizeSS3 = 6 4259 sizeSS4 = 6 4260 sizeSS5 = 6 4261 sizeSS6 = 6 4262 sizeSSE = 6 4263 sizeSSF = 6 4264 ) 4265 4266 // instruction format variations 4267 type form int 4268 4269 const ( 4270 _a form = iota 4271 _b 4272 _c 4273 _d 4274 _e 4275 _f 4276 ) 4277 4278 func zE(op uint32, asm *[]byte) { 4279 *asm = append(*asm, uint8(op>>8), uint8(op)) 4280 } 4281 4282 func zI(op, i1 uint32, asm *[]byte) { 4283 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4284 } 4285 4286 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4287 *asm = append(*asm, 4288 uint8(op>>8), 4289 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4290 uint8(ri2), 4291 uint8(ri3>>16), 4292 uint8(ri3>>8), 4293 uint8(ri3)) 4294 } 4295 4296 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4297 *asm = append(*asm, 4298 uint8(op>>8), 4299 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4300 uint8(i2_ri2>>8), 4301 uint8(i2_ri2)) 4302 } 4303 4304 // Expected argument values for the instruction formats. 4305 // 4306 // Format a1 a2 a3 a4 a5 a6 a7 4307 // ------------------------------------ 4308 // a r1, 0, i2, 0, 0, m3, 0 4309 // b r1, r2, ri4, 0, 0, m3, 0 4310 // c r1, m3, ri4, 0, 0, 0, i2 4311 // d r1, r3, i2, 0, 0, 0, 0 4312 // e r1, r3, ri2, 0, 0, 0, 0 4313 // f r1, r2, 0, i3, i4, 0, i5 4314 // g r1, m3, i2, 0, 0, 0, 0 4315 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4316 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4317 4318 switch f { 4319 default: 4320 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4321 case _f: 4322 *asm = append(*asm, uint8(i3), uint8(i4)) 4323 } 4324 4325 switch f { 4326 case _a, _b: 4327 *asm = append(*asm, uint8(m3)<<4) 4328 default: 4329 *asm = append(*asm, uint8(i2_i5)) 4330 } 4331 4332 *asm = append(*asm, uint8(op)) 4333 } 4334 4335 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4336 if f == _a || f == _b { 4337 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4338 } 4339 *asm = append(*asm, 4340 uint8(op>>8), 4341 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4342 uint8(i2_ri2>>24), 4343 uint8(i2_ri2>>16), 4344 uint8(i2_ri2>>8), 4345 uint8(i2_ri2)) 4346 } 4347 4348 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4349 *asm = append(*asm, 4350 uint8(op>>8), 4351 (uint8(r1)<<4)|uint8(m3&0x0F), 4352 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4353 uint8(d4), 4354 uint8(i2), 4355 uint8(op)) 4356 } 4357 4358 func zRR(op, r1, r2 uint32, asm *[]byte) { 4359 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4360 } 4361 4362 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4363 *asm = append(*asm, 4364 uint8(op>>8), 4365 uint8(op), 4366 uint8(r1)<<4, 4367 (uint8(r3)<<4)|uint8(r2&0x0F)) 4368 } 4369 4370 func zRRE(op, r1, r2 uint32, asm *[]byte) { 4371 *asm = append(*asm, 4372 uint8(op>>8), 4373 uint8(op), 4374 0, 4375 (uint8(r1)<<4)|uint8(r2&0x0F)) 4376 } 4377 4378 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4379 *asm = append(*asm, 4380 uint8(op>>8), 4381 uint8(op), 4382 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4383 (uint8(r1)<<4)|uint8(r2&0x0F)) 4384 } 4385 4386 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4387 *asm = append(*asm, 4388 uint8(op>>8), 4389 (uint8(r1)<<4)|uint8(r2&0x0F), 4390 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4391 uint8(d4), 4392 uint8(m3)<<4, 4393 uint8(op)) 4394 } 4395 4396 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4397 *asm = append(*asm, 4398 uint8(op>>8), 4399 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4400 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4401 uint8(d2)) 4402 } 4403 4404 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4405 *asm = append(*asm, 4406 uint8(op>>8), 4407 (uint8(r1)<<4)|uint8(r3&0x0F), 4408 uint8(ri2>>8), 4409 uint8(ri2)) 4410 } 4411 4412 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4413 *asm = append(*asm, 4414 uint8(op>>8), 4415 uint8(l1), 4416 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4417 uint8(d2), 4418 uint8(op)) 4419 } 4420 4421 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4422 dl2 := uint16(d2) & 0x0FFF 4423 *asm = append(*asm, 4424 uint8(op>>8), 4425 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4426 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4427 uint8(dl2), 4428 uint8(d2>>12), 4429 uint8(op)) 4430 } 4431 4432 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4433 *asm = append(*asm, 4434 uint8(op>>8), 4435 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4436 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4437 uint8(d2)) 4438 } 4439 4440 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4441 *asm = append(*asm, 4442 uint8(op>>8), 4443 (uint8(r1)<<4)|uint8(x2&0x0F), 4444 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4445 uint8(d2), 4446 uint8(m3)<<4, 4447 uint8(op)) 4448 } 4449 4450 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4451 *asm = append(*asm, 4452 uint8(op>>8), 4453 (uint8(r3)<<4)|uint8(x2&0x0F), 4454 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4455 uint8(d2), 4456 uint8(m1)<<4, 4457 uint8(op)) 4458 } 4459 4460 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4461 dl2 := uint16(d2) & 0x0FFF 4462 *asm = append(*asm, 4463 uint8(op>>8), 4464 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4465 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4466 uint8(dl2), 4467 uint8(d2>>12), 4468 uint8(op)) 4469 } 4470 4471 func zS(op, b2, d2 uint32, asm *[]byte) { 4472 *asm = append(*asm, 4473 uint8(op>>8), 4474 uint8(op), 4475 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4476 uint8(d2)) 4477 } 4478 4479 func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4480 *asm = append(*asm, 4481 uint8(op>>8), 4482 uint8(i2), 4483 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4484 uint8(d1)) 4485 } 4486 4487 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4488 *asm = append(*asm, 4489 uint8(op>>8), 4490 uint8(op), 4491 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4492 uint8(d1), 4493 uint8(i2>>8), 4494 uint8(i2)) 4495 } 4496 4497 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4498 dl1 := uint16(d1) & 0x0FFF 4499 *asm = append(*asm, 4500 uint8(op>>8), 4501 uint8(i2), 4502 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4503 uint8(dl1), 4504 uint8(d1>>12), 4505 uint8(op)) 4506 } 4507 4508 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4509 *asm = append(*asm, 4510 uint8(op>>8), 4511 uint8(m1)<<4, 4512 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4513 uint8(d3), 4514 uint8(ri2>>8), 4515 uint8(ri2)) 4516 } 4517 4518 // Expected argument values for the instruction formats. 4519 // 4520 // Format a1 a2 a3 a4 a5 a6 4521 // ------------------------------- 4522 // a l1, 0, b1, d1, b2, d2 4523 // b l1, l2, b1, d1, b2, d2 4524 // c l1, i3, b1, d1, b2, d2 4525 // d r1, r3, b1, d1, b2, d2 4526 // e r1, r3, b2, d2, b4, d4 4527 // f 0, l2, b1, d1, b2, d2 4528 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4529 *asm = append(*asm, uint8(op>>8)) 4530 4531 switch f { 4532 case _a: 4533 *asm = append(*asm, uint8(l1_r1)) 4534 case _b, _c, _d, _e: 4535 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4536 case _f: 4537 *asm = append(*asm, uint8(l2_i3_r3)) 4538 } 4539 4540 *asm = append(*asm, 4541 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4542 uint8(d1_d2), 4543 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4544 uint8(d2_d4)) 4545 } 4546 4547 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4548 *asm = append(*asm, 4549 uint8(op>>8), 4550 uint8(op), 4551 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4552 uint8(d1), 4553 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4554 uint8(d2)) 4555 } 4556 4557 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4558 *asm = append(*asm, 4559 uint8(op>>8), 4560 (uint8(r3)<<4)|(uint8(op)&0x0F), 4561 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4562 uint8(d1), 4563 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4564 uint8(d2)) 4565 } 4566 4567 func rxb(va, vb, vc, vd uint32) uint8 { 4568 mask := uint8(0) 4569 if va >= REG_V16 && va <= REG_V31 { 4570 mask |= 0x8 4571 } 4572 if vb >= REG_V16 && vb <= REG_V31 { 4573 mask |= 0x4 4574 } 4575 if vc >= REG_V16 && vc <= REG_V31 { 4576 mask |= 0x2 4577 } 4578 if vd >= REG_V16 && vd <= REG_V31 { 4579 mask |= 0x1 4580 } 4581 return mask 4582 } 4583 4584 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 4585 *asm = append(*asm, 4586 uint8(op>>8), 4587 (uint8(v1)<<4)|(uint8(x2)&0xf), 4588 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4589 uint8(d2), 4590 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4591 uint8(op)) 4592 } 4593 4594 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 4595 *asm = append(*asm, 4596 uint8(op>>8), 4597 (uint8(v1)<<4)|(uint8(v2)&0xf), 4598 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4599 uint8(d2), 4600 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4601 uint8(op)) 4602 } 4603 4604 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 4605 *asm = append(*asm, 4606 uint8(op>>8), 4607 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 4608 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4609 uint8(d2), 4610 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 4611 uint8(op)) 4612 } 4613 4614 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 4615 *asm = append(*asm, 4616 uint8(op>>8), 4617 (uint8(v1)<<4)|(uint8(v2)&0xf), 4618 0, 4619 (uint8(m5)<<4)|(uint8(m4)&0xf), 4620 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4621 uint8(op)) 4622 } 4623 4624 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 4625 *asm = append(*asm, 4626 uint8(op>>8), 4627 (uint8(v1)<<4)|(uint8(v2)&0xf), 4628 uint8(v3)<<4, 4629 uint8(m5)<<4, 4630 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4631 uint8(op)) 4632 } 4633 4634 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 4635 *asm = append(*asm, 4636 uint8(op>>8), 4637 (uint8(v1)<<4)|(uint8(v2)&0xf), 4638 uint8(v3)<<4, 4639 (uint8(m6)<<4)|(uint8(m5)&0xf), 4640 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4641 uint8(op)) 4642 } 4643 4644 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 4645 *asm = append(*asm, 4646 uint8(op>>8), 4647 (uint8(v1)<<4)|(uint8(v2)&0xf), 4648 (uint8(v3)<<4)|(uint8(m5)&0xf), 4649 uint8(m6)<<4, 4650 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4651 uint8(op)) 4652 } 4653 4654 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 4655 *asm = append(*asm, 4656 uint8(op>>8), 4657 (uint8(v1)<<4)|(uint8(v2)&0xf), 4658 (uint8(v3)<<4)|(uint8(m6)&0xf), 4659 uint8(m5), 4660 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4661 uint8(op)) 4662 } 4663 4664 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 4665 *asm = append(*asm, 4666 uint8(op>>8), 4667 (uint8(v1)<<4)|(uint8(r2)&0xf), 4668 uint8(r3)<<4, 4669 0, 4670 rxb(v1, 0, 0, 0), 4671 uint8(op)) 4672 } 4673 4674 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 4675 *asm = append(*asm, 4676 uint8(op>>8), 4677 uint8(v1)<<4, 4678 uint8(i2>>8), 4679 uint8(i2), 4680 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4681 uint8(op)) 4682 } 4683 4684 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 4685 *asm = append(*asm, 4686 uint8(op>>8), 4687 uint8(v1)<<4, 4688 uint8(i2), 4689 uint8(i3), 4690 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 4691 uint8(op)) 4692 } 4693 4694 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 4695 *asm = append(*asm, 4696 uint8(op>>8), 4697 (uint8(v1)<<4)|(uint8(v3)&0xf), 4698 uint8(i2>>8), 4699 uint8(i2), 4700 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 4701 uint8(op)) 4702 } 4703 4704 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 4705 *asm = append(*asm, 4706 uint8(op>>8), 4707 (uint8(v1)<<4)|(uint8(v2)&0xf), 4708 uint8(v3)<<4, 4709 uint8(i4), 4710 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 4711 uint8(op)) 4712 } 4713 4714 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 4715 *asm = append(*asm, 4716 uint8(op>>8), 4717 (uint8(v1)<<4)|(uint8(v2)&0xf), 4718 uint8(i3>>4), 4719 (uint8(i3)<<4)|(uint8(m5)&0xf), 4720 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 4721 uint8(op)) 4722 }