github.com/tinygo-org/tinygo@v0.31.3-0.20240404173401-90b0bf646c27/src/device/arm/scb.go (about) 1 // Hand created file. DO NOT DELETE. 2 // Cortex-M System Control Block-related definitions. 3 4 //go:build cortexm 5 6 package arm 7 8 import ( 9 "runtime/volatile" 10 "unsafe" 11 ) 12 13 const SCB_BASE = SCS_BASE + 0x0D00 14 15 // System Control Block (SCB) 16 // 17 // SCB_Type provides the definitions for the System Control Block Registers. 18 type SCB_Type struct { 19 CPUID volatile.Register32 // 0xD00: CPUID Base Register 20 ICSR volatile.Register32 // 0xD04: Interrupt Control and State Register 21 VTOR volatile.Register32 // 0xD08: Vector Table Offset Register 22 AIRCR volatile.Register32 // 0xD0C: Application Interrupt and Reset Control Register 23 SCR volatile.Register32 // 0xD10: System Control Register 24 CCR volatile.Register32 // 0xD14: Configuration and Control Register 25 SHPR1 volatile.Register32 // 0xD18: System Handler Priority Register 1 (Cortex-M3/M33/M4/M7 only) 26 SHPR2 volatile.Register32 // 0xD1C: System Handler Priority Register 2 27 SHPR3 volatile.Register32 // 0xD20: System Handler Priority Register 3 28 // the following are only applicable for Cortex-M3/M33/M4/M7 29 SHCSR volatile.Register32 // 0xD24: System Handler Control and State Register 30 CFSR volatile.Register32 // 0xD28: Configurable Fault Status Register 31 HFSR volatile.Register32 // 0xD2C: HardFault Status Register 32 DFSR volatile.Register32 // 0xD30: Debug Fault Status Register 33 MMFAR volatile.Register32 // 0xD34: MemManage Fault Address Register 34 BFAR volatile.Register32 // 0xD38: BusFault Address Register 35 AFSR volatile.Register32 // 0xD3C: Auxiliary Fault Status Register 36 PFR [2]volatile.Register32 // 0xD40: Processor Feature Register 37 DFR volatile.Register32 // 0xD48: Debug Feature Register 38 ADR volatile.Register32 // 0xD4C: Auxiliary Feature Register 39 MMFR [4]volatile.Register32 // 0xD50: Memory Model Feature Register 40 ISAR [5]volatile.Register32 // 0xD60: Instruction Set Attributes Register 41 _ [5]uint32 // reserved 42 CPACR volatile.Register32 // 0xD88: Coprocessor Access Control Register 43 44 } 45 46 var SCB = (*SCB_Type)(unsafe.Pointer(uintptr(SCB_BASE))) 47 48 // SystemReset performs a hard system reset. 49 func SystemReset() { 50 SCB.AIRCR.Set((0x5FA << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk) 51 for { 52 Asm("wfi") 53 } 54 } 55 56 const ( 57 // CPUID: CPUID Base Register 58 SCB_CPUID_REVISION_Pos = 0x0 // Position of REVISION field. 59 SCB_CPUID_REVISION_Msk = 0xf // Bit mask of REVISION field. 60 SCB_CPUID_PARTNO_Pos = 0x4 // Position of PARTNO field. 61 SCB_CPUID_PARTNO_Msk = 0xfff0 // Bit mask of PARTNO field. 62 SCB_CPUID_ARCHITECTURE_Pos = 0x10 // Position of ARCHITECTURE field. 63 SCB_CPUID_ARCHITECTURE_Msk = 0xf0000 // Bit mask of ARCHITECTURE field. 64 SCB_CPUID_VARIANT_Pos = 0x14 // Position of VARIANT field. 65 SCB_CPUID_VARIANT_Msk = 0xf00000 // Bit mask of VARIANT field. 66 SCB_CPUID_IMPLEMENTER_Pos = 0x18 // Position of IMPLEMENTER field. 67 SCB_CPUID_IMPLEMENTER_Msk = 0xff000000 // Bit mask of IMPLEMENTER field. 68 69 // ICSR: Interrupt Control and State Register 70 SCB_ICSR_VECTACTIVE_Pos = 0x0 // Position of VECTACTIVE field. 71 SCB_ICSR_VECTACTIVE_Msk = 0x1ff // Bit mask of VECTACTIVE field. 72 SCB_ICSR_RETTOBASE_Pos = 0xb // Position of RETTOBASE field. 73 SCB_ICSR_RETTOBASE_Msk = 0x800 // Bit mask of RETTOBASE field. 74 SCB_ICSR_RETTOBASE = 0x800 // Bit RETTOBASE. 75 SCB_ICSR_RETTOBASE_RETTOBASE_0 = 0x0 // there are preempted active exceptions to execute 76 SCB_ICSR_RETTOBASE_RETTOBASE_1 = 0x1 // there are no active exceptions, or the currently-executing exception is the only active exception 77 SCB_ICSR_VECTPENDING_Pos = 0xc // Position of VECTPENDING field. 78 SCB_ICSR_VECTPENDING_Msk = 0x1ff000 // Bit mask of VECTPENDING field. 79 SCB_ICSR_ISRPENDING_Pos = 0x16 // Position of ISRPENDING field. 80 SCB_ICSR_ISRPENDING_Msk = 0x400000 // Bit mask of ISRPENDING field. 81 SCB_ICSR_ISRPENDING = 0x400000 // Bit ISRPENDING. 82 SCB_ICSR_ISRPENDING_ISRPENDING_0 = 0x0 // No external interrupt pending. 83 SCB_ICSR_ISRPENDING_ISRPENDING_1 = 0x1 // External interrupt pending. 84 SCB_ICSR_PENDSTCLR_Pos = 0x19 // Position of PENDSTCLR field. 85 SCB_ICSR_PENDSTCLR_Msk = 0x2000000 // Bit mask of PENDSTCLR field. 86 SCB_ICSR_PENDSTCLR = 0x2000000 // Bit PENDSTCLR. 87 SCB_ICSR_PENDSTCLR_PENDSTCLR_0 = 0x0 // no effect 88 SCB_ICSR_PENDSTCLR_PENDSTCLR_1 = 0x1 // removes the pending state from the SysTick exception 89 SCB_ICSR_PENDSTSET_Pos = 0x1a // Position of PENDSTSET field. 90 SCB_ICSR_PENDSTSET_Msk = 0x4000000 // Bit mask of PENDSTSET field. 91 SCB_ICSR_PENDSTSET = 0x4000000 // Bit PENDSTSET. 92 SCB_ICSR_PENDSTSET_PENDSTSET_0 = 0x0 // write: no effect; read: SysTick exception is not pending 93 SCB_ICSR_PENDSTSET_PENDSTSET_1 = 0x1 // write: changes SysTick exception state to pending; read: SysTick exception is pending 94 SCB_ICSR_PENDSVCLR_Pos = 0x1b // Position of PENDSVCLR field. 95 SCB_ICSR_PENDSVCLR_Msk = 0x8000000 // Bit mask of PENDSVCLR field. 96 SCB_ICSR_PENDSVCLR = 0x8000000 // Bit PENDSVCLR. 97 SCB_ICSR_PENDSVCLR_PENDSVCLR_0 = 0x0 // no effect 98 SCB_ICSR_PENDSVCLR_PENDSVCLR_1 = 0x1 // removes the pending state from the PendSV exception 99 SCB_ICSR_PENDSVSET_Pos = 0x1c // Position of PENDSVSET field. 100 SCB_ICSR_PENDSVSET_Msk = 0x10000000 // Bit mask of PENDSVSET field. 101 SCB_ICSR_PENDSVSET = 0x10000000 // Bit PENDSVSET. 102 SCB_ICSR_PENDSVSET_PENDSVSET_0 = 0x0 // write: no effect; read: PendSV exception is not pending 103 SCB_ICSR_PENDSVSET_PENDSVSET_1 = 0x1 // write: changes PendSV exception state to pending; read: PendSV exception is pending 104 SCB_ICSR_NMIPENDSET_Pos = 0x1f // Position of NMIPENDSET field. 105 SCB_ICSR_NMIPENDSET_Msk = 0x80000000 // Bit mask of NMIPENDSET field. 106 SCB_ICSR_NMIPENDSET = 0x80000000 // Bit NMIPENDSET. 107 SCB_ICSR_NMIPENDSET_NMIPENDSET_0 = 0x0 // write: no effect; read: NMI exception is not pending 108 SCB_ICSR_NMIPENDSET_NMIPENDSET_1 = 0x1 // write: changes NMI exception state to pending; read: NMI exception is pending 109 110 // VTOR: Vector Table Offset Register 111 SCB_VTOR_TBLOFF_Pos = 0x7 // Position of TBLOFF field. 112 SCB_VTOR_TBLOFF_Msk = 0xffffff80 // Bit mask of TBLOFF field. 113 114 // AIRCR: Application Interrupt and Reset Control Register 115 SCB_AIRCR_VECTRESET_Pos = 0x0 // Position of VECTRESET field. 116 SCB_AIRCR_VECTRESET_Msk = 0x1 // Bit mask of VECTRESET field. 117 SCB_AIRCR_VECTRESET = 0x1 // Bit VECTRESET. 118 SCB_AIRCR_VECTRESET_VECTRESET_0 = 0x0 // No change 119 SCB_AIRCR_VECTRESET_VECTRESET_1 = 0x1 // Causes a local system reset 120 SCB_AIRCR_VECTCLRACTIVE_Pos = 0x1 // Position of VECTCLRACTIVE field. 121 SCB_AIRCR_VECTCLRACTIVE_Msk = 0x2 // Bit mask of VECTCLRACTIVE field. 122 SCB_AIRCR_VECTCLRACTIVE = 0x2 // Bit VECTCLRACTIVE. 123 SCB_AIRCR_VECTCLRACTIVE_VECTCLRACTIVE_0 = 0x0 // No change 124 SCB_AIRCR_VECTCLRACTIVE_VECTCLRACTIVE_1 = 0x1 // Clears all active state information for fixed and configurable exceptions 125 SCB_AIRCR_SYSRESETREQ_Pos = 0x2 // Position of SYSRESETREQ field. 126 SCB_AIRCR_SYSRESETREQ_Msk = 0x4 // Bit mask of SYSRESETREQ field. 127 SCB_AIRCR_SYSRESETREQ = 0x4 // Bit SYSRESETREQ. 128 SCB_AIRCR_SYSRESETREQ_SYSRESETREQ_0 = 0x0 // no system reset request 129 SCB_AIRCR_SYSRESETREQ_SYSRESETREQ_1 = 0x1 // asserts a signal to the outer system that requests a reset 130 SCB_AIRCR_PRIGROUP_Pos = 0x8 // Position of PRIGROUP field. 131 SCB_AIRCR_PRIGROUP_Msk = 0x700 // Bit mask of PRIGROUP field. 132 SCB_AIRCR_ENDIANNESS_Pos = 0xf // Position of ENDIANNESS field. 133 SCB_AIRCR_ENDIANNESS_Msk = 0x8000 // Bit mask of ENDIANNESS field. 134 SCB_AIRCR_ENDIANNESS = 0x8000 // Bit ENDIANNESS. 135 SCB_AIRCR_ENDIANNESS_ENDIANNESS_0 = 0x0 // Little-endian 136 SCB_AIRCR_ENDIANNESS_ENDIANNESS_1 = 0x1 // Big-endian 137 SCB_AIRCR_VECTKEY_Pos = 0x10 // Position of VECTKEY field. 138 SCB_AIRCR_VECTKEY_Msk = 0xffff0000 // Bit mask of VECTKEY field. 139 140 // SCR: System Control Register 141 SCB_SCR_SLEEPONEXIT_Pos = 0x1 // Position of SLEEPONEXIT field. 142 SCB_SCR_SLEEPONEXIT_Msk = 0x2 // Bit mask of SLEEPONEXIT field. 143 SCB_SCR_SLEEPONEXIT = 0x2 // Bit SLEEPONEXIT. 144 SCB_SCR_SLEEPONEXIT_SLEEPONEXIT_0 = 0x0 // o not sleep when returning to Thread mode 145 SCB_SCR_SLEEPONEXIT_SLEEPONEXIT_1 = 0x1 // enter sleep, or deep sleep, on return from an ISR 146 SCB_SCR_SLEEPDEEP_Pos = 0x2 // Position of SLEEPDEEP field. 147 SCB_SCR_SLEEPDEEP_Msk = 0x4 // Bit mask of SLEEPDEEP field. 148 SCB_SCR_SLEEPDEEP = 0x4 // Bit SLEEPDEEP. 149 SCB_SCR_SLEEPDEEP_SLEEPDEEP_0 = 0x0 // sleep 150 SCB_SCR_SLEEPDEEP_SLEEPDEEP_1 = 0x1 // deep sleep 151 SCB_SCR_SEVONPEND_Pos = 0x4 // Position of SEVONPEND field. 152 SCB_SCR_SEVONPEND_Msk = 0x10 // Bit mask of SEVONPEND field. 153 SCB_SCR_SEVONPEND = 0x10 // Bit SEVONPEND. 154 SCB_SCR_SEVONPEND_SEVONPEND_0 = 0x0 // only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 155 SCB_SCR_SEVONPEND_SEVONPEND_1 = 0x1 // enabled events and all interrupts, including disabled interrupts, can wakeup the processor 156 157 // CCR: Configuration and Control Register 158 SCB_CCR_NONBASETHRDENA_Pos = 0x0 // Position of NONBASETHRDENA field. 159 SCB_CCR_NONBASETHRDENA_Msk = 0x1 // Bit mask of NONBASETHRDENA field. 160 SCB_CCR_NONBASETHRDENA = 0x1 // Bit NONBASETHRDENA. 161 SCB_CCR_NONBASETHRDENA_NONBASETHRDENA_0 = 0x0 // processor can enter Thread mode only when no exception is active 162 SCB_CCR_NONBASETHRDENA_NONBASETHRDENA_1 = 0x1 // processor can enter Thread mode from any level under the control of an EXC_RETURN value 163 SCB_CCR_USERSETMPEND_Pos = 0x1 // Position of USERSETMPEND field. 164 SCB_CCR_USERSETMPEND_Msk = 0x2 // Bit mask of USERSETMPEND field. 165 SCB_CCR_USERSETMPEND = 0x2 // Bit USERSETMPEND. 166 SCB_CCR_USERSETMPEND_USERSETMPEND_0 = 0x0 // disable 167 SCB_CCR_USERSETMPEND_USERSETMPEND_1 = 0x1 // enable 168 SCB_CCR_UNALIGN_TRP_Pos = 0x3 // Position of UNALIGN_TRP field. 169 SCB_CCR_UNALIGN_TRP_Msk = 0x8 // Bit mask of UNALIGN_TRP field. 170 SCB_CCR_UNALIGN_TRP = 0x8 // Bit UNALIGN_TRP. 171 SCB_CCR_UNALIGN_TRP_UNALIGN_TRP_0 = 0x0 // do not trap unaligned halfword and word accesses 172 SCB_CCR_UNALIGN_TRP_UNALIGN_TRP_1 = 0x1 // trap unaligned halfword and word accesses 173 SCB_CCR_DIV_0_TRP_Pos = 0x4 // Position of DIV_0_TRP field. 174 SCB_CCR_DIV_0_TRP_Msk = 0x10 // Bit mask of DIV_0_TRP field. 175 SCB_CCR_DIV_0_TRP = 0x10 // Bit DIV_0_TRP. 176 SCB_CCR_DIV_0_TRP_DIV_0_TRP_0 = 0x0 // do not trap divide by 0 177 SCB_CCR_DIV_0_TRP_DIV_0_TRP_1 = 0x1 // trap divide by 0 178 SCB_CCR_BFHFNMIGN_Pos = 0x8 // Position of BFHFNMIGN field. 179 SCB_CCR_BFHFNMIGN_Msk = 0x100 // Bit mask of BFHFNMIGN field. 180 SCB_CCR_BFHFNMIGN = 0x100 // Bit BFHFNMIGN. 181 SCB_CCR_BFHFNMIGN_BFHFNMIGN_0 = 0x0 // data bus faults caused by load and store instructions cause a lock-up 182 SCB_CCR_BFHFNMIGN_BFHFNMIGN_1 = 0x1 // handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions 183 SCB_CCR_STKALIGN_Pos = 0x9 // Position of STKALIGN field. 184 SCB_CCR_STKALIGN_Msk = 0x200 // Bit mask of STKALIGN field. 185 SCB_CCR_STKALIGN = 0x200 // Bit STKALIGN. 186 SCB_CCR_STKALIGN_STKALIGN_0 = 0x0 // 4-byte aligned 187 SCB_CCR_STKALIGN_STKALIGN_1 = 0x1 // 8-byte aligned 188 SCB_CCR_DC_Pos = 0x10 // Position of DC field. 189 SCB_CCR_DC_Msk = 0x10000 // Bit mask of DC field. 190 SCB_CCR_DC = 0x10000 // Bit DC. 191 SCB_CCR_DC_DC_0 = 0x0 // L1 data cache disabled 192 SCB_CCR_DC_DC_1 = 0x1 // L1 data cache enabled 193 SCB_CCR_IC_Pos = 0x11 // Position of IC field. 194 SCB_CCR_IC_Msk = 0x20000 // Bit mask of IC field. 195 SCB_CCR_IC = 0x20000 // Bit IC. 196 SCB_CCR_IC_IC_0 = 0x0 // L1 instruction cache disabled 197 SCB_CCR_IC_IC_1 = 0x1 // L1 instruction cache enabled 198 SCB_CCR_BP_Pos = 0x12 // Position of BP field. 199 SCB_CCR_BP_Msk = 0x40000 // Bit mask of BP field. 200 SCB_CCR_BP = 0x40000 // Bit BP. 201 202 // SHPR1: System Handler Priority Register 1 203 SCB_SHPR1_PRI_4_Pos = 0x0 // Position of PRI_4 field. 204 SCB_SHPR1_PRI_4_Msk = 0xff // Bit mask of PRI_4 field. 205 SCB_SHPR1_PRI_5_Pos = 0x8 // Position of PRI_5 field. 206 SCB_SHPR1_PRI_5_Msk = 0xff00 // Bit mask of PRI_5 field. 207 SCB_SHPR1_PRI_6_Pos = 0x10 // Position of PRI_6 field. 208 SCB_SHPR1_PRI_6_Msk = 0xff0000 // Bit mask of PRI_6 field. 209 210 // SHPR2: System Handler Priority Register 2 211 SCB_SHPR2_PRI_11_Pos = 0x18 // Position of PRI_11 field. 212 SCB_SHPR2_PRI_11_Msk = 0xff000000 // Bit mask of PRI_11 field. 213 214 // SHPR3: System Handler Priority Register 3 215 SCB_SHPR3_PRI_14_Pos = 0x10 // Position of PRI_14 field. 216 SCB_SHPR3_PRI_14_Msk = 0xff0000 // Bit mask of PRI_14 field. 217 SCB_SHPR3_PRI_15_Pos = 0x18 // Position of PRI_15 field. 218 SCB_SHPR3_PRI_15_Msk = 0xff000000 // Bit mask of PRI_15 field. 219 220 // SHCSR: System Handler Control and State Register 221 SCB_SHCSR_MEMFAULTACT_Pos = 0x0 // Position of MEMFAULTACT field. 222 SCB_SHCSR_MEMFAULTACT_Msk = 0x1 // Bit mask of MEMFAULTACT field. 223 SCB_SHCSR_MEMFAULTACT = 0x1 // Bit MEMFAULTACT. 224 SCB_SHCSR_MEMFAULTACT_MEMFAULTACT_0 = 0x0 // exception is not active 225 SCB_SHCSR_MEMFAULTACT_MEMFAULTACT_1 = 0x1 // exception is active 226 SCB_SHCSR_BUSFAULTACT_Pos = 0x1 // Position of BUSFAULTACT field. 227 SCB_SHCSR_BUSFAULTACT_Msk = 0x2 // Bit mask of BUSFAULTACT field. 228 SCB_SHCSR_BUSFAULTACT = 0x2 // Bit BUSFAULTACT. 229 SCB_SHCSR_BUSFAULTACT_BUSFAULTACT_0 = 0x0 // exception is not active 230 SCB_SHCSR_BUSFAULTACT_BUSFAULTACT_1 = 0x1 // exception is active 231 SCB_SHCSR_USGFAULTACT_Pos = 0x3 // Position of USGFAULTACT field. 232 SCB_SHCSR_USGFAULTACT_Msk = 0x8 // Bit mask of USGFAULTACT field. 233 SCB_SHCSR_USGFAULTACT = 0x8 // Bit USGFAULTACT. 234 SCB_SHCSR_USGFAULTACT_USGFAULTACT_0 = 0x0 // exception is not active 235 SCB_SHCSR_USGFAULTACT_USGFAULTACT_1 = 0x1 // exception is active 236 SCB_SHCSR_SVCALLACT_Pos = 0x7 // Position of SVCALLACT field. 237 SCB_SHCSR_SVCALLACT_Msk = 0x80 // Bit mask of SVCALLACT field. 238 SCB_SHCSR_SVCALLACT = 0x80 // Bit SVCALLACT. 239 SCB_SHCSR_SVCALLACT_SVCALLACT_0 = 0x0 // exception is not active 240 SCB_SHCSR_SVCALLACT_SVCALLACT_1 = 0x1 // exception is active 241 SCB_SHCSR_MONITORACT_Pos = 0x8 // Position of MONITORACT field. 242 SCB_SHCSR_MONITORACT_Msk = 0x100 // Bit mask of MONITORACT field. 243 SCB_SHCSR_MONITORACT = 0x100 // Bit MONITORACT. 244 SCB_SHCSR_MONITORACT_MONITORACT_0 = 0x0 // exception is not active 245 SCB_SHCSR_MONITORACT_MONITORACT_1 = 0x1 // exception is active 246 SCB_SHCSR_PENDSVACT_Pos = 0xa // Position of PENDSVACT field. 247 SCB_SHCSR_PENDSVACT_Msk = 0x400 // Bit mask of PENDSVACT field. 248 SCB_SHCSR_PENDSVACT = 0x400 // Bit PENDSVACT. 249 SCB_SHCSR_PENDSVACT_PENDSVACT_0 = 0x0 // exception is not active 250 SCB_SHCSR_PENDSVACT_PENDSVACT_1 = 0x1 // exception is active 251 SCB_SHCSR_SYSTICKACT_Pos = 0xb // Position of SYSTICKACT field. 252 SCB_SHCSR_SYSTICKACT_Msk = 0x800 // Bit mask of SYSTICKACT field. 253 SCB_SHCSR_SYSTICKACT = 0x800 // Bit SYSTICKACT. 254 SCB_SHCSR_SYSTICKACT_SYSTICKACT_0 = 0x0 // exception is not active 255 SCB_SHCSR_SYSTICKACT_SYSTICKACT_1 = 0x1 // exception is active 256 SCB_SHCSR_USGFAULTPENDED_Pos = 0xc // Position of USGFAULTPENDED field. 257 SCB_SHCSR_USGFAULTPENDED_Msk = 0x1000 // Bit mask of USGFAULTPENDED field. 258 SCB_SHCSR_USGFAULTPENDED = 0x1000 // Bit USGFAULTPENDED. 259 SCB_SHCSR_USGFAULTPENDED_USGFAULTPENDED_0 = 0x0 // exception is not pending 260 SCB_SHCSR_USGFAULTPENDED_USGFAULTPENDED_1 = 0x1 // exception is pending 261 SCB_SHCSR_MEMFAULTPENDED_Pos = 0xd // Position of MEMFAULTPENDED field. 262 SCB_SHCSR_MEMFAULTPENDED_Msk = 0x2000 // Bit mask of MEMFAULTPENDED field. 263 SCB_SHCSR_MEMFAULTPENDED = 0x2000 // Bit MEMFAULTPENDED. 264 SCB_SHCSR_MEMFAULTPENDED_MEMFAULTPENDED_0 = 0x0 // exception is not pending 265 SCB_SHCSR_MEMFAULTPENDED_MEMFAULTPENDED_1 = 0x1 // exception is pending 266 SCB_SHCSR_BUSFAULTPENDED_Pos = 0xe // Position of BUSFAULTPENDED field. 267 SCB_SHCSR_BUSFAULTPENDED_Msk = 0x4000 // Bit mask of BUSFAULTPENDED field. 268 SCB_SHCSR_BUSFAULTPENDED = 0x4000 // Bit BUSFAULTPENDED. 269 SCB_SHCSR_BUSFAULTPENDED_BUSFAULTPENDED_0 = 0x0 // exception is not pending 270 SCB_SHCSR_BUSFAULTPENDED_BUSFAULTPENDED_1 = 0x1 // exception is pending 271 SCB_SHCSR_SVCALLPENDED_Pos = 0xf // Position of SVCALLPENDED field. 272 SCB_SHCSR_SVCALLPENDED_Msk = 0x8000 // Bit mask of SVCALLPENDED field. 273 SCB_SHCSR_SVCALLPENDED = 0x8000 // Bit SVCALLPENDED. 274 SCB_SHCSR_SVCALLPENDED_SVCALLPENDED_0 = 0x0 // exception is not pending 275 SCB_SHCSR_SVCALLPENDED_SVCALLPENDED_1 = 0x1 // exception is pending 276 SCB_SHCSR_MEMFAULTENA_Pos = 0x10 // Position of MEMFAULTENA field. 277 SCB_SHCSR_MEMFAULTENA_Msk = 0x10000 // Bit mask of MEMFAULTENA field. 278 SCB_SHCSR_MEMFAULTENA = 0x10000 // Bit MEMFAULTENA. 279 SCB_SHCSR_MEMFAULTENA_MEMFAULTENA_0 = 0x0 // disable the exception 280 SCB_SHCSR_MEMFAULTENA_MEMFAULTENA_1 = 0x1 // enable the exception 281 SCB_SHCSR_BUSFAULTENA_Pos = 0x11 // Position of BUSFAULTENA field. 282 SCB_SHCSR_BUSFAULTENA_Msk = 0x20000 // Bit mask of BUSFAULTENA field. 283 SCB_SHCSR_BUSFAULTENA = 0x20000 // Bit BUSFAULTENA. 284 SCB_SHCSR_BUSFAULTENA_BUSFAULTENA_0 = 0x0 // disable the exception 285 SCB_SHCSR_BUSFAULTENA_BUSFAULTENA_1 = 0x1 // enable the exception 286 SCB_SHCSR_USGFAULTENA_Pos = 0x12 // Position of USGFAULTENA field. 287 SCB_SHCSR_USGFAULTENA_Msk = 0x40000 // Bit mask of USGFAULTENA field. 288 SCB_SHCSR_USGFAULTENA = 0x40000 // Bit USGFAULTENA. 289 SCB_SHCSR_USGFAULTENA_USGFAULTENA_0 = 0x0 // disable the exception 290 SCB_SHCSR_USGFAULTENA_USGFAULTENA_1 = 0x1 // enable the exception 291 292 // CFSR: Configurable Fault Status Register 293 SCB_CFSR_IACCVIOL_Pos = 0x0 // Position of IACCVIOL field. 294 SCB_CFSR_IACCVIOL_Msk = 0x1 // Bit mask of IACCVIOL field. 295 SCB_CFSR_IACCVIOL = 0x1 // Bit IACCVIOL. 296 SCB_CFSR_IACCVIOL_IACCVIOL_0 = 0x0 // no instruction access violation fault 297 SCB_CFSR_IACCVIOL_IACCVIOL_1 = 0x1 // the processor attempted an instruction fetch from a location that does not permit execution 298 SCB_CFSR_DACCVIOL_Pos = 0x1 // Position of DACCVIOL field. 299 SCB_CFSR_DACCVIOL_Msk = 0x2 // Bit mask of DACCVIOL field. 300 SCB_CFSR_DACCVIOL = 0x2 // Bit DACCVIOL. 301 SCB_CFSR_DACCVIOL_DACCVIOL_0 = 0x0 // no data access violation fault 302 SCB_CFSR_DACCVIOL_DACCVIOL_1 = 0x1 // the processor attempted a load or store at a location that does not permit the operation 303 SCB_CFSR_MUNSTKERR_Pos = 0x3 // Position of MUNSTKERR field. 304 SCB_CFSR_MUNSTKERR_Msk = 0x8 // Bit mask of MUNSTKERR field. 305 SCB_CFSR_MUNSTKERR = 0x8 // Bit MUNSTKERR. 306 SCB_CFSR_MUNSTKERR_MUNSTKERR_0 = 0x0 // no unstacking fault 307 SCB_CFSR_MUNSTKERR_MUNSTKERR_1 = 0x1 // unstack for an exception return has caused one or more access violations 308 SCB_CFSR_MSTKERR_Pos = 0x4 // Position of MSTKERR field. 309 SCB_CFSR_MSTKERR_Msk = 0x10 // Bit mask of MSTKERR field. 310 SCB_CFSR_MSTKERR = 0x10 // Bit MSTKERR. 311 SCB_CFSR_MSTKERR_MSTKERR_0 = 0x0 // no stacking fault 312 SCB_CFSR_MSTKERR_MSTKERR_1 = 0x1 // stacking for an exception entry has caused one or more access violations 313 SCB_CFSR_MLSPERR_Pos = 0x5 // Position of MLSPERR field. 314 SCB_CFSR_MLSPERR_Msk = 0x20 // Bit mask of MLSPERR field. 315 SCB_CFSR_MLSPERR = 0x20 // Bit MLSPERR. 316 SCB_CFSR_MLSPERR_MLSPERR_0 = 0x0 // No MemManage fault occurred during floating-point lazy state preservation 317 SCB_CFSR_MLSPERR_MLSPERR_1 = 0x1 // A MemManage fault occurred during floating-point lazy state preservation 318 SCB_CFSR_MMARVALID_Pos = 0x7 // Position of MMARVALID field. 319 SCB_CFSR_MMARVALID_Msk = 0x80 // Bit mask of MMARVALID field. 320 SCB_CFSR_MMARVALID = 0x80 // Bit MMARVALID. 321 SCB_CFSR_MMARVALID_MMARVALID_0 = 0x0 // value in MMAR is not a valid fault address 322 SCB_CFSR_MMARVALID_MMARVALID_1 = 0x1 // MMAR holds a valid fault address 323 SCB_CFSR_IBUSERR_Pos = 0x8 // Position of IBUSERR field. 324 SCB_CFSR_IBUSERR_Msk = 0x100 // Bit mask of IBUSERR field. 325 SCB_CFSR_IBUSERR = 0x100 // Bit IBUSERR. 326 SCB_CFSR_IBUSERR_IBUSERR_0 = 0x0 // no instruction bus error 327 SCB_CFSR_IBUSERR_IBUSERR_1 = 0x1 // instruction bus error 328 SCB_CFSR_PRECISERR_Pos = 0x9 // Position of PRECISERR field. 329 SCB_CFSR_PRECISERR_Msk = 0x200 // Bit mask of PRECISERR field. 330 SCB_CFSR_PRECISERR = 0x200 // Bit PRECISERR. 331 SCB_CFSR_PRECISERR_PRECISERR_0 = 0x0 // no precise data bus error 332 SCB_CFSR_PRECISERR_PRECISERR_1 = 0x1 // a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault 333 SCB_CFSR_IMPRECISERR_Pos = 0xa // Position of IMPRECISERR field. 334 SCB_CFSR_IMPRECISERR_Msk = 0x400 // Bit mask of IMPRECISERR field. 335 SCB_CFSR_IMPRECISERR = 0x400 // Bit IMPRECISERR. 336 SCB_CFSR_IMPRECISERR_IMPRECISERR_0 = 0x0 // no imprecise data bus error 337 SCB_CFSR_IMPRECISERR_IMPRECISERR_1 = 0x1 // a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error 338 SCB_CFSR_UNSTKERR_Pos = 0xb // Position of UNSTKERR field. 339 SCB_CFSR_UNSTKERR_Msk = 0x800 // Bit mask of UNSTKERR field. 340 SCB_CFSR_UNSTKERR = 0x800 // Bit UNSTKERR. 341 SCB_CFSR_UNSTKERR_UNSTKERR_0 = 0x0 // no unstacking fault 342 SCB_CFSR_UNSTKERR_UNSTKERR_1 = 0x1 // unstack for an exception return has caused one or more BusFaults 343 SCB_CFSR_STKERR_Pos = 0xc // Position of STKERR field. 344 SCB_CFSR_STKERR_Msk = 0x1000 // Bit mask of STKERR field. 345 SCB_CFSR_STKERR = 0x1000 // Bit STKERR. 346 SCB_CFSR_STKERR_STKERR_0 = 0x0 // no stacking fault 347 SCB_CFSR_STKERR_STKERR_1 = 0x1 // stacking for an exception entry has caused one or more BusFaults 348 SCB_CFSR_LSPERR_Pos = 0xd // Position of LSPERR field. 349 SCB_CFSR_LSPERR_Msk = 0x2000 // Bit mask of LSPERR field. 350 SCB_CFSR_LSPERR = 0x2000 // Bit LSPERR. 351 SCB_CFSR_LSPERR_LSPERR_0 = 0x0 // No bus fault occurred during floating-point lazy state preservation 352 SCB_CFSR_LSPERR_LSPERR_1 = 0x1 // A bus fault occurred during floating-point lazy state preservation 353 SCB_CFSR_BFARVALID_Pos = 0xf // Position of BFARVALID field. 354 SCB_CFSR_BFARVALID_Msk = 0x8000 // Bit mask of BFARVALID field. 355 SCB_CFSR_BFARVALID = 0x8000 // Bit BFARVALID. 356 SCB_CFSR_BFARVALID_BFARVALID_0 = 0x0 // value in BFAR is not a valid fault address 357 SCB_CFSR_BFARVALID_BFARVALID_1 = 0x1 // BFAR holds a valid fault address 358 SCB_CFSR_UNDEFINSTR_Pos = 0x10 // Position of UNDEFINSTR field. 359 SCB_CFSR_UNDEFINSTR_Msk = 0x10000 // Bit mask of UNDEFINSTR field. 360 SCB_CFSR_UNDEFINSTR = 0x10000 // Bit UNDEFINSTR. 361 SCB_CFSR_UNDEFINSTR_UNDEFINSTR_0 = 0x0 // no undefined instruction UsageFault 362 SCB_CFSR_UNDEFINSTR_UNDEFINSTR_1 = 0x1 // the processor has attempted to execute an undefined instruction 363 SCB_CFSR_INVSTATE_Pos = 0x11 // Position of INVSTATE field. 364 SCB_CFSR_INVSTATE_Msk = 0x20000 // Bit mask of INVSTATE field. 365 SCB_CFSR_INVSTATE = 0x20000 // Bit INVSTATE. 366 SCB_CFSR_INVSTATE_INVSTATE_0 = 0x0 // no invalid state UsageFault 367 SCB_CFSR_INVSTATE_INVSTATE_1 = 0x1 // the processor has attempted to execute an instruction that makes illegal use of the EPSR 368 SCB_CFSR_INVPC_Pos = 0x12 // Position of INVPC field. 369 SCB_CFSR_INVPC_Msk = 0x40000 // Bit mask of INVPC field. 370 SCB_CFSR_INVPC = 0x40000 // Bit INVPC. 371 SCB_CFSR_INVPC_INVPC_0 = 0x0 // no invalid PC load UsageFault 372 SCB_CFSR_INVPC_INVPC_1 = 0x1 // the processor has attempted an illegal load of EXC_RETURN to the PC 373 SCB_CFSR_NOCP_Pos = 0x13 // Position of NOCP field. 374 SCB_CFSR_NOCP_Msk = 0x80000 // Bit mask of NOCP field. 375 SCB_CFSR_NOCP = 0x80000 // Bit NOCP. 376 SCB_CFSR_NOCP_NOCP_0 = 0x0 // no UsageFault caused by attempting to access a coprocessor 377 SCB_CFSR_NOCP_NOCP_1 = 0x1 // the processor has attempted to access a coprocessor 378 SCB_CFSR_UNALIGNED_Pos = 0x18 // Position of UNALIGNED field. 379 SCB_CFSR_UNALIGNED_Msk = 0x1000000 // Bit mask of UNALIGNED field. 380 SCB_CFSR_UNALIGNED = 0x1000000 // Bit UNALIGNED. 381 SCB_CFSR_UNALIGNED_UNALIGNED_0 = 0x0 // no unaligned access fault, or unaligned access trapping not enabled 382 SCB_CFSR_UNALIGNED_UNALIGNED_1 = 0x1 // the processor has made an unaligned memory access 383 SCB_CFSR_DIVBYZERO_Pos = 0x19 // Position of DIVBYZERO field. 384 SCB_CFSR_DIVBYZERO_Msk = 0x2000000 // Bit mask of DIVBYZERO field. 385 SCB_CFSR_DIVBYZERO = 0x2000000 // Bit DIVBYZERO. 386 SCB_CFSR_DIVBYZERO_DIVBYZERO_0 = 0x0 // no divide by zero fault, or divide by zero trapping not enabled 387 SCB_CFSR_DIVBYZERO_DIVBYZERO_1 = 0x1 // the processor has executed an SDIV or UDIV instruction with a divisor of 0 388 389 // HFSR: HardFault Status register 390 SCB_HFSR_VECTTBL_Pos = 0x1 // Position of VECTTBL field. 391 SCB_HFSR_VECTTBL_Msk = 0x2 // Bit mask of VECTTBL field. 392 SCB_HFSR_VECTTBL = 0x2 // Bit VECTTBL. 393 SCB_HFSR_VECTTBL_VECTTBL_0 = 0x0 // no BusFault on vector table read 394 SCB_HFSR_VECTTBL_VECTTBL_1 = 0x1 // BusFault on vector table read 395 SCB_HFSR_FORCED_Pos = 0x1e // Position of FORCED field. 396 SCB_HFSR_FORCED_Msk = 0x40000000 // Bit mask of FORCED field. 397 SCB_HFSR_FORCED = 0x40000000 // Bit FORCED. 398 SCB_HFSR_FORCED_FORCED_0 = 0x0 // no forced HardFault 399 SCB_HFSR_FORCED_FORCED_1 = 0x1 // forced HardFault 400 SCB_HFSR_DEBUGEVT_Pos = 0x1f // Position of DEBUGEVT field. 401 SCB_HFSR_DEBUGEVT_Msk = 0x80000000 // Bit mask of DEBUGEVT field. 402 SCB_HFSR_DEBUGEVT = 0x80000000 // Bit DEBUGEVT. 403 SCB_HFSR_DEBUGEVT_DEBUGEVT_0 = 0x0 // No Debug event has occurred. 404 SCB_HFSR_DEBUGEVT_DEBUGEVT_1 = 0x1 // Debug event has occurred. The Debug Fault Status Register has been updated. 405 406 // DFSR: Debug Fault Status Register 407 SCB_DFSR_HALTED_Pos = 0x0 // Position of HALTED field. 408 SCB_DFSR_HALTED_Msk = 0x1 // Bit mask of HALTED field. 409 SCB_DFSR_HALTED = 0x1 // Bit HALTED. 410 SCB_DFSR_HALTED_HALTED_0 = 0x0 // No active halt request debug event 411 SCB_DFSR_HALTED_HALTED_1 = 0x1 // Halt request debug event active 412 SCB_DFSR_BKPT_Pos = 0x1 // Position of BKPT field. 413 SCB_DFSR_BKPT_Msk = 0x2 // Bit mask of BKPT field. 414 SCB_DFSR_BKPT = 0x2 // Bit BKPT. 415 SCB_DFSR_BKPT_BKPT_0 = 0x0 // No current breakpoint debug event 416 SCB_DFSR_BKPT_BKPT_1 = 0x1 // At least one current breakpoint debug event 417 SCB_DFSR_DWTTRAP_Pos = 0x2 // Position of DWTTRAP field. 418 SCB_DFSR_DWTTRAP_Msk = 0x4 // Bit mask of DWTTRAP field. 419 SCB_DFSR_DWTTRAP = 0x4 // Bit DWTTRAP. 420 SCB_DFSR_DWTTRAP_DWTTRAP_0 = 0x0 // No current debug events generated by the DWT 421 SCB_DFSR_DWTTRAP_DWTTRAP_1 = 0x1 // At least one current debug event generated by the DWT 422 SCB_DFSR_VCATCH_Pos = 0x3 // Position of VCATCH field. 423 SCB_DFSR_VCATCH_Msk = 0x8 // Bit mask of VCATCH field. 424 SCB_DFSR_VCATCH = 0x8 // Bit VCATCH. 425 SCB_DFSR_VCATCH_VCATCH_0 = 0x0 // No Vector catch triggered 426 SCB_DFSR_VCATCH_VCATCH_1 = 0x1 // Vector catch triggered 427 SCB_DFSR_EXTERNAL_Pos = 0x4 // Position of EXTERNAL field. 428 SCB_DFSR_EXTERNAL_Msk = 0x10 // Bit mask of EXTERNAL field. 429 SCB_DFSR_EXTERNAL = 0x10 // Bit EXTERNAL. 430 SCB_DFSR_EXTERNAL_EXTERNAL_0 = 0x0 // No external debug request debug event 431 SCB_DFSR_EXTERNAL_EXTERNAL_1 = 0x1 // External debug request debug event 432 433 // MMFAR: MemManage Fault Address Register 434 SCB_MMFAR_ADDRESS_Pos = 0x0 // Position of ADDRESS field. 435 SCB_MMFAR_ADDRESS_Msk = 0xffffffff // Bit mask of ADDRESS field. 436 437 // BFAR: BusFault Address Register 438 SCB_BFAR_ADDRESS_Pos = 0x0 // Position of ADDRESS field. 439 SCB_BFAR_ADDRESS_Msk = 0xffffffff // Bit mask of ADDRESS field. 440 )