github.com/tinygo-org/tinygo@v0.31.3-0.20240404173401-90b0bf646c27/src/device/sam/atsame5x-bitfields.go (about)

     1  // Hand created file. DO NOT DELETE.
     2  // atsamd51x bitfield definitions that are not auto-generated by gen-device-svd.go
     3  
     4  //go:build sam && atsame5x
     5  
     6  // These are the supported pchctrl function numberings on the atsamd51x
     7  // See http://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf
     8  // table 14-9
     9  
    10  package sam
    11  
    12  const (
    13  	PCHCTRL_GCLK_OSCCTRL_DFLL48     = 0 // DFLL48 input clock source
    14  	PCHCTRL_GCLK_OSCCTRL_FDPLL0     = 1 // Reference clock for FDPLL0
    15  	PCHCTRL_GCLK_OSCCTRL_FDPLL1     = 2 // Reference clock for FDPLL1
    16  	PCHCTRL_GCLK_OSCCTRL_FDPLL0_32K = 3 // FDPLL0 = 3 // 32KHz clock for internal lock timer
    17  	PCHCTRL_GCLK_OSCCTRL_FDPLL1_32K = 3 // FDPLL1 = 3 // 32KHz clock for internal lock timer
    18  	PCHCTRL_GCLK_SDHC0_SLOW         = 3 // SDHC0 = 3 // Slow
    19  	PCHCTRL_GCLK_SDHC1_SLOW         = 3 // SDHC1 = 3 // Slow
    20  	PCHCTRL_GCLK_SERCOMX_SLOW       = 3 // GCLK_SERCOM[0..7]_SLOW = 3
    21  	PCHCTRL_GCLK_EIC                = 4
    22  	PCHCTRL_GCLK_FREQM_MSR          = 5 // FREQM Measure
    23  	PCHCTRL_GCLK_FREQM_REF          = 6 // FREQM Reference
    24  	PCHCTRL_GCLK_SERCOM0_CORE       = 7 // SERCOM0 Core
    25  	PCHCTRL_GCLK_SERCOM1_CORE       = 8 // SERCOM1 Core
    26  	PCHCTRL_GCLK_TC0                = 9
    27  	PCHCTRL_GCLK_TC1                = 9  // TC0, TC1
    28  	PCHCTRL_GCLK_USB                = 10 // USB
    29  	PCHCTRL_GCLK_EVSYS0             = 11
    30  	PCHCTRL_GCLK_EVSYS1             = 12
    31  	PCHCTRL_GCLK_EVSYS2             = 13
    32  	PCHCTRL_GCLK_EVSYS3             = 14
    33  	PCHCTRL_GCLK_EVSYS4             = 15
    34  	PCHCTRL_GCLK_EVSYS5             = 16
    35  	PCHCTRL_GCLK_EVSYS6             = 17
    36  	PCHCTRL_GCLK_EVSYS7             = 18
    37  	PCHCTRL_GCLK_EVSYS8             = 19
    38  	PCHCTRL_GCLK_EVSYS9             = 20
    39  	PCHCTRL_GCLK_EVSYS10            = 21
    40  	PCHCTRL_GCLK_EVSYS11            = 22
    41  	PCHCTRL_GCLK_SERCOM2_CORE       = 23 // SERCOM2 Core
    42  	PCHCTRL_GCLK_SERCOM3_CORE       = 24 // SERCOM3 Core
    43  	PCHCTRL_GCLK_TCC0               = 25
    44  	PCHCTRL_GCLK_TCC1               = 25 // TCC0, TCC1
    45  	PCHCTRL_GCLK_TC2                = 26
    46  	PCHCTRL_GCLK_TC3                = 26 // TC2, TC3
    47  	PCHCTRL_GCLK_CAN0               = 27 // CAN0
    48  	PCHCTRL_GCLK_CAN1               = 28 // CAN1
    49  	PCHCTRL_GCLK_TCC2               = 29
    50  	PCHCTRL_GCLK_TCC3               = 29 // TCC2, TCC3
    51  	PCHCTRL_GCLK_TC4                = 30
    52  	PCHCTRL_GCLK_TC5                = 30 // TC4, TC5
    53  	PCHCTRL_GCLK_PDEC               = 31 // PDEC
    54  	PCHCTRL_GCLK_AC                 = 32 // AC
    55  	PCHCTRL_GCLK_CCL                = 33 // CCL
    56  	PCHCTRL_GCLK_SERCOM4_CORE       = 34 // SERCOM4 Core
    57  	PCHCTRL_GCLK_SERCOM5_CORE       = 35 // SERCOM5 Core
    58  	PCHCTRL_GCLK_SERCOM6_CORE       = 36 // SERCOM6 Core
    59  	PCHCTRL_GCLK_SERCOM7_CORE       = 37 // SERCOM7 Core
    60  	PCHCTRL_GCLK_TCC4               = 38 // TCC4
    61  	PCHCTRL_GCLK_TC6                = 39
    62  	PCHCTRL_GCLK_TC7                = 39 // TC6, TC7
    63  	PCHCTRL_GCLK_ADC0               = 40 // ADC0
    64  	PCHCTRL_GCLK_ADC1               = 41 // ADC1
    65  	PCHCTRL_GCLK_DAC                = 42 // DAC
    66  	PCHCTRL_GCLK_I2S0               = 43
    67  	PCHCTRL_GCLK_I2S1               = 44
    68  	PCHCTRL_GCLK_SDHC0              = 45 // SDHC0
    69  	PCHCTRL_GCLK_SDHC1              = 46 // SDHC1
    70  	PCHCTRL_GCLK_CM4_TRACE          = 47 // CM4 Trace
    71  )