github.com/tinygo-org/tinygo@v0.31.3-0.20240404173401-90b0bf646c27/src/machine/machine_stm32f7.go (about) 1 //go:build stm32f7 2 3 package machine 4 5 // Peripheral abstraction layer for the stm32f4 6 7 import ( 8 "device/stm32" 9 "runtime/interrupt" 10 "runtime/volatile" 11 "unsafe" 12 ) 13 14 var deviceIDAddr = []uintptr{0x1FF0F420, 0x1FF0F424, 0x1FF0F428} 15 16 // Alternative peripheral pin functions 17 const ( 18 AF0_SYSTEM = 0 19 AF1_TIM1_2 = 1 20 AF2_TIM3_4_5 = 2 21 AF3_TIM8_9_10_11_LPTIM1 = 3 22 AF4_I2C1_2_3_USART1 = 4 23 AF5_SPI1_2_3_4_5_I2S1_2_3 = 5 24 AF6_SPI2_3_I2S2_3_SAI1_UART4 = 6 25 AF7_SPI2_3_I2S2_3_USART1_2_3_UART5 = 7 26 AF8_SAI2_USART6_UART4_5_7_8_OTG1_FS = 8 27 AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS = 9 28 AF10_SAI2_QUADSPI_SDMMC2_OTG2_HS_OTG1_FS = 10 29 AF11_SDMMC2 = 11 30 AF12_UART7_FMC_SDMMC1_OTG2_FS = 12 31 AF15_EVENTOUT = 15 32 ) 33 34 const ( 35 PA0 = portA + 0 36 PA1 = portA + 1 37 PA2 = portA + 2 38 PA3 = portA + 3 39 PA4 = portA + 4 40 PA5 = portA + 5 41 PA6 = portA + 6 42 PA7 = portA + 7 43 PA8 = portA + 8 44 PA9 = portA + 9 45 PA10 = portA + 10 46 PA11 = portA + 11 47 PA12 = portA + 12 48 PA13 = portA + 13 49 PA14 = portA + 14 50 PA15 = portA + 15 51 52 PB0 = portB + 0 53 PB1 = portB + 1 54 PB2 = portB + 2 55 PB3 = portB + 3 56 PB4 = portB + 4 57 PB5 = portB + 5 58 PB6 = portB + 6 59 PB7 = portB + 7 60 PB8 = portB + 8 61 PB9 = portB + 9 62 PB10 = portB + 10 63 PB11 = portB + 11 64 PB12 = portB + 12 65 PB13 = portB + 13 66 PB14 = portB + 14 67 PB15 = portB + 15 68 69 PC0 = portC + 0 70 PC1 = portC + 1 71 PC2 = portC + 2 72 PC3 = portC + 3 73 PC4 = portC + 4 74 PC5 = portC + 5 75 PC6 = portC + 6 76 PC7 = portC + 7 77 PC8 = portC + 8 78 PC9 = portC + 9 79 PC10 = portC + 10 80 PC11 = portC + 11 81 PC12 = portC + 12 82 PC13 = portC + 13 83 PC14 = portC + 14 84 PC15 = portC + 15 85 86 PD0 = portD + 0 87 PD1 = portD + 1 88 PD2 = portD + 2 89 PD3 = portD + 3 90 PD4 = portD + 4 91 PD5 = portD + 5 92 PD6 = portD + 6 93 PD7 = portD + 7 94 PD8 = portD + 8 95 PD9 = portD + 9 96 PD10 = portD + 10 97 PD11 = portD + 11 98 PD12 = portD + 12 99 PD13 = portD + 13 100 PD14 = portD + 14 101 PD15 = portD + 15 102 103 PE0 = portE + 0 104 PE1 = portE + 1 105 PE2 = portE + 2 106 PE3 = portE + 3 107 PE4 = portE + 4 108 PE5 = portE + 5 109 PE6 = portE + 6 110 PE7 = portE + 7 111 PE8 = portE + 8 112 PE9 = portE + 9 113 PE10 = portE + 10 114 PE11 = portE + 11 115 PE12 = portE + 12 116 PE13 = portE + 13 117 PE14 = portE + 14 118 PE15 = portE + 15 119 120 PF0 = portF + 0 121 PF1 = portF + 1 122 PF2 = portF + 2 123 PF3 = portF + 3 124 PF4 = portF + 4 125 PF5 = portF + 5 126 PF6 = portF + 6 127 PF7 = portF + 7 128 PF8 = portF + 8 129 PF9 = portF + 9 130 PF10 = portF + 10 131 PF11 = portF + 11 132 PF12 = portF + 12 133 PF13 = portF + 13 134 PF14 = portF + 14 135 PF15 = portF + 15 136 137 PG0 = portG + 0 138 PG1 = portG + 1 139 PG2 = portG + 2 140 PG3 = portG + 3 141 PG4 = portG + 4 142 PG5 = portG + 5 143 PG6 = portG + 6 144 PG7 = portG + 7 145 PG8 = portG + 8 146 PG9 = portG + 9 147 PG10 = portG + 10 148 PG11 = portG + 11 149 PG12 = portG + 12 150 PG13 = portG + 13 151 PG14 = portG + 14 152 PG15 = portG + 15 153 154 PH0 = portH + 0 155 PH1 = portH + 1 156 PH2 = portH + 2 157 PH3 = portH + 3 158 PH4 = portH + 4 159 PH5 = portH + 5 160 PH6 = portH + 6 161 PH7 = portH + 7 162 PH8 = portH + 8 163 PH9 = portH + 9 164 PH10 = portH + 10 165 PH11 = portH + 11 166 PH12 = portH + 12 167 PH13 = portH + 13 168 PH14 = portH + 14 169 PH15 = portH + 15 170 171 PI0 = portI + 0 172 PI1 = portI + 1 173 PI2 = portI + 2 174 PI3 = portI + 3 175 PI4 = portI + 4 176 PI5 = portI + 5 177 PI6 = portI + 6 178 PI7 = portI + 7 179 PI8 = portI + 8 180 PI9 = portI + 9 181 PI10 = portI + 10 182 PI11 = portI + 11 183 PI12 = portI + 12 184 PI13 = portI + 13 185 PI14 = portI + 14 186 PI15 = portI + 15 187 ) 188 189 func (p Pin) getPort() *stm32.GPIO_Type { 190 switch p / 16 { 191 case 0: 192 return stm32.GPIOA 193 case 1: 194 return stm32.GPIOB 195 case 2: 196 return stm32.GPIOC 197 case 3: 198 return stm32.GPIOD 199 case 4: 200 return stm32.GPIOE 201 case 5: 202 return stm32.GPIOF 203 case 6: 204 return stm32.GPIOG 205 case 7: 206 return stm32.GPIOH 207 case 8: 208 return stm32.GPIOI 209 default: 210 panic("machine: unknown port") 211 } 212 } 213 214 // enableClock enables the clock for this desired GPIO port. 215 func (p Pin) enableClock() { 216 switch p / 16 { 217 case 0: 218 stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOAEN) 219 case 1: 220 stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOBEN) 221 case 2: 222 stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOCEN) 223 case 3: 224 stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIODEN) 225 case 4: 226 stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOEEN) 227 case 5: 228 stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOFEN) 229 case 6: 230 stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOGEN) 231 case 7: 232 stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOHEN) 233 case 8: 234 stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOIEN) 235 default: 236 panic("machine: unknown port") 237 } 238 } 239 240 // Enable peripheral clock 241 func enableAltFuncClock(bus unsafe.Pointer) { 242 switch bus { 243 case unsafe.Pointer(stm32.DAC): // DAC interface clock enable 244 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_DACEN) 245 case unsafe.Pointer(stm32.PWR): // Power interface clock enable 246 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN) 247 case unsafe.Pointer(stm32.CAN1): // CAN 1 clock enable 248 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_CAN1EN) 249 case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable 250 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C3EN) 251 case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable 252 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C2EN) 253 case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable 254 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN) 255 case unsafe.Pointer(stm32.UART5): // UART5 clock enable 256 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_UART5EN) 257 case unsafe.Pointer(stm32.UART4): // UART4 clock enable 258 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_UART4EN) 259 case unsafe.Pointer(stm32.USART3): // USART3 clock enable 260 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART3EN) 261 case unsafe.Pointer(stm32.USART2): // USART2 clock enable 262 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN) 263 case unsafe.Pointer(stm32.SPI3): // SPI3 clock enable 264 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI3EN) 265 case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable 266 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI2EN) 267 case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable 268 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_WWDGEN) 269 case unsafe.Pointer(stm32.TIM14): // TIM14 clock enable 270 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM14EN) 271 case unsafe.Pointer(stm32.TIM13): // TIM13 clock enable 272 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM13EN) 273 case unsafe.Pointer(stm32.TIM12): // TIM12 clock enable 274 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM12EN) 275 case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable 276 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM7EN) 277 case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable 278 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM6EN) 279 case unsafe.Pointer(stm32.TIM5): // TIM5 clock enable 280 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM5EN) 281 case unsafe.Pointer(stm32.TIM4): // TIM4 clock enable 282 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM4EN) 283 case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable 284 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM3EN) 285 case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable 286 stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM2EN) 287 case unsafe.Pointer(stm32.TIM11): // TIM11 clock enable 288 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM11EN) 289 case unsafe.Pointer(stm32.TIM10): // TIM10 clock enable 290 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM10EN) 291 case unsafe.Pointer(stm32.TIM9): // TIM9 clock enable 292 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM9EN) 293 case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable 294 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN) 295 case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable 296 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN) 297 case unsafe.Pointer(stm32.ADC3): // ADC3 clock enable 298 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC3EN) 299 case unsafe.Pointer(stm32.ADC2): // ADC2 clock enable 300 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC2EN) 301 case unsafe.Pointer(stm32.ADC1): // ADC1 clock enable 302 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC1EN) 303 case unsafe.Pointer(stm32.USART6): // USART6 clock enable 304 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART6EN) 305 case unsafe.Pointer(stm32.USART1): // USART1 clock enable 306 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN) 307 case unsafe.Pointer(stm32.TIM8): // TIM8 clock enable 308 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM8EN) 309 case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable 310 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN) 311 } 312 } 313 314 func (p Pin) registerInterrupt() interrupt.Interrupt { 315 pin := uint8(p) % 16 316 317 switch pin { 318 case 0: 319 return interrupt.New(stm32.IRQ_EXTI0, func(interrupt.Interrupt) { handlePinInterrupt(0) }) 320 case 1: 321 return interrupt.New(stm32.IRQ_EXTI1, func(interrupt.Interrupt) { handlePinInterrupt(1) }) 322 case 2: 323 return interrupt.New(stm32.IRQ_EXTI2, func(interrupt.Interrupt) { handlePinInterrupt(2) }) 324 case 3: 325 return interrupt.New(stm32.IRQ_EXTI3, func(interrupt.Interrupt) { handlePinInterrupt(3) }) 326 case 4: 327 return interrupt.New(stm32.IRQ_EXTI4, func(interrupt.Interrupt) { handlePinInterrupt(4) }) 328 case 5: 329 return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(5) }) 330 case 6: 331 return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(6) }) 332 case 7: 333 return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(7) }) 334 case 8: 335 return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(8) }) 336 case 9: 337 return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(9) }) 338 case 10: 339 return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(10) }) 340 case 11: 341 return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(11) }) 342 case 12: 343 return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(12) }) 344 case 13: 345 return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(13) }) 346 case 14: 347 return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(14) }) 348 case 15: 349 return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(15) }) 350 } 351 352 return interrupt.Interrupt{} 353 } 354 355 //---------- Timer related code 356 357 var ( 358 TIM1 = TIM{ 359 EnableRegister: &stm32.RCC.APB2ENR, 360 EnableFlag: stm32.RCC_APB2ENR_TIM1EN, 361 Device: stm32.TIM1, 362 Channels: [4]TimerChannel{ 363 TimerChannel{Pins: []PinFunction{ 364 {PA8, AF1_TIM1_2}, 365 {PE9, AF1_TIM1_2}, 366 }}, 367 TimerChannel{Pins: []PinFunction{ 368 {PA9, AF1_TIM1_2}, 369 {PE11, AF1_TIM1_2}, 370 }}, 371 TimerChannel{Pins: []PinFunction{ 372 {PA10, AF1_TIM1_2}, 373 {PE13, AF1_TIM1_2}, 374 }}, 375 TimerChannel{Pins: []PinFunction{ 376 {PA11, AF1_TIM1_2}, 377 {PE14, AF1_TIM1_2}, 378 }}, 379 }, 380 busFreq: APB2_TIM_FREQ, 381 } 382 383 TIM2 = TIM{ 384 EnableRegister: &stm32.RCC.APB1ENR, 385 EnableFlag: stm32.RCC_APB1ENR_TIM2EN, 386 Device: stm32.TIM2, 387 Channels: [4]TimerChannel{ 388 TimerChannel{Pins: []PinFunction{ 389 {PA0, AF1_TIM1_2}, 390 {PA5, AF1_TIM1_2}, 391 {PA15, AF1_TIM1_2}, 392 }}, 393 TimerChannel{Pins: []PinFunction{ 394 {PA1, AF1_TIM1_2}, 395 {PB3, AF1_TIM1_2}, 396 }}, 397 TimerChannel{Pins: []PinFunction{ 398 {PA2, AF1_TIM1_2}, 399 {PB10, AF1_TIM1_2}, 400 }}, 401 TimerChannel{Pins: []PinFunction{ 402 {PA3, AF1_TIM1_2}, 403 {PB11, AF1_TIM1_2}, 404 }}, 405 }, 406 busFreq: APB1_TIM_FREQ, 407 } 408 409 TIM3 = TIM{ 410 EnableRegister: &stm32.RCC.APB1ENR, 411 EnableFlag: stm32.RCC_APB1ENR_TIM3EN, 412 Device: stm32.TIM3, 413 Channels: [4]TimerChannel{ 414 TimerChannel{Pins: []PinFunction{ 415 {PA6, AF2_TIM3_4_5}, 416 {PB4, AF2_TIM3_4_5}, 417 {PC6, AF2_TIM3_4_5}, 418 }}, 419 TimerChannel{Pins: []PinFunction{ 420 {PA7, AF2_TIM3_4_5}, 421 {PB5, AF2_TIM3_4_5}, 422 {PC7, AF2_TIM3_4_5}, 423 }}, 424 TimerChannel{Pins: []PinFunction{ 425 {PB0, AF2_TIM3_4_5}, 426 {PC8, AF2_TIM3_4_5}, 427 }}, 428 TimerChannel{Pins: []PinFunction{ 429 {PB1, AF2_TIM3_4_5}, 430 {PC9, AF2_TIM3_4_5}, 431 }}, 432 }, 433 busFreq: APB1_TIM_FREQ, 434 } 435 436 TIM4 = TIM{ 437 EnableRegister: &stm32.RCC.APB1ENR, 438 EnableFlag: stm32.RCC_APB1ENR_TIM4EN, 439 Device: stm32.TIM4, 440 Channels: [4]TimerChannel{ 441 TimerChannel{Pins: []PinFunction{ 442 {PB6, AF2_TIM3_4_5}, 443 {PD12, AF2_TIM3_4_5}, 444 }}, 445 TimerChannel{Pins: []PinFunction{ 446 {PB7, AF2_TIM3_4_5}, 447 {PD13, AF2_TIM3_4_5}, 448 }}, 449 TimerChannel{Pins: []PinFunction{ 450 {PB8, AF2_TIM3_4_5}, 451 {PD14, AF2_TIM3_4_5}, 452 }}, 453 TimerChannel{Pins: []PinFunction{ 454 {PB9, AF2_TIM3_4_5}, 455 {PD15, AF2_TIM3_4_5}, 456 }}, 457 }, 458 busFreq: APB1_TIM_FREQ, 459 } 460 461 TIM5 = TIM{ 462 EnableRegister: &stm32.RCC.APB1ENR, 463 EnableFlag: stm32.RCC_APB1ENR_TIM5EN, 464 Device: stm32.TIM5, 465 Channels: [4]TimerChannel{ 466 TimerChannel{Pins: []PinFunction{ 467 {PA0, AF2_TIM3_4_5}, 468 {PH10, AF2_TIM3_4_5}, 469 }}, 470 TimerChannel{Pins: []PinFunction{ 471 {PA1, AF2_TIM3_4_5}, 472 {PH11, AF2_TIM3_4_5}, 473 }}, 474 TimerChannel{Pins: []PinFunction{ 475 {PA2, AF2_TIM3_4_5}, 476 {PH12, AF2_TIM3_4_5}, 477 }}, 478 TimerChannel{Pins: []PinFunction{ 479 {PA3, AF2_TIM3_4_5}, 480 {PI0, AF2_TIM3_4_5}, 481 }}, 482 }, 483 busFreq: APB1_TIM_FREQ, 484 } 485 486 TIM6 = TIM{ 487 EnableRegister: &stm32.RCC.APB1ENR, 488 EnableFlag: stm32.RCC_APB1ENR_TIM6EN, 489 Device: stm32.TIM6, 490 Channels: [4]TimerChannel{ 491 TimerChannel{Pins: []PinFunction{}}, 492 TimerChannel{Pins: []PinFunction{}}, 493 TimerChannel{Pins: []PinFunction{}}, 494 TimerChannel{Pins: []PinFunction{}}, 495 }, 496 busFreq: APB1_TIM_FREQ, 497 } 498 499 TIM7 = TIM{ 500 EnableRegister: &stm32.RCC.APB1ENR, 501 EnableFlag: stm32.RCC_APB1ENR_TIM7EN, 502 Device: stm32.TIM7, 503 Channels: [4]TimerChannel{ 504 TimerChannel{Pins: []PinFunction{}}, 505 TimerChannel{Pins: []PinFunction{}}, 506 TimerChannel{Pins: []PinFunction{}}, 507 TimerChannel{Pins: []PinFunction{}}, 508 }, 509 busFreq: APB1_TIM_FREQ, 510 } 511 512 TIM8 = TIM{ 513 EnableRegister: &stm32.RCC.APB2ENR, 514 EnableFlag: stm32.RCC_APB2ENR_TIM8EN, 515 Device: stm32.TIM8, 516 Channels: [4]TimerChannel{ 517 TimerChannel{Pins: []PinFunction{ 518 {PC6, AF3_TIM8_9_10_11_LPTIM1}, 519 {PI5, AF3_TIM8_9_10_11_LPTIM1}, 520 }}, 521 TimerChannel{Pins: []PinFunction{ 522 {PC7, AF3_TIM8_9_10_11_LPTIM1}, 523 {PI6, AF3_TIM8_9_10_11_LPTIM1}, 524 }}, 525 TimerChannel{Pins: []PinFunction{ 526 {PC8, AF3_TIM8_9_10_11_LPTIM1}, 527 {PI7, AF3_TIM8_9_10_11_LPTIM1}, 528 }}, 529 TimerChannel{Pins: []PinFunction{ 530 {PC9, AF3_TIM8_9_10_11_LPTIM1}, 531 {PI2, AF3_TIM8_9_10_11_LPTIM1}, 532 }}, 533 }, 534 busFreq: APB2_TIM_FREQ, 535 } 536 537 TIM9 = TIM{ 538 EnableRegister: &stm32.RCC.APB2ENR, 539 EnableFlag: stm32.RCC_APB2ENR_TIM9EN, 540 Device: stm32.TIM9, 541 Channels: [4]TimerChannel{ 542 TimerChannel{Pins: []PinFunction{ 543 {PA2, AF3_TIM8_9_10_11_LPTIM1}, 544 {PE5, AF3_TIM8_9_10_11_LPTIM1}, 545 }}, 546 TimerChannel{Pins: []PinFunction{ 547 {PA3, AF3_TIM8_9_10_11_LPTIM1}, 548 {PE6, AF3_TIM8_9_10_11_LPTIM1}, 549 }}, 550 TimerChannel{Pins: []PinFunction{}}, 551 TimerChannel{Pins: []PinFunction{}}, 552 }, 553 busFreq: APB2_TIM_FREQ, 554 } 555 556 TIM10 = TIM{ 557 EnableRegister: &stm32.RCC.APB2ENR, 558 EnableFlag: stm32.RCC_APB2ENR_TIM10EN, 559 Device: stm32.TIM10, 560 Channels: [4]TimerChannel{ 561 TimerChannel{Pins: []PinFunction{ 562 {PB8, AF3_TIM8_9_10_11_LPTIM1}, 563 {PF6, AF3_TIM8_9_10_11_LPTIM1}, 564 }}, 565 TimerChannel{Pins: []PinFunction{}}, 566 TimerChannel{Pins: []PinFunction{}}, 567 TimerChannel{Pins: []PinFunction{}}, 568 }, 569 busFreq: APB2_TIM_FREQ, 570 } 571 572 TIM11 = TIM{ 573 EnableRegister: &stm32.RCC.APB2ENR, 574 EnableFlag: stm32.RCC_APB2ENR_TIM11EN, 575 Device: stm32.TIM11, 576 Channels: [4]TimerChannel{ 577 TimerChannel{Pins: []PinFunction{ 578 {PB9, AF3_TIM8_9_10_11_LPTIM1}, 579 {PF7, AF3_TIM8_9_10_11_LPTIM1}, 580 }}, 581 TimerChannel{Pins: []PinFunction{}}, 582 TimerChannel{Pins: []PinFunction{}}, 583 TimerChannel{Pins: []PinFunction{}}, 584 }, 585 busFreq: APB2_TIM_FREQ, 586 } 587 588 TIM12 = TIM{ 589 EnableRegister: &stm32.RCC.APB1ENR, 590 EnableFlag: stm32.RCC_APB1ENR_TIM12EN, 591 Device: stm32.TIM12, 592 Channels: [4]TimerChannel{ 593 TimerChannel{Pins: []PinFunction{ 594 {PB14, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, 595 {PH6, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, 596 }}, 597 TimerChannel{Pins: []PinFunction{ 598 {PB15, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, 599 {PH9, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, 600 }}, 601 TimerChannel{Pins: []PinFunction{}}, 602 TimerChannel{Pins: []PinFunction{}}, 603 }, 604 busFreq: APB1_TIM_FREQ, 605 } 606 607 TIM13 = TIM{ 608 EnableRegister: &stm32.RCC.APB1ENR, 609 EnableFlag: stm32.RCC_APB1ENR_TIM13EN, 610 Device: stm32.TIM13, 611 Channels: [4]TimerChannel{ 612 TimerChannel{Pins: []PinFunction{ 613 {PA6, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, 614 {PF8, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, 615 }}, 616 TimerChannel{Pins: []PinFunction{}}, 617 TimerChannel{Pins: []PinFunction{}}, 618 TimerChannel{Pins: []PinFunction{}}, 619 }, 620 busFreq: APB1_TIM_FREQ, 621 } 622 623 TIM14 = TIM{ 624 EnableRegister: &stm32.RCC.APB1ENR, 625 EnableFlag: stm32.RCC_APB1ENR_TIM14EN, 626 Device: stm32.TIM14, 627 Channels: [4]TimerChannel{ 628 TimerChannel{Pins: []PinFunction{ 629 {PA7, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, 630 {PF9, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS}, 631 }}, 632 TimerChannel{Pins: []PinFunction{}}, 633 TimerChannel{Pins: []PinFunction{}}, 634 TimerChannel{Pins: []PinFunction{}}, 635 }, 636 busFreq: APB1_TIM_FREQ, 637 } 638 ) 639 640 func (t *TIM) registerUPInterrupt() interrupt.Interrupt { 641 switch t { 642 case &TIM1: 643 return interrupt.New(stm32.IRQ_TIM1_UP_TIM10, TIM1.handleUPInterrupt) 644 case &TIM2: 645 return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt) 646 case &TIM3: 647 return interrupt.New(stm32.IRQ_TIM3, TIM3.handleUPInterrupt) 648 case &TIM4: 649 return interrupt.New(stm32.IRQ_TIM4, TIM4.handleUPInterrupt) 650 case &TIM5: 651 return interrupt.New(stm32.IRQ_TIM5, TIM5.handleUPInterrupt) 652 case &TIM6: 653 return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleUPInterrupt) 654 case &TIM7: 655 return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt) 656 case &TIM8: 657 return interrupt.New(stm32.IRQ_TIM8_UP_TIM13, TIM8.handleUPInterrupt) 658 case &TIM9: 659 return interrupt.New(stm32.IRQ_TIM1_BRK_TIM9, TIM9.handleUPInterrupt) 660 case &TIM10: 661 return interrupt.New(stm32.IRQ_TIM1_UP_TIM10, TIM10.handleUPInterrupt) 662 case &TIM11: 663 return interrupt.New(stm32.IRQ_TIM1_TRG_COM_TIM11, TIM11.handleUPInterrupt) 664 case &TIM12: 665 return interrupt.New(stm32.IRQ_TIM8_BRK_TIM12, TIM12.handleUPInterrupt) 666 case &TIM13: 667 return interrupt.New(stm32.IRQ_TIM8_UP_TIM13, TIM13.handleUPInterrupt) 668 case &TIM14: 669 return interrupt.New(stm32.IRQ_TIM8_TRG_COM_TIM14, TIM14.handleUPInterrupt) 670 } 671 672 return interrupt.Interrupt{} 673 } 674 675 func (t *TIM) registerOCInterrupt() interrupt.Interrupt { 676 switch t { 677 case &TIM1: 678 return interrupt.New(stm32.IRQ_TIM1_CC, TIM1.handleUPInterrupt) 679 case &TIM2: 680 return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt) 681 case &TIM3: 682 return interrupt.New(stm32.IRQ_TIM3, TIM3.handleOCInterrupt) 683 case &TIM4: 684 return interrupt.New(stm32.IRQ_TIM4, TIM4.handleOCInterrupt) 685 case &TIM5: 686 return interrupt.New(stm32.IRQ_TIM5, TIM5.handleOCInterrupt) 687 case &TIM6: 688 return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleOCInterrupt) 689 case &TIM7: 690 return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt) 691 case &TIM8: 692 return interrupt.New(stm32.IRQ_TIM8_CC, TIM8.handleOCInterrupt) 693 case &TIM9: 694 return interrupt.New(stm32.IRQ_TIM1_BRK_TIM9, TIM9.handleOCInterrupt) 695 case &TIM10: 696 return interrupt.New(stm32.IRQ_TIM1_UP_TIM10, TIM10.handleOCInterrupt) 697 case &TIM11: 698 return interrupt.New(stm32.IRQ_TIM1_TRG_COM_TIM11, TIM11.handleOCInterrupt) 699 case &TIM12: 700 return interrupt.New(stm32.IRQ_TIM8_BRK_TIM12, TIM12.handleOCInterrupt) 701 case &TIM13: 702 return interrupt.New(stm32.IRQ_TIM8_UP_TIM13, TIM13.handleOCInterrupt) 703 case &TIM14: 704 return interrupt.New(stm32.IRQ_TIM8_TRG_COM_TIM14, TIM14.handleOCInterrupt) 705 } 706 707 return interrupt.Interrupt{} 708 } 709 710 func (t *TIM) enableMainOutput() { 711 t.Device.BDTR.SetBits(stm32.TIM_BDTR_MOE) 712 } 713 714 type arrtype = uint32 715 type arrRegType = volatile.Register32 716 717 const ( 718 ARR_MAX = 0x10000 719 PSC_MAX = 0x10000 720 ) 721 722 func initRNG() { 723 stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_RNGEN) 724 stm32.RNG.CR.SetBits(stm32.RNG_CR_RNGEN) 725 }