github.com/tinygo-org/tinygo@v0.31.3-0.20240404173401-90b0bf646c27/src/machine/machine_stm32l0x1.go (about)

     1  //go:build stm32l0x1
     2  
     3  package machine
     4  
     5  // Peripheral abstraction layer for the stm32l0
     6  
     7  import (
     8  	"device/stm32"
     9  	"runtime/interrupt"
    10  	"runtime/volatile"
    11  	"unsafe"
    12  )
    13  
    14  const (
    15  	AF0_SYSTEM_SPI1_USART2_LPTIM_TIM21 = 0
    16  	AF1_SPI1_I2C1_LPTIM                = 1
    17  	AF2_LPTIM_TIM2                     = 2
    18  	AF3_I2C1                           = 3
    19  	AF4_I2C1_USART2_LPUART1_TIM22      = 4
    20  	AF5_TIM2_21_22                     = 5
    21  	AF6_LPUART1                        = 6
    22  	AF7_COMP1_2                        = 7
    23  )
    24  
    25  // Enable peripheral clock
    26  func enableAltFuncClock(bus unsafe.Pointer) {
    27  	switch bus {
    28  	case unsafe.Pointer(stm32.PWR): // Power interface clock enable
    29  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN)
    30  	case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable
    31  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C3EN)
    32  	case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable
    33  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C2EN)
    34  	case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable
    35  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN)
    36  	case unsafe.Pointer(stm32.USART5): // UART5 clock enable
    37  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART5EN)
    38  	case unsafe.Pointer(stm32.USART4): // UART4 clock enable
    39  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART4EN)
    40  	case unsafe.Pointer(stm32.USART2): // USART2 clock enable
    41  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN)
    42  	case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable
    43  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI2EN)
    44  	case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable
    45  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_LPUART1EN)
    46  	case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable
    47  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_WWDGEN)
    48  	case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable
    49  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM7EN)
    50  	case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable
    51  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM6EN)
    52  	case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable
    53  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM3EN)
    54  	case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable
    55  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM2EN)
    56  	case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable
    57  		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN)
    58  	case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable
    59  		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN)
    60  	case unsafe.Pointer(stm32.ADC): // ADC clock enable
    61  		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADCEN)
    62  	case unsafe.Pointer(stm32.USART1): // USART1 clock enable
    63  		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
    64  	}
    65  }
    66  
    67  //---------- Timer related code
    68  
    69  var (
    70  	TIM2 = TIM{
    71  		EnableRegister: &stm32.RCC.APB1ENR,
    72  		EnableFlag:     stm32.RCC_APB1ENR_TIM2EN,
    73  		Device:         stm32.TIM2,
    74  		Channels: [4]TimerChannel{
    75  			TimerChannel{Pins: []PinFunction{{PA0, AF2_LPTIM_TIM2}, {PA5, AF5_TIM2_21_22}, {PA8, AF5_TIM2_21_22}, {PA15, AF5_TIM2_21_22}}},
    76  			TimerChannel{Pins: []PinFunction{{PA1, AF2_LPTIM_TIM2}, {PB3, AF2_LPTIM_TIM2}}},
    77  			TimerChannel{Pins: []PinFunction{{PA2, AF2_LPTIM_TIM2}, {PB0, AF5_TIM2_21_22}, {PB10, AF2_LPTIM_TIM2}}},
    78  			TimerChannel{Pins: []PinFunction{{PA3, AF2_LPTIM_TIM2}, {PB1, AF5_TIM2_21_22}, {PB11, AF2_LPTIM_TIM2}}},
    79  		},
    80  		busFreq: APB1_TIM_FREQ,
    81  	}
    82  
    83  	TIM3 = TIM{
    84  		EnableRegister: &stm32.RCC.APB1ENR,
    85  		EnableFlag:     stm32.RCC_APB1ENR_TIM3EN,
    86  		Device:         stm32.TIM3,
    87  		Channels: [4]TimerChannel{
    88  			TimerChannel{Pins: []PinFunction{}},
    89  			TimerChannel{Pins: []PinFunction{}},
    90  			TimerChannel{Pins: []PinFunction{}},
    91  			TimerChannel{Pins: []PinFunction{}},
    92  		},
    93  		busFreq: APB1_TIM_FREQ,
    94  	}
    95  
    96  	TIM6 = TIM{
    97  		EnableRegister: &stm32.RCC.APB1ENR,
    98  		EnableFlag:     stm32.RCC_APB1ENR_TIM6EN,
    99  		Device:         stm32.TIM6,
   100  		Channels: [4]TimerChannel{
   101  			TimerChannel{Pins: []PinFunction{}},
   102  			TimerChannel{Pins: []PinFunction{}},
   103  			TimerChannel{Pins: []PinFunction{}},
   104  			TimerChannel{Pins: []PinFunction{}},
   105  		},
   106  		busFreq: APB1_TIM_FREQ,
   107  	}
   108  
   109  	TIM7 = TIM{
   110  		EnableRegister: &stm32.RCC.APB1ENR,
   111  		EnableFlag:     stm32.RCC_APB1ENR_TIM7EN,
   112  		Device:         stm32.TIM7,
   113  		Channels: [4]TimerChannel{
   114  			TimerChannel{Pins: []PinFunction{}},
   115  			TimerChannel{Pins: []PinFunction{}},
   116  			TimerChannel{Pins: []PinFunction{}},
   117  			TimerChannel{Pins: []PinFunction{}},
   118  		},
   119  		busFreq: APB1_TIM_FREQ,
   120  	}
   121  
   122  	TIM21 = TIM{
   123  		EnableRegister: &stm32.RCC.APB2ENR,
   124  		EnableFlag:     stm32.RCC_APB2ENR_TIM21EN,
   125  		Device:         stm32.TIM21,
   126  		Channels: [4]TimerChannel{
   127  			TimerChannel{Pins: []PinFunction{}},
   128  			TimerChannel{Pins: []PinFunction{}},
   129  			TimerChannel{Pins: []PinFunction{}},
   130  			TimerChannel{Pins: []PinFunction{}},
   131  		},
   132  		busFreq: APB2_TIM_FREQ,
   133  	}
   134  
   135  	TIM22 = TIM{
   136  		EnableRegister: &stm32.RCC.APB2ENR,
   137  		EnableFlag:     stm32.RCC_APB2ENR_TIM22EN,
   138  		Device:         stm32.TIM2,
   139  		Channels: [4]TimerChannel{
   140  			TimerChannel{Pins: []PinFunction{}},
   141  			TimerChannel{Pins: []PinFunction{}},
   142  			TimerChannel{Pins: []PinFunction{}},
   143  			TimerChannel{Pins: []PinFunction{}},
   144  		},
   145  		busFreq: APB2_TIM_FREQ,
   146  	}
   147  )
   148  
   149  func (t *TIM) registerUPInterrupt() interrupt.Interrupt {
   150  	switch t {
   151  	case &TIM2:
   152  		return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt)
   153  	case &TIM3:
   154  		return interrupt.New(stm32.IRQ_TIM3, TIM3.handleUPInterrupt)
   155  	case &TIM6:
   156  		return interrupt.New(stm32.IRQ_TIM6, TIM6.handleUPInterrupt)
   157  	case &TIM7:
   158  		return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt)
   159  	case &TIM21:
   160  		return interrupt.New(stm32.IRQ_TIM21, TIM21.handleUPInterrupt)
   161  	case &TIM22:
   162  		return interrupt.New(stm32.IRQ_TIM22, TIM22.handleUPInterrupt)
   163  	}
   164  
   165  	return interrupt.Interrupt{}
   166  }
   167  
   168  func (t *TIM) registerOCInterrupt() interrupt.Interrupt {
   169  	switch t {
   170  	case &TIM2:
   171  		return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt)
   172  	case &TIM3:
   173  		return interrupt.New(stm32.IRQ_TIM3, TIM3.handleOCInterrupt)
   174  	case &TIM6:
   175  		return interrupt.New(stm32.IRQ_TIM6, TIM6.handleOCInterrupt)
   176  	case &TIM7:
   177  		return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt)
   178  	case &TIM21:
   179  		return interrupt.New(stm32.IRQ_TIM21, TIM21.handleOCInterrupt)
   180  	case &TIM22:
   181  		return interrupt.New(stm32.IRQ_TIM22, TIM22.handleOCInterrupt)
   182  	}
   183  
   184  	return interrupt.Interrupt{}
   185  }
   186  
   187  func (t *TIM) enableMainOutput() {
   188  	// nothing to do - no BDTR register
   189  }
   190  
   191  type arrtype = uint16
   192  type arrRegType = volatile.Register16
   193  
   194  const (
   195  	ARR_MAX = 0x10000
   196  	PSC_MAX = 0x10000
   197  )