github.com/tinygo-org/tinygo@v0.31.3-0.20240404173401-90b0bf646c27/src/machine/machine_stm32l0x2.go (about)

     1  //go:build stm32l0x2
     2  
     3  package machine
     4  
     5  // Peripheral abstraction layer for the stm32l0
     6  
     7  import (
     8  	"device/stm32"
     9  	"runtime/interrupt"
    10  	"runtime/volatile"
    11  	"unsafe"
    12  )
    13  
    14  const (
    15  	AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22 = 0
    16  	AF1_SPI1_2_I2S2_I2C1_TIM2_21                                      = 1
    17  	AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3                  = 2
    18  	AF3_I2C1_TSC                                                      = 3
    19  	AF4_I2C1_USART1_2_LPUART1_TIM3_22                                 = 4
    20  	AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22                              = 5
    21  	AF6_I2C1_2_LPUART1_USART4_5_TIM21                                 = 6
    22  	AF7_I2C3_LPUART1_COMP1_2_TIM3                                     = 7
    23  )
    24  
    25  // Enable peripheral clock
    26  func enableAltFuncClock(bus unsafe.Pointer) {
    27  	switch bus {
    28  	case unsafe.Pointer(stm32.DAC): // DAC interface clock enable
    29  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_DACEN)
    30  	case unsafe.Pointer(stm32.PWR): // Power interface clock enable
    31  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN)
    32  	case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable
    33  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C3EN)
    34  	case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable
    35  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C2EN)
    36  	case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable
    37  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN)
    38  	case unsafe.Pointer(stm32.USART5): // UART5 clock enable
    39  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART5EN)
    40  	case unsafe.Pointer(stm32.USART4): // UART4 clock enable
    41  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART4EN)
    42  	case unsafe.Pointer(stm32.USART2): // USART2 clock enable
    43  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN)
    44  	case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable
    45  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI2EN)
    46  	case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable
    47  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_LPUART1EN)
    48  	case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable
    49  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_WWDGEN)
    50  	case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable
    51  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM7EN)
    52  	case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable
    53  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM6EN)
    54  	case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable
    55  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM3EN)
    56  	case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable
    57  		stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM2EN)
    58  	case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable
    59  		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN)
    60  	case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable
    61  		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN)
    62  	case unsafe.Pointer(stm32.ADC): // ADC clock enable
    63  		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADCEN)
    64  	case unsafe.Pointer(stm32.USART1): // USART1 clock enable
    65  		stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
    66  	}
    67  }
    68  
    69  //---------- Timer related code
    70  
    71  var (
    72  	TIM2 = TIM{
    73  		EnableRegister: &stm32.RCC.APB1ENR,
    74  		EnableFlag:     stm32.RCC_APB1ENR_TIM2EN,
    75  		Device:         stm32.TIM2,
    76  		Channels: [4]TimerChannel{
    77  			TimerChannel{Pins: []PinFunction{
    78  				{PA0, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
    79  				{PA5, AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22},
    80  				{PA15, AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22},
    81  				{PE9, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
    82  			}},
    83  			TimerChannel{Pins: []PinFunction{
    84  				{PA1, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
    85  				{PB3, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
    86  				{PE10, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
    87  			}},
    88  			TimerChannel{Pins: []PinFunction{
    89  				{PA2, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
    90  				{PB10, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
    91  				{PE11, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
    92  			}},
    93  			TimerChannel{Pins: []PinFunction{
    94  				{PA3, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
    95  				{PB11, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
    96  				{PE12, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
    97  			}},
    98  		},
    99  		busFreq: APB1_TIM_FREQ,
   100  	}
   101  
   102  	TIM3 = TIM{
   103  		EnableRegister: &stm32.RCC.APB1ENR,
   104  		EnableFlag:     stm32.RCC_APB1ENR_TIM3EN,
   105  		Device:         stm32.TIM3,
   106  		Channels: [4]TimerChannel{
   107  			TimerChannel{Pins: []PinFunction{
   108  				{PA6, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
   109  				{PB4, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
   110  				{PC6, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
   111  				{PE3, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
   112  			}},
   113  			TimerChannel{Pins: []PinFunction{
   114  				{PA7, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
   115  				{PB5, AF4_I2C1_USART1_2_LPUART1_TIM3_22},
   116  				{PC7, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
   117  				{PE4, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
   118  			}},
   119  			TimerChannel{Pins: []PinFunction{
   120  				{PB0, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
   121  				{PC8, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
   122  				{PE5, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
   123  			}},
   124  			TimerChannel{Pins: []PinFunction{
   125  				{PB1, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
   126  				{PC9, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
   127  				{PE6, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
   128  			}},
   129  		},
   130  		busFreq: APB1_TIM_FREQ,
   131  	}
   132  
   133  	TIM6 = TIM{
   134  		EnableRegister: &stm32.RCC.APB1ENR,
   135  		EnableFlag:     stm32.RCC_APB1ENR_TIM6EN,
   136  		Device:         stm32.TIM6,
   137  		Channels: [4]TimerChannel{
   138  			TimerChannel{Pins: []PinFunction{}},
   139  			TimerChannel{Pins: []PinFunction{}},
   140  			TimerChannel{Pins: []PinFunction{}},
   141  			TimerChannel{Pins: []PinFunction{}},
   142  		},
   143  		busFreq: APB1_TIM_FREQ,
   144  	}
   145  
   146  	TIM7 = TIM{
   147  		EnableRegister: &stm32.RCC.APB1ENR,
   148  		EnableFlag:     stm32.RCC_APB1ENR_TIM7EN,
   149  		Device:         stm32.TIM7,
   150  		Channels: [4]TimerChannel{
   151  			TimerChannel{Pins: []PinFunction{}},
   152  			TimerChannel{Pins: []PinFunction{}},
   153  			TimerChannel{Pins: []PinFunction{}},
   154  			TimerChannel{Pins: []PinFunction{}},
   155  		},
   156  		busFreq: APB1_TIM_FREQ,
   157  	}
   158  
   159  	TIM21 = TIM{
   160  		EnableRegister: &stm32.RCC.APB2ENR,
   161  		EnableFlag:     stm32.RCC_APB2ENR_TIM21EN,
   162  		Device:         stm32.TIM21,
   163  		Channels: [4]TimerChannel{
   164  			TimerChannel{Pins: []PinFunction{
   165  				{PA2, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
   166  				{PB13, AF6_I2C1_2_LPUART1_USART4_5_TIM21},
   167  				{PD0, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
   168  				{PE5, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
   169  			}},
   170  			TimerChannel{Pins: []PinFunction{
   171  				{PA3, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
   172  				{PB14, AF6_I2C1_2_LPUART1_USART4_5_TIM21},
   173  				{PD7, AF1_SPI1_2_I2S2_I2C1_TIM2_21},
   174  				{PE6, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
   175  			}},
   176  			TimerChannel{Pins: []PinFunction{}},
   177  			TimerChannel{Pins: []PinFunction{}},
   178  		},
   179  		busFreq: APB2_TIM_FREQ,
   180  	}
   181  
   182  	TIM22 = TIM{
   183  		EnableRegister: &stm32.RCC.APB2ENR,
   184  		EnableFlag:     stm32.RCC_APB2ENR_TIM22EN,
   185  		Device:         stm32.TIM2,
   186  		Channels: [4]TimerChannel{
   187  			TimerChannel{Pins: []PinFunction{
   188  				{PA6, AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22},
   189  				{PB4, AF4_I2C1_USART1_2_LPUART1_TIM3_22},
   190  				{PC6, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
   191  				{PE3, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
   192  			}},
   193  			TimerChannel{Pins: []PinFunction{
   194  				{PA7, AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22},
   195  				{PB5, AF4_I2C1_USART1_2_LPUART1_TIM3_22},
   196  				{PC7, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
   197  				{PE4, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
   198  			}},
   199  			TimerChannel{Pins: []PinFunction{}},
   200  			TimerChannel{Pins: []PinFunction{}},
   201  		},
   202  		busFreq: APB2_TIM_FREQ,
   203  	}
   204  )
   205  
   206  func (t *TIM) registerUPInterrupt() interrupt.Interrupt {
   207  	switch t {
   208  	case &TIM2:
   209  		return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt)
   210  	case &TIM3:
   211  		return interrupt.New(stm32.IRQ_TIM3, TIM3.handleUPInterrupt)
   212  	case &TIM6:
   213  		return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleUPInterrupt)
   214  	case &TIM7:
   215  		return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt)
   216  	case &TIM21:
   217  		return interrupt.New(stm32.IRQ_TIM21, TIM21.handleUPInterrupt)
   218  	case &TIM22:
   219  		return interrupt.New(stm32.IRQ_TIM22, TIM22.handleUPInterrupt)
   220  	}
   221  
   222  	return interrupt.Interrupt{}
   223  }
   224  
   225  func (t *TIM) registerOCInterrupt() interrupt.Interrupt {
   226  	switch t {
   227  	case &TIM2:
   228  		return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt)
   229  	case &TIM3:
   230  		return interrupt.New(stm32.IRQ_TIM3, TIM3.handleOCInterrupt)
   231  	case &TIM6:
   232  		return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleOCInterrupt)
   233  	case &TIM7:
   234  		return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt)
   235  	case &TIM21:
   236  		return interrupt.New(stm32.IRQ_TIM21, TIM21.handleOCInterrupt)
   237  	case &TIM22:
   238  		return interrupt.New(stm32.IRQ_TIM22, TIM22.handleOCInterrupt)
   239  	}
   240  
   241  	return interrupt.Interrupt{}
   242  }
   243  
   244  func (t *TIM) enableMainOutput() {
   245  	// nothing to do - no BDTR register
   246  }
   247  
   248  type arrtype = uint16
   249  type arrRegType = volatile.Register16
   250  
   251  const (
   252  	ARR_MAX = 0x10000
   253  	PSC_MAX = 0x10000
   254  )
   255  
   256  func initRNG() {
   257  	stm32.RCC.AHBENR.SetBits(stm32.RCC_AHBENR_RNGEN)
   258  	stm32.RNG.CR.SetBits(stm32.RNG_CR_RNGEN)
   259  }