github.com/tinygo-org/tinygo@v0.31.3-0.20240404173401-90b0bf646c27/src/machine/machine_stm32l5.go (about) 1 //go:build stm32l5 2 3 package machine 4 5 // Peripheral abstraction layer for the stm32l5 6 7 import ( 8 "device/stm32" 9 "runtime/interrupt" 10 "runtime/volatile" 11 "unsafe" 12 ) 13 14 var deviceIDAddr = []uintptr{0x0BFA0590, 0x0BFA0594, 0x0BFA0598} 15 16 const ( 17 AF0_SYSTEM = 0 18 AF1_TIM1_2_5_8_LPTIM1 = 1 19 AF2_TIM1_2_3_4_5_LPTIM3 = 2 20 AF3_SPI2_SAI1_I2C4_USART2_TIM1_8_OCTOSPI1 = 3 21 AF4_I2C1_2_3_4 = 4 22 AF5_SPI1_2_3_I2C4_DFSDM1_OCTOSPI1 = 5 23 AF6_SPI3_I2C3_DFSDM1_COMP1 = 6 24 AF7_USART1_2_3 = 7 25 AF8_UART4_5_LPUART1_SDMMC1 = 8 26 AF9_FDCAN1_TSC = 9 27 AF10_USB_OCTOSPI1 = 10 28 AF11_UCPD1 = 11 29 AF12_SDMMC1_COMP1_2_TIM1_8_FMC = 12 30 AF13_SAI1_2_TIM8 = 13 31 AF14_TIM2_8_15_16_17_LPTIM2 = 14 32 AF15_EVENTOUT = 15 33 ) 34 35 const ( 36 PA0 = portA + 0 37 PA1 = portA + 1 38 PA2 = portA + 2 39 PA3 = portA + 3 40 PA4 = portA + 4 41 PA5 = portA + 5 42 PA6 = portA + 6 43 PA7 = portA + 7 44 PA8 = portA + 8 45 PA9 = portA + 9 46 PA10 = portA + 10 47 PA11 = portA + 11 48 PA12 = portA + 12 49 PA13 = portA + 13 50 PA14 = portA + 14 51 PA15 = portA + 15 52 53 PB0 = portB + 0 54 PB1 = portB + 1 55 PB2 = portB + 2 56 PB3 = portB + 3 57 PB4 = portB + 4 58 PB5 = portB + 5 59 PB6 = portB + 6 60 PB7 = portB + 7 61 PB8 = portB + 8 62 PB9 = portB + 9 63 PB10 = portB + 10 64 PB11 = portB + 11 65 PB12 = portB + 12 66 PB13 = portB + 13 67 PB14 = portB + 14 68 PB15 = portB + 15 69 70 PC0 = portC + 0 71 PC1 = portC + 1 72 PC2 = portC + 2 73 PC3 = portC + 3 74 PC4 = portC + 4 75 PC5 = portC + 5 76 PC6 = portC + 6 77 PC7 = portC + 7 78 PC8 = portC + 8 79 PC9 = portC + 9 80 PC10 = portC + 10 81 PC11 = portC + 11 82 PC12 = portC + 12 83 PC13 = portC + 13 84 PC14 = portC + 14 85 PC15 = portC + 15 86 87 PD0 = portD + 0 88 PD1 = portD + 1 89 PD2 = portD + 2 90 PD3 = portD + 3 91 PD4 = portD + 4 92 PD5 = portD + 5 93 PD6 = portD + 6 94 PD7 = portD + 7 95 PD8 = portD + 8 96 PD9 = portD + 9 97 PD10 = portD + 10 98 PD11 = portD + 11 99 PD12 = portD + 12 100 PD13 = portD + 13 101 PD14 = portD + 14 102 PD15 = portD + 15 103 104 PE0 = portE + 0 105 PE1 = portE + 1 106 PE2 = portE + 2 107 PE3 = portE + 3 108 PE4 = portE + 4 109 PE5 = portE + 5 110 PE6 = portE + 6 111 PE7 = portE + 7 112 PE8 = portE + 8 113 PE9 = portE + 9 114 PE10 = portE + 10 115 PE11 = portE + 11 116 PE12 = portE + 12 117 PE13 = portE + 13 118 PE14 = portE + 14 119 PE15 = portE + 15 120 121 PF0 = portF + 0 122 PF1 = portF + 1 123 PF2 = portF + 2 124 PF3 = portF + 3 125 PF4 = portF + 4 126 PF5 = portF + 5 127 PF6 = portF + 6 128 PF7 = portF + 7 129 PF8 = portF + 8 130 PF9 = portF + 9 131 PF10 = portF + 10 132 PF11 = portF + 11 133 PF12 = portF + 12 134 PF13 = portF + 13 135 PF14 = portF + 14 136 PF15 = portF + 15 137 138 PG0 = portG + 0 139 PG1 = portG + 1 140 PG2 = portG + 2 141 PG3 = portG + 3 142 PG4 = portG + 4 143 PG5 = portG + 5 144 PG6 = portG + 6 145 PG7 = portG + 7 146 PG8 = portG + 8 147 PG9 = portG + 9 148 PG10 = portG + 10 149 PG11 = portG + 11 150 PG12 = portG + 12 151 PG13 = portG + 13 152 PG14 = portG + 14 153 PG15 = portG + 15 154 155 PH0 = portH + 0 156 PH1 = portH + 1 157 ) 158 159 func (p Pin) getPort() *stm32.GPIO_Type { 160 switch p / 16 { 161 case 0: 162 return stm32.GPIOA 163 case 1: 164 return stm32.GPIOB 165 case 2: 166 return stm32.GPIOC 167 case 3: 168 return stm32.GPIOD 169 case 4: 170 return stm32.GPIOE 171 case 5: 172 return stm32.GPIOF 173 case 6: 174 return stm32.GPIOG 175 case 7: 176 return stm32.GPIOH 177 default: 178 panic("machine: unknown port") 179 } 180 } 181 182 // enableClock enables the clock for this desired GPIO port. 183 func (p Pin) enableClock() { 184 switch p / 16 { 185 case 0: 186 stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOAEN) 187 case 1: 188 stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOBEN) 189 case 2: 190 stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOCEN) 191 case 3: 192 stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIODEN) 193 case 4: 194 stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOEEN) 195 case 5: 196 stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOFEN) 197 case 6: 198 stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOGEN) 199 case 7: 200 stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOHEN) 201 default: 202 panic("machine: unknown port") 203 } 204 } 205 206 // Enable peripheral clock 207 func enableAltFuncClock(bus unsafe.Pointer) { 208 switch bus { 209 case unsafe.Pointer(stm32.DAC): // DAC interface clock enable 210 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_DAC1EN) 211 case unsafe.Pointer(stm32.PWR): // Power interface clock enable 212 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_PWREN) 213 case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable 214 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C3EN) 215 case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable 216 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C2EN) 217 case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable 218 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C1EN) 219 case unsafe.Pointer(stm32.UART5): // UART5 clock enable 220 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_UART5EN) 221 case unsafe.Pointer(stm32.UART4): // UART4 clock enable 222 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_UART4EN) 223 case unsafe.Pointer(stm32.USART3): // USART3 clock enable 224 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART3EN) 225 case unsafe.Pointer(stm32.USART2): // USART2 clock enable 226 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART2EN) 227 case unsafe.Pointer(stm32.SPI3): // SPI3 clock enable 228 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SP3EN) 229 case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable 230 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SPI2EN) 231 case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable 232 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_WWDGEN) 233 case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable 234 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM7EN) 235 case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable 236 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM6EN) 237 case unsafe.Pointer(stm32.TIM5): // TIM5 clock enable 238 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM5EN) 239 case unsafe.Pointer(stm32.TIM4): // TIM4 clock enable 240 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM4EN) 241 case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable 242 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM3EN) 243 case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable 244 stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM2EN) 245 case unsafe.Pointer(stm32.UCPD1): // UCPD1 clock enable 246 stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_UCPD1EN) 247 case unsafe.Pointer(stm32.FDCAN1): // FDCAN1 clock enable 248 stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_FDCAN1EN) 249 case unsafe.Pointer(stm32.LPTIM3): // LPTIM3 clock enable 250 stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM3EN) 251 case unsafe.Pointer(stm32.LPTIM2): // LPTIM2 clock enable 252 stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM2EN) 253 case unsafe.Pointer(stm32.I2C4): // I2C4 clock enable 254 stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_I2C4EN) 255 case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable 256 stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPUART1EN) 257 case unsafe.Pointer(stm32.TIM17): // TIM17 clock enable 258 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM17EN) 259 case unsafe.Pointer(stm32.TIM16): // TIM16 clock enable 260 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM16EN) 261 case unsafe.Pointer(stm32.TIM15): // TIM15 clock enable 262 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM15EN) 263 case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable 264 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN) 265 case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable 266 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN) 267 case unsafe.Pointer(stm32.USART1): // USART1 clock enable 268 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN) 269 case unsafe.Pointer(stm32.TIM8): // TIM8 clock enable 270 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM8EN) 271 case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable 272 stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN) 273 } 274 } 275 276 func (p Pin) registerInterrupt() interrupt.Interrupt { 277 pin := uint8(p) % 16 278 279 switch pin { 280 case 0: 281 return interrupt.New(stm32.IRQ_EXTI0, func(interrupt.Interrupt) { handlePinInterrupt(0) }) 282 case 1: 283 return interrupt.New(stm32.IRQ_EXTI1, func(interrupt.Interrupt) { handlePinInterrupt(1) }) 284 case 2: 285 return interrupt.New(stm32.IRQ_EXTI2, func(interrupt.Interrupt) { handlePinInterrupt(2) }) 286 case 3: 287 return interrupt.New(stm32.IRQ_EXTI3, func(interrupt.Interrupt) { handlePinInterrupt(3) }) 288 case 4: 289 return interrupt.New(stm32.IRQ_EXTI4, func(interrupt.Interrupt) { handlePinInterrupt(4) }) 290 case 5: 291 return interrupt.New(stm32.IRQ_EXTI5, func(interrupt.Interrupt) { handlePinInterrupt(5) }) 292 case 6: 293 return interrupt.New(stm32.IRQ_EXTI6, func(interrupt.Interrupt) { handlePinInterrupt(6) }) 294 case 7: 295 return interrupt.New(stm32.IRQ_EXTI7, func(interrupt.Interrupt) { handlePinInterrupt(7) }) 296 case 8: 297 return interrupt.New(stm32.IRQ_EXTI8, func(interrupt.Interrupt) { handlePinInterrupt(8) }) 298 case 9: 299 return interrupt.New(stm32.IRQ_EXTI9, func(interrupt.Interrupt) { handlePinInterrupt(9) }) 300 case 10: 301 return interrupt.New(stm32.IRQ_EXTI10, func(interrupt.Interrupt) { handlePinInterrupt(10) }) 302 case 11: 303 return interrupt.New(stm32.IRQ_EXTI11, func(interrupt.Interrupt) { handlePinInterrupt(11) }) 304 case 12: 305 return interrupt.New(stm32.IRQ_EXTI12, func(interrupt.Interrupt) { handlePinInterrupt(12) }) 306 case 13: 307 return interrupt.New(stm32.IRQ_EXTI13, func(interrupt.Interrupt) { handlePinInterrupt(13) }) 308 case 14: 309 return interrupt.New(stm32.IRQ_EXTI14, func(interrupt.Interrupt) { handlePinInterrupt(14) }) 310 case 15: 311 return interrupt.New(stm32.IRQ_EXTI15, func(interrupt.Interrupt) { handlePinInterrupt(15) }) 312 } 313 314 return interrupt.Interrupt{} 315 } 316 317 func handlePinInterrupt(pin uint8) { 318 // The pin abstraction doesn't differentiate pull-up 319 // events from pull-down events, so combine them to 320 // a single call here. 321 322 if stm32.EXTI.RPR1.HasBits(1<<pin) || stm32.EXTI.FPR1.HasBits(1<<pin) { 323 // Writing 1 to the pending register clears the 324 // pending flag for that bit 325 stm32.EXTI.RPR1.Set(1 << pin) 326 stm32.EXTI.FPR1.Set(1 << pin) 327 328 callback := pinCallbacks[pin] 329 if callback != nil { 330 callback(interruptPins[pin]) 331 } 332 } 333 } 334 335 //---------- Timer related code 336 337 var ( 338 TIM1 = TIM{ 339 EnableRegister: &stm32.RCC.APB2ENR, 340 EnableFlag: stm32.RCC_APB2ENR_TIM1EN, 341 Device: stm32.TIM1, 342 Channels: [4]TimerChannel{ 343 TimerChannel{Pins: []PinFunction{{PA8, AF1_TIM1_2_5_8_LPTIM1}, {PE9, AF1_TIM1_2_5_8_LPTIM1}}}, 344 TimerChannel{Pins: []PinFunction{{PA9, AF1_TIM1_2_5_8_LPTIM1}, {PE11, AF1_TIM1_2_5_8_LPTIM1}}}, 345 TimerChannel{Pins: []PinFunction{{PA10, AF1_TIM1_2_5_8_LPTIM1}, {PE13, AF1_TIM1_2_5_8_LPTIM1}}}, 346 TimerChannel{Pins: []PinFunction{{PA11, AF1_TIM1_2_5_8_LPTIM1}, {PE14, AF1_TIM1_2_5_8_LPTIM1}}}, 347 }, 348 busFreq: APB2_TIM_FREQ, 349 } 350 351 TIM2 = TIM{ 352 EnableRegister: &stm32.RCC.APB1ENR1, 353 EnableFlag: stm32.RCC_APB1ENR1_TIM2EN, 354 Device: stm32.TIM2, 355 Channels: [4]TimerChannel{ 356 TimerChannel{Pins: []PinFunction{{PA0, AF1_TIM1_2_5_8_LPTIM1}, {PA5, AF1_TIM1_2_5_8_LPTIM1}, {PA15, AF1_TIM1_2_5_8_LPTIM1}}}, 357 TimerChannel{Pins: []PinFunction{{PA1, AF1_TIM1_2_5_8_LPTIM1}, {PB3, AF1_TIM1_2_5_8_LPTIM1}}}, 358 TimerChannel{Pins: []PinFunction{{PA2, AF1_TIM1_2_5_8_LPTIM1}, {PB10, AF1_TIM1_2_5_8_LPTIM1}}}, 359 TimerChannel{Pins: []PinFunction{{PA3, AF1_TIM1_2_5_8_LPTIM1}, {PB11, AF1_TIM1_2_5_8_LPTIM1}}}, 360 }, 361 busFreq: APB1_TIM_FREQ, 362 } 363 364 TIM3 = TIM{ 365 EnableRegister: &stm32.RCC.APB1ENR1, 366 EnableFlag: stm32.RCC_APB1ENR1_TIM3EN, 367 Device: stm32.TIM3, 368 Channels: [4]TimerChannel{ 369 TimerChannel{Pins: []PinFunction{{PA6, AF2_TIM1_2_3_4_5_LPTIM3}, {PB4, AF2_TIM1_2_3_4_5_LPTIM3}, {PC6, AF2_TIM1_2_3_4_5_LPTIM3}, {PE3, AF2_TIM1_2_3_4_5_LPTIM3}}}, 370 TimerChannel{Pins: []PinFunction{{PA7, AF2_TIM1_2_3_4_5_LPTIM3}, {PB5, AF2_TIM1_2_3_4_5_LPTIM3}, {PC7, AF2_TIM1_2_3_4_5_LPTIM3}, {PE4, AF2_TIM1_2_3_4_5_LPTIM3}}}, 371 TimerChannel{Pins: []PinFunction{{PB0, AF2_TIM1_2_3_4_5_LPTIM3}, {PC8, AF2_TIM1_2_3_4_5_LPTIM3}, {PE5, AF2_TIM1_2_3_4_5_LPTIM3}}}, 372 TimerChannel{Pins: []PinFunction{{PB1, AF2_TIM1_2_3_4_5_LPTIM3}, {PC9, AF2_TIM1_2_3_4_5_LPTIM3}, {PE6, AF2_TIM1_2_3_4_5_LPTIM3}}}, 373 }, 374 busFreq: APB1_TIM_FREQ, 375 } 376 377 TIM4 = TIM{ 378 EnableRegister: &stm32.RCC.APB1ENR1, 379 EnableFlag: stm32.RCC_APB1ENR1_TIM4EN, 380 Device: stm32.TIM4, 381 Channels: [4]TimerChannel{ 382 TimerChannel{Pins: []PinFunction{{PB6, AF2_TIM1_2_3_4_5_LPTIM3}, {PD12, AF2_TIM1_2_3_4_5_LPTIM3}}}, 383 TimerChannel{Pins: []PinFunction{{PB7, AF2_TIM1_2_3_4_5_LPTIM3}, {PD13, AF2_TIM1_2_3_4_5_LPTIM3}}}, 384 TimerChannel{Pins: []PinFunction{{PB8, AF2_TIM1_2_3_4_5_LPTIM3}, {PD14, AF2_TIM1_2_3_4_5_LPTIM3}}}, 385 TimerChannel{Pins: []PinFunction{{PB9, AF2_TIM1_2_3_4_5_LPTIM3}, {PD15, AF2_TIM1_2_3_4_5_LPTIM3}}}, 386 }, 387 busFreq: APB1_TIM_FREQ, 388 } 389 390 TIM5 = TIM{ 391 EnableRegister: &stm32.RCC.APB1ENR1, 392 EnableFlag: stm32.RCC_APB1ENR1_TIM5EN, 393 Device: stm32.TIM5, 394 Channels: [4]TimerChannel{ 395 TimerChannel{Pins: []PinFunction{{PA0, AF2_TIM1_2_3_4_5_LPTIM3}, {PF6, AF2_TIM1_2_3_4_5_LPTIM3}}}, 396 TimerChannel{Pins: []PinFunction{{PA1, AF2_TIM1_2_3_4_5_LPTIM3}, {PF7, AF2_TIM1_2_3_4_5_LPTIM3}}}, 397 TimerChannel{Pins: []PinFunction{{PA2, AF2_TIM1_2_3_4_5_LPTIM3}, {PF8, AF2_TIM1_2_3_4_5_LPTIM3}}}, 398 TimerChannel{Pins: []PinFunction{{PA3, AF2_TIM1_2_3_4_5_LPTIM3}, {PF9, AF2_TIM1_2_3_4_5_LPTIM3}}}, 399 }, 400 busFreq: APB1_TIM_FREQ, 401 } 402 403 TIM6 = TIM{ 404 EnableRegister: &stm32.RCC.APB1ENR1, 405 EnableFlag: stm32.RCC_APB1ENR1_TIM6EN, 406 Device: stm32.TIM6, 407 Channels: [4]TimerChannel{ 408 TimerChannel{Pins: []PinFunction{}}, 409 TimerChannel{Pins: []PinFunction{}}, 410 TimerChannel{Pins: []PinFunction{}}, 411 TimerChannel{Pins: []PinFunction{}}, 412 }, 413 busFreq: APB1_TIM_FREQ, 414 } 415 416 TIM7 = TIM{ 417 EnableRegister: &stm32.RCC.APB1ENR1, 418 EnableFlag: stm32.RCC_APB1ENR1_TIM7EN, 419 Device: stm32.TIM7, 420 Channels: [4]TimerChannel{ 421 TimerChannel{Pins: []PinFunction{}}, 422 TimerChannel{Pins: []PinFunction{}}, 423 TimerChannel{Pins: []PinFunction{}}, 424 TimerChannel{Pins: []PinFunction{}}, 425 }, 426 busFreq: APB1_TIM_FREQ, 427 } 428 429 TIM8 = TIM{ 430 EnableRegister: &stm32.RCC.APB2ENR, 431 EnableFlag: stm32.RCC_APB2ENR_TIM8EN, 432 Device: stm32.TIM8, 433 Channels: [4]TimerChannel{ 434 TimerChannel{Pins: []PinFunction{{PC6, AF3_SPI2_SAI1_I2C4_USART2_TIM1_8_OCTOSPI1}}}, 435 TimerChannel{Pins: []PinFunction{{PC7, AF3_SPI2_SAI1_I2C4_USART2_TIM1_8_OCTOSPI1}}}, 436 TimerChannel{Pins: []PinFunction{{PC8, AF3_SPI2_SAI1_I2C4_USART2_TIM1_8_OCTOSPI1}}}, 437 TimerChannel{Pins: []PinFunction{{PC9, AF3_SPI2_SAI1_I2C4_USART2_TIM1_8_OCTOSPI1}}}, 438 }, 439 busFreq: APB2_TIM_FREQ, 440 } 441 442 TIM15 = TIM{ 443 EnableRegister: &stm32.RCC.APB2ENR, 444 EnableFlag: stm32.RCC_APB2ENR_TIM15EN, 445 Device: stm32.TIM15, 446 Channels: [4]TimerChannel{ 447 TimerChannel{Pins: []PinFunction{{PA1, AF14_TIM2_8_15_16_17_LPTIM2}, {PB14, AF14_TIM2_8_15_16_17_LPTIM2}, {PF9, AF14_TIM2_8_15_16_17_LPTIM2}, {PG10, AF14_TIM2_8_15_16_17_LPTIM2}}}, 448 TimerChannel{Pins: []PinFunction{{PA2, AF14_TIM2_8_15_16_17_LPTIM2}, {PB15, AF14_TIM2_8_15_16_17_LPTIM2}, {PF10, AF14_TIM2_8_15_16_17_LPTIM2}, {PG11, AF14_TIM2_8_15_16_17_LPTIM2}}}, 449 TimerChannel{Pins: []PinFunction{}}, 450 TimerChannel{Pins: []PinFunction{}}, 451 }, 452 busFreq: APB2_TIM_FREQ, 453 } 454 455 TIM16 = TIM{ 456 EnableRegister: &stm32.RCC.APB2ENR, 457 EnableFlag: stm32.RCC_APB2ENR_TIM16EN, 458 Device: stm32.TIM16, 459 Channels: [4]TimerChannel{ 460 TimerChannel{Pins: []PinFunction{{PA6, AF14_TIM2_8_15_16_17_LPTIM2}, {PB8, AF14_TIM2_8_15_16_17_LPTIM2}, {PE0, AF14_TIM2_8_15_16_17_LPTIM2}}}, 461 TimerChannel{Pins: []PinFunction{}}, 462 TimerChannel{Pins: []PinFunction{}}, 463 TimerChannel{Pins: []PinFunction{}}, 464 }, 465 busFreq: APB2_TIM_FREQ, 466 } 467 468 TIM17 = TIM{ 469 EnableRegister: &stm32.RCC.APB2ENR, 470 EnableFlag: stm32.RCC_APB2ENR_TIM17EN, 471 Device: stm32.TIM17, 472 Channels: [4]TimerChannel{ 473 TimerChannel{Pins: []PinFunction{{PA7, AF14_TIM2_8_15_16_17_LPTIM2}, {PB9, AF14_TIM2_8_15_16_17_LPTIM2}, {PE1, AF14_TIM2_8_15_16_17_LPTIM2}}}, 474 TimerChannel{Pins: []PinFunction{}}, 475 TimerChannel{Pins: []PinFunction{}}, 476 TimerChannel{Pins: []PinFunction{}}, 477 }, 478 busFreq: APB2_TIM_FREQ, 479 } 480 ) 481 482 func (t *TIM) registerUPInterrupt() interrupt.Interrupt { 483 switch t { 484 case &TIM1: 485 return interrupt.New(stm32.IRQ_TIM1_UP, TIM1.handleUPInterrupt) 486 case &TIM2: 487 return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt) 488 case &TIM3: 489 return interrupt.New(stm32.IRQ_TIM3, TIM3.handleUPInterrupt) 490 case &TIM4: 491 return interrupt.New(stm32.IRQ_TIM4, TIM4.handleUPInterrupt) 492 case &TIM5: 493 return interrupt.New(stm32.IRQ_TIM5, TIM5.handleUPInterrupt) 494 case &TIM6: 495 return interrupt.New(stm32.IRQ_TIM6, TIM6.handleUPInterrupt) 496 case &TIM7: 497 return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt) 498 case &TIM8: 499 return interrupt.New(stm32.IRQ_TIM8_UP, TIM8.handleUPInterrupt) 500 case &TIM15: 501 return interrupt.New(stm32.IRQ_TIM15, TIM15.handleUPInterrupt) 502 case &TIM16: 503 return interrupt.New(stm32.IRQ_TIM16, TIM16.handleUPInterrupt) 504 case &TIM17: 505 return interrupt.New(stm32.IRQ_TIM17, TIM17.handleUPInterrupt) 506 } 507 508 return interrupt.Interrupt{} 509 } 510 511 func (t *TIM) registerOCInterrupt() interrupt.Interrupt { 512 switch t { 513 case &TIM1: 514 return interrupt.New(stm32.IRQ_TIM1_CC, TIM1.handleOCInterrupt) 515 case &TIM2: 516 return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt) 517 case &TIM3: 518 return interrupt.New(stm32.IRQ_TIM3, TIM3.handleOCInterrupt) 519 case &TIM4: 520 return interrupt.New(stm32.IRQ_TIM4, TIM4.handleOCInterrupt) 521 case &TIM5: 522 return interrupt.New(stm32.IRQ_TIM5, TIM5.handleOCInterrupt) 523 case &TIM6: 524 return interrupt.New(stm32.IRQ_TIM6, TIM6.handleOCInterrupt) 525 case &TIM7: 526 return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt) 527 case &TIM8: 528 return interrupt.New(stm32.IRQ_TIM8_CC, TIM8.handleOCInterrupt) 529 case &TIM15: 530 return interrupt.New(stm32.IRQ_TIM15, TIM15.handleOCInterrupt) 531 case &TIM16: 532 return interrupt.New(stm32.IRQ_TIM16, TIM16.handleOCInterrupt) 533 case &TIM17: 534 return interrupt.New(stm32.IRQ_TIM17, TIM17.handleOCInterrupt) 535 } 536 537 return interrupt.Interrupt{} 538 } 539 540 func (t *TIM) enableMainOutput() { 541 t.Device.BDTR.SetBits(stm32.TIM_BDTR_MOE) 542 } 543 544 type arrtype = uint32 545 type arrRegType = volatile.Register32 546 547 const ( 548 ARR_MAX = 0x10000 549 PSC_MAX = 0x10000 550 ) 551 552 func initRNG() { 553 stm32.RCC.CRRCR.SetBits(stm32.RCC_CRRCR_HSI48ON) 554 for !stm32.RCC.CRRCR.HasBits(stm32.RCC_CRRCR_HSI48RDY) { 555 } 556 557 stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_RNGEN) 558 stm32.RNG.CR.SetBits(stm32.RNG_CR_RNGEN) 559 }