github.com/ttpreport/gvisor-ligolo@v0.0.0-20240123134145-a858404967ba/pkg/cpuid/features_arm64.go (about)

     1  // Copyright 2020 The gVisor Authors.
     2  //
     3  // Licensed under the Apache License, Version 2.0 (the "License");
     4  // you may not use this file except in compliance with the License.
     5  // You may obtain a copy of the License at
     6  //
     7  //     http://www.apache.org/licenses/LICENSE-2.0
     8  //
     9  // Unless required by applicable law or agreed to in writing, software
    10  // distributed under the License is distributed on an "AS IS" BASIS,
    11  // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    12  // See the License for the specific language governing permissions and
    13  // limitations under the License.
    14  
    15  //go:build arm64
    16  // +build arm64
    17  
    18  package cpuid
    19  
    20  const (
    21  	// ARM64FeatureFP indicates support for single and double precision
    22  	// float point types.
    23  	ARM64FeatureFP Feature = iota
    24  
    25  	// ARM64FeatureASIMD indicates support for Advanced SIMD with single
    26  	// and double precision float point arithmetic.
    27  	ARM64FeatureASIMD
    28  
    29  	// ARM64FeatureEVTSTRM indicates support for the generic timer
    30  	// configured to generate events at a frequency of approximately
    31  	// 100KHz.
    32  	ARM64FeatureEVTSTRM
    33  
    34  	// ARM64FeatureAES indicates support for AES instructions
    35  	// (AESE/AESD/AESMC/AESIMC).
    36  	ARM64FeatureAES
    37  
    38  	// ARM64FeaturePMULL indicates support for AES instructions
    39  	// (PMULL/PMULL2).
    40  	ARM64FeaturePMULL
    41  
    42  	// ARM64FeatureSHA1 indicates support for SHA1 instructions
    43  	// (SHA1C/SHA1P/SHA1M etc).
    44  	ARM64FeatureSHA1
    45  
    46  	// ARM64FeatureSHA2 indicates support for SHA2 instructions
    47  	// (SHA256H/SHA256H2/SHA256SU0 etc).
    48  	ARM64FeatureSHA2
    49  
    50  	// ARM64FeatureCRC32 indicates support for CRC32 instructions
    51  	// (CRC32B/CRC32H/CRC32W etc).
    52  	ARM64FeatureCRC32
    53  
    54  	// ARM64FeatureATOMICS indicates support for atomic instructions
    55  	// (LDADD/LDCLR/LDEOR/LDSET etc).
    56  	ARM64FeatureATOMICS
    57  
    58  	// ARM64FeatureFPHP indicates support for half precision float point
    59  	// arithmetic.
    60  	ARM64FeatureFPHP
    61  
    62  	// ARM64FeatureASIMDHP indicates support for ASIMD with half precision
    63  	// float point arithmetic.
    64  	ARM64FeatureASIMDHP
    65  
    66  	// ARM64FeatureCPUID indicates support for EL0 access to certain ID
    67  	// registers is available.
    68  	ARM64FeatureCPUID
    69  
    70  	// ARM64FeatureASIMDRDM indicates support for SQRDMLAH and SQRDMLSH
    71  	// instructions.
    72  	ARM64FeatureASIMDRDM
    73  
    74  	// ARM64FeatureJSCVT indicates support for the FJCVTZS instruction.
    75  	ARM64FeatureJSCVT
    76  
    77  	// ARM64FeatureFCMA indicates support for the FCMLA and FCADD
    78  	// instructions.
    79  	ARM64FeatureFCMA
    80  
    81  	// ARM64FeatureLRCPC indicates support for the LDAPRB/LDAPRH/LDAPR
    82  	// instructions.
    83  	ARM64FeatureLRCPC
    84  
    85  	// ARM64FeatureDCPOP indicates support for DC instruction (DC CVAP).
    86  	ARM64FeatureDCPOP
    87  
    88  	// ARM64FeatureSHA3 indicates support for SHA3 instructions
    89  	// (EOR3/RAX1/XAR/BCAX).
    90  	ARM64FeatureSHA3
    91  
    92  	// ARM64FeatureSM3 indicates support for SM3 instructions
    93  	// (SM3SS1/SM3TT1A/SM3TT1B).
    94  	ARM64FeatureSM3
    95  
    96  	// ARM64FeatureSM4 indicates support for SM4 instructions
    97  	// (SM4E/SM4EKEY).
    98  	ARM64FeatureSM4
    99  
   100  	// ARM64FeatureASIMDDP indicates support for dot product instructions
   101  	// (UDOT/SDOT).
   102  	ARM64FeatureASIMDDP
   103  
   104  	// ARM64FeatureSHA512 indicates support for SHA2 instructions
   105  	// (SHA512H/SHA512H2/SHA512SU0).
   106  	ARM64FeatureSHA512
   107  
   108  	// ARM64FeatureSVE indicates support for Scalable Vector Extension.
   109  	ARM64FeatureSVE
   110  
   111  	// ARM64FeatureASIMDFHM indicates support for FMLAL and FMLSL
   112  	// instructions.
   113  	ARM64FeatureASIMDFHM
   114  )
   115  
   116  var allFeatures = map[Feature]allFeatureInfo{
   117  	ARM64FeatureFP:       {"fp", true},
   118  	ARM64FeatureASIMD:    {"asimd", true},
   119  	ARM64FeatureEVTSTRM:  {"evtstrm", true},
   120  	ARM64FeatureAES:      {"aes", true},
   121  	ARM64FeaturePMULL:    {"pmull", true},
   122  	ARM64FeatureSHA1:     {"sha1", true},
   123  	ARM64FeatureSHA2:     {"sha2", true},
   124  	ARM64FeatureCRC32:    {"crc32", true},
   125  	ARM64FeatureATOMICS:  {"atomics", true},
   126  	ARM64FeatureFPHP:     {"fphp", true},
   127  	ARM64FeatureASIMDHP:  {"asimdhp", true},
   128  	ARM64FeatureCPUID:    {"cpuid", true},
   129  	ARM64FeatureASIMDRDM: {"asimdrdm", true},
   130  	ARM64FeatureJSCVT:    {"jscvt", true},
   131  	ARM64FeatureFCMA:     {"fcma", true},
   132  	ARM64FeatureLRCPC:    {"lrcpc", true},
   133  	ARM64FeatureDCPOP:    {"dcpop", true},
   134  	ARM64FeatureSHA3:     {"sha3", true},
   135  	ARM64FeatureSM3:      {"sm3", true},
   136  	ARM64FeatureSM4:      {"sm4", true},
   137  	ARM64FeatureASIMDDP:  {"asimddp", true},
   138  	ARM64FeatureSHA512:   {"sha512", true},
   139  	ARM64FeatureSVE:      {"sve", true},
   140  	ARM64FeatureASIMDFHM: {"asimdfhm", true},
   141  }
   142  
   143  func archFlagOrder(fn func(Feature)) {
   144  	for i := 0; i < len(allFeatures); i++ {
   145  		fn(Feature(i))
   146  	}
   147  }