github.com/u-root/u-root@v7.0.1-0.20200915234505-ad7babab0a8e+incompatible/pkg/msr/intel.go (about)

     1  // Copyright 2012-2020 the u-root Authors. All rights reserved
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package msr
     6  
     7  const (
     8  	// This is Intel's name. It makes no sense: this register is present
     9  	// in 64-bit CPUs.
    10  	IntelIA32FeatureControl  MSR = 0x3A  // MSR_IA32_FEATURE_CONTROL
    11  	IntelPkgCstConfigControl MSR = 0xE2  // MSR_PKG_CST_CONFIG_CONTROL
    12  	IntelFeatureConfig       MSR = 0x13c // MSR_FEATURE_CONFIG
    13  	IntelDramPowerLimit      MSR = 0x618 // MSR_DRAM_POWER_LIMIT
    14  	IntelConfigTDPControl    MSR = 0x64B // MSR_CONFIG_TDP_CONTROL
    15  	IntelIA32DebugInterface  MSR = 0xC80 // IA32_DEBUG_INTERFACE
    16  )
    17  
    18  var LockIntel = []MSRVal{
    19  	{
    20  		// Architectural MSR. All systems.
    21  		// Enables features like VMX.
    22  		Addr: IntelIA32FeatureControl,
    23  		Name: "IntelIA32FeatureControl",
    24  		Set:  1 << 0, // Locks this register.
    25  	},
    26  	{
    27  		// Silvermont, Airmont, Nehalem...
    28  		// Controls Processor C States.
    29  		Addr: IntelPkgCstConfigControl,
    30  		Name: "IntelPkgCstConfigControl",
    31  		Set:  1 << 15, // Locks this register.
    32  	},
    33  	{
    34  		// Westmere onwards.
    35  		// Note that this turns on AES instructions, however
    36  		// 3 will turn off AES until reset.
    37  		Addr: IntelFeatureConfig,
    38  		Name: "IntelFeatureConfig",
    39  		Set:  1 << 0,
    40  	},
    41  	{
    42  		// Goldmont, SandyBridge
    43  		// Controls DRAM power limits. See Intel SDM
    44  		Addr: IntelDramPowerLimit,
    45  		Name: "IntelDramPowerLimit",
    46  		Set:  1 << 31, // Locks this register.
    47  	},
    48  	{
    49  		// IvyBridge Onwards.
    50  		// Not much information in the SDM, seems to control power limits
    51  		Addr: IntelConfigTDPControl,
    52  		Name: "IntelConfigTDPControl",
    53  		Set:  1 << 31, // Locks this register.
    54  	},
    55  	{
    56  		// Architectural MSR. All systems.
    57  		// This is the actual spelling of the MSR in the manual.
    58  		// Controls availability of silicon debug interfaces
    59  		Addr: IntelIA32DebugInterface,
    60  		Name: "IntelIA32DebugInterface",
    61  		Set:  1 << 30, // Locks this register.
    62  	},
    63  }