github.com/undoio/delve@v1.9.0/pkg/proc/amd64_disasm.go (about) 1 // TODO: disassembler support should be compiled in unconditionally, 2 // instead of being decided by the build-target architecture, and be 3 // part of the Arch object instead. 4 5 package proc 6 7 import ( 8 "github.com/undoio/delve/pkg/dwarf/op" 9 "github.com/undoio/delve/pkg/dwarf/regnum" 10 11 "golang.org/x/arch/x86/x86asm" 12 ) 13 14 func amd64AsmDecode(asmInst *AsmInstruction, mem []byte, regs *op.DwarfRegisters, memrw MemoryReadWriter, bi *BinaryInfo) error { 15 return x86AsmDecode(asmInst, mem, regs, memrw, bi, 64) 16 } 17 18 // Possible stacksplit prologues are inserted by stacksplit in 19 // $GOROOT/src/cmd/internal/obj/x86/obj6.go. 20 // The stacksplit prologue will always begin with loading curg in CX, this 21 // instruction is added by load_g_cx in the same file and is either 1 or 2 22 // MOVs. 23 var prologuesAMD64 []opcodeSeq 24 25 func init() { 26 var tinyStacksplit = opcodeSeq{uint64(x86asm.CMP), uint64(x86asm.JBE)} 27 var smallStacksplit = opcodeSeq{uint64(x86asm.LEA), uint64(x86asm.CMP), uint64(x86asm.JBE)} 28 var bigStacksplit = opcodeSeq{uint64(x86asm.MOV), uint64(x86asm.CMP), uint64(x86asm.JE), uint64(x86asm.LEA), uint64(x86asm.SUB), uint64(x86asm.CMP), uint64(x86asm.JBE)} 29 var unixGetG = opcodeSeq{uint64(x86asm.MOV)} 30 var windowsGetG = opcodeSeq{uint64(x86asm.MOV), uint64(x86asm.MOV)} 31 32 prologuesAMD64 = make([]opcodeSeq, 0, 2*3) 33 for _, getG := range []opcodeSeq{unixGetG, windowsGetG} { 34 for _, stacksplit := range []opcodeSeq{tinyStacksplit, smallStacksplit, bigStacksplit} { 35 prologue := make(opcodeSeq, 0, len(getG)+len(stacksplit)) 36 prologue = append(prologue, getG...) 37 prologue = append(prologue, stacksplit...) 38 prologuesAMD64 = append(prologuesAMD64, prologue) 39 } 40 } 41 } 42 43 var amd64AsmRegisters = map[int]asmRegister{ 44 // 8-bit 45 int(x86asm.AL): asmRegister{regnum.AMD64_Rax, 0, mask8}, 46 int(x86asm.CL): asmRegister{regnum.AMD64_Rcx, 0, mask8}, 47 int(x86asm.DL): asmRegister{regnum.AMD64_Rdx, 0, mask8}, 48 int(x86asm.BL): asmRegister{regnum.AMD64_Rbx, 0, mask8}, 49 int(x86asm.AH): asmRegister{regnum.AMD64_Rax, 8, mask8}, 50 int(x86asm.CH): asmRegister{regnum.AMD64_Rcx, 8, mask8}, 51 int(x86asm.DH): asmRegister{regnum.AMD64_Rdx, 8, mask8}, 52 int(x86asm.BH): asmRegister{regnum.AMD64_Rbx, 8, mask8}, 53 int(x86asm.SPB): asmRegister{regnum.AMD64_Rsp, 0, mask8}, 54 int(x86asm.BPB): asmRegister{regnum.AMD64_Rbp, 0, mask8}, 55 int(x86asm.SIB): asmRegister{regnum.AMD64_Rsi, 0, mask8}, 56 int(x86asm.DIB): asmRegister{regnum.AMD64_Rdi, 0, mask8}, 57 int(x86asm.R8B): asmRegister{regnum.AMD64_R8, 0, mask8}, 58 int(x86asm.R9B): asmRegister{regnum.AMD64_R9, 0, mask8}, 59 int(x86asm.R10B): asmRegister{regnum.AMD64_R10, 0, mask8}, 60 int(x86asm.R11B): asmRegister{regnum.AMD64_R11, 0, mask8}, 61 int(x86asm.R12B): asmRegister{regnum.AMD64_R12, 0, mask8}, 62 int(x86asm.R13B): asmRegister{regnum.AMD64_R13, 0, mask8}, 63 int(x86asm.R14B): asmRegister{regnum.AMD64_R14, 0, mask8}, 64 int(x86asm.R15B): asmRegister{regnum.AMD64_R15, 0, mask8}, 65 66 // 16-bit 67 int(x86asm.AX): asmRegister{regnum.AMD64_Rax, 0, mask16}, 68 int(x86asm.CX): asmRegister{regnum.AMD64_Rcx, 0, mask16}, 69 int(x86asm.DX): asmRegister{regnum.AMD64_Rdx, 0, mask16}, 70 int(x86asm.BX): asmRegister{regnum.AMD64_Rbx, 0, mask16}, 71 int(x86asm.SP): asmRegister{regnum.AMD64_Rsp, 0, mask16}, 72 int(x86asm.BP): asmRegister{regnum.AMD64_Rbp, 0, mask16}, 73 int(x86asm.SI): asmRegister{regnum.AMD64_Rsi, 0, mask16}, 74 int(x86asm.DI): asmRegister{regnum.AMD64_Rdi, 0, mask16}, 75 int(x86asm.R8W): asmRegister{regnum.AMD64_R8, 0, mask16}, 76 int(x86asm.R9W): asmRegister{regnum.AMD64_R9, 0, mask16}, 77 int(x86asm.R10W): asmRegister{regnum.AMD64_R10, 0, mask16}, 78 int(x86asm.R11W): asmRegister{regnum.AMD64_R11, 0, mask16}, 79 int(x86asm.R12W): asmRegister{regnum.AMD64_R12, 0, mask16}, 80 int(x86asm.R13W): asmRegister{regnum.AMD64_R13, 0, mask16}, 81 int(x86asm.R14W): asmRegister{regnum.AMD64_R14, 0, mask16}, 82 int(x86asm.R15W): asmRegister{regnum.AMD64_R15, 0, mask16}, 83 84 // 32-bit 85 int(x86asm.EAX): asmRegister{regnum.AMD64_Rax, 0, mask32}, 86 int(x86asm.ECX): asmRegister{regnum.AMD64_Rcx, 0, mask32}, 87 int(x86asm.EDX): asmRegister{regnum.AMD64_Rdx, 0, mask32}, 88 int(x86asm.EBX): asmRegister{regnum.AMD64_Rbx, 0, mask32}, 89 int(x86asm.ESP): asmRegister{regnum.AMD64_Rsp, 0, mask32}, 90 int(x86asm.EBP): asmRegister{regnum.AMD64_Rbp, 0, mask32}, 91 int(x86asm.ESI): asmRegister{regnum.AMD64_Rsi, 0, mask32}, 92 int(x86asm.EDI): asmRegister{regnum.AMD64_Rdi, 0, mask32}, 93 int(x86asm.R8L): asmRegister{regnum.AMD64_R8, 0, mask32}, 94 int(x86asm.R9L): asmRegister{regnum.AMD64_R9, 0, mask32}, 95 int(x86asm.R10L): asmRegister{regnum.AMD64_R10, 0, mask32}, 96 int(x86asm.R11L): asmRegister{regnum.AMD64_R11, 0, mask32}, 97 int(x86asm.R12L): asmRegister{regnum.AMD64_R12, 0, mask32}, 98 int(x86asm.R13L): asmRegister{regnum.AMD64_R13, 0, mask32}, 99 int(x86asm.R14L): asmRegister{regnum.AMD64_R14, 0, mask32}, 100 int(x86asm.R15L): asmRegister{regnum.AMD64_R15, 0, mask32}, 101 102 // 64-bit 103 int(x86asm.RAX): asmRegister{regnum.AMD64_Rax, 0, 0}, 104 int(x86asm.RCX): asmRegister{regnum.AMD64_Rcx, 0, 0}, 105 int(x86asm.RDX): asmRegister{regnum.AMD64_Rdx, 0, 0}, 106 int(x86asm.RBX): asmRegister{regnum.AMD64_Rbx, 0, 0}, 107 int(x86asm.RSP): asmRegister{regnum.AMD64_Rsp, 0, 0}, 108 int(x86asm.RBP): asmRegister{regnum.AMD64_Rbp, 0, 0}, 109 int(x86asm.RSI): asmRegister{regnum.AMD64_Rsi, 0, 0}, 110 int(x86asm.RDI): asmRegister{regnum.AMD64_Rdi, 0, 0}, 111 int(x86asm.R8): asmRegister{regnum.AMD64_R8, 0, 0}, 112 int(x86asm.R9): asmRegister{regnum.AMD64_R9, 0, 0}, 113 int(x86asm.R10): asmRegister{regnum.AMD64_R10, 0, 0}, 114 int(x86asm.R11): asmRegister{regnum.AMD64_R11, 0, 0}, 115 int(x86asm.R12): asmRegister{regnum.AMD64_R12, 0, 0}, 116 int(x86asm.R13): asmRegister{regnum.AMD64_R13, 0, 0}, 117 int(x86asm.R14): asmRegister{regnum.AMD64_R14, 0, 0}, 118 int(x86asm.R15): asmRegister{regnum.AMD64_R15, 0, 0}, 119 }