github.com/usbarmory/tamago@v0.0.0-20240508072735-8612bbe1e454/arm/cache.go (about)

     1  // ARM processor support
     2  // https://github.com/usbarmory/tamago
     3  //
     4  // Copyright (c) WithSecure Corporation
     5  // https://foundry.withsecure.com
     6  //
     7  // Use of this source code is governed by the license
     8  // that can be found in the LICENSE file.
     9  
    10  package arm
    11  
    12  // ARM cache register constants
    13  const (
    14  	ACTLR_SMP = 6
    15  )
    16  
    17  // defined in cache.s
    18  func read_actlr() uint32
    19  func write_actlr(aux uint32)
    20  func cache_enable()
    21  func cache_disable()
    22  func cache_flush_data()
    23  func cache_flush_instruction()
    24  
    25  // EnableSMP sets the SMP bit in Cortex-A7 Auxiliary Control Register, to
    26  // enable coherent requests to the processor. This must be ensured before
    27  // caches and MMU are enabled or any cache and TLB maintenance operations are
    28  // performed (p115, Cortex™-A7 MPCore® Technical Reference Manual r0p5).
    29  func (cpu *CPU) EnableSMP() {
    30  	aux := read_actlr()
    31  	aux |= 1 << ACTLR_SMP
    32  	write_actlr(aux)
    33  }
    34  
    35  // EnableCache activates the ARM instruction and data caches.
    36  func (cpu *CPU) EnableCache() {
    37  	cache_enable()
    38  }
    39  
    40  // DisableCache disables the ARM instruction and data caches.
    41  func (cpu *CPU) DisableCache() {
    42  	cache_disable()
    43  }
    44  
    45  // FlushDataCache flushes the ARM data cache.
    46  func (cpu *CPU) FlushDataCache() {
    47  	cache_flush_data()
    48  }
    49  
    50  // FlushInstructionCache flushes the ARM instruction cache.
    51  func (cpu *CPU) FlushInstructionCache() {
    52  	cache_flush_instruction()
    53  }
    54  
    55  // FlushTLBs flushes the ARM Translation Lookaside Buffers.
    56  func (cpu *CPU) FlushTLBs() {
    57  	flush_tlb()
    58  }