github.com/usbarmory/tamago@v0.0.0-20240508072735-8612bbe1e454/board/qemu/sifive_u/qemu-riscv64-sifive_u.dts (about) 1 /dts-v1/; 2 3 / { 4 #address-cells = <0x02>; 5 #size-cells = <0x02>; 6 compatible = "sifive,hifive-unleashed-a00"; 7 model = "SiFive HiFive Unleashed A00"; 8 9 chosen { 10 bootargs = [00]; 11 stdout-path = "/soc/serial@10010000"; 12 }; 13 14 aliases { 15 serial0 = "/soc/serial@10010000"; 16 serial1 = "/soc/serial@10011000"; 17 ethernet0 = "/soc/ethernet@10090000"; 18 }; 19 20 gpio-restart { 21 compatible = "gpio-restart"; 22 gpios = <0x07 0x0a 0x01>; 23 }; 24 25 cpus { 26 #address-cells = <0x01>; 27 #size-cells = <0x00>; 28 timebase-frequency = <0xf4240>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 reg = <0x00>; 33 status = "okay"; 34 compatible = "riscv"; 35 riscv,isa = "rv64imafdcsu"; 36 mmu-type = "riscv,sv48"; 37 38 interrupt-controller { 39 #interrupt-cells = <0x01>; 40 interrupt-controller; 41 compatible = "riscv,cpu-intc"; 42 phandle = <0x04>; 43 }; 44 }; 45 }; 46 47 memory@80000000 { 48 device_type = "memory"; 49 reg = <0x00 0x80000000 0x00 0x8000000>; 50 }; 51 52 rtcclk { 53 #clock-cells = <0x00>; 54 compatible = "fixed-clock"; 55 clock-frequency = <0xf4240>; 56 clock-output-names = "rtcclk"; 57 phandle = <0x02>; 58 }; 59 60 hfclk { 61 #clock-cells = <0x00>; 62 compatible = "fixed-clock"; 63 clock-frequency = <0x1fca055>; 64 clock-output-names = "hfclk"; 65 phandle = <0x01>; 66 }; 67 68 soc { 69 #address-cells = <0x02>; 70 #size-cells = <0x02>; 71 compatible = "simple-bus"; 72 ranges; 73 74 serial@10010000 { 75 interrupts = <0x04>; 76 interrupt-parent = <0x06>; 77 clocks = <0x05 0x03>; 78 reg = <0x00 0x10010000 0x00 0x1000>; 79 compatible = "sifive,uart0"; 80 }; 81 82 serial@10011000 { 83 interrupts = <0x05>; 84 interrupt-parent = <0x06>; 85 clocks = <0x05 0x03>; 86 reg = <0x00 0x10011000 0x00 0x1000>; 87 compatible = "sifive,uart0"; 88 }; 89 90 pwm@10021000 { 91 #pwm-cells = <0x00>; 92 clocks = <0x05 0x03>; 93 interrupts = <0x2e 0x2f 0x30 0x31>; 94 interrupt-parent = <0x06>; 95 reg = <0x00 0x10021000 0x00 0x1000>; 96 compatible = "sifive,pwm0"; 97 }; 98 99 pwm@10020000 { 100 #pwm-cells = <0x00>; 101 clocks = <0x05 0x03>; 102 interrupts = <0x2a 0x2b 0x2c 0x2d>; 103 interrupt-parent = <0x06>; 104 reg = <0x00 0x10020000 0x00 0x1000>; 105 compatible = "sifive,pwm0"; 106 }; 107 108 ethernet@10090000 { 109 #size-cells = <0x00>; 110 #address-cells = <0x01>; 111 local-mac-address = [52 54 00 12 34 56]; 112 clock-names = "pclk\0hclk"; 113 clocks = <0x05 0x02 0x05 0x02>; 114 interrupts = <0x35>; 115 interrupt-parent = <0x06>; 116 phy-handle = <0x08>; 117 phy-mode = "gmii"; 118 reg-names = "control"; 119 reg = <0x00 0x10090000 0x00 0x2000 0x00 0x100a0000 0x00 0x1000>; 120 compatible = "sifive,fu540-c000-gem"; 121 122 ethernet-phy@0 { 123 reg = <0x00>; 124 phandle = <0x08>; 125 }; 126 }; 127 128 spi@10040000 { 129 compatible = "sifive,spi0"; 130 reg = <0x00 0x10040000 0x00 0x1000>; 131 interrupt-parent = <0x06>; 132 interrupts = <0x33>; 133 clocks = <0x05 0x03>; 134 #address-cells = <0x01>; 135 #size-cells = <0x00>; 136 137 flash@0 { 138 compatible = "jedec,spi-nor"; 139 reg = <0x00>; 140 spi-max-frequency = <0x2faf080>; 141 m25p,fast-read; 142 spi-tx-bus-width = <0x04>; 143 spi-rx-bus-width = <0x04>; 144 }; 145 }; 146 147 spi@10050000 { 148 compatible = "sifive,spi0"; 149 reg = <0x00 0x10050000 0x00 0x1000>; 150 interrupt-parent = <0x06>; 151 interrupts = <0x06>; 152 clocks = <0x05 0x03>; 153 #address-cells = <0x01>; 154 #size-cells = <0x00>; 155 156 mmc@0 { 157 compatible = "mmc-spi-slot"; 158 reg = <0x00>; 159 spi-max-frequency = <0x1312d00>; 160 voltage-ranges = <0xce4 0xce4>; 161 disable-wp; 162 }; 163 }; 164 165 cache-controller@2010000 { 166 compatible = "sifive,fu540-c000-ccache"; 167 cache-block-size = <0x40>; 168 cache-level = <0x02>; 169 cache-sets = <0x400>; 170 cache-size = <0x200000>; 171 cache-unified; 172 interrupt-parent = <0x06>; 173 interrupts = <0x01 0x02 0x03>; 174 reg = <0x00 0x2010000 0x00 0x1000>; 175 }; 176 177 dma@3000000 { 178 compatible = "sifive,fu540-c000-pdma"; 179 reg = <0x00 0x3000000 0x00 0x100000>; 180 interrupt-parent = <0x06>; 181 interrupts = <0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e>; 182 #dma-cells = <0x01>; 183 }; 184 185 gpio@10060000 { 186 compatible = "sifive,gpio0"; 187 interrupt-parent = <0x06>; 188 interrupts = <0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16>; 189 reg = <0x00 0x10060000 0x00 0x1000>; 190 gpio-controller; 191 #gpio-cells = <0x02>; 192 interrupt-controller; 193 #interrupt-cells = <0x02>; 194 clocks = <0x05 0x03>; 195 phandle = <0x07>; 196 }; 197 198 interrupt-controller@c000000 { 199 phandle = <0x06>; 200 riscv,ndev = <0x35>; 201 reg = <0x00 0xc000000 0x00 0x4000000>; 202 interrupts-extended = <0x04 0x0b 0x03 0x0b 0x03 0x09>; 203 interrupt-controller; 204 compatible = "sifive,plic-1.0.0\0riscv,plic0"; 205 #interrupt-cells = <0x01>; 206 }; 207 208 clock-controller@10000000 { 209 compatible = "sifive,fu540-c000-prci"; 210 reg = <0x00 0x10000000 0x00 0x1000>; 211 clocks = <0x01 0x02>; 212 #clock-cells = <0x01>; 213 phandle = <0x05>; 214 }; 215 216 otp@10070000 { 217 compatible = "sifive,fu540-c000-otp"; 218 reg = <0x00 0x10070000 0x00 0x1000>; 219 fuse-count = <0x1000>; 220 }; 221 222 clint@2000000 { 223 interrupts-extended = <0x04 0x03 0x04 0x07 0x03 0x03 0x03 0x07>; 224 reg = <0x00 0x2000000 0x00 0x10000>; 225 compatible = "sifive,clint0\0riscv,clint0"; 226 }; 227 }; 228 };