github.com/usbarmory/tamago@v0.0.0-20240508072735-8612bbe1e454/soc/nxp/csu/const.go (about) 1 // NXP i.MX Central Security Unit (CSU) driver 2 // https://github.com/usbarmory/tamago 3 // 4 // Copyright (c) WithSecure Corporation 5 // https://foundry.withsecure.com 6 // 7 // Use of this source code is governed by the license 8 // that can be found in the LICENSE file. 9 10 package csu 11 12 // p383, 11.2.3.1 CSU Peripheral Access Policy, IMX6ULLRM 13 const ( 14 // NonSecure User: RW, NonSecure Supervisor: RW, Secure User: RW, Secure Supervisor: RW 15 SEC_LEVEL_0 = 0b11111111 16 // NonSecure User: NA, NonSecure Supervisor: RW, Secure User: RW, Secure Supervisor: RW 17 SEC_LEVEL_1 = 0b10111011 18 // NonSecure User: RO, NonSecure Supervisor: RO, Secure User: RW, Secure Supervisor: RW 19 SEC_LEVEL_2 = 0b00111111 20 // NonSecure User: NA, NonSecure Supervisor: RO, Secure User: RW, Secure Supervisor: RW 21 SEC_LEVEL_3 = 0b00111011 22 // NonSecure User: NA, NonSecure Supervisor: NA, Secure User: RW, Secure Supervisor: RW 23 SEC_LEVEL_4 = 0b00110011 24 // NonSecure User: NA, NonSecure Supervisor: NA, Secure User: NA, Secure Supervisor: RW 25 SEC_LEVEL_5 = 0b00100010 26 // NonSecure User: NA, NonSecure Supervisor: NA, Secure User: RO, Secure Supervisor: RO 27 SEC_LEVEL_6 = 0b00000011 28 // NonSecure User: NA, NonSecure Supervisor: NA, Secure User: NA, Secure Supervisor: NA 29 SEC_LEVEL_7 = 0b00000000 30 31 // NonSecure Supervisor Write Access bit 32 CSL_NW_SUP_WR = 7 33 // NonSecure User Write Access bit 34 CSL_NW_USR_WR = 6 35 // Secure Supervisor Write Access bit 36 CSL_SW_SUP_WR = 5 37 // Secure User Write Access bit 38 CSL_SW_USR_WR = 4 39 // NonSecure Supervisor Read Access bit 40 CSL_NW_SUP_RD = 3 41 // NonSecure User Read Access bit 42 CSL_NW_USR_RD = 2 43 // Secure Supervisor Read Access bit 44 CSL_SW_SUP_RD = 1 45 // Secure User Read Access bit 46 CSL_SW_USR_RD = 0 47 ) 48 49 // The following peripheral, slave identifiers can be used to set the CSL using 50 // SetSecurityLevel on i.MX6 P/Ns. Note that peripherals presence depends on 51 // the specific P/Ns: 52 // 53 // | ID | Blocks (¹UL/ULL/ULZ, ²SX, ³SL, ⁴S/D/DL/Q) | 54 // |-------|-------------------------------------------------------------------------| 55 // | 0, 0 | PWM | 56 // | 0, 1 | CAN1¹²⁴, DBGMON³ | 57 // | 1, 0 | CAN2¹²⁴, QOS³ | 58 // | 1, 1 | GPT1, EPIT | 59 // | 2, 0 | GPIO1, GPIO2 | 60 // | 2, 1 | GPIO3, GPIO4 | 61 // | 3, 0 | GPIO5, GPIO6²⁴ | 62 // | 3, 1 | GPIO7²⁴, SNVS_LP¹ | 63 // | 4, 0 | KPP | 64 // | 4, 1 | WDOG1 | 65 // | 5, 0 | WDOG2 | 66 // | 5, 1 | CCM, SNVS_HP, SRC, GPC | 67 // | 6, 0 | ANATOP | 68 // | 6, 1 | IOMUXC | 69 // | 7, 0 | IOMUXC_GPR¹², CSI³, TCON³, DCIC⁴ | 70 // | 7, 1 | SDMA, EPDC⁴⁽ˢ⁄ᴰᴸ⁾, LCDIF⁴⁽ˢ⁄ᴰᴸ⁾, PXP⁴⁽ˢ⁄ᴰᴸ⁾ | 71 // | 8, 0 | USB | 72 // | 8, 1 | ENET¹²⁴, FEC³ | 73 // | 9, 0 | GPT2¹, MLB²⁴, MSHC³ | 74 // | 9, 1 | USDHC1 | 75 // | 10, 0 | USDHC2 | 76 // | 10, 1 | USDHC3²³⁴, SIM1¹⁽ᵁᴸ⁾ | 77 // | 11, 0 | USDHC4²³⁴, SIM2¹⁽ᵁᴸ⁾ | 78 // | 11, 1 | I2C1 | 79 // | 12, 0 | I2C2 | 80 // | 12, 1 | I2C3 | 81 // | 13, 0 | ROMCP | 82 // | 13, 1 | MMDC, DCP³, VPU⁴ | 83 // | 14, 0 | WEIM¹², EIM³⁴ | 84 // | 14, 1 | OCOTP_CTRL | 85 // | 15, 0 | SCTR¹, RDC² | 86 // | 15, 1 | SCTR¹, PERFMON²³⁴ | 87 // | 16, 0 | SCTR¹, DBGMON², TZASC1³⁴ | 88 // | 16, 1 | TZASC1¹, TZASC2²⁴, RNGB³ | 89 // | 17, 0 | AUDMUX²³⁴, SAI¹² | 90 // | 17, 1 | QSPI¹², ASRC¹, CAAM⁴ | 91 // | 18, 0 | SPDIF | 92 // | 18, 1 | eCSPI1 | 93 // | 19, 0 | eCSPI2 | 94 // | 19, 1 | eCSPI3 | 95 // | 20, 0 | eCSPI4, I2C4¹² | 96 // | 20, 1 | ecSPI5²⁴⁽ˢ⁄ᴰᴸ⁾, IPS_1TO4_MUX¹, UART5³ | 97 // | 21, 0 | UART1 | 98 // | 21, 1 | UART7¹, UART2³, ESAI²⁴ | 99 // | 22, 0 | UART8¹, ESAI¹⁽ᵁᴸᴸ⁄ᵁᴸᶻ⁾, SSI1²³⁴ | 100 // | 22, 1 | SSI2²³⁴ | 101 // | 23, 0 | SSI3²³⁴ | 102 // | 23, 1 | ASRC²⁴, UART3³ | 103 // | 24, 0 | CANFD² | 104 // | 24, 1 | RDC_SEMA4², ROMCP³⁴ | 105 // | 25, 0 | WDOG3¹² | 106 // | 25, 1 | ADC1¹² | 107 // | 26, 0 | ADC2¹², OCRAM³ | 108 // | 27, 0 | APBH_DMA⁴ | 109 // | 27, 1 | SEMA4², HDMI⁴ | 110 // | 28, 0 | IOMUXC_SNVS¹⁽ᵁᴸᴸ⁄ᵁᴸᶻ⁾, MU(A9)², GPU3D⁴ | 111 // | 28, 1 | IOMUXC_SNVS_GPR¹⁽ᵁᴸᴸ⁄ᵁᴸᶻ⁾, CANFD_MEM², PXP³, SATA⁴⁽ˢ⁄ᴰᴸ⁾ | 112 // | 29, 0 | UART8¹, MU(M4)², OPENVG³⁴⁽ˢ⁄ᴰᴸ⁾ | 113 // | 29, 1 | UART6¹², ARM³⁴ | 114 // | 30, 0 | UART2¹², EPDC³, HSI⁴ | 115 // | 30, 1 | UART3¹², IPU1⁴ | 116 // | 31, 0 | UART4¹², LCDIF³, IPU2⁴⁽ˢ⁄ᴰᴸ⁾ | 117 // | 31, 1 | UART5¹², EIM³, WEIM⁴ | 118 // | 32, 0 | LCDIF¹², CSI¹², PXP¹², EPDC¹⁽ᵁᴸᴸ⁄ᵁᴸᶻ⁾, VDEC², VADC², DCIC², GIS², PCIE⁴ | 119 // | 32, 1 | SPBA², GPU2D⁴ | 120 // | 33, 0 | SPBA¹², MIPI_CORE_CSI⁴ | 121 // | 33, 1 | TSC¹⁽ᵁᴸᴸ⁄ᵁᴸᶻ⁾, MIPI_CORE_HIS⁴ | 122 // | 34, 0 | DCP¹⁽ᵁᴸᴸ⁄ᵁᴸᶻ⁾, VDOA⁴ | 123 // | 34, 1 | RNGB¹⁽ᵁᴸᴸ⁄ᵁᴸᶻ⁾, OCRAM², UART2⁴ | 124 // | 35, 0 | UART3⁴ | 125 // | 35, 1 | UART4⁴ | 126 // | 36, 0 | UART5⁴⁽ˢ⁄ᴰᴸ⁾, I2C4⁴ | 127 // | 36, 1 | DTCP⁴ | 128 // | 38, 1 | UART4³ | 129 // | 39, 0 | SPBA³ | 130 // | 39, 1 | OCRAM¹ | 131 // 132 // ¹UL/ULL/ULZ, ²SX, ³SL, ⁴S/D/DL/Q 133 const ( 134 CSL_MIN = 0 135 CSL_MAX = 39 136 137 // Second slave 138 CSL_S2_LOCK = 24 139 CSL_S2 = 16 140 // First slave 141 CSL_S1_LOCK = 8 142 CSL_S1 = 0 143 ) 144 145 // The following master identifiers can be used to set the SA using 146 // SetAccess on i.MX6 P/Ns. Note that peripherals presence depends on 147 // the specific P/Ns: 148 // 149 // | ID | Blocks (¹UL/ULL/ULZ, ²SX, ³SL, ⁴S/D/DL/Q) | 150 // |-----|----------------------------------------------------------------| 151 // | 0 | CA7¹, CP15⁴ | 152 // | 1 | M4², DCP³, SATA⁴ | 153 // | 2 | SDMA | 154 // | 3 | PXP, CSI², LCDIF²³⁴, GPU²³⁴, EPDC³⁴, TCON³, VDOA⁴, IPU⁴, VPU⁴ | 155 // | 4 | USB, MLB⁴ | 156 // | 5 | TEST, PCIE²⁴ | 157 // | 6 | MLB², CSI³ | 158 // | 7 | RAWNAND_DMA¹²⁴, MSHC³ | 159 // | 8 | RAWNAND_APBH_DMA¹², FEC³, ENET⁴ | 160 // | 9 | ENET¹², DAP³⁴ | 161 // | 10 | USDHC1 | 162 // | 11 | USDHC2 | 163 // | 12 | USDHC3²³⁴ | 164 // | 13 | USDHC4²³⁴ | 165 // | 14 | DCP¹^, DAP¹, HDMI⁴, HSI⁴ | 166 // 167 // ^ULL/ULZ only, undocumented and found through testing, confirmed by NXP R&D. 168 const ( 169 SA_MIN = 0 170 SA_MAX = 15 171 )