github.com/wasilibs/wazerox@v0.0.0-20240124024944-4923be63ab5f/internal/asm/arm64/consts.go (about) 1 package arm64 2 3 import ( 4 "fmt" 5 6 "github.com/wasilibs/wazerox/internal/asm" 7 ) 8 9 // Arm64-specific register states. 10 // 11 // Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm 12 // See https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/condition-codes-1-condition-flags-and-codes 13 const ( 14 // CondEQ is the eq (equal) condition code 15 CondEQ = asm.ConditionalRegisterStateUnset + 1 + iota 16 // CondNE is the ne (not equal) condition code 17 CondNE 18 // CondHS is the hs (unsigned higher or same) condition code 19 CondHS 20 // CondLO is the lo (unsigned lower) condition code 21 CondLO 22 // CondMI is the mi (negative) condition code 23 CondMI 24 // CondPL is the pl (positive or zero) condition code 25 CondPL 26 // CondVS is the vs (signed overflow) condition code 27 CondVS 28 // CondVC is the vc (no signed overflow) condition code 29 CondVC 30 // CondHI is the hi (unsigned higher) condition code 31 CondHI 32 // CondLS is the ls (unsigned lower or same) condition code 33 CondLS 34 // CondGE is the ge (signed greater than or equal) condition code 35 CondGE 36 // CondLT is the lt (signed less than) condition code 37 CondLT 38 // CondGT is the gt (signed greater than) condition code 39 CondGT 40 // CondLE is the le (signed less than or equal) condition code 41 CondLE 42 // CondAL is the al (always executed) condition code 43 CondAL 44 // CondNV has the same meaning as CondAL 45 CondNV 46 ) 47 48 // Arm64-specific registers. 49 // 50 // Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm 51 // See https://developer.arm.com/documentation/dui0801/a/Overview-of-AArch64-state/Predeclared-core-register-names-in-AArch64-state 52 const ( 53 // Integer registers. 54 55 // RegR0 is the R0 register 56 RegR0 asm.Register = asm.NilRegister + 1 + iota 57 // RegR1 is the R1 register 58 RegR1 59 // RegR2 is the R2 register 60 RegR2 61 // RegR3 is the R3 register 62 RegR3 63 // RegR4 is the R4 register 64 RegR4 65 // RegR5 is the R5 register 66 RegR5 67 // RegR6 is the R6 register 68 RegR6 69 // RegR7 is the R7 register 70 RegR7 71 // RegR8 is the R8 register 72 RegR8 73 // RegR9 is the R9 register 74 RegR9 75 // RegR10 is the R10 register 76 RegR10 77 // RegR11 is the R11 register 78 RegR11 79 // RegR12 is the R12 register 80 RegR12 81 // RegR13 is the R13 register 82 RegR13 83 // RegR14 is the R14 register 84 RegR14 85 // RegR15 is the R15 register 86 RegR15 87 // RegR16 is the R16 register 88 RegR16 89 // RegR17 is the R17 register 90 RegR17 91 // RegR18 is the R18 register 92 RegR18 93 // RegR19 is the R19 register 94 RegR19 95 // RegR20 is the R20 register 96 RegR20 97 // RegR21 is the R21 register 98 RegR21 99 // RegR22 is the R22 register 100 RegR22 101 // RegR23 is the R23 register 102 RegR23 103 // RegR24 is the R24 register 104 RegR24 105 // RegR25 is the R25 register 106 RegR25 107 // RegR26 is the R26 register 108 RegR26 109 // RegR27 is the R27 register 110 RegR27 111 // RegR28 is the R28 register 112 RegR28 113 // RegR29 is the R29 register 114 RegR29 115 // RegR30 is the R30 register 116 RegR30 117 // RegRZR is the RZR register (read-only, always returning zero) 118 RegRZR 119 // RegSP is the SP register 120 RegSP 121 122 // Scalar floating point registers. 123 124 // RegV0 is the V0 register 125 RegV0 126 // RegV1 is the V1 register 127 RegV1 128 // RegV2 is the V2 register 129 RegV2 130 // RegV3 is the V3 register 131 RegV3 132 // RegV4 is the V4 register 133 RegV4 134 // RegV5 is the V5 register 135 RegV5 136 // RegV6 is the V6 register 137 RegV6 138 // RegV7 is the V7 register 139 RegV7 140 // RegV8 is the V8 register 141 RegV8 142 // RegV9 is the V9 register 143 RegV9 144 // RegV10 is the V10 register 145 RegV10 146 // RegV11 is the V11 register 147 RegV11 148 // RegV12 is the V12 register 149 RegV12 150 // RegV13 is the V13 register 151 RegV13 152 // RegV14 is the V14 register 153 RegV14 154 // RegV15 is the V15 register 155 RegV15 156 // RegV16 is the V16 register 157 RegV16 158 // RegV17 is the V17 register 159 RegV17 160 // RegV18 is the V18 register 161 RegV18 162 // RegV19 is the V19 register 163 RegV19 164 // RegV20 is the V20 register 165 RegV20 166 // RegV21 is the V21 register 167 RegV21 168 // RegV22 is the V22 register 169 RegV22 170 // RegV23 is the V23 register 171 RegV23 172 // RegV24 is the V24 register 173 RegV24 174 // RegV25 is the V25 register 175 RegV25 176 // RegV26 is the V26 register 177 RegV26 178 // RegV27 is the V27 register 179 RegV27 180 // RegV28 is the V28 register 181 RegV28 182 // RegV29 is the V29 register 183 RegV29 184 // RegV30 is the V30 register 185 RegV30 186 // RegV31 is the V31 register 187 RegV31 188 189 // Floating point status register. 190 191 // RegFPSR is the FPSR register 192 RegFPSR 193 194 // Assign each conditional register state to the unique register ID. 195 // This is to reduce the size of nodeImpl struct without having dedicated field 196 // for conditional register state which would not be used by most nodes. 197 // This is taking advantage of the fact that conditional operations are always 198 // on a single register and condition code, and never two registers. 199 200 // RegCondEQ encodes CondEQ into a field that would otherwise store a register 201 RegCondEQ 202 // RegCondNE encodes CondNE into a field that would otherwise store a register 203 RegCondNE 204 // RegCondHS encodes CondHS into a field that would otherwise store a register 205 RegCondHS 206 // RegCondLO encodes CondLO into a field that would otherwise store a register 207 RegCondLO 208 // RegCondMI encodes CondMI into a field that would otherwise store a register 209 RegCondMI 210 // RegCondPL encodes CondPL into a field that would otherwise store a register 211 RegCondPL 212 // RegCondVS encodes CondVS into a field that would otherwise store a register 213 RegCondVS 214 // RegCondVC encodes CondVC into a field that would otherwise store a register 215 RegCondVC 216 // RegCondHI encodes CondHI into a field that would otherwise store a register 217 RegCondHI 218 // RegCondLS encodes CondLS into a field that would otherwise store a register 219 RegCondLS 220 // RegCondGE encodes CondGE into a field that would otherwise store a register 221 RegCondGE 222 // RegCondLT encodes CondLT into a field that would otherwise store a register 223 RegCondLT 224 // RegCondGT encodes CondGT into a field that would otherwise store a register 225 RegCondGT 226 // RegCondLE encodes CondLE into a field that would otherwise store a register 227 RegCondLE 228 // RegCondAL encodes CondAL into a field that would otherwise store a register 229 RegCondAL 230 // RegCondNV encodes CondNV into a field that would otherwise store a register 231 RegCondNV 232 ) 233 234 // conditionalRegisterStateToRegister cast a conditional register to its unique register ID. 235 // See the comment on RegCondEQ above. 236 func conditionalRegisterStateToRegister(c asm.ConditionalRegisterState) asm.Register { 237 switch c { 238 case CondEQ: 239 return RegCondEQ 240 case CondNE: 241 return RegCondNE 242 case CondHS: 243 return RegCondHS 244 case CondLO: 245 return RegCondLO 246 case CondMI: 247 return RegCondMI 248 case CondPL: 249 return RegCondPL 250 case CondVS: 251 return RegCondVS 252 case CondVC: 253 return RegCondVC 254 case CondHI: 255 return RegCondHI 256 case CondLS: 257 return RegCondLS 258 case CondGE: 259 return RegCondGE 260 case CondLT: 261 return RegCondLT 262 case CondGT: 263 return RegCondGT 264 case CondLE: 265 return RegCondLE 266 case CondAL: 267 return RegCondAL 268 case CondNV: 269 return RegCondNV 270 } 271 return asm.NilRegister 272 } 273 274 // RegisterName returns the name of a given register 275 func RegisterName(r asm.Register) string { 276 switch r { 277 case asm.NilRegister: 278 return "nil" 279 case RegR0: 280 return "R0" 281 case RegR1: 282 return "R1" 283 case RegR2: 284 return "R2" 285 case RegR3: 286 return "R3" 287 case RegR4: 288 return "R4" 289 case RegR5: 290 return "R5" 291 case RegR6: 292 return "R6" 293 case RegR7: 294 return "R7" 295 case RegR8: 296 return "R8" 297 case RegR9: 298 return "R9" 299 case RegR10: 300 return "R10" 301 case RegR11: 302 return "R11" 303 case RegR12: 304 return "R12" 305 case RegR13: 306 return "R13" 307 case RegR14: 308 return "R14" 309 case RegR15: 310 return "R15" 311 case RegR16: 312 return "R16" 313 case RegR17: 314 return "R17" 315 case RegR18: 316 return "R18" 317 case RegR19: 318 return "R19" 319 case RegR20: 320 return "R20" 321 case RegR21: 322 return "R21" 323 case RegR22: 324 return "R22" 325 case RegR23: 326 return "R23" 327 case RegR24: 328 return "R24" 329 case RegR25: 330 return "R25" 331 case RegR26: 332 return "R26" 333 case RegR27: 334 return "R27" 335 case RegR28: 336 return "R28" 337 case RegR29: 338 return "R29" 339 case RegR30: 340 return "R30" 341 case RegRZR: 342 return "RZR" 343 case RegSP: 344 return "SP" 345 case RegV0: 346 return "V0" 347 case RegV1: 348 return "V1" 349 case RegV2: 350 return "V2" 351 case RegV3: 352 return "V3" 353 case RegV4: 354 return "V4" 355 case RegV5: 356 return "V5" 357 case RegV6: 358 return "V6" 359 case RegV7: 360 return "V7" 361 case RegV8: 362 return "V8" 363 case RegV9: 364 return "V9" 365 case RegV10: 366 return "V10" 367 case RegV11: 368 return "V11" 369 case RegV12: 370 return "V12" 371 case RegV13: 372 return "V13" 373 case RegV14: 374 return "V14" 375 case RegV15: 376 return "V15" 377 case RegV16: 378 return "V16" 379 case RegV17: 380 return "V17" 381 case RegV18: 382 return "V18" 383 case RegV19: 384 return "V19" 385 case RegV20: 386 return "V20" 387 case RegV21: 388 return "V21" 389 case RegV22: 390 return "V22" 391 case RegV23: 392 return "V23" 393 case RegV24: 394 return "V24" 395 case RegV25: 396 return "V25" 397 case RegV26: 398 return "V26" 399 case RegV27: 400 return "V27" 401 case RegV28: 402 return "V28" 403 case RegV29: 404 return "V29" 405 case RegV30: 406 return "V30" 407 case RegV31: 408 return "V31" 409 case RegFPSR: 410 return "FPSR" 411 case RegCondEQ: 412 return "COND_EQ" 413 case RegCondNE: 414 return "COND_NE" 415 case RegCondHS: 416 return "COND_HS" 417 case RegCondLO: 418 return "COND_LO" 419 case RegCondMI: 420 return "COND_MI" 421 case RegCondPL: 422 return "COND_PL" 423 case RegCondVS: 424 return "COND_VS" 425 case RegCondVC: 426 return "COND_VC" 427 case RegCondHI: 428 return "COND_HI" 429 case RegCondLS: 430 return "COND_LS" 431 case RegCondGE: 432 return "COND_GE" 433 case RegCondLT: 434 return "COND_LT" 435 case RegCondGT: 436 return "COND_GT" 437 case RegCondLE: 438 return "COND_LE" 439 case RegCondAL: 440 return "COND_AL" 441 case RegCondNV: 442 return "COND_NV" 443 } 444 return "UNKNOWN" 445 } 446 447 // Arm64-specific instructions. 448 // 449 // Note: This only defines arm64 instructions used by wazero's compiler. 450 // Note: Naming conventions partially match the Go assembler: https://go.dev/doc/asm 451 const ( 452 // NOP is the NOP instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NOP 453 NOP asm.Instruction = iota 454 // RET is the RET instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RET 455 RET 456 // ADD is the ADD instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADD--shifted-register- 457 ADD 458 // ADDS is the ADDS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADDS--shifted-register- 459 ADDS 460 // ADDW is the ADD instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADD--shifted-register- 461 ADDW 462 // ADR is the ADR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADR 463 ADR 464 // AND is the AND instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/AND--shifted-register- 465 AND 466 // ANDIMM32 is the AND(immediate) instruction in 32-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/AND--immediate---Bitwise-AND--immediate--?lang=en 467 ANDIMM32 468 // ANDIMM64 is the AND(immediate) instruction in 64-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/AND--immediate---Bitwise-AND--immediate--?lang=en 469 ANDIMM64 470 // ANDW is the AND instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/AND--register- 471 ANDW 472 // ANDS is the ANDS instruction in 64-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ANDS--immediate---Bitwise-AND--immediate---setting-flags-?lang=en 473 ANDS 474 // ANDSW is the ANDS instruction in 32-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ANDS--immediate---Bitwise-AND--immediate---setting-flags-?lang=en 475 ANDSW 476 // ASR is the ASR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ASR--register- 477 ASR 478 // ASRW is the ASR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ASR--register- 479 ASRW 480 // B is the B instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B 481 B 482 483 // Below are B.cond instructions. 484 // * https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond 485 // * https://developer.arm.com/documentation/dui0802/a/A32-and-T32-Instructions/Condition-codes 486 487 // BCONDEQ is the B.cond instruction with CondEQ. 488 BCONDEQ 489 // BCONDGE is the B.cond instruction with CondGE. 490 BCONDGE 491 // BCONDGT is the B.cond instruction with CondGT. 492 BCONDGT 493 // BCONDHI is the B.cond instruction with CondHI. 494 BCONDHI 495 // BCONDHS is the B.cond instruction with CondHS. 496 BCONDHS 497 // BCONDLE is the B.cond instruction with CondLE. 498 BCONDLE 499 // BCONDLO is the B.cond instruction with CondLO. 500 BCONDLO 501 // BCONDLS is the B.cond instruction with CondLS. 502 BCONDLS 503 // BCONDLT is the B.cond instruction with CondLT. 504 BCONDLT 505 // BCONDMI is the B.cond instruction with CondMI. 506 BCONDMI 507 // BCONDPL is the B.cond instruction with CondPL. 508 BCONDPL 509 // BCONDNE is the B.cond instruction with CondNE. 510 BCONDNE 511 // BCONDVS is the B.cond instruction with CondVS. 512 BCONDVS 513 // BCONDVC is the B.cond instruction with CondVC. 514 BCONDVC 515 516 // CLZ is the CLZ instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CLZ 517 CLZ 518 // CLZW is the CLZ instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CLZ 519 CLZW 520 // CMP is the CMP instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CMP--shifted-register- 521 CMP 522 // CMPW is the CMP instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CMP--shifted-register- 523 CMPW 524 // CSET is the CSET instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CSET 525 CSET 526 // EOR is the EOR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/EOR--shifted-register- 527 EOR 528 // EORW is the EOR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/EOR--shifted-register- 529 EORW 530 // FABSD is the FABS instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FABS--scalar- 531 FABSD 532 // FABSS is the FABS instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FABS--scalar- 533 FABSS 534 // FADDD is the FADD instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FADD--scalar- 535 FADDD 536 // FADDS is the FADD instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FADD--scalar- 537 FADDS 538 // FCMPD is the FCMP instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCMP 539 FCMPD 540 // FCMPS is the FCMP instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCMP 541 FCMPS 542 // FCVTDS is the FCVT instruction, for single to double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVT 543 FCVTDS 544 // FCVTSD is the FCVT instruction, for double to single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVT 545 FCVTSD 546 // FCVTZSD is the FCVTZS instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- 547 FCVTZSD 548 // FCVTZSDW is the FCVTZS instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- 549 FCVTZSDW 550 // FCVTZSS is the FCVTZS instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- 551 FCVTZSS 552 // FCVTZSSW is the FCVTZS instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- 553 FCVTZSSW 554 // FCVTZUD is the FCVTZU instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- 555 FCVTZUD 556 // FCVTZUDW is the FCVTZU instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- 557 FCVTZUDW 558 // FCVTZUS is the FCVTZU instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- 559 FCVTZUS 560 // FCVTZUSW is the FCVTZU instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- 561 FCVTZUSW 562 // FDIVD is the FDIV instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FDIV--scalar- 563 FDIVD 564 // FDIVS is the FDIV instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FDIV--scalar- 565 FDIVS 566 // FMAXD is the FMAX instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMAX--scalar- 567 FMAXD 568 // FMAXS is the FMAX instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMAX--scalar- 569 FMAXS 570 // FMIND is the FMIN instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMIN--scalar- 571 FMIND 572 // FMINS is the FMIN instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMIN--scalar- 573 FMINS 574 // FMOVD is the FMOV instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMOV--register- 575 FMOVD 576 // FMOVS is the FMOV instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMOV--register- 577 FMOVS 578 // FMULD is the FMUL instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMUL--scalar- 579 FMULD 580 // FMULS is the FMUL instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMUL--scalar- 581 FMULS 582 // FNEGD is the FNEG instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FNEG--scalar- 583 FNEGD 584 // FNEGS is the FNEG instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FNEG--scalar- 585 FNEGS 586 // FRINTMD is the FRINTM instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTM--scalar- 587 FRINTMD 588 // FRINTMS is the FRINTM instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTM--scalar- 589 FRINTMS 590 // FRINTND is the FRINTN instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTN--scalar- 591 FRINTND 592 // FRINTNS is the FRINTN instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTN--scalar- 593 FRINTNS 594 // FRINTPD is the FRINTP instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTP--scalar- 595 FRINTPD 596 // FRINTPS is the FRINTP instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTP--scalar- 597 FRINTPS 598 // FRINTZD is the FRINTZ instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTZ--scalar- 599 FRINTZD 600 // FRINTZS is the FRINTZ instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTZ--scalar- 601 FRINTZS 602 // FSQRTD is the FSQRT instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSQRT--scalar- 603 FSQRTD 604 // FSQRTS is the FSQRT instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSQRT--scalar- 605 FSQRTS 606 // FSUBD is the FSUB instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSUB--scalar- 607 FSUBD 608 // FSUBS is the FSUB instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSUB--scalar- 609 FSUBS 610 // LSL is the LSL instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSL--register- 611 LSL 612 // LSLW is the LSL instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSL--register- 613 LSLW 614 // LSR is the LSR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSR--register- 615 LSR 616 // LSRW is the LSR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSR--register- 617 LSRW 618 // FLDRD is the LDR (SIMD&FP) instruction for double precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LDR--register--SIMD-FP---Load-SIMD-FP-Register--register-offset--?lang=en 619 FLDRD 620 // FLDRS is the LDR (SIMD&FP) instruction for single precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LDR--register--SIMD-FP---Load-SIMD-FP-Register--register-offset--?lang=en 621 FLDRS 622 // LDRD is the LDR instruction in 64-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en 623 LDRD 624 // LDRW is the LDR instruction in 32-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en 625 LDRW 626 // LDRSBD is the LDRSB instruction in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSB--register- 627 LDRSBD 628 // LDRSBW is the LDRSB instruction in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSB--register- 629 LDRSBW 630 // LDRB is the LDRB instruction. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRB--register- 631 LDRB 632 // LDRSHD is the LDRSHW instruction in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSH--register- 633 LDRSHD 634 // LDRSHW is the LDRSHW instruction in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSH--register- 635 LDRSHW 636 // LDRH is the LDRH instruction. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRH--register- 637 LDRH 638 // LDRSW is the LDRSW instruction https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSW--register- 639 LDRSW 640 // FSTRD is the STR (SIMD&FP) instruction for double precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset--?lang=en 641 FSTRD 642 // FSTRS is the STR (SIMD&FP) instruction for single precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset--?lang=en 643 FSTRS 644 // STRD is the STR instruction in 64-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STR--register---Store-Register--register--?lang=en 645 STRD 646 // STRW is the STR instruction in 32-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STR--register---Store-Register--register--?lang=en 647 STRW 648 // STRH is the STRH instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STRH--register---Store-Register-Halfword--register--?lang=en 649 STRH 650 // STRB is the STRB instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STRB--register---Store-Register-Byte--register--?lang=en 651 STRB 652 // MOVD moves a double word from register to register, or const to register. 653 MOVD 654 // MOVW moves a word from register to register, or const to register. 655 MOVW 656 // MRS is the MRS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MRS 657 MRS 658 // MSR is the MSR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSR--register- 659 MSR 660 // MSUB is the MSUB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSUB 661 MSUB 662 // MSUBW is the MSUB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSUB 663 MSUBW 664 // MUL is the MUL instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MUL 665 MUL 666 // MULW is the MUL instruction, in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MUL 667 MULW 668 // NEG is the NEG instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NEG 669 NEG 670 // NEGW is the NEG instruction, in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NEG 671 NEGW 672 // ORR is the ORR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ORR--shifted-register- 673 ORR 674 // ORRW is the ORR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ORR--shifted-register- 675 ORRW 676 // ORN is the ORN instruction. https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/ORN--shifted-register---Bitwise-OR-NOT--shifted-register--?lang=en#ORN_32_log_shift 677 ORN 678 // ORNW is the ORN instruction, in 32-bit mode. https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/ORN--shifted-register---Bitwise-OR-NOT--shifted-register--?lang=en#ORN_32_log_shift 679 ORNW 680 // RBIT is the RBIT instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RBIT 681 RBIT 682 // RBITW is the RBIT instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RBIT 683 RBITW 684 // ROR is the ROR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ROR--register- 685 ROR 686 // RORW is the RORW instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ROR--register- 687 RORW 688 // SCVTFD is the SCVTF instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- 689 SCVTFD 690 // SCVTFS is the SCVTF instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- 691 SCVTFS 692 // SCVTFWD is the SCVTF instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- 693 SCVTFWD 694 // SCVTFWS is the SCVTF instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- 695 SCVTFWS 696 // SDIV is the SDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SDIV 697 SDIV 698 // SDIVW is the SDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SDIV 699 SDIVW 700 // SUB is the SUB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUB--shifted-register- 701 SUB 702 // SUBS is the SUBS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUBS--shifted-register- 703 SUBS 704 // SUBW is the SUB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUB--shifted-register- 705 SUBW 706 // SXTB is the SXTB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTB 707 SXTB 708 // SXTBW is the SXTB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTB 709 SXTBW 710 // SXTH is the SXTH instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTH 711 SXTH 712 // SXTHW is the SXTH instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTH 713 SXTHW 714 // SXTW is the SXTW instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTW 715 SXTW 716 // UCVTFD is the UCVTF instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- 717 UCVTFD 718 // UCVTFS is the UCVTF instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- 719 UCVTFS 720 // UCVTFWD is the UCVTF instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- 721 UCVTFWD 722 // UCVTFWS is the UCVTF instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- 723 UCVTFWS 724 // UDIV is the UDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV 725 UDIV 726 // UDIVW is the UDIV instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV 727 UDIVW 728 // VBIT is the BIT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/BIT--vector- 729 VBIT 730 // VCNT is the CNT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/CNT--vector- 731 VCNT 732 // VMOV has different semantics depending on the types of operands: 733 // - LDR(SIMD&FP) if the src is memory and dst is a vector: https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/LDR--immediate--SIMD-FP---Load-SIMD-FP-Register--immediate-offset-- 734 // - LDR(literal, SIMD&FP) if the src is static const and dst is a vector: https://developer.arm.com/documentation/dui0801/h/A64-Floating-point-Instructions/LDR--literal--SIMD-and-FP- 735 // - STR(SIMD&FP) if the dst is memory and src is a vector: https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset-- 736 VMOV 737 // UMOV is the UMOV instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMOV--Unsigned-Move-vector-element-to-general-purpose-register-?lang=en 738 UMOV 739 // INSGEN is the INS(general) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/INS--general---Insert-vector-element-from-general-purpose-register-?lang=en 740 INSGEN 741 // INSELEM is the INS(element) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/INS--element---Insert-vector-element-from-another-vector-element-?lang=en 742 INSELEM 743 // UADDLV is the UADDLV(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/UADDLV--vector- 744 UADDLV 745 // VADD is the ADD(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/ADD--vector- 746 VADD 747 // VFADDS is the FADD(vector) instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FADD--vector- 748 VFADDS 749 // VFADDD is the FADD(vector) instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FADD--vector- 750 VFADDD 751 // VSUB is the SUB(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/SUB--vector- 752 VSUB 753 // VFSUBS is the FSUB(vector) instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FSUB--vector- 754 VFSUBS 755 // VFSUBD is the FSUB(vector) instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FSUB--vector- 756 VFSUBD 757 // SSHL is the SSHL(vector,register) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHL--Signed-Shift-Left--register--?lang=en 758 SSHL 759 // SSHLL is the SSHLL(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- 760 SSHLL 761 // USHL is the USHL(vector,register) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHL--Signed-Shift-Left--register--?lang=en 762 USHL 763 // USHLL is the USHLL(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- 764 USHLL 765 // LD1R is the LD1R instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LD1R--Load-one-single-element-structure-and-Replicate-to-all-lanes--of-one-register-- 766 LD1R 767 // SMOV32 is the 32-bit variant of SMOV(vector) instruction. https://developer.arm.com/documentation/100069/0610/A64-SIMD-Vector-Instructions/SMOV--vector- 768 SMOV32 769 // DUPGEN is the DUP(general) instruction. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/DUP--general---Duplicate-general-purpose-register-to-vector- 770 DUPGEN 771 // DUPELEM is the DUP(element) instruction. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/DUP--element---Duplicate-vector-element-to-vector-or-scalar- 772 DUPELEM 773 // UMAXP is the UMAXP(vector) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/UMAXP--vector- 774 UMAXP 775 // UMINV is the UMINV(vector) instruction. https://developer.arm.com/documentation/100069/0610/A64-SIMD-Vector-Instructions/UMINV--vector- 776 UMINV 777 // CMEQ is the CMEQ(vector, register) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/CMEQ--vector--register- 778 CMEQ 779 // CMEQZERO is the CMEP(zero) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMEQ--zero---Compare-bitwise-Equal-to-zero--vector--?lang=en 780 CMEQZERO 781 // ADDP is the ADDP(scalar) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ADDP--scalar---Add-Pair-of-elements--scalar--?lang=en 782 ADDP 783 // VADDP is the ADDP(vector) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/ADDP--vector- 784 // Note: prefixed by V to distinguish from the non-vector variant of ADDP(scalar). 785 VADDP 786 // TBL1 is the TBL instruction whose source is one vector. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup- 787 TBL1 788 // TBL2 is the TBL instruction whose source is two vectors. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup- 789 TBL2 790 // NOT is the NOT(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/NOT--Bitwise-NOT--vector--?lang=en 791 NOT 792 // VAND is the AND(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/AND--vector---Bitwise-AND--vector-- 793 // Note: prefixed by V to distinguish from the non-vector variant of AND. 794 VAND 795 // VORR is the ORR(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/ORR--vector--register---Bitwise-inclusive-OR--vector--register-- 796 // Note: prefixed by V to distinguish from the non-vector variant of ORR. 797 VORR 798 // BSL https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/BSL--Bitwise-Select- 799 BSL 800 // BIC is the BIC(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/BIC--vector--register---Bitwise-bit-Clear--vector--register-- 801 BIC 802 // VFNEG is the FNEG(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/FNEG--vector---Floating-point-Negate--vector-- 803 // Note: prefixed by V to distinguish from the non-vector variant of FNEG. 804 VFNEG 805 // ADDV is the ADDV instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/ADDV--Add-across-Vector- 806 ADDV 807 // ZIP1 is the ZIP1 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ZIP1--Zip-vectors--primary--?lang=en 808 ZIP1 809 // SSHR is the SSHR(immediate,vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHR--Signed-Shift-Right--immediate--?lang=en 810 SSHR 811 // EXT is the EXT instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/EXT--Extract-vector-from-pair-of-vectors-?lang=en 812 EXT 813 // CMGT is the CMGT(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMGT--register---Compare-signed-Greater-than--vector--?lang=en 814 CMGT 815 // CMHI is the CMHI(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMHI--register---Compare-unsigned-Higher--vector--?lang=en 816 CMHI 817 // CMGE is the CMGE(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMGE--register---Compare-signed-Greater-than-or-Equal--vector--?lang=en 818 CMGE 819 // CMHS is the CMHS(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMHS--register---Compare-unsigned-Higher-or-Same--vector--?lang=en 820 CMHS 821 // FCMEQ is the FCMEQ(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMEQ--register---Floating-point-Compare-Equal--vector--?lang=en 822 FCMEQ 823 // FCMGT is the FCMGT(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMGT--register---Floating-point-Compare-Greater-than--vector--?lang=en 824 FCMGT 825 // FCMGE is the FCMGE(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMGE--register---Floating-point-Compare-Greater-than-or-Equal--vector--?lang=en 826 FCMGE 827 // VFMUL is the FMUL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMUL--vector---Floating-point-Multiply--vector--?lang=en 828 // Note: prefixed by V to distinguish from the non-vector variant. 829 VFMUL 830 // VFDIV is the FDIV(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FDIV--vector---Floating-point-Divide--vector--?lang=en 831 // Note: prefixed by V to distinguish from the non-vector variant. 832 VFDIV 833 // VFSQRT is the FSQRT(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FSQRT--vector---Floating-point-Square-Root--vector--?lang=en 834 // Note: prefixed by V to distinguish from the non-vector variant. 835 VFSQRT 836 // VFMIN is the FMIN(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMIN--vector---Floating-point-minimum--vector--?lang=en 837 // Note: prefixed by V to distinguish from the non-vector variant. 838 VFMIN 839 // VFMAX is the FMAX(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMAX--vector---Floating-point-Maximum--vector--?lang=en 840 // Note: prefixed by V to distinguish from the non-vector variant. 841 VFMAX 842 // VFABS is the FABS(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FABS--vector---Floating-point-Absolute-value--vector--?lang=en 843 // Note: prefixed by V to distinguish from the non-vector variant. 844 VFABS 845 // VFRINTP is the FRINTP(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTP--vector---Floating-point-Round-to-Integral--toward-Plus-infinity--vector--?lang=en 846 // Note: prefixed by V to distinguish from the non-vector variant. 847 VFRINTP 848 // VFRINTM is the FRINTM(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTM--vector---Floating-point-Round-to-Integral--toward-Minus-infinity--vector--?lang=en 849 // Note: prefixed by V to distinguish from the non-vector variant. 850 VFRINTM 851 // VFRINTZ is the FRINTZ(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTZ--vector---Floating-point-Round-to-Integral--toward-Zero--vector--?lang=en 852 // Note: prefixed by V to distinguish from the non-vector variant. 853 VFRINTZ 854 // VFRINTN is the FRINTN(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTN--vector---Floating-point-Round-to-Integral--to-nearest-with-ties-to-even--vector--?lang=en 855 // Note: prefixed by V to distinguish from the non-vector variant. 856 VFRINTN 857 // VMUL is the MUL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/MUL--vector---Multiply--vector--?lang=en 858 // Note: prefixed by V to distinguish from the non-vector variant. 859 VMUL 860 // VNEG is the NEG(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/NEG--vector---Negate--vector--?lang=en 861 // Note: prefixed by V to distinguish from the non-vector variant. 862 VNEG 863 // VABS is the ABS(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ABS--Absolute-value--vector--?lang=en 864 // Note: prefixed by V to distinguish from the non-vector variant. 865 VABS 866 // VSQADD is the SQADD(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQADD--Signed-saturating-Add-?lang=en 867 // Note: prefixed by V to distinguish from the non-vector variant. 868 VSQADD 869 // VUQADD is the UQADD(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQADD--Unsigned-saturating-Add-?lang=en 870 // Note: prefixed by V to distinguish from the non-vector variant. 871 VUQADD 872 // VSQSUB is the SQSUB(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQSUB--Signed-saturating-Subtract-?lang=en 873 // Note: prefixed by V to distinguish from the non-vector variant. 874 VSQSUB 875 // VUQSUB is the UQSUB(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQSUB--Unsigned-saturating-Subtract-?lang=en 876 // Note: prefixed by V to distinguish from the non-vector variant. 877 VUQSUB 878 // SMIN is the SMIN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMIN--Signed-Minimum--vector--?lang=en 879 SMIN 880 // SMAX is the SMAX instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMAX--Signed-Maximum--vector--?lang=en 881 SMAX 882 // UMIN is the UMIN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMIN--Unsigned-Minimum--vector--?lang=en 883 UMIN 884 // UMAX is the UMAX instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMAX--Unsigned-Maximum--vector--?lang=en 885 UMAX 886 // URHADD is the URHADD instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/URHADD--Unsigned-Rounding-Halving-Add-?lang=en 887 URHADD 888 // REV64 is the REV64 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/REV64--Reverse-elements-in-64-bit-doublewords--vector--?lang=en 889 REV64 890 // XTN is the XTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/XTN--XTN2--Extract-Narrow-?lang=en 891 XTN 892 // VUMLAL is the UMLAL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMLAL--UMLAL2--vector---Unsigned-Multiply-Add-Long--vector--?lang=en 893 // Note: prefixed by V to distinguish from the non-vector variant. 894 VUMLAL 895 // SHLL is the SHLL instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SHLL--SHLL2--Shift-Left-Long--by-element-size--?lang=en 896 SHLL 897 // SADDLP is the SADDLP instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SADDLP--Signed-Add-Long-Pairwise-?lang=en 898 SADDLP 899 // UADDLP is the UADDLP instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UADDLP--Unsigned-Add-Long-Pairwise-?lang=en 900 UADDLP 901 // SSHLL2 is the SSHLL2(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- 902 SSHLL2 903 // USHLL2 is the USHLL2(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- 904 USHLL2 905 // SQRDMULH is the SQRDMULH(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQRDMULH--vector---Signed-saturating-Rounding-Doubling-Multiply-returning-High-half-?lang=en 906 SQRDMULH 907 // SMULL is the SMULL(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMULL--SMULL2--vector---Signed-Multiply-Long--vector--?lang=en 908 SMULL 909 // SMULL2 is the SMULL2(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMULL--SMULL2--vector---Signed-Multiply-Long--vector--?lang=en 910 SMULL2 911 // UMULL is the UMULL instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en 912 UMULL 913 // UMULL2 is the UMULL2 instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en 914 UMULL2 915 // VFCVTZS is the FCVTZS(vector,integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTZS--vector--integer---Floating-point-Convert-to-Signed-integer--rounding-toward-Zero--vector--?lang=en 916 // Note: prefixed by V to distinguish from the non-vector variant. 917 VFCVTZS 918 // VFCVTZU is the FCVTZU(vector,integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTZU--vector--integer---Floating-point-Convert-to-Unsigned-integer--rounding-toward-Zero--vector--?lang=en 919 // Note: prefixed by V to distinguish from the non-vector variant. 920 VFCVTZU 921 // SQXTN is the SQXTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTN--SQXTN2--Signed-saturating-extract-Narrow-?lang=en 922 SQXTN 923 // UQXTN is the UQXTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQXTN--UQXTN2--Unsigned-saturating-extract-Narrow-?lang=en 924 UQXTN 925 // SQXTN2 is the SQXTN2 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTN--SQXTN2--Signed-saturating-extract-Narrow-?lang=en 926 SQXTN2 927 // SQXTUN is the SQXTUN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTUN--SQXTUN2--Signed-saturating-extract-Unsigned-Narrow-?lang=en 928 SQXTUN 929 // SQXTUN2 is the SQXTUN2 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTUN--SQXTUN2--Signed-saturating-extract-Unsigned-Narrow-?lang=en 930 SQXTUN2 931 // VSCVTF is the SCVTF(vector, integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SCVTF--vector--integer---Signed-integer-Convert-to-Floating-point--vector--?lang=en 932 // Note: prefixed by V to distinguish from the non-vector variant. 933 VSCVTF 934 // VUCVTF is the UCVTF(vector, integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UCVTF--vector--integer---Unsigned-integer-Convert-to-Floating-point--vector--?lang=en 935 // Note: prefixed by V to distinguish from the non-vector variant. 936 VUCVTF 937 // FCVTL is the FCVTL instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTL--FCVTL2--Floating-point-Convert-to-higher-precision-Long--vector--?lang=en 938 FCVTL 939 // FCVTN is the FCVTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTN--FCVTN2--Floating-point-Convert-to-lower-precision-Narrow--vector--?lang=en 940 FCVTN 941 942 // LDARD is the LDAR instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDAR--Load-Acquire-Register- 943 LDARD 944 // LDARD is the LDAR instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDAR--Load-Acquire-Register- 945 LDARW 946 // LDARH is the LDARH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDARH--Load-Acquire-Register-Halfword- 947 LDARH 948 // LDARB is the LDARB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDARB--Load-Acquire-Register-Byte- 949 LDARB 950 951 // STLRD is the STLR instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/STLR--Store-Release-Register- 952 STLRD 953 // STLRW is the STLR instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/STLR--Store-Release-Register- 954 STLRW 955 // STLRH is the STLRH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/STLRH--Store-Release-Register-Halfword- 956 STLRH 957 // STLRB is the STLRB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/STLRB--Store-Release-Register-Byte- 958 STLRB 959 960 // Note, there is no LDSUB type of instruction, so sub needs to be implemented by first negating the second parameter. 961 962 // LDADDALD is the LDADDAL instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDADD--LDADDA--LDADDAL--LDADDL--Atomic-add-on-word-or-doubleword-in-memory- 963 LDADDALD 964 // LDADDALW is the LDADDAL instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDADD--LDADDA--LDADDAL--LDADDL--Atomic-add-on-word-or-doubleword-in-memory- 965 LDADDALW 966 // LDADDALH is the LDADDALH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDADDH--LDADDAH--LDADDALH--LDADDLH--Atomic-add-on-halfword-in-memory- 967 LDADDALH 968 // LDADDALB is the LDADDALB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDADDB--LDADDAB--LDADDALB--LDADDLB--Atomic-add-on-byte-in-memory- 969 LDADDALB 970 971 // Note, arm's CLR is equivalent to AND NOT 972 973 // LDCLRALD is the LDCLRAL instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDCLR--LDCLRA--LDCLRAL--LDCLRL--Atomic-bit-clear-on-word-or-doubleword-in-memory- 974 LDCLRALD 975 // LDCLRALW is the LDCLRAL instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDCLR--LDCLRA--LDCLRAL--LDCLRL--Atomic-bit-clear-on-word-or-doubleword-in-memory- 976 LDCLRALW 977 // LDCLRALH is the LDCLRALH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDCLRH--LDCLRAH--LDCLRALH--LDCLRLH--Atomic-bit-clear-on-halfword-in-memory- 978 LDCLRALH 979 // LDCLRALB is the LDCLRALB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDCLRB--LDCLRAB--LDCLRALB--LDCLRLB--Atomic-bit-clear-on-byte-in-memory- 980 LDCLRALB 981 982 // Note, arm's SET is equivalent to OR 983 984 // LDSETALD is the LDSETAL instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDSET--LDSETA--LDSETAL--LDSETL--Atomic-bit-set-on-word-or-doubleword-in-memory- 985 LDSETALD 986 // LDSETALW is the LDSETAL instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDSET--LDSETA--LDSETAL--LDSETL--Atomic-bit-set-on-word-or-doubleword-in-memory- 987 LDSETALW 988 // LDSETALH is the LDSETALH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDSETH--LDSETAH--LDSETALH--LDSETLH--Atomic-bit-set-on-halfword-in-memory- 989 LDSETALH 990 // LDSETALB is the LDSETALB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDSETB--LDSETAB--LDSETALB--LDSETLB--Atomic-bit-set-on-byte-in-memory- 991 LDSETALB 992 993 // LDEORALD is the LDEORAL instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDEOR--LDEORA--LDEORAL--LDEORL--Atomic-bitwise-exclusive-OR-on-word-or-doubleword-in-memory- 994 LDEORALD 995 // LDEORALW is the LDEORAL instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDEOR--LDEORA--LDEORAL--LDEORL--Atomic-bitwise-exclusive-OR-on-word-or-doubleword-in-memory- 996 LDEORALW 997 // LDEORALH is the LDEORALH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDEORH--LDEORAH--LDEORALH--LDEORLH--Atomic-bitwise-exclusive-OR-on-halfword-in-memory- 998 LDEORALH 999 // LDEORALB is the LDEORALB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDEORB--LDEORAB--LDEORALB--LDEORLB--Atomic-bitwise-exclusive-OR-on-byte-in-memory- 1000 LDEORALB 1001 1002 // SWPALD is the SWPAL instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/SWP--SWPA--SWPAL--SWPL--Swap-word-or-doubleword-in-memory- 1003 SWPALD 1004 // SWPALW is the SWPAL instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/SWP--SWPA--SWPAL--SWPL--Swap-word-or-doubleword-in-memory- 1005 SWPALW 1006 // SWPALH is the SWPALH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/SWPH--SWPAH--SWPALH--SWPLH--Swap-halfword-in-memory- 1007 SWPALH 1008 // SWPALB is the SWPALB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/SWPB--SWPAB--SWPALB--SWPLB--Swap-byte-in-memory- 1009 SWPALB 1010 1011 // CASALD is the CASAL instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/CAS--CASA--CASAL--CASL--Compare-and-swap-word-or-doubleword-in-memory- 1012 CASALD 1013 // CASALW is the CASAL instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/CAS--CASA--CASAL--CASL--Compare-and-swap-word-or-doubleword-in-memory- 1014 CASALW 1015 // CASALH is the CASALH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/CASH--CASA--CASALH--CASLH--Compare-and-swap-halfword-in-memory- 1016 CASALH 1017 // CASALB is the CASALB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/CASB--CASAB--CASALB--CASLB--Compare-and-swap-byte-in-memory- 1018 CASALB 1019 1020 // DMB is the DMB instruction for inner-sharable domain https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/DMB--Data-Memory-Barrier- 1021 DMB 1022 1023 // UDF is the UDF instruction https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/UDF--Permanently-Undefined-?lang=en 1024 UDF 1025 1026 // instructionEnd is always placed at the bottom of this iota definition to be used in the test. 1027 instructionEnd 1028 ) 1029 1030 // VectorArrangement is the arrangement of data within a vector register. 1031 type VectorArrangement byte 1032 1033 const ( 1034 // VectorArrangementNone is an arrangement indicating no data is stored. 1035 VectorArrangementNone VectorArrangement = iota 1036 // VectorArrangement8B is an arrangement of 8 bytes (64-bit vector) 1037 VectorArrangement8B 1038 // VectorArrangement16B is an arrangement of 16 bytes (128-bit vector) 1039 VectorArrangement16B 1040 // VectorArrangement4H is an arrangement of 4 half precisions (64-bit vector) 1041 VectorArrangement4H 1042 // VectorArrangement8H is an arrangement of 8 half precisions (128-bit vector) 1043 VectorArrangement8H 1044 // VectorArrangement2S is an arrangement of 2 single precisions (64-bit vector) 1045 VectorArrangement2S 1046 // VectorArrangement4S is an arrangement of 4 single precisions (128-bit vector) 1047 VectorArrangement4S 1048 // VectorArrangement1D is an arrangement of 1 double precision (64-bit vector) 1049 VectorArrangement1D 1050 // VectorArrangement2D is an arrangement of 2 double precisions (128-bit vector) 1051 VectorArrangement2D 1052 1053 // Assign each vector size specifier to a vector arrangement ID. 1054 // Instructions can only have an arrangement or a size specifier, but not both, so it 1055 // simplifies the internal representation of vector instructions by being able to 1056 // store either into the same field. 1057 1058 // VectorArrangementB is a size specifier of byte 1059 VectorArrangementB 1060 // VectorArrangementH is a size specifier of word (16-bit) 1061 VectorArrangementH 1062 // VectorArrangementS is a size specifier of double word (32-bit) 1063 VectorArrangementS 1064 // VectorArrangementD is a size specifier of quad word (64-bit) 1065 VectorArrangementD 1066 // VectorArrangementQ is a size specifier of the entire vector (128-bit) 1067 VectorArrangementQ 1068 ) 1069 1070 func (v VectorArrangement) String() (ret string) { 1071 switch v { 1072 case VectorArrangement8B: 1073 ret = "8B" 1074 case VectorArrangement16B: 1075 ret = "16B" 1076 case VectorArrangement4H: 1077 ret = "4H" 1078 case VectorArrangement8H: 1079 ret = "8H" 1080 case VectorArrangement2S: 1081 ret = "2S" 1082 case VectorArrangement4S: 1083 ret = "4S" 1084 case VectorArrangement1D: 1085 ret = "1D" 1086 case VectorArrangement2D: 1087 ret = "2D" 1088 case VectorArrangementB: 1089 ret = "B" 1090 case VectorArrangementH: 1091 ret = "H" 1092 case VectorArrangementS: 1093 ret = "S" 1094 case VectorArrangementD: 1095 ret = "D" 1096 case VectorArrangementQ: 1097 ret = "Q" 1098 case VectorArrangementNone: 1099 ret = "none" 1100 default: 1101 panic(v) 1102 } 1103 return 1104 } 1105 1106 // VectorIndex is the index of an element of a vector register 1107 type VectorIndex byte 1108 1109 // VectorIndexNone indicates no vector index specified. 1110 const VectorIndexNone = ^VectorIndex(0) 1111 1112 // InstructionName returns the name of the given instruction 1113 func InstructionName(i asm.Instruction) string { 1114 switch i { 1115 case NOP: 1116 return "NOP" 1117 case RET: 1118 return "RET" 1119 case ADD: 1120 return "ADD" 1121 case ADDS: 1122 return "ADDS" 1123 case ADDW: 1124 return "ADDW" 1125 case ADR: 1126 return "ADR" 1127 case AND: 1128 return "AND" 1129 case ANDIMM32: 1130 return "ANDIMM32" 1131 case ANDIMM64: 1132 return "ANDIMM64" 1133 case ANDW: 1134 return "ANDW" 1135 case ANDS: 1136 return "ANDS" 1137 case ANDSW: 1138 return "ANDSW" 1139 case ASR: 1140 return "ASR" 1141 case ASRW: 1142 return "ASRW" 1143 case B: 1144 return "B" 1145 case BCONDEQ: 1146 return "BCONDEQ" 1147 case BCONDGE: 1148 return "BCONDGE" 1149 case BCONDGT: 1150 return "BCONDGT" 1151 case BCONDHI: 1152 return "BCONDHI" 1153 case BCONDHS: 1154 return "BCONDHS" 1155 case BCONDLE: 1156 return "BCONDLE" 1157 case BCONDLO: 1158 return "BCONDLO" 1159 case BCONDLS: 1160 return "BCONDLS" 1161 case BCONDLT: 1162 return "BCONDLT" 1163 case BCONDMI: 1164 return "BCONDMI" 1165 case BCONDPL: 1166 return "BCONDPL" 1167 case BCONDNE: 1168 return "BCONDNE" 1169 case BCONDVS: 1170 return "BCONDVS" 1171 case BCONDVC: 1172 return "BCONDVC" 1173 case CLZ: 1174 return "CLZ" 1175 case CLZW: 1176 return "CLZW" 1177 case CMP: 1178 return "CMP" 1179 case CMPW: 1180 return "CMPW" 1181 case CSET: 1182 return "CSET" 1183 case EOR: 1184 return "EOR" 1185 case EORW: 1186 return "EORW" 1187 case FABSD: 1188 return "FABSD" 1189 case FABSS: 1190 return "FABSS" 1191 case FADDD: 1192 return "FADDD" 1193 case FADDS: 1194 return "FADDS" 1195 case FCMPD: 1196 return "FCMPD" 1197 case FCMPS: 1198 return "FCMPS" 1199 case FCVTDS: 1200 return "FCVTDS" 1201 case FCVTSD: 1202 return "FCVTSD" 1203 case FCVTZSD: 1204 return "FCVTZSD" 1205 case FCVTZSDW: 1206 return "FCVTZSDW" 1207 case FCVTZSS: 1208 return "FCVTZSS" 1209 case FCVTZSSW: 1210 return "FCVTZSSW" 1211 case FCVTZUD: 1212 return "FCVTZUD" 1213 case FCVTZUDW: 1214 return "FCVTZUDW" 1215 case FCVTZUS: 1216 return "FCVTZUS" 1217 case FCVTZUSW: 1218 return "FCVTZUSW" 1219 case FDIVD: 1220 return "FDIVD" 1221 case FDIVS: 1222 return "FDIVS" 1223 case FMAXD: 1224 return "FMAXD" 1225 case FMAXS: 1226 return "FMAXS" 1227 case FMIND: 1228 return "FMIND" 1229 case FMINS: 1230 return "FMINS" 1231 case FMOVD: 1232 return "FMOVD" 1233 case FMOVS: 1234 return "FMOVS" 1235 case FMULD: 1236 return "FMULD" 1237 case FMULS: 1238 return "FMULS" 1239 case FNEGD: 1240 return "FNEGD" 1241 case FNEGS: 1242 return "FNEGS" 1243 case FRINTMD: 1244 return "FRINTMD" 1245 case FRINTMS: 1246 return "FRINTMS" 1247 case FRINTND: 1248 return "FRINTND" 1249 case FRINTNS: 1250 return "FRINTNS" 1251 case FRINTPD: 1252 return "FRINTPD" 1253 case FRINTPS: 1254 return "FRINTPS" 1255 case FRINTZD: 1256 return "FRINTZD" 1257 case FRINTZS: 1258 return "FRINTZS" 1259 case FSQRTD: 1260 return "FSQRTD" 1261 case FSQRTS: 1262 return "FSQRTS" 1263 case FSUBD: 1264 return "FSUBD" 1265 case FSUBS: 1266 return "FSUBS" 1267 case LSL: 1268 return "LSL" 1269 case LSLW: 1270 return "LSLW" 1271 case LSR: 1272 return "LSR" 1273 case LSRW: 1274 return "LSRW" 1275 case LDRSBD: 1276 return "LDRSBD" 1277 case LDRSBW: 1278 return "LDRSBW" 1279 case LDRB: 1280 return "LDRB" 1281 case MOVD: 1282 return "MOVD" 1283 case LDRSHD: 1284 return "LDRSHD" 1285 case LDRSHW: 1286 return "LDRSHW" 1287 case LDRH: 1288 return "LDRH" 1289 case LDRSW: 1290 return "LDRSW" 1291 case STRD: 1292 return "STRD" 1293 case STRW: 1294 return "STRW" 1295 case STRH: 1296 return "STRH" 1297 case STRB: 1298 return "STRB" 1299 case MOVW: 1300 return "MOVW" 1301 case MRS: 1302 return "MRS" 1303 case MSR: 1304 return "MSR" 1305 case MSUB: 1306 return "MSUB" 1307 case MSUBW: 1308 return "MSUBW" 1309 case MUL: 1310 return "MUL" 1311 case MULW: 1312 return "MULW" 1313 case NEG: 1314 return "NEG" 1315 case NEGW: 1316 return "NEGW" 1317 case ORR: 1318 return "ORR" 1319 case ORRW: 1320 return "ORRW" 1321 case ORN: 1322 return "ORN" 1323 case ORNW: 1324 return "ORNW" 1325 case RBIT: 1326 return "RBIT" 1327 case RBITW: 1328 return "RBITW" 1329 case ROR: 1330 return "ROR" 1331 case RORW: 1332 return "RORW" 1333 case SCVTFD: 1334 return "SCVTFD" 1335 case SCVTFS: 1336 return "SCVTFS" 1337 case SCVTFWD: 1338 return "SCVTFWD" 1339 case SCVTFWS: 1340 return "SCVTFWS" 1341 case SDIV: 1342 return "SDIV" 1343 case SDIVW: 1344 return "SDIVW" 1345 case SUB: 1346 return "SUB" 1347 case SUBS: 1348 return "SUBS" 1349 case SUBW: 1350 return "SUBW" 1351 case SXTB: 1352 return "SXTB" 1353 case SXTBW: 1354 return "SXTBW" 1355 case SXTH: 1356 return "SXTH" 1357 case SXTHW: 1358 return "SXTHW" 1359 case SXTW: 1360 return "SXTW" 1361 case UCVTFD: 1362 return "UCVTFD" 1363 case UCVTFS: 1364 return "UCVTFS" 1365 case UCVTFWD: 1366 return "UCVTFWD" 1367 case UCVTFWS: 1368 return "UCVTFWS" 1369 case UDIV: 1370 return "UDIV" 1371 case UDIVW: 1372 return "UDIVW" 1373 case VBIT: 1374 return "VBIT" 1375 case VCNT: 1376 return "VCNT" 1377 case UADDLV: 1378 return "UADDLV" 1379 case VMOV: 1380 return "VMOV" 1381 case INSELEM: 1382 return "INSELEM" 1383 case UMOV: 1384 return "UMOV" 1385 case INSGEN: 1386 return "INSGEN" 1387 case VADD: 1388 return "VADD" 1389 case VFADDS: 1390 return "VFADDS" 1391 case VFADDD: 1392 return "VFADDD" 1393 case VSUB: 1394 return "VSUB" 1395 case VFSUBS: 1396 return "VFSUBS" 1397 case VFSUBD: 1398 return "VFSUBD" 1399 case SSHL: 1400 return "SSHL" 1401 case USHL: 1402 return "USHL" 1403 case SSHLL: 1404 return "SSHLL" 1405 case USHLL: 1406 return "USHLL" 1407 case LD1R: 1408 return "LD1R" 1409 case SMOV32: 1410 return "SMOV32" 1411 case DUPGEN: 1412 return "DUPGEN" 1413 case DUPELEM: 1414 return "DUPELEM" 1415 case UMAXP: 1416 return "UMAXP" 1417 case UMINV: 1418 return "UMINV" 1419 case CMEQ: 1420 return "CMEQ" 1421 case ADDP: 1422 return "ADDP" 1423 case VADDP: 1424 return "VADDP" 1425 case TBL1: 1426 return "TBL1" 1427 case TBL2: 1428 return "TBL2" 1429 case NOT: 1430 return "NOT" 1431 case VAND: 1432 return "VAND" 1433 case VORR: 1434 return "VORR" 1435 case BSL: 1436 return "BSL" 1437 case BIC: 1438 return "BIC" 1439 case VFNEG: 1440 return "VFNEG" 1441 case ADDV: 1442 return "ADDV" 1443 case CMEQZERO: 1444 return "CMEQZERO" 1445 case ZIP1: 1446 return "ZIP1" 1447 case SSHR: 1448 return "SSHR" 1449 case EXT: 1450 return "EXT" 1451 case CMGT: 1452 return "CMGT" 1453 case CMHI: 1454 return "CMHI" 1455 case CMGE: 1456 return "CMGE" 1457 case CMHS: 1458 return "CMHS" 1459 case FCMEQ: 1460 return "FCMEQ" 1461 case FCMGT: 1462 return "FCMGT" 1463 case FCMGE: 1464 return "FCMGE" 1465 case VFMUL: 1466 return "VFMUL" 1467 case VFDIV: 1468 return "VFDIV" 1469 case VFSQRT: 1470 return "VFSQRT" 1471 case VFMIN: 1472 return "VFMIN" 1473 case VFMAX: 1474 return "VFMAX" 1475 case VFABS: 1476 return "VFABS" 1477 case VFRINTP: 1478 return "VFRINTP" 1479 case VFRINTM: 1480 return "VFRINTM" 1481 case VFRINTZ: 1482 return "VFRINTZ" 1483 case VFRINTN: 1484 return "VFRINTN" 1485 case VMUL: 1486 return "VMUL" 1487 case VNEG: 1488 return "VNEG" 1489 case VABS: 1490 return "VABS" 1491 case VSQADD: 1492 return "VSQADD" 1493 case VUQADD: 1494 return "VUQADD" 1495 case SMIN: 1496 return "SMIN" 1497 case SMAX: 1498 return "SMAX" 1499 case UMIN: 1500 return "UMIN" 1501 case UMAX: 1502 return "UMAX" 1503 case URHADD: 1504 return "URHADD" 1505 case VSQSUB: 1506 return "VSQSUB" 1507 case VUQSUB: 1508 return "VUQSUB" 1509 case REV64: 1510 return "REV64" 1511 case XTN: 1512 return "XTN" 1513 case VUMLAL: 1514 return "VUMLAL" 1515 case SHLL: 1516 return "SHLL" 1517 case SSHLL2: 1518 return "SSHLL2" 1519 case USHLL2: 1520 return "USHLL2" 1521 case SQRDMULH: 1522 return "SQRDMULH" 1523 case SADDLP: 1524 return "SADDLP" 1525 case UADDLP: 1526 return "UADDLP" 1527 case SMULL: 1528 return "SMULL" 1529 case SMULL2: 1530 return "SMULL2" 1531 case UMULL: 1532 return "UMULL" 1533 case UMULL2: 1534 return "UMULL2" 1535 case VFCVTZS: 1536 return "VFCVTZS" 1537 case VFCVTZU: 1538 return "VFCVTZU" 1539 case SQXTN: 1540 return "SQXTN" 1541 case UQXTN: 1542 return "UQXTN" 1543 case SQXTN2: 1544 return "SQXTN2" 1545 case SQXTUN: 1546 return "SQXTUN" 1547 case SQXTUN2: 1548 return "SQXTUN2" 1549 case VSCVTF: 1550 return "VSCVTF" 1551 case VUCVTF: 1552 return "VUCVTF" 1553 case FCVTL: 1554 return "FCVTL" 1555 case FCVTN: 1556 return "FCVTN" 1557 case LDARD: 1558 return "LDARD" 1559 case LDARW: 1560 return "LDARW" 1561 case LDARH: 1562 return "LDARH" 1563 case LDARB: 1564 return "LDARB" 1565 case STLRD: 1566 return "STLRD" 1567 case STLRW: 1568 return "STLRW" 1569 case STLRH: 1570 return "STLRH" 1571 case STLRB: 1572 return "STLRB" 1573 case LDADDALD: 1574 return "LDADDALD" 1575 case LDADDALW: 1576 return "LDADDALW" 1577 case LDADDALH: 1578 return "LDADDALH" 1579 case LDADDALB: 1580 return "LDADDALB" 1581 case LDCLRALD: 1582 return "LDCLRALD" 1583 case LDCLRALW: 1584 return "LDCLRALW" 1585 case LDCLRALH: 1586 return "LDCLRALH" 1587 case LDCLRALB: 1588 return "LDCLRALB" 1589 case LDSETALD: 1590 return "LDSETALD" 1591 case LDSETALW: 1592 return "LDSETALW" 1593 case LDSETALH: 1594 return "LDSETALH" 1595 case LDSETALB: 1596 return "LDSETALB" 1597 case LDEORALD: 1598 return "LDEORALD" 1599 case LDEORALW: 1600 return "LDEORALW" 1601 case LDEORALH: 1602 return "LDEORALH" 1603 case LDEORALB: 1604 return "LDEORALB" 1605 case SWPALD: 1606 return "SWPALD" 1607 case SWPALW: 1608 return "SWPALW" 1609 case SWPALH: 1610 return "SWPALH" 1611 case SWPALB: 1612 return "SWPALB" 1613 case CASALD: 1614 return "CASALD" 1615 case CASALW: 1616 return "CASALW" 1617 case CASALH: 1618 return "CASALH" 1619 case CASALB: 1620 return "CASALB" 1621 case DMB: 1622 return "DMB" 1623 case FSTRD: 1624 return "FSTRD" 1625 case FSTRS: 1626 return "FSTRS" 1627 case LDRD: 1628 return "LDRD" 1629 case LDRW: 1630 return "LDRW" 1631 case FLDRD: 1632 return "FLDRD" 1633 case FLDRS: 1634 return "FLDRS" 1635 case UDF: 1636 return "UDF" 1637 } 1638 panic(fmt.Errorf("unknown instruction %d", i)) 1639 }