github.com/xushiwei/go@v0.0.0-20130601165731-2b9d83f45bc9/src/pkg/runtime/defs_darwin_amd64.h (about) 1 // Created by cgo -cdefs - DO NOT EDIT 2 // cgo -cdefs defs_darwin.go 3 4 5 enum { 6 EINTR = 0x4, 7 EFAULT = 0xe, 8 9 PROT_NONE = 0x0, 10 PROT_READ = 0x1, 11 PROT_WRITE = 0x2, 12 PROT_EXEC = 0x4, 13 14 MAP_ANON = 0x1000, 15 MAP_PRIVATE = 0x2, 16 MAP_FIXED = 0x10, 17 18 MADV_DONTNEED = 0x4, 19 MADV_FREE = 0x5, 20 21 MACH_MSG_TYPE_MOVE_RECEIVE = 0x10, 22 MACH_MSG_TYPE_MOVE_SEND = 0x11, 23 MACH_MSG_TYPE_MOVE_SEND_ONCE = 0x12, 24 MACH_MSG_TYPE_COPY_SEND = 0x13, 25 MACH_MSG_TYPE_MAKE_SEND = 0x14, 26 MACH_MSG_TYPE_MAKE_SEND_ONCE = 0x15, 27 MACH_MSG_TYPE_COPY_RECEIVE = 0x16, 28 29 MACH_MSG_PORT_DESCRIPTOR = 0x0, 30 MACH_MSG_OOL_DESCRIPTOR = 0x1, 31 MACH_MSG_OOL_PORTS_DESCRIPTOR = 0x2, 32 MACH_MSG_OOL_VOLATILE_DESCRIPTOR = 0x3, 33 34 MACH_MSGH_BITS_COMPLEX = 0x80000000, 35 36 MACH_SEND_MSG = 0x1, 37 MACH_RCV_MSG = 0x2, 38 MACH_RCV_LARGE = 0x4, 39 40 MACH_SEND_TIMEOUT = 0x10, 41 MACH_SEND_INTERRUPT = 0x40, 42 MACH_SEND_ALWAYS = 0x10000, 43 MACH_SEND_TRAILER = 0x20000, 44 MACH_RCV_TIMEOUT = 0x100, 45 MACH_RCV_NOTIFY = 0x200, 46 MACH_RCV_INTERRUPT = 0x400, 47 MACH_RCV_OVERWRITE = 0x1000, 48 49 NDR_PROTOCOL_2_0 = 0x0, 50 NDR_INT_BIG_ENDIAN = 0x0, 51 NDR_INT_LITTLE_ENDIAN = 0x1, 52 NDR_FLOAT_IEEE = 0x0, 53 NDR_CHAR_ASCII = 0x0, 54 55 SA_SIGINFO = 0x40, 56 SA_RESTART = 0x2, 57 SA_ONSTACK = 0x1, 58 SA_USERTRAMP = 0x100, 59 SA_64REGSET = 0x200, 60 61 SIGHUP = 0x1, 62 SIGINT = 0x2, 63 SIGQUIT = 0x3, 64 SIGILL = 0x4, 65 SIGTRAP = 0x5, 66 SIGABRT = 0x6, 67 SIGEMT = 0x7, 68 SIGFPE = 0x8, 69 SIGKILL = 0x9, 70 SIGBUS = 0xa, 71 SIGSEGV = 0xb, 72 SIGSYS = 0xc, 73 SIGPIPE = 0xd, 74 SIGALRM = 0xe, 75 SIGTERM = 0xf, 76 SIGURG = 0x10, 77 SIGSTOP = 0x11, 78 SIGTSTP = 0x12, 79 SIGCONT = 0x13, 80 SIGCHLD = 0x14, 81 SIGTTIN = 0x15, 82 SIGTTOU = 0x16, 83 SIGIO = 0x17, 84 SIGXCPU = 0x18, 85 SIGXFSZ = 0x19, 86 SIGVTALRM = 0x1a, 87 SIGPROF = 0x1b, 88 SIGWINCH = 0x1c, 89 SIGINFO = 0x1d, 90 SIGUSR1 = 0x1e, 91 SIGUSR2 = 0x1f, 92 93 FPE_INTDIV = 0x7, 94 FPE_INTOVF = 0x8, 95 FPE_FLTDIV = 0x1, 96 FPE_FLTOVF = 0x2, 97 FPE_FLTUND = 0x3, 98 FPE_FLTRES = 0x4, 99 FPE_FLTINV = 0x5, 100 FPE_FLTSUB = 0x6, 101 102 BUS_ADRALN = 0x1, 103 BUS_ADRERR = 0x2, 104 BUS_OBJERR = 0x3, 105 106 SEGV_MAPERR = 0x1, 107 SEGV_ACCERR = 0x2, 108 109 ITIMER_REAL = 0x0, 110 ITIMER_VIRTUAL = 0x1, 111 ITIMER_PROF = 0x2, 112 113 EV_ADD = 0x1, 114 EV_DELETE = 0x2, 115 EV_CLEAR = 0x20, 116 EV_RECEIPT = 0x40, 117 EV_ERROR = 0x4000, 118 EVFILT_READ = -0x1, 119 EVFILT_WRITE = -0x2, 120 }; 121 122 typedef struct MachBody MachBody; 123 typedef struct MachHeader MachHeader; 124 typedef struct MachNDR MachNDR; 125 typedef struct MachPort MachPort; 126 typedef struct StackT StackT; 127 typedef struct Sigaction Sigaction; 128 typedef struct Siginfo Siginfo; 129 typedef struct Timeval Timeval; 130 typedef struct Itimerval Itimerval; 131 typedef struct Timespec Timespec; 132 typedef struct FPControl FPControl; 133 typedef struct FPStatus FPStatus; 134 typedef struct RegMMST RegMMST; 135 typedef struct RegXMM RegXMM; 136 typedef struct Regs64 Regs64; 137 typedef struct FloatState64 FloatState64; 138 typedef struct ExceptionState64 ExceptionState64; 139 typedef struct Mcontext64 Mcontext64; 140 typedef struct Regs32 Regs32; 141 typedef struct FloatState32 FloatState32; 142 typedef struct ExceptionState32 ExceptionState32; 143 typedef struct Mcontext32 Mcontext32; 144 typedef struct Ucontext Ucontext; 145 typedef struct Kevent Kevent; 146 147 #pragma pack on 148 149 struct MachBody { 150 uint32 msgh_descriptor_count; 151 }; 152 struct MachHeader { 153 uint32 msgh_bits; 154 uint32 msgh_size; 155 uint32 msgh_remote_port; 156 uint32 msgh_local_port; 157 uint32 msgh_reserved; 158 int32 msgh_id; 159 }; 160 struct MachNDR { 161 uint8 mig_vers; 162 uint8 if_vers; 163 uint8 reserved1; 164 uint8 mig_encoding; 165 uint8 int_rep; 166 uint8 char_rep; 167 uint8 float_rep; 168 uint8 reserved2; 169 }; 170 struct MachPort { 171 uint32 name; 172 uint32 pad1; 173 uint16 pad2; 174 uint8 disposition; 175 uint8 type; 176 }; 177 178 struct StackT { 179 byte *ss_sp; 180 uint64 ss_size; 181 int32 ss_flags; 182 byte Pad_cgo_0[4]; 183 }; 184 typedef byte Sighandler[8]; 185 186 struct Sigaction { 187 byte __sigaction_u[8]; 188 void *sa_tramp; 189 uint32 sa_mask; 190 int32 sa_flags; 191 }; 192 193 typedef byte Sigval[8]; 194 struct Siginfo { 195 int32 si_signo; 196 int32 si_errno; 197 int32 si_code; 198 int32 si_pid; 199 uint32 si_uid; 200 int32 si_status; 201 byte *si_addr; 202 byte si_value[8]; 203 int64 si_band; 204 uint64 __pad[7]; 205 }; 206 struct Timeval { 207 int64 tv_sec; 208 int32 tv_usec; 209 byte Pad_cgo_0[4]; 210 }; 211 struct Itimerval { 212 Timeval it_interval; 213 Timeval it_value; 214 }; 215 struct Timespec { 216 int64 tv_sec; 217 int64 tv_nsec; 218 }; 219 220 struct FPControl { 221 byte Pad_cgo_0[2]; 222 }; 223 struct FPStatus { 224 byte Pad_cgo_0[2]; 225 }; 226 struct RegMMST { 227 int8 mmst_reg[10]; 228 int8 mmst_rsrv[6]; 229 }; 230 struct RegXMM { 231 int8 xmm_reg[16]; 232 }; 233 234 struct Regs64 { 235 uint64 rax; 236 uint64 rbx; 237 uint64 rcx; 238 uint64 rdx; 239 uint64 rdi; 240 uint64 rsi; 241 uint64 rbp; 242 uint64 rsp; 243 uint64 r8; 244 uint64 r9; 245 uint64 r10; 246 uint64 r11; 247 uint64 r12; 248 uint64 r13; 249 uint64 r14; 250 uint64 r15; 251 uint64 rip; 252 uint64 rflags; 253 uint64 cs; 254 uint64 fs; 255 uint64 gs; 256 }; 257 struct FloatState64 { 258 int32 fpu_reserved[2]; 259 FPControl fpu_fcw; 260 FPStatus fpu_fsw; 261 uint8 fpu_ftw; 262 uint8 fpu_rsrv1; 263 uint16 fpu_fop; 264 uint32 fpu_ip; 265 uint16 fpu_cs; 266 uint16 fpu_rsrv2; 267 uint32 fpu_dp; 268 uint16 fpu_ds; 269 uint16 fpu_rsrv3; 270 uint32 fpu_mxcsr; 271 uint32 fpu_mxcsrmask; 272 RegMMST fpu_stmm0; 273 RegMMST fpu_stmm1; 274 RegMMST fpu_stmm2; 275 RegMMST fpu_stmm3; 276 RegMMST fpu_stmm4; 277 RegMMST fpu_stmm5; 278 RegMMST fpu_stmm6; 279 RegMMST fpu_stmm7; 280 RegXMM fpu_xmm0; 281 RegXMM fpu_xmm1; 282 RegXMM fpu_xmm2; 283 RegXMM fpu_xmm3; 284 RegXMM fpu_xmm4; 285 RegXMM fpu_xmm5; 286 RegXMM fpu_xmm6; 287 RegXMM fpu_xmm7; 288 RegXMM fpu_xmm8; 289 RegXMM fpu_xmm9; 290 RegXMM fpu_xmm10; 291 RegXMM fpu_xmm11; 292 RegXMM fpu_xmm12; 293 RegXMM fpu_xmm13; 294 RegXMM fpu_xmm14; 295 RegXMM fpu_xmm15; 296 int8 fpu_rsrv4[96]; 297 int32 fpu_reserved1; 298 }; 299 struct ExceptionState64 { 300 uint16 trapno; 301 uint16 cpu; 302 uint32 err; 303 uint64 faultvaddr; 304 }; 305 struct Mcontext64 { 306 ExceptionState64 es; 307 Regs64 ss; 308 FloatState64 fs; 309 byte Pad_cgo_0[4]; 310 }; 311 312 struct Regs32 { 313 uint32 eax; 314 uint32 ebx; 315 uint32 ecx; 316 uint32 edx; 317 uint32 edi; 318 uint32 esi; 319 uint32 ebp; 320 uint32 esp; 321 uint32 ss; 322 uint32 eflags; 323 uint32 eip; 324 uint32 cs; 325 uint32 ds; 326 uint32 es; 327 uint32 fs; 328 uint32 gs; 329 }; 330 struct FloatState32 { 331 int32 fpu_reserved[2]; 332 FPControl fpu_fcw; 333 FPStatus fpu_fsw; 334 uint8 fpu_ftw; 335 uint8 fpu_rsrv1; 336 uint16 fpu_fop; 337 uint32 fpu_ip; 338 uint16 fpu_cs; 339 uint16 fpu_rsrv2; 340 uint32 fpu_dp; 341 uint16 fpu_ds; 342 uint16 fpu_rsrv3; 343 uint32 fpu_mxcsr; 344 uint32 fpu_mxcsrmask; 345 RegMMST fpu_stmm0; 346 RegMMST fpu_stmm1; 347 RegMMST fpu_stmm2; 348 RegMMST fpu_stmm3; 349 RegMMST fpu_stmm4; 350 RegMMST fpu_stmm5; 351 RegMMST fpu_stmm6; 352 RegMMST fpu_stmm7; 353 RegXMM fpu_xmm0; 354 RegXMM fpu_xmm1; 355 RegXMM fpu_xmm2; 356 RegXMM fpu_xmm3; 357 RegXMM fpu_xmm4; 358 RegXMM fpu_xmm5; 359 RegXMM fpu_xmm6; 360 RegXMM fpu_xmm7; 361 int8 fpu_rsrv4[224]; 362 int32 fpu_reserved1; 363 }; 364 struct ExceptionState32 { 365 uint16 trapno; 366 uint16 cpu; 367 uint32 err; 368 uint32 faultvaddr; 369 }; 370 struct Mcontext32 { 371 ExceptionState32 es; 372 Regs32 ss; 373 FloatState32 fs; 374 }; 375 376 struct Ucontext { 377 int32 uc_onstack; 378 uint32 uc_sigmask; 379 StackT uc_stack; 380 Ucontext *uc_link; 381 uint64 uc_mcsize; 382 Mcontext64 *uc_mcontext; 383 }; 384 385 struct Kevent { 386 uint64 ident; 387 int16 filter; 388 uint16 flags; 389 uint32 fflags; 390 int64 data; 391 byte *udata; 392 }; 393 394 395 #pragma pack off