github.com/yukk001/go1.10.8@v0.0.0-20190813125351-6df2d3982e20/src/cmd/compile/internal/ssa/gen/MIPS64.rules (about) 1 // Copyright 2016 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 (AddPtr x y) -> (ADDV x y) 6 (Add64 x y) -> (ADDV x y) 7 (Add32 x y) -> (ADDV x y) 8 (Add16 x y) -> (ADDV x y) 9 (Add8 x y) -> (ADDV x y) 10 (Add32F x y) -> (ADDF x y) 11 (Add64F x y) -> (ADDD x y) 12 13 (SubPtr x y) -> (SUBV x y) 14 (Sub64 x y) -> (SUBV x y) 15 (Sub32 x y) -> (SUBV x y) 16 (Sub16 x y) -> (SUBV x y) 17 (Sub8 x y) -> (SUBV x y) 18 (Sub32F x y) -> (SUBF x y) 19 (Sub64F x y) -> (SUBD x y) 20 21 (Mul64 x y) -> (Select1 (MULVU x y)) 22 (Mul32 x y) -> (Select1 (MULVU x y)) 23 (Mul16 x y) -> (Select1 (MULVU x y)) 24 (Mul8 x y) -> (Select1 (MULVU x y)) 25 (Mul32F x y) -> (MULF x y) 26 (Mul64F x y) -> (MULD x y) 27 28 (Hmul64 x y) -> (Select0 (MULV x y)) 29 (Hmul64u x y) -> (Select0 (MULVU x y)) 30 (Hmul32 x y) -> (SRAVconst (Select1 <typ.Int64> (MULV (SignExt32to64 x) (SignExt32to64 y))) [32]) 31 (Hmul32u x y) -> (SRLVconst (Select1 <typ.UInt64> (MULVU (ZeroExt32to64 x) (ZeroExt32to64 y))) [32]) 32 33 (Div64 x y) -> (Select1 (DIVV x y)) 34 (Div64u x y) -> (Select1 (DIVVU x y)) 35 (Div32 x y) -> (Select1 (DIVV (SignExt32to64 x) (SignExt32to64 y))) 36 (Div32u x y) -> (Select1 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y))) 37 (Div16 x y) -> (Select1 (DIVV (SignExt16to64 x) (SignExt16to64 y))) 38 (Div16u x y) -> (Select1 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))) 39 (Div8 x y) -> (Select1 (DIVV (SignExt8to64 x) (SignExt8to64 y))) 40 (Div8u x y) -> (Select1 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))) 41 (Div32F x y) -> (DIVF x y) 42 (Div64F x y) -> (DIVD x y) 43 44 (Mod64 x y) -> (Select0 (DIVV x y)) 45 (Mod64u x y) -> (Select0 (DIVVU x y)) 46 (Mod32 x y) -> (Select0 (DIVV (SignExt32to64 x) (SignExt32to64 y))) 47 (Mod32u x y) -> (Select0 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y))) 48 (Mod16 x y) -> (Select0 (DIVV (SignExt16to64 x) (SignExt16to64 y))) 49 (Mod16u x y) -> (Select0 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))) 50 (Mod8 x y) -> (Select0 (DIVV (SignExt8to64 x) (SignExt8to64 y))) 51 (Mod8u x y) -> (Select0 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))) 52 53 // (x + y) / 2 with x>=y -> (x - y) / 2 + y 54 (Avg64u <t> x y) -> (ADDV (SRLVconst <t> (SUBV <t> x y) [1]) y) 55 56 (And64 x y) -> (AND x y) 57 (And32 x y) -> (AND x y) 58 (And16 x y) -> (AND x y) 59 (And8 x y) -> (AND x y) 60 61 (Or64 x y) -> (OR x y) 62 (Or32 x y) -> (OR x y) 63 (Or16 x y) -> (OR x y) 64 (Or8 x y) -> (OR x y) 65 66 (Xor64 x y) -> (XOR x y) 67 (Xor32 x y) -> (XOR x y) 68 (Xor16 x y) -> (XOR x y) 69 (Xor8 x y) -> (XOR x y) 70 71 // shifts 72 // hardware instruction uses only the low 6 bits of the shift 73 // we compare to 64 to ensure Go semantics for large shifts 74 (Lsh64x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y)) 75 (Lsh64x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 76 (Lsh64x16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 77 (Lsh64x8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 78 79 (Lsh32x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y)) 80 (Lsh32x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 81 (Lsh32x16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 82 (Lsh32x8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 83 84 (Lsh16x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y)) 85 (Lsh16x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 86 (Lsh16x16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 87 (Lsh16x8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 88 89 (Lsh8x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y)) 90 (Lsh8x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 91 (Lsh8x16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 92 (Lsh8x8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 93 94 (Rsh64Ux64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> x y)) 95 (Rsh64Ux32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> x (ZeroExt32to64 y))) 96 (Rsh64Ux16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> x (ZeroExt16to64 y))) 97 (Rsh64Ux8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> x (ZeroExt8to64 y))) 98 99 (Rsh32Ux64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt32to64 x) y)) 100 (Rsh32Ux32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt32to64 y))) 101 (Rsh32Ux16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt16to64 y))) 102 (Rsh32Ux8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt8to64 y))) 103 104 (Rsh16Ux64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt16to64 x) y)) 105 (Rsh16Ux32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt32to64 y))) 106 (Rsh16Ux16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt16to64 y))) 107 (Rsh16Ux8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt8to64 y))) 108 109 (Rsh8Ux64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt8to64 x) y)) 110 (Rsh8Ux32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt32to64 y))) 111 (Rsh8Ux16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt16to64 y))) 112 (Rsh8Ux8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt8to64 y))) 113 114 (Rsh64x64 <t> x y) -> (SRAV x (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y)) 115 (Rsh64x32 <t> x y) -> (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y))) 116 (Rsh64x16 <t> x y) -> (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y))) 117 (Rsh64x8 <t> x y) -> (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y))) 118 119 (Rsh32x64 <t> x y) -> (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y)) 120 (Rsh32x32 <t> x y) -> (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y))) 121 (Rsh32x16 <t> x y) -> (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y))) 122 (Rsh32x8 <t> x y) -> (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y))) 123 124 (Rsh16x64 <t> x y) -> (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y)) 125 (Rsh16x32 <t> x y) -> (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y))) 126 (Rsh16x16 <t> x y) -> (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y))) 127 (Rsh16x8 <t> x y) -> (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y))) 128 129 (Rsh8x64 <t> x y) -> (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y)) 130 (Rsh8x32 <t> x y) -> (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y))) 131 (Rsh8x16 <t> x y) -> (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y))) 132 (Rsh8x8 <t> x y) -> (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y))) 133 134 // unary ops 135 (Neg64 x) -> (NEGV x) 136 (Neg32 x) -> (NEGV x) 137 (Neg16 x) -> (NEGV x) 138 (Neg8 x) -> (NEGV x) 139 (Neg32F x) -> (NEGF x) 140 (Neg64F x) -> (NEGD x) 141 142 (Com64 x) -> (NOR (MOVVconst [0]) x) 143 (Com32 x) -> (NOR (MOVVconst [0]) x) 144 (Com16 x) -> (NOR (MOVVconst [0]) x) 145 (Com8 x) -> (NOR (MOVVconst [0]) x) 146 147 // boolean ops -- booleans are represented with 0=false, 1=true 148 (AndB x y) -> (AND x y) 149 (OrB x y) -> (OR x y) 150 (EqB x y) -> (XOR (MOVVconst [1]) (XOR <typ.Bool> x y)) 151 (NeqB x y) -> (XOR x y) 152 (Not x) -> (XORconst [1] x) 153 154 // constants 155 (Const64 [val]) -> (MOVVconst [val]) 156 (Const32 [val]) -> (MOVVconst [val]) 157 (Const16 [val]) -> (MOVVconst [val]) 158 (Const8 [val]) -> (MOVVconst [val]) 159 (Const32F [val]) -> (MOVFconst [val]) 160 (Const64F [val]) -> (MOVDconst [val]) 161 (ConstNil) -> (MOVVconst [0]) 162 (ConstBool [b]) -> (MOVVconst [b]) 163 164 (Slicemask <t> x) -> (SRAVconst (NEGV <t> x) [63]) 165 166 // truncations 167 // Because we ignore high parts of registers, truncates are just copies. 168 (Trunc16to8 x) -> x 169 (Trunc32to8 x) -> x 170 (Trunc32to16 x) -> x 171 (Trunc64to8 x) -> x 172 (Trunc64to16 x) -> x 173 (Trunc64to32 x) -> x 174 175 // Zero-/Sign-extensions 176 (ZeroExt8to16 x) -> (MOVBUreg x) 177 (ZeroExt8to32 x) -> (MOVBUreg x) 178 (ZeroExt16to32 x) -> (MOVHUreg x) 179 (ZeroExt8to64 x) -> (MOVBUreg x) 180 (ZeroExt16to64 x) -> (MOVHUreg x) 181 (ZeroExt32to64 x) -> (MOVWUreg x) 182 183 (SignExt8to16 x) -> (MOVBreg x) 184 (SignExt8to32 x) -> (MOVBreg x) 185 (SignExt16to32 x) -> (MOVHreg x) 186 (SignExt8to64 x) -> (MOVBreg x) 187 (SignExt16to64 x) -> (MOVHreg x) 188 (SignExt32to64 x) -> (MOVWreg x) 189 190 // float <-> int conversion 191 (Cvt32to32F x) -> (MOVWF x) 192 (Cvt32to64F x) -> (MOVWD x) 193 (Cvt64to32F x) -> (MOVVF x) 194 (Cvt64to64F x) -> (MOVVD x) 195 (Cvt32Fto32 x) -> (TRUNCFW x) 196 (Cvt64Fto32 x) -> (TRUNCDW x) 197 (Cvt32Fto64 x) -> (TRUNCFV x) 198 (Cvt64Fto64 x) -> (TRUNCDV x) 199 (Cvt32Fto64F x) -> (MOVFD x) 200 (Cvt64Fto32F x) -> (MOVDF x) 201 202 (Round32F x) -> x 203 (Round64F x) -> x 204 205 // comparisons 206 (Eq8 x y) -> (SGTU (MOVVconst [1]) (XOR (ZeroExt8to64 x) (ZeroExt8to64 y))) 207 (Eq16 x y) -> (SGTU (MOVVconst [1]) (XOR (ZeroExt16to64 x) (ZeroExt16to64 y))) 208 (Eq32 x y) -> (SGTU (MOVVconst [1]) (XOR (ZeroExt32to64 x) (ZeroExt32to64 y))) 209 (Eq64 x y) -> (SGTU (MOVVconst [1]) (XOR x y)) 210 (EqPtr x y) -> (SGTU (MOVVconst [1]) (XOR x y)) 211 (Eq32F x y) -> (FPFlagTrue (CMPEQF x y)) 212 (Eq64F x y) -> (FPFlagTrue (CMPEQD x y)) 213 214 (Neq8 x y) -> (SGTU (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)) (MOVVconst [0])) 215 (Neq16 x y) -> (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to64 y)) (MOVVconst [0])) 216 (Neq32 x y) -> (SGTU (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)) (MOVVconst [0])) 217 (Neq64 x y) -> (SGTU (XOR x y) (MOVVconst [0])) 218 (NeqPtr x y) -> (SGTU (XOR x y) (MOVVconst [0])) 219 (Neq32F x y) -> (FPFlagFalse (CMPEQF x y)) 220 (Neq64F x y) -> (FPFlagFalse (CMPEQD x y)) 221 222 (Less8 x y) -> (SGT (SignExt8to64 y) (SignExt8to64 x)) 223 (Less16 x y) -> (SGT (SignExt16to64 y) (SignExt16to64 x)) 224 (Less32 x y) -> (SGT (SignExt32to64 y) (SignExt32to64 x)) 225 (Less64 x y) -> (SGT y x) 226 (Less32F x y) -> (FPFlagTrue (CMPGTF y x)) // reverse operands to work around NaN 227 (Less64F x y) -> (FPFlagTrue (CMPGTD y x)) // reverse operands to work around NaN 228 229 (Less8U x y) -> (SGTU (ZeroExt8to64 y) (ZeroExt8to64 x)) 230 (Less16U x y) -> (SGTU (ZeroExt16to64 y) (ZeroExt16to64 x)) 231 (Less32U x y) -> (SGTU (ZeroExt32to64 y) (ZeroExt32to64 x)) 232 (Less64U x y) -> (SGTU y x) 233 234 (Leq8 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt8to64 x) (SignExt8to64 y))) 235 (Leq16 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt16to64 x) (SignExt16to64 y))) 236 (Leq32 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt32to64 x) (SignExt32to64 y))) 237 (Leq64 x y) -> (XOR (MOVVconst [1]) (SGT x y)) 238 (Leq32F x y) -> (FPFlagTrue (CMPGEF y x)) // reverse operands to work around NaN 239 (Leq64F x y) -> (FPFlagTrue (CMPGED y x)) // reverse operands to work around NaN 240 241 (Leq8U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt8to64 x) (ZeroExt8to64 y))) 242 (Leq16U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt16to64 x) (ZeroExt16to64 y))) 243 (Leq32U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt32to64 x) (ZeroExt32to64 y))) 244 (Leq64U x y) -> (XOR (MOVVconst [1]) (SGTU x y)) 245 246 (Greater8 x y) -> (SGT (SignExt8to64 x) (SignExt8to64 y)) 247 (Greater16 x y) -> (SGT (SignExt16to64 x) (SignExt16to64 y)) 248 (Greater32 x y) -> (SGT (SignExt32to64 x) (SignExt32to64 y)) 249 (Greater64 x y) -> (SGT x y) 250 (Greater32F x y) -> (FPFlagTrue (CMPGTF x y)) 251 (Greater64F x y) -> (FPFlagTrue (CMPGTD x y)) 252 253 (Greater8U x y) -> (SGTU (ZeroExt8to64 x) (ZeroExt8to64 y)) 254 (Greater16U x y) -> (SGTU (ZeroExt16to64 x) (ZeroExt16to64 y)) 255 (Greater32U x y) -> (SGTU (ZeroExt32to64 x) (ZeroExt32to64 y)) 256 (Greater64U x y) -> (SGTU x y) 257 258 (Geq8 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt8to64 y) (SignExt8to64 x))) 259 (Geq16 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt16to64 y) (SignExt16to64 x))) 260 (Geq32 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt32to64 y) (SignExt32to64 x))) 261 (Geq64 x y) -> (XOR (MOVVconst [1]) (SGT y x)) 262 (Geq32F x y) -> (FPFlagTrue (CMPGEF x y)) 263 (Geq64F x y) -> (FPFlagTrue (CMPGED x y)) 264 265 (Geq8U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt8to64 y) (ZeroExt8to64 x))) 266 (Geq16U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt16to64 y) (ZeroExt16to64 x))) 267 (Geq32U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt32to64 y) (ZeroExt32to64 x))) 268 (Geq64U x y) -> (XOR (MOVVconst [1]) (SGTU y x)) 269 270 (OffPtr [off] ptr:(SP)) -> (MOVVaddr [off] ptr) 271 (OffPtr [off] ptr) -> (ADDVconst [off] ptr) 272 273 (Addr {sym} base) -> (MOVVaddr {sym} base) 274 275 // loads 276 (Load <t> ptr mem) && t.IsBoolean() -> (MOVBUload ptr mem) 277 (Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) -> (MOVBload ptr mem) 278 (Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) -> (MOVBUload ptr mem) 279 (Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) -> (MOVHload ptr mem) 280 (Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) -> (MOVHUload ptr mem) 281 (Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) -> (MOVWload ptr mem) 282 (Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) -> (MOVWUload ptr mem) 283 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) -> (MOVVload ptr mem) 284 (Load <t> ptr mem) && is32BitFloat(t) -> (MOVFload ptr mem) 285 (Load <t> ptr mem) && is64BitFloat(t) -> (MOVDload ptr mem) 286 287 // stores 288 (Store {t} ptr val mem) && t.(*types.Type).Size() == 1 -> (MOVBstore ptr val mem) 289 (Store {t} ptr val mem) && t.(*types.Type).Size() == 2 -> (MOVHstore ptr val mem) 290 (Store {t} ptr val mem) && t.(*types.Type).Size() == 4 && !is32BitFloat(val.Type) -> (MOVWstore ptr val mem) 291 (Store {t} ptr val mem) && t.(*types.Type).Size() == 8 && !is64BitFloat(val.Type) -> (MOVVstore ptr val mem) 292 (Store {t} ptr val mem) && t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) -> (MOVFstore ptr val mem) 293 (Store {t} ptr val mem) && t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) -> (MOVDstore ptr val mem) 294 295 // zeroing 296 (Zero [0] _ mem) -> mem 297 (Zero [1] ptr mem) -> (MOVBstore ptr (MOVVconst [0]) mem) 298 (Zero [2] {t} ptr mem) && t.(*types.Type).Alignment()%2 == 0 -> 299 (MOVHstore ptr (MOVVconst [0]) mem) 300 (Zero [2] ptr mem) -> 301 (MOVBstore [1] ptr (MOVVconst [0]) 302 (MOVBstore [0] ptr (MOVVconst [0]) mem)) 303 (Zero [4] {t} ptr mem) && t.(*types.Type).Alignment()%4 == 0 -> 304 (MOVWstore ptr (MOVVconst [0]) mem) 305 (Zero [4] {t} ptr mem) && t.(*types.Type).Alignment()%2 == 0 -> 306 (MOVHstore [2] ptr (MOVVconst [0]) 307 (MOVHstore [0] ptr (MOVVconst [0]) mem)) 308 (Zero [4] ptr mem) -> 309 (MOVBstore [3] ptr (MOVVconst [0]) 310 (MOVBstore [2] ptr (MOVVconst [0]) 311 (MOVBstore [1] ptr (MOVVconst [0]) 312 (MOVBstore [0] ptr (MOVVconst [0]) mem)))) 313 (Zero [8] {t} ptr mem) && t.(*types.Type).Alignment()%8 == 0 -> 314 (MOVVstore ptr (MOVVconst [0]) mem) 315 (Zero [8] {t} ptr mem) && t.(*types.Type).Alignment()%4 == 0 -> 316 (MOVWstore [4] ptr (MOVVconst [0]) 317 (MOVWstore [0] ptr (MOVVconst [0]) mem)) 318 (Zero [8] {t} ptr mem) && t.(*types.Type).Alignment()%2 == 0 -> 319 (MOVHstore [6] ptr (MOVVconst [0]) 320 (MOVHstore [4] ptr (MOVVconst [0]) 321 (MOVHstore [2] ptr (MOVVconst [0]) 322 (MOVHstore [0] ptr (MOVVconst [0]) mem)))) 323 324 (Zero [3] ptr mem) -> 325 (MOVBstore [2] ptr (MOVVconst [0]) 326 (MOVBstore [1] ptr (MOVVconst [0]) 327 (MOVBstore [0] ptr (MOVVconst [0]) mem))) 328 (Zero [6] {t} ptr mem) && t.(*types.Type).Alignment()%2 == 0 -> 329 (MOVHstore [4] ptr (MOVVconst [0]) 330 (MOVHstore [2] ptr (MOVVconst [0]) 331 (MOVHstore [0] ptr (MOVVconst [0]) mem))) 332 (Zero [12] {t} ptr mem) && t.(*types.Type).Alignment()%4 == 0 -> 333 (MOVWstore [8] ptr (MOVVconst [0]) 334 (MOVWstore [4] ptr (MOVVconst [0]) 335 (MOVWstore [0] ptr (MOVVconst [0]) mem))) 336 (Zero [16] {t} ptr mem) && t.(*types.Type).Alignment()%8 == 0 -> 337 (MOVVstore [8] ptr (MOVVconst [0]) 338 (MOVVstore [0] ptr (MOVVconst [0]) mem)) 339 (Zero [24] {t} ptr mem) && t.(*types.Type).Alignment()%8 == 0 -> 340 (MOVVstore [16] ptr (MOVVconst [0]) 341 (MOVVstore [8] ptr (MOVVconst [0]) 342 (MOVVstore [0] ptr (MOVVconst [0]) mem))) 343 344 // medium zeroing uses a duff device 345 // 8, and 128 are magic constants, see runtime/mkduff.go 346 (Zero [s] {t} ptr mem) 347 && s%8 == 0 && s > 24 && s <= 8*128 348 && t.(*types.Type).Alignment()%8 == 0 && !config.noDuffDevice -> 349 (DUFFZERO [8 * (128 - int64(s/8))] ptr mem) 350 351 // large or unaligned zeroing uses a loop 352 (Zero [s] {t} ptr mem) 353 && (s > 8*128 || config.noDuffDevice) || t.(*types.Type).Alignment()%8 != 0 -> 354 (LoweredZero [t.(*types.Type).Alignment()] 355 ptr 356 (ADDVconst <ptr.Type> ptr [s-moveSize(t.(*types.Type).Alignment(), config)]) 357 mem) 358 359 // moves 360 (Move [0] _ _ mem) -> mem 361 (Move [1] dst src mem) -> (MOVBstore dst (MOVBload src mem) mem) 362 (Move [2] {t} dst src mem) && t.(*types.Type).Alignment()%2 == 0 -> 363 (MOVHstore dst (MOVHload src mem) mem) 364 (Move [2] dst src mem) -> 365 (MOVBstore [1] dst (MOVBload [1] src mem) 366 (MOVBstore dst (MOVBload src mem) mem)) 367 (Move [4] {t} dst src mem) && t.(*types.Type).Alignment()%4 == 0 -> 368 (MOVWstore dst (MOVWload src mem) mem) 369 (Move [4] {t} dst src mem) && t.(*types.Type).Alignment()%2 == 0 -> 370 (MOVHstore [2] dst (MOVHload [2] src mem) 371 (MOVHstore dst (MOVHload src mem) mem)) 372 (Move [4] dst src mem) -> 373 (MOVBstore [3] dst (MOVBload [3] src mem) 374 (MOVBstore [2] dst (MOVBload [2] src mem) 375 (MOVBstore [1] dst (MOVBload [1] src mem) 376 (MOVBstore dst (MOVBload src mem) mem)))) 377 (Move [8] {t} dst src mem) && t.(*types.Type).Alignment()%8 == 0 -> 378 (MOVVstore dst (MOVVload src mem) mem) 379 (Move [8] {t} dst src mem) && t.(*types.Type).Alignment()%4 == 0 -> 380 (MOVWstore [4] dst (MOVWload [4] src mem) 381 (MOVWstore dst (MOVWload src mem) mem)) 382 (Move [8] {t} dst src mem) && t.(*types.Type).Alignment()%2 == 0 -> 383 (MOVHstore [6] dst (MOVHload [6] src mem) 384 (MOVHstore [4] dst (MOVHload [4] src mem) 385 (MOVHstore [2] dst (MOVHload [2] src mem) 386 (MOVHstore dst (MOVHload src mem) mem)))) 387 388 (Move [3] dst src mem) -> 389 (MOVBstore [2] dst (MOVBload [2] src mem) 390 (MOVBstore [1] dst (MOVBload [1] src mem) 391 (MOVBstore dst (MOVBload src mem) mem))) 392 (Move [6] {t} dst src mem) && t.(*types.Type).Alignment()%2 == 0 -> 393 (MOVHstore [4] dst (MOVHload [4] src mem) 394 (MOVHstore [2] dst (MOVHload [2] src mem) 395 (MOVHstore dst (MOVHload src mem) mem))) 396 (Move [12] {t} dst src mem) && t.(*types.Type).Alignment()%4 == 0 -> 397 (MOVWstore [8] dst (MOVWload [8] src mem) 398 (MOVWstore [4] dst (MOVWload [4] src mem) 399 (MOVWstore dst (MOVWload src mem) mem))) 400 (Move [16] {t} dst src mem) && t.(*types.Type).Alignment()%8 == 0 -> 401 (MOVVstore [8] dst (MOVVload [8] src mem) 402 (MOVVstore dst (MOVVload src mem) mem)) 403 (Move [24] {t} dst src mem) && t.(*types.Type).Alignment()%8 == 0 -> 404 (MOVVstore [16] dst (MOVVload [16] src mem) 405 (MOVVstore [8] dst (MOVVload [8] src mem) 406 (MOVVstore dst (MOVVload src mem) mem))) 407 408 // large or unaligned move uses a loop 409 (Move [s] {t} dst src mem) 410 && s > 24 || t.(*types.Type).Alignment()%8 != 0 -> 411 (LoweredMove [t.(*types.Type).Alignment()] 412 dst 413 src 414 (ADDVconst <src.Type> src [s-moveSize(t.(*types.Type).Alignment(), config)]) 415 mem) 416 417 // calls 418 (StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem) 419 (ClosureCall [argwid] entry closure mem) -> (CALLclosure [argwid] entry closure mem) 420 (InterCall [argwid] entry mem) -> (CALLinter [argwid] entry mem) 421 422 // atomic intrinsics 423 (AtomicLoad32 ptr mem) -> (LoweredAtomicLoad32 ptr mem) 424 (AtomicLoad64 ptr mem) -> (LoweredAtomicLoad64 ptr mem) 425 (AtomicLoadPtr ptr mem) -> (LoweredAtomicLoad64 ptr mem) 426 427 (AtomicStore32 ptr val mem) -> (LoweredAtomicStore32 ptr val mem) 428 (AtomicStore64 ptr val mem) -> (LoweredAtomicStore64 ptr val mem) 429 (AtomicStorePtrNoWB ptr val mem) -> (LoweredAtomicStore64 ptr val mem) 430 431 (AtomicExchange32 ptr val mem) -> (LoweredAtomicExchange32 ptr val mem) 432 (AtomicExchange64 ptr val mem) -> (LoweredAtomicExchange64 ptr val mem) 433 434 (AtomicAdd32 ptr val mem) -> (LoweredAtomicAdd32 ptr val mem) 435 (AtomicAdd64 ptr val mem) -> (LoweredAtomicAdd64 ptr val mem) 436 437 (AtomicCompareAndSwap32 ptr old new_ mem) -> (LoweredAtomicCas32 ptr old new_ mem) 438 (AtomicCompareAndSwap64 ptr old new_ mem) -> (LoweredAtomicCas64 ptr old new_ mem) 439 440 // checks 441 (NilCheck ptr mem) -> (LoweredNilCheck ptr mem) 442 (IsNonNil ptr) -> (SGTU ptr (MOVVconst [0])) 443 (IsInBounds idx len) -> (SGTU len idx) 444 (IsSliceInBounds idx len) -> (XOR (MOVVconst [1]) (SGTU idx len)) 445 446 // pseudo-ops 447 (GetClosurePtr) -> (LoweredGetClosurePtr) 448 (GetCallerSP) -> (LoweredGetCallerSP) 449 (Convert x mem) -> (MOVVconvert x mem) 450 451 (If cond yes no) -> (NE cond yes no) 452 453 // Optimizations 454 455 // Absorb boolean tests into block 456 (NE (FPFlagTrue cmp) yes no) -> (FPT cmp yes no) 457 (NE (FPFlagFalse cmp) yes no) -> (FPF cmp yes no) 458 (EQ (FPFlagTrue cmp) yes no) -> (FPF cmp yes no) 459 (EQ (FPFlagFalse cmp) yes no) -> (FPT cmp yes no) 460 (NE (XORconst [1] cmp:(SGT _ _)) yes no) -> (EQ cmp yes no) 461 (NE (XORconst [1] cmp:(SGTU _ _)) yes no) -> (EQ cmp yes no) 462 (NE (XORconst [1] cmp:(SGTconst _)) yes no) -> (EQ cmp yes no) 463 (NE (XORconst [1] cmp:(SGTUconst _)) yes no) -> (EQ cmp yes no) 464 (EQ (XORconst [1] cmp:(SGT _ _)) yes no) -> (NE cmp yes no) 465 (EQ (XORconst [1] cmp:(SGTU _ _)) yes no) -> (NE cmp yes no) 466 (EQ (XORconst [1] cmp:(SGTconst _)) yes no) -> (NE cmp yes no) 467 (EQ (XORconst [1] cmp:(SGTUconst _)) yes no) -> (NE cmp yes no) 468 (NE (SGTUconst [1] x) yes no) -> (EQ x yes no) 469 (EQ (SGTUconst [1] x) yes no) -> (NE x yes no) 470 (NE (SGTU x (MOVVconst [0])) yes no) -> (NE x yes no) 471 (EQ (SGTU x (MOVVconst [0])) yes no) -> (EQ x yes no) 472 (NE (SGTconst [0] x) yes no) -> (LTZ x yes no) 473 (EQ (SGTconst [0] x) yes no) -> (GEZ x yes no) 474 (NE (SGT x (MOVVconst [0])) yes no) -> (GTZ x yes no) 475 (EQ (SGT x (MOVVconst [0])) yes no) -> (LEZ x yes no) 476 477 // fold offset into address 478 (ADDVconst [off1] (MOVVaddr [off2] {sym} ptr)) -> (MOVVaddr [off1+off2] {sym} ptr) 479 480 // fold address into load/store 481 (MOVBload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem) 482 (MOVBUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBUload [off1+off2] {sym} ptr mem) 483 (MOVHload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHload [off1+off2] {sym} ptr mem) 484 (MOVHUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHUload [off1+off2] {sym} ptr mem) 485 (MOVWload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem) 486 (MOVWUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWUload [off1+off2] {sym} ptr mem) 487 (MOVVload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVVload [off1+off2] {sym} ptr mem) 488 (MOVFload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVFload [off1+off2] {sym} ptr mem) 489 (MOVDload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem) 490 491 (MOVBstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem) 492 (MOVHstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} ptr val mem) 493 (MOVWstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem) 494 (MOVVstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVVstore [off1+off2] {sym} ptr val mem) 495 (MOVFstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVFstore [off1+off2] {sym} ptr val mem) 496 (MOVDstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} ptr val mem) 497 (MOVBstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBstorezero [off1+off2] {sym} ptr mem) 498 (MOVHstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHstorezero [off1+off2] {sym} ptr mem) 499 (MOVWstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWstorezero [off1+off2] {sym} ptr mem) 500 (MOVVstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVVstorezero [off1+off2] {sym} ptr mem) 501 502 (MOVBload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 503 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 504 (MOVBUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 505 (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 506 (MOVHload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 507 (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 508 (MOVHUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 509 (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 510 (MOVWload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 511 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 512 (MOVWUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 513 (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 514 (MOVVload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 515 (MOVVload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 516 (MOVFload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 517 (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 518 (MOVDload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 519 (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 520 521 (MOVBstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 522 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 523 (MOVHstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 524 (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 525 (MOVWstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 526 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 527 (MOVVstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 528 (MOVVstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 529 (MOVFstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 530 (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 531 (MOVDstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 532 (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 533 (MOVBstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 534 (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 535 (MOVHstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 536 (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 537 (MOVWstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 538 (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 539 (MOVVstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 540 (MOVVstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 541 542 // store zero 543 (MOVBstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVBstorezero [off] {sym} ptr mem) 544 (MOVHstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVHstorezero [off] {sym} ptr mem) 545 (MOVWstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVWstorezero [off] {sym} ptr mem) 546 (MOVVstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVVstorezero [off] {sym} ptr mem) 547 548 // don't extend after proper load 549 (MOVBreg x:(MOVBload _ _)) -> (MOVVreg x) 550 (MOVBUreg x:(MOVBUload _ _)) -> (MOVVreg x) 551 (MOVHreg x:(MOVBload _ _)) -> (MOVVreg x) 552 (MOVHreg x:(MOVBUload _ _)) -> (MOVVreg x) 553 (MOVHreg x:(MOVHload _ _)) -> (MOVVreg x) 554 (MOVHUreg x:(MOVBUload _ _)) -> (MOVVreg x) 555 (MOVHUreg x:(MOVHUload _ _)) -> (MOVVreg x) 556 (MOVWreg x:(MOVBload _ _)) -> (MOVVreg x) 557 (MOVWreg x:(MOVBUload _ _)) -> (MOVVreg x) 558 (MOVWreg x:(MOVHload _ _)) -> (MOVVreg x) 559 (MOVWreg x:(MOVHUload _ _)) -> (MOVVreg x) 560 (MOVWreg x:(MOVWload _ _)) -> (MOVVreg x) 561 (MOVWUreg x:(MOVBUload _ _)) -> (MOVVreg x) 562 (MOVWUreg x:(MOVHUload _ _)) -> (MOVVreg x) 563 (MOVWUreg x:(MOVWUload _ _)) -> (MOVVreg x) 564 565 // fold double extensions 566 (MOVBreg x:(MOVBreg _)) -> (MOVVreg x) 567 (MOVBUreg x:(MOVBUreg _)) -> (MOVVreg x) 568 (MOVHreg x:(MOVBreg _)) -> (MOVVreg x) 569 (MOVHreg x:(MOVBUreg _)) -> (MOVVreg x) 570 (MOVHreg x:(MOVHreg _)) -> (MOVVreg x) 571 (MOVHUreg x:(MOVBUreg _)) -> (MOVVreg x) 572 (MOVHUreg x:(MOVHUreg _)) -> (MOVVreg x) 573 (MOVWreg x:(MOVBreg _)) -> (MOVVreg x) 574 (MOVWreg x:(MOVBUreg _)) -> (MOVVreg x) 575 (MOVWreg x:(MOVHreg _)) -> (MOVVreg x) 576 (MOVWreg x:(MOVHreg _)) -> (MOVVreg x) 577 (MOVWreg x:(MOVWreg _)) -> (MOVVreg x) 578 (MOVWUreg x:(MOVBUreg _)) -> (MOVVreg x) 579 (MOVWUreg x:(MOVHUreg _)) -> (MOVVreg x) 580 (MOVWUreg x:(MOVWUreg _)) -> (MOVVreg x) 581 582 // don't extend before store 583 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 584 (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 585 (MOVBstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 586 (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 587 (MOVBstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 588 (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 589 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 590 (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 591 (MOVHstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 592 (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 593 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 594 (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 595 596 // if a register move has only 1 use, just use the same register without emitting instruction 597 // MOVVnop doesn't emit instruction, only for ensuring the type. 598 (MOVVreg x) && x.Uses == 1 -> (MOVVnop x) 599 600 // fold constant into arithmatic ops 601 (ADDV x (MOVVconst [c])) && is32Bit(c) -> (ADDVconst [c] x) 602 (SUBV x (MOVVconst [c])) && is32Bit(c) -> (SUBVconst [c] x) 603 (AND x (MOVVconst [c])) && is32Bit(c) -> (ANDconst [c] x) 604 (OR x (MOVVconst [c])) && is32Bit(c) -> (ORconst [c] x) 605 (XOR x (MOVVconst [c])) && is32Bit(c) -> (XORconst [c] x) 606 (NOR x (MOVVconst [c])) && is32Bit(c) -> (NORconst [c] x) 607 608 (SLLV _ (MOVVconst [c])) && uint64(c)>=64 -> (MOVVconst [0]) 609 (SRLV _ (MOVVconst [c])) && uint64(c)>=64 -> (MOVVconst [0]) 610 (SRAV x (MOVVconst [c])) && uint64(c)>=64 -> (SRAVconst x [63]) 611 (SLLV x (MOVVconst [c])) -> (SLLVconst x [c]) 612 (SRLV x (MOVVconst [c])) -> (SRLVconst x [c]) 613 (SRAV x (MOVVconst [c])) -> (SRAVconst x [c]) 614 615 (SGT (MOVVconst [c]) x) && is32Bit(c) -> (SGTconst [c] x) 616 (SGTU (MOVVconst [c]) x) && is32Bit(c) -> (SGTUconst [c] x) 617 618 // mul by constant 619 (Select1 (MULVU x (MOVVconst [-1]))) -> (NEGV x) 620 (Select1 (MULVU _ (MOVVconst [0]))) -> (MOVVconst [0]) 621 (Select1 (MULVU x (MOVVconst [1]))) -> x 622 (Select1 (MULVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (SLLVconst [log2(c)] x) 623 624 (Select1 (MULVU (MOVVconst [-1]) x)) -> (NEGV x) 625 (Select1 (MULVU (MOVVconst [0]) _)) -> (MOVVconst [0]) 626 (Select1 (MULVU (MOVVconst [1]) x)) -> x 627 (Select1 (MULVU (MOVVconst [c]) x)) && isPowerOfTwo(c) -> (SLLVconst [log2(c)] x) 628 629 // div by constant 630 (Select1 (DIVVU x (MOVVconst [1]))) -> x 631 (Select1 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (SRLVconst [log2(c)] x) 632 (Select0 (DIVVU _ (MOVVconst [1]))) -> (MOVVconst [0]) // mod 633 (Select0 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (ANDconst [c-1] x) // mod 634 635 // generic simplifications 636 (ADDV x (NEGV y)) -> (SUBV x y) 637 (SUBV x x) -> (MOVVconst [0]) 638 (SUBV (MOVVconst [0]) x) -> (NEGV x) 639 (AND x x) -> x 640 (OR x x) -> x 641 (XOR x x) -> (MOVVconst [0]) 642 643 // remove redundant *const ops 644 (ADDVconst [0] x) -> x 645 (SUBVconst [0] x) -> x 646 (ANDconst [0] _) -> (MOVVconst [0]) 647 (ANDconst [-1] x) -> x 648 (ORconst [0] x) -> x 649 (ORconst [-1] _) -> (MOVVconst [-1]) 650 (XORconst [0] x) -> x 651 (XORconst [-1] x) -> (NORconst [0] x) 652 653 // generic constant folding 654 (ADDVconst [c] (MOVVconst [d])) -> (MOVVconst [c+d]) 655 (ADDVconst [c] (ADDVconst [d] x)) && is32Bit(c+d) -> (ADDVconst [c+d] x) 656 (ADDVconst [c] (SUBVconst [d] x)) && is32Bit(c-d) -> (ADDVconst [c-d] x) 657 (SUBVconst [c] (MOVVconst [d])) -> (MOVVconst [d-c]) 658 (SUBVconst [c] (SUBVconst [d] x)) && is32Bit(-c-d) -> (ADDVconst [-c-d] x) 659 (SUBVconst [c] (ADDVconst [d] x)) && is32Bit(-c+d) -> (ADDVconst [-c+d] x) 660 (SLLVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(d)<<uint64(c)]) 661 (SRLVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(uint64(d)>>uint64(c))]) 662 (SRAVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(d)>>uint64(c)]) 663 (Select1 (MULVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [c*d]) 664 (Select1 (DIVV (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(c)/int64(d)]) 665 (Select1 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(uint64(c)/uint64(d))]) 666 (Select0 (DIVV (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(c)%int64(d)]) // mod 667 (Select0 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(uint64(c)%uint64(d))]) // mod 668 (ANDconst [c] (MOVVconst [d])) -> (MOVVconst [c&d]) 669 (ANDconst [c] (ANDconst [d] x)) -> (ANDconst [c&d] x) 670 (ORconst [c] (MOVVconst [d])) -> (MOVVconst [c|d]) 671 (ORconst [c] (ORconst [d] x)) && is32Bit(c|d) -> (ORconst [c|d] x) 672 (XORconst [c] (MOVVconst [d])) -> (MOVVconst [c^d]) 673 (XORconst [c] (XORconst [d] x)) && is32Bit(c^d) -> (XORconst [c^d] x) 674 (NORconst [c] (MOVVconst [d])) -> (MOVVconst [^(c|d)]) 675 (NEGV (MOVVconst [c])) -> (MOVVconst [-c]) 676 (MOVBreg (MOVVconst [c])) -> (MOVVconst [int64(int8(c))]) 677 (MOVBUreg (MOVVconst [c])) -> (MOVVconst [int64(uint8(c))]) 678 (MOVHreg (MOVVconst [c])) -> (MOVVconst [int64(int16(c))]) 679 (MOVHUreg (MOVVconst [c])) -> (MOVVconst [int64(uint16(c))]) 680 (MOVWreg (MOVVconst [c])) -> (MOVVconst [int64(int32(c))]) 681 (MOVWUreg (MOVVconst [c])) -> (MOVVconst [int64(uint32(c))]) 682 (MOVVreg (MOVVconst [c])) -> (MOVVconst [c]) 683 (LoweredAtomicStore32 ptr (MOVVconst [0]) mem) -> (LoweredAtomicStorezero32 ptr mem) 684 (LoweredAtomicStore64 ptr (MOVVconst [0]) mem) -> (LoweredAtomicStorezero64 ptr mem) 685 (LoweredAtomicAdd32 ptr (MOVVconst [c]) mem) && is32Bit(c) -> (LoweredAtomicAddconst32 [c] ptr mem) 686 (LoweredAtomicAdd64 ptr (MOVVconst [c]) mem) && is32Bit(c) -> (LoweredAtomicAddconst64 [c] ptr mem) 687 688 // constant comparisons 689 (SGTconst [c] (MOVVconst [d])) && int64(c)>int64(d) -> (MOVVconst [1]) 690 (SGTconst [c] (MOVVconst [d])) && int64(c)<=int64(d) -> (MOVVconst [0]) 691 (SGTUconst [c] (MOVVconst [d])) && uint64(c)>uint64(d) -> (MOVVconst [1]) 692 (SGTUconst [c] (MOVVconst [d])) && uint64(c)<=uint64(d) -> (MOVVconst [0]) 693 694 // other known comparisons 695 (SGTconst [c] (MOVBreg _)) && 0x7f < int64(c) -> (MOVVconst [1]) 696 (SGTconst [c] (MOVBreg _)) && int64(c) <= -0x80 -> (MOVVconst [0]) 697 (SGTconst [c] (MOVBUreg _)) && 0xff < int64(c) -> (MOVVconst [1]) 698 (SGTconst [c] (MOVBUreg _)) && int64(c) < 0 -> (MOVVconst [0]) 699 (SGTUconst [c] (MOVBUreg _)) && 0xff < uint64(c) -> (MOVVconst [1]) 700 (SGTconst [c] (MOVHreg _)) && 0x7fff < int64(c) -> (MOVVconst [1]) 701 (SGTconst [c] (MOVHreg _)) && int64(c) <= -0x8000 -> (MOVVconst [0]) 702 (SGTconst [c] (MOVHUreg _)) && 0xffff < int64(c) -> (MOVVconst [1]) 703 (SGTconst [c] (MOVHUreg _)) && int64(c) < 0 -> (MOVVconst [0]) 704 (SGTUconst [c] (MOVHUreg _)) && 0xffff < uint64(c) -> (MOVVconst [1]) 705 (SGTconst [c] (MOVWUreg _)) && int64(c) < 0 -> (MOVVconst [0]) 706 (SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c -> (MOVVconst [1]) 707 (SGTUconst [c] (ANDconst [m] _)) && uint64(m) < uint64(c) -> (MOVVconst [1]) 708 (SGTconst [c] (SRLVconst _ [d])) && 0 <= c && 0 < d && d <= 63 && 1<<uint64(64-d) <= c -> (MOVVconst [1]) 709 (SGTUconst [c] (SRLVconst _ [d])) && 0 < d && d <= 63 && 1<<uint64(64-d) <= uint64(c) -> (MOVVconst [1]) 710 711 // absorb constants into branches 712 (EQ (MOVVconst [0]) yes no) -> (First nil yes no) 713 (EQ (MOVVconst [c]) yes no) && c != 0 -> (First nil no yes) 714 (NE (MOVVconst [0]) yes no) -> (First nil no yes) 715 (NE (MOVVconst [c]) yes no) && c != 0 -> (First nil yes no) 716 (LTZ (MOVVconst [c]) yes no) && c < 0 -> (First nil yes no) 717 (LTZ (MOVVconst [c]) yes no) && c >= 0 -> (First nil no yes) 718 (LEZ (MOVVconst [c]) yes no) && c <= 0 -> (First nil yes no) 719 (LEZ (MOVVconst [c]) yes no) && c > 0 -> (First nil no yes) 720 (GTZ (MOVVconst [c]) yes no) && c > 0 -> (First nil yes no) 721 (GTZ (MOVVconst [c]) yes no) && c <= 0 -> (First nil no yes) 722 (GEZ (MOVVconst [c]) yes no) && c >= 0 -> (First nil yes no) 723 (GEZ (MOVVconst [c]) yes no) && c < 0 -> (First nil no yes)