github.com/zebozhuang/go@v0.0.0-20200207033046-f8a98f6f5c5d/src/cmd/compile/internal/ssa/opGen.go (about) 1 // Code generated from gen/*Ops.go; DO NOT EDIT. 2 3 package ssa 4 5 import ( 6 "cmd/internal/obj" 7 "cmd/internal/obj/arm" 8 "cmd/internal/obj/arm64" 9 "cmd/internal/obj/mips" 10 "cmd/internal/obj/ppc64" 11 "cmd/internal/obj/s390x" 12 "cmd/internal/obj/x86" 13 ) 14 15 const ( 16 BlockInvalid BlockKind = iota 17 18 Block386EQ 19 Block386NE 20 Block386LT 21 Block386LE 22 Block386GT 23 Block386GE 24 Block386ULT 25 Block386ULE 26 Block386UGT 27 Block386UGE 28 Block386EQF 29 Block386NEF 30 Block386ORD 31 Block386NAN 32 33 BlockAMD64EQ 34 BlockAMD64NE 35 BlockAMD64LT 36 BlockAMD64LE 37 BlockAMD64GT 38 BlockAMD64GE 39 BlockAMD64ULT 40 BlockAMD64ULE 41 BlockAMD64UGT 42 BlockAMD64UGE 43 BlockAMD64EQF 44 BlockAMD64NEF 45 BlockAMD64ORD 46 BlockAMD64NAN 47 48 BlockARMEQ 49 BlockARMNE 50 BlockARMLT 51 BlockARMLE 52 BlockARMGT 53 BlockARMGE 54 BlockARMULT 55 BlockARMULE 56 BlockARMUGT 57 BlockARMUGE 58 59 BlockARM64EQ 60 BlockARM64NE 61 BlockARM64LT 62 BlockARM64LE 63 BlockARM64GT 64 BlockARM64GE 65 BlockARM64ULT 66 BlockARM64ULE 67 BlockARM64UGT 68 BlockARM64UGE 69 BlockARM64Z 70 BlockARM64NZ 71 BlockARM64ZW 72 BlockARM64NZW 73 74 BlockMIPSEQ 75 BlockMIPSNE 76 BlockMIPSLTZ 77 BlockMIPSLEZ 78 BlockMIPSGTZ 79 BlockMIPSGEZ 80 BlockMIPSFPT 81 BlockMIPSFPF 82 83 BlockMIPS64EQ 84 BlockMIPS64NE 85 BlockMIPS64LTZ 86 BlockMIPS64LEZ 87 BlockMIPS64GTZ 88 BlockMIPS64GEZ 89 BlockMIPS64FPT 90 BlockMIPS64FPF 91 92 BlockPPC64EQ 93 BlockPPC64NE 94 BlockPPC64LT 95 BlockPPC64LE 96 BlockPPC64GT 97 BlockPPC64GE 98 BlockPPC64FLT 99 BlockPPC64FLE 100 BlockPPC64FGT 101 BlockPPC64FGE 102 103 BlockS390XEQ 104 BlockS390XNE 105 BlockS390XLT 106 BlockS390XLE 107 BlockS390XGT 108 BlockS390XGE 109 BlockS390XGTF 110 BlockS390XGEF 111 112 BlockPlain 113 BlockIf 114 BlockDefer 115 BlockRet 116 BlockRetJmp 117 BlockExit 118 BlockFirst 119 ) 120 121 var blockString = [...]string{ 122 BlockInvalid: "BlockInvalid", 123 124 Block386EQ: "EQ", 125 Block386NE: "NE", 126 Block386LT: "LT", 127 Block386LE: "LE", 128 Block386GT: "GT", 129 Block386GE: "GE", 130 Block386ULT: "ULT", 131 Block386ULE: "ULE", 132 Block386UGT: "UGT", 133 Block386UGE: "UGE", 134 Block386EQF: "EQF", 135 Block386NEF: "NEF", 136 Block386ORD: "ORD", 137 Block386NAN: "NAN", 138 139 BlockAMD64EQ: "EQ", 140 BlockAMD64NE: "NE", 141 BlockAMD64LT: "LT", 142 BlockAMD64LE: "LE", 143 BlockAMD64GT: "GT", 144 BlockAMD64GE: "GE", 145 BlockAMD64ULT: "ULT", 146 BlockAMD64ULE: "ULE", 147 BlockAMD64UGT: "UGT", 148 BlockAMD64UGE: "UGE", 149 BlockAMD64EQF: "EQF", 150 BlockAMD64NEF: "NEF", 151 BlockAMD64ORD: "ORD", 152 BlockAMD64NAN: "NAN", 153 154 BlockARMEQ: "EQ", 155 BlockARMNE: "NE", 156 BlockARMLT: "LT", 157 BlockARMLE: "LE", 158 BlockARMGT: "GT", 159 BlockARMGE: "GE", 160 BlockARMULT: "ULT", 161 BlockARMULE: "ULE", 162 BlockARMUGT: "UGT", 163 BlockARMUGE: "UGE", 164 165 BlockARM64EQ: "EQ", 166 BlockARM64NE: "NE", 167 BlockARM64LT: "LT", 168 BlockARM64LE: "LE", 169 BlockARM64GT: "GT", 170 BlockARM64GE: "GE", 171 BlockARM64ULT: "ULT", 172 BlockARM64ULE: "ULE", 173 BlockARM64UGT: "UGT", 174 BlockARM64UGE: "UGE", 175 BlockARM64Z: "Z", 176 BlockARM64NZ: "NZ", 177 BlockARM64ZW: "ZW", 178 BlockARM64NZW: "NZW", 179 180 BlockMIPSEQ: "EQ", 181 BlockMIPSNE: "NE", 182 BlockMIPSLTZ: "LTZ", 183 BlockMIPSLEZ: "LEZ", 184 BlockMIPSGTZ: "GTZ", 185 BlockMIPSGEZ: "GEZ", 186 BlockMIPSFPT: "FPT", 187 BlockMIPSFPF: "FPF", 188 189 BlockMIPS64EQ: "EQ", 190 BlockMIPS64NE: "NE", 191 BlockMIPS64LTZ: "LTZ", 192 BlockMIPS64LEZ: "LEZ", 193 BlockMIPS64GTZ: "GTZ", 194 BlockMIPS64GEZ: "GEZ", 195 BlockMIPS64FPT: "FPT", 196 BlockMIPS64FPF: "FPF", 197 198 BlockPPC64EQ: "EQ", 199 BlockPPC64NE: "NE", 200 BlockPPC64LT: "LT", 201 BlockPPC64LE: "LE", 202 BlockPPC64GT: "GT", 203 BlockPPC64GE: "GE", 204 BlockPPC64FLT: "FLT", 205 BlockPPC64FLE: "FLE", 206 BlockPPC64FGT: "FGT", 207 BlockPPC64FGE: "FGE", 208 209 BlockS390XEQ: "EQ", 210 BlockS390XNE: "NE", 211 BlockS390XLT: "LT", 212 BlockS390XLE: "LE", 213 BlockS390XGT: "GT", 214 BlockS390XGE: "GE", 215 BlockS390XGTF: "GTF", 216 BlockS390XGEF: "GEF", 217 218 BlockPlain: "Plain", 219 BlockIf: "If", 220 BlockDefer: "Defer", 221 BlockRet: "Ret", 222 BlockRetJmp: "RetJmp", 223 BlockExit: "Exit", 224 BlockFirst: "First", 225 } 226 227 func (k BlockKind) String() string { return blockString[k] } 228 229 const ( 230 OpInvalid Op = iota 231 232 Op386ADDSS 233 Op386ADDSD 234 Op386SUBSS 235 Op386SUBSD 236 Op386MULSS 237 Op386MULSD 238 Op386DIVSS 239 Op386DIVSD 240 Op386MOVSSload 241 Op386MOVSDload 242 Op386MOVSSconst 243 Op386MOVSDconst 244 Op386MOVSSloadidx1 245 Op386MOVSSloadidx4 246 Op386MOVSDloadidx1 247 Op386MOVSDloadidx8 248 Op386MOVSSstore 249 Op386MOVSDstore 250 Op386MOVSSstoreidx1 251 Op386MOVSSstoreidx4 252 Op386MOVSDstoreidx1 253 Op386MOVSDstoreidx8 254 Op386ADDL 255 Op386ADDLconst 256 Op386ADDLcarry 257 Op386ADDLconstcarry 258 Op386ADCL 259 Op386ADCLconst 260 Op386SUBL 261 Op386SUBLconst 262 Op386SUBLcarry 263 Op386SUBLconstcarry 264 Op386SBBL 265 Op386SBBLconst 266 Op386MULL 267 Op386MULLconst 268 Op386HMULL 269 Op386HMULLU 270 Op386MULLQU 271 Op386AVGLU 272 Op386DIVL 273 Op386DIVW 274 Op386DIVLU 275 Op386DIVWU 276 Op386MODL 277 Op386MODW 278 Op386MODLU 279 Op386MODWU 280 Op386ANDL 281 Op386ANDLconst 282 Op386ORL 283 Op386ORLconst 284 Op386XORL 285 Op386XORLconst 286 Op386CMPL 287 Op386CMPW 288 Op386CMPB 289 Op386CMPLconst 290 Op386CMPWconst 291 Op386CMPBconst 292 Op386UCOMISS 293 Op386UCOMISD 294 Op386TESTL 295 Op386TESTW 296 Op386TESTB 297 Op386TESTLconst 298 Op386TESTWconst 299 Op386TESTBconst 300 Op386SHLL 301 Op386SHLLconst 302 Op386SHRL 303 Op386SHRW 304 Op386SHRB 305 Op386SHRLconst 306 Op386SHRWconst 307 Op386SHRBconst 308 Op386SARL 309 Op386SARW 310 Op386SARB 311 Op386SARLconst 312 Op386SARWconst 313 Op386SARBconst 314 Op386ROLLconst 315 Op386ROLWconst 316 Op386ROLBconst 317 Op386NEGL 318 Op386NOTL 319 Op386BSFL 320 Op386BSFW 321 Op386BSRL 322 Op386BSRW 323 Op386BSWAPL 324 Op386SQRTSD 325 Op386SBBLcarrymask 326 Op386SETEQ 327 Op386SETNE 328 Op386SETL 329 Op386SETLE 330 Op386SETG 331 Op386SETGE 332 Op386SETB 333 Op386SETBE 334 Op386SETA 335 Op386SETAE 336 Op386SETEQF 337 Op386SETNEF 338 Op386SETORD 339 Op386SETNAN 340 Op386SETGF 341 Op386SETGEF 342 Op386MOVBLSX 343 Op386MOVBLZX 344 Op386MOVWLSX 345 Op386MOVWLZX 346 Op386MOVLconst 347 Op386CVTTSD2SL 348 Op386CVTTSS2SL 349 Op386CVTSL2SS 350 Op386CVTSL2SD 351 Op386CVTSD2SS 352 Op386CVTSS2SD 353 Op386PXOR 354 Op386LEAL 355 Op386LEAL1 356 Op386LEAL2 357 Op386LEAL4 358 Op386LEAL8 359 Op386MOVBload 360 Op386MOVBLSXload 361 Op386MOVWload 362 Op386MOVWLSXload 363 Op386MOVLload 364 Op386MOVBstore 365 Op386MOVWstore 366 Op386MOVLstore 367 Op386MOVBloadidx1 368 Op386MOVWloadidx1 369 Op386MOVWloadidx2 370 Op386MOVLloadidx1 371 Op386MOVLloadidx4 372 Op386MOVBstoreidx1 373 Op386MOVWstoreidx1 374 Op386MOVWstoreidx2 375 Op386MOVLstoreidx1 376 Op386MOVLstoreidx4 377 Op386MOVBstoreconst 378 Op386MOVWstoreconst 379 Op386MOVLstoreconst 380 Op386MOVBstoreconstidx1 381 Op386MOVWstoreconstidx1 382 Op386MOVWstoreconstidx2 383 Op386MOVLstoreconstidx1 384 Op386MOVLstoreconstidx4 385 Op386DUFFZERO 386 Op386REPSTOSL 387 Op386CALLstatic 388 Op386CALLclosure 389 Op386CALLinter 390 Op386DUFFCOPY 391 Op386REPMOVSL 392 Op386InvertFlags 393 Op386LoweredGetG 394 Op386LoweredGetClosurePtr 395 Op386LoweredNilCheck 396 Op386MOVLconvert 397 Op386FlagEQ 398 Op386FlagLT_ULT 399 Op386FlagLT_UGT 400 Op386FlagGT_UGT 401 Op386FlagGT_ULT 402 Op386FCHS 403 Op386MOVSSconst1 404 Op386MOVSDconst1 405 Op386MOVSSconst2 406 Op386MOVSDconst2 407 408 OpAMD64ADDSS 409 OpAMD64ADDSD 410 OpAMD64SUBSS 411 OpAMD64SUBSD 412 OpAMD64MULSS 413 OpAMD64MULSD 414 OpAMD64DIVSS 415 OpAMD64DIVSD 416 OpAMD64MOVSSload 417 OpAMD64MOVSDload 418 OpAMD64MOVSSconst 419 OpAMD64MOVSDconst 420 OpAMD64MOVSSloadidx1 421 OpAMD64MOVSSloadidx4 422 OpAMD64MOVSDloadidx1 423 OpAMD64MOVSDloadidx8 424 OpAMD64MOVSSstore 425 OpAMD64MOVSDstore 426 OpAMD64MOVSSstoreidx1 427 OpAMD64MOVSSstoreidx4 428 OpAMD64MOVSDstoreidx1 429 OpAMD64MOVSDstoreidx8 430 OpAMD64ADDSDmem 431 OpAMD64ADDSSmem 432 OpAMD64SUBSSmem 433 OpAMD64SUBSDmem 434 OpAMD64MULSSmem 435 OpAMD64MULSDmem 436 OpAMD64ADDQ 437 OpAMD64ADDL 438 OpAMD64ADDQconst 439 OpAMD64ADDLconst 440 OpAMD64SUBQ 441 OpAMD64SUBL 442 OpAMD64SUBQconst 443 OpAMD64SUBLconst 444 OpAMD64MULQ 445 OpAMD64MULL 446 OpAMD64MULQconst 447 OpAMD64MULLconst 448 OpAMD64HMULQ 449 OpAMD64HMULL 450 OpAMD64HMULQU 451 OpAMD64HMULLU 452 OpAMD64AVGQU 453 OpAMD64DIVQ 454 OpAMD64DIVL 455 OpAMD64DIVW 456 OpAMD64DIVQU 457 OpAMD64DIVLU 458 OpAMD64DIVWU 459 OpAMD64MULQU2 460 OpAMD64DIVQU2 461 OpAMD64ANDQ 462 OpAMD64ANDL 463 OpAMD64ANDQconst 464 OpAMD64ANDLconst 465 OpAMD64ORQ 466 OpAMD64ORL 467 OpAMD64ORQconst 468 OpAMD64ORLconst 469 OpAMD64XORQ 470 OpAMD64XORL 471 OpAMD64XORQconst 472 OpAMD64XORLconst 473 OpAMD64CMPQ 474 OpAMD64CMPL 475 OpAMD64CMPW 476 OpAMD64CMPB 477 OpAMD64CMPQconst 478 OpAMD64CMPLconst 479 OpAMD64CMPWconst 480 OpAMD64CMPBconst 481 OpAMD64UCOMISS 482 OpAMD64UCOMISD 483 OpAMD64BTL 484 OpAMD64BTQ 485 OpAMD64BTLconst 486 OpAMD64BTQconst 487 OpAMD64TESTQ 488 OpAMD64TESTL 489 OpAMD64TESTW 490 OpAMD64TESTB 491 OpAMD64TESTQconst 492 OpAMD64TESTLconst 493 OpAMD64TESTWconst 494 OpAMD64TESTBconst 495 OpAMD64SHLQ 496 OpAMD64SHLL 497 OpAMD64SHLQconst 498 OpAMD64SHLLconst 499 OpAMD64SHRQ 500 OpAMD64SHRL 501 OpAMD64SHRW 502 OpAMD64SHRB 503 OpAMD64SHRQconst 504 OpAMD64SHRLconst 505 OpAMD64SHRWconst 506 OpAMD64SHRBconst 507 OpAMD64SARQ 508 OpAMD64SARL 509 OpAMD64SARW 510 OpAMD64SARB 511 OpAMD64SARQconst 512 OpAMD64SARLconst 513 OpAMD64SARWconst 514 OpAMD64SARBconst 515 OpAMD64ROLQ 516 OpAMD64ROLL 517 OpAMD64ROLW 518 OpAMD64ROLB 519 OpAMD64RORQ 520 OpAMD64RORL 521 OpAMD64RORW 522 OpAMD64RORB 523 OpAMD64ROLQconst 524 OpAMD64ROLLconst 525 OpAMD64ROLWconst 526 OpAMD64ROLBconst 527 OpAMD64ADDLmem 528 OpAMD64ADDQmem 529 OpAMD64SUBQmem 530 OpAMD64SUBLmem 531 OpAMD64ANDLmem 532 OpAMD64ANDQmem 533 OpAMD64ORQmem 534 OpAMD64ORLmem 535 OpAMD64XORQmem 536 OpAMD64XORLmem 537 OpAMD64NEGQ 538 OpAMD64NEGL 539 OpAMD64NOTQ 540 OpAMD64NOTL 541 OpAMD64BSFQ 542 OpAMD64BSFL 543 OpAMD64BSRQ 544 OpAMD64BSRL 545 OpAMD64CMOVQEQ 546 OpAMD64CMOVLEQ 547 OpAMD64BSWAPQ 548 OpAMD64BSWAPL 549 OpAMD64POPCNTQ 550 OpAMD64POPCNTL 551 OpAMD64SQRTSD 552 OpAMD64SBBQcarrymask 553 OpAMD64SBBLcarrymask 554 OpAMD64SETEQ 555 OpAMD64SETNE 556 OpAMD64SETL 557 OpAMD64SETLE 558 OpAMD64SETG 559 OpAMD64SETGE 560 OpAMD64SETB 561 OpAMD64SETBE 562 OpAMD64SETA 563 OpAMD64SETAE 564 OpAMD64SETEQF 565 OpAMD64SETNEF 566 OpAMD64SETORD 567 OpAMD64SETNAN 568 OpAMD64SETGF 569 OpAMD64SETGEF 570 OpAMD64MOVBQSX 571 OpAMD64MOVBQZX 572 OpAMD64MOVWQSX 573 OpAMD64MOVWQZX 574 OpAMD64MOVLQSX 575 OpAMD64MOVLQZX 576 OpAMD64MOVLconst 577 OpAMD64MOVQconst 578 OpAMD64CVTTSD2SL 579 OpAMD64CVTTSD2SQ 580 OpAMD64CVTTSS2SL 581 OpAMD64CVTTSS2SQ 582 OpAMD64CVTSL2SS 583 OpAMD64CVTSL2SD 584 OpAMD64CVTSQ2SS 585 OpAMD64CVTSQ2SD 586 OpAMD64CVTSD2SS 587 OpAMD64CVTSS2SD 588 OpAMD64PXOR 589 OpAMD64LEAQ 590 OpAMD64LEAQ1 591 OpAMD64LEAQ2 592 OpAMD64LEAQ4 593 OpAMD64LEAQ8 594 OpAMD64LEAL 595 OpAMD64MOVBload 596 OpAMD64MOVBQSXload 597 OpAMD64MOVWload 598 OpAMD64MOVWQSXload 599 OpAMD64MOVLload 600 OpAMD64MOVLQSXload 601 OpAMD64MOVQload 602 OpAMD64MOVBstore 603 OpAMD64MOVWstore 604 OpAMD64MOVLstore 605 OpAMD64MOVQstore 606 OpAMD64MOVOload 607 OpAMD64MOVOstore 608 OpAMD64MOVBloadidx1 609 OpAMD64MOVWloadidx1 610 OpAMD64MOVWloadidx2 611 OpAMD64MOVLloadidx1 612 OpAMD64MOVLloadidx4 613 OpAMD64MOVQloadidx1 614 OpAMD64MOVQloadidx8 615 OpAMD64MOVBstoreidx1 616 OpAMD64MOVWstoreidx1 617 OpAMD64MOVWstoreidx2 618 OpAMD64MOVLstoreidx1 619 OpAMD64MOVLstoreidx4 620 OpAMD64MOVQstoreidx1 621 OpAMD64MOVQstoreidx8 622 OpAMD64MOVBstoreconst 623 OpAMD64MOVWstoreconst 624 OpAMD64MOVLstoreconst 625 OpAMD64MOVQstoreconst 626 OpAMD64MOVBstoreconstidx1 627 OpAMD64MOVWstoreconstidx1 628 OpAMD64MOVWstoreconstidx2 629 OpAMD64MOVLstoreconstidx1 630 OpAMD64MOVLstoreconstidx4 631 OpAMD64MOVQstoreconstidx1 632 OpAMD64MOVQstoreconstidx8 633 OpAMD64DUFFZERO 634 OpAMD64MOVOconst 635 OpAMD64REPSTOSQ 636 OpAMD64CALLstatic 637 OpAMD64CALLclosure 638 OpAMD64CALLinter 639 OpAMD64DUFFCOPY 640 OpAMD64REPMOVSQ 641 OpAMD64InvertFlags 642 OpAMD64LoweredGetG 643 OpAMD64LoweredGetClosurePtr 644 OpAMD64LoweredNilCheck 645 OpAMD64MOVQconvert 646 OpAMD64MOVLconvert 647 OpAMD64FlagEQ 648 OpAMD64FlagLT_ULT 649 OpAMD64FlagLT_UGT 650 OpAMD64FlagGT_UGT 651 OpAMD64FlagGT_ULT 652 OpAMD64MOVLatomicload 653 OpAMD64MOVQatomicload 654 OpAMD64XCHGL 655 OpAMD64XCHGQ 656 OpAMD64XADDLlock 657 OpAMD64XADDQlock 658 OpAMD64AddTupleFirst32 659 OpAMD64AddTupleFirst64 660 OpAMD64CMPXCHGLlock 661 OpAMD64CMPXCHGQlock 662 OpAMD64ANDBlock 663 OpAMD64ORBlock 664 665 OpARMADD 666 OpARMADDconst 667 OpARMSUB 668 OpARMSUBconst 669 OpARMRSB 670 OpARMRSBconst 671 OpARMMUL 672 OpARMHMUL 673 OpARMHMULU 674 OpARMCALLudiv 675 OpARMADDS 676 OpARMADDSconst 677 OpARMADC 678 OpARMADCconst 679 OpARMSUBS 680 OpARMSUBSconst 681 OpARMRSBSconst 682 OpARMSBC 683 OpARMSBCconst 684 OpARMRSCconst 685 OpARMMULLU 686 OpARMMULA 687 OpARMADDF 688 OpARMADDD 689 OpARMSUBF 690 OpARMSUBD 691 OpARMMULF 692 OpARMMULD 693 OpARMDIVF 694 OpARMDIVD 695 OpARMAND 696 OpARMANDconst 697 OpARMOR 698 OpARMORconst 699 OpARMXOR 700 OpARMXORconst 701 OpARMBIC 702 OpARMBICconst 703 OpARMMVN 704 OpARMNEGF 705 OpARMNEGD 706 OpARMSQRTD 707 OpARMCLZ 708 OpARMREV 709 OpARMRBIT 710 OpARMSLL 711 OpARMSLLconst 712 OpARMSRL 713 OpARMSRLconst 714 OpARMSRA 715 OpARMSRAconst 716 OpARMSRRconst 717 OpARMADDshiftLL 718 OpARMADDshiftRL 719 OpARMADDshiftRA 720 OpARMSUBshiftLL 721 OpARMSUBshiftRL 722 OpARMSUBshiftRA 723 OpARMRSBshiftLL 724 OpARMRSBshiftRL 725 OpARMRSBshiftRA 726 OpARMANDshiftLL 727 OpARMANDshiftRL 728 OpARMANDshiftRA 729 OpARMORshiftLL 730 OpARMORshiftRL 731 OpARMORshiftRA 732 OpARMXORshiftLL 733 OpARMXORshiftRL 734 OpARMXORshiftRA 735 OpARMXORshiftRR 736 OpARMBICshiftLL 737 OpARMBICshiftRL 738 OpARMBICshiftRA 739 OpARMMVNshiftLL 740 OpARMMVNshiftRL 741 OpARMMVNshiftRA 742 OpARMADCshiftLL 743 OpARMADCshiftRL 744 OpARMADCshiftRA 745 OpARMSBCshiftLL 746 OpARMSBCshiftRL 747 OpARMSBCshiftRA 748 OpARMRSCshiftLL 749 OpARMRSCshiftRL 750 OpARMRSCshiftRA 751 OpARMADDSshiftLL 752 OpARMADDSshiftRL 753 OpARMADDSshiftRA 754 OpARMSUBSshiftLL 755 OpARMSUBSshiftRL 756 OpARMSUBSshiftRA 757 OpARMRSBSshiftLL 758 OpARMRSBSshiftRL 759 OpARMRSBSshiftRA 760 OpARMADDshiftLLreg 761 OpARMADDshiftRLreg 762 OpARMADDshiftRAreg 763 OpARMSUBshiftLLreg 764 OpARMSUBshiftRLreg 765 OpARMSUBshiftRAreg 766 OpARMRSBshiftLLreg 767 OpARMRSBshiftRLreg 768 OpARMRSBshiftRAreg 769 OpARMANDshiftLLreg 770 OpARMANDshiftRLreg 771 OpARMANDshiftRAreg 772 OpARMORshiftLLreg 773 OpARMORshiftRLreg 774 OpARMORshiftRAreg 775 OpARMXORshiftLLreg 776 OpARMXORshiftRLreg 777 OpARMXORshiftRAreg 778 OpARMBICshiftLLreg 779 OpARMBICshiftRLreg 780 OpARMBICshiftRAreg 781 OpARMMVNshiftLLreg 782 OpARMMVNshiftRLreg 783 OpARMMVNshiftRAreg 784 OpARMADCshiftLLreg 785 OpARMADCshiftRLreg 786 OpARMADCshiftRAreg 787 OpARMSBCshiftLLreg 788 OpARMSBCshiftRLreg 789 OpARMSBCshiftRAreg 790 OpARMRSCshiftLLreg 791 OpARMRSCshiftRLreg 792 OpARMRSCshiftRAreg 793 OpARMADDSshiftLLreg 794 OpARMADDSshiftRLreg 795 OpARMADDSshiftRAreg 796 OpARMSUBSshiftLLreg 797 OpARMSUBSshiftRLreg 798 OpARMSUBSshiftRAreg 799 OpARMRSBSshiftLLreg 800 OpARMRSBSshiftRLreg 801 OpARMRSBSshiftRAreg 802 OpARMCMP 803 OpARMCMPconst 804 OpARMCMN 805 OpARMCMNconst 806 OpARMTST 807 OpARMTSTconst 808 OpARMTEQ 809 OpARMTEQconst 810 OpARMCMPF 811 OpARMCMPD 812 OpARMCMPshiftLL 813 OpARMCMPshiftRL 814 OpARMCMPshiftRA 815 OpARMCMPshiftLLreg 816 OpARMCMPshiftRLreg 817 OpARMCMPshiftRAreg 818 OpARMCMPF0 819 OpARMCMPD0 820 OpARMMOVWconst 821 OpARMMOVFconst 822 OpARMMOVDconst 823 OpARMMOVWaddr 824 OpARMMOVBload 825 OpARMMOVBUload 826 OpARMMOVHload 827 OpARMMOVHUload 828 OpARMMOVWload 829 OpARMMOVFload 830 OpARMMOVDload 831 OpARMMOVBstore 832 OpARMMOVHstore 833 OpARMMOVWstore 834 OpARMMOVFstore 835 OpARMMOVDstore 836 OpARMMOVWloadidx 837 OpARMMOVWloadshiftLL 838 OpARMMOVWloadshiftRL 839 OpARMMOVWloadshiftRA 840 OpARMMOVWstoreidx 841 OpARMMOVWstoreshiftLL 842 OpARMMOVWstoreshiftRL 843 OpARMMOVWstoreshiftRA 844 OpARMMOVBreg 845 OpARMMOVBUreg 846 OpARMMOVHreg 847 OpARMMOVHUreg 848 OpARMMOVWreg 849 OpARMMOVWnop 850 OpARMMOVWF 851 OpARMMOVWD 852 OpARMMOVWUF 853 OpARMMOVWUD 854 OpARMMOVFW 855 OpARMMOVDW 856 OpARMMOVFWU 857 OpARMMOVDWU 858 OpARMMOVFD 859 OpARMMOVDF 860 OpARMCMOVWHSconst 861 OpARMCMOVWLSconst 862 OpARMSRAcond 863 OpARMCALLstatic 864 OpARMCALLclosure 865 OpARMCALLinter 866 OpARMLoweredNilCheck 867 OpARMEqual 868 OpARMNotEqual 869 OpARMLessThan 870 OpARMLessEqual 871 OpARMGreaterThan 872 OpARMGreaterEqual 873 OpARMLessThanU 874 OpARMLessEqualU 875 OpARMGreaterThanU 876 OpARMGreaterEqualU 877 OpARMDUFFZERO 878 OpARMDUFFCOPY 879 OpARMLoweredZero 880 OpARMLoweredMove 881 OpARMLoweredGetClosurePtr 882 OpARMMOVWconvert 883 OpARMFlagEQ 884 OpARMFlagLT_ULT 885 OpARMFlagLT_UGT 886 OpARMFlagGT_UGT 887 OpARMFlagGT_ULT 888 OpARMInvertFlags 889 890 OpARM64ADD 891 OpARM64ADDconst 892 OpARM64SUB 893 OpARM64SUBconst 894 OpARM64MUL 895 OpARM64MULW 896 OpARM64MULH 897 OpARM64UMULH 898 OpARM64MULL 899 OpARM64UMULL 900 OpARM64DIV 901 OpARM64UDIV 902 OpARM64DIVW 903 OpARM64UDIVW 904 OpARM64MOD 905 OpARM64UMOD 906 OpARM64MODW 907 OpARM64UMODW 908 OpARM64FADDS 909 OpARM64FADDD 910 OpARM64FSUBS 911 OpARM64FSUBD 912 OpARM64FMULS 913 OpARM64FMULD 914 OpARM64FDIVS 915 OpARM64FDIVD 916 OpARM64AND 917 OpARM64ANDconst 918 OpARM64OR 919 OpARM64ORconst 920 OpARM64XOR 921 OpARM64XORconst 922 OpARM64BIC 923 OpARM64BICconst 924 OpARM64MVN 925 OpARM64NEG 926 OpARM64FNEGS 927 OpARM64FNEGD 928 OpARM64FSQRTD 929 OpARM64REV 930 OpARM64REVW 931 OpARM64REV16W 932 OpARM64RBIT 933 OpARM64RBITW 934 OpARM64CLZ 935 OpARM64CLZW 936 OpARM64SLL 937 OpARM64SLLconst 938 OpARM64SRL 939 OpARM64SRLconst 940 OpARM64SRA 941 OpARM64SRAconst 942 OpARM64RORconst 943 OpARM64RORWconst 944 OpARM64CMP 945 OpARM64CMPconst 946 OpARM64CMPW 947 OpARM64CMPWconst 948 OpARM64CMN 949 OpARM64CMNconst 950 OpARM64CMNW 951 OpARM64CMNWconst 952 OpARM64FCMPS 953 OpARM64FCMPD 954 OpARM64ADDshiftLL 955 OpARM64ADDshiftRL 956 OpARM64ADDshiftRA 957 OpARM64SUBshiftLL 958 OpARM64SUBshiftRL 959 OpARM64SUBshiftRA 960 OpARM64ANDshiftLL 961 OpARM64ANDshiftRL 962 OpARM64ANDshiftRA 963 OpARM64ORshiftLL 964 OpARM64ORshiftRL 965 OpARM64ORshiftRA 966 OpARM64XORshiftLL 967 OpARM64XORshiftRL 968 OpARM64XORshiftRA 969 OpARM64BICshiftLL 970 OpARM64BICshiftRL 971 OpARM64BICshiftRA 972 OpARM64CMPshiftLL 973 OpARM64CMPshiftRL 974 OpARM64CMPshiftRA 975 OpARM64MOVDconst 976 OpARM64FMOVSconst 977 OpARM64FMOVDconst 978 OpARM64MOVDaddr 979 OpARM64MOVBload 980 OpARM64MOVBUload 981 OpARM64MOVHload 982 OpARM64MOVHUload 983 OpARM64MOVWload 984 OpARM64MOVWUload 985 OpARM64MOVDload 986 OpARM64FMOVSload 987 OpARM64FMOVDload 988 OpARM64MOVBstore 989 OpARM64MOVHstore 990 OpARM64MOVWstore 991 OpARM64MOVDstore 992 OpARM64FMOVSstore 993 OpARM64FMOVDstore 994 OpARM64MOVBstorezero 995 OpARM64MOVHstorezero 996 OpARM64MOVWstorezero 997 OpARM64MOVDstorezero 998 OpARM64MOVBreg 999 OpARM64MOVBUreg 1000 OpARM64MOVHreg 1001 OpARM64MOVHUreg 1002 OpARM64MOVWreg 1003 OpARM64MOVWUreg 1004 OpARM64MOVDreg 1005 OpARM64MOVDnop 1006 OpARM64SCVTFWS 1007 OpARM64SCVTFWD 1008 OpARM64UCVTFWS 1009 OpARM64UCVTFWD 1010 OpARM64SCVTFS 1011 OpARM64SCVTFD 1012 OpARM64UCVTFS 1013 OpARM64UCVTFD 1014 OpARM64FCVTZSSW 1015 OpARM64FCVTZSDW 1016 OpARM64FCVTZUSW 1017 OpARM64FCVTZUDW 1018 OpARM64FCVTZSS 1019 OpARM64FCVTZSD 1020 OpARM64FCVTZUS 1021 OpARM64FCVTZUD 1022 OpARM64FCVTSD 1023 OpARM64FCVTDS 1024 OpARM64CSELULT 1025 OpARM64CSELULT0 1026 OpARM64CALLstatic 1027 OpARM64CALLclosure 1028 OpARM64CALLinter 1029 OpARM64LoweredNilCheck 1030 OpARM64Equal 1031 OpARM64NotEqual 1032 OpARM64LessThan 1033 OpARM64LessEqual 1034 OpARM64GreaterThan 1035 OpARM64GreaterEqual 1036 OpARM64LessThanU 1037 OpARM64LessEqualU 1038 OpARM64GreaterThanU 1039 OpARM64GreaterEqualU 1040 OpARM64DUFFZERO 1041 OpARM64LoweredZero 1042 OpARM64DUFFCOPY 1043 OpARM64LoweredMove 1044 OpARM64LoweredGetClosurePtr 1045 OpARM64MOVDconvert 1046 OpARM64FlagEQ 1047 OpARM64FlagLT_ULT 1048 OpARM64FlagLT_UGT 1049 OpARM64FlagGT_UGT 1050 OpARM64FlagGT_ULT 1051 OpARM64InvertFlags 1052 OpARM64LDAR 1053 OpARM64LDARW 1054 OpARM64STLR 1055 OpARM64STLRW 1056 OpARM64LoweredAtomicExchange64 1057 OpARM64LoweredAtomicExchange32 1058 OpARM64LoweredAtomicAdd64 1059 OpARM64LoweredAtomicAdd32 1060 OpARM64LoweredAtomicCas64 1061 OpARM64LoweredAtomicCas32 1062 OpARM64LoweredAtomicAnd8 1063 OpARM64LoweredAtomicOr8 1064 1065 OpMIPSADD 1066 OpMIPSADDconst 1067 OpMIPSSUB 1068 OpMIPSSUBconst 1069 OpMIPSMUL 1070 OpMIPSMULT 1071 OpMIPSMULTU 1072 OpMIPSDIV 1073 OpMIPSDIVU 1074 OpMIPSADDF 1075 OpMIPSADDD 1076 OpMIPSSUBF 1077 OpMIPSSUBD 1078 OpMIPSMULF 1079 OpMIPSMULD 1080 OpMIPSDIVF 1081 OpMIPSDIVD 1082 OpMIPSAND 1083 OpMIPSANDconst 1084 OpMIPSOR 1085 OpMIPSORconst 1086 OpMIPSXOR 1087 OpMIPSXORconst 1088 OpMIPSNOR 1089 OpMIPSNORconst 1090 OpMIPSNEG 1091 OpMIPSNEGF 1092 OpMIPSNEGD 1093 OpMIPSSQRTD 1094 OpMIPSSLL 1095 OpMIPSSLLconst 1096 OpMIPSSRL 1097 OpMIPSSRLconst 1098 OpMIPSSRA 1099 OpMIPSSRAconst 1100 OpMIPSCLZ 1101 OpMIPSSGT 1102 OpMIPSSGTconst 1103 OpMIPSSGTzero 1104 OpMIPSSGTU 1105 OpMIPSSGTUconst 1106 OpMIPSSGTUzero 1107 OpMIPSCMPEQF 1108 OpMIPSCMPEQD 1109 OpMIPSCMPGEF 1110 OpMIPSCMPGED 1111 OpMIPSCMPGTF 1112 OpMIPSCMPGTD 1113 OpMIPSMOVWconst 1114 OpMIPSMOVFconst 1115 OpMIPSMOVDconst 1116 OpMIPSMOVWaddr 1117 OpMIPSMOVBload 1118 OpMIPSMOVBUload 1119 OpMIPSMOVHload 1120 OpMIPSMOVHUload 1121 OpMIPSMOVWload 1122 OpMIPSMOVFload 1123 OpMIPSMOVDload 1124 OpMIPSMOVBstore 1125 OpMIPSMOVHstore 1126 OpMIPSMOVWstore 1127 OpMIPSMOVFstore 1128 OpMIPSMOVDstore 1129 OpMIPSMOVBstorezero 1130 OpMIPSMOVHstorezero 1131 OpMIPSMOVWstorezero 1132 OpMIPSMOVBreg 1133 OpMIPSMOVBUreg 1134 OpMIPSMOVHreg 1135 OpMIPSMOVHUreg 1136 OpMIPSMOVWreg 1137 OpMIPSMOVWnop 1138 OpMIPSCMOVZ 1139 OpMIPSCMOVZzero 1140 OpMIPSMOVWF 1141 OpMIPSMOVWD 1142 OpMIPSTRUNCFW 1143 OpMIPSTRUNCDW 1144 OpMIPSMOVFD 1145 OpMIPSMOVDF 1146 OpMIPSCALLstatic 1147 OpMIPSCALLclosure 1148 OpMIPSCALLinter 1149 OpMIPSLoweredAtomicLoad 1150 OpMIPSLoweredAtomicStore 1151 OpMIPSLoweredAtomicStorezero 1152 OpMIPSLoweredAtomicExchange 1153 OpMIPSLoweredAtomicAdd 1154 OpMIPSLoweredAtomicAddconst 1155 OpMIPSLoweredAtomicCas 1156 OpMIPSLoweredAtomicAnd 1157 OpMIPSLoweredAtomicOr 1158 OpMIPSLoweredZero 1159 OpMIPSLoweredMove 1160 OpMIPSLoweredNilCheck 1161 OpMIPSFPFlagTrue 1162 OpMIPSFPFlagFalse 1163 OpMIPSLoweredGetClosurePtr 1164 OpMIPSMOVWconvert 1165 1166 OpMIPS64ADDV 1167 OpMIPS64ADDVconst 1168 OpMIPS64SUBV 1169 OpMIPS64SUBVconst 1170 OpMIPS64MULV 1171 OpMIPS64MULVU 1172 OpMIPS64DIVV 1173 OpMIPS64DIVVU 1174 OpMIPS64ADDF 1175 OpMIPS64ADDD 1176 OpMIPS64SUBF 1177 OpMIPS64SUBD 1178 OpMIPS64MULF 1179 OpMIPS64MULD 1180 OpMIPS64DIVF 1181 OpMIPS64DIVD 1182 OpMIPS64AND 1183 OpMIPS64ANDconst 1184 OpMIPS64OR 1185 OpMIPS64ORconst 1186 OpMIPS64XOR 1187 OpMIPS64XORconst 1188 OpMIPS64NOR 1189 OpMIPS64NORconst 1190 OpMIPS64NEGV 1191 OpMIPS64NEGF 1192 OpMIPS64NEGD 1193 OpMIPS64SLLV 1194 OpMIPS64SLLVconst 1195 OpMIPS64SRLV 1196 OpMIPS64SRLVconst 1197 OpMIPS64SRAV 1198 OpMIPS64SRAVconst 1199 OpMIPS64SGT 1200 OpMIPS64SGTconst 1201 OpMIPS64SGTU 1202 OpMIPS64SGTUconst 1203 OpMIPS64CMPEQF 1204 OpMIPS64CMPEQD 1205 OpMIPS64CMPGEF 1206 OpMIPS64CMPGED 1207 OpMIPS64CMPGTF 1208 OpMIPS64CMPGTD 1209 OpMIPS64MOVVconst 1210 OpMIPS64MOVFconst 1211 OpMIPS64MOVDconst 1212 OpMIPS64MOVVaddr 1213 OpMIPS64MOVBload 1214 OpMIPS64MOVBUload 1215 OpMIPS64MOVHload 1216 OpMIPS64MOVHUload 1217 OpMIPS64MOVWload 1218 OpMIPS64MOVWUload 1219 OpMIPS64MOVVload 1220 OpMIPS64MOVFload 1221 OpMIPS64MOVDload 1222 OpMIPS64MOVBstore 1223 OpMIPS64MOVHstore 1224 OpMIPS64MOVWstore 1225 OpMIPS64MOVVstore 1226 OpMIPS64MOVFstore 1227 OpMIPS64MOVDstore 1228 OpMIPS64MOVBstorezero 1229 OpMIPS64MOVHstorezero 1230 OpMIPS64MOVWstorezero 1231 OpMIPS64MOVVstorezero 1232 OpMIPS64MOVBreg 1233 OpMIPS64MOVBUreg 1234 OpMIPS64MOVHreg 1235 OpMIPS64MOVHUreg 1236 OpMIPS64MOVWreg 1237 OpMIPS64MOVWUreg 1238 OpMIPS64MOVVreg 1239 OpMIPS64MOVVnop 1240 OpMIPS64MOVWF 1241 OpMIPS64MOVWD 1242 OpMIPS64MOVVF 1243 OpMIPS64MOVVD 1244 OpMIPS64TRUNCFW 1245 OpMIPS64TRUNCDW 1246 OpMIPS64TRUNCFV 1247 OpMIPS64TRUNCDV 1248 OpMIPS64MOVFD 1249 OpMIPS64MOVDF 1250 OpMIPS64CALLstatic 1251 OpMIPS64CALLclosure 1252 OpMIPS64CALLinter 1253 OpMIPS64DUFFZERO 1254 OpMIPS64LoweredZero 1255 OpMIPS64LoweredMove 1256 OpMIPS64LoweredNilCheck 1257 OpMIPS64FPFlagTrue 1258 OpMIPS64FPFlagFalse 1259 OpMIPS64LoweredGetClosurePtr 1260 OpMIPS64MOVVconvert 1261 1262 OpPPC64ADD 1263 OpPPC64ADDconst 1264 OpPPC64FADD 1265 OpPPC64FADDS 1266 OpPPC64SUB 1267 OpPPC64FSUB 1268 OpPPC64FSUBS 1269 OpPPC64MULLD 1270 OpPPC64MULLW 1271 OpPPC64MULHD 1272 OpPPC64MULHW 1273 OpPPC64MULHDU 1274 OpPPC64MULHWU 1275 OpPPC64FMUL 1276 OpPPC64FMULS 1277 OpPPC64FMADD 1278 OpPPC64FMADDS 1279 OpPPC64FMSUB 1280 OpPPC64FMSUBS 1281 OpPPC64SRAD 1282 OpPPC64SRAW 1283 OpPPC64SRD 1284 OpPPC64SRW 1285 OpPPC64SLD 1286 OpPPC64SLW 1287 OpPPC64ADDconstForCarry 1288 OpPPC64MaskIfNotCarry 1289 OpPPC64SRADconst 1290 OpPPC64SRAWconst 1291 OpPPC64SRDconst 1292 OpPPC64SRWconst 1293 OpPPC64SLDconst 1294 OpPPC64SLWconst 1295 OpPPC64ROTLconst 1296 OpPPC64ROTLWconst 1297 OpPPC64CNTLZD 1298 OpPPC64CNTLZW 1299 OpPPC64POPCNTD 1300 OpPPC64POPCNTW 1301 OpPPC64POPCNTB 1302 OpPPC64FDIV 1303 OpPPC64FDIVS 1304 OpPPC64DIVD 1305 OpPPC64DIVW 1306 OpPPC64DIVDU 1307 OpPPC64DIVWU 1308 OpPPC64FCTIDZ 1309 OpPPC64FCTIWZ 1310 OpPPC64FCFID 1311 OpPPC64FRSP 1312 OpPPC64Xf2i64 1313 OpPPC64Xi2f64 1314 OpPPC64AND 1315 OpPPC64ANDN 1316 OpPPC64OR 1317 OpPPC64ORN 1318 OpPPC64NOR 1319 OpPPC64XOR 1320 OpPPC64EQV 1321 OpPPC64NEG 1322 OpPPC64FNEG 1323 OpPPC64FSQRT 1324 OpPPC64FSQRTS 1325 OpPPC64ORconst 1326 OpPPC64XORconst 1327 OpPPC64ANDconst 1328 OpPPC64ANDCCconst 1329 OpPPC64MOVBreg 1330 OpPPC64MOVBZreg 1331 OpPPC64MOVHreg 1332 OpPPC64MOVHZreg 1333 OpPPC64MOVWreg 1334 OpPPC64MOVWZreg 1335 OpPPC64MOVBZload 1336 OpPPC64MOVHload 1337 OpPPC64MOVHZload 1338 OpPPC64MOVWload 1339 OpPPC64MOVWZload 1340 OpPPC64MOVDload 1341 OpPPC64FMOVDload 1342 OpPPC64FMOVSload 1343 OpPPC64MOVBstore 1344 OpPPC64MOVHstore 1345 OpPPC64MOVWstore 1346 OpPPC64MOVDstore 1347 OpPPC64FMOVDstore 1348 OpPPC64FMOVSstore 1349 OpPPC64MOVBstorezero 1350 OpPPC64MOVHstorezero 1351 OpPPC64MOVWstorezero 1352 OpPPC64MOVDstorezero 1353 OpPPC64MOVDaddr 1354 OpPPC64MOVDconst 1355 OpPPC64FMOVDconst 1356 OpPPC64FMOVSconst 1357 OpPPC64FCMPU 1358 OpPPC64CMP 1359 OpPPC64CMPU 1360 OpPPC64CMPW 1361 OpPPC64CMPWU 1362 OpPPC64CMPconst 1363 OpPPC64CMPUconst 1364 OpPPC64CMPWconst 1365 OpPPC64CMPWUconst 1366 OpPPC64Equal 1367 OpPPC64NotEqual 1368 OpPPC64LessThan 1369 OpPPC64FLessThan 1370 OpPPC64LessEqual 1371 OpPPC64FLessEqual 1372 OpPPC64GreaterThan 1373 OpPPC64FGreaterThan 1374 OpPPC64GreaterEqual 1375 OpPPC64FGreaterEqual 1376 OpPPC64LoweredGetClosurePtr 1377 OpPPC64LoweredNilCheck 1378 OpPPC64LoweredRound32F 1379 OpPPC64LoweredRound64F 1380 OpPPC64MOVDconvert 1381 OpPPC64CALLstatic 1382 OpPPC64CALLclosure 1383 OpPPC64CALLinter 1384 OpPPC64LoweredZero 1385 OpPPC64LoweredMove 1386 OpPPC64LoweredAtomicStore32 1387 OpPPC64LoweredAtomicStore64 1388 OpPPC64LoweredAtomicLoad32 1389 OpPPC64LoweredAtomicLoad64 1390 OpPPC64LoweredAtomicLoadPtr 1391 OpPPC64LoweredAtomicAdd32 1392 OpPPC64LoweredAtomicAdd64 1393 OpPPC64LoweredAtomicExchange32 1394 OpPPC64LoweredAtomicExchange64 1395 OpPPC64LoweredAtomicCas64 1396 OpPPC64LoweredAtomicCas32 1397 OpPPC64LoweredAtomicAnd8 1398 OpPPC64LoweredAtomicOr8 1399 OpPPC64InvertFlags 1400 OpPPC64FlagEQ 1401 OpPPC64FlagLT 1402 OpPPC64FlagGT 1403 1404 OpS390XFADDS 1405 OpS390XFADD 1406 OpS390XFSUBS 1407 OpS390XFSUB 1408 OpS390XFMULS 1409 OpS390XFMUL 1410 OpS390XFDIVS 1411 OpS390XFDIV 1412 OpS390XFNEGS 1413 OpS390XFNEG 1414 OpS390XFMADDS 1415 OpS390XFMADD 1416 OpS390XFMSUBS 1417 OpS390XFMSUB 1418 OpS390XFMOVSload 1419 OpS390XFMOVDload 1420 OpS390XFMOVSconst 1421 OpS390XFMOVDconst 1422 OpS390XFMOVSloadidx 1423 OpS390XFMOVDloadidx 1424 OpS390XFMOVSstore 1425 OpS390XFMOVDstore 1426 OpS390XFMOVSstoreidx 1427 OpS390XFMOVDstoreidx 1428 OpS390XADD 1429 OpS390XADDW 1430 OpS390XADDconst 1431 OpS390XADDWconst 1432 OpS390XADDload 1433 OpS390XADDWload 1434 OpS390XSUB 1435 OpS390XSUBW 1436 OpS390XSUBconst 1437 OpS390XSUBWconst 1438 OpS390XSUBload 1439 OpS390XSUBWload 1440 OpS390XMULLD 1441 OpS390XMULLW 1442 OpS390XMULLDconst 1443 OpS390XMULLWconst 1444 OpS390XMULLDload 1445 OpS390XMULLWload 1446 OpS390XMULHD 1447 OpS390XMULHDU 1448 OpS390XDIVD 1449 OpS390XDIVW 1450 OpS390XDIVDU 1451 OpS390XDIVWU 1452 OpS390XMODD 1453 OpS390XMODW 1454 OpS390XMODDU 1455 OpS390XMODWU 1456 OpS390XAND 1457 OpS390XANDW 1458 OpS390XANDconst 1459 OpS390XANDWconst 1460 OpS390XANDload 1461 OpS390XANDWload 1462 OpS390XOR 1463 OpS390XORW 1464 OpS390XORconst 1465 OpS390XORWconst 1466 OpS390XORload 1467 OpS390XORWload 1468 OpS390XXOR 1469 OpS390XXORW 1470 OpS390XXORconst 1471 OpS390XXORWconst 1472 OpS390XXORload 1473 OpS390XXORWload 1474 OpS390XCMP 1475 OpS390XCMPW 1476 OpS390XCMPU 1477 OpS390XCMPWU 1478 OpS390XCMPconst 1479 OpS390XCMPWconst 1480 OpS390XCMPUconst 1481 OpS390XCMPWUconst 1482 OpS390XFCMPS 1483 OpS390XFCMP 1484 OpS390XSLD 1485 OpS390XSLW 1486 OpS390XSLDconst 1487 OpS390XSLWconst 1488 OpS390XSRD 1489 OpS390XSRW 1490 OpS390XSRDconst 1491 OpS390XSRWconst 1492 OpS390XSRAD 1493 OpS390XSRAW 1494 OpS390XSRADconst 1495 OpS390XSRAWconst 1496 OpS390XRLLGconst 1497 OpS390XRLLconst 1498 OpS390XNEG 1499 OpS390XNEGW 1500 OpS390XNOT 1501 OpS390XNOTW 1502 OpS390XFSQRT 1503 OpS390XSUBEcarrymask 1504 OpS390XSUBEWcarrymask 1505 OpS390XMOVDEQ 1506 OpS390XMOVDNE 1507 OpS390XMOVDLT 1508 OpS390XMOVDLE 1509 OpS390XMOVDGT 1510 OpS390XMOVDGE 1511 OpS390XMOVDGTnoinv 1512 OpS390XMOVDGEnoinv 1513 OpS390XMOVBreg 1514 OpS390XMOVBZreg 1515 OpS390XMOVHreg 1516 OpS390XMOVHZreg 1517 OpS390XMOVWreg 1518 OpS390XMOVWZreg 1519 OpS390XMOVDreg 1520 OpS390XMOVDnop 1521 OpS390XMOVDconst 1522 OpS390XCFDBRA 1523 OpS390XCGDBRA 1524 OpS390XCFEBRA 1525 OpS390XCGEBRA 1526 OpS390XCEFBRA 1527 OpS390XCDFBRA 1528 OpS390XCEGBRA 1529 OpS390XCDGBRA 1530 OpS390XLEDBR 1531 OpS390XLDEBR 1532 OpS390XMOVDaddr 1533 OpS390XMOVDaddridx 1534 OpS390XMOVBZload 1535 OpS390XMOVBload 1536 OpS390XMOVHZload 1537 OpS390XMOVHload 1538 OpS390XMOVWZload 1539 OpS390XMOVWload 1540 OpS390XMOVDload 1541 OpS390XMOVWBR 1542 OpS390XMOVDBR 1543 OpS390XMOVHBRload 1544 OpS390XMOVWBRload 1545 OpS390XMOVDBRload 1546 OpS390XMOVBstore 1547 OpS390XMOVHstore 1548 OpS390XMOVWstore 1549 OpS390XMOVDstore 1550 OpS390XMOVHBRstore 1551 OpS390XMOVWBRstore 1552 OpS390XMOVDBRstore 1553 OpS390XMVC 1554 OpS390XMOVBZloadidx 1555 OpS390XMOVHZloadidx 1556 OpS390XMOVWZloadidx 1557 OpS390XMOVDloadidx 1558 OpS390XMOVHBRloadidx 1559 OpS390XMOVWBRloadidx 1560 OpS390XMOVDBRloadidx 1561 OpS390XMOVBstoreidx 1562 OpS390XMOVHstoreidx 1563 OpS390XMOVWstoreidx 1564 OpS390XMOVDstoreidx 1565 OpS390XMOVHBRstoreidx 1566 OpS390XMOVWBRstoreidx 1567 OpS390XMOVDBRstoreidx 1568 OpS390XMOVBstoreconst 1569 OpS390XMOVHstoreconst 1570 OpS390XMOVWstoreconst 1571 OpS390XMOVDstoreconst 1572 OpS390XCLEAR 1573 OpS390XCALLstatic 1574 OpS390XCALLclosure 1575 OpS390XCALLinter 1576 OpS390XInvertFlags 1577 OpS390XLoweredGetG 1578 OpS390XLoweredGetClosurePtr 1579 OpS390XLoweredNilCheck 1580 OpS390XLoweredRound32F 1581 OpS390XLoweredRound64F 1582 OpS390XMOVDconvert 1583 OpS390XFlagEQ 1584 OpS390XFlagLT 1585 OpS390XFlagGT 1586 OpS390XMOVWZatomicload 1587 OpS390XMOVDatomicload 1588 OpS390XMOVWatomicstore 1589 OpS390XMOVDatomicstore 1590 OpS390XLAA 1591 OpS390XLAAG 1592 OpS390XAddTupleFirst32 1593 OpS390XAddTupleFirst64 1594 OpS390XLoweredAtomicCas32 1595 OpS390XLoweredAtomicCas64 1596 OpS390XLoweredAtomicExchange32 1597 OpS390XLoweredAtomicExchange64 1598 OpS390XFLOGR 1599 OpS390XSTMG2 1600 OpS390XSTMG3 1601 OpS390XSTMG4 1602 OpS390XSTM2 1603 OpS390XSTM3 1604 OpS390XSTM4 1605 OpS390XLoweredMove 1606 OpS390XLoweredZero 1607 1608 OpAdd8 1609 OpAdd16 1610 OpAdd32 1611 OpAdd64 1612 OpAddPtr 1613 OpAdd32F 1614 OpAdd64F 1615 OpSub8 1616 OpSub16 1617 OpSub32 1618 OpSub64 1619 OpSubPtr 1620 OpSub32F 1621 OpSub64F 1622 OpMul8 1623 OpMul16 1624 OpMul32 1625 OpMul64 1626 OpMul32F 1627 OpMul64F 1628 OpDiv32F 1629 OpDiv64F 1630 OpHmul32 1631 OpHmul32u 1632 OpHmul64 1633 OpHmul64u 1634 OpMul32uhilo 1635 OpMul64uhilo 1636 OpAvg32u 1637 OpAvg64u 1638 OpDiv8 1639 OpDiv8u 1640 OpDiv16 1641 OpDiv16u 1642 OpDiv32 1643 OpDiv32u 1644 OpDiv64 1645 OpDiv64u 1646 OpDiv128u 1647 OpMod8 1648 OpMod8u 1649 OpMod16 1650 OpMod16u 1651 OpMod32 1652 OpMod32u 1653 OpMod64 1654 OpMod64u 1655 OpAnd8 1656 OpAnd16 1657 OpAnd32 1658 OpAnd64 1659 OpOr8 1660 OpOr16 1661 OpOr32 1662 OpOr64 1663 OpXor8 1664 OpXor16 1665 OpXor32 1666 OpXor64 1667 OpLsh8x8 1668 OpLsh8x16 1669 OpLsh8x32 1670 OpLsh8x64 1671 OpLsh16x8 1672 OpLsh16x16 1673 OpLsh16x32 1674 OpLsh16x64 1675 OpLsh32x8 1676 OpLsh32x16 1677 OpLsh32x32 1678 OpLsh32x64 1679 OpLsh64x8 1680 OpLsh64x16 1681 OpLsh64x32 1682 OpLsh64x64 1683 OpRsh8x8 1684 OpRsh8x16 1685 OpRsh8x32 1686 OpRsh8x64 1687 OpRsh16x8 1688 OpRsh16x16 1689 OpRsh16x32 1690 OpRsh16x64 1691 OpRsh32x8 1692 OpRsh32x16 1693 OpRsh32x32 1694 OpRsh32x64 1695 OpRsh64x8 1696 OpRsh64x16 1697 OpRsh64x32 1698 OpRsh64x64 1699 OpRsh8Ux8 1700 OpRsh8Ux16 1701 OpRsh8Ux32 1702 OpRsh8Ux64 1703 OpRsh16Ux8 1704 OpRsh16Ux16 1705 OpRsh16Ux32 1706 OpRsh16Ux64 1707 OpRsh32Ux8 1708 OpRsh32Ux16 1709 OpRsh32Ux32 1710 OpRsh32Ux64 1711 OpRsh64Ux8 1712 OpRsh64Ux16 1713 OpRsh64Ux32 1714 OpRsh64Ux64 1715 OpEq8 1716 OpEq16 1717 OpEq32 1718 OpEq64 1719 OpEqPtr 1720 OpEqInter 1721 OpEqSlice 1722 OpEq32F 1723 OpEq64F 1724 OpNeq8 1725 OpNeq16 1726 OpNeq32 1727 OpNeq64 1728 OpNeqPtr 1729 OpNeqInter 1730 OpNeqSlice 1731 OpNeq32F 1732 OpNeq64F 1733 OpLess8 1734 OpLess8U 1735 OpLess16 1736 OpLess16U 1737 OpLess32 1738 OpLess32U 1739 OpLess64 1740 OpLess64U 1741 OpLess32F 1742 OpLess64F 1743 OpLeq8 1744 OpLeq8U 1745 OpLeq16 1746 OpLeq16U 1747 OpLeq32 1748 OpLeq32U 1749 OpLeq64 1750 OpLeq64U 1751 OpLeq32F 1752 OpLeq64F 1753 OpGreater8 1754 OpGreater8U 1755 OpGreater16 1756 OpGreater16U 1757 OpGreater32 1758 OpGreater32U 1759 OpGreater64 1760 OpGreater64U 1761 OpGreater32F 1762 OpGreater64F 1763 OpGeq8 1764 OpGeq8U 1765 OpGeq16 1766 OpGeq16U 1767 OpGeq32 1768 OpGeq32U 1769 OpGeq64 1770 OpGeq64U 1771 OpGeq32F 1772 OpGeq64F 1773 OpAndB 1774 OpOrB 1775 OpEqB 1776 OpNeqB 1777 OpNot 1778 OpNeg8 1779 OpNeg16 1780 OpNeg32 1781 OpNeg64 1782 OpNeg32F 1783 OpNeg64F 1784 OpCom8 1785 OpCom16 1786 OpCom32 1787 OpCom64 1788 OpCtz32 1789 OpCtz64 1790 OpBitLen32 1791 OpBitLen64 1792 OpBswap32 1793 OpBswap64 1794 OpBitRev8 1795 OpBitRev16 1796 OpBitRev32 1797 OpBitRev64 1798 OpPopCount8 1799 OpPopCount16 1800 OpPopCount32 1801 OpPopCount64 1802 OpSqrt 1803 OpPhi 1804 OpCopy 1805 OpConvert 1806 OpConstBool 1807 OpConstString 1808 OpConstNil 1809 OpConst8 1810 OpConst16 1811 OpConst32 1812 OpConst64 1813 OpConst32F 1814 OpConst64F 1815 OpConstInterface 1816 OpConstSlice 1817 OpInitMem 1818 OpArg 1819 OpAddr 1820 OpSP 1821 OpSB 1822 OpLoad 1823 OpStore 1824 OpMove 1825 OpZero 1826 OpStoreWB 1827 OpMoveWB 1828 OpZeroWB 1829 OpClosureCall 1830 OpStaticCall 1831 OpInterCall 1832 OpSignExt8to16 1833 OpSignExt8to32 1834 OpSignExt8to64 1835 OpSignExt16to32 1836 OpSignExt16to64 1837 OpSignExt32to64 1838 OpZeroExt8to16 1839 OpZeroExt8to32 1840 OpZeroExt8to64 1841 OpZeroExt16to32 1842 OpZeroExt16to64 1843 OpZeroExt32to64 1844 OpTrunc16to8 1845 OpTrunc32to8 1846 OpTrunc32to16 1847 OpTrunc64to8 1848 OpTrunc64to16 1849 OpTrunc64to32 1850 OpCvt32to32F 1851 OpCvt32to64F 1852 OpCvt64to32F 1853 OpCvt64to64F 1854 OpCvt32Fto32 1855 OpCvt32Fto64 1856 OpCvt64Fto32 1857 OpCvt64Fto64 1858 OpCvt32Fto64F 1859 OpCvt64Fto32F 1860 OpRound32F 1861 OpRound64F 1862 OpIsNonNil 1863 OpIsInBounds 1864 OpIsSliceInBounds 1865 OpNilCheck 1866 OpGetG 1867 OpGetClosurePtr 1868 OpPtrIndex 1869 OpOffPtr 1870 OpSliceMake 1871 OpSlicePtr 1872 OpSliceLen 1873 OpSliceCap 1874 OpComplexMake 1875 OpComplexReal 1876 OpComplexImag 1877 OpStringMake 1878 OpStringPtr 1879 OpStringLen 1880 OpIMake 1881 OpITab 1882 OpIData 1883 OpStructMake0 1884 OpStructMake1 1885 OpStructMake2 1886 OpStructMake3 1887 OpStructMake4 1888 OpStructSelect 1889 OpArrayMake0 1890 OpArrayMake1 1891 OpArraySelect 1892 OpStoreReg 1893 OpLoadReg 1894 OpFwdRef 1895 OpUnknown 1896 OpVarDef 1897 OpVarKill 1898 OpVarLive 1899 OpKeepAlive 1900 OpInt64Make 1901 OpInt64Hi 1902 OpInt64Lo 1903 OpAdd32carry 1904 OpAdd32withcarry 1905 OpSub32carry 1906 OpSub32withcarry 1907 OpSignmask 1908 OpZeromask 1909 OpSlicemask 1910 OpCvt32Uto32F 1911 OpCvt32Uto64F 1912 OpCvt32Fto32U 1913 OpCvt64Fto32U 1914 OpCvt64Uto32F 1915 OpCvt64Uto64F 1916 OpCvt32Fto64U 1917 OpCvt64Fto64U 1918 OpSelect0 1919 OpSelect1 1920 OpAtomicLoad32 1921 OpAtomicLoad64 1922 OpAtomicLoadPtr 1923 OpAtomicStore32 1924 OpAtomicStore64 1925 OpAtomicStorePtrNoWB 1926 OpAtomicExchange32 1927 OpAtomicExchange64 1928 OpAtomicAdd32 1929 OpAtomicAdd64 1930 OpAtomicCompareAndSwap32 1931 OpAtomicCompareAndSwap64 1932 OpAtomicAnd8 1933 OpAtomicOr8 1934 OpClobber 1935 ) 1936 1937 var opcodeTable = [...]opInfo{ 1938 {name: "OpInvalid"}, 1939 1940 { 1941 name: "ADDSS", 1942 argLen: 2, 1943 commutative: true, 1944 resultInArg0: true, 1945 usesScratch: true, 1946 asm: x86.AADDSS, 1947 reg: regInfo{ 1948 inputs: []inputInfo{ 1949 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1950 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1951 }, 1952 outputs: []outputInfo{ 1953 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1954 }, 1955 }, 1956 }, 1957 { 1958 name: "ADDSD", 1959 argLen: 2, 1960 commutative: true, 1961 resultInArg0: true, 1962 asm: x86.AADDSD, 1963 reg: regInfo{ 1964 inputs: []inputInfo{ 1965 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1966 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1967 }, 1968 outputs: []outputInfo{ 1969 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1970 }, 1971 }, 1972 }, 1973 { 1974 name: "SUBSS", 1975 argLen: 2, 1976 resultInArg0: true, 1977 usesScratch: true, 1978 asm: x86.ASUBSS, 1979 reg: regInfo{ 1980 inputs: []inputInfo{ 1981 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1982 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1983 }, 1984 outputs: []outputInfo{ 1985 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1986 }, 1987 }, 1988 }, 1989 { 1990 name: "SUBSD", 1991 argLen: 2, 1992 resultInArg0: true, 1993 asm: x86.ASUBSD, 1994 reg: regInfo{ 1995 inputs: []inputInfo{ 1996 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1997 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1998 }, 1999 outputs: []outputInfo{ 2000 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2001 }, 2002 }, 2003 }, 2004 { 2005 name: "MULSS", 2006 argLen: 2, 2007 commutative: true, 2008 resultInArg0: true, 2009 usesScratch: true, 2010 asm: x86.AMULSS, 2011 reg: regInfo{ 2012 inputs: []inputInfo{ 2013 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2014 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2015 }, 2016 outputs: []outputInfo{ 2017 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2018 }, 2019 }, 2020 }, 2021 { 2022 name: "MULSD", 2023 argLen: 2, 2024 commutative: true, 2025 resultInArg0: true, 2026 asm: x86.AMULSD, 2027 reg: regInfo{ 2028 inputs: []inputInfo{ 2029 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2030 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2031 }, 2032 outputs: []outputInfo{ 2033 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2034 }, 2035 }, 2036 }, 2037 { 2038 name: "DIVSS", 2039 argLen: 2, 2040 resultInArg0: true, 2041 usesScratch: true, 2042 asm: x86.ADIVSS, 2043 reg: regInfo{ 2044 inputs: []inputInfo{ 2045 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2046 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2047 }, 2048 outputs: []outputInfo{ 2049 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2050 }, 2051 }, 2052 }, 2053 { 2054 name: "DIVSD", 2055 argLen: 2, 2056 resultInArg0: true, 2057 asm: x86.ADIVSD, 2058 reg: regInfo{ 2059 inputs: []inputInfo{ 2060 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2061 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2062 }, 2063 outputs: []outputInfo{ 2064 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2065 }, 2066 }, 2067 }, 2068 { 2069 name: "MOVSSload", 2070 auxType: auxSymOff, 2071 argLen: 2, 2072 faultOnNilArg0: true, 2073 symEffect: SymRead, 2074 asm: x86.AMOVSS, 2075 reg: regInfo{ 2076 inputs: []inputInfo{ 2077 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2078 }, 2079 outputs: []outputInfo{ 2080 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2081 }, 2082 }, 2083 }, 2084 { 2085 name: "MOVSDload", 2086 auxType: auxSymOff, 2087 argLen: 2, 2088 faultOnNilArg0: true, 2089 symEffect: SymRead, 2090 asm: x86.AMOVSD, 2091 reg: regInfo{ 2092 inputs: []inputInfo{ 2093 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2094 }, 2095 outputs: []outputInfo{ 2096 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2097 }, 2098 }, 2099 }, 2100 { 2101 name: "MOVSSconst", 2102 auxType: auxFloat32, 2103 argLen: 0, 2104 rematerializeable: true, 2105 asm: x86.AMOVSS, 2106 reg: regInfo{ 2107 outputs: []outputInfo{ 2108 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2109 }, 2110 }, 2111 }, 2112 { 2113 name: "MOVSDconst", 2114 auxType: auxFloat64, 2115 argLen: 0, 2116 rematerializeable: true, 2117 asm: x86.AMOVSD, 2118 reg: regInfo{ 2119 outputs: []outputInfo{ 2120 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2121 }, 2122 }, 2123 }, 2124 { 2125 name: "MOVSSloadidx1", 2126 auxType: auxSymOff, 2127 argLen: 3, 2128 symEffect: SymRead, 2129 asm: x86.AMOVSS, 2130 reg: regInfo{ 2131 inputs: []inputInfo{ 2132 {1, 255}, // AX CX DX BX SP BP SI DI 2133 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2134 }, 2135 outputs: []outputInfo{ 2136 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2137 }, 2138 }, 2139 }, 2140 { 2141 name: "MOVSSloadidx4", 2142 auxType: auxSymOff, 2143 argLen: 3, 2144 symEffect: SymRead, 2145 asm: x86.AMOVSS, 2146 reg: regInfo{ 2147 inputs: []inputInfo{ 2148 {1, 255}, // AX CX DX BX SP BP SI DI 2149 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2150 }, 2151 outputs: []outputInfo{ 2152 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2153 }, 2154 }, 2155 }, 2156 { 2157 name: "MOVSDloadidx1", 2158 auxType: auxSymOff, 2159 argLen: 3, 2160 symEffect: SymRead, 2161 asm: x86.AMOVSD, 2162 reg: regInfo{ 2163 inputs: []inputInfo{ 2164 {1, 255}, // AX CX DX BX SP BP SI DI 2165 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2166 }, 2167 outputs: []outputInfo{ 2168 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2169 }, 2170 }, 2171 }, 2172 { 2173 name: "MOVSDloadidx8", 2174 auxType: auxSymOff, 2175 argLen: 3, 2176 symEffect: SymRead, 2177 asm: x86.AMOVSD, 2178 reg: regInfo{ 2179 inputs: []inputInfo{ 2180 {1, 255}, // AX CX DX BX SP BP SI DI 2181 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2182 }, 2183 outputs: []outputInfo{ 2184 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2185 }, 2186 }, 2187 }, 2188 { 2189 name: "MOVSSstore", 2190 auxType: auxSymOff, 2191 argLen: 3, 2192 faultOnNilArg0: true, 2193 symEffect: SymWrite, 2194 asm: x86.AMOVSS, 2195 reg: regInfo{ 2196 inputs: []inputInfo{ 2197 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2198 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2199 }, 2200 }, 2201 }, 2202 { 2203 name: "MOVSDstore", 2204 auxType: auxSymOff, 2205 argLen: 3, 2206 faultOnNilArg0: true, 2207 symEffect: SymWrite, 2208 asm: x86.AMOVSD, 2209 reg: regInfo{ 2210 inputs: []inputInfo{ 2211 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2212 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2213 }, 2214 }, 2215 }, 2216 { 2217 name: "MOVSSstoreidx1", 2218 auxType: auxSymOff, 2219 argLen: 4, 2220 symEffect: SymWrite, 2221 asm: x86.AMOVSS, 2222 reg: regInfo{ 2223 inputs: []inputInfo{ 2224 {1, 255}, // AX CX DX BX SP BP SI DI 2225 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2226 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2227 }, 2228 }, 2229 }, 2230 { 2231 name: "MOVSSstoreidx4", 2232 auxType: auxSymOff, 2233 argLen: 4, 2234 symEffect: SymWrite, 2235 asm: x86.AMOVSS, 2236 reg: regInfo{ 2237 inputs: []inputInfo{ 2238 {1, 255}, // AX CX DX BX SP BP SI DI 2239 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2240 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2241 }, 2242 }, 2243 }, 2244 { 2245 name: "MOVSDstoreidx1", 2246 auxType: auxSymOff, 2247 argLen: 4, 2248 symEffect: SymWrite, 2249 asm: x86.AMOVSD, 2250 reg: regInfo{ 2251 inputs: []inputInfo{ 2252 {1, 255}, // AX CX DX BX SP BP SI DI 2253 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2254 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2255 }, 2256 }, 2257 }, 2258 { 2259 name: "MOVSDstoreidx8", 2260 auxType: auxSymOff, 2261 argLen: 4, 2262 symEffect: SymWrite, 2263 asm: x86.AMOVSD, 2264 reg: regInfo{ 2265 inputs: []inputInfo{ 2266 {1, 255}, // AX CX DX BX SP BP SI DI 2267 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2268 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2269 }, 2270 }, 2271 }, 2272 { 2273 name: "ADDL", 2274 argLen: 2, 2275 commutative: true, 2276 clobberFlags: true, 2277 asm: x86.AADDL, 2278 reg: regInfo{ 2279 inputs: []inputInfo{ 2280 {1, 239}, // AX CX DX BX BP SI DI 2281 {0, 255}, // AX CX DX BX SP BP SI DI 2282 }, 2283 outputs: []outputInfo{ 2284 {0, 239}, // AX CX DX BX BP SI DI 2285 }, 2286 }, 2287 }, 2288 { 2289 name: "ADDLconst", 2290 auxType: auxInt32, 2291 argLen: 1, 2292 clobberFlags: true, 2293 asm: x86.AADDL, 2294 reg: regInfo{ 2295 inputs: []inputInfo{ 2296 {0, 255}, // AX CX DX BX SP BP SI DI 2297 }, 2298 outputs: []outputInfo{ 2299 {0, 239}, // AX CX DX BX BP SI DI 2300 }, 2301 }, 2302 }, 2303 { 2304 name: "ADDLcarry", 2305 argLen: 2, 2306 commutative: true, 2307 resultInArg0: true, 2308 asm: x86.AADDL, 2309 reg: regInfo{ 2310 inputs: []inputInfo{ 2311 {0, 239}, // AX CX DX BX BP SI DI 2312 {1, 239}, // AX CX DX BX BP SI DI 2313 }, 2314 outputs: []outputInfo{ 2315 {1, 0}, 2316 {0, 239}, // AX CX DX BX BP SI DI 2317 }, 2318 }, 2319 }, 2320 { 2321 name: "ADDLconstcarry", 2322 auxType: auxInt32, 2323 argLen: 1, 2324 resultInArg0: true, 2325 asm: x86.AADDL, 2326 reg: regInfo{ 2327 inputs: []inputInfo{ 2328 {0, 239}, // AX CX DX BX BP SI DI 2329 }, 2330 outputs: []outputInfo{ 2331 {1, 0}, 2332 {0, 239}, // AX CX DX BX BP SI DI 2333 }, 2334 }, 2335 }, 2336 { 2337 name: "ADCL", 2338 argLen: 3, 2339 commutative: true, 2340 resultInArg0: true, 2341 clobberFlags: true, 2342 asm: x86.AADCL, 2343 reg: regInfo{ 2344 inputs: []inputInfo{ 2345 {0, 239}, // AX CX DX BX BP SI DI 2346 {1, 239}, // AX CX DX BX BP SI DI 2347 }, 2348 outputs: []outputInfo{ 2349 {0, 239}, // AX CX DX BX BP SI DI 2350 }, 2351 }, 2352 }, 2353 { 2354 name: "ADCLconst", 2355 auxType: auxInt32, 2356 argLen: 2, 2357 resultInArg0: true, 2358 clobberFlags: true, 2359 asm: x86.AADCL, 2360 reg: regInfo{ 2361 inputs: []inputInfo{ 2362 {0, 239}, // AX CX DX BX BP SI DI 2363 }, 2364 outputs: []outputInfo{ 2365 {0, 239}, // AX CX DX BX BP SI DI 2366 }, 2367 }, 2368 }, 2369 { 2370 name: "SUBL", 2371 argLen: 2, 2372 resultInArg0: true, 2373 clobberFlags: true, 2374 asm: x86.ASUBL, 2375 reg: regInfo{ 2376 inputs: []inputInfo{ 2377 {0, 239}, // AX CX DX BX BP SI DI 2378 {1, 239}, // AX CX DX BX BP SI DI 2379 }, 2380 outputs: []outputInfo{ 2381 {0, 239}, // AX CX DX BX BP SI DI 2382 }, 2383 }, 2384 }, 2385 { 2386 name: "SUBLconst", 2387 auxType: auxInt32, 2388 argLen: 1, 2389 resultInArg0: true, 2390 clobberFlags: true, 2391 asm: x86.ASUBL, 2392 reg: regInfo{ 2393 inputs: []inputInfo{ 2394 {0, 239}, // AX CX DX BX BP SI DI 2395 }, 2396 outputs: []outputInfo{ 2397 {0, 239}, // AX CX DX BX BP SI DI 2398 }, 2399 }, 2400 }, 2401 { 2402 name: "SUBLcarry", 2403 argLen: 2, 2404 resultInArg0: true, 2405 asm: x86.ASUBL, 2406 reg: regInfo{ 2407 inputs: []inputInfo{ 2408 {0, 239}, // AX CX DX BX BP SI DI 2409 {1, 239}, // AX CX DX BX BP SI DI 2410 }, 2411 outputs: []outputInfo{ 2412 {1, 0}, 2413 {0, 239}, // AX CX DX BX BP SI DI 2414 }, 2415 }, 2416 }, 2417 { 2418 name: "SUBLconstcarry", 2419 auxType: auxInt32, 2420 argLen: 1, 2421 resultInArg0: true, 2422 asm: x86.ASUBL, 2423 reg: regInfo{ 2424 inputs: []inputInfo{ 2425 {0, 239}, // AX CX DX BX BP SI DI 2426 }, 2427 outputs: []outputInfo{ 2428 {1, 0}, 2429 {0, 239}, // AX CX DX BX BP SI DI 2430 }, 2431 }, 2432 }, 2433 { 2434 name: "SBBL", 2435 argLen: 3, 2436 resultInArg0: true, 2437 clobberFlags: true, 2438 asm: x86.ASBBL, 2439 reg: regInfo{ 2440 inputs: []inputInfo{ 2441 {0, 239}, // AX CX DX BX BP SI DI 2442 {1, 239}, // AX CX DX BX BP SI DI 2443 }, 2444 outputs: []outputInfo{ 2445 {0, 239}, // AX CX DX BX BP SI DI 2446 }, 2447 }, 2448 }, 2449 { 2450 name: "SBBLconst", 2451 auxType: auxInt32, 2452 argLen: 2, 2453 resultInArg0: true, 2454 clobberFlags: true, 2455 asm: x86.ASBBL, 2456 reg: regInfo{ 2457 inputs: []inputInfo{ 2458 {0, 239}, // AX CX DX BX BP SI DI 2459 }, 2460 outputs: []outputInfo{ 2461 {0, 239}, // AX CX DX BX BP SI DI 2462 }, 2463 }, 2464 }, 2465 { 2466 name: "MULL", 2467 argLen: 2, 2468 commutative: true, 2469 resultInArg0: true, 2470 clobberFlags: true, 2471 asm: x86.AIMULL, 2472 reg: regInfo{ 2473 inputs: []inputInfo{ 2474 {0, 239}, // AX CX DX BX BP SI DI 2475 {1, 239}, // AX CX DX BX BP SI DI 2476 }, 2477 outputs: []outputInfo{ 2478 {0, 239}, // AX CX DX BX BP SI DI 2479 }, 2480 }, 2481 }, 2482 { 2483 name: "MULLconst", 2484 auxType: auxInt32, 2485 argLen: 1, 2486 resultInArg0: true, 2487 clobberFlags: true, 2488 asm: x86.AIMULL, 2489 reg: regInfo{ 2490 inputs: []inputInfo{ 2491 {0, 239}, // AX CX DX BX BP SI DI 2492 }, 2493 outputs: []outputInfo{ 2494 {0, 239}, // AX CX DX BX BP SI DI 2495 }, 2496 }, 2497 }, 2498 { 2499 name: "HMULL", 2500 argLen: 2, 2501 commutative: true, 2502 clobberFlags: true, 2503 asm: x86.AIMULL, 2504 reg: regInfo{ 2505 inputs: []inputInfo{ 2506 {0, 1}, // AX 2507 {1, 255}, // AX CX DX BX SP BP SI DI 2508 }, 2509 clobbers: 1, // AX 2510 outputs: []outputInfo{ 2511 {0, 4}, // DX 2512 }, 2513 }, 2514 }, 2515 { 2516 name: "HMULLU", 2517 argLen: 2, 2518 commutative: true, 2519 clobberFlags: true, 2520 asm: x86.AMULL, 2521 reg: regInfo{ 2522 inputs: []inputInfo{ 2523 {0, 1}, // AX 2524 {1, 255}, // AX CX DX BX SP BP SI DI 2525 }, 2526 clobbers: 1, // AX 2527 outputs: []outputInfo{ 2528 {0, 4}, // DX 2529 }, 2530 }, 2531 }, 2532 { 2533 name: "MULLQU", 2534 argLen: 2, 2535 commutative: true, 2536 clobberFlags: true, 2537 asm: x86.AMULL, 2538 reg: regInfo{ 2539 inputs: []inputInfo{ 2540 {0, 1}, // AX 2541 {1, 255}, // AX CX DX BX SP BP SI DI 2542 }, 2543 outputs: []outputInfo{ 2544 {0, 4}, // DX 2545 {1, 1}, // AX 2546 }, 2547 }, 2548 }, 2549 { 2550 name: "AVGLU", 2551 argLen: 2, 2552 commutative: true, 2553 resultInArg0: true, 2554 clobberFlags: true, 2555 reg: regInfo{ 2556 inputs: []inputInfo{ 2557 {0, 239}, // AX CX DX BX BP SI DI 2558 {1, 239}, // AX CX DX BX BP SI DI 2559 }, 2560 outputs: []outputInfo{ 2561 {0, 239}, // AX CX DX BX BP SI DI 2562 }, 2563 }, 2564 }, 2565 { 2566 name: "DIVL", 2567 argLen: 2, 2568 clobberFlags: true, 2569 asm: x86.AIDIVL, 2570 reg: regInfo{ 2571 inputs: []inputInfo{ 2572 {0, 1}, // AX 2573 {1, 251}, // AX CX BX SP BP SI DI 2574 }, 2575 clobbers: 4, // DX 2576 outputs: []outputInfo{ 2577 {0, 1}, // AX 2578 }, 2579 }, 2580 }, 2581 { 2582 name: "DIVW", 2583 argLen: 2, 2584 clobberFlags: true, 2585 asm: x86.AIDIVW, 2586 reg: regInfo{ 2587 inputs: []inputInfo{ 2588 {0, 1}, // AX 2589 {1, 251}, // AX CX BX SP BP SI DI 2590 }, 2591 clobbers: 4, // DX 2592 outputs: []outputInfo{ 2593 {0, 1}, // AX 2594 }, 2595 }, 2596 }, 2597 { 2598 name: "DIVLU", 2599 argLen: 2, 2600 clobberFlags: true, 2601 asm: x86.ADIVL, 2602 reg: regInfo{ 2603 inputs: []inputInfo{ 2604 {0, 1}, // AX 2605 {1, 251}, // AX CX BX SP BP SI DI 2606 }, 2607 clobbers: 4, // DX 2608 outputs: []outputInfo{ 2609 {0, 1}, // AX 2610 }, 2611 }, 2612 }, 2613 { 2614 name: "DIVWU", 2615 argLen: 2, 2616 clobberFlags: true, 2617 asm: x86.ADIVW, 2618 reg: regInfo{ 2619 inputs: []inputInfo{ 2620 {0, 1}, // AX 2621 {1, 251}, // AX CX BX SP BP SI DI 2622 }, 2623 clobbers: 4, // DX 2624 outputs: []outputInfo{ 2625 {0, 1}, // AX 2626 }, 2627 }, 2628 }, 2629 { 2630 name: "MODL", 2631 argLen: 2, 2632 clobberFlags: true, 2633 asm: x86.AIDIVL, 2634 reg: regInfo{ 2635 inputs: []inputInfo{ 2636 {0, 1}, // AX 2637 {1, 251}, // AX CX BX SP BP SI DI 2638 }, 2639 clobbers: 1, // AX 2640 outputs: []outputInfo{ 2641 {0, 4}, // DX 2642 }, 2643 }, 2644 }, 2645 { 2646 name: "MODW", 2647 argLen: 2, 2648 clobberFlags: true, 2649 asm: x86.AIDIVW, 2650 reg: regInfo{ 2651 inputs: []inputInfo{ 2652 {0, 1}, // AX 2653 {1, 251}, // AX CX BX SP BP SI DI 2654 }, 2655 clobbers: 1, // AX 2656 outputs: []outputInfo{ 2657 {0, 4}, // DX 2658 }, 2659 }, 2660 }, 2661 { 2662 name: "MODLU", 2663 argLen: 2, 2664 clobberFlags: true, 2665 asm: x86.ADIVL, 2666 reg: regInfo{ 2667 inputs: []inputInfo{ 2668 {0, 1}, // AX 2669 {1, 251}, // AX CX BX SP BP SI DI 2670 }, 2671 clobbers: 1, // AX 2672 outputs: []outputInfo{ 2673 {0, 4}, // DX 2674 }, 2675 }, 2676 }, 2677 { 2678 name: "MODWU", 2679 argLen: 2, 2680 clobberFlags: true, 2681 asm: x86.ADIVW, 2682 reg: regInfo{ 2683 inputs: []inputInfo{ 2684 {0, 1}, // AX 2685 {1, 251}, // AX CX BX SP BP SI DI 2686 }, 2687 clobbers: 1, // AX 2688 outputs: []outputInfo{ 2689 {0, 4}, // DX 2690 }, 2691 }, 2692 }, 2693 { 2694 name: "ANDL", 2695 argLen: 2, 2696 commutative: true, 2697 resultInArg0: true, 2698 clobberFlags: true, 2699 asm: x86.AANDL, 2700 reg: regInfo{ 2701 inputs: []inputInfo{ 2702 {0, 239}, // AX CX DX BX BP SI DI 2703 {1, 239}, // AX CX DX BX BP SI DI 2704 }, 2705 outputs: []outputInfo{ 2706 {0, 239}, // AX CX DX BX BP SI DI 2707 }, 2708 }, 2709 }, 2710 { 2711 name: "ANDLconst", 2712 auxType: auxInt32, 2713 argLen: 1, 2714 resultInArg0: true, 2715 clobberFlags: true, 2716 asm: x86.AANDL, 2717 reg: regInfo{ 2718 inputs: []inputInfo{ 2719 {0, 239}, // AX CX DX BX BP SI DI 2720 }, 2721 outputs: []outputInfo{ 2722 {0, 239}, // AX CX DX BX BP SI DI 2723 }, 2724 }, 2725 }, 2726 { 2727 name: "ORL", 2728 argLen: 2, 2729 commutative: true, 2730 resultInArg0: true, 2731 clobberFlags: true, 2732 asm: x86.AORL, 2733 reg: regInfo{ 2734 inputs: []inputInfo{ 2735 {0, 239}, // AX CX DX BX BP SI DI 2736 {1, 239}, // AX CX DX BX BP SI DI 2737 }, 2738 outputs: []outputInfo{ 2739 {0, 239}, // AX CX DX BX BP SI DI 2740 }, 2741 }, 2742 }, 2743 { 2744 name: "ORLconst", 2745 auxType: auxInt32, 2746 argLen: 1, 2747 resultInArg0: true, 2748 clobberFlags: true, 2749 asm: x86.AORL, 2750 reg: regInfo{ 2751 inputs: []inputInfo{ 2752 {0, 239}, // AX CX DX BX BP SI DI 2753 }, 2754 outputs: []outputInfo{ 2755 {0, 239}, // AX CX DX BX BP SI DI 2756 }, 2757 }, 2758 }, 2759 { 2760 name: "XORL", 2761 argLen: 2, 2762 commutative: true, 2763 resultInArg0: true, 2764 clobberFlags: true, 2765 asm: x86.AXORL, 2766 reg: regInfo{ 2767 inputs: []inputInfo{ 2768 {0, 239}, // AX CX DX BX BP SI DI 2769 {1, 239}, // AX CX DX BX BP SI DI 2770 }, 2771 outputs: []outputInfo{ 2772 {0, 239}, // AX CX DX BX BP SI DI 2773 }, 2774 }, 2775 }, 2776 { 2777 name: "XORLconst", 2778 auxType: auxInt32, 2779 argLen: 1, 2780 resultInArg0: true, 2781 clobberFlags: true, 2782 asm: x86.AXORL, 2783 reg: regInfo{ 2784 inputs: []inputInfo{ 2785 {0, 239}, // AX CX DX BX BP SI DI 2786 }, 2787 outputs: []outputInfo{ 2788 {0, 239}, // AX CX DX BX BP SI DI 2789 }, 2790 }, 2791 }, 2792 { 2793 name: "CMPL", 2794 argLen: 2, 2795 asm: x86.ACMPL, 2796 reg: regInfo{ 2797 inputs: []inputInfo{ 2798 {0, 255}, // AX CX DX BX SP BP SI DI 2799 {1, 255}, // AX CX DX BX SP BP SI DI 2800 }, 2801 }, 2802 }, 2803 { 2804 name: "CMPW", 2805 argLen: 2, 2806 asm: x86.ACMPW, 2807 reg: regInfo{ 2808 inputs: []inputInfo{ 2809 {0, 255}, // AX CX DX BX SP BP SI DI 2810 {1, 255}, // AX CX DX BX SP BP SI DI 2811 }, 2812 }, 2813 }, 2814 { 2815 name: "CMPB", 2816 argLen: 2, 2817 asm: x86.ACMPB, 2818 reg: regInfo{ 2819 inputs: []inputInfo{ 2820 {0, 255}, // AX CX DX BX SP BP SI DI 2821 {1, 255}, // AX CX DX BX SP BP SI DI 2822 }, 2823 }, 2824 }, 2825 { 2826 name: "CMPLconst", 2827 auxType: auxInt32, 2828 argLen: 1, 2829 asm: x86.ACMPL, 2830 reg: regInfo{ 2831 inputs: []inputInfo{ 2832 {0, 255}, // AX CX DX BX SP BP SI DI 2833 }, 2834 }, 2835 }, 2836 { 2837 name: "CMPWconst", 2838 auxType: auxInt16, 2839 argLen: 1, 2840 asm: x86.ACMPW, 2841 reg: regInfo{ 2842 inputs: []inputInfo{ 2843 {0, 255}, // AX CX DX BX SP BP SI DI 2844 }, 2845 }, 2846 }, 2847 { 2848 name: "CMPBconst", 2849 auxType: auxInt8, 2850 argLen: 1, 2851 asm: x86.ACMPB, 2852 reg: regInfo{ 2853 inputs: []inputInfo{ 2854 {0, 255}, // AX CX DX BX SP BP SI DI 2855 }, 2856 }, 2857 }, 2858 { 2859 name: "UCOMISS", 2860 argLen: 2, 2861 usesScratch: true, 2862 asm: x86.AUCOMISS, 2863 reg: regInfo{ 2864 inputs: []inputInfo{ 2865 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2866 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2867 }, 2868 }, 2869 }, 2870 { 2871 name: "UCOMISD", 2872 argLen: 2, 2873 usesScratch: true, 2874 asm: x86.AUCOMISD, 2875 reg: regInfo{ 2876 inputs: []inputInfo{ 2877 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2878 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2879 }, 2880 }, 2881 }, 2882 { 2883 name: "TESTL", 2884 argLen: 2, 2885 commutative: true, 2886 asm: x86.ATESTL, 2887 reg: regInfo{ 2888 inputs: []inputInfo{ 2889 {0, 255}, // AX CX DX BX SP BP SI DI 2890 {1, 255}, // AX CX DX BX SP BP SI DI 2891 }, 2892 }, 2893 }, 2894 { 2895 name: "TESTW", 2896 argLen: 2, 2897 commutative: true, 2898 asm: x86.ATESTW, 2899 reg: regInfo{ 2900 inputs: []inputInfo{ 2901 {0, 255}, // AX CX DX BX SP BP SI DI 2902 {1, 255}, // AX CX DX BX SP BP SI DI 2903 }, 2904 }, 2905 }, 2906 { 2907 name: "TESTB", 2908 argLen: 2, 2909 commutative: true, 2910 asm: x86.ATESTB, 2911 reg: regInfo{ 2912 inputs: []inputInfo{ 2913 {0, 255}, // AX CX DX BX SP BP SI DI 2914 {1, 255}, // AX CX DX BX SP BP SI DI 2915 }, 2916 }, 2917 }, 2918 { 2919 name: "TESTLconst", 2920 auxType: auxInt32, 2921 argLen: 1, 2922 asm: x86.ATESTL, 2923 reg: regInfo{ 2924 inputs: []inputInfo{ 2925 {0, 255}, // AX CX DX BX SP BP SI DI 2926 }, 2927 }, 2928 }, 2929 { 2930 name: "TESTWconst", 2931 auxType: auxInt16, 2932 argLen: 1, 2933 asm: x86.ATESTW, 2934 reg: regInfo{ 2935 inputs: []inputInfo{ 2936 {0, 255}, // AX CX DX BX SP BP SI DI 2937 }, 2938 }, 2939 }, 2940 { 2941 name: "TESTBconst", 2942 auxType: auxInt8, 2943 argLen: 1, 2944 asm: x86.ATESTB, 2945 reg: regInfo{ 2946 inputs: []inputInfo{ 2947 {0, 255}, // AX CX DX BX SP BP SI DI 2948 }, 2949 }, 2950 }, 2951 { 2952 name: "SHLL", 2953 argLen: 2, 2954 resultInArg0: true, 2955 clobberFlags: true, 2956 asm: x86.ASHLL, 2957 reg: regInfo{ 2958 inputs: []inputInfo{ 2959 {1, 2}, // CX 2960 {0, 239}, // AX CX DX BX BP SI DI 2961 }, 2962 outputs: []outputInfo{ 2963 {0, 239}, // AX CX DX BX BP SI DI 2964 }, 2965 }, 2966 }, 2967 { 2968 name: "SHLLconst", 2969 auxType: auxInt32, 2970 argLen: 1, 2971 resultInArg0: true, 2972 clobberFlags: true, 2973 asm: x86.ASHLL, 2974 reg: regInfo{ 2975 inputs: []inputInfo{ 2976 {0, 239}, // AX CX DX BX BP SI DI 2977 }, 2978 outputs: []outputInfo{ 2979 {0, 239}, // AX CX DX BX BP SI DI 2980 }, 2981 }, 2982 }, 2983 { 2984 name: "SHRL", 2985 argLen: 2, 2986 resultInArg0: true, 2987 clobberFlags: true, 2988 asm: x86.ASHRL, 2989 reg: regInfo{ 2990 inputs: []inputInfo{ 2991 {1, 2}, // CX 2992 {0, 239}, // AX CX DX BX BP SI DI 2993 }, 2994 outputs: []outputInfo{ 2995 {0, 239}, // AX CX DX BX BP SI DI 2996 }, 2997 }, 2998 }, 2999 { 3000 name: "SHRW", 3001 argLen: 2, 3002 resultInArg0: true, 3003 clobberFlags: true, 3004 asm: x86.ASHRW, 3005 reg: regInfo{ 3006 inputs: []inputInfo{ 3007 {1, 2}, // CX 3008 {0, 239}, // AX CX DX BX BP SI DI 3009 }, 3010 outputs: []outputInfo{ 3011 {0, 239}, // AX CX DX BX BP SI DI 3012 }, 3013 }, 3014 }, 3015 { 3016 name: "SHRB", 3017 argLen: 2, 3018 resultInArg0: true, 3019 clobberFlags: true, 3020 asm: x86.ASHRB, 3021 reg: regInfo{ 3022 inputs: []inputInfo{ 3023 {1, 2}, // CX 3024 {0, 239}, // AX CX DX BX BP SI DI 3025 }, 3026 outputs: []outputInfo{ 3027 {0, 239}, // AX CX DX BX BP SI DI 3028 }, 3029 }, 3030 }, 3031 { 3032 name: "SHRLconst", 3033 auxType: auxInt32, 3034 argLen: 1, 3035 resultInArg0: true, 3036 clobberFlags: true, 3037 asm: x86.ASHRL, 3038 reg: regInfo{ 3039 inputs: []inputInfo{ 3040 {0, 239}, // AX CX DX BX BP SI DI 3041 }, 3042 outputs: []outputInfo{ 3043 {0, 239}, // AX CX DX BX BP SI DI 3044 }, 3045 }, 3046 }, 3047 { 3048 name: "SHRWconst", 3049 auxType: auxInt16, 3050 argLen: 1, 3051 resultInArg0: true, 3052 clobberFlags: true, 3053 asm: x86.ASHRW, 3054 reg: regInfo{ 3055 inputs: []inputInfo{ 3056 {0, 239}, // AX CX DX BX BP SI DI 3057 }, 3058 outputs: []outputInfo{ 3059 {0, 239}, // AX CX DX BX BP SI DI 3060 }, 3061 }, 3062 }, 3063 { 3064 name: "SHRBconst", 3065 auxType: auxInt8, 3066 argLen: 1, 3067 resultInArg0: true, 3068 clobberFlags: true, 3069 asm: x86.ASHRB, 3070 reg: regInfo{ 3071 inputs: []inputInfo{ 3072 {0, 239}, // AX CX DX BX BP SI DI 3073 }, 3074 outputs: []outputInfo{ 3075 {0, 239}, // AX CX DX BX BP SI DI 3076 }, 3077 }, 3078 }, 3079 { 3080 name: "SARL", 3081 argLen: 2, 3082 resultInArg0: true, 3083 clobberFlags: true, 3084 asm: x86.ASARL, 3085 reg: regInfo{ 3086 inputs: []inputInfo{ 3087 {1, 2}, // CX 3088 {0, 239}, // AX CX DX BX BP SI DI 3089 }, 3090 outputs: []outputInfo{ 3091 {0, 239}, // AX CX DX BX BP SI DI 3092 }, 3093 }, 3094 }, 3095 { 3096 name: "SARW", 3097 argLen: 2, 3098 resultInArg0: true, 3099 clobberFlags: true, 3100 asm: x86.ASARW, 3101 reg: regInfo{ 3102 inputs: []inputInfo{ 3103 {1, 2}, // CX 3104 {0, 239}, // AX CX DX BX BP SI DI 3105 }, 3106 outputs: []outputInfo{ 3107 {0, 239}, // AX CX DX BX BP SI DI 3108 }, 3109 }, 3110 }, 3111 { 3112 name: "SARB", 3113 argLen: 2, 3114 resultInArg0: true, 3115 clobberFlags: true, 3116 asm: x86.ASARB, 3117 reg: regInfo{ 3118 inputs: []inputInfo{ 3119 {1, 2}, // CX 3120 {0, 239}, // AX CX DX BX BP SI DI 3121 }, 3122 outputs: []outputInfo{ 3123 {0, 239}, // AX CX DX BX BP SI DI 3124 }, 3125 }, 3126 }, 3127 { 3128 name: "SARLconst", 3129 auxType: auxInt32, 3130 argLen: 1, 3131 resultInArg0: true, 3132 clobberFlags: true, 3133 asm: x86.ASARL, 3134 reg: regInfo{ 3135 inputs: []inputInfo{ 3136 {0, 239}, // AX CX DX BX BP SI DI 3137 }, 3138 outputs: []outputInfo{ 3139 {0, 239}, // AX CX DX BX BP SI DI 3140 }, 3141 }, 3142 }, 3143 { 3144 name: "SARWconst", 3145 auxType: auxInt16, 3146 argLen: 1, 3147 resultInArg0: true, 3148 clobberFlags: true, 3149 asm: x86.ASARW, 3150 reg: regInfo{ 3151 inputs: []inputInfo{ 3152 {0, 239}, // AX CX DX BX BP SI DI 3153 }, 3154 outputs: []outputInfo{ 3155 {0, 239}, // AX CX DX BX BP SI DI 3156 }, 3157 }, 3158 }, 3159 { 3160 name: "SARBconst", 3161 auxType: auxInt8, 3162 argLen: 1, 3163 resultInArg0: true, 3164 clobberFlags: true, 3165 asm: x86.ASARB, 3166 reg: regInfo{ 3167 inputs: []inputInfo{ 3168 {0, 239}, // AX CX DX BX BP SI DI 3169 }, 3170 outputs: []outputInfo{ 3171 {0, 239}, // AX CX DX BX BP SI DI 3172 }, 3173 }, 3174 }, 3175 { 3176 name: "ROLLconst", 3177 auxType: auxInt32, 3178 argLen: 1, 3179 resultInArg0: true, 3180 clobberFlags: true, 3181 asm: x86.AROLL, 3182 reg: regInfo{ 3183 inputs: []inputInfo{ 3184 {0, 239}, // AX CX DX BX BP SI DI 3185 }, 3186 outputs: []outputInfo{ 3187 {0, 239}, // AX CX DX BX BP SI DI 3188 }, 3189 }, 3190 }, 3191 { 3192 name: "ROLWconst", 3193 auxType: auxInt16, 3194 argLen: 1, 3195 resultInArg0: true, 3196 clobberFlags: true, 3197 asm: x86.AROLW, 3198 reg: regInfo{ 3199 inputs: []inputInfo{ 3200 {0, 239}, // AX CX DX BX BP SI DI 3201 }, 3202 outputs: []outputInfo{ 3203 {0, 239}, // AX CX DX BX BP SI DI 3204 }, 3205 }, 3206 }, 3207 { 3208 name: "ROLBconst", 3209 auxType: auxInt8, 3210 argLen: 1, 3211 resultInArg0: true, 3212 clobberFlags: true, 3213 asm: x86.AROLB, 3214 reg: regInfo{ 3215 inputs: []inputInfo{ 3216 {0, 239}, // AX CX DX BX BP SI DI 3217 }, 3218 outputs: []outputInfo{ 3219 {0, 239}, // AX CX DX BX BP SI DI 3220 }, 3221 }, 3222 }, 3223 { 3224 name: "NEGL", 3225 argLen: 1, 3226 resultInArg0: true, 3227 clobberFlags: true, 3228 asm: x86.ANEGL, 3229 reg: regInfo{ 3230 inputs: []inputInfo{ 3231 {0, 239}, // AX CX DX BX BP SI DI 3232 }, 3233 outputs: []outputInfo{ 3234 {0, 239}, // AX CX DX BX BP SI DI 3235 }, 3236 }, 3237 }, 3238 { 3239 name: "NOTL", 3240 argLen: 1, 3241 resultInArg0: true, 3242 clobberFlags: true, 3243 asm: x86.ANOTL, 3244 reg: regInfo{ 3245 inputs: []inputInfo{ 3246 {0, 239}, // AX CX DX BX BP SI DI 3247 }, 3248 outputs: []outputInfo{ 3249 {0, 239}, // AX CX DX BX BP SI DI 3250 }, 3251 }, 3252 }, 3253 { 3254 name: "BSFL", 3255 argLen: 1, 3256 clobberFlags: true, 3257 asm: x86.ABSFL, 3258 reg: regInfo{ 3259 inputs: []inputInfo{ 3260 {0, 239}, // AX CX DX BX BP SI DI 3261 }, 3262 outputs: []outputInfo{ 3263 {0, 239}, // AX CX DX BX BP SI DI 3264 }, 3265 }, 3266 }, 3267 { 3268 name: "BSFW", 3269 argLen: 1, 3270 clobberFlags: true, 3271 asm: x86.ABSFW, 3272 reg: regInfo{ 3273 inputs: []inputInfo{ 3274 {0, 239}, // AX CX DX BX BP SI DI 3275 }, 3276 outputs: []outputInfo{ 3277 {0, 239}, // AX CX DX BX BP SI DI 3278 }, 3279 }, 3280 }, 3281 { 3282 name: "BSRL", 3283 argLen: 1, 3284 clobberFlags: true, 3285 asm: x86.ABSRL, 3286 reg: regInfo{ 3287 inputs: []inputInfo{ 3288 {0, 239}, // AX CX DX BX BP SI DI 3289 }, 3290 outputs: []outputInfo{ 3291 {0, 239}, // AX CX DX BX BP SI DI 3292 }, 3293 }, 3294 }, 3295 { 3296 name: "BSRW", 3297 argLen: 1, 3298 clobberFlags: true, 3299 asm: x86.ABSRW, 3300 reg: regInfo{ 3301 inputs: []inputInfo{ 3302 {0, 239}, // AX CX DX BX BP SI DI 3303 }, 3304 outputs: []outputInfo{ 3305 {0, 239}, // AX CX DX BX BP SI DI 3306 }, 3307 }, 3308 }, 3309 { 3310 name: "BSWAPL", 3311 argLen: 1, 3312 resultInArg0: true, 3313 clobberFlags: true, 3314 asm: x86.ABSWAPL, 3315 reg: regInfo{ 3316 inputs: []inputInfo{ 3317 {0, 239}, // AX CX DX BX BP SI DI 3318 }, 3319 outputs: []outputInfo{ 3320 {0, 239}, // AX CX DX BX BP SI DI 3321 }, 3322 }, 3323 }, 3324 { 3325 name: "SQRTSD", 3326 argLen: 1, 3327 asm: x86.ASQRTSD, 3328 reg: regInfo{ 3329 inputs: []inputInfo{ 3330 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3331 }, 3332 outputs: []outputInfo{ 3333 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3334 }, 3335 }, 3336 }, 3337 { 3338 name: "SBBLcarrymask", 3339 argLen: 1, 3340 asm: x86.ASBBL, 3341 reg: regInfo{ 3342 outputs: []outputInfo{ 3343 {0, 239}, // AX CX DX BX BP SI DI 3344 }, 3345 }, 3346 }, 3347 { 3348 name: "SETEQ", 3349 argLen: 1, 3350 asm: x86.ASETEQ, 3351 reg: regInfo{ 3352 outputs: []outputInfo{ 3353 {0, 239}, // AX CX DX BX BP SI DI 3354 }, 3355 }, 3356 }, 3357 { 3358 name: "SETNE", 3359 argLen: 1, 3360 asm: x86.ASETNE, 3361 reg: regInfo{ 3362 outputs: []outputInfo{ 3363 {0, 239}, // AX CX DX BX BP SI DI 3364 }, 3365 }, 3366 }, 3367 { 3368 name: "SETL", 3369 argLen: 1, 3370 asm: x86.ASETLT, 3371 reg: regInfo{ 3372 outputs: []outputInfo{ 3373 {0, 239}, // AX CX DX BX BP SI DI 3374 }, 3375 }, 3376 }, 3377 { 3378 name: "SETLE", 3379 argLen: 1, 3380 asm: x86.ASETLE, 3381 reg: regInfo{ 3382 outputs: []outputInfo{ 3383 {0, 239}, // AX CX DX BX BP SI DI 3384 }, 3385 }, 3386 }, 3387 { 3388 name: "SETG", 3389 argLen: 1, 3390 asm: x86.ASETGT, 3391 reg: regInfo{ 3392 outputs: []outputInfo{ 3393 {0, 239}, // AX CX DX BX BP SI DI 3394 }, 3395 }, 3396 }, 3397 { 3398 name: "SETGE", 3399 argLen: 1, 3400 asm: x86.ASETGE, 3401 reg: regInfo{ 3402 outputs: []outputInfo{ 3403 {0, 239}, // AX CX DX BX BP SI DI 3404 }, 3405 }, 3406 }, 3407 { 3408 name: "SETB", 3409 argLen: 1, 3410 asm: x86.ASETCS, 3411 reg: regInfo{ 3412 outputs: []outputInfo{ 3413 {0, 239}, // AX CX DX BX BP SI DI 3414 }, 3415 }, 3416 }, 3417 { 3418 name: "SETBE", 3419 argLen: 1, 3420 asm: x86.ASETLS, 3421 reg: regInfo{ 3422 outputs: []outputInfo{ 3423 {0, 239}, // AX CX DX BX BP SI DI 3424 }, 3425 }, 3426 }, 3427 { 3428 name: "SETA", 3429 argLen: 1, 3430 asm: x86.ASETHI, 3431 reg: regInfo{ 3432 outputs: []outputInfo{ 3433 {0, 239}, // AX CX DX BX BP SI DI 3434 }, 3435 }, 3436 }, 3437 { 3438 name: "SETAE", 3439 argLen: 1, 3440 asm: x86.ASETCC, 3441 reg: regInfo{ 3442 outputs: []outputInfo{ 3443 {0, 239}, // AX CX DX BX BP SI DI 3444 }, 3445 }, 3446 }, 3447 { 3448 name: "SETEQF", 3449 argLen: 1, 3450 clobberFlags: true, 3451 asm: x86.ASETEQ, 3452 reg: regInfo{ 3453 clobbers: 1, // AX 3454 outputs: []outputInfo{ 3455 {0, 238}, // CX DX BX BP SI DI 3456 }, 3457 }, 3458 }, 3459 { 3460 name: "SETNEF", 3461 argLen: 1, 3462 clobberFlags: true, 3463 asm: x86.ASETNE, 3464 reg: regInfo{ 3465 clobbers: 1, // AX 3466 outputs: []outputInfo{ 3467 {0, 238}, // CX DX BX BP SI DI 3468 }, 3469 }, 3470 }, 3471 { 3472 name: "SETORD", 3473 argLen: 1, 3474 asm: x86.ASETPC, 3475 reg: regInfo{ 3476 outputs: []outputInfo{ 3477 {0, 239}, // AX CX DX BX BP SI DI 3478 }, 3479 }, 3480 }, 3481 { 3482 name: "SETNAN", 3483 argLen: 1, 3484 asm: x86.ASETPS, 3485 reg: regInfo{ 3486 outputs: []outputInfo{ 3487 {0, 239}, // AX CX DX BX BP SI DI 3488 }, 3489 }, 3490 }, 3491 { 3492 name: "SETGF", 3493 argLen: 1, 3494 asm: x86.ASETHI, 3495 reg: regInfo{ 3496 outputs: []outputInfo{ 3497 {0, 239}, // AX CX DX BX BP SI DI 3498 }, 3499 }, 3500 }, 3501 { 3502 name: "SETGEF", 3503 argLen: 1, 3504 asm: x86.ASETCC, 3505 reg: regInfo{ 3506 outputs: []outputInfo{ 3507 {0, 239}, // AX CX DX BX BP SI DI 3508 }, 3509 }, 3510 }, 3511 { 3512 name: "MOVBLSX", 3513 argLen: 1, 3514 asm: x86.AMOVBLSX, 3515 reg: regInfo{ 3516 inputs: []inputInfo{ 3517 {0, 239}, // AX CX DX BX BP SI DI 3518 }, 3519 outputs: []outputInfo{ 3520 {0, 239}, // AX CX DX BX BP SI DI 3521 }, 3522 }, 3523 }, 3524 { 3525 name: "MOVBLZX", 3526 argLen: 1, 3527 asm: x86.AMOVBLZX, 3528 reg: regInfo{ 3529 inputs: []inputInfo{ 3530 {0, 239}, // AX CX DX BX BP SI DI 3531 }, 3532 outputs: []outputInfo{ 3533 {0, 239}, // AX CX DX BX BP SI DI 3534 }, 3535 }, 3536 }, 3537 { 3538 name: "MOVWLSX", 3539 argLen: 1, 3540 asm: x86.AMOVWLSX, 3541 reg: regInfo{ 3542 inputs: []inputInfo{ 3543 {0, 239}, // AX CX DX BX BP SI DI 3544 }, 3545 outputs: []outputInfo{ 3546 {0, 239}, // AX CX DX BX BP SI DI 3547 }, 3548 }, 3549 }, 3550 { 3551 name: "MOVWLZX", 3552 argLen: 1, 3553 asm: x86.AMOVWLZX, 3554 reg: regInfo{ 3555 inputs: []inputInfo{ 3556 {0, 239}, // AX CX DX BX BP SI DI 3557 }, 3558 outputs: []outputInfo{ 3559 {0, 239}, // AX CX DX BX BP SI DI 3560 }, 3561 }, 3562 }, 3563 { 3564 name: "MOVLconst", 3565 auxType: auxInt32, 3566 argLen: 0, 3567 rematerializeable: true, 3568 asm: x86.AMOVL, 3569 reg: regInfo{ 3570 outputs: []outputInfo{ 3571 {0, 239}, // AX CX DX BX BP SI DI 3572 }, 3573 }, 3574 }, 3575 { 3576 name: "CVTTSD2SL", 3577 argLen: 1, 3578 usesScratch: true, 3579 asm: x86.ACVTTSD2SL, 3580 reg: regInfo{ 3581 inputs: []inputInfo{ 3582 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3583 }, 3584 outputs: []outputInfo{ 3585 {0, 239}, // AX CX DX BX BP SI DI 3586 }, 3587 }, 3588 }, 3589 { 3590 name: "CVTTSS2SL", 3591 argLen: 1, 3592 usesScratch: true, 3593 asm: x86.ACVTTSS2SL, 3594 reg: regInfo{ 3595 inputs: []inputInfo{ 3596 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3597 }, 3598 outputs: []outputInfo{ 3599 {0, 239}, // AX CX DX BX BP SI DI 3600 }, 3601 }, 3602 }, 3603 { 3604 name: "CVTSL2SS", 3605 argLen: 1, 3606 usesScratch: true, 3607 asm: x86.ACVTSL2SS, 3608 reg: regInfo{ 3609 inputs: []inputInfo{ 3610 {0, 239}, // AX CX DX BX BP SI DI 3611 }, 3612 outputs: []outputInfo{ 3613 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3614 }, 3615 }, 3616 }, 3617 { 3618 name: "CVTSL2SD", 3619 argLen: 1, 3620 usesScratch: true, 3621 asm: x86.ACVTSL2SD, 3622 reg: regInfo{ 3623 inputs: []inputInfo{ 3624 {0, 239}, // AX CX DX BX BP SI DI 3625 }, 3626 outputs: []outputInfo{ 3627 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3628 }, 3629 }, 3630 }, 3631 { 3632 name: "CVTSD2SS", 3633 argLen: 1, 3634 usesScratch: true, 3635 asm: x86.ACVTSD2SS, 3636 reg: regInfo{ 3637 inputs: []inputInfo{ 3638 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3639 }, 3640 outputs: []outputInfo{ 3641 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3642 }, 3643 }, 3644 }, 3645 { 3646 name: "CVTSS2SD", 3647 argLen: 1, 3648 asm: x86.ACVTSS2SD, 3649 reg: regInfo{ 3650 inputs: []inputInfo{ 3651 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3652 }, 3653 outputs: []outputInfo{ 3654 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3655 }, 3656 }, 3657 }, 3658 { 3659 name: "PXOR", 3660 argLen: 2, 3661 commutative: true, 3662 resultInArg0: true, 3663 asm: x86.APXOR, 3664 reg: regInfo{ 3665 inputs: []inputInfo{ 3666 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3667 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3668 }, 3669 outputs: []outputInfo{ 3670 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3671 }, 3672 }, 3673 }, 3674 { 3675 name: "LEAL", 3676 auxType: auxSymOff, 3677 argLen: 1, 3678 rematerializeable: true, 3679 symEffect: SymAddr, 3680 reg: regInfo{ 3681 inputs: []inputInfo{ 3682 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3683 }, 3684 outputs: []outputInfo{ 3685 {0, 239}, // AX CX DX BX BP SI DI 3686 }, 3687 }, 3688 }, 3689 { 3690 name: "LEAL1", 3691 auxType: auxSymOff, 3692 argLen: 2, 3693 commutative: true, 3694 symEffect: SymAddr, 3695 reg: regInfo{ 3696 inputs: []inputInfo{ 3697 {1, 255}, // AX CX DX BX SP BP SI DI 3698 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3699 }, 3700 outputs: []outputInfo{ 3701 {0, 239}, // AX CX DX BX BP SI DI 3702 }, 3703 }, 3704 }, 3705 { 3706 name: "LEAL2", 3707 auxType: auxSymOff, 3708 argLen: 2, 3709 symEffect: SymAddr, 3710 reg: regInfo{ 3711 inputs: []inputInfo{ 3712 {1, 255}, // AX CX DX BX SP BP SI DI 3713 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3714 }, 3715 outputs: []outputInfo{ 3716 {0, 239}, // AX CX DX BX BP SI DI 3717 }, 3718 }, 3719 }, 3720 { 3721 name: "LEAL4", 3722 auxType: auxSymOff, 3723 argLen: 2, 3724 symEffect: SymAddr, 3725 reg: regInfo{ 3726 inputs: []inputInfo{ 3727 {1, 255}, // AX CX DX BX SP BP SI DI 3728 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3729 }, 3730 outputs: []outputInfo{ 3731 {0, 239}, // AX CX DX BX BP SI DI 3732 }, 3733 }, 3734 }, 3735 { 3736 name: "LEAL8", 3737 auxType: auxSymOff, 3738 argLen: 2, 3739 symEffect: SymAddr, 3740 reg: regInfo{ 3741 inputs: []inputInfo{ 3742 {1, 255}, // AX CX DX BX SP BP SI DI 3743 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3744 }, 3745 outputs: []outputInfo{ 3746 {0, 239}, // AX CX DX BX BP SI DI 3747 }, 3748 }, 3749 }, 3750 { 3751 name: "MOVBload", 3752 auxType: auxSymOff, 3753 argLen: 2, 3754 faultOnNilArg0: true, 3755 symEffect: SymRead, 3756 asm: x86.AMOVBLZX, 3757 reg: regInfo{ 3758 inputs: []inputInfo{ 3759 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3760 }, 3761 outputs: []outputInfo{ 3762 {0, 239}, // AX CX DX BX BP SI DI 3763 }, 3764 }, 3765 }, 3766 { 3767 name: "MOVBLSXload", 3768 auxType: auxSymOff, 3769 argLen: 2, 3770 faultOnNilArg0: true, 3771 symEffect: SymRead, 3772 asm: x86.AMOVBLSX, 3773 reg: regInfo{ 3774 inputs: []inputInfo{ 3775 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3776 }, 3777 outputs: []outputInfo{ 3778 {0, 239}, // AX CX DX BX BP SI DI 3779 }, 3780 }, 3781 }, 3782 { 3783 name: "MOVWload", 3784 auxType: auxSymOff, 3785 argLen: 2, 3786 faultOnNilArg0: true, 3787 symEffect: SymRead, 3788 asm: x86.AMOVWLZX, 3789 reg: regInfo{ 3790 inputs: []inputInfo{ 3791 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3792 }, 3793 outputs: []outputInfo{ 3794 {0, 239}, // AX CX DX BX BP SI DI 3795 }, 3796 }, 3797 }, 3798 { 3799 name: "MOVWLSXload", 3800 auxType: auxSymOff, 3801 argLen: 2, 3802 faultOnNilArg0: true, 3803 symEffect: SymRead, 3804 asm: x86.AMOVWLSX, 3805 reg: regInfo{ 3806 inputs: []inputInfo{ 3807 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3808 }, 3809 outputs: []outputInfo{ 3810 {0, 239}, // AX CX DX BX BP SI DI 3811 }, 3812 }, 3813 }, 3814 { 3815 name: "MOVLload", 3816 auxType: auxSymOff, 3817 argLen: 2, 3818 faultOnNilArg0: true, 3819 symEffect: SymRead, 3820 asm: x86.AMOVL, 3821 reg: regInfo{ 3822 inputs: []inputInfo{ 3823 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3824 }, 3825 outputs: []outputInfo{ 3826 {0, 239}, // AX CX DX BX BP SI DI 3827 }, 3828 }, 3829 }, 3830 { 3831 name: "MOVBstore", 3832 auxType: auxSymOff, 3833 argLen: 3, 3834 faultOnNilArg0: true, 3835 symEffect: SymWrite, 3836 asm: x86.AMOVB, 3837 reg: regInfo{ 3838 inputs: []inputInfo{ 3839 {1, 255}, // AX CX DX BX SP BP SI DI 3840 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3841 }, 3842 }, 3843 }, 3844 { 3845 name: "MOVWstore", 3846 auxType: auxSymOff, 3847 argLen: 3, 3848 faultOnNilArg0: true, 3849 symEffect: SymWrite, 3850 asm: x86.AMOVW, 3851 reg: regInfo{ 3852 inputs: []inputInfo{ 3853 {1, 255}, // AX CX DX BX SP BP SI DI 3854 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3855 }, 3856 }, 3857 }, 3858 { 3859 name: "MOVLstore", 3860 auxType: auxSymOff, 3861 argLen: 3, 3862 faultOnNilArg0: true, 3863 symEffect: SymWrite, 3864 asm: x86.AMOVL, 3865 reg: regInfo{ 3866 inputs: []inputInfo{ 3867 {1, 255}, // AX CX DX BX SP BP SI DI 3868 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3869 }, 3870 }, 3871 }, 3872 { 3873 name: "MOVBloadidx1", 3874 auxType: auxSymOff, 3875 argLen: 3, 3876 commutative: true, 3877 symEffect: SymRead, 3878 asm: x86.AMOVBLZX, 3879 reg: regInfo{ 3880 inputs: []inputInfo{ 3881 {1, 255}, // AX CX DX BX SP BP SI DI 3882 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3883 }, 3884 outputs: []outputInfo{ 3885 {0, 239}, // AX CX DX BX BP SI DI 3886 }, 3887 }, 3888 }, 3889 { 3890 name: "MOVWloadidx1", 3891 auxType: auxSymOff, 3892 argLen: 3, 3893 commutative: true, 3894 symEffect: SymRead, 3895 asm: x86.AMOVWLZX, 3896 reg: regInfo{ 3897 inputs: []inputInfo{ 3898 {1, 255}, // AX CX DX BX SP BP SI DI 3899 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3900 }, 3901 outputs: []outputInfo{ 3902 {0, 239}, // AX CX DX BX BP SI DI 3903 }, 3904 }, 3905 }, 3906 { 3907 name: "MOVWloadidx2", 3908 auxType: auxSymOff, 3909 argLen: 3, 3910 symEffect: SymRead, 3911 asm: x86.AMOVWLZX, 3912 reg: regInfo{ 3913 inputs: []inputInfo{ 3914 {1, 255}, // AX CX DX BX SP BP SI DI 3915 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3916 }, 3917 outputs: []outputInfo{ 3918 {0, 239}, // AX CX DX BX BP SI DI 3919 }, 3920 }, 3921 }, 3922 { 3923 name: "MOVLloadidx1", 3924 auxType: auxSymOff, 3925 argLen: 3, 3926 commutative: true, 3927 symEffect: SymRead, 3928 asm: x86.AMOVL, 3929 reg: regInfo{ 3930 inputs: []inputInfo{ 3931 {1, 255}, // AX CX DX BX SP BP SI DI 3932 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3933 }, 3934 outputs: []outputInfo{ 3935 {0, 239}, // AX CX DX BX BP SI DI 3936 }, 3937 }, 3938 }, 3939 { 3940 name: "MOVLloadidx4", 3941 auxType: auxSymOff, 3942 argLen: 3, 3943 symEffect: SymRead, 3944 asm: x86.AMOVL, 3945 reg: regInfo{ 3946 inputs: []inputInfo{ 3947 {1, 255}, // AX CX DX BX SP BP SI DI 3948 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3949 }, 3950 outputs: []outputInfo{ 3951 {0, 239}, // AX CX DX BX BP SI DI 3952 }, 3953 }, 3954 }, 3955 { 3956 name: "MOVBstoreidx1", 3957 auxType: auxSymOff, 3958 argLen: 4, 3959 commutative: true, 3960 symEffect: SymWrite, 3961 asm: x86.AMOVB, 3962 reg: regInfo{ 3963 inputs: []inputInfo{ 3964 {1, 255}, // AX CX DX BX SP BP SI DI 3965 {2, 255}, // AX CX DX BX SP BP SI DI 3966 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3967 }, 3968 }, 3969 }, 3970 { 3971 name: "MOVWstoreidx1", 3972 auxType: auxSymOff, 3973 argLen: 4, 3974 commutative: true, 3975 symEffect: SymWrite, 3976 asm: x86.AMOVW, 3977 reg: regInfo{ 3978 inputs: []inputInfo{ 3979 {1, 255}, // AX CX DX BX SP BP SI DI 3980 {2, 255}, // AX CX DX BX SP BP SI DI 3981 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3982 }, 3983 }, 3984 }, 3985 { 3986 name: "MOVWstoreidx2", 3987 auxType: auxSymOff, 3988 argLen: 4, 3989 symEffect: SymWrite, 3990 asm: x86.AMOVW, 3991 reg: regInfo{ 3992 inputs: []inputInfo{ 3993 {1, 255}, // AX CX DX BX SP BP SI DI 3994 {2, 255}, // AX CX DX BX SP BP SI DI 3995 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3996 }, 3997 }, 3998 }, 3999 { 4000 name: "MOVLstoreidx1", 4001 auxType: auxSymOff, 4002 argLen: 4, 4003 commutative: true, 4004 symEffect: SymWrite, 4005 asm: x86.AMOVL, 4006 reg: regInfo{ 4007 inputs: []inputInfo{ 4008 {1, 255}, // AX CX DX BX SP BP SI DI 4009 {2, 255}, // AX CX DX BX SP BP SI DI 4010 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4011 }, 4012 }, 4013 }, 4014 { 4015 name: "MOVLstoreidx4", 4016 auxType: auxSymOff, 4017 argLen: 4, 4018 symEffect: SymWrite, 4019 asm: x86.AMOVL, 4020 reg: regInfo{ 4021 inputs: []inputInfo{ 4022 {1, 255}, // AX CX DX BX SP BP SI DI 4023 {2, 255}, // AX CX DX BX SP BP SI DI 4024 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4025 }, 4026 }, 4027 }, 4028 { 4029 name: "MOVBstoreconst", 4030 auxType: auxSymValAndOff, 4031 argLen: 2, 4032 faultOnNilArg0: true, 4033 symEffect: SymWrite, 4034 asm: x86.AMOVB, 4035 reg: regInfo{ 4036 inputs: []inputInfo{ 4037 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4038 }, 4039 }, 4040 }, 4041 { 4042 name: "MOVWstoreconst", 4043 auxType: auxSymValAndOff, 4044 argLen: 2, 4045 faultOnNilArg0: true, 4046 symEffect: SymWrite, 4047 asm: x86.AMOVW, 4048 reg: regInfo{ 4049 inputs: []inputInfo{ 4050 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4051 }, 4052 }, 4053 }, 4054 { 4055 name: "MOVLstoreconst", 4056 auxType: auxSymValAndOff, 4057 argLen: 2, 4058 faultOnNilArg0: true, 4059 symEffect: SymWrite, 4060 asm: x86.AMOVL, 4061 reg: regInfo{ 4062 inputs: []inputInfo{ 4063 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4064 }, 4065 }, 4066 }, 4067 { 4068 name: "MOVBstoreconstidx1", 4069 auxType: auxSymValAndOff, 4070 argLen: 3, 4071 symEffect: SymWrite, 4072 asm: x86.AMOVB, 4073 reg: regInfo{ 4074 inputs: []inputInfo{ 4075 {1, 255}, // AX CX DX BX SP BP SI DI 4076 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4077 }, 4078 }, 4079 }, 4080 { 4081 name: "MOVWstoreconstidx1", 4082 auxType: auxSymValAndOff, 4083 argLen: 3, 4084 symEffect: SymWrite, 4085 asm: x86.AMOVW, 4086 reg: regInfo{ 4087 inputs: []inputInfo{ 4088 {1, 255}, // AX CX DX BX SP BP SI DI 4089 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4090 }, 4091 }, 4092 }, 4093 { 4094 name: "MOVWstoreconstidx2", 4095 auxType: auxSymValAndOff, 4096 argLen: 3, 4097 symEffect: SymWrite, 4098 asm: x86.AMOVW, 4099 reg: regInfo{ 4100 inputs: []inputInfo{ 4101 {1, 255}, // AX CX DX BX SP BP SI DI 4102 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4103 }, 4104 }, 4105 }, 4106 { 4107 name: "MOVLstoreconstidx1", 4108 auxType: auxSymValAndOff, 4109 argLen: 3, 4110 symEffect: SymWrite, 4111 asm: x86.AMOVL, 4112 reg: regInfo{ 4113 inputs: []inputInfo{ 4114 {1, 255}, // AX CX DX BX SP BP SI DI 4115 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4116 }, 4117 }, 4118 }, 4119 { 4120 name: "MOVLstoreconstidx4", 4121 auxType: auxSymValAndOff, 4122 argLen: 3, 4123 symEffect: SymWrite, 4124 asm: x86.AMOVL, 4125 reg: regInfo{ 4126 inputs: []inputInfo{ 4127 {1, 255}, // AX CX DX BX SP BP SI DI 4128 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4129 }, 4130 }, 4131 }, 4132 { 4133 name: "DUFFZERO", 4134 auxType: auxInt64, 4135 argLen: 3, 4136 faultOnNilArg0: true, 4137 reg: regInfo{ 4138 inputs: []inputInfo{ 4139 {0, 128}, // DI 4140 {1, 1}, // AX 4141 }, 4142 clobbers: 130, // CX DI 4143 }, 4144 }, 4145 { 4146 name: "REPSTOSL", 4147 argLen: 4, 4148 faultOnNilArg0: true, 4149 reg: regInfo{ 4150 inputs: []inputInfo{ 4151 {0, 128}, // DI 4152 {1, 2}, // CX 4153 {2, 1}, // AX 4154 }, 4155 clobbers: 130, // CX DI 4156 }, 4157 }, 4158 { 4159 name: "CALLstatic", 4160 auxType: auxSymOff, 4161 argLen: 1, 4162 clobberFlags: true, 4163 call: true, 4164 symEffect: SymNone, 4165 reg: regInfo{ 4166 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4167 }, 4168 }, 4169 { 4170 name: "CALLclosure", 4171 auxType: auxInt64, 4172 argLen: 3, 4173 clobberFlags: true, 4174 call: true, 4175 reg: regInfo{ 4176 inputs: []inputInfo{ 4177 {1, 4}, // DX 4178 {0, 255}, // AX CX DX BX SP BP SI DI 4179 }, 4180 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4181 }, 4182 }, 4183 { 4184 name: "CALLinter", 4185 auxType: auxInt64, 4186 argLen: 2, 4187 clobberFlags: true, 4188 call: true, 4189 reg: regInfo{ 4190 inputs: []inputInfo{ 4191 {0, 239}, // AX CX DX BX BP SI DI 4192 }, 4193 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4194 }, 4195 }, 4196 { 4197 name: "DUFFCOPY", 4198 auxType: auxInt64, 4199 argLen: 3, 4200 clobberFlags: true, 4201 faultOnNilArg0: true, 4202 faultOnNilArg1: true, 4203 reg: regInfo{ 4204 inputs: []inputInfo{ 4205 {0, 128}, // DI 4206 {1, 64}, // SI 4207 }, 4208 clobbers: 194, // CX SI DI 4209 }, 4210 }, 4211 { 4212 name: "REPMOVSL", 4213 argLen: 4, 4214 faultOnNilArg0: true, 4215 faultOnNilArg1: true, 4216 reg: regInfo{ 4217 inputs: []inputInfo{ 4218 {0, 128}, // DI 4219 {1, 64}, // SI 4220 {2, 2}, // CX 4221 }, 4222 clobbers: 194, // CX SI DI 4223 }, 4224 }, 4225 { 4226 name: "InvertFlags", 4227 argLen: 1, 4228 reg: regInfo{}, 4229 }, 4230 { 4231 name: "LoweredGetG", 4232 argLen: 1, 4233 reg: regInfo{ 4234 outputs: []outputInfo{ 4235 {0, 239}, // AX CX DX BX BP SI DI 4236 }, 4237 }, 4238 }, 4239 { 4240 name: "LoweredGetClosurePtr", 4241 argLen: 0, 4242 reg: regInfo{ 4243 outputs: []outputInfo{ 4244 {0, 4}, // DX 4245 }, 4246 }, 4247 }, 4248 { 4249 name: "LoweredNilCheck", 4250 argLen: 2, 4251 clobberFlags: true, 4252 nilCheck: true, 4253 faultOnNilArg0: true, 4254 reg: regInfo{ 4255 inputs: []inputInfo{ 4256 {0, 255}, // AX CX DX BX SP BP SI DI 4257 }, 4258 }, 4259 }, 4260 { 4261 name: "MOVLconvert", 4262 argLen: 2, 4263 asm: x86.AMOVL, 4264 reg: regInfo{ 4265 inputs: []inputInfo{ 4266 {0, 239}, // AX CX DX BX BP SI DI 4267 }, 4268 outputs: []outputInfo{ 4269 {0, 239}, // AX CX DX BX BP SI DI 4270 }, 4271 }, 4272 }, 4273 { 4274 name: "FlagEQ", 4275 argLen: 0, 4276 reg: regInfo{}, 4277 }, 4278 { 4279 name: "FlagLT_ULT", 4280 argLen: 0, 4281 reg: regInfo{}, 4282 }, 4283 { 4284 name: "FlagLT_UGT", 4285 argLen: 0, 4286 reg: regInfo{}, 4287 }, 4288 { 4289 name: "FlagGT_UGT", 4290 argLen: 0, 4291 reg: regInfo{}, 4292 }, 4293 { 4294 name: "FlagGT_ULT", 4295 argLen: 0, 4296 reg: regInfo{}, 4297 }, 4298 { 4299 name: "FCHS", 4300 argLen: 1, 4301 reg: regInfo{ 4302 inputs: []inputInfo{ 4303 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4304 }, 4305 outputs: []outputInfo{ 4306 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4307 }, 4308 }, 4309 }, 4310 { 4311 name: "MOVSSconst1", 4312 auxType: auxFloat32, 4313 argLen: 0, 4314 reg: regInfo{ 4315 outputs: []outputInfo{ 4316 {0, 239}, // AX CX DX BX BP SI DI 4317 }, 4318 }, 4319 }, 4320 { 4321 name: "MOVSDconst1", 4322 auxType: auxFloat64, 4323 argLen: 0, 4324 reg: regInfo{ 4325 outputs: []outputInfo{ 4326 {0, 239}, // AX CX DX BX BP SI DI 4327 }, 4328 }, 4329 }, 4330 { 4331 name: "MOVSSconst2", 4332 argLen: 1, 4333 asm: x86.AMOVSS, 4334 reg: regInfo{ 4335 inputs: []inputInfo{ 4336 {0, 239}, // AX CX DX BX BP SI DI 4337 }, 4338 outputs: []outputInfo{ 4339 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4340 }, 4341 }, 4342 }, 4343 { 4344 name: "MOVSDconst2", 4345 argLen: 1, 4346 asm: x86.AMOVSD, 4347 reg: regInfo{ 4348 inputs: []inputInfo{ 4349 {0, 239}, // AX CX DX BX BP SI DI 4350 }, 4351 outputs: []outputInfo{ 4352 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4353 }, 4354 }, 4355 }, 4356 4357 { 4358 name: "ADDSS", 4359 argLen: 2, 4360 commutative: true, 4361 resultInArg0: true, 4362 asm: x86.AADDSS, 4363 reg: regInfo{ 4364 inputs: []inputInfo{ 4365 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4366 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4367 }, 4368 outputs: []outputInfo{ 4369 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4370 }, 4371 }, 4372 }, 4373 { 4374 name: "ADDSD", 4375 argLen: 2, 4376 commutative: true, 4377 resultInArg0: true, 4378 asm: x86.AADDSD, 4379 reg: regInfo{ 4380 inputs: []inputInfo{ 4381 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4382 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4383 }, 4384 outputs: []outputInfo{ 4385 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4386 }, 4387 }, 4388 }, 4389 { 4390 name: "SUBSS", 4391 argLen: 2, 4392 resultInArg0: true, 4393 asm: x86.ASUBSS, 4394 reg: regInfo{ 4395 inputs: []inputInfo{ 4396 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4397 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4398 }, 4399 outputs: []outputInfo{ 4400 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4401 }, 4402 }, 4403 }, 4404 { 4405 name: "SUBSD", 4406 argLen: 2, 4407 resultInArg0: true, 4408 asm: x86.ASUBSD, 4409 reg: regInfo{ 4410 inputs: []inputInfo{ 4411 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4412 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4413 }, 4414 outputs: []outputInfo{ 4415 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4416 }, 4417 }, 4418 }, 4419 { 4420 name: "MULSS", 4421 argLen: 2, 4422 commutative: true, 4423 resultInArg0: true, 4424 asm: x86.AMULSS, 4425 reg: regInfo{ 4426 inputs: []inputInfo{ 4427 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4428 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4429 }, 4430 outputs: []outputInfo{ 4431 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4432 }, 4433 }, 4434 }, 4435 { 4436 name: "MULSD", 4437 argLen: 2, 4438 commutative: true, 4439 resultInArg0: true, 4440 asm: x86.AMULSD, 4441 reg: regInfo{ 4442 inputs: []inputInfo{ 4443 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4444 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4445 }, 4446 outputs: []outputInfo{ 4447 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4448 }, 4449 }, 4450 }, 4451 { 4452 name: "DIVSS", 4453 argLen: 2, 4454 resultInArg0: true, 4455 asm: x86.ADIVSS, 4456 reg: regInfo{ 4457 inputs: []inputInfo{ 4458 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4459 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4460 }, 4461 outputs: []outputInfo{ 4462 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4463 }, 4464 }, 4465 }, 4466 { 4467 name: "DIVSD", 4468 argLen: 2, 4469 resultInArg0: true, 4470 asm: x86.ADIVSD, 4471 reg: regInfo{ 4472 inputs: []inputInfo{ 4473 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4474 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4475 }, 4476 outputs: []outputInfo{ 4477 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4478 }, 4479 }, 4480 }, 4481 { 4482 name: "MOVSSload", 4483 auxType: auxSymOff, 4484 argLen: 2, 4485 faultOnNilArg0: true, 4486 symEffect: SymRead, 4487 asm: x86.AMOVSS, 4488 reg: regInfo{ 4489 inputs: []inputInfo{ 4490 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4491 }, 4492 outputs: []outputInfo{ 4493 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4494 }, 4495 }, 4496 }, 4497 { 4498 name: "MOVSDload", 4499 auxType: auxSymOff, 4500 argLen: 2, 4501 faultOnNilArg0: true, 4502 symEffect: SymRead, 4503 asm: x86.AMOVSD, 4504 reg: regInfo{ 4505 inputs: []inputInfo{ 4506 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4507 }, 4508 outputs: []outputInfo{ 4509 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4510 }, 4511 }, 4512 }, 4513 { 4514 name: "MOVSSconst", 4515 auxType: auxFloat32, 4516 argLen: 0, 4517 rematerializeable: true, 4518 asm: x86.AMOVSS, 4519 reg: regInfo{ 4520 outputs: []outputInfo{ 4521 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4522 }, 4523 }, 4524 }, 4525 { 4526 name: "MOVSDconst", 4527 auxType: auxFloat64, 4528 argLen: 0, 4529 rematerializeable: true, 4530 asm: x86.AMOVSD, 4531 reg: regInfo{ 4532 outputs: []outputInfo{ 4533 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4534 }, 4535 }, 4536 }, 4537 { 4538 name: "MOVSSloadidx1", 4539 auxType: auxSymOff, 4540 argLen: 3, 4541 symEffect: SymRead, 4542 asm: x86.AMOVSS, 4543 reg: regInfo{ 4544 inputs: []inputInfo{ 4545 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4546 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4547 }, 4548 outputs: []outputInfo{ 4549 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4550 }, 4551 }, 4552 }, 4553 { 4554 name: "MOVSSloadidx4", 4555 auxType: auxSymOff, 4556 argLen: 3, 4557 symEffect: SymRead, 4558 asm: x86.AMOVSS, 4559 reg: regInfo{ 4560 inputs: []inputInfo{ 4561 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4562 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4563 }, 4564 outputs: []outputInfo{ 4565 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4566 }, 4567 }, 4568 }, 4569 { 4570 name: "MOVSDloadidx1", 4571 auxType: auxSymOff, 4572 argLen: 3, 4573 symEffect: SymRead, 4574 asm: x86.AMOVSD, 4575 reg: regInfo{ 4576 inputs: []inputInfo{ 4577 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4578 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4579 }, 4580 outputs: []outputInfo{ 4581 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4582 }, 4583 }, 4584 }, 4585 { 4586 name: "MOVSDloadidx8", 4587 auxType: auxSymOff, 4588 argLen: 3, 4589 symEffect: SymRead, 4590 asm: x86.AMOVSD, 4591 reg: regInfo{ 4592 inputs: []inputInfo{ 4593 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4594 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4595 }, 4596 outputs: []outputInfo{ 4597 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4598 }, 4599 }, 4600 }, 4601 { 4602 name: "MOVSSstore", 4603 auxType: auxSymOff, 4604 argLen: 3, 4605 faultOnNilArg0: true, 4606 symEffect: SymWrite, 4607 asm: x86.AMOVSS, 4608 reg: regInfo{ 4609 inputs: []inputInfo{ 4610 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4611 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4612 }, 4613 }, 4614 }, 4615 { 4616 name: "MOVSDstore", 4617 auxType: auxSymOff, 4618 argLen: 3, 4619 faultOnNilArg0: true, 4620 symEffect: SymWrite, 4621 asm: x86.AMOVSD, 4622 reg: regInfo{ 4623 inputs: []inputInfo{ 4624 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4625 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4626 }, 4627 }, 4628 }, 4629 { 4630 name: "MOVSSstoreidx1", 4631 auxType: auxSymOff, 4632 argLen: 4, 4633 symEffect: SymWrite, 4634 asm: x86.AMOVSS, 4635 reg: regInfo{ 4636 inputs: []inputInfo{ 4637 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4638 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4639 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4640 }, 4641 }, 4642 }, 4643 { 4644 name: "MOVSSstoreidx4", 4645 auxType: auxSymOff, 4646 argLen: 4, 4647 symEffect: SymWrite, 4648 asm: x86.AMOVSS, 4649 reg: regInfo{ 4650 inputs: []inputInfo{ 4651 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4652 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4653 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4654 }, 4655 }, 4656 }, 4657 { 4658 name: "MOVSDstoreidx1", 4659 auxType: auxSymOff, 4660 argLen: 4, 4661 symEffect: SymWrite, 4662 asm: x86.AMOVSD, 4663 reg: regInfo{ 4664 inputs: []inputInfo{ 4665 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4666 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4667 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4668 }, 4669 }, 4670 }, 4671 { 4672 name: "MOVSDstoreidx8", 4673 auxType: auxSymOff, 4674 argLen: 4, 4675 symEffect: SymWrite, 4676 asm: x86.AMOVSD, 4677 reg: regInfo{ 4678 inputs: []inputInfo{ 4679 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4680 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4681 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4682 }, 4683 }, 4684 }, 4685 { 4686 name: "ADDSDmem", 4687 auxType: auxSymOff, 4688 argLen: 3, 4689 resultInArg0: true, 4690 faultOnNilArg1: true, 4691 symEffect: SymRead, 4692 asm: x86.AADDSD, 4693 reg: regInfo{ 4694 inputs: []inputInfo{ 4695 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4696 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4697 }, 4698 outputs: []outputInfo{ 4699 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4700 }, 4701 }, 4702 }, 4703 { 4704 name: "ADDSSmem", 4705 auxType: auxSymOff, 4706 argLen: 3, 4707 resultInArg0: true, 4708 faultOnNilArg1: true, 4709 symEffect: SymRead, 4710 asm: x86.AADDSS, 4711 reg: regInfo{ 4712 inputs: []inputInfo{ 4713 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4714 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4715 }, 4716 outputs: []outputInfo{ 4717 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4718 }, 4719 }, 4720 }, 4721 { 4722 name: "SUBSSmem", 4723 auxType: auxSymOff, 4724 argLen: 3, 4725 resultInArg0: true, 4726 faultOnNilArg1: true, 4727 symEffect: SymRead, 4728 asm: x86.ASUBSS, 4729 reg: regInfo{ 4730 inputs: []inputInfo{ 4731 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4732 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4733 }, 4734 outputs: []outputInfo{ 4735 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4736 }, 4737 }, 4738 }, 4739 { 4740 name: "SUBSDmem", 4741 auxType: auxSymOff, 4742 argLen: 3, 4743 resultInArg0: true, 4744 faultOnNilArg1: true, 4745 symEffect: SymRead, 4746 asm: x86.ASUBSD, 4747 reg: regInfo{ 4748 inputs: []inputInfo{ 4749 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4750 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4751 }, 4752 outputs: []outputInfo{ 4753 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4754 }, 4755 }, 4756 }, 4757 { 4758 name: "MULSSmem", 4759 auxType: auxSymOff, 4760 argLen: 3, 4761 resultInArg0: true, 4762 faultOnNilArg1: true, 4763 symEffect: SymRead, 4764 asm: x86.AMULSS, 4765 reg: regInfo{ 4766 inputs: []inputInfo{ 4767 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4768 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4769 }, 4770 outputs: []outputInfo{ 4771 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4772 }, 4773 }, 4774 }, 4775 { 4776 name: "MULSDmem", 4777 auxType: auxSymOff, 4778 argLen: 3, 4779 resultInArg0: true, 4780 faultOnNilArg1: true, 4781 symEffect: SymRead, 4782 asm: x86.AMULSD, 4783 reg: regInfo{ 4784 inputs: []inputInfo{ 4785 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4786 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4787 }, 4788 outputs: []outputInfo{ 4789 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4790 }, 4791 }, 4792 }, 4793 { 4794 name: "ADDQ", 4795 argLen: 2, 4796 commutative: true, 4797 clobberFlags: true, 4798 asm: x86.AADDQ, 4799 reg: regInfo{ 4800 inputs: []inputInfo{ 4801 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4802 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4803 }, 4804 outputs: []outputInfo{ 4805 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4806 }, 4807 }, 4808 }, 4809 { 4810 name: "ADDL", 4811 argLen: 2, 4812 commutative: true, 4813 clobberFlags: true, 4814 asm: x86.AADDL, 4815 reg: regInfo{ 4816 inputs: []inputInfo{ 4817 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4818 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4819 }, 4820 outputs: []outputInfo{ 4821 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4822 }, 4823 }, 4824 }, 4825 { 4826 name: "ADDQconst", 4827 auxType: auxInt32, 4828 argLen: 1, 4829 clobberFlags: true, 4830 asm: x86.AADDQ, 4831 reg: regInfo{ 4832 inputs: []inputInfo{ 4833 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4834 }, 4835 outputs: []outputInfo{ 4836 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4837 }, 4838 }, 4839 }, 4840 { 4841 name: "ADDLconst", 4842 auxType: auxInt32, 4843 argLen: 1, 4844 clobberFlags: true, 4845 asm: x86.AADDL, 4846 reg: regInfo{ 4847 inputs: []inputInfo{ 4848 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4849 }, 4850 outputs: []outputInfo{ 4851 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4852 }, 4853 }, 4854 }, 4855 { 4856 name: "SUBQ", 4857 argLen: 2, 4858 resultInArg0: true, 4859 clobberFlags: true, 4860 asm: x86.ASUBQ, 4861 reg: regInfo{ 4862 inputs: []inputInfo{ 4863 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4864 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4865 }, 4866 outputs: []outputInfo{ 4867 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4868 }, 4869 }, 4870 }, 4871 { 4872 name: "SUBL", 4873 argLen: 2, 4874 resultInArg0: true, 4875 clobberFlags: true, 4876 asm: x86.ASUBL, 4877 reg: regInfo{ 4878 inputs: []inputInfo{ 4879 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4880 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4881 }, 4882 outputs: []outputInfo{ 4883 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4884 }, 4885 }, 4886 }, 4887 { 4888 name: "SUBQconst", 4889 auxType: auxInt32, 4890 argLen: 1, 4891 resultInArg0: true, 4892 clobberFlags: true, 4893 asm: x86.ASUBQ, 4894 reg: regInfo{ 4895 inputs: []inputInfo{ 4896 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4897 }, 4898 outputs: []outputInfo{ 4899 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4900 }, 4901 }, 4902 }, 4903 { 4904 name: "SUBLconst", 4905 auxType: auxInt32, 4906 argLen: 1, 4907 resultInArg0: true, 4908 clobberFlags: true, 4909 asm: x86.ASUBL, 4910 reg: regInfo{ 4911 inputs: []inputInfo{ 4912 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4913 }, 4914 outputs: []outputInfo{ 4915 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4916 }, 4917 }, 4918 }, 4919 { 4920 name: "MULQ", 4921 argLen: 2, 4922 commutative: true, 4923 resultInArg0: true, 4924 clobberFlags: true, 4925 asm: x86.AIMULQ, 4926 reg: regInfo{ 4927 inputs: []inputInfo{ 4928 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4929 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4930 }, 4931 outputs: []outputInfo{ 4932 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4933 }, 4934 }, 4935 }, 4936 { 4937 name: "MULL", 4938 argLen: 2, 4939 commutative: true, 4940 resultInArg0: true, 4941 clobberFlags: true, 4942 asm: x86.AIMULL, 4943 reg: regInfo{ 4944 inputs: []inputInfo{ 4945 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4946 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4947 }, 4948 outputs: []outputInfo{ 4949 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4950 }, 4951 }, 4952 }, 4953 { 4954 name: "MULQconst", 4955 auxType: auxInt32, 4956 argLen: 1, 4957 resultInArg0: true, 4958 clobberFlags: true, 4959 asm: x86.AIMULQ, 4960 reg: regInfo{ 4961 inputs: []inputInfo{ 4962 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4963 }, 4964 outputs: []outputInfo{ 4965 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4966 }, 4967 }, 4968 }, 4969 { 4970 name: "MULLconst", 4971 auxType: auxInt32, 4972 argLen: 1, 4973 resultInArg0: true, 4974 clobberFlags: true, 4975 asm: x86.AIMULL, 4976 reg: regInfo{ 4977 inputs: []inputInfo{ 4978 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4979 }, 4980 outputs: []outputInfo{ 4981 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4982 }, 4983 }, 4984 }, 4985 { 4986 name: "HMULQ", 4987 argLen: 2, 4988 commutative: true, 4989 clobberFlags: true, 4990 asm: x86.AIMULQ, 4991 reg: regInfo{ 4992 inputs: []inputInfo{ 4993 {0, 1}, // AX 4994 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4995 }, 4996 clobbers: 1, // AX 4997 outputs: []outputInfo{ 4998 {0, 4}, // DX 4999 }, 5000 }, 5001 }, 5002 { 5003 name: "HMULL", 5004 argLen: 2, 5005 commutative: true, 5006 clobberFlags: true, 5007 asm: x86.AIMULL, 5008 reg: regInfo{ 5009 inputs: []inputInfo{ 5010 {0, 1}, // AX 5011 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5012 }, 5013 clobbers: 1, // AX 5014 outputs: []outputInfo{ 5015 {0, 4}, // DX 5016 }, 5017 }, 5018 }, 5019 { 5020 name: "HMULQU", 5021 argLen: 2, 5022 commutative: true, 5023 clobberFlags: true, 5024 asm: x86.AMULQ, 5025 reg: regInfo{ 5026 inputs: []inputInfo{ 5027 {0, 1}, // AX 5028 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5029 }, 5030 clobbers: 1, // AX 5031 outputs: []outputInfo{ 5032 {0, 4}, // DX 5033 }, 5034 }, 5035 }, 5036 { 5037 name: "HMULLU", 5038 argLen: 2, 5039 commutative: true, 5040 clobberFlags: true, 5041 asm: x86.AMULL, 5042 reg: regInfo{ 5043 inputs: []inputInfo{ 5044 {0, 1}, // AX 5045 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5046 }, 5047 clobbers: 1, // AX 5048 outputs: []outputInfo{ 5049 {0, 4}, // DX 5050 }, 5051 }, 5052 }, 5053 { 5054 name: "AVGQU", 5055 argLen: 2, 5056 commutative: true, 5057 resultInArg0: true, 5058 clobberFlags: true, 5059 reg: regInfo{ 5060 inputs: []inputInfo{ 5061 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5062 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5063 }, 5064 outputs: []outputInfo{ 5065 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5066 }, 5067 }, 5068 }, 5069 { 5070 name: "DIVQ", 5071 argLen: 2, 5072 clobberFlags: true, 5073 asm: x86.AIDIVQ, 5074 reg: regInfo{ 5075 inputs: []inputInfo{ 5076 {0, 1}, // AX 5077 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5078 }, 5079 outputs: []outputInfo{ 5080 {0, 1}, // AX 5081 {1, 4}, // DX 5082 }, 5083 }, 5084 }, 5085 { 5086 name: "DIVL", 5087 argLen: 2, 5088 clobberFlags: true, 5089 asm: x86.AIDIVL, 5090 reg: regInfo{ 5091 inputs: []inputInfo{ 5092 {0, 1}, // AX 5093 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5094 }, 5095 outputs: []outputInfo{ 5096 {0, 1}, // AX 5097 {1, 4}, // DX 5098 }, 5099 }, 5100 }, 5101 { 5102 name: "DIVW", 5103 argLen: 2, 5104 clobberFlags: true, 5105 asm: x86.AIDIVW, 5106 reg: regInfo{ 5107 inputs: []inputInfo{ 5108 {0, 1}, // AX 5109 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5110 }, 5111 outputs: []outputInfo{ 5112 {0, 1}, // AX 5113 {1, 4}, // DX 5114 }, 5115 }, 5116 }, 5117 { 5118 name: "DIVQU", 5119 argLen: 2, 5120 clobberFlags: true, 5121 asm: x86.ADIVQ, 5122 reg: regInfo{ 5123 inputs: []inputInfo{ 5124 {0, 1}, // AX 5125 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5126 }, 5127 outputs: []outputInfo{ 5128 {0, 1}, // AX 5129 {1, 4}, // DX 5130 }, 5131 }, 5132 }, 5133 { 5134 name: "DIVLU", 5135 argLen: 2, 5136 clobberFlags: true, 5137 asm: x86.ADIVL, 5138 reg: regInfo{ 5139 inputs: []inputInfo{ 5140 {0, 1}, // AX 5141 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5142 }, 5143 outputs: []outputInfo{ 5144 {0, 1}, // AX 5145 {1, 4}, // DX 5146 }, 5147 }, 5148 }, 5149 { 5150 name: "DIVWU", 5151 argLen: 2, 5152 clobberFlags: true, 5153 asm: x86.ADIVW, 5154 reg: regInfo{ 5155 inputs: []inputInfo{ 5156 {0, 1}, // AX 5157 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5158 }, 5159 outputs: []outputInfo{ 5160 {0, 1}, // AX 5161 {1, 4}, // DX 5162 }, 5163 }, 5164 }, 5165 { 5166 name: "MULQU2", 5167 argLen: 2, 5168 commutative: true, 5169 clobberFlags: true, 5170 asm: x86.AMULQ, 5171 reg: regInfo{ 5172 inputs: []inputInfo{ 5173 {0, 1}, // AX 5174 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5175 }, 5176 outputs: []outputInfo{ 5177 {0, 4}, // DX 5178 {1, 1}, // AX 5179 }, 5180 }, 5181 }, 5182 { 5183 name: "DIVQU2", 5184 argLen: 3, 5185 clobberFlags: true, 5186 asm: x86.ADIVQ, 5187 reg: regInfo{ 5188 inputs: []inputInfo{ 5189 {0, 4}, // DX 5190 {1, 1}, // AX 5191 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5192 }, 5193 outputs: []outputInfo{ 5194 {0, 1}, // AX 5195 {1, 4}, // DX 5196 }, 5197 }, 5198 }, 5199 { 5200 name: "ANDQ", 5201 argLen: 2, 5202 commutative: true, 5203 resultInArg0: true, 5204 clobberFlags: true, 5205 asm: x86.AANDQ, 5206 reg: regInfo{ 5207 inputs: []inputInfo{ 5208 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5209 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5210 }, 5211 outputs: []outputInfo{ 5212 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5213 }, 5214 }, 5215 }, 5216 { 5217 name: "ANDL", 5218 argLen: 2, 5219 commutative: true, 5220 resultInArg0: true, 5221 clobberFlags: true, 5222 asm: x86.AANDL, 5223 reg: regInfo{ 5224 inputs: []inputInfo{ 5225 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5226 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5227 }, 5228 outputs: []outputInfo{ 5229 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5230 }, 5231 }, 5232 }, 5233 { 5234 name: "ANDQconst", 5235 auxType: auxInt32, 5236 argLen: 1, 5237 resultInArg0: true, 5238 clobberFlags: true, 5239 asm: x86.AANDQ, 5240 reg: regInfo{ 5241 inputs: []inputInfo{ 5242 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5243 }, 5244 outputs: []outputInfo{ 5245 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5246 }, 5247 }, 5248 }, 5249 { 5250 name: "ANDLconst", 5251 auxType: auxInt32, 5252 argLen: 1, 5253 resultInArg0: true, 5254 clobberFlags: true, 5255 asm: x86.AANDL, 5256 reg: regInfo{ 5257 inputs: []inputInfo{ 5258 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5259 }, 5260 outputs: []outputInfo{ 5261 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5262 }, 5263 }, 5264 }, 5265 { 5266 name: "ORQ", 5267 argLen: 2, 5268 commutative: true, 5269 resultInArg0: true, 5270 clobberFlags: true, 5271 asm: x86.AORQ, 5272 reg: regInfo{ 5273 inputs: []inputInfo{ 5274 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5275 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5276 }, 5277 outputs: []outputInfo{ 5278 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5279 }, 5280 }, 5281 }, 5282 { 5283 name: "ORL", 5284 argLen: 2, 5285 commutative: true, 5286 resultInArg0: true, 5287 clobberFlags: true, 5288 asm: x86.AORL, 5289 reg: regInfo{ 5290 inputs: []inputInfo{ 5291 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5292 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5293 }, 5294 outputs: []outputInfo{ 5295 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5296 }, 5297 }, 5298 }, 5299 { 5300 name: "ORQconst", 5301 auxType: auxInt32, 5302 argLen: 1, 5303 resultInArg0: true, 5304 clobberFlags: true, 5305 asm: x86.AORQ, 5306 reg: regInfo{ 5307 inputs: []inputInfo{ 5308 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5309 }, 5310 outputs: []outputInfo{ 5311 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5312 }, 5313 }, 5314 }, 5315 { 5316 name: "ORLconst", 5317 auxType: auxInt32, 5318 argLen: 1, 5319 resultInArg0: true, 5320 clobberFlags: true, 5321 asm: x86.AORL, 5322 reg: regInfo{ 5323 inputs: []inputInfo{ 5324 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5325 }, 5326 outputs: []outputInfo{ 5327 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5328 }, 5329 }, 5330 }, 5331 { 5332 name: "XORQ", 5333 argLen: 2, 5334 commutative: true, 5335 resultInArg0: true, 5336 clobberFlags: true, 5337 asm: x86.AXORQ, 5338 reg: regInfo{ 5339 inputs: []inputInfo{ 5340 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5341 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5342 }, 5343 outputs: []outputInfo{ 5344 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5345 }, 5346 }, 5347 }, 5348 { 5349 name: "XORL", 5350 argLen: 2, 5351 commutative: true, 5352 resultInArg0: true, 5353 clobberFlags: true, 5354 asm: x86.AXORL, 5355 reg: regInfo{ 5356 inputs: []inputInfo{ 5357 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5358 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5359 }, 5360 outputs: []outputInfo{ 5361 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5362 }, 5363 }, 5364 }, 5365 { 5366 name: "XORQconst", 5367 auxType: auxInt32, 5368 argLen: 1, 5369 resultInArg0: true, 5370 clobberFlags: true, 5371 asm: x86.AXORQ, 5372 reg: regInfo{ 5373 inputs: []inputInfo{ 5374 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5375 }, 5376 outputs: []outputInfo{ 5377 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5378 }, 5379 }, 5380 }, 5381 { 5382 name: "XORLconst", 5383 auxType: auxInt32, 5384 argLen: 1, 5385 resultInArg0: true, 5386 clobberFlags: true, 5387 asm: x86.AXORL, 5388 reg: regInfo{ 5389 inputs: []inputInfo{ 5390 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5391 }, 5392 outputs: []outputInfo{ 5393 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5394 }, 5395 }, 5396 }, 5397 { 5398 name: "CMPQ", 5399 argLen: 2, 5400 asm: x86.ACMPQ, 5401 reg: regInfo{ 5402 inputs: []inputInfo{ 5403 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5404 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5405 }, 5406 }, 5407 }, 5408 { 5409 name: "CMPL", 5410 argLen: 2, 5411 asm: x86.ACMPL, 5412 reg: regInfo{ 5413 inputs: []inputInfo{ 5414 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5415 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5416 }, 5417 }, 5418 }, 5419 { 5420 name: "CMPW", 5421 argLen: 2, 5422 asm: x86.ACMPW, 5423 reg: regInfo{ 5424 inputs: []inputInfo{ 5425 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5426 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5427 }, 5428 }, 5429 }, 5430 { 5431 name: "CMPB", 5432 argLen: 2, 5433 asm: x86.ACMPB, 5434 reg: regInfo{ 5435 inputs: []inputInfo{ 5436 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5437 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5438 }, 5439 }, 5440 }, 5441 { 5442 name: "CMPQconst", 5443 auxType: auxInt32, 5444 argLen: 1, 5445 asm: x86.ACMPQ, 5446 reg: regInfo{ 5447 inputs: []inputInfo{ 5448 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5449 }, 5450 }, 5451 }, 5452 { 5453 name: "CMPLconst", 5454 auxType: auxInt32, 5455 argLen: 1, 5456 asm: x86.ACMPL, 5457 reg: regInfo{ 5458 inputs: []inputInfo{ 5459 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5460 }, 5461 }, 5462 }, 5463 { 5464 name: "CMPWconst", 5465 auxType: auxInt16, 5466 argLen: 1, 5467 asm: x86.ACMPW, 5468 reg: regInfo{ 5469 inputs: []inputInfo{ 5470 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5471 }, 5472 }, 5473 }, 5474 { 5475 name: "CMPBconst", 5476 auxType: auxInt8, 5477 argLen: 1, 5478 asm: x86.ACMPB, 5479 reg: regInfo{ 5480 inputs: []inputInfo{ 5481 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5482 }, 5483 }, 5484 }, 5485 { 5486 name: "UCOMISS", 5487 argLen: 2, 5488 asm: x86.AUCOMISS, 5489 reg: regInfo{ 5490 inputs: []inputInfo{ 5491 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5492 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5493 }, 5494 }, 5495 }, 5496 { 5497 name: "UCOMISD", 5498 argLen: 2, 5499 asm: x86.AUCOMISD, 5500 reg: regInfo{ 5501 inputs: []inputInfo{ 5502 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5503 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5504 }, 5505 }, 5506 }, 5507 { 5508 name: "BTL", 5509 argLen: 2, 5510 asm: x86.ABTL, 5511 reg: regInfo{ 5512 inputs: []inputInfo{ 5513 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5514 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5515 }, 5516 }, 5517 }, 5518 { 5519 name: "BTQ", 5520 argLen: 2, 5521 asm: x86.ABTQ, 5522 reg: regInfo{ 5523 inputs: []inputInfo{ 5524 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5525 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5526 }, 5527 }, 5528 }, 5529 { 5530 name: "BTLconst", 5531 auxType: auxInt8, 5532 argLen: 1, 5533 asm: x86.ABTL, 5534 reg: regInfo{ 5535 inputs: []inputInfo{ 5536 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5537 }, 5538 }, 5539 }, 5540 { 5541 name: "BTQconst", 5542 auxType: auxInt8, 5543 argLen: 1, 5544 asm: x86.ABTQ, 5545 reg: regInfo{ 5546 inputs: []inputInfo{ 5547 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5548 }, 5549 }, 5550 }, 5551 { 5552 name: "TESTQ", 5553 argLen: 2, 5554 commutative: true, 5555 asm: x86.ATESTQ, 5556 reg: regInfo{ 5557 inputs: []inputInfo{ 5558 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5559 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5560 }, 5561 }, 5562 }, 5563 { 5564 name: "TESTL", 5565 argLen: 2, 5566 commutative: true, 5567 asm: x86.ATESTL, 5568 reg: regInfo{ 5569 inputs: []inputInfo{ 5570 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5571 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5572 }, 5573 }, 5574 }, 5575 { 5576 name: "TESTW", 5577 argLen: 2, 5578 commutative: true, 5579 asm: x86.ATESTW, 5580 reg: regInfo{ 5581 inputs: []inputInfo{ 5582 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5583 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5584 }, 5585 }, 5586 }, 5587 { 5588 name: "TESTB", 5589 argLen: 2, 5590 commutative: true, 5591 asm: x86.ATESTB, 5592 reg: regInfo{ 5593 inputs: []inputInfo{ 5594 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5595 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5596 }, 5597 }, 5598 }, 5599 { 5600 name: "TESTQconst", 5601 auxType: auxInt32, 5602 argLen: 1, 5603 asm: x86.ATESTQ, 5604 reg: regInfo{ 5605 inputs: []inputInfo{ 5606 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5607 }, 5608 }, 5609 }, 5610 { 5611 name: "TESTLconst", 5612 auxType: auxInt32, 5613 argLen: 1, 5614 asm: x86.ATESTL, 5615 reg: regInfo{ 5616 inputs: []inputInfo{ 5617 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5618 }, 5619 }, 5620 }, 5621 { 5622 name: "TESTWconst", 5623 auxType: auxInt16, 5624 argLen: 1, 5625 asm: x86.ATESTW, 5626 reg: regInfo{ 5627 inputs: []inputInfo{ 5628 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5629 }, 5630 }, 5631 }, 5632 { 5633 name: "TESTBconst", 5634 auxType: auxInt8, 5635 argLen: 1, 5636 asm: x86.ATESTB, 5637 reg: regInfo{ 5638 inputs: []inputInfo{ 5639 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5640 }, 5641 }, 5642 }, 5643 { 5644 name: "SHLQ", 5645 argLen: 2, 5646 resultInArg0: true, 5647 clobberFlags: true, 5648 asm: x86.ASHLQ, 5649 reg: regInfo{ 5650 inputs: []inputInfo{ 5651 {1, 2}, // CX 5652 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5653 }, 5654 outputs: []outputInfo{ 5655 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5656 }, 5657 }, 5658 }, 5659 { 5660 name: "SHLL", 5661 argLen: 2, 5662 resultInArg0: true, 5663 clobberFlags: true, 5664 asm: x86.ASHLL, 5665 reg: regInfo{ 5666 inputs: []inputInfo{ 5667 {1, 2}, // CX 5668 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5669 }, 5670 outputs: []outputInfo{ 5671 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5672 }, 5673 }, 5674 }, 5675 { 5676 name: "SHLQconst", 5677 auxType: auxInt8, 5678 argLen: 1, 5679 resultInArg0: true, 5680 clobberFlags: true, 5681 asm: x86.ASHLQ, 5682 reg: regInfo{ 5683 inputs: []inputInfo{ 5684 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5685 }, 5686 outputs: []outputInfo{ 5687 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5688 }, 5689 }, 5690 }, 5691 { 5692 name: "SHLLconst", 5693 auxType: auxInt8, 5694 argLen: 1, 5695 resultInArg0: true, 5696 clobberFlags: true, 5697 asm: x86.ASHLL, 5698 reg: regInfo{ 5699 inputs: []inputInfo{ 5700 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5701 }, 5702 outputs: []outputInfo{ 5703 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5704 }, 5705 }, 5706 }, 5707 { 5708 name: "SHRQ", 5709 argLen: 2, 5710 resultInArg0: true, 5711 clobberFlags: true, 5712 asm: x86.ASHRQ, 5713 reg: regInfo{ 5714 inputs: []inputInfo{ 5715 {1, 2}, // CX 5716 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5717 }, 5718 outputs: []outputInfo{ 5719 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5720 }, 5721 }, 5722 }, 5723 { 5724 name: "SHRL", 5725 argLen: 2, 5726 resultInArg0: true, 5727 clobberFlags: true, 5728 asm: x86.ASHRL, 5729 reg: regInfo{ 5730 inputs: []inputInfo{ 5731 {1, 2}, // CX 5732 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5733 }, 5734 outputs: []outputInfo{ 5735 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5736 }, 5737 }, 5738 }, 5739 { 5740 name: "SHRW", 5741 argLen: 2, 5742 resultInArg0: true, 5743 clobberFlags: true, 5744 asm: x86.ASHRW, 5745 reg: regInfo{ 5746 inputs: []inputInfo{ 5747 {1, 2}, // CX 5748 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5749 }, 5750 outputs: []outputInfo{ 5751 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5752 }, 5753 }, 5754 }, 5755 { 5756 name: "SHRB", 5757 argLen: 2, 5758 resultInArg0: true, 5759 clobberFlags: true, 5760 asm: x86.ASHRB, 5761 reg: regInfo{ 5762 inputs: []inputInfo{ 5763 {1, 2}, // CX 5764 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5765 }, 5766 outputs: []outputInfo{ 5767 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5768 }, 5769 }, 5770 }, 5771 { 5772 name: "SHRQconst", 5773 auxType: auxInt8, 5774 argLen: 1, 5775 resultInArg0: true, 5776 clobberFlags: true, 5777 asm: x86.ASHRQ, 5778 reg: regInfo{ 5779 inputs: []inputInfo{ 5780 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5781 }, 5782 outputs: []outputInfo{ 5783 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5784 }, 5785 }, 5786 }, 5787 { 5788 name: "SHRLconst", 5789 auxType: auxInt8, 5790 argLen: 1, 5791 resultInArg0: true, 5792 clobberFlags: true, 5793 asm: x86.ASHRL, 5794 reg: regInfo{ 5795 inputs: []inputInfo{ 5796 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5797 }, 5798 outputs: []outputInfo{ 5799 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5800 }, 5801 }, 5802 }, 5803 { 5804 name: "SHRWconst", 5805 auxType: auxInt8, 5806 argLen: 1, 5807 resultInArg0: true, 5808 clobberFlags: true, 5809 asm: x86.ASHRW, 5810 reg: regInfo{ 5811 inputs: []inputInfo{ 5812 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5813 }, 5814 outputs: []outputInfo{ 5815 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5816 }, 5817 }, 5818 }, 5819 { 5820 name: "SHRBconst", 5821 auxType: auxInt8, 5822 argLen: 1, 5823 resultInArg0: true, 5824 clobberFlags: true, 5825 asm: x86.ASHRB, 5826 reg: regInfo{ 5827 inputs: []inputInfo{ 5828 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5829 }, 5830 outputs: []outputInfo{ 5831 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5832 }, 5833 }, 5834 }, 5835 { 5836 name: "SARQ", 5837 argLen: 2, 5838 resultInArg0: true, 5839 clobberFlags: true, 5840 asm: x86.ASARQ, 5841 reg: regInfo{ 5842 inputs: []inputInfo{ 5843 {1, 2}, // CX 5844 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5845 }, 5846 outputs: []outputInfo{ 5847 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5848 }, 5849 }, 5850 }, 5851 { 5852 name: "SARL", 5853 argLen: 2, 5854 resultInArg0: true, 5855 clobberFlags: true, 5856 asm: x86.ASARL, 5857 reg: regInfo{ 5858 inputs: []inputInfo{ 5859 {1, 2}, // CX 5860 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5861 }, 5862 outputs: []outputInfo{ 5863 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5864 }, 5865 }, 5866 }, 5867 { 5868 name: "SARW", 5869 argLen: 2, 5870 resultInArg0: true, 5871 clobberFlags: true, 5872 asm: x86.ASARW, 5873 reg: regInfo{ 5874 inputs: []inputInfo{ 5875 {1, 2}, // CX 5876 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5877 }, 5878 outputs: []outputInfo{ 5879 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5880 }, 5881 }, 5882 }, 5883 { 5884 name: "SARB", 5885 argLen: 2, 5886 resultInArg0: true, 5887 clobberFlags: true, 5888 asm: x86.ASARB, 5889 reg: regInfo{ 5890 inputs: []inputInfo{ 5891 {1, 2}, // CX 5892 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5893 }, 5894 outputs: []outputInfo{ 5895 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5896 }, 5897 }, 5898 }, 5899 { 5900 name: "SARQconst", 5901 auxType: auxInt8, 5902 argLen: 1, 5903 resultInArg0: true, 5904 clobberFlags: true, 5905 asm: x86.ASARQ, 5906 reg: regInfo{ 5907 inputs: []inputInfo{ 5908 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5909 }, 5910 outputs: []outputInfo{ 5911 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5912 }, 5913 }, 5914 }, 5915 { 5916 name: "SARLconst", 5917 auxType: auxInt8, 5918 argLen: 1, 5919 resultInArg0: true, 5920 clobberFlags: true, 5921 asm: x86.ASARL, 5922 reg: regInfo{ 5923 inputs: []inputInfo{ 5924 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5925 }, 5926 outputs: []outputInfo{ 5927 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5928 }, 5929 }, 5930 }, 5931 { 5932 name: "SARWconst", 5933 auxType: auxInt8, 5934 argLen: 1, 5935 resultInArg0: true, 5936 clobberFlags: true, 5937 asm: x86.ASARW, 5938 reg: regInfo{ 5939 inputs: []inputInfo{ 5940 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5941 }, 5942 outputs: []outputInfo{ 5943 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5944 }, 5945 }, 5946 }, 5947 { 5948 name: "SARBconst", 5949 auxType: auxInt8, 5950 argLen: 1, 5951 resultInArg0: true, 5952 clobberFlags: true, 5953 asm: x86.ASARB, 5954 reg: regInfo{ 5955 inputs: []inputInfo{ 5956 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5957 }, 5958 outputs: []outputInfo{ 5959 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5960 }, 5961 }, 5962 }, 5963 { 5964 name: "ROLQ", 5965 argLen: 2, 5966 resultInArg0: true, 5967 clobberFlags: true, 5968 asm: x86.AROLQ, 5969 reg: regInfo{ 5970 inputs: []inputInfo{ 5971 {1, 2}, // CX 5972 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5973 }, 5974 outputs: []outputInfo{ 5975 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5976 }, 5977 }, 5978 }, 5979 { 5980 name: "ROLL", 5981 argLen: 2, 5982 resultInArg0: true, 5983 clobberFlags: true, 5984 asm: x86.AROLL, 5985 reg: regInfo{ 5986 inputs: []inputInfo{ 5987 {1, 2}, // CX 5988 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5989 }, 5990 outputs: []outputInfo{ 5991 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5992 }, 5993 }, 5994 }, 5995 { 5996 name: "ROLW", 5997 argLen: 2, 5998 resultInArg0: true, 5999 clobberFlags: true, 6000 asm: x86.AROLW, 6001 reg: regInfo{ 6002 inputs: []inputInfo{ 6003 {1, 2}, // CX 6004 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6005 }, 6006 outputs: []outputInfo{ 6007 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6008 }, 6009 }, 6010 }, 6011 { 6012 name: "ROLB", 6013 argLen: 2, 6014 resultInArg0: true, 6015 clobberFlags: true, 6016 asm: x86.AROLB, 6017 reg: regInfo{ 6018 inputs: []inputInfo{ 6019 {1, 2}, // CX 6020 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6021 }, 6022 outputs: []outputInfo{ 6023 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6024 }, 6025 }, 6026 }, 6027 { 6028 name: "RORQ", 6029 argLen: 2, 6030 resultInArg0: true, 6031 clobberFlags: true, 6032 asm: x86.ARORQ, 6033 reg: regInfo{ 6034 inputs: []inputInfo{ 6035 {1, 2}, // CX 6036 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6037 }, 6038 outputs: []outputInfo{ 6039 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6040 }, 6041 }, 6042 }, 6043 { 6044 name: "RORL", 6045 argLen: 2, 6046 resultInArg0: true, 6047 clobberFlags: true, 6048 asm: x86.ARORL, 6049 reg: regInfo{ 6050 inputs: []inputInfo{ 6051 {1, 2}, // CX 6052 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6053 }, 6054 outputs: []outputInfo{ 6055 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6056 }, 6057 }, 6058 }, 6059 { 6060 name: "RORW", 6061 argLen: 2, 6062 resultInArg0: true, 6063 clobberFlags: true, 6064 asm: x86.ARORW, 6065 reg: regInfo{ 6066 inputs: []inputInfo{ 6067 {1, 2}, // CX 6068 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6069 }, 6070 outputs: []outputInfo{ 6071 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6072 }, 6073 }, 6074 }, 6075 { 6076 name: "RORB", 6077 argLen: 2, 6078 resultInArg0: true, 6079 clobberFlags: true, 6080 asm: x86.ARORB, 6081 reg: regInfo{ 6082 inputs: []inputInfo{ 6083 {1, 2}, // CX 6084 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6085 }, 6086 outputs: []outputInfo{ 6087 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6088 }, 6089 }, 6090 }, 6091 { 6092 name: "ROLQconst", 6093 auxType: auxInt8, 6094 argLen: 1, 6095 resultInArg0: true, 6096 clobberFlags: true, 6097 asm: x86.AROLQ, 6098 reg: regInfo{ 6099 inputs: []inputInfo{ 6100 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6101 }, 6102 outputs: []outputInfo{ 6103 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6104 }, 6105 }, 6106 }, 6107 { 6108 name: "ROLLconst", 6109 auxType: auxInt8, 6110 argLen: 1, 6111 resultInArg0: true, 6112 clobberFlags: true, 6113 asm: x86.AROLL, 6114 reg: regInfo{ 6115 inputs: []inputInfo{ 6116 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6117 }, 6118 outputs: []outputInfo{ 6119 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6120 }, 6121 }, 6122 }, 6123 { 6124 name: "ROLWconst", 6125 auxType: auxInt8, 6126 argLen: 1, 6127 resultInArg0: true, 6128 clobberFlags: true, 6129 asm: x86.AROLW, 6130 reg: regInfo{ 6131 inputs: []inputInfo{ 6132 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6133 }, 6134 outputs: []outputInfo{ 6135 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6136 }, 6137 }, 6138 }, 6139 { 6140 name: "ROLBconst", 6141 auxType: auxInt8, 6142 argLen: 1, 6143 resultInArg0: true, 6144 clobberFlags: true, 6145 asm: x86.AROLB, 6146 reg: regInfo{ 6147 inputs: []inputInfo{ 6148 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6149 }, 6150 outputs: []outputInfo{ 6151 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6152 }, 6153 }, 6154 }, 6155 { 6156 name: "ADDLmem", 6157 auxType: auxSymOff, 6158 argLen: 3, 6159 resultInArg0: true, 6160 clobberFlags: true, 6161 faultOnNilArg1: true, 6162 symEffect: SymRead, 6163 asm: x86.AADDL, 6164 reg: regInfo{ 6165 inputs: []inputInfo{ 6166 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6167 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6168 }, 6169 outputs: []outputInfo{ 6170 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6171 }, 6172 }, 6173 }, 6174 { 6175 name: "ADDQmem", 6176 auxType: auxSymOff, 6177 argLen: 3, 6178 resultInArg0: true, 6179 clobberFlags: true, 6180 faultOnNilArg1: true, 6181 symEffect: SymRead, 6182 asm: x86.AADDQ, 6183 reg: regInfo{ 6184 inputs: []inputInfo{ 6185 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6186 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6187 }, 6188 outputs: []outputInfo{ 6189 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6190 }, 6191 }, 6192 }, 6193 { 6194 name: "SUBQmem", 6195 auxType: auxSymOff, 6196 argLen: 3, 6197 resultInArg0: true, 6198 clobberFlags: true, 6199 faultOnNilArg1: true, 6200 symEffect: SymRead, 6201 asm: x86.ASUBQ, 6202 reg: regInfo{ 6203 inputs: []inputInfo{ 6204 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6205 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6206 }, 6207 outputs: []outputInfo{ 6208 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6209 }, 6210 }, 6211 }, 6212 { 6213 name: "SUBLmem", 6214 auxType: auxSymOff, 6215 argLen: 3, 6216 resultInArg0: true, 6217 clobberFlags: true, 6218 faultOnNilArg1: true, 6219 symEffect: SymRead, 6220 asm: x86.ASUBL, 6221 reg: regInfo{ 6222 inputs: []inputInfo{ 6223 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6224 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6225 }, 6226 outputs: []outputInfo{ 6227 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6228 }, 6229 }, 6230 }, 6231 { 6232 name: "ANDLmem", 6233 auxType: auxSymOff, 6234 argLen: 3, 6235 resultInArg0: true, 6236 clobberFlags: true, 6237 faultOnNilArg1: true, 6238 symEffect: SymRead, 6239 asm: x86.AANDL, 6240 reg: regInfo{ 6241 inputs: []inputInfo{ 6242 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6243 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6244 }, 6245 outputs: []outputInfo{ 6246 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6247 }, 6248 }, 6249 }, 6250 { 6251 name: "ANDQmem", 6252 auxType: auxSymOff, 6253 argLen: 3, 6254 resultInArg0: true, 6255 clobberFlags: true, 6256 faultOnNilArg1: true, 6257 symEffect: SymRead, 6258 asm: x86.AANDQ, 6259 reg: regInfo{ 6260 inputs: []inputInfo{ 6261 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6262 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6263 }, 6264 outputs: []outputInfo{ 6265 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6266 }, 6267 }, 6268 }, 6269 { 6270 name: "ORQmem", 6271 auxType: auxSymOff, 6272 argLen: 3, 6273 resultInArg0: true, 6274 clobberFlags: true, 6275 faultOnNilArg1: true, 6276 symEffect: SymRead, 6277 asm: x86.AORQ, 6278 reg: regInfo{ 6279 inputs: []inputInfo{ 6280 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6281 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6282 }, 6283 outputs: []outputInfo{ 6284 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6285 }, 6286 }, 6287 }, 6288 { 6289 name: "ORLmem", 6290 auxType: auxSymOff, 6291 argLen: 3, 6292 resultInArg0: true, 6293 clobberFlags: true, 6294 faultOnNilArg1: true, 6295 symEffect: SymRead, 6296 asm: x86.AORL, 6297 reg: regInfo{ 6298 inputs: []inputInfo{ 6299 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6300 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6301 }, 6302 outputs: []outputInfo{ 6303 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6304 }, 6305 }, 6306 }, 6307 { 6308 name: "XORQmem", 6309 auxType: auxSymOff, 6310 argLen: 3, 6311 resultInArg0: true, 6312 clobberFlags: true, 6313 faultOnNilArg1: true, 6314 symEffect: SymRead, 6315 asm: x86.AXORQ, 6316 reg: regInfo{ 6317 inputs: []inputInfo{ 6318 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6319 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6320 }, 6321 outputs: []outputInfo{ 6322 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6323 }, 6324 }, 6325 }, 6326 { 6327 name: "XORLmem", 6328 auxType: auxSymOff, 6329 argLen: 3, 6330 resultInArg0: true, 6331 clobberFlags: true, 6332 faultOnNilArg1: true, 6333 symEffect: SymRead, 6334 asm: x86.AXORL, 6335 reg: regInfo{ 6336 inputs: []inputInfo{ 6337 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6338 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6339 }, 6340 outputs: []outputInfo{ 6341 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6342 }, 6343 }, 6344 }, 6345 { 6346 name: "NEGQ", 6347 argLen: 1, 6348 resultInArg0: true, 6349 clobberFlags: true, 6350 asm: x86.ANEGQ, 6351 reg: regInfo{ 6352 inputs: []inputInfo{ 6353 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6354 }, 6355 outputs: []outputInfo{ 6356 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6357 }, 6358 }, 6359 }, 6360 { 6361 name: "NEGL", 6362 argLen: 1, 6363 resultInArg0: true, 6364 clobberFlags: true, 6365 asm: x86.ANEGL, 6366 reg: regInfo{ 6367 inputs: []inputInfo{ 6368 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6369 }, 6370 outputs: []outputInfo{ 6371 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6372 }, 6373 }, 6374 }, 6375 { 6376 name: "NOTQ", 6377 argLen: 1, 6378 resultInArg0: true, 6379 clobberFlags: true, 6380 asm: x86.ANOTQ, 6381 reg: regInfo{ 6382 inputs: []inputInfo{ 6383 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6384 }, 6385 outputs: []outputInfo{ 6386 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6387 }, 6388 }, 6389 }, 6390 { 6391 name: "NOTL", 6392 argLen: 1, 6393 resultInArg0: true, 6394 clobberFlags: true, 6395 asm: x86.ANOTL, 6396 reg: regInfo{ 6397 inputs: []inputInfo{ 6398 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6399 }, 6400 outputs: []outputInfo{ 6401 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6402 }, 6403 }, 6404 }, 6405 { 6406 name: "BSFQ", 6407 argLen: 1, 6408 asm: x86.ABSFQ, 6409 reg: regInfo{ 6410 inputs: []inputInfo{ 6411 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6412 }, 6413 outputs: []outputInfo{ 6414 {1, 0}, 6415 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6416 }, 6417 }, 6418 }, 6419 { 6420 name: "BSFL", 6421 argLen: 1, 6422 asm: x86.ABSFL, 6423 reg: regInfo{ 6424 inputs: []inputInfo{ 6425 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6426 }, 6427 outputs: []outputInfo{ 6428 {1, 0}, 6429 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6430 }, 6431 }, 6432 }, 6433 { 6434 name: "BSRQ", 6435 argLen: 1, 6436 asm: x86.ABSRQ, 6437 reg: regInfo{ 6438 inputs: []inputInfo{ 6439 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6440 }, 6441 outputs: []outputInfo{ 6442 {1, 0}, 6443 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6444 }, 6445 }, 6446 }, 6447 { 6448 name: "BSRL", 6449 argLen: 1, 6450 asm: x86.ABSRL, 6451 reg: regInfo{ 6452 inputs: []inputInfo{ 6453 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6454 }, 6455 outputs: []outputInfo{ 6456 {1, 0}, 6457 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6458 }, 6459 }, 6460 }, 6461 { 6462 name: "CMOVQEQ", 6463 argLen: 3, 6464 resultInArg0: true, 6465 asm: x86.ACMOVQEQ, 6466 reg: regInfo{ 6467 inputs: []inputInfo{ 6468 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6469 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6470 }, 6471 outputs: []outputInfo{ 6472 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6473 }, 6474 }, 6475 }, 6476 { 6477 name: "CMOVLEQ", 6478 argLen: 3, 6479 resultInArg0: true, 6480 asm: x86.ACMOVLEQ, 6481 reg: regInfo{ 6482 inputs: []inputInfo{ 6483 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6484 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6485 }, 6486 outputs: []outputInfo{ 6487 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6488 }, 6489 }, 6490 }, 6491 { 6492 name: "BSWAPQ", 6493 argLen: 1, 6494 resultInArg0: true, 6495 clobberFlags: true, 6496 asm: x86.ABSWAPQ, 6497 reg: regInfo{ 6498 inputs: []inputInfo{ 6499 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6500 }, 6501 outputs: []outputInfo{ 6502 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6503 }, 6504 }, 6505 }, 6506 { 6507 name: "BSWAPL", 6508 argLen: 1, 6509 resultInArg0: true, 6510 clobberFlags: true, 6511 asm: x86.ABSWAPL, 6512 reg: regInfo{ 6513 inputs: []inputInfo{ 6514 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6515 }, 6516 outputs: []outputInfo{ 6517 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6518 }, 6519 }, 6520 }, 6521 { 6522 name: "POPCNTQ", 6523 argLen: 1, 6524 clobberFlags: true, 6525 asm: x86.APOPCNTQ, 6526 reg: regInfo{ 6527 inputs: []inputInfo{ 6528 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6529 }, 6530 outputs: []outputInfo{ 6531 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6532 }, 6533 }, 6534 }, 6535 { 6536 name: "POPCNTL", 6537 argLen: 1, 6538 clobberFlags: true, 6539 asm: x86.APOPCNTL, 6540 reg: regInfo{ 6541 inputs: []inputInfo{ 6542 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6543 }, 6544 outputs: []outputInfo{ 6545 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6546 }, 6547 }, 6548 }, 6549 { 6550 name: "SQRTSD", 6551 argLen: 1, 6552 asm: x86.ASQRTSD, 6553 reg: regInfo{ 6554 inputs: []inputInfo{ 6555 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6556 }, 6557 outputs: []outputInfo{ 6558 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6559 }, 6560 }, 6561 }, 6562 { 6563 name: "SBBQcarrymask", 6564 argLen: 1, 6565 asm: x86.ASBBQ, 6566 reg: regInfo{ 6567 outputs: []outputInfo{ 6568 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6569 }, 6570 }, 6571 }, 6572 { 6573 name: "SBBLcarrymask", 6574 argLen: 1, 6575 asm: x86.ASBBL, 6576 reg: regInfo{ 6577 outputs: []outputInfo{ 6578 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6579 }, 6580 }, 6581 }, 6582 { 6583 name: "SETEQ", 6584 argLen: 1, 6585 asm: x86.ASETEQ, 6586 reg: regInfo{ 6587 outputs: []outputInfo{ 6588 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6589 }, 6590 }, 6591 }, 6592 { 6593 name: "SETNE", 6594 argLen: 1, 6595 asm: x86.ASETNE, 6596 reg: regInfo{ 6597 outputs: []outputInfo{ 6598 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6599 }, 6600 }, 6601 }, 6602 { 6603 name: "SETL", 6604 argLen: 1, 6605 asm: x86.ASETLT, 6606 reg: regInfo{ 6607 outputs: []outputInfo{ 6608 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6609 }, 6610 }, 6611 }, 6612 { 6613 name: "SETLE", 6614 argLen: 1, 6615 asm: x86.ASETLE, 6616 reg: regInfo{ 6617 outputs: []outputInfo{ 6618 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6619 }, 6620 }, 6621 }, 6622 { 6623 name: "SETG", 6624 argLen: 1, 6625 asm: x86.ASETGT, 6626 reg: regInfo{ 6627 outputs: []outputInfo{ 6628 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6629 }, 6630 }, 6631 }, 6632 { 6633 name: "SETGE", 6634 argLen: 1, 6635 asm: x86.ASETGE, 6636 reg: regInfo{ 6637 outputs: []outputInfo{ 6638 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6639 }, 6640 }, 6641 }, 6642 { 6643 name: "SETB", 6644 argLen: 1, 6645 asm: x86.ASETCS, 6646 reg: regInfo{ 6647 outputs: []outputInfo{ 6648 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6649 }, 6650 }, 6651 }, 6652 { 6653 name: "SETBE", 6654 argLen: 1, 6655 asm: x86.ASETLS, 6656 reg: regInfo{ 6657 outputs: []outputInfo{ 6658 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6659 }, 6660 }, 6661 }, 6662 { 6663 name: "SETA", 6664 argLen: 1, 6665 asm: x86.ASETHI, 6666 reg: regInfo{ 6667 outputs: []outputInfo{ 6668 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6669 }, 6670 }, 6671 }, 6672 { 6673 name: "SETAE", 6674 argLen: 1, 6675 asm: x86.ASETCC, 6676 reg: regInfo{ 6677 outputs: []outputInfo{ 6678 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6679 }, 6680 }, 6681 }, 6682 { 6683 name: "SETEQF", 6684 argLen: 1, 6685 clobberFlags: true, 6686 asm: x86.ASETEQ, 6687 reg: regInfo{ 6688 clobbers: 1, // AX 6689 outputs: []outputInfo{ 6690 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6691 }, 6692 }, 6693 }, 6694 { 6695 name: "SETNEF", 6696 argLen: 1, 6697 clobberFlags: true, 6698 asm: x86.ASETNE, 6699 reg: regInfo{ 6700 clobbers: 1, // AX 6701 outputs: []outputInfo{ 6702 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6703 }, 6704 }, 6705 }, 6706 { 6707 name: "SETORD", 6708 argLen: 1, 6709 asm: x86.ASETPC, 6710 reg: regInfo{ 6711 outputs: []outputInfo{ 6712 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6713 }, 6714 }, 6715 }, 6716 { 6717 name: "SETNAN", 6718 argLen: 1, 6719 asm: x86.ASETPS, 6720 reg: regInfo{ 6721 outputs: []outputInfo{ 6722 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6723 }, 6724 }, 6725 }, 6726 { 6727 name: "SETGF", 6728 argLen: 1, 6729 asm: x86.ASETHI, 6730 reg: regInfo{ 6731 outputs: []outputInfo{ 6732 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6733 }, 6734 }, 6735 }, 6736 { 6737 name: "SETGEF", 6738 argLen: 1, 6739 asm: x86.ASETCC, 6740 reg: regInfo{ 6741 outputs: []outputInfo{ 6742 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6743 }, 6744 }, 6745 }, 6746 { 6747 name: "MOVBQSX", 6748 argLen: 1, 6749 asm: x86.AMOVBQSX, 6750 reg: regInfo{ 6751 inputs: []inputInfo{ 6752 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6753 }, 6754 outputs: []outputInfo{ 6755 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6756 }, 6757 }, 6758 }, 6759 { 6760 name: "MOVBQZX", 6761 argLen: 1, 6762 asm: x86.AMOVBLZX, 6763 reg: regInfo{ 6764 inputs: []inputInfo{ 6765 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6766 }, 6767 outputs: []outputInfo{ 6768 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6769 }, 6770 }, 6771 }, 6772 { 6773 name: "MOVWQSX", 6774 argLen: 1, 6775 asm: x86.AMOVWQSX, 6776 reg: regInfo{ 6777 inputs: []inputInfo{ 6778 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6779 }, 6780 outputs: []outputInfo{ 6781 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6782 }, 6783 }, 6784 }, 6785 { 6786 name: "MOVWQZX", 6787 argLen: 1, 6788 asm: x86.AMOVWLZX, 6789 reg: regInfo{ 6790 inputs: []inputInfo{ 6791 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6792 }, 6793 outputs: []outputInfo{ 6794 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6795 }, 6796 }, 6797 }, 6798 { 6799 name: "MOVLQSX", 6800 argLen: 1, 6801 asm: x86.AMOVLQSX, 6802 reg: regInfo{ 6803 inputs: []inputInfo{ 6804 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6805 }, 6806 outputs: []outputInfo{ 6807 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6808 }, 6809 }, 6810 }, 6811 { 6812 name: "MOVLQZX", 6813 argLen: 1, 6814 asm: x86.AMOVL, 6815 reg: regInfo{ 6816 inputs: []inputInfo{ 6817 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6818 }, 6819 outputs: []outputInfo{ 6820 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6821 }, 6822 }, 6823 }, 6824 { 6825 name: "MOVLconst", 6826 auxType: auxInt32, 6827 argLen: 0, 6828 rematerializeable: true, 6829 asm: x86.AMOVL, 6830 reg: regInfo{ 6831 outputs: []outputInfo{ 6832 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6833 }, 6834 }, 6835 }, 6836 { 6837 name: "MOVQconst", 6838 auxType: auxInt64, 6839 argLen: 0, 6840 rematerializeable: true, 6841 asm: x86.AMOVQ, 6842 reg: regInfo{ 6843 outputs: []outputInfo{ 6844 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6845 }, 6846 }, 6847 }, 6848 { 6849 name: "CVTTSD2SL", 6850 argLen: 1, 6851 asm: x86.ACVTTSD2SL, 6852 reg: regInfo{ 6853 inputs: []inputInfo{ 6854 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6855 }, 6856 outputs: []outputInfo{ 6857 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6858 }, 6859 }, 6860 }, 6861 { 6862 name: "CVTTSD2SQ", 6863 argLen: 1, 6864 asm: x86.ACVTTSD2SQ, 6865 reg: regInfo{ 6866 inputs: []inputInfo{ 6867 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6868 }, 6869 outputs: []outputInfo{ 6870 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6871 }, 6872 }, 6873 }, 6874 { 6875 name: "CVTTSS2SL", 6876 argLen: 1, 6877 asm: x86.ACVTTSS2SL, 6878 reg: regInfo{ 6879 inputs: []inputInfo{ 6880 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6881 }, 6882 outputs: []outputInfo{ 6883 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6884 }, 6885 }, 6886 }, 6887 { 6888 name: "CVTTSS2SQ", 6889 argLen: 1, 6890 asm: x86.ACVTTSS2SQ, 6891 reg: regInfo{ 6892 inputs: []inputInfo{ 6893 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6894 }, 6895 outputs: []outputInfo{ 6896 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6897 }, 6898 }, 6899 }, 6900 { 6901 name: "CVTSL2SS", 6902 argLen: 1, 6903 asm: x86.ACVTSL2SS, 6904 reg: regInfo{ 6905 inputs: []inputInfo{ 6906 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6907 }, 6908 outputs: []outputInfo{ 6909 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6910 }, 6911 }, 6912 }, 6913 { 6914 name: "CVTSL2SD", 6915 argLen: 1, 6916 asm: x86.ACVTSL2SD, 6917 reg: regInfo{ 6918 inputs: []inputInfo{ 6919 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6920 }, 6921 outputs: []outputInfo{ 6922 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6923 }, 6924 }, 6925 }, 6926 { 6927 name: "CVTSQ2SS", 6928 argLen: 1, 6929 asm: x86.ACVTSQ2SS, 6930 reg: regInfo{ 6931 inputs: []inputInfo{ 6932 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6933 }, 6934 outputs: []outputInfo{ 6935 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6936 }, 6937 }, 6938 }, 6939 { 6940 name: "CVTSQ2SD", 6941 argLen: 1, 6942 asm: x86.ACVTSQ2SD, 6943 reg: regInfo{ 6944 inputs: []inputInfo{ 6945 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6946 }, 6947 outputs: []outputInfo{ 6948 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6949 }, 6950 }, 6951 }, 6952 { 6953 name: "CVTSD2SS", 6954 argLen: 1, 6955 asm: x86.ACVTSD2SS, 6956 reg: regInfo{ 6957 inputs: []inputInfo{ 6958 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6959 }, 6960 outputs: []outputInfo{ 6961 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6962 }, 6963 }, 6964 }, 6965 { 6966 name: "CVTSS2SD", 6967 argLen: 1, 6968 asm: x86.ACVTSS2SD, 6969 reg: regInfo{ 6970 inputs: []inputInfo{ 6971 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6972 }, 6973 outputs: []outputInfo{ 6974 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6975 }, 6976 }, 6977 }, 6978 { 6979 name: "PXOR", 6980 argLen: 2, 6981 commutative: true, 6982 resultInArg0: true, 6983 asm: x86.APXOR, 6984 reg: regInfo{ 6985 inputs: []inputInfo{ 6986 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6987 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6988 }, 6989 outputs: []outputInfo{ 6990 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6991 }, 6992 }, 6993 }, 6994 { 6995 name: "LEAQ", 6996 auxType: auxSymOff, 6997 argLen: 1, 6998 rematerializeable: true, 6999 symEffect: SymAddr, 7000 asm: x86.ALEAQ, 7001 reg: regInfo{ 7002 inputs: []inputInfo{ 7003 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7004 }, 7005 outputs: []outputInfo{ 7006 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7007 }, 7008 }, 7009 }, 7010 { 7011 name: "LEAQ1", 7012 auxType: auxSymOff, 7013 argLen: 2, 7014 commutative: true, 7015 symEffect: SymAddr, 7016 reg: regInfo{ 7017 inputs: []inputInfo{ 7018 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7019 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7020 }, 7021 outputs: []outputInfo{ 7022 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7023 }, 7024 }, 7025 }, 7026 { 7027 name: "LEAQ2", 7028 auxType: auxSymOff, 7029 argLen: 2, 7030 symEffect: SymAddr, 7031 reg: regInfo{ 7032 inputs: []inputInfo{ 7033 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7034 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7035 }, 7036 outputs: []outputInfo{ 7037 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7038 }, 7039 }, 7040 }, 7041 { 7042 name: "LEAQ4", 7043 auxType: auxSymOff, 7044 argLen: 2, 7045 symEffect: SymAddr, 7046 reg: regInfo{ 7047 inputs: []inputInfo{ 7048 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7049 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7050 }, 7051 outputs: []outputInfo{ 7052 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7053 }, 7054 }, 7055 }, 7056 { 7057 name: "LEAQ8", 7058 auxType: auxSymOff, 7059 argLen: 2, 7060 symEffect: SymAddr, 7061 reg: regInfo{ 7062 inputs: []inputInfo{ 7063 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7064 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7065 }, 7066 outputs: []outputInfo{ 7067 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7068 }, 7069 }, 7070 }, 7071 { 7072 name: "LEAL", 7073 auxType: auxSymOff, 7074 argLen: 1, 7075 rematerializeable: true, 7076 symEffect: SymAddr, 7077 asm: x86.ALEAL, 7078 reg: regInfo{ 7079 inputs: []inputInfo{ 7080 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7081 }, 7082 outputs: []outputInfo{ 7083 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7084 }, 7085 }, 7086 }, 7087 { 7088 name: "MOVBload", 7089 auxType: auxSymOff, 7090 argLen: 2, 7091 faultOnNilArg0: true, 7092 symEffect: SymRead, 7093 asm: x86.AMOVBLZX, 7094 reg: regInfo{ 7095 inputs: []inputInfo{ 7096 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7097 }, 7098 outputs: []outputInfo{ 7099 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7100 }, 7101 }, 7102 }, 7103 { 7104 name: "MOVBQSXload", 7105 auxType: auxSymOff, 7106 argLen: 2, 7107 faultOnNilArg0: true, 7108 symEffect: SymRead, 7109 asm: x86.AMOVBQSX, 7110 reg: regInfo{ 7111 inputs: []inputInfo{ 7112 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7113 }, 7114 outputs: []outputInfo{ 7115 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7116 }, 7117 }, 7118 }, 7119 { 7120 name: "MOVWload", 7121 auxType: auxSymOff, 7122 argLen: 2, 7123 faultOnNilArg0: true, 7124 symEffect: SymRead, 7125 asm: x86.AMOVWLZX, 7126 reg: regInfo{ 7127 inputs: []inputInfo{ 7128 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7129 }, 7130 outputs: []outputInfo{ 7131 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7132 }, 7133 }, 7134 }, 7135 { 7136 name: "MOVWQSXload", 7137 auxType: auxSymOff, 7138 argLen: 2, 7139 faultOnNilArg0: true, 7140 symEffect: SymRead, 7141 asm: x86.AMOVWQSX, 7142 reg: regInfo{ 7143 inputs: []inputInfo{ 7144 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7145 }, 7146 outputs: []outputInfo{ 7147 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7148 }, 7149 }, 7150 }, 7151 { 7152 name: "MOVLload", 7153 auxType: auxSymOff, 7154 argLen: 2, 7155 faultOnNilArg0: true, 7156 symEffect: SymRead, 7157 asm: x86.AMOVL, 7158 reg: regInfo{ 7159 inputs: []inputInfo{ 7160 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7161 }, 7162 outputs: []outputInfo{ 7163 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7164 }, 7165 }, 7166 }, 7167 { 7168 name: "MOVLQSXload", 7169 auxType: auxSymOff, 7170 argLen: 2, 7171 faultOnNilArg0: true, 7172 symEffect: SymRead, 7173 asm: x86.AMOVLQSX, 7174 reg: regInfo{ 7175 inputs: []inputInfo{ 7176 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7177 }, 7178 outputs: []outputInfo{ 7179 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7180 }, 7181 }, 7182 }, 7183 { 7184 name: "MOVQload", 7185 auxType: auxSymOff, 7186 argLen: 2, 7187 faultOnNilArg0: true, 7188 symEffect: SymRead, 7189 asm: x86.AMOVQ, 7190 reg: regInfo{ 7191 inputs: []inputInfo{ 7192 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7193 }, 7194 outputs: []outputInfo{ 7195 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7196 }, 7197 }, 7198 }, 7199 { 7200 name: "MOVBstore", 7201 auxType: auxSymOff, 7202 argLen: 3, 7203 faultOnNilArg0: true, 7204 symEffect: SymWrite, 7205 asm: x86.AMOVB, 7206 reg: regInfo{ 7207 inputs: []inputInfo{ 7208 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7209 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7210 }, 7211 }, 7212 }, 7213 { 7214 name: "MOVWstore", 7215 auxType: auxSymOff, 7216 argLen: 3, 7217 faultOnNilArg0: true, 7218 symEffect: SymWrite, 7219 asm: x86.AMOVW, 7220 reg: regInfo{ 7221 inputs: []inputInfo{ 7222 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7223 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7224 }, 7225 }, 7226 }, 7227 { 7228 name: "MOVLstore", 7229 auxType: auxSymOff, 7230 argLen: 3, 7231 faultOnNilArg0: true, 7232 symEffect: SymWrite, 7233 asm: x86.AMOVL, 7234 reg: regInfo{ 7235 inputs: []inputInfo{ 7236 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7237 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7238 }, 7239 }, 7240 }, 7241 { 7242 name: "MOVQstore", 7243 auxType: auxSymOff, 7244 argLen: 3, 7245 faultOnNilArg0: true, 7246 symEffect: SymWrite, 7247 asm: x86.AMOVQ, 7248 reg: regInfo{ 7249 inputs: []inputInfo{ 7250 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7251 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7252 }, 7253 }, 7254 }, 7255 { 7256 name: "MOVOload", 7257 auxType: auxSymOff, 7258 argLen: 2, 7259 faultOnNilArg0: true, 7260 symEffect: SymRead, 7261 asm: x86.AMOVUPS, 7262 reg: regInfo{ 7263 inputs: []inputInfo{ 7264 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7265 }, 7266 outputs: []outputInfo{ 7267 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7268 }, 7269 }, 7270 }, 7271 { 7272 name: "MOVOstore", 7273 auxType: auxSymOff, 7274 argLen: 3, 7275 faultOnNilArg0: true, 7276 symEffect: SymWrite, 7277 asm: x86.AMOVUPS, 7278 reg: regInfo{ 7279 inputs: []inputInfo{ 7280 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7281 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7282 }, 7283 }, 7284 }, 7285 { 7286 name: "MOVBloadidx1", 7287 auxType: auxSymOff, 7288 argLen: 3, 7289 commutative: true, 7290 symEffect: SymRead, 7291 asm: x86.AMOVBLZX, 7292 reg: regInfo{ 7293 inputs: []inputInfo{ 7294 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7295 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7296 }, 7297 outputs: []outputInfo{ 7298 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7299 }, 7300 }, 7301 }, 7302 { 7303 name: "MOVWloadidx1", 7304 auxType: auxSymOff, 7305 argLen: 3, 7306 commutative: true, 7307 symEffect: SymRead, 7308 asm: x86.AMOVWLZX, 7309 reg: regInfo{ 7310 inputs: []inputInfo{ 7311 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7312 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7313 }, 7314 outputs: []outputInfo{ 7315 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7316 }, 7317 }, 7318 }, 7319 { 7320 name: "MOVWloadidx2", 7321 auxType: auxSymOff, 7322 argLen: 3, 7323 symEffect: SymRead, 7324 asm: x86.AMOVWLZX, 7325 reg: regInfo{ 7326 inputs: []inputInfo{ 7327 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7328 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7329 }, 7330 outputs: []outputInfo{ 7331 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7332 }, 7333 }, 7334 }, 7335 { 7336 name: "MOVLloadidx1", 7337 auxType: auxSymOff, 7338 argLen: 3, 7339 commutative: true, 7340 symEffect: SymRead, 7341 asm: x86.AMOVL, 7342 reg: regInfo{ 7343 inputs: []inputInfo{ 7344 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7345 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7346 }, 7347 outputs: []outputInfo{ 7348 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7349 }, 7350 }, 7351 }, 7352 { 7353 name: "MOVLloadidx4", 7354 auxType: auxSymOff, 7355 argLen: 3, 7356 symEffect: SymRead, 7357 asm: x86.AMOVL, 7358 reg: regInfo{ 7359 inputs: []inputInfo{ 7360 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7361 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7362 }, 7363 outputs: []outputInfo{ 7364 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7365 }, 7366 }, 7367 }, 7368 { 7369 name: "MOVQloadidx1", 7370 auxType: auxSymOff, 7371 argLen: 3, 7372 commutative: true, 7373 symEffect: SymRead, 7374 asm: x86.AMOVQ, 7375 reg: regInfo{ 7376 inputs: []inputInfo{ 7377 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7378 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7379 }, 7380 outputs: []outputInfo{ 7381 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7382 }, 7383 }, 7384 }, 7385 { 7386 name: "MOVQloadidx8", 7387 auxType: auxSymOff, 7388 argLen: 3, 7389 symEffect: SymRead, 7390 asm: x86.AMOVQ, 7391 reg: regInfo{ 7392 inputs: []inputInfo{ 7393 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7394 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7395 }, 7396 outputs: []outputInfo{ 7397 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7398 }, 7399 }, 7400 }, 7401 { 7402 name: "MOVBstoreidx1", 7403 auxType: auxSymOff, 7404 argLen: 4, 7405 symEffect: SymWrite, 7406 asm: x86.AMOVB, 7407 reg: regInfo{ 7408 inputs: []inputInfo{ 7409 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7410 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7411 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7412 }, 7413 }, 7414 }, 7415 { 7416 name: "MOVWstoreidx1", 7417 auxType: auxSymOff, 7418 argLen: 4, 7419 symEffect: SymWrite, 7420 asm: x86.AMOVW, 7421 reg: regInfo{ 7422 inputs: []inputInfo{ 7423 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7424 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7425 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7426 }, 7427 }, 7428 }, 7429 { 7430 name: "MOVWstoreidx2", 7431 auxType: auxSymOff, 7432 argLen: 4, 7433 symEffect: SymWrite, 7434 asm: x86.AMOVW, 7435 reg: regInfo{ 7436 inputs: []inputInfo{ 7437 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7438 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7439 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7440 }, 7441 }, 7442 }, 7443 { 7444 name: "MOVLstoreidx1", 7445 auxType: auxSymOff, 7446 argLen: 4, 7447 symEffect: SymWrite, 7448 asm: x86.AMOVL, 7449 reg: regInfo{ 7450 inputs: []inputInfo{ 7451 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7452 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7453 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7454 }, 7455 }, 7456 }, 7457 { 7458 name: "MOVLstoreidx4", 7459 auxType: auxSymOff, 7460 argLen: 4, 7461 symEffect: SymWrite, 7462 asm: x86.AMOVL, 7463 reg: regInfo{ 7464 inputs: []inputInfo{ 7465 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7466 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7467 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7468 }, 7469 }, 7470 }, 7471 { 7472 name: "MOVQstoreidx1", 7473 auxType: auxSymOff, 7474 argLen: 4, 7475 symEffect: SymWrite, 7476 asm: x86.AMOVQ, 7477 reg: regInfo{ 7478 inputs: []inputInfo{ 7479 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7480 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7481 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7482 }, 7483 }, 7484 }, 7485 { 7486 name: "MOVQstoreidx8", 7487 auxType: auxSymOff, 7488 argLen: 4, 7489 symEffect: SymWrite, 7490 asm: x86.AMOVQ, 7491 reg: regInfo{ 7492 inputs: []inputInfo{ 7493 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7494 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7495 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7496 }, 7497 }, 7498 }, 7499 { 7500 name: "MOVBstoreconst", 7501 auxType: auxSymValAndOff, 7502 argLen: 2, 7503 faultOnNilArg0: true, 7504 symEffect: SymWrite, 7505 asm: x86.AMOVB, 7506 reg: regInfo{ 7507 inputs: []inputInfo{ 7508 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7509 }, 7510 }, 7511 }, 7512 { 7513 name: "MOVWstoreconst", 7514 auxType: auxSymValAndOff, 7515 argLen: 2, 7516 faultOnNilArg0: true, 7517 symEffect: SymWrite, 7518 asm: x86.AMOVW, 7519 reg: regInfo{ 7520 inputs: []inputInfo{ 7521 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7522 }, 7523 }, 7524 }, 7525 { 7526 name: "MOVLstoreconst", 7527 auxType: auxSymValAndOff, 7528 argLen: 2, 7529 faultOnNilArg0: true, 7530 symEffect: SymWrite, 7531 asm: x86.AMOVL, 7532 reg: regInfo{ 7533 inputs: []inputInfo{ 7534 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7535 }, 7536 }, 7537 }, 7538 { 7539 name: "MOVQstoreconst", 7540 auxType: auxSymValAndOff, 7541 argLen: 2, 7542 faultOnNilArg0: true, 7543 symEffect: SymWrite, 7544 asm: x86.AMOVQ, 7545 reg: regInfo{ 7546 inputs: []inputInfo{ 7547 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7548 }, 7549 }, 7550 }, 7551 { 7552 name: "MOVBstoreconstidx1", 7553 auxType: auxSymValAndOff, 7554 argLen: 3, 7555 symEffect: SymWrite, 7556 asm: x86.AMOVB, 7557 reg: regInfo{ 7558 inputs: []inputInfo{ 7559 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7560 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7561 }, 7562 }, 7563 }, 7564 { 7565 name: "MOVWstoreconstidx1", 7566 auxType: auxSymValAndOff, 7567 argLen: 3, 7568 symEffect: SymWrite, 7569 asm: x86.AMOVW, 7570 reg: regInfo{ 7571 inputs: []inputInfo{ 7572 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7573 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7574 }, 7575 }, 7576 }, 7577 { 7578 name: "MOVWstoreconstidx2", 7579 auxType: auxSymValAndOff, 7580 argLen: 3, 7581 symEffect: SymWrite, 7582 asm: x86.AMOVW, 7583 reg: regInfo{ 7584 inputs: []inputInfo{ 7585 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7586 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7587 }, 7588 }, 7589 }, 7590 { 7591 name: "MOVLstoreconstidx1", 7592 auxType: auxSymValAndOff, 7593 argLen: 3, 7594 symEffect: SymWrite, 7595 asm: x86.AMOVL, 7596 reg: regInfo{ 7597 inputs: []inputInfo{ 7598 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7599 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7600 }, 7601 }, 7602 }, 7603 { 7604 name: "MOVLstoreconstidx4", 7605 auxType: auxSymValAndOff, 7606 argLen: 3, 7607 symEffect: SymWrite, 7608 asm: x86.AMOVL, 7609 reg: regInfo{ 7610 inputs: []inputInfo{ 7611 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7612 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7613 }, 7614 }, 7615 }, 7616 { 7617 name: "MOVQstoreconstidx1", 7618 auxType: auxSymValAndOff, 7619 argLen: 3, 7620 symEffect: SymWrite, 7621 asm: x86.AMOVQ, 7622 reg: regInfo{ 7623 inputs: []inputInfo{ 7624 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7625 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7626 }, 7627 }, 7628 }, 7629 { 7630 name: "MOVQstoreconstidx8", 7631 auxType: auxSymValAndOff, 7632 argLen: 3, 7633 symEffect: SymWrite, 7634 asm: x86.AMOVQ, 7635 reg: regInfo{ 7636 inputs: []inputInfo{ 7637 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7638 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7639 }, 7640 }, 7641 }, 7642 { 7643 name: "DUFFZERO", 7644 auxType: auxInt64, 7645 argLen: 3, 7646 clobberFlags: true, 7647 faultOnNilArg0: true, 7648 reg: regInfo{ 7649 inputs: []inputInfo{ 7650 {0, 128}, // DI 7651 {1, 65536}, // X0 7652 }, 7653 clobbers: 128, // DI 7654 }, 7655 }, 7656 { 7657 name: "MOVOconst", 7658 auxType: auxInt128, 7659 argLen: 0, 7660 rematerializeable: true, 7661 reg: regInfo{ 7662 outputs: []outputInfo{ 7663 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7664 }, 7665 }, 7666 }, 7667 { 7668 name: "REPSTOSQ", 7669 argLen: 4, 7670 faultOnNilArg0: true, 7671 reg: regInfo{ 7672 inputs: []inputInfo{ 7673 {0, 128}, // DI 7674 {1, 2}, // CX 7675 {2, 1}, // AX 7676 }, 7677 clobbers: 130, // CX DI 7678 }, 7679 }, 7680 { 7681 name: "CALLstatic", 7682 auxType: auxSymOff, 7683 argLen: 1, 7684 clobberFlags: true, 7685 call: true, 7686 symEffect: SymNone, 7687 reg: regInfo{ 7688 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7689 }, 7690 }, 7691 { 7692 name: "CALLclosure", 7693 auxType: auxInt64, 7694 argLen: 3, 7695 clobberFlags: true, 7696 call: true, 7697 reg: regInfo{ 7698 inputs: []inputInfo{ 7699 {1, 4}, // DX 7700 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7701 }, 7702 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7703 }, 7704 }, 7705 { 7706 name: "CALLinter", 7707 auxType: auxInt64, 7708 argLen: 2, 7709 clobberFlags: true, 7710 call: true, 7711 reg: regInfo{ 7712 inputs: []inputInfo{ 7713 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7714 }, 7715 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7716 }, 7717 }, 7718 { 7719 name: "DUFFCOPY", 7720 auxType: auxInt64, 7721 argLen: 3, 7722 clobberFlags: true, 7723 faultOnNilArg0: true, 7724 faultOnNilArg1: true, 7725 reg: regInfo{ 7726 inputs: []inputInfo{ 7727 {0, 128}, // DI 7728 {1, 64}, // SI 7729 }, 7730 clobbers: 65728, // SI DI X0 7731 }, 7732 }, 7733 { 7734 name: "REPMOVSQ", 7735 argLen: 4, 7736 faultOnNilArg0: true, 7737 faultOnNilArg1: true, 7738 reg: regInfo{ 7739 inputs: []inputInfo{ 7740 {0, 128}, // DI 7741 {1, 64}, // SI 7742 {2, 2}, // CX 7743 }, 7744 clobbers: 194, // CX SI DI 7745 }, 7746 }, 7747 { 7748 name: "InvertFlags", 7749 argLen: 1, 7750 reg: regInfo{}, 7751 }, 7752 { 7753 name: "LoweredGetG", 7754 argLen: 1, 7755 reg: regInfo{ 7756 outputs: []outputInfo{ 7757 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7758 }, 7759 }, 7760 }, 7761 { 7762 name: "LoweredGetClosurePtr", 7763 argLen: 0, 7764 reg: regInfo{ 7765 outputs: []outputInfo{ 7766 {0, 4}, // DX 7767 }, 7768 }, 7769 }, 7770 { 7771 name: "LoweredNilCheck", 7772 argLen: 2, 7773 clobberFlags: true, 7774 nilCheck: true, 7775 faultOnNilArg0: true, 7776 reg: regInfo{ 7777 inputs: []inputInfo{ 7778 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7779 }, 7780 }, 7781 }, 7782 { 7783 name: "MOVQconvert", 7784 argLen: 2, 7785 asm: x86.AMOVQ, 7786 reg: regInfo{ 7787 inputs: []inputInfo{ 7788 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7789 }, 7790 outputs: []outputInfo{ 7791 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7792 }, 7793 }, 7794 }, 7795 { 7796 name: "MOVLconvert", 7797 argLen: 2, 7798 asm: x86.AMOVL, 7799 reg: regInfo{ 7800 inputs: []inputInfo{ 7801 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7802 }, 7803 outputs: []outputInfo{ 7804 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7805 }, 7806 }, 7807 }, 7808 { 7809 name: "FlagEQ", 7810 argLen: 0, 7811 reg: regInfo{}, 7812 }, 7813 { 7814 name: "FlagLT_ULT", 7815 argLen: 0, 7816 reg: regInfo{}, 7817 }, 7818 { 7819 name: "FlagLT_UGT", 7820 argLen: 0, 7821 reg: regInfo{}, 7822 }, 7823 { 7824 name: "FlagGT_UGT", 7825 argLen: 0, 7826 reg: regInfo{}, 7827 }, 7828 { 7829 name: "FlagGT_ULT", 7830 argLen: 0, 7831 reg: regInfo{}, 7832 }, 7833 { 7834 name: "MOVLatomicload", 7835 auxType: auxSymOff, 7836 argLen: 2, 7837 faultOnNilArg0: true, 7838 symEffect: SymRead, 7839 asm: x86.AMOVL, 7840 reg: regInfo{ 7841 inputs: []inputInfo{ 7842 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7843 }, 7844 outputs: []outputInfo{ 7845 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7846 }, 7847 }, 7848 }, 7849 { 7850 name: "MOVQatomicload", 7851 auxType: auxSymOff, 7852 argLen: 2, 7853 faultOnNilArg0: true, 7854 symEffect: SymRead, 7855 asm: x86.AMOVQ, 7856 reg: regInfo{ 7857 inputs: []inputInfo{ 7858 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7859 }, 7860 outputs: []outputInfo{ 7861 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7862 }, 7863 }, 7864 }, 7865 { 7866 name: "XCHGL", 7867 auxType: auxSymOff, 7868 argLen: 3, 7869 resultInArg0: true, 7870 faultOnNilArg1: true, 7871 hasSideEffects: true, 7872 symEffect: SymRdWr, 7873 asm: x86.AXCHGL, 7874 reg: regInfo{ 7875 inputs: []inputInfo{ 7876 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7877 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7878 }, 7879 outputs: []outputInfo{ 7880 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7881 }, 7882 }, 7883 }, 7884 { 7885 name: "XCHGQ", 7886 auxType: auxSymOff, 7887 argLen: 3, 7888 resultInArg0: true, 7889 faultOnNilArg1: true, 7890 hasSideEffects: true, 7891 symEffect: SymRdWr, 7892 asm: x86.AXCHGQ, 7893 reg: regInfo{ 7894 inputs: []inputInfo{ 7895 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7896 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7897 }, 7898 outputs: []outputInfo{ 7899 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7900 }, 7901 }, 7902 }, 7903 { 7904 name: "XADDLlock", 7905 auxType: auxSymOff, 7906 argLen: 3, 7907 resultInArg0: true, 7908 clobberFlags: true, 7909 faultOnNilArg1: true, 7910 hasSideEffects: true, 7911 symEffect: SymRdWr, 7912 asm: x86.AXADDL, 7913 reg: regInfo{ 7914 inputs: []inputInfo{ 7915 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7916 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7917 }, 7918 outputs: []outputInfo{ 7919 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7920 }, 7921 }, 7922 }, 7923 { 7924 name: "XADDQlock", 7925 auxType: auxSymOff, 7926 argLen: 3, 7927 resultInArg0: true, 7928 clobberFlags: true, 7929 faultOnNilArg1: true, 7930 hasSideEffects: true, 7931 symEffect: SymRdWr, 7932 asm: x86.AXADDQ, 7933 reg: regInfo{ 7934 inputs: []inputInfo{ 7935 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7936 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7937 }, 7938 outputs: []outputInfo{ 7939 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7940 }, 7941 }, 7942 }, 7943 { 7944 name: "AddTupleFirst32", 7945 argLen: 2, 7946 reg: regInfo{}, 7947 }, 7948 { 7949 name: "AddTupleFirst64", 7950 argLen: 2, 7951 reg: regInfo{}, 7952 }, 7953 { 7954 name: "CMPXCHGLlock", 7955 auxType: auxSymOff, 7956 argLen: 4, 7957 clobberFlags: true, 7958 faultOnNilArg0: true, 7959 hasSideEffects: true, 7960 symEffect: SymRdWr, 7961 asm: x86.ACMPXCHGL, 7962 reg: regInfo{ 7963 inputs: []inputInfo{ 7964 {1, 1}, // AX 7965 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7966 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7967 }, 7968 clobbers: 1, // AX 7969 outputs: []outputInfo{ 7970 {1, 0}, 7971 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7972 }, 7973 }, 7974 }, 7975 { 7976 name: "CMPXCHGQlock", 7977 auxType: auxSymOff, 7978 argLen: 4, 7979 clobberFlags: true, 7980 faultOnNilArg0: true, 7981 hasSideEffects: true, 7982 symEffect: SymRdWr, 7983 asm: x86.ACMPXCHGQ, 7984 reg: regInfo{ 7985 inputs: []inputInfo{ 7986 {1, 1}, // AX 7987 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7988 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7989 }, 7990 clobbers: 1, // AX 7991 outputs: []outputInfo{ 7992 {1, 0}, 7993 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7994 }, 7995 }, 7996 }, 7997 { 7998 name: "ANDBlock", 7999 auxType: auxSymOff, 8000 argLen: 3, 8001 clobberFlags: true, 8002 faultOnNilArg0: true, 8003 hasSideEffects: true, 8004 symEffect: SymRdWr, 8005 asm: x86.AANDB, 8006 reg: regInfo{ 8007 inputs: []inputInfo{ 8008 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8009 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8010 }, 8011 }, 8012 }, 8013 { 8014 name: "ORBlock", 8015 auxType: auxSymOff, 8016 argLen: 3, 8017 clobberFlags: true, 8018 faultOnNilArg0: true, 8019 hasSideEffects: true, 8020 symEffect: SymRdWr, 8021 asm: x86.AORB, 8022 reg: regInfo{ 8023 inputs: []inputInfo{ 8024 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8025 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8026 }, 8027 }, 8028 }, 8029 8030 { 8031 name: "ADD", 8032 argLen: 2, 8033 commutative: true, 8034 asm: arm.AADD, 8035 reg: regInfo{ 8036 inputs: []inputInfo{ 8037 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8038 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8039 }, 8040 outputs: []outputInfo{ 8041 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8042 }, 8043 }, 8044 }, 8045 { 8046 name: "ADDconst", 8047 auxType: auxInt32, 8048 argLen: 1, 8049 asm: arm.AADD, 8050 reg: regInfo{ 8051 inputs: []inputInfo{ 8052 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 8053 }, 8054 outputs: []outputInfo{ 8055 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8056 }, 8057 }, 8058 }, 8059 { 8060 name: "SUB", 8061 argLen: 2, 8062 asm: arm.ASUB, 8063 reg: regInfo{ 8064 inputs: []inputInfo{ 8065 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8066 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8067 }, 8068 outputs: []outputInfo{ 8069 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8070 }, 8071 }, 8072 }, 8073 { 8074 name: "SUBconst", 8075 auxType: auxInt32, 8076 argLen: 1, 8077 asm: arm.ASUB, 8078 reg: regInfo{ 8079 inputs: []inputInfo{ 8080 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8081 }, 8082 outputs: []outputInfo{ 8083 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8084 }, 8085 }, 8086 }, 8087 { 8088 name: "RSB", 8089 argLen: 2, 8090 asm: arm.ARSB, 8091 reg: regInfo{ 8092 inputs: []inputInfo{ 8093 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8094 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8095 }, 8096 outputs: []outputInfo{ 8097 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8098 }, 8099 }, 8100 }, 8101 { 8102 name: "RSBconst", 8103 auxType: auxInt32, 8104 argLen: 1, 8105 asm: arm.ARSB, 8106 reg: regInfo{ 8107 inputs: []inputInfo{ 8108 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8109 }, 8110 outputs: []outputInfo{ 8111 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8112 }, 8113 }, 8114 }, 8115 { 8116 name: "MUL", 8117 argLen: 2, 8118 commutative: true, 8119 asm: arm.AMUL, 8120 reg: regInfo{ 8121 inputs: []inputInfo{ 8122 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8123 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8124 }, 8125 outputs: []outputInfo{ 8126 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8127 }, 8128 }, 8129 }, 8130 { 8131 name: "HMUL", 8132 argLen: 2, 8133 commutative: true, 8134 asm: arm.AMULL, 8135 reg: regInfo{ 8136 inputs: []inputInfo{ 8137 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8138 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8139 }, 8140 outputs: []outputInfo{ 8141 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8142 }, 8143 }, 8144 }, 8145 { 8146 name: "HMULU", 8147 argLen: 2, 8148 commutative: true, 8149 asm: arm.AMULLU, 8150 reg: regInfo{ 8151 inputs: []inputInfo{ 8152 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8153 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8154 }, 8155 outputs: []outputInfo{ 8156 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8157 }, 8158 }, 8159 }, 8160 { 8161 name: "CALLudiv", 8162 argLen: 2, 8163 clobberFlags: true, 8164 reg: regInfo{ 8165 inputs: []inputInfo{ 8166 {0, 2}, // R1 8167 {1, 1}, // R0 8168 }, 8169 clobbers: 16396, // R2 R3 R14 8170 outputs: []outputInfo{ 8171 {0, 1}, // R0 8172 {1, 2}, // R1 8173 }, 8174 }, 8175 }, 8176 { 8177 name: "ADDS", 8178 argLen: 2, 8179 commutative: true, 8180 asm: arm.AADD, 8181 reg: regInfo{ 8182 inputs: []inputInfo{ 8183 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8184 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8185 }, 8186 outputs: []outputInfo{ 8187 {1, 0}, 8188 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8189 }, 8190 }, 8191 }, 8192 { 8193 name: "ADDSconst", 8194 auxType: auxInt32, 8195 argLen: 1, 8196 asm: arm.AADD, 8197 reg: regInfo{ 8198 inputs: []inputInfo{ 8199 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8200 }, 8201 outputs: []outputInfo{ 8202 {1, 0}, 8203 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8204 }, 8205 }, 8206 }, 8207 { 8208 name: "ADC", 8209 argLen: 3, 8210 commutative: true, 8211 asm: arm.AADC, 8212 reg: regInfo{ 8213 inputs: []inputInfo{ 8214 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8215 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8216 }, 8217 outputs: []outputInfo{ 8218 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8219 }, 8220 }, 8221 }, 8222 { 8223 name: "ADCconst", 8224 auxType: auxInt32, 8225 argLen: 2, 8226 asm: arm.AADC, 8227 reg: regInfo{ 8228 inputs: []inputInfo{ 8229 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8230 }, 8231 outputs: []outputInfo{ 8232 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8233 }, 8234 }, 8235 }, 8236 { 8237 name: "SUBS", 8238 argLen: 2, 8239 asm: arm.ASUB, 8240 reg: regInfo{ 8241 inputs: []inputInfo{ 8242 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8243 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8244 }, 8245 outputs: []outputInfo{ 8246 {1, 0}, 8247 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8248 }, 8249 }, 8250 }, 8251 { 8252 name: "SUBSconst", 8253 auxType: auxInt32, 8254 argLen: 1, 8255 asm: arm.ASUB, 8256 reg: regInfo{ 8257 inputs: []inputInfo{ 8258 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8259 }, 8260 outputs: []outputInfo{ 8261 {1, 0}, 8262 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8263 }, 8264 }, 8265 }, 8266 { 8267 name: "RSBSconst", 8268 auxType: auxInt32, 8269 argLen: 1, 8270 asm: arm.ARSB, 8271 reg: regInfo{ 8272 inputs: []inputInfo{ 8273 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8274 }, 8275 outputs: []outputInfo{ 8276 {1, 0}, 8277 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8278 }, 8279 }, 8280 }, 8281 { 8282 name: "SBC", 8283 argLen: 3, 8284 asm: arm.ASBC, 8285 reg: regInfo{ 8286 inputs: []inputInfo{ 8287 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8288 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8289 }, 8290 outputs: []outputInfo{ 8291 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8292 }, 8293 }, 8294 }, 8295 { 8296 name: "SBCconst", 8297 auxType: auxInt32, 8298 argLen: 2, 8299 asm: arm.ASBC, 8300 reg: regInfo{ 8301 inputs: []inputInfo{ 8302 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8303 }, 8304 outputs: []outputInfo{ 8305 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8306 }, 8307 }, 8308 }, 8309 { 8310 name: "RSCconst", 8311 auxType: auxInt32, 8312 argLen: 2, 8313 asm: arm.ARSC, 8314 reg: regInfo{ 8315 inputs: []inputInfo{ 8316 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8317 }, 8318 outputs: []outputInfo{ 8319 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8320 }, 8321 }, 8322 }, 8323 { 8324 name: "MULLU", 8325 argLen: 2, 8326 commutative: true, 8327 asm: arm.AMULLU, 8328 reg: regInfo{ 8329 inputs: []inputInfo{ 8330 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8331 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8332 }, 8333 outputs: []outputInfo{ 8334 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8335 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8336 }, 8337 }, 8338 }, 8339 { 8340 name: "MULA", 8341 argLen: 3, 8342 asm: arm.AMULA, 8343 reg: regInfo{ 8344 inputs: []inputInfo{ 8345 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8346 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8347 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8348 }, 8349 outputs: []outputInfo{ 8350 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8351 }, 8352 }, 8353 }, 8354 { 8355 name: "ADDF", 8356 argLen: 2, 8357 commutative: true, 8358 asm: arm.AADDF, 8359 reg: regInfo{ 8360 inputs: []inputInfo{ 8361 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8362 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8363 }, 8364 outputs: []outputInfo{ 8365 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8366 }, 8367 }, 8368 }, 8369 { 8370 name: "ADDD", 8371 argLen: 2, 8372 commutative: true, 8373 asm: arm.AADDD, 8374 reg: regInfo{ 8375 inputs: []inputInfo{ 8376 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8377 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8378 }, 8379 outputs: []outputInfo{ 8380 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8381 }, 8382 }, 8383 }, 8384 { 8385 name: "SUBF", 8386 argLen: 2, 8387 asm: arm.ASUBF, 8388 reg: regInfo{ 8389 inputs: []inputInfo{ 8390 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8391 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8392 }, 8393 outputs: []outputInfo{ 8394 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8395 }, 8396 }, 8397 }, 8398 { 8399 name: "SUBD", 8400 argLen: 2, 8401 asm: arm.ASUBD, 8402 reg: regInfo{ 8403 inputs: []inputInfo{ 8404 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8405 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8406 }, 8407 outputs: []outputInfo{ 8408 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8409 }, 8410 }, 8411 }, 8412 { 8413 name: "MULF", 8414 argLen: 2, 8415 commutative: true, 8416 asm: arm.AMULF, 8417 reg: regInfo{ 8418 inputs: []inputInfo{ 8419 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8420 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8421 }, 8422 outputs: []outputInfo{ 8423 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8424 }, 8425 }, 8426 }, 8427 { 8428 name: "MULD", 8429 argLen: 2, 8430 commutative: true, 8431 asm: arm.AMULD, 8432 reg: regInfo{ 8433 inputs: []inputInfo{ 8434 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8435 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8436 }, 8437 outputs: []outputInfo{ 8438 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8439 }, 8440 }, 8441 }, 8442 { 8443 name: "DIVF", 8444 argLen: 2, 8445 asm: arm.ADIVF, 8446 reg: regInfo{ 8447 inputs: []inputInfo{ 8448 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8449 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8450 }, 8451 outputs: []outputInfo{ 8452 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8453 }, 8454 }, 8455 }, 8456 { 8457 name: "DIVD", 8458 argLen: 2, 8459 asm: arm.ADIVD, 8460 reg: regInfo{ 8461 inputs: []inputInfo{ 8462 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8463 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8464 }, 8465 outputs: []outputInfo{ 8466 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8467 }, 8468 }, 8469 }, 8470 { 8471 name: "AND", 8472 argLen: 2, 8473 commutative: true, 8474 asm: arm.AAND, 8475 reg: regInfo{ 8476 inputs: []inputInfo{ 8477 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8478 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8479 }, 8480 outputs: []outputInfo{ 8481 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8482 }, 8483 }, 8484 }, 8485 { 8486 name: "ANDconst", 8487 auxType: auxInt32, 8488 argLen: 1, 8489 asm: arm.AAND, 8490 reg: regInfo{ 8491 inputs: []inputInfo{ 8492 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8493 }, 8494 outputs: []outputInfo{ 8495 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8496 }, 8497 }, 8498 }, 8499 { 8500 name: "OR", 8501 argLen: 2, 8502 commutative: true, 8503 asm: arm.AORR, 8504 reg: regInfo{ 8505 inputs: []inputInfo{ 8506 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8507 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8508 }, 8509 outputs: []outputInfo{ 8510 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8511 }, 8512 }, 8513 }, 8514 { 8515 name: "ORconst", 8516 auxType: auxInt32, 8517 argLen: 1, 8518 asm: arm.AORR, 8519 reg: regInfo{ 8520 inputs: []inputInfo{ 8521 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8522 }, 8523 outputs: []outputInfo{ 8524 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8525 }, 8526 }, 8527 }, 8528 { 8529 name: "XOR", 8530 argLen: 2, 8531 commutative: true, 8532 asm: arm.AEOR, 8533 reg: regInfo{ 8534 inputs: []inputInfo{ 8535 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8536 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8537 }, 8538 outputs: []outputInfo{ 8539 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8540 }, 8541 }, 8542 }, 8543 { 8544 name: "XORconst", 8545 auxType: auxInt32, 8546 argLen: 1, 8547 asm: arm.AEOR, 8548 reg: regInfo{ 8549 inputs: []inputInfo{ 8550 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8551 }, 8552 outputs: []outputInfo{ 8553 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8554 }, 8555 }, 8556 }, 8557 { 8558 name: "BIC", 8559 argLen: 2, 8560 asm: arm.ABIC, 8561 reg: regInfo{ 8562 inputs: []inputInfo{ 8563 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8564 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8565 }, 8566 outputs: []outputInfo{ 8567 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8568 }, 8569 }, 8570 }, 8571 { 8572 name: "BICconst", 8573 auxType: auxInt32, 8574 argLen: 1, 8575 asm: arm.ABIC, 8576 reg: regInfo{ 8577 inputs: []inputInfo{ 8578 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8579 }, 8580 outputs: []outputInfo{ 8581 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8582 }, 8583 }, 8584 }, 8585 { 8586 name: "MVN", 8587 argLen: 1, 8588 asm: arm.AMVN, 8589 reg: regInfo{ 8590 inputs: []inputInfo{ 8591 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8592 }, 8593 outputs: []outputInfo{ 8594 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8595 }, 8596 }, 8597 }, 8598 { 8599 name: "NEGF", 8600 argLen: 1, 8601 asm: arm.ANEGF, 8602 reg: regInfo{ 8603 inputs: []inputInfo{ 8604 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8605 }, 8606 outputs: []outputInfo{ 8607 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8608 }, 8609 }, 8610 }, 8611 { 8612 name: "NEGD", 8613 argLen: 1, 8614 asm: arm.ANEGD, 8615 reg: regInfo{ 8616 inputs: []inputInfo{ 8617 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8618 }, 8619 outputs: []outputInfo{ 8620 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8621 }, 8622 }, 8623 }, 8624 { 8625 name: "SQRTD", 8626 argLen: 1, 8627 asm: arm.ASQRTD, 8628 reg: regInfo{ 8629 inputs: []inputInfo{ 8630 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8631 }, 8632 outputs: []outputInfo{ 8633 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8634 }, 8635 }, 8636 }, 8637 { 8638 name: "CLZ", 8639 argLen: 1, 8640 asm: arm.ACLZ, 8641 reg: regInfo{ 8642 inputs: []inputInfo{ 8643 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8644 }, 8645 outputs: []outputInfo{ 8646 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8647 }, 8648 }, 8649 }, 8650 { 8651 name: "REV", 8652 argLen: 1, 8653 asm: arm.AREV, 8654 reg: regInfo{ 8655 inputs: []inputInfo{ 8656 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8657 }, 8658 outputs: []outputInfo{ 8659 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8660 }, 8661 }, 8662 }, 8663 { 8664 name: "RBIT", 8665 argLen: 1, 8666 asm: arm.ARBIT, 8667 reg: regInfo{ 8668 inputs: []inputInfo{ 8669 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8670 }, 8671 outputs: []outputInfo{ 8672 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8673 }, 8674 }, 8675 }, 8676 { 8677 name: "SLL", 8678 argLen: 2, 8679 asm: arm.ASLL, 8680 reg: regInfo{ 8681 inputs: []inputInfo{ 8682 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8683 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8684 }, 8685 outputs: []outputInfo{ 8686 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8687 }, 8688 }, 8689 }, 8690 { 8691 name: "SLLconst", 8692 auxType: auxInt32, 8693 argLen: 1, 8694 asm: arm.ASLL, 8695 reg: regInfo{ 8696 inputs: []inputInfo{ 8697 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8698 }, 8699 outputs: []outputInfo{ 8700 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8701 }, 8702 }, 8703 }, 8704 { 8705 name: "SRL", 8706 argLen: 2, 8707 asm: arm.ASRL, 8708 reg: regInfo{ 8709 inputs: []inputInfo{ 8710 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8711 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8712 }, 8713 outputs: []outputInfo{ 8714 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8715 }, 8716 }, 8717 }, 8718 { 8719 name: "SRLconst", 8720 auxType: auxInt32, 8721 argLen: 1, 8722 asm: arm.ASRL, 8723 reg: regInfo{ 8724 inputs: []inputInfo{ 8725 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8726 }, 8727 outputs: []outputInfo{ 8728 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8729 }, 8730 }, 8731 }, 8732 { 8733 name: "SRA", 8734 argLen: 2, 8735 asm: arm.ASRA, 8736 reg: regInfo{ 8737 inputs: []inputInfo{ 8738 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8739 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8740 }, 8741 outputs: []outputInfo{ 8742 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8743 }, 8744 }, 8745 }, 8746 { 8747 name: "SRAconst", 8748 auxType: auxInt32, 8749 argLen: 1, 8750 asm: arm.ASRA, 8751 reg: regInfo{ 8752 inputs: []inputInfo{ 8753 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8754 }, 8755 outputs: []outputInfo{ 8756 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8757 }, 8758 }, 8759 }, 8760 { 8761 name: "SRRconst", 8762 auxType: auxInt32, 8763 argLen: 1, 8764 reg: regInfo{ 8765 inputs: []inputInfo{ 8766 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8767 }, 8768 outputs: []outputInfo{ 8769 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8770 }, 8771 }, 8772 }, 8773 { 8774 name: "ADDshiftLL", 8775 auxType: auxInt32, 8776 argLen: 2, 8777 asm: arm.AADD, 8778 reg: regInfo{ 8779 inputs: []inputInfo{ 8780 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8781 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8782 }, 8783 outputs: []outputInfo{ 8784 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8785 }, 8786 }, 8787 }, 8788 { 8789 name: "ADDshiftRL", 8790 auxType: auxInt32, 8791 argLen: 2, 8792 asm: arm.AADD, 8793 reg: regInfo{ 8794 inputs: []inputInfo{ 8795 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8796 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8797 }, 8798 outputs: []outputInfo{ 8799 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8800 }, 8801 }, 8802 }, 8803 { 8804 name: "ADDshiftRA", 8805 auxType: auxInt32, 8806 argLen: 2, 8807 asm: arm.AADD, 8808 reg: regInfo{ 8809 inputs: []inputInfo{ 8810 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8811 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8812 }, 8813 outputs: []outputInfo{ 8814 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8815 }, 8816 }, 8817 }, 8818 { 8819 name: "SUBshiftLL", 8820 auxType: auxInt32, 8821 argLen: 2, 8822 asm: arm.ASUB, 8823 reg: regInfo{ 8824 inputs: []inputInfo{ 8825 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8826 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8827 }, 8828 outputs: []outputInfo{ 8829 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8830 }, 8831 }, 8832 }, 8833 { 8834 name: "SUBshiftRL", 8835 auxType: auxInt32, 8836 argLen: 2, 8837 asm: arm.ASUB, 8838 reg: regInfo{ 8839 inputs: []inputInfo{ 8840 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8841 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8842 }, 8843 outputs: []outputInfo{ 8844 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8845 }, 8846 }, 8847 }, 8848 { 8849 name: "SUBshiftRA", 8850 auxType: auxInt32, 8851 argLen: 2, 8852 asm: arm.ASUB, 8853 reg: regInfo{ 8854 inputs: []inputInfo{ 8855 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8856 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8857 }, 8858 outputs: []outputInfo{ 8859 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8860 }, 8861 }, 8862 }, 8863 { 8864 name: "RSBshiftLL", 8865 auxType: auxInt32, 8866 argLen: 2, 8867 asm: arm.ARSB, 8868 reg: regInfo{ 8869 inputs: []inputInfo{ 8870 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8871 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8872 }, 8873 outputs: []outputInfo{ 8874 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8875 }, 8876 }, 8877 }, 8878 { 8879 name: "RSBshiftRL", 8880 auxType: auxInt32, 8881 argLen: 2, 8882 asm: arm.ARSB, 8883 reg: regInfo{ 8884 inputs: []inputInfo{ 8885 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8886 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8887 }, 8888 outputs: []outputInfo{ 8889 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8890 }, 8891 }, 8892 }, 8893 { 8894 name: "RSBshiftRA", 8895 auxType: auxInt32, 8896 argLen: 2, 8897 asm: arm.ARSB, 8898 reg: regInfo{ 8899 inputs: []inputInfo{ 8900 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8901 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8902 }, 8903 outputs: []outputInfo{ 8904 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8905 }, 8906 }, 8907 }, 8908 { 8909 name: "ANDshiftLL", 8910 auxType: auxInt32, 8911 argLen: 2, 8912 asm: arm.AAND, 8913 reg: regInfo{ 8914 inputs: []inputInfo{ 8915 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8916 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8917 }, 8918 outputs: []outputInfo{ 8919 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8920 }, 8921 }, 8922 }, 8923 { 8924 name: "ANDshiftRL", 8925 auxType: auxInt32, 8926 argLen: 2, 8927 asm: arm.AAND, 8928 reg: regInfo{ 8929 inputs: []inputInfo{ 8930 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8931 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8932 }, 8933 outputs: []outputInfo{ 8934 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8935 }, 8936 }, 8937 }, 8938 { 8939 name: "ANDshiftRA", 8940 auxType: auxInt32, 8941 argLen: 2, 8942 asm: arm.AAND, 8943 reg: regInfo{ 8944 inputs: []inputInfo{ 8945 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8946 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8947 }, 8948 outputs: []outputInfo{ 8949 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8950 }, 8951 }, 8952 }, 8953 { 8954 name: "ORshiftLL", 8955 auxType: auxInt32, 8956 argLen: 2, 8957 asm: arm.AORR, 8958 reg: regInfo{ 8959 inputs: []inputInfo{ 8960 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8961 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8962 }, 8963 outputs: []outputInfo{ 8964 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8965 }, 8966 }, 8967 }, 8968 { 8969 name: "ORshiftRL", 8970 auxType: auxInt32, 8971 argLen: 2, 8972 asm: arm.AORR, 8973 reg: regInfo{ 8974 inputs: []inputInfo{ 8975 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8976 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8977 }, 8978 outputs: []outputInfo{ 8979 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8980 }, 8981 }, 8982 }, 8983 { 8984 name: "ORshiftRA", 8985 auxType: auxInt32, 8986 argLen: 2, 8987 asm: arm.AORR, 8988 reg: regInfo{ 8989 inputs: []inputInfo{ 8990 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8991 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8992 }, 8993 outputs: []outputInfo{ 8994 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8995 }, 8996 }, 8997 }, 8998 { 8999 name: "XORshiftLL", 9000 auxType: auxInt32, 9001 argLen: 2, 9002 asm: arm.AEOR, 9003 reg: regInfo{ 9004 inputs: []inputInfo{ 9005 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9006 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9007 }, 9008 outputs: []outputInfo{ 9009 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9010 }, 9011 }, 9012 }, 9013 { 9014 name: "XORshiftRL", 9015 auxType: auxInt32, 9016 argLen: 2, 9017 asm: arm.AEOR, 9018 reg: regInfo{ 9019 inputs: []inputInfo{ 9020 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9021 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9022 }, 9023 outputs: []outputInfo{ 9024 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9025 }, 9026 }, 9027 }, 9028 { 9029 name: "XORshiftRA", 9030 auxType: auxInt32, 9031 argLen: 2, 9032 asm: arm.AEOR, 9033 reg: regInfo{ 9034 inputs: []inputInfo{ 9035 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9036 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9037 }, 9038 outputs: []outputInfo{ 9039 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9040 }, 9041 }, 9042 }, 9043 { 9044 name: "XORshiftRR", 9045 auxType: auxInt32, 9046 argLen: 2, 9047 asm: arm.AEOR, 9048 reg: regInfo{ 9049 inputs: []inputInfo{ 9050 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9051 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9052 }, 9053 outputs: []outputInfo{ 9054 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9055 }, 9056 }, 9057 }, 9058 { 9059 name: "BICshiftLL", 9060 auxType: auxInt32, 9061 argLen: 2, 9062 asm: arm.ABIC, 9063 reg: regInfo{ 9064 inputs: []inputInfo{ 9065 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9066 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9067 }, 9068 outputs: []outputInfo{ 9069 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9070 }, 9071 }, 9072 }, 9073 { 9074 name: "BICshiftRL", 9075 auxType: auxInt32, 9076 argLen: 2, 9077 asm: arm.ABIC, 9078 reg: regInfo{ 9079 inputs: []inputInfo{ 9080 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9081 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9082 }, 9083 outputs: []outputInfo{ 9084 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9085 }, 9086 }, 9087 }, 9088 { 9089 name: "BICshiftRA", 9090 auxType: auxInt32, 9091 argLen: 2, 9092 asm: arm.ABIC, 9093 reg: regInfo{ 9094 inputs: []inputInfo{ 9095 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9096 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9097 }, 9098 outputs: []outputInfo{ 9099 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9100 }, 9101 }, 9102 }, 9103 { 9104 name: "MVNshiftLL", 9105 auxType: auxInt32, 9106 argLen: 1, 9107 asm: arm.AMVN, 9108 reg: regInfo{ 9109 inputs: []inputInfo{ 9110 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9111 }, 9112 outputs: []outputInfo{ 9113 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9114 }, 9115 }, 9116 }, 9117 { 9118 name: "MVNshiftRL", 9119 auxType: auxInt32, 9120 argLen: 1, 9121 asm: arm.AMVN, 9122 reg: regInfo{ 9123 inputs: []inputInfo{ 9124 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9125 }, 9126 outputs: []outputInfo{ 9127 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9128 }, 9129 }, 9130 }, 9131 { 9132 name: "MVNshiftRA", 9133 auxType: auxInt32, 9134 argLen: 1, 9135 asm: arm.AMVN, 9136 reg: regInfo{ 9137 inputs: []inputInfo{ 9138 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9139 }, 9140 outputs: []outputInfo{ 9141 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9142 }, 9143 }, 9144 }, 9145 { 9146 name: "ADCshiftLL", 9147 auxType: auxInt32, 9148 argLen: 3, 9149 asm: arm.AADC, 9150 reg: regInfo{ 9151 inputs: []inputInfo{ 9152 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9153 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9154 }, 9155 outputs: []outputInfo{ 9156 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9157 }, 9158 }, 9159 }, 9160 { 9161 name: "ADCshiftRL", 9162 auxType: auxInt32, 9163 argLen: 3, 9164 asm: arm.AADC, 9165 reg: regInfo{ 9166 inputs: []inputInfo{ 9167 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9168 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9169 }, 9170 outputs: []outputInfo{ 9171 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9172 }, 9173 }, 9174 }, 9175 { 9176 name: "ADCshiftRA", 9177 auxType: auxInt32, 9178 argLen: 3, 9179 asm: arm.AADC, 9180 reg: regInfo{ 9181 inputs: []inputInfo{ 9182 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9183 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9184 }, 9185 outputs: []outputInfo{ 9186 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9187 }, 9188 }, 9189 }, 9190 { 9191 name: "SBCshiftLL", 9192 auxType: auxInt32, 9193 argLen: 3, 9194 asm: arm.ASBC, 9195 reg: regInfo{ 9196 inputs: []inputInfo{ 9197 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9198 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9199 }, 9200 outputs: []outputInfo{ 9201 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9202 }, 9203 }, 9204 }, 9205 { 9206 name: "SBCshiftRL", 9207 auxType: auxInt32, 9208 argLen: 3, 9209 asm: arm.ASBC, 9210 reg: regInfo{ 9211 inputs: []inputInfo{ 9212 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9213 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9214 }, 9215 outputs: []outputInfo{ 9216 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9217 }, 9218 }, 9219 }, 9220 { 9221 name: "SBCshiftRA", 9222 auxType: auxInt32, 9223 argLen: 3, 9224 asm: arm.ASBC, 9225 reg: regInfo{ 9226 inputs: []inputInfo{ 9227 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9228 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9229 }, 9230 outputs: []outputInfo{ 9231 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9232 }, 9233 }, 9234 }, 9235 { 9236 name: "RSCshiftLL", 9237 auxType: auxInt32, 9238 argLen: 3, 9239 asm: arm.ARSC, 9240 reg: regInfo{ 9241 inputs: []inputInfo{ 9242 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9243 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9244 }, 9245 outputs: []outputInfo{ 9246 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9247 }, 9248 }, 9249 }, 9250 { 9251 name: "RSCshiftRL", 9252 auxType: auxInt32, 9253 argLen: 3, 9254 asm: arm.ARSC, 9255 reg: regInfo{ 9256 inputs: []inputInfo{ 9257 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9258 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9259 }, 9260 outputs: []outputInfo{ 9261 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9262 }, 9263 }, 9264 }, 9265 { 9266 name: "RSCshiftRA", 9267 auxType: auxInt32, 9268 argLen: 3, 9269 asm: arm.ARSC, 9270 reg: regInfo{ 9271 inputs: []inputInfo{ 9272 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9273 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9274 }, 9275 outputs: []outputInfo{ 9276 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9277 }, 9278 }, 9279 }, 9280 { 9281 name: "ADDSshiftLL", 9282 auxType: auxInt32, 9283 argLen: 2, 9284 asm: arm.AADD, 9285 reg: regInfo{ 9286 inputs: []inputInfo{ 9287 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9288 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9289 }, 9290 outputs: []outputInfo{ 9291 {1, 0}, 9292 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9293 }, 9294 }, 9295 }, 9296 { 9297 name: "ADDSshiftRL", 9298 auxType: auxInt32, 9299 argLen: 2, 9300 asm: arm.AADD, 9301 reg: regInfo{ 9302 inputs: []inputInfo{ 9303 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9304 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9305 }, 9306 outputs: []outputInfo{ 9307 {1, 0}, 9308 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9309 }, 9310 }, 9311 }, 9312 { 9313 name: "ADDSshiftRA", 9314 auxType: auxInt32, 9315 argLen: 2, 9316 asm: arm.AADD, 9317 reg: regInfo{ 9318 inputs: []inputInfo{ 9319 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9320 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9321 }, 9322 outputs: []outputInfo{ 9323 {1, 0}, 9324 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9325 }, 9326 }, 9327 }, 9328 { 9329 name: "SUBSshiftLL", 9330 auxType: auxInt32, 9331 argLen: 2, 9332 asm: arm.ASUB, 9333 reg: regInfo{ 9334 inputs: []inputInfo{ 9335 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9336 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9337 }, 9338 outputs: []outputInfo{ 9339 {1, 0}, 9340 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9341 }, 9342 }, 9343 }, 9344 { 9345 name: "SUBSshiftRL", 9346 auxType: auxInt32, 9347 argLen: 2, 9348 asm: arm.ASUB, 9349 reg: regInfo{ 9350 inputs: []inputInfo{ 9351 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9352 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9353 }, 9354 outputs: []outputInfo{ 9355 {1, 0}, 9356 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9357 }, 9358 }, 9359 }, 9360 { 9361 name: "SUBSshiftRA", 9362 auxType: auxInt32, 9363 argLen: 2, 9364 asm: arm.ASUB, 9365 reg: regInfo{ 9366 inputs: []inputInfo{ 9367 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9368 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9369 }, 9370 outputs: []outputInfo{ 9371 {1, 0}, 9372 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9373 }, 9374 }, 9375 }, 9376 { 9377 name: "RSBSshiftLL", 9378 auxType: auxInt32, 9379 argLen: 2, 9380 asm: arm.ARSB, 9381 reg: regInfo{ 9382 inputs: []inputInfo{ 9383 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9384 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9385 }, 9386 outputs: []outputInfo{ 9387 {1, 0}, 9388 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9389 }, 9390 }, 9391 }, 9392 { 9393 name: "RSBSshiftRL", 9394 auxType: auxInt32, 9395 argLen: 2, 9396 asm: arm.ARSB, 9397 reg: regInfo{ 9398 inputs: []inputInfo{ 9399 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9400 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9401 }, 9402 outputs: []outputInfo{ 9403 {1, 0}, 9404 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9405 }, 9406 }, 9407 }, 9408 { 9409 name: "RSBSshiftRA", 9410 auxType: auxInt32, 9411 argLen: 2, 9412 asm: arm.ARSB, 9413 reg: regInfo{ 9414 inputs: []inputInfo{ 9415 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9416 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9417 }, 9418 outputs: []outputInfo{ 9419 {1, 0}, 9420 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9421 }, 9422 }, 9423 }, 9424 { 9425 name: "ADDshiftLLreg", 9426 argLen: 3, 9427 asm: arm.AADD, 9428 reg: regInfo{ 9429 inputs: []inputInfo{ 9430 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9431 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9432 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9433 }, 9434 outputs: []outputInfo{ 9435 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9436 }, 9437 }, 9438 }, 9439 { 9440 name: "ADDshiftRLreg", 9441 argLen: 3, 9442 asm: arm.AADD, 9443 reg: regInfo{ 9444 inputs: []inputInfo{ 9445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9446 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9447 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9448 }, 9449 outputs: []outputInfo{ 9450 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9451 }, 9452 }, 9453 }, 9454 { 9455 name: "ADDshiftRAreg", 9456 argLen: 3, 9457 asm: arm.AADD, 9458 reg: regInfo{ 9459 inputs: []inputInfo{ 9460 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9461 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9462 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9463 }, 9464 outputs: []outputInfo{ 9465 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9466 }, 9467 }, 9468 }, 9469 { 9470 name: "SUBshiftLLreg", 9471 argLen: 3, 9472 asm: arm.ASUB, 9473 reg: regInfo{ 9474 inputs: []inputInfo{ 9475 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9476 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9477 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9478 }, 9479 outputs: []outputInfo{ 9480 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9481 }, 9482 }, 9483 }, 9484 { 9485 name: "SUBshiftRLreg", 9486 argLen: 3, 9487 asm: arm.ASUB, 9488 reg: regInfo{ 9489 inputs: []inputInfo{ 9490 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9491 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9492 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9493 }, 9494 outputs: []outputInfo{ 9495 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9496 }, 9497 }, 9498 }, 9499 { 9500 name: "SUBshiftRAreg", 9501 argLen: 3, 9502 asm: arm.ASUB, 9503 reg: regInfo{ 9504 inputs: []inputInfo{ 9505 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9506 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9507 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9508 }, 9509 outputs: []outputInfo{ 9510 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9511 }, 9512 }, 9513 }, 9514 { 9515 name: "RSBshiftLLreg", 9516 argLen: 3, 9517 asm: arm.ARSB, 9518 reg: regInfo{ 9519 inputs: []inputInfo{ 9520 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9521 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9522 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9523 }, 9524 outputs: []outputInfo{ 9525 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9526 }, 9527 }, 9528 }, 9529 { 9530 name: "RSBshiftRLreg", 9531 argLen: 3, 9532 asm: arm.ARSB, 9533 reg: regInfo{ 9534 inputs: []inputInfo{ 9535 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9536 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9537 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9538 }, 9539 outputs: []outputInfo{ 9540 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9541 }, 9542 }, 9543 }, 9544 { 9545 name: "RSBshiftRAreg", 9546 argLen: 3, 9547 asm: arm.ARSB, 9548 reg: regInfo{ 9549 inputs: []inputInfo{ 9550 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9551 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9552 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9553 }, 9554 outputs: []outputInfo{ 9555 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9556 }, 9557 }, 9558 }, 9559 { 9560 name: "ANDshiftLLreg", 9561 argLen: 3, 9562 asm: arm.AAND, 9563 reg: regInfo{ 9564 inputs: []inputInfo{ 9565 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9566 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9567 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9568 }, 9569 outputs: []outputInfo{ 9570 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9571 }, 9572 }, 9573 }, 9574 { 9575 name: "ANDshiftRLreg", 9576 argLen: 3, 9577 asm: arm.AAND, 9578 reg: regInfo{ 9579 inputs: []inputInfo{ 9580 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9581 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9582 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9583 }, 9584 outputs: []outputInfo{ 9585 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9586 }, 9587 }, 9588 }, 9589 { 9590 name: "ANDshiftRAreg", 9591 argLen: 3, 9592 asm: arm.AAND, 9593 reg: regInfo{ 9594 inputs: []inputInfo{ 9595 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9596 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9597 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9598 }, 9599 outputs: []outputInfo{ 9600 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9601 }, 9602 }, 9603 }, 9604 { 9605 name: "ORshiftLLreg", 9606 argLen: 3, 9607 asm: arm.AORR, 9608 reg: regInfo{ 9609 inputs: []inputInfo{ 9610 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9611 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9612 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9613 }, 9614 outputs: []outputInfo{ 9615 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9616 }, 9617 }, 9618 }, 9619 { 9620 name: "ORshiftRLreg", 9621 argLen: 3, 9622 asm: arm.AORR, 9623 reg: regInfo{ 9624 inputs: []inputInfo{ 9625 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9626 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9627 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9628 }, 9629 outputs: []outputInfo{ 9630 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9631 }, 9632 }, 9633 }, 9634 { 9635 name: "ORshiftRAreg", 9636 argLen: 3, 9637 asm: arm.AORR, 9638 reg: regInfo{ 9639 inputs: []inputInfo{ 9640 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9641 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9642 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9643 }, 9644 outputs: []outputInfo{ 9645 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9646 }, 9647 }, 9648 }, 9649 { 9650 name: "XORshiftLLreg", 9651 argLen: 3, 9652 asm: arm.AEOR, 9653 reg: regInfo{ 9654 inputs: []inputInfo{ 9655 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9656 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9657 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9658 }, 9659 outputs: []outputInfo{ 9660 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9661 }, 9662 }, 9663 }, 9664 { 9665 name: "XORshiftRLreg", 9666 argLen: 3, 9667 asm: arm.AEOR, 9668 reg: regInfo{ 9669 inputs: []inputInfo{ 9670 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9671 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9672 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9673 }, 9674 outputs: []outputInfo{ 9675 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9676 }, 9677 }, 9678 }, 9679 { 9680 name: "XORshiftRAreg", 9681 argLen: 3, 9682 asm: arm.AEOR, 9683 reg: regInfo{ 9684 inputs: []inputInfo{ 9685 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9686 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9687 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9688 }, 9689 outputs: []outputInfo{ 9690 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9691 }, 9692 }, 9693 }, 9694 { 9695 name: "BICshiftLLreg", 9696 argLen: 3, 9697 asm: arm.ABIC, 9698 reg: regInfo{ 9699 inputs: []inputInfo{ 9700 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9701 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9702 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9703 }, 9704 outputs: []outputInfo{ 9705 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9706 }, 9707 }, 9708 }, 9709 { 9710 name: "BICshiftRLreg", 9711 argLen: 3, 9712 asm: arm.ABIC, 9713 reg: regInfo{ 9714 inputs: []inputInfo{ 9715 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9716 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9717 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9718 }, 9719 outputs: []outputInfo{ 9720 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9721 }, 9722 }, 9723 }, 9724 { 9725 name: "BICshiftRAreg", 9726 argLen: 3, 9727 asm: arm.ABIC, 9728 reg: regInfo{ 9729 inputs: []inputInfo{ 9730 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9731 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9732 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9733 }, 9734 outputs: []outputInfo{ 9735 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9736 }, 9737 }, 9738 }, 9739 { 9740 name: "MVNshiftLLreg", 9741 argLen: 2, 9742 asm: arm.AMVN, 9743 reg: regInfo{ 9744 inputs: []inputInfo{ 9745 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9746 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9747 }, 9748 outputs: []outputInfo{ 9749 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9750 }, 9751 }, 9752 }, 9753 { 9754 name: "MVNshiftRLreg", 9755 argLen: 2, 9756 asm: arm.AMVN, 9757 reg: regInfo{ 9758 inputs: []inputInfo{ 9759 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9760 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9761 }, 9762 outputs: []outputInfo{ 9763 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9764 }, 9765 }, 9766 }, 9767 { 9768 name: "MVNshiftRAreg", 9769 argLen: 2, 9770 asm: arm.AMVN, 9771 reg: regInfo{ 9772 inputs: []inputInfo{ 9773 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9774 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9775 }, 9776 outputs: []outputInfo{ 9777 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9778 }, 9779 }, 9780 }, 9781 { 9782 name: "ADCshiftLLreg", 9783 argLen: 4, 9784 asm: arm.AADC, 9785 reg: regInfo{ 9786 inputs: []inputInfo{ 9787 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9788 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9789 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9790 }, 9791 outputs: []outputInfo{ 9792 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9793 }, 9794 }, 9795 }, 9796 { 9797 name: "ADCshiftRLreg", 9798 argLen: 4, 9799 asm: arm.AADC, 9800 reg: regInfo{ 9801 inputs: []inputInfo{ 9802 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9803 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9804 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9805 }, 9806 outputs: []outputInfo{ 9807 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9808 }, 9809 }, 9810 }, 9811 { 9812 name: "ADCshiftRAreg", 9813 argLen: 4, 9814 asm: arm.AADC, 9815 reg: regInfo{ 9816 inputs: []inputInfo{ 9817 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9818 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9819 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9820 }, 9821 outputs: []outputInfo{ 9822 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9823 }, 9824 }, 9825 }, 9826 { 9827 name: "SBCshiftLLreg", 9828 argLen: 4, 9829 asm: arm.ASBC, 9830 reg: regInfo{ 9831 inputs: []inputInfo{ 9832 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9833 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9834 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9835 }, 9836 outputs: []outputInfo{ 9837 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9838 }, 9839 }, 9840 }, 9841 { 9842 name: "SBCshiftRLreg", 9843 argLen: 4, 9844 asm: arm.ASBC, 9845 reg: regInfo{ 9846 inputs: []inputInfo{ 9847 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9848 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9849 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9850 }, 9851 outputs: []outputInfo{ 9852 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9853 }, 9854 }, 9855 }, 9856 { 9857 name: "SBCshiftRAreg", 9858 argLen: 4, 9859 asm: arm.ASBC, 9860 reg: regInfo{ 9861 inputs: []inputInfo{ 9862 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9863 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9864 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9865 }, 9866 outputs: []outputInfo{ 9867 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9868 }, 9869 }, 9870 }, 9871 { 9872 name: "RSCshiftLLreg", 9873 argLen: 4, 9874 asm: arm.ARSC, 9875 reg: regInfo{ 9876 inputs: []inputInfo{ 9877 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9878 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9879 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9880 }, 9881 outputs: []outputInfo{ 9882 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9883 }, 9884 }, 9885 }, 9886 { 9887 name: "RSCshiftRLreg", 9888 argLen: 4, 9889 asm: arm.ARSC, 9890 reg: regInfo{ 9891 inputs: []inputInfo{ 9892 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9893 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9894 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9895 }, 9896 outputs: []outputInfo{ 9897 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9898 }, 9899 }, 9900 }, 9901 { 9902 name: "RSCshiftRAreg", 9903 argLen: 4, 9904 asm: arm.ARSC, 9905 reg: regInfo{ 9906 inputs: []inputInfo{ 9907 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9908 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9909 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9910 }, 9911 outputs: []outputInfo{ 9912 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9913 }, 9914 }, 9915 }, 9916 { 9917 name: "ADDSshiftLLreg", 9918 argLen: 3, 9919 asm: arm.AADD, 9920 reg: regInfo{ 9921 inputs: []inputInfo{ 9922 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9923 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9924 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9925 }, 9926 outputs: []outputInfo{ 9927 {1, 0}, 9928 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9929 }, 9930 }, 9931 }, 9932 { 9933 name: "ADDSshiftRLreg", 9934 argLen: 3, 9935 asm: arm.AADD, 9936 reg: regInfo{ 9937 inputs: []inputInfo{ 9938 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9939 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9940 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9941 }, 9942 outputs: []outputInfo{ 9943 {1, 0}, 9944 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9945 }, 9946 }, 9947 }, 9948 { 9949 name: "ADDSshiftRAreg", 9950 argLen: 3, 9951 asm: arm.AADD, 9952 reg: regInfo{ 9953 inputs: []inputInfo{ 9954 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9955 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9956 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9957 }, 9958 outputs: []outputInfo{ 9959 {1, 0}, 9960 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9961 }, 9962 }, 9963 }, 9964 { 9965 name: "SUBSshiftLLreg", 9966 argLen: 3, 9967 asm: arm.ASUB, 9968 reg: regInfo{ 9969 inputs: []inputInfo{ 9970 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9971 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9972 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9973 }, 9974 outputs: []outputInfo{ 9975 {1, 0}, 9976 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9977 }, 9978 }, 9979 }, 9980 { 9981 name: "SUBSshiftRLreg", 9982 argLen: 3, 9983 asm: arm.ASUB, 9984 reg: regInfo{ 9985 inputs: []inputInfo{ 9986 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9987 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9988 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9989 }, 9990 outputs: []outputInfo{ 9991 {1, 0}, 9992 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9993 }, 9994 }, 9995 }, 9996 { 9997 name: "SUBSshiftRAreg", 9998 argLen: 3, 9999 asm: arm.ASUB, 10000 reg: regInfo{ 10001 inputs: []inputInfo{ 10002 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10003 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10004 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10005 }, 10006 outputs: []outputInfo{ 10007 {1, 0}, 10008 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10009 }, 10010 }, 10011 }, 10012 { 10013 name: "RSBSshiftLLreg", 10014 argLen: 3, 10015 asm: arm.ARSB, 10016 reg: regInfo{ 10017 inputs: []inputInfo{ 10018 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10019 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10020 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10021 }, 10022 outputs: []outputInfo{ 10023 {1, 0}, 10024 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10025 }, 10026 }, 10027 }, 10028 { 10029 name: "RSBSshiftRLreg", 10030 argLen: 3, 10031 asm: arm.ARSB, 10032 reg: regInfo{ 10033 inputs: []inputInfo{ 10034 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10035 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10036 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10037 }, 10038 outputs: []outputInfo{ 10039 {1, 0}, 10040 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10041 }, 10042 }, 10043 }, 10044 { 10045 name: "RSBSshiftRAreg", 10046 argLen: 3, 10047 asm: arm.ARSB, 10048 reg: regInfo{ 10049 inputs: []inputInfo{ 10050 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10051 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10052 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10053 }, 10054 outputs: []outputInfo{ 10055 {1, 0}, 10056 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10057 }, 10058 }, 10059 }, 10060 { 10061 name: "CMP", 10062 argLen: 2, 10063 asm: arm.ACMP, 10064 reg: regInfo{ 10065 inputs: []inputInfo{ 10066 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10067 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10068 }, 10069 }, 10070 }, 10071 { 10072 name: "CMPconst", 10073 auxType: auxInt32, 10074 argLen: 1, 10075 asm: arm.ACMP, 10076 reg: regInfo{ 10077 inputs: []inputInfo{ 10078 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10079 }, 10080 }, 10081 }, 10082 { 10083 name: "CMN", 10084 argLen: 2, 10085 asm: arm.ACMN, 10086 reg: regInfo{ 10087 inputs: []inputInfo{ 10088 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10089 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10090 }, 10091 }, 10092 }, 10093 { 10094 name: "CMNconst", 10095 auxType: auxInt32, 10096 argLen: 1, 10097 asm: arm.ACMN, 10098 reg: regInfo{ 10099 inputs: []inputInfo{ 10100 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10101 }, 10102 }, 10103 }, 10104 { 10105 name: "TST", 10106 argLen: 2, 10107 commutative: true, 10108 asm: arm.ATST, 10109 reg: regInfo{ 10110 inputs: []inputInfo{ 10111 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10112 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10113 }, 10114 }, 10115 }, 10116 { 10117 name: "TSTconst", 10118 auxType: auxInt32, 10119 argLen: 1, 10120 asm: arm.ATST, 10121 reg: regInfo{ 10122 inputs: []inputInfo{ 10123 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10124 }, 10125 }, 10126 }, 10127 { 10128 name: "TEQ", 10129 argLen: 2, 10130 commutative: true, 10131 asm: arm.ATEQ, 10132 reg: regInfo{ 10133 inputs: []inputInfo{ 10134 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10135 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10136 }, 10137 }, 10138 }, 10139 { 10140 name: "TEQconst", 10141 auxType: auxInt32, 10142 argLen: 1, 10143 asm: arm.ATEQ, 10144 reg: regInfo{ 10145 inputs: []inputInfo{ 10146 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10147 }, 10148 }, 10149 }, 10150 { 10151 name: "CMPF", 10152 argLen: 2, 10153 asm: arm.ACMPF, 10154 reg: regInfo{ 10155 inputs: []inputInfo{ 10156 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10157 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10158 }, 10159 }, 10160 }, 10161 { 10162 name: "CMPD", 10163 argLen: 2, 10164 asm: arm.ACMPD, 10165 reg: regInfo{ 10166 inputs: []inputInfo{ 10167 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10168 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10169 }, 10170 }, 10171 }, 10172 { 10173 name: "CMPshiftLL", 10174 auxType: auxInt32, 10175 argLen: 2, 10176 asm: arm.ACMP, 10177 reg: regInfo{ 10178 inputs: []inputInfo{ 10179 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10180 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10181 }, 10182 }, 10183 }, 10184 { 10185 name: "CMPshiftRL", 10186 auxType: auxInt32, 10187 argLen: 2, 10188 asm: arm.ACMP, 10189 reg: regInfo{ 10190 inputs: []inputInfo{ 10191 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10192 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10193 }, 10194 }, 10195 }, 10196 { 10197 name: "CMPshiftRA", 10198 auxType: auxInt32, 10199 argLen: 2, 10200 asm: arm.ACMP, 10201 reg: regInfo{ 10202 inputs: []inputInfo{ 10203 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10204 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10205 }, 10206 }, 10207 }, 10208 { 10209 name: "CMPshiftLLreg", 10210 argLen: 3, 10211 asm: arm.ACMP, 10212 reg: regInfo{ 10213 inputs: []inputInfo{ 10214 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10215 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10216 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10217 }, 10218 }, 10219 }, 10220 { 10221 name: "CMPshiftRLreg", 10222 argLen: 3, 10223 asm: arm.ACMP, 10224 reg: regInfo{ 10225 inputs: []inputInfo{ 10226 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10227 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10228 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10229 }, 10230 }, 10231 }, 10232 { 10233 name: "CMPshiftRAreg", 10234 argLen: 3, 10235 asm: arm.ACMP, 10236 reg: regInfo{ 10237 inputs: []inputInfo{ 10238 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10239 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10240 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10241 }, 10242 }, 10243 }, 10244 { 10245 name: "CMPF0", 10246 argLen: 1, 10247 asm: arm.ACMPF, 10248 reg: regInfo{ 10249 inputs: []inputInfo{ 10250 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10251 }, 10252 }, 10253 }, 10254 { 10255 name: "CMPD0", 10256 argLen: 1, 10257 asm: arm.ACMPD, 10258 reg: regInfo{ 10259 inputs: []inputInfo{ 10260 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10261 }, 10262 }, 10263 }, 10264 { 10265 name: "MOVWconst", 10266 auxType: auxInt32, 10267 argLen: 0, 10268 rematerializeable: true, 10269 asm: arm.AMOVW, 10270 reg: regInfo{ 10271 outputs: []outputInfo{ 10272 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10273 }, 10274 }, 10275 }, 10276 { 10277 name: "MOVFconst", 10278 auxType: auxFloat64, 10279 argLen: 0, 10280 rematerializeable: true, 10281 asm: arm.AMOVF, 10282 reg: regInfo{ 10283 outputs: []outputInfo{ 10284 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10285 }, 10286 }, 10287 }, 10288 { 10289 name: "MOVDconst", 10290 auxType: auxFloat64, 10291 argLen: 0, 10292 rematerializeable: true, 10293 asm: arm.AMOVD, 10294 reg: regInfo{ 10295 outputs: []outputInfo{ 10296 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10297 }, 10298 }, 10299 }, 10300 { 10301 name: "MOVWaddr", 10302 auxType: auxSymOff, 10303 argLen: 1, 10304 rematerializeable: true, 10305 symEffect: SymAddr, 10306 asm: arm.AMOVW, 10307 reg: regInfo{ 10308 inputs: []inputInfo{ 10309 {0, 4294975488}, // SP SB 10310 }, 10311 outputs: []outputInfo{ 10312 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10313 }, 10314 }, 10315 }, 10316 { 10317 name: "MOVBload", 10318 auxType: auxSymOff, 10319 argLen: 2, 10320 faultOnNilArg0: true, 10321 symEffect: SymRead, 10322 asm: arm.AMOVB, 10323 reg: regInfo{ 10324 inputs: []inputInfo{ 10325 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10326 }, 10327 outputs: []outputInfo{ 10328 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10329 }, 10330 }, 10331 }, 10332 { 10333 name: "MOVBUload", 10334 auxType: auxSymOff, 10335 argLen: 2, 10336 faultOnNilArg0: true, 10337 symEffect: SymRead, 10338 asm: arm.AMOVBU, 10339 reg: regInfo{ 10340 inputs: []inputInfo{ 10341 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10342 }, 10343 outputs: []outputInfo{ 10344 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10345 }, 10346 }, 10347 }, 10348 { 10349 name: "MOVHload", 10350 auxType: auxSymOff, 10351 argLen: 2, 10352 faultOnNilArg0: true, 10353 symEffect: SymRead, 10354 asm: arm.AMOVH, 10355 reg: regInfo{ 10356 inputs: []inputInfo{ 10357 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10358 }, 10359 outputs: []outputInfo{ 10360 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10361 }, 10362 }, 10363 }, 10364 { 10365 name: "MOVHUload", 10366 auxType: auxSymOff, 10367 argLen: 2, 10368 faultOnNilArg0: true, 10369 symEffect: SymRead, 10370 asm: arm.AMOVHU, 10371 reg: regInfo{ 10372 inputs: []inputInfo{ 10373 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10374 }, 10375 outputs: []outputInfo{ 10376 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10377 }, 10378 }, 10379 }, 10380 { 10381 name: "MOVWload", 10382 auxType: auxSymOff, 10383 argLen: 2, 10384 faultOnNilArg0: true, 10385 symEffect: SymRead, 10386 asm: arm.AMOVW, 10387 reg: regInfo{ 10388 inputs: []inputInfo{ 10389 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10390 }, 10391 outputs: []outputInfo{ 10392 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10393 }, 10394 }, 10395 }, 10396 { 10397 name: "MOVFload", 10398 auxType: auxSymOff, 10399 argLen: 2, 10400 faultOnNilArg0: true, 10401 symEffect: SymRead, 10402 asm: arm.AMOVF, 10403 reg: regInfo{ 10404 inputs: []inputInfo{ 10405 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10406 }, 10407 outputs: []outputInfo{ 10408 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10409 }, 10410 }, 10411 }, 10412 { 10413 name: "MOVDload", 10414 auxType: auxSymOff, 10415 argLen: 2, 10416 faultOnNilArg0: true, 10417 symEffect: SymRead, 10418 asm: arm.AMOVD, 10419 reg: regInfo{ 10420 inputs: []inputInfo{ 10421 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10422 }, 10423 outputs: []outputInfo{ 10424 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10425 }, 10426 }, 10427 }, 10428 { 10429 name: "MOVBstore", 10430 auxType: auxSymOff, 10431 argLen: 3, 10432 faultOnNilArg0: true, 10433 symEffect: SymWrite, 10434 asm: arm.AMOVB, 10435 reg: regInfo{ 10436 inputs: []inputInfo{ 10437 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10438 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10439 }, 10440 }, 10441 }, 10442 { 10443 name: "MOVHstore", 10444 auxType: auxSymOff, 10445 argLen: 3, 10446 faultOnNilArg0: true, 10447 symEffect: SymWrite, 10448 asm: arm.AMOVH, 10449 reg: regInfo{ 10450 inputs: []inputInfo{ 10451 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10452 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10453 }, 10454 }, 10455 }, 10456 { 10457 name: "MOVWstore", 10458 auxType: auxSymOff, 10459 argLen: 3, 10460 faultOnNilArg0: true, 10461 symEffect: SymWrite, 10462 asm: arm.AMOVW, 10463 reg: regInfo{ 10464 inputs: []inputInfo{ 10465 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10466 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10467 }, 10468 }, 10469 }, 10470 { 10471 name: "MOVFstore", 10472 auxType: auxSymOff, 10473 argLen: 3, 10474 faultOnNilArg0: true, 10475 symEffect: SymWrite, 10476 asm: arm.AMOVF, 10477 reg: regInfo{ 10478 inputs: []inputInfo{ 10479 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10480 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10481 }, 10482 }, 10483 }, 10484 { 10485 name: "MOVDstore", 10486 auxType: auxSymOff, 10487 argLen: 3, 10488 faultOnNilArg0: true, 10489 symEffect: SymWrite, 10490 asm: arm.AMOVD, 10491 reg: regInfo{ 10492 inputs: []inputInfo{ 10493 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10494 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10495 }, 10496 }, 10497 }, 10498 { 10499 name: "MOVWloadidx", 10500 argLen: 3, 10501 asm: arm.AMOVW, 10502 reg: regInfo{ 10503 inputs: []inputInfo{ 10504 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10505 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10506 }, 10507 outputs: []outputInfo{ 10508 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10509 }, 10510 }, 10511 }, 10512 { 10513 name: "MOVWloadshiftLL", 10514 auxType: auxInt32, 10515 argLen: 3, 10516 asm: arm.AMOVW, 10517 reg: regInfo{ 10518 inputs: []inputInfo{ 10519 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10520 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10521 }, 10522 outputs: []outputInfo{ 10523 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10524 }, 10525 }, 10526 }, 10527 { 10528 name: "MOVWloadshiftRL", 10529 auxType: auxInt32, 10530 argLen: 3, 10531 asm: arm.AMOVW, 10532 reg: regInfo{ 10533 inputs: []inputInfo{ 10534 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10535 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10536 }, 10537 outputs: []outputInfo{ 10538 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10539 }, 10540 }, 10541 }, 10542 { 10543 name: "MOVWloadshiftRA", 10544 auxType: auxInt32, 10545 argLen: 3, 10546 asm: arm.AMOVW, 10547 reg: regInfo{ 10548 inputs: []inputInfo{ 10549 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10550 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10551 }, 10552 outputs: []outputInfo{ 10553 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10554 }, 10555 }, 10556 }, 10557 { 10558 name: "MOVWstoreidx", 10559 argLen: 4, 10560 asm: arm.AMOVW, 10561 reg: regInfo{ 10562 inputs: []inputInfo{ 10563 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10564 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10565 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10566 }, 10567 }, 10568 }, 10569 { 10570 name: "MOVWstoreshiftLL", 10571 auxType: auxInt32, 10572 argLen: 4, 10573 asm: arm.AMOVW, 10574 reg: regInfo{ 10575 inputs: []inputInfo{ 10576 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10577 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10578 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10579 }, 10580 }, 10581 }, 10582 { 10583 name: "MOVWstoreshiftRL", 10584 auxType: auxInt32, 10585 argLen: 4, 10586 asm: arm.AMOVW, 10587 reg: regInfo{ 10588 inputs: []inputInfo{ 10589 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10590 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10591 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10592 }, 10593 }, 10594 }, 10595 { 10596 name: "MOVWstoreshiftRA", 10597 auxType: auxInt32, 10598 argLen: 4, 10599 asm: arm.AMOVW, 10600 reg: regInfo{ 10601 inputs: []inputInfo{ 10602 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10603 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10604 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 10605 }, 10606 }, 10607 }, 10608 { 10609 name: "MOVBreg", 10610 argLen: 1, 10611 asm: arm.AMOVBS, 10612 reg: regInfo{ 10613 inputs: []inputInfo{ 10614 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10615 }, 10616 outputs: []outputInfo{ 10617 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10618 }, 10619 }, 10620 }, 10621 { 10622 name: "MOVBUreg", 10623 argLen: 1, 10624 asm: arm.AMOVBU, 10625 reg: regInfo{ 10626 inputs: []inputInfo{ 10627 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10628 }, 10629 outputs: []outputInfo{ 10630 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10631 }, 10632 }, 10633 }, 10634 { 10635 name: "MOVHreg", 10636 argLen: 1, 10637 asm: arm.AMOVHS, 10638 reg: regInfo{ 10639 inputs: []inputInfo{ 10640 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10641 }, 10642 outputs: []outputInfo{ 10643 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10644 }, 10645 }, 10646 }, 10647 { 10648 name: "MOVHUreg", 10649 argLen: 1, 10650 asm: arm.AMOVHU, 10651 reg: regInfo{ 10652 inputs: []inputInfo{ 10653 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10654 }, 10655 outputs: []outputInfo{ 10656 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10657 }, 10658 }, 10659 }, 10660 { 10661 name: "MOVWreg", 10662 argLen: 1, 10663 asm: arm.AMOVW, 10664 reg: regInfo{ 10665 inputs: []inputInfo{ 10666 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10667 }, 10668 outputs: []outputInfo{ 10669 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10670 }, 10671 }, 10672 }, 10673 { 10674 name: "MOVWnop", 10675 argLen: 1, 10676 resultInArg0: true, 10677 reg: regInfo{ 10678 inputs: []inputInfo{ 10679 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10680 }, 10681 outputs: []outputInfo{ 10682 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10683 }, 10684 }, 10685 }, 10686 { 10687 name: "MOVWF", 10688 argLen: 1, 10689 asm: arm.AMOVWF, 10690 reg: regInfo{ 10691 inputs: []inputInfo{ 10692 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10693 }, 10694 clobbers: 2147483648, // F15 10695 outputs: []outputInfo{ 10696 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10697 }, 10698 }, 10699 }, 10700 { 10701 name: "MOVWD", 10702 argLen: 1, 10703 asm: arm.AMOVWD, 10704 reg: regInfo{ 10705 inputs: []inputInfo{ 10706 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10707 }, 10708 clobbers: 2147483648, // F15 10709 outputs: []outputInfo{ 10710 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10711 }, 10712 }, 10713 }, 10714 { 10715 name: "MOVWUF", 10716 argLen: 1, 10717 asm: arm.AMOVWF, 10718 reg: regInfo{ 10719 inputs: []inputInfo{ 10720 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10721 }, 10722 clobbers: 2147483648, // F15 10723 outputs: []outputInfo{ 10724 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10725 }, 10726 }, 10727 }, 10728 { 10729 name: "MOVWUD", 10730 argLen: 1, 10731 asm: arm.AMOVWD, 10732 reg: regInfo{ 10733 inputs: []inputInfo{ 10734 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10735 }, 10736 clobbers: 2147483648, // F15 10737 outputs: []outputInfo{ 10738 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10739 }, 10740 }, 10741 }, 10742 { 10743 name: "MOVFW", 10744 argLen: 1, 10745 asm: arm.AMOVFW, 10746 reg: regInfo{ 10747 inputs: []inputInfo{ 10748 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10749 }, 10750 clobbers: 2147483648, // F15 10751 outputs: []outputInfo{ 10752 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10753 }, 10754 }, 10755 }, 10756 { 10757 name: "MOVDW", 10758 argLen: 1, 10759 asm: arm.AMOVDW, 10760 reg: regInfo{ 10761 inputs: []inputInfo{ 10762 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10763 }, 10764 clobbers: 2147483648, // F15 10765 outputs: []outputInfo{ 10766 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10767 }, 10768 }, 10769 }, 10770 { 10771 name: "MOVFWU", 10772 argLen: 1, 10773 asm: arm.AMOVFW, 10774 reg: regInfo{ 10775 inputs: []inputInfo{ 10776 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10777 }, 10778 clobbers: 2147483648, // F15 10779 outputs: []outputInfo{ 10780 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10781 }, 10782 }, 10783 }, 10784 { 10785 name: "MOVDWU", 10786 argLen: 1, 10787 asm: arm.AMOVDW, 10788 reg: regInfo{ 10789 inputs: []inputInfo{ 10790 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10791 }, 10792 clobbers: 2147483648, // F15 10793 outputs: []outputInfo{ 10794 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10795 }, 10796 }, 10797 }, 10798 { 10799 name: "MOVFD", 10800 argLen: 1, 10801 asm: arm.AMOVFD, 10802 reg: regInfo{ 10803 inputs: []inputInfo{ 10804 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10805 }, 10806 outputs: []outputInfo{ 10807 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10808 }, 10809 }, 10810 }, 10811 { 10812 name: "MOVDF", 10813 argLen: 1, 10814 asm: arm.AMOVDF, 10815 reg: regInfo{ 10816 inputs: []inputInfo{ 10817 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10818 }, 10819 outputs: []outputInfo{ 10820 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10821 }, 10822 }, 10823 }, 10824 { 10825 name: "CMOVWHSconst", 10826 auxType: auxInt32, 10827 argLen: 2, 10828 resultInArg0: true, 10829 asm: arm.AMOVW, 10830 reg: regInfo{ 10831 inputs: []inputInfo{ 10832 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10833 }, 10834 outputs: []outputInfo{ 10835 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10836 }, 10837 }, 10838 }, 10839 { 10840 name: "CMOVWLSconst", 10841 auxType: auxInt32, 10842 argLen: 2, 10843 resultInArg0: true, 10844 asm: arm.AMOVW, 10845 reg: regInfo{ 10846 inputs: []inputInfo{ 10847 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10848 }, 10849 outputs: []outputInfo{ 10850 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10851 }, 10852 }, 10853 }, 10854 { 10855 name: "SRAcond", 10856 argLen: 3, 10857 asm: arm.ASRA, 10858 reg: regInfo{ 10859 inputs: []inputInfo{ 10860 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10861 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10862 }, 10863 outputs: []outputInfo{ 10864 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10865 }, 10866 }, 10867 }, 10868 { 10869 name: "CALLstatic", 10870 auxType: auxSymOff, 10871 argLen: 1, 10872 clobberFlags: true, 10873 call: true, 10874 symEffect: SymNone, 10875 reg: regInfo{ 10876 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10877 }, 10878 }, 10879 { 10880 name: "CALLclosure", 10881 auxType: auxInt64, 10882 argLen: 3, 10883 clobberFlags: true, 10884 call: true, 10885 reg: regInfo{ 10886 inputs: []inputInfo{ 10887 {1, 128}, // R7 10888 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 10889 }, 10890 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10891 }, 10892 }, 10893 { 10894 name: "CALLinter", 10895 auxType: auxInt64, 10896 argLen: 2, 10897 clobberFlags: true, 10898 call: true, 10899 reg: regInfo{ 10900 inputs: []inputInfo{ 10901 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10902 }, 10903 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10904 }, 10905 }, 10906 { 10907 name: "LoweredNilCheck", 10908 argLen: 2, 10909 nilCheck: true, 10910 faultOnNilArg0: true, 10911 reg: regInfo{ 10912 inputs: []inputInfo{ 10913 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10914 }, 10915 }, 10916 }, 10917 { 10918 name: "Equal", 10919 argLen: 1, 10920 reg: regInfo{ 10921 outputs: []outputInfo{ 10922 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10923 }, 10924 }, 10925 }, 10926 { 10927 name: "NotEqual", 10928 argLen: 1, 10929 reg: regInfo{ 10930 outputs: []outputInfo{ 10931 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10932 }, 10933 }, 10934 }, 10935 { 10936 name: "LessThan", 10937 argLen: 1, 10938 reg: regInfo{ 10939 outputs: []outputInfo{ 10940 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10941 }, 10942 }, 10943 }, 10944 { 10945 name: "LessEqual", 10946 argLen: 1, 10947 reg: regInfo{ 10948 outputs: []outputInfo{ 10949 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10950 }, 10951 }, 10952 }, 10953 { 10954 name: "GreaterThan", 10955 argLen: 1, 10956 reg: regInfo{ 10957 outputs: []outputInfo{ 10958 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10959 }, 10960 }, 10961 }, 10962 { 10963 name: "GreaterEqual", 10964 argLen: 1, 10965 reg: regInfo{ 10966 outputs: []outputInfo{ 10967 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10968 }, 10969 }, 10970 }, 10971 { 10972 name: "LessThanU", 10973 argLen: 1, 10974 reg: regInfo{ 10975 outputs: []outputInfo{ 10976 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10977 }, 10978 }, 10979 }, 10980 { 10981 name: "LessEqualU", 10982 argLen: 1, 10983 reg: regInfo{ 10984 outputs: []outputInfo{ 10985 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10986 }, 10987 }, 10988 }, 10989 { 10990 name: "GreaterThanU", 10991 argLen: 1, 10992 reg: regInfo{ 10993 outputs: []outputInfo{ 10994 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10995 }, 10996 }, 10997 }, 10998 { 10999 name: "GreaterEqualU", 11000 argLen: 1, 11001 reg: regInfo{ 11002 outputs: []outputInfo{ 11003 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11004 }, 11005 }, 11006 }, 11007 { 11008 name: "DUFFZERO", 11009 auxType: auxInt64, 11010 argLen: 3, 11011 faultOnNilArg0: true, 11012 reg: regInfo{ 11013 inputs: []inputInfo{ 11014 {0, 2}, // R1 11015 {1, 1}, // R0 11016 }, 11017 clobbers: 16386, // R1 R14 11018 }, 11019 }, 11020 { 11021 name: "DUFFCOPY", 11022 auxType: auxInt64, 11023 argLen: 3, 11024 faultOnNilArg0: true, 11025 faultOnNilArg1: true, 11026 reg: regInfo{ 11027 inputs: []inputInfo{ 11028 {0, 4}, // R2 11029 {1, 2}, // R1 11030 }, 11031 clobbers: 16391, // R0 R1 R2 R14 11032 }, 11033 }, 11034 { 11035 name: "LoweredZero", 11036 auxType: auxInt64, 11037 argLen: 4, 11038 clobberFlags: true, 11039 faultOnNilArg0: true, 11040 reg: regInfo{ 11041 inputs: []inputInfo{ 11042 {0, 2}, // R1 11043 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11044 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11045 }, 11046 clobbers: 2, // R1 11047 }, 11048 }, 11049 { 11050 name: "LoweredMove", 11051 auxType: auxInt64, 11052 argLen: 4, 11053 clobberFlags: true, 11054 faultOnNilArg0: true, 11055 faultOnNilArg1: true, 11056 reg: regInfo{ 11057 inputs: []inputInfo{ 11058 {0, 4}, // R2 11059 {1, 2}, // R1 11060 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11061 }, 11062 clobbers: 6, // R1 R2 11063 }, 11064 }, 11065 { 11066 name: "LoweredGetClosurePtr", 11067 argLen: 0, 11068 reg: regInfo{ 11069 outputs: []outputInfo{ 11070 {0, 128}, // R7 11071 }, 11072 }, 11073 }, 11074 { 11075 name: "MOVWconvert", 11076 argLen: 2, 11077 asm: arm.AMOVW, 11078 reg: regInfo{ 11079 inputs: []inputInfo{ 11080 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11081 }, 11082 outputs: []outputInfo{ 11083 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11084 }, 11085 }, 11086 }, 11087 { 11088 name: "FlagEQ", 11089 argLen: 0, 11090 reg: regInfo{}, 11091 }, 11092 { 11093 name: "FlagLT_ULT", 11094 argLen: 0, 11095 reg: regInfo{}, 11096 }, 11097 { 11098 name: "FlagLT_UGT", 11099 argLen: 0, 11100 reg: regInfo{}, 11101 }, 11102 { 11103 name: "FlagGT_UGT", 11104 argLen: 0, 11105 reg: regInfo{}, 11106 }, 11107 { 11108 name: "FlagGT_ULT", 11109 argLen: 0, 11110 reg: regInfo{}, 11111 }, 11112 { 11113 name: "InvertFlags", 11114 argLen: 1, 11115 reg: regInfo{}, 11116 }, 11117 11118 { 11119 name: "ADD", 11120 argLen: 2, 11121 commutative: true, 11122 asm: arm64.AADD, 11123 reg: regInfo{ 11124 inputs: []inputInfo{ 11125 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11126 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11127 }, 11128 outputs: []outputInfo{ 11129 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11130 }, 11131 }, 11132 }, 11133 { 11134 name: "ADDconst", 11135 auxType: auxInt64, 11136 argLen: 1, 11137 asm: arm64.AADD, 11138 reg: regInfo{ 11139 inputs: []inputInfo{ 11140 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 11141 }, 11142 outputs: []outputInfo{ 11143 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11144 }, 11145 }, 11146 }, 11147 { 11148 name: "SUB", 11149 argLen: 2, 11150 asm: arm64.ASUB, 11151 reg: regInfo{ 11152 inputs: []inputInfo{ 11153 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11154 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11155 }, 11156 outputs: []outputInfo{ 11157 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11158 }, 11159 }, 11160 }, 11161 { 11162 name: "SUBconst", 11163 auxType: auxInt64, 11164 argLen: 1, 11165 asm: arm64.ASUB, 11166 reg: regInfo{ 11167 inputs: []inputInfo{ 11168 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11169 }, 11170 outputs: []outputInfo{ 11171 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11172 }, 11173 }, 11174 }, 11175 { 11176 name: "MUL", 11177 argLen: 2, 11178 commutative: true, 11179 asm: arm64.AMUL, 11180 reg: regInfo{ 11181 inputs: []inputInfo{ 11182 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11183 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11184 }, 11185 outputs: []outputInfo{ 11186 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11187 }, 11188 }, 11189 }, 11190 { 11191 name: "MULW", 11192 argLen: 2, 11193 commutative: true, 11194 asm: arm64.AMULW, 11195 reg: regInfo{ 11196 inputs: []inputInfo{ 11197 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11198 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11199 }, 11200 outputs: []outputInfo{ 11201 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11202 }, 11203 }, 11204 }, 11205 { 11206 name: "MULH", 11207 argLen: 2, 11208 commutative: true, 11209 asm: arm64.ASMULH, 11210 reg: regInfo{ 11211 inputs: []inputInfo{ 11212 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11213 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11214 }, 11215 outputs: []outputInfo{ 11216 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11217 }, 11218 }, 11219 }, 11220 { 11221 name: "UMULH", 11222 argLen: 2, 11223 commutative: true, 11224 asm: arm64.AUMULH, 11225 reg: regInfo{ 11226 inputs: []inputInfo{ 11227 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11228 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11229 }, 11230 outputs: []outputInfo{ 11231 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11232 }, 11233 }, 11234 }, 11235 { 11236 name: "MULL", 11237 argLen: 2, 11238 commutative: true, 11239 asm: arm64.ASMULL, 11240 reg: regInfo{ 11241 inputs: []inputInfo{ 11242 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11243 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11244 }, 11245 outputs: []outputInfo{ 11246 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11247 }, 11248 }, 11249 }, 11250 { 11251 name: "UMULL", 11252 argLen: 2, 11253 commutative: true, 11254 asm: arm64.AUMULL, 11255 reg: regInfo{ 11256 inputs: []inputInfo{ 11257 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11258 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11259 }, 11260 outputs: []outputInfo{ 11261 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11262 }, 11263 }, 11264 }, 11265 { 11266 name: "DIV", 11267 argLen: 2, 11268 asm: arm64.ASDIV, 11269 reg: regInfo{ 11270 inputs: []inputInfo{ 11271 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11272 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11273 }, 11274 outputs: []outputInfo{ 11275 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11276 }, 11277 }, 11278 }, 11279 { 11280 name: "UDIV", 11281 argLen: 2, 11282 asm: arm64.AUDIV, 11283 reg: regInfo{ 11284 inputs: []inputInfo{ 11285 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11286 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11287 }, 11288 outputs: []outputInfo{ 11289 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11290 }, 11291 }, 11292 }, 11293 { 11294 name: "DIVW", 11295 argLen: 2, 11296 asm: arm64.ASDIVW, 11297 reg: regInfo{ 11298 inputs: []inputInfo{ 11299 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11300 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11301 }, 11302 outputs: []outputInfo{ 11303 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11304 }, 11305 }, 11306 }, 11307 { 11308 name: "UDIVW", 11309 argLen: 2, 11310 asm: arm64.AUDIVW, 11311 reg: regInfo{ 11312 inputs: []inputInfo{ 11313 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11314 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11315 }, 11316 outputs: []outputInfo{ 11317 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11318 }, 11319 }, 11320 }, 11321 { 11322 name: "MOD", 11323 argLen: 2, 11324 asm: arm64.AREM, 11325 reg: regInfo{ 11326 inputs: []inputInfo{ 11327 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11328 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11329 }, 11330 outputs: []outputInfo{ 11331 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11332 }, 11333 }, 11334 }, 11335 { 11336 name: "UMOD", 11337 argLen: 2, 11338 asm: arm64.AUREM, 11339 reg: regInfo{ 11340 inputs: []inputInfo{ 11341 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11342 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11343 }, 11344 outputs: []outputInfo{ 11345 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11346 }, 11347 }, 11348 }, 11349 { 11350 name: "MODW", 11351 argLen: 2, 11352 asm: arm64.AREMW, 11353 reg: regInfo{ 11354 inputs: []inputInfo{ 11355 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11356 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11357 }, 11358 outputs: []outputInfo{ 11359 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11360 }, 11361 }, 11362 }, 11363 { 11364 name: "UMODW", 11365 argLen: 2, 11366 asm: arm64.AUREMW, 11367 reg: regInfo{ 11368 inputs: []inputInfo{ 11369 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11370 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11371 }, 11372 outputs: []outputInfo{ 11373 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11374 }, 11375 }, 11376 }, 11377 { 11378 name: "FADDS", 11379 argLen: 2, 11380 commutative: true, 11381 asm: arm64.AFADDS, 11382 reg: regInfo{ 11383 inputs: []inputInfo{ 11384 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11385 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11386 }, 11387 outputs: []outputInfo{ 11388 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11389 }, 11390 }, 11391 }, 11392 { 11393 name: "FADDD", 11394 argLen: 2, 11395 commutative: true, 11396 asm: arm64.AFADDD, 11397 reg: regInfo{ 11398 inputs: []inputInfo{ 11399 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11400 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11401 }, 11402 outputs: []outputInfo{ 11403 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11404 }, 11405 }, 11406 }, 11407 { 11408 name: "FSUBS", 11409 argLen: 2, 11410 asm: arm64.AFSUBS, 11411 reg: regInfo{ 11412 inputs: []inputInfo{ 11413 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11414 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11415 }, 11416 outputs: []outputInfo{ 11417 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11418 }, 11419 }, 11420 }, 11421 { 11422 name: "FSUBD", 11423 argLen: 2, 11424 asm: arm64.AFSUBD, 11425 reg: regInfo{ 11426 inputs: []inputInfo{ 11427 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11428 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11429 }, 11430 outputs: []outputInfo{ 11431 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11432 }, 11433 }, 11434 }, 11435 { 11436 name: "FMULS", 11437 argLen: 2, 11438 commutative: true, 11439 asm: arm64.AFMULS, 11440 reg: regInfo{ 11441 inputs: []inputInfo{ 11442 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11443 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11444 }, 11445 outputs: []outputInfo{ 11446 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11447 }, 11448 }, 11449 }, 11450 { 11451 name: "FMULD", 11452 argLen: 2, 11453 commutative: true, 11454 asm: arm64.AFMULD, 11455 reg: regInfo{ 11456 inputs: []inputInfo{ 11457 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11458 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11459 }, 11460 outputs: []outputInfo{ 11461 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11462 }, 11463 }, 11464 }, 11465 { 11466 name: "FDIVS", 11467 argLen: 2, 11468 asm: arm64.AFDIVS, 11469 reg: regInfo{ 11470 inputs: []inputInfo{ 11471 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11472 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11473 }, 11474 outputs: []outputInfo{ 11475 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11476 }, 11477 }, 11478 }, 11479 { 11480 name: "FDIVD", 11481 argLen: 2, 11482 asm: arm64.AFDIVD, 11483 reg: regInfo{ 11484 inputs: []inputInfo{ 11485 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11486 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11487 }, 11488 outputs: []outputInfo{ 11489 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11490 }, 11491 }, 11492 }, 11493 { 11494 name: "AND", 11495 argLen: 2, 11496 commutative: true, 11497 asm: arm64.AAND, 11498 reg: regInfo{ 11499 inputs: []inputInfo{ 11500 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11501 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11502 }, 11503 outputs: []outputInfo{ 11504 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11505 }, 11506 }, 11507 }, 11508 { 11509 name: "ANDconst", 11510 auxType: auxInt64, 11511 argLen: 1, 11512 asm: arm64.AAND, 11513 reg: regInfo{ 11514 inputs: []inputInfo{ 11515 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11516 }, 11517 outputs: []outputInfo{ 11518 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11519 }, 11520 }, 11521 }, 11522 { 11523 name: "OR", 11524 argLen: 2, 11525 commutative: true, 11526 asm: arm64.AORR, 11527 reg: regInfo{ 11528 inputs: []inputInfo{ 11529 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11530 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11531 }, 11532 outputs: []outputInfo{ 11533 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11534 }, 11535 }, 11536 }, 11537 { 11538 name: "ORconst", 11539 auxType: auxInt64, 11540 argLen: 1, 11541 asm: arm64.AORR, 11542 reg: regInfo{ 11543 inputs: []inputInfo{ 11544 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11545 }, 11546 outputs: []outputInfo{ 11547 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11548 }, 11549 }, 11550 }, 11551 { 11552 name: "XOR", 11553 argLen: 2, 11554 commutative: true, 11555 asm: arm64.AEOR, 11556 reg: regInfo{ 11557 inputs: []inputInfo{ 11558 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11559 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11560 }, 11561 outputs: []outputInfo{ 11562 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11563 }, 11564 }, 11565 }, 11566 { 11567 name: "XORconst", 11568 auxType: auxInt64, 11569 argLen: 1, 11570 asm: arm64.AEOR, 11571 reg: regInfo{ 11572 inputs: []inputInfo{ 11573 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11574 }, 11575 outputs: []outputInfo{ 11576 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11577 }, 11578 }, 11579 }, 11580 { 11581 name: "BIC", 11582 argLen: 2, 11583 asm: arm64.ABIC, 11584 reg: regInfo{ 11585 inputs: []inputInfo{ 11586 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11587 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11588 }, 11589 outputs: []outputInfo{ 11590 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11591 }, 11592 }, 11593 }, 11594 { 11595 name: "BICconst", 11596 auxType: auxInt64, 11597 argLen: 1, 11598 asm: arm64.ABIC, 11599 reg: regInfo{ 11600 inputs: []inputInfo{ 11601 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11602 }, 11603 outputs: []outputInfo{ 11604 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11605 }, 11606 }, 11607 }, 11608 { 11609 name: "MVN", 11610 argLen: 1, 11611 asm: arm64.AMVN, 11612 reg: regInfo{ 11613 inputs: []inputInfo{ 11614 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11615 }, 11616 outputs: []outputInfo{ 11617 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11618 }, 11619 }, 11620 }, 11621 { 11622 name: "NEG", 11623 argLen: 1, 11624 asm: arm64.ANEG, 11625 reg: regInfo{ 11626 inputs: []inputInfo{ 11627 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11628 }, 11629 outputs: []outputInfo{ 11630 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11631 }, 11632 }, 11633 }, 11634 { 11635 name: "FNEGS", 11636 argLen: 1, 11637 asm: arm64.AFNEGS, 11638 reg: regInfo{ 11639 inputs: []inputInfo{ 11640 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11641 }, 11642 outputs: []outputInfo{ 11643 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11644 }, 11645 }, 11646 }, 11647 { 11648 name: "FNEGD", 11649 argLen: 1, 11650 asm: arm64.AFNEGD, 11651 reg: regInfo{ 11652 inputs: []inputInfo{ 11653 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11654 }, 11655 outputs: []outputInfo{ 11656 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11657 }, 11658 }, 11659 }, 11660 { 11661 name: "FSQRTD", 11662 argLen: 1, 11663 asm: arm64.AFSQRTD, 11664 reg: regInfo{ 11665 inputs: []inputInfo{ 11666 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11667 }, 11668 outputs: []outputInfo{ 11669 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11670 }, 11671 }, 11672 }, 11673 { 11674 name: "REV", 11675 argLen: 1, 11676 asm: arm64.AREV, 11677 reg: regInfo{ 11678 inputs: []inputInfo{ 11679 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11680 }, 11681 outputs: []outputInfo{ 11682 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11683 }, 11684 }, 11685 }, 11686 { 11687 name: "REVW", 11688 argLen: 1, 11689 asm: arm64.AREVW, 11690 reg: regInfo{ 11691 inputs: []inputInfo{ 11692 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11693 }, 11694 outputs: []outputInfo{ 11695 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11696 }, 11697 }, 11698 }, 11699 { 11700 name: "REV16W", 11701 argLen: 1, 11702 asm: arm64.AREV16W, 11703 reg: regInfo{ 11704 inputs: []inputInfo{ 11705 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11706 }, 11707 outputs: []outputInfo{ 11708 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11709 }, 11710 }, 11711 }, 11712 { 11713 name: "RBIT", 11714 argLen: 1, 11715 asm: arm64.ARBIT, 11716 reg: regInfo{ 11717 inputs: []inputInfo{ 11718 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11719 }, 11720 outputs: []outputInfo{ 11721 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11722 }, 11723 }, 11724 }, 11725 { 11726 name: "RBITW", 11727 argLen: 1, 11728 asm: arm64.ARBITW, 11729 reg: regInfo{ 11730 inputs: []inputInfo{ 11731 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11732 }, 11733 outputs: []outputInfo{ 11734 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11735 }, 11736 }, 11737 }, 11738 { 11739 name: "CLZ", 11740 argLen: 1, 11741 asm: arm64.ACLZ, 11742 reg: regInfo{ 11743 inputs: []inputInfo{ 11744 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11745 }, 11746 outputs: []outputInfo{ 11747 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11748 }, 11749 }, 11750 }, 11751 { 11752 name: "CLZW", 11753 argLen: 1, 11754 asm: arm64.ACLZW, 11755 reg: regInfo{ 11756 inputs: []inputInfo{ 11757 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11758 }, 11759 outputs: []outputInfo{ 11760 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11761 }, 11762 }, 11763 }, 11764 { 11765 name: "SLL", 11766 argLen: 2, 11767 asm: arm64.ALSL, 11768 reg: regInfo{ 11769 inputs: []inputInfo{ 11770 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11771 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11772 }, 11773 outputs: []outputInfo{ 11774 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11775 }, 11776 }, 11777 }, 11778 { 11779 name: "SLLconst", 11780 auxType: auxInt64, 11781 argLen: 1, 11782 asm: arm64.ALSL, 11783 reg: regInfo{ 11784 inputs: []inputInfo{ 11785 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11786 }, 11787 outputs: []outputInfo{ 11788 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11789 }, 11790 }, 11791 }, 11792 { 11793 name: "SRL", 11794 argLen: 2, 11795 asm: arm64.ALSR, 11796 reg: regInfo{ 11797 inputs: []inputInfo{ 11798 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11799 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11800 }, 11801 outputs: []outputInfo{ 11802 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11803 }, 11804 }, 11805 }, 11806 { 11807 name: "SRLconst", 11808 auxType: auxInt64, 11809 argLen: 1, 11810 asm: arm64.ALSR, 11811 reg: regInfo{ 11812 inputs: []inputInfo{ 11813 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11814 }, 11815 outputs: []outputInfo{ 11816 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11817 }, 11818 }, 11819 }, 11820 { 11821 name: "SRA", 11822 argLen: 2, 11823 asm: arm64.AASR, 11824 reg: regInfo{ 11825 inputs: []inputInfo{ 11826 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11827 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11828 }, 11829 outputs: []outputInfo{ 11830 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11831 }, 11832 }, 11833 }, 11834 { 11835 name: "SRAconst", 11836 auxType: auxInt64, 11837 argLen: 1, 11838 asm: arm64.AASR, 11839 reg: regInfo{ 11840 inputs: []inputInfo{ 11841 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11842 }, 11843 outputs: []outputInfo{ 11844 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11845 }, 11846 }, 11847 }, 11848 { 11849 name: "RORconst", 11850 auxType: auxInt64, 11851 argLen: 1, 11852 asm: arm64.AROR, 11853 reg: regInfo{ 11854 inputs: []inputInfo{ 11855 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11856 }, 11857 outputs: []outputInfo{ 11858 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11859 }, 11860 }, 11861 }, 11862 { 11863 name: "RORWconst", 11864 auxType: auxInt64, 11865 argLen: 1, 11866 asm: arm64.ARORW, 11867 reg: regInfo{ 11868 inputs: []inputInfo{ 11869 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11870 }, 11871 outputs: []outputInfo{ 11872 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11873 }, 11874 }, 11875 }, 11876 { 11877 name: "CMP", 11878 argLen: 2, 11879 asm: arm64.ACMP, 11880 reg: regInfo{ 11881 inputs: []inputInfo{ 11882 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11883 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11884 }, 11885 }, 11886 }, 11887 { 11888 name: "CMPconst", 11889 auxType: auxInt64, 11890 argLen: 1, 11891 asm: arm64.ACMP, 11892 reg: regInfo{ 11893 inputs: []inputInfo{ 11894 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11895 }, 11896 }, 11897 }, 11898 { 11899 name: "CMPW", 11900 argLen: 2, 11901 asm: arm64.ACMPW, 11902 reg: regInfo{ 11903 inputs: []inputInfo{ 11904 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11905 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11906 }, 11907 }, 11908 }, 11909 { 11910 name: "CMPWconst", 11911 auxType: auxInt32, 11912 argLen: 1, 11913 asm: arm64.ACMPW, 11914 reg: regInfo{ 11915 inputs: []inputInfo{ 11916 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11917 }, 11918 }, 11919 }, 11920 { 11921 name: "CMN", 11922 argLen: 2, 11923 asm: arm64.ACMN, 11924 reg: regInfo{ 11925 inputs: []inputInfo{ 11926 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11927 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11928 }, 11929 }, 11930 }, 11931 { 11932 name: "CMNconst", 11933 auxType: auxInt64, 11934 argLen: 1, 11935 asm: arm64.ACMN, 11936 reg: regInfo{ 11937 inputs: []inputInfo{ 11938 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11939 }, 11940 }, 11941 }, 11942 { 11943 name: "CMNW", 11944 argLen: 2, 11945 asm: arm64.ACMNW, 11946 reg: regInfo{ 11947 inputs: []inputInfo{ 11948 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11949 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11950 }, 11951 }, 11952 }, 11953 { 11954 name: "CMNWconst", 11955 auxType: auxInt32, 11956 argLen: 1, 11957 asm: arm64.ACMNW, 11958 reg: regInfo{ 11959 inputs: []inputInfo{ 11960 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11961 }, 11962 }, 11963 }, 11964 { 11965 name: "FCMPS", 11966 argLen: 2, 11967 asm: arm64.AFCMPS, 11968 reg: regInfo{ 11969 inputs: []inputInfo{ 11970 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11971 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11972 }, 11973 }, 11974 }, 11975 { 11976 name: "FCMPD", 11977 argLen: 2, 11978 asm: arm64.AFCMPD, 11979 reg: regInfo{ 11980 inputs: []inputInfo{ 11981 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11982 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11983 }, 11984 }, 11985 }, 11986 { 11987 name: "ADDshiftLL", 11988 auxType: auxInt64, 11989 argLen: 2, 11990 asm: arm64.AADD, 11991 reg: regInfo{ 11992 inputs: []inputInfo{ 11993 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11994 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11995 }, 11996 outputs: []outputInfo{ 11997 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11998 }, 11999 }, 12000 }, 12001 { 12002 name: "ADDshiftRL", 12003 auxType: auxInt64, 12004 argLen: 2, 12005 asm: arm64.AADD, 12006 reg: regInfo{ 12007 inputs: []inputInfo{ 12008 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12009 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12010 }, 12011 outputs: []outputInfo{ 12012 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12013 }, 12014 }, 12015 }, 12016 { 12017 name: "ADDshiftRA", 12018 auxType: auxInt64, 12019 argLen: 2, 12020 asm: arm64.AADD, 12021 reg: regInfo{ 12022 inputs: []inputInfo{ 12023 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12024 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12025 }, 12026 outputs: []outputInfo{ 12027 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12028 }, 12029 }, 12030 }, 12031 { 12032 name: "SUBshiftLL", 12033 auxType: auxInt64, 12034 argLen: 2, 12035 asm: arm64.ASUB, 12036 reg: regInfo{ 12037 inputs: []inputInfo{ 12038 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12039 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12040 }, 12041 outputs: []outputInfo{ 12042 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12043 }, 12044 }, 12045 }, 12046 { 12047 name: "SUBshiftRL", 12048 auxType: auxInt64, 12049 argLen: 2, 12050 asm: arm64.ASUB, 12051 reg: regInfo{ 12052 inputs: []inputInfo{ 12053 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12054 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12055 }, 12056 outputs: []outputInfo{ 12057 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12058 }, 12059 }, 12060 }, 12061 { 12062 name: "SUBshiftRA", 12063 auxType: auxInt64, 12064 argLen: 2, 12065 asm: arm64.ASUB, 12066 reg: regInfo{ 12067 inputs: []inputInfo{ 12068 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12069 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12070 }, 12071 outputs: []outputInfo{ 12072 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12073 }, 12074 }, 12075 }, 12076 { 12077 name: "ANDshiftLL", 12078 auxType: auxInt64, 12079 argLen: 2, 12080 asm: arm64.AAND, 12081 reg: regInfo{ 12082 inputs: []inputInfo{ 12083 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12084 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12085 }, 12086 outputs: []outputInfo{ 12087 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12088 }, 12089 }, 12090 }, 12091 { 12092 name: "ANDshiftRL", 12093 auxType: auxInt64, 12094 argLen: 2, 12095 asm: arm64.AAND, 12096 reg: regInfo{ 12097 inputs: []inputInfo{ 12098 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12099 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12100 }, 12101 outputs: []outputInfo{ 12102 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12103 }, 12104 }, 12105 }, 12106 { 12107 name: "ANDshiftRA", 12108 auxType: auxInt64, 12109 argLen: 2, 12110 asm: arm64.AAND, 12111 reg: regInfo{ 12112 inputs: []inputInfo{ 12113 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12114 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12115 }, 12116 outputs: []outputInfo{ 12117 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12118 }, 12119 }, 12120 }, 12121 { 12122 name: "ORshiftLL", 12123 auxType: auxInt64, 12124 argLen: 2, 12125 asm: arm64.AORR, 12126 reg: regInfo{ 12127 inputs: []inputInfo{ 12128 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12129 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12130 }, 12131 outputs: []outputInfo{ 12132 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12133 }, 12134 }, 12135 }, 12136 { 12137 name: "ORshiftRL", 12138 auxType: auxInt64, 12139 argLen: 2, 12140 asm: arm64.AORR, 12141 reg: regInfo{ 12142 inputs: []inputInfo{ 12143 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12144 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12145 }, 12146 outputs: []outputInfo{ 12147 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12148 }, 12149 }, 12150 }, 12151 { 12152 name: "ORshiftRA", 12153 auxType: auxInt64, 12154 argLen: 2, 12155 asm: arm64.AORR, 12156 reg: regInfo{ 12157 inputs: []inputInfo{ 12158 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12159 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12160 }, 12161 outputs: []outputInfo{ 12162 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12163 }, 12164 }, 12165 }, 12166 { 12167 name: "XORshiftLL", 12168 auxType: auxInt64, 12169 argLen: 2, 12170 asm: arm64.AEOR, 12171 reg: regInfo{ 12172 inputs: []inputInfo{ 12173 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12174 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12175 }, 12176 outputs: []outputInfo{ 12177 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12178 }, 12179 }, 12180 }, 12181 { 12182 name: "XORshiftRL", 12183 auxType: auxInt64, 12184 argLen: 2, 12185 asm: arm64.AEOR, 12186 reg: regInfo{ 12187 inputs: []inputInfo{ 12188 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12189 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12190 }, 12191 outputs: []outputInfo{ 12192 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12193 }, 12194 }, 12195 }, 12196 { 12197 name: "XORshiftRA", 12198 auxType: auxInt64, 12199 argLen: 2, 12200 asm: arm64.AEOR, 12201 reg: regInfo{ 12202 inputs: []inputInfo{ 12203 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12204 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12205 }, 12206 outputs: []outputInfo{ 12207 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12208 }, 12209 }, 12210 }, 12211 { 12212 name: "BICshiftLL", 12213 auxType: auxInt64, 12214 argLen: 2, 12215 asm: arm64.ABIC, 12216 reg: regInfo{ 12217 inputs: []inputInfo{ 12218 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12219 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12220 }, 12221 outputs: []outputInfo{ 12222 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12223 }, 12224 }, 12225 }, 12226 { 12227 name: "BICshiftRL", 12228 auxType: auxInt64, 12229 argLen: 2, 12230 asm: arm64.ABIC, 12231 reg: regInfo{ 12232 inputs: []inputInfo{ 12233 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12234 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12235 }, 12236 outputs: []outputInfo{ 12237 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12238 }, 12239 }, 12240 }, 12241 { 12242 name: "BICshiftRA", 12243 auxType: auxInt64, 12244 argLen: 2, 12245 asm: arm64.ABIC, 12246 reg: regInfo{ 12247 inputs: []inputInfo{ 12248 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12249 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12250 }, 12251 outputs: []outputInfo{ 12252 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12253 }, 12254 }, 12255 }, 12256 { 12257 name: "CMPshiftLL", 12258 auxType: auxInt64, 12259 argLen: 2, 12260 asm: arm64.ACMP, 12261 reg: regInfo{ 12262 inputs: []inputInfo{ 12263 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12264 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12265 }, 12266 }, 12267 }, 12268 { 12269 name: "CMPshiftRL", 12270 auxType: auxInt64, 12271 argLen: 2, 12272 asm: arm64.ACMP, 12273 reg: regInfo{ 12274 inputs: []inputInfo{ 12275 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12276 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12277 }, 12278 }, 12279 }, 12280 { 12281 name: "CMPshiftRA", 12282 auxType: auxInt64, 12283 argLen: 2, 12284 asm: arm64.ACMP, 12285 reg: regInfo{ 12286 inputs: []inputInfo{ 12287 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12288 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12289 }, 12290 }, 12291 }, 12292 { 12293 name: "MOVDconst", 12294 auxType: auxInt64, 12295 argLen: 0, 12296 rematerializeable: true, 12297 asm: arm64.AMOVD, 12298 reg: regInfo{ 12299 outputs: []outputInfo{ 12300 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12301 }, 12302 }, 12303 }, 12304 { 12305 name: "FMOVSconst", 12306 auxType: auxFloat64, 12307 argLen: 0, 12308 rematerializeable: true, 12309 asm: arm64.AFMOVS, 12310 reg: regInfo{ 12311 outputs: []outputInfo{ 12312 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12313 }, 12314 }, 12315 }, 12316 { 12317 name: "FMOVDconst", 12318 auxType: auxFloat64, 12319 argLen: 0, 12320 rematerializeable: true, 12321 asm: arm64.AFMOVD, 12322 reg: regInfo{ 12323 outputs: []outputInfo{ 12324 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12325 }, 12326 }, 12327 }, 12328 { 12329 name: "MOVDaddr", 12330 auxType: auxSymOff, 12331 argLen: 1, 12332 rematerializeable: true, 12333 symEffect: SymAddr, 12334 asm: arm64.AMOVD, 12335 reg: regInfo{ 12336 inputs: []inputInfo{ 12337 {0, 9223372037928517632}, // SP SB 12338 }, 12339 outputs: []outputInfo{ 12340 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12341 }, 12342 }, 12343 }, 12344 { 12345 name: "MOVBload", 12346 auxType: auxSymOff, 12347 argLen: 2, 12348 faultOnNilArg0: true, 12349 symEffect: SymRead, 12350 asm: arm64.AMOVB, 12351 reg: regInfo{ 12352 inputs: []inputInfo{ 12353 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12354 }, 12355 outputs: []outputInfo{ 12356 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12357 }, 12358 }, 12359 }, 12360 { 12361 name: "MOVBUload", 12362 auxType: auxSymOff, 12363 argLen: 2, 12364 faultOnNilArg0: true, 12365 symEffect: SymRead, 12366 asm: arm64.AMOVBU, 12367 reg: regInfo{ 12368 inputs: []inputInfo{ 12369 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12370 }, 12371 outputs: []outputInfo{ 12372 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12373 }, 12374 }, 12375 }, 12376 { 12377 name: "MOVHload", 12378 auxType: auxSymOff, 12379 argLen: 2, 12380 faultOnNilArg0: true, 12381 symEffect: SymRead, 12382 asm: arm64.AMOVH, 12383 reg: regInfo{ 12384 inputs: []inputInfo{ 12385 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12386 }, 12387 outputs: []outputInfo{ 12388 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12389 }, 12390 }, 12391 }, 12392 { 12393 name: "MOVHUload", 12394 auxType: auxSymOff, 12395 argLen: 2, 12396 faultOnNilArg0: true, 12397 symEffect: SymRead, 12398 asm: arm64.AMOVHU, 12399 reg: regInfo{ 12400 inputs: []inputInfo{ 12401 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12402 }, 12403 outputs: []outputInfo{ 12404 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12405 }, 12406 }, 12407 }, 12408 { 12409 name: "MOVWload", 12410 auxType: auxSymOff, 12411 argLen: 2, 12412 faultOnNilArg0: true, 12413 symEffect: SymRead, 12414 asm: arm64.AMOVW, 12415 reg: regInfo{ 12416 inputs: []inputInfo{ 12417 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12418 }, 12419 outputs: []outputInfo{ 12420 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12421 }, 12422 }, 12423 }, 12424 { 12425 name: "MOVWUload", 12426 auxType: auxSymOff, 12427 argLen: 2, 12428 faultOnNilArg0: true, 12429 symEffect: SymRead, 12430 asm: arm64.AMOVWU, 12431 reg: regInfo{ 12432 inputs: []inputInfo{ 12433 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12434 }, 12435 outputs: []outputInfo{ 12436 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12437 }, 12438 }, 12439 }, 12440 { 12441 name: "MOVDload", 12442 auxType: auxSymOff, 12443 argLen: 2, 12444 faultOnNilArg0: true, 12445 symEffect: SymRead, 12446 asm: arm64.AMOVD, 12447 reg: regInfo{ 12448 inputs: []inputInfo{ 12449 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12450 }, 12451 outputs: []outputInfo{ 12452 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12453 }, 12454 }, 12455 }, 12456 { 12457 name: "FMOVSload", 12458 auxType: auxSymOff, 12459 argLen: 2, 12460 faultOnNilArg0: true, 12461 symEffect: SymRead, 12462 asm: arm64.AFMOVS, 12463 reg: regInfo{ 12464 inputs: []inputInfo{ 12465 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12466 }, 12467 outputs: []outputInfo{ 12468 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12469 }, 12470 }, 12471 }, 12472 { 12473 name: "FMOVDload", 12474 auxType: auxSymOff, 12475 argLen: 2, 12476 faultOnNilArg0: true, 12477 symEffect: SymRead, 12478 asm: arm64.AFMOVD, 12479 reg: regInfo{ 12480 inputs: []inputInfo{ 12481 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12482 }, 12483 outputs: []outputInfo{ 12484 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12485 }, 12486 }, 12487 }, 12488 { 12489 name: "MOVBstore", 12490 auxType: auxSymOff, 12491 argLen: 3, 12492 faultOnNilArg0: true, 12493 symEffect: SymWrite, 12494 asm: arm64.AMOVB, 12495 reg: regInfo{ 12496 inputs: []inputInfo{ 12497 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12498 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12499 }, 12500 }, 12501 }, 12502 { 12503 name: "MOVHstore", 12504 auxType: auxSymOff, 12505 argLen: 3, 12506 faultOnNilArg0: true, 12507 symEffect: SymWrite, 12508 asm: arm64.AMOVH, 12509 reg: regInfo{ 12510 inputs: []inputInfo{ 12511 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12512 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12513 }, 12514 }, 12515 }, 12516 { 12517 name: "MOVWstore", 12518 auxType: auxSymOff, 12519 argLen: 3, 12520 faultOnNilArg0: true, 12521 symEffect: SymWrite, 12522 asm: arm64.AMOVW, 12523 reg: regInfo{ 12524 inputs: []inputInfo{ 12525 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12526 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12527 }, 12528 }, 12529 }, 12530 { 12531 name: "MOVDstore", 12532 auxType: auxSymOff, 12533 argLen: 3, 12534 faultOnNilArg0: true, 12535 symEffect: SymWrite, 12536 asm: arm64.AMOVD, 12537 reg: regInfo{ 12538 inputs: []inputInfo{ 12539 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12540 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12541 }, 12542 }, 12543 }, 12544 { 12545 name: "FMOVSstore", 12546 auxType: auxSymOff, 12547 argLen: 3, 12548 faultOnNilArg0: true, 12549 symEffect: SymWrite, 12550 asm: arm64.AFMOVS, 12551 reg: regInfo{ 12552 inputs: []inputInfo{ 12553 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12554 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12555 }, 12556 }, 12557 }, 12558 { 12559 name: "FMOVDstore", 12560 auxType: auxSymOff, 12561 argLen: 3, 12562 faultOnNilArg0: true, 12563 symEffect: SymWrite, 12564 asm: arm64.AFMOVD, 12565 reg: regInfo{ 12566 inputs: []inputInfo{ 12567 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12568 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12569 }, 12570 }, 12571 }, 12572 { 12573 name: "MOVBstorezero", 12574 auxType: auxSymOff, 12575 argLen: 2, 12576 faultOnNilArg0: true, 12577 symEffect: SymWrite, 12578 asm: arm64.AMOVB, 12579 reg: regInfo{ 12580 inputs: []inputInfo{ 12581 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12582 }, 12583 }, 12584 }, 12585 { 12586 name: "MOVHstorezero", 12587 auxType: auxSymOff, 12588 argLen: 2, 12589 faultOnNilArg0: true, 12590 symEffect: SymWrite, 12591 asm: arm64.AMOVH, 12592 reg: regInfo{ 12593 inputs: []inputInfo{ 12594 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12595 }, 12596 }, 12597 }, 12598 { 12599 name: "MOVWstorezero", 12600 auxType: auxSymOff, 12601 argLen: 2, 12602 faultOnNilArg0: true, 12603 symEffect: SymWrite, 12604 asm: arm64.AMOVW, 12605 reg: regInfo{ 12606 inputs: []inputInfo{ 12607 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12608 }, 12609 }, 12610 }, 12611 { 12612 name: "MOVDstorezero", 12613 auxType: auxSymOff, 12614 argLen: 2, 12615 faultOnNilArg0: true, 12616 symEffect: SymWrite, 12617 asm: arm64.AMOVD, 12618 reg: regInfo{ 12619 inputs: []inputInfo{ 12620 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12621 }, 12622 }, 12623 }, 12624 { 12625 name: "MOVBreg", 12626 argLen: 1, 12627 asm: arm64.AMOVB, 12628 reg: regInfo{ 12629 inputs: []inputInfo{ 12630 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12631 }, 12632 outputs: []outputInfo{ 12633 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12634 }, 12635 }, 12636 }, 12637 { 12638 name: "MOVBUreg", 12639 argLen: 1, 12640 asm: arm64.AMOVBU, 12641 reg: regInfo{ 12642 inputs: []inputInfo{ 12643 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12644 }, 12645 outputs: []outputInfo{ 12646 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12647 }, 12648 }, 12649 }, 12650 { 12651 name: "MOVHreg", 12652 argLen: 1, 12653 asm: arm64.AMOVH, 12654 reg: regInfo{ 12655 inputs: []inputInfo{ 12656 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12657 }, 12658 outputs: []outputInfo{ 12659 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12660 }, 12661 }, 12662 }, 12663 { 12664 name: "MOVHUreg", 12665 argLen: 1, 12666 asm: arm64.AMOVHU, 12667 reg: regInfo{ 12668 inputs: []inputInfo{ 12669 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12670 }, 12671 outputs: []outputInfo{ 12672 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12673 }, 12674 }, 12675 }, 12676 { 12677 name: "MOVWreg", 12678 argLen: 1, 12679 asm: arm64.AMOVW, 12680 reg: regInfo{ 12681 inputs: []inputInfo{ 12682 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12683 }, 12684 outputs: []outputInfo{ 12685 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12686 }, 12687 }, 12688 }, 12689 { 12690 name: "MOVWUreg", 12691 argLen: 1, 12692 asm: arm64.AMOVWU, 12693 reg: regInfo{ 12694 inputs: []inputInfo{ 12695 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12696 }, 12697 outputs: []outputInfo{ 12698 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12699 }, 12700 }, 12701 }, 12702 { 12703 name: "MOVDreg", 12704 argLen: 1, 12705 asm: arm64.AMOVD, 12706 reg: regInfo{ 12707 inputs: []inputInfo{ 12708 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12709 }, 12710 outputs: []outputInfo{ 12711 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12712 }, 12713 }, 12714 }, 12715 { 12716 name: "MOVDnop", 12717 argLen: 1, 12718 resultInArg0: true, 12719 reg: regInfo{ 12720 inputs: []inputInfo{ 12721 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12722 }, 12723 outputs: []outputInfo{ 12724 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12725 }, 12726 }, 12727 }, 12728 { 12729 name: "SCVTFWS", 12730 argLen: 1, 12731 asm: arm64.ASCVTFWS, 12732 reg: regInfo{ 12733 inputs: []inputInfo{ 12734 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12735 }, 12736 outputs: []outputInfo{ 12737 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12738 }, 12739 }, 12740 }, 12741 { 12742 name: "SCVTFWD", 12743 argLen: 1, 12744 asm: arm64.ASCVTFWD, 12745 reg: regInfo{ 12746 inputs: []inputInfo{ 12747 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12748 }, 12749 outputs: []outputInfo{ 12750 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12751 }, 12752 }, 12753 }, 12754 { 12755 name: "UCVTFWS", 12756 argLen: 1, 12757 asm: arm64.AUCVTFWS, 12758 reg: regInfo{ 12759 inputs: []inputInfo{ 12760 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12761 }, 12762 outputs: []outputInfo{ 12763 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12764 }, 12765 }, 12766 }, 12767 { 12768 name: "UCVTFWD", 12769 argLen: 1, 12770 asm: arm64.AUCVTFWD, 12771 reg: regInfo{ 12772 inputs: []inputInfo{ 12773 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12774 }, 12775 outputs: []outputInfo{ 12776 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12777 }, 12778 }, 12779 }, 12780 { 12781 name: "SCVTFS", 12782 argLen: 1, 12783 asm: arm64.ASCVTFS, 12784 reg: regInfo{ 12785 inputs: []inputInfo{ 12786 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12787 }, 12788 outputs: []outputInfo{ 12789 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12790 }, 12791 }, 12792 }, 12793 { 12794 name: "SCVTFD", 12795 argLen: 1, 12796 asm: arm64.ASCVTFD, 12797 reg: regInfo{ 12798 inputs: []inputInfo{ 12799 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12800 }, 12801 outputs: []outputInfo{ 12802 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12803 }, 12804 }, 12805 }, 12806 { 12807 name: "UCVTFS", 12808 argLen: 1, 12809 asm: arm64.AUCVTFS, 12810 reg: regInfo{ 12811 inputs: []inputInfo{ 12812 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12813 }, 12814 outputs: []outputInfo{ 12815 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12816 }, 12817 }, 12818 }, 12819 { 12820 name: "UCVTFD", 12821 argLen: 1, 12822 asm: arm64.AUCVTFD, 12823 reg: regInfo{ 12824 inputs: []inputInfo{ 12825 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12826 }, 12827 outputs: []outputInfo{ 12828 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12829 }, 12830 }, 12831 }, 12832 { 12833 name: "FCVTZSSW", 12834 argLen: 1, 12835 asm: arm64.AFCVTZSSW, 12836 reg: regInfo{ 12837 inputs: []inputInfo{ 12838 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12839 }, 12840 outputs: []outputInfo{ 12841 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12842 }, 12843 }, 12844 }, 12845 { 12846 name: "FCVTZSDW", 12847 argLen: 1, 12848 asm: arm64.AFCVTZSDW, 12849 reg: regInfo{ 12850 inputs: []inputInfo{ 12851 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12852 }, 12853 outputs: []outputInfo{ 12854 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12855 }, 12856 }, 12857 }, 12858 { 12859 name: "FCVTZUSW", 12860 argLen: 1, 12861 asm: arm64.AFCVTZUSW, 12862 reg: regInfo{ 12863 inputs: []inputInfo{ 12864 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12865 }, 12866 outputs: []outputInfo{ 12867 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12868 }, 12869 }, 12870 }, 12871 { 12872 name: "FCVTZUDW", 12873 argLen: 1, 12874 asm: arm64.AFCVTZUDW, 12875 reg: regInfo{ 12876 inputs: []inputInfo{ 12877 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12878 }, 12879 outputs: []outputInfo{ 12880 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12881 }, 12882 }, 12883 }, 12884 { 12885 name: "FCVTZSS", 12886 argLen: 1, 12887 asm: arm64.AFCVTZSS, 12888 reg: regInfo{ 12889 inputs: []inputInfo{ 12890 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12891 }, 12892 outputs: []outputInfo{ 12893 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12894 }, 12895 }, 12896 }, 12897 { 12898 name: "FCVTZSD", 12899 argLen: 1, 12900 asm: arm64.AFCVTZSD, 12901 reg: regInfo{ 12902 inputs: []inputInfo{ 12903 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12904 }, 12905 outputs: []outputInfo{ 12906 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12907 }, 12908 }, 12909 }, 12910 { 12911 name: "FCVTZUS", 12912 argLen: 1, 12913 asm: arm64.AFCVTZUS, 12914 reg: regInfo{ 12915 inputs: []inputInfo{ 12916 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12917 }, 12918 outputs: []outputInfo{ 12919 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12920 }, 12921 }, 12922 }, 12923 { 12924 name: "FCVTZUD", 12925 argLen: 1, 12926 asm: arm64.AFCVTZUD, 12927 reg: regInfo{ 12928 inputs: []inputInfo{ 12929 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12930 }, 12931 outputs: []outputInfo{ 12932 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12933 }, 12934 }, 12935 }, 12936 { 12937 name: "FCVTSD", 12938 argLen: 1, 12939 asm: arm64.AFCVTSD, 12940 reg: regInfo{ 12941 inputs: []inputInfo{ 12942 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12943 }, 12944 outputs: []outputInfo{ 12945 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12946 }, 12947 }, 12948 }, 12949 { 12950 name: "FCVTDS", 12951 argLen: 1, 12952 asm: arm64.AFCVTDS, 12953 reg: regInfo{ 12954 inputs: []inputInfo{ 12955 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12956 }, 12957 outputs: []outputInfo{ 12958 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12959 }, 12960 }, 12961 }, 12962 { 12963 name: "CSELULT", 12964 argLen: 3, 12965 asm: arm64.ACSEL, 12966 reg: regInfo{ 12967 inputs: []inputInfo{ 12968 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12969 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12970 }, 12971 outputs: []outputInfo{ 12972 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12973 }, 12974 }, 12975 }, 12976 { 12977 name: "CSELULT0", 12978 argLen: 2, 12979 asm: arm64.ACSEL, 12980 reg: regInfo{ 12981 inputs: []inputInfo{ 12982 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12983 }, 12984 outputs: []outputInfo{ 12985 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12986 }, 12987 }, 12988 }, 12989 { 12990 name: "CALLstatic", 12991 auxType: auxSymOff, 12992 argLen: 1, 12993 clobberFlags: true, 12994 call: true, 12995 symEffect: SymNone, 12996 reg: regInfo{ 12997 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12998 }, 12999 }, 13000 { 13001 name: "CALLclosure", 13002 auxType: auxInt64, 13003 argLen: 3, 13004 clobberFlags: true, 13005 call: true, 13006 reg: regInfo{ 13007 inputs: []inputInfo{ 13008 {1, 67108864}, // R26 13009 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 13010 }, 13011 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13012 }, 13013 }, 13014 { 13015 name: "CALLinter", 13016 auxType: auxInt64, 13017 argLen: 2, 13018 clobberFlags: true, 13019 call: true, 13020 reg: regInfo{ 13021 inputs: []inputInfo{ 13022 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13023 }, 13024 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13025 }, 13026 }, 13027 { 13028 name: "LoweredNilCheck", 13029 argLen: 2, 13030 nilCheck: true, 13031 faultOnNilArg0: true, 13032 reg: regInfo{ 13033 inputs: []inputInfo{ 13034 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13035 }, 13036 }, 13037 }, 13038 { 13039 name: "Equal", 13040 argLen: 1, 13041 reg: regInfo{ 13042 outputs: []outputInfo{ 13043 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13044 }, 13045 }, 13046 }, 13047 { 13048 name: "NotEqual", 13049 argLen: 1, 13050 reg: regInfo{ 13051 outputs: []outputInfo{ 13052 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13053 }, 13054 }, 13055 }, 13056 { 13057 name: "LessThan", 13058 argLen: 1, 13059 reg: regInfo{ 13060 outputs: []outputInfo{ 13061 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13062 }, 13063 }, 13064 }, 13065 { 13066 name: "LessEqual", 13067 argLen: 1, 13068 reg: regInfo{ 13069 outputs: []outputInfo{ 13070 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13071 }, 13072 }, 13073 }, 13074 { 13075 name: "GreaterThan", 13076 argLen: 1, 13077 reg: regInfo{ 13078 outputs: []outputInfo{ 13079 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13080 }, 13081 }, 13082 }, 13083 { 13084 name: "GreaterEqual", 13085 argLen: 1, 13086 reg: regInfo{ 13087 outputs: []outputInfo{ 13088 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13089 }, 13090 }, 13091 }, 13092 { 13093 name: "LessThanU", 13094 argLen: 1, 13095 reg: regInfo{ 13096 outputs: []outputInfo{ 13097 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13098 }, 13099 }, 13100 }, 13101 { 13102 name: "LessEqualU", 13103 argLen: 1, 13104 reg: regInfo{ 13105 outputs: []outputInfo{ 13106 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13107 }, 13108 }, 13109 }, 13110 { 13111 name: "GreaterThanU", 13112 argLen: 1, 13113 reg: regInfo{ 13114 outputs: []outputInfo{ 13115 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13116 }, 13117 }, 13118 }, 13119 { 13120 name: "GreaterEqualU", 13121 argLen: 1, 13122 reg: regInfo{ 13123 outputs: []outputInfo{ 13124 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13125 }, 13126 }, 13127 }, 13128 { 13129 name: "DUFFZERO", 13130 auxType: auxInt64, 13131 argLen: 2, 13132 faultOnNilArg0: true, 13133 reg: regInfo{ 13134 inputs: []inputInfo{ 13135 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13136 }, 13137 clobbers: 536936448, // R16 R30 13138 }, 13139 }, 13140 { 13141 name: "LoweredZero", 13142 argLen: 3, 13143 clobberFlags: true, 13144 faultOnNilArg0: true, 13145 reg: regInfo{ 13146 inputs: []inputInfo{ 13147 {0, 65536}, // R16 13148 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13149 }, 13150 clobbers: 65536, // R16 13151 }, 13152 }, 13153 { 13154 name: "DUFFCOPY", 13155 auxType: auxInt64, 13156 argLen: 3, 13157 faultOnNilArg0: true, 13158 faultOnNilArg1: true, 13159 reg: regInfo{ 13160 inputs: []inputInfo{ 13161 {0, 131072}, // R17 13162 {1, 65536}, // R16 13163 }, 13164 clobbers: 537067520, // R16 R17 R30 13165 }, 13166 }, 13167 { 13168 name: "LoweredMove", 13169 argLen: 4, 13170 clobberFlags: true, 13171 faultOnNilArg0: true, 13172 faultOnNilArg1: true, 13173 reg: regInfo{ 13174 inputs: []inputInfo{ 13175 {0, 131072}, // R17 13176 {1, 65536}, // R16 13177 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13178 }, 13179 clobbers: 196608, // R16 R17 13180 }, 13181 }, 13182 { 13183 name: "LoweredGetClosurePtr", 13184 argLen: 0, 13185 reg: regInfo{ 13186 outputs: []outputInfo{ 13187 {0, 67108864}, // R26 13188 }, 13189 }, 13190 }, 13191 { 13192 name: "MOVDconvert", 13193 argLen: 2, 13194 asm: arm64.AMOVD, 13195 reg: regInfo{ 13196 inputs: []inputInfo{ 13197 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13198 }, 13199 outputs: []outputInfo{ 13200 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13201 }, 13202 }, 13203 }, 13204 { 13205 name: "FlagEQ", 13206 argLen: 0, 13207 reg: regInfo{}, 13208 }, 13209 { 13210 name: "FlagLT_ULT", 13211 argLen: 0, 13212 reg: regInfo{}, 13213 }, 13214 { 13215 name: "FlagLT_UGT", 13216 argLen: 0, 13217 reg: regInfo{}, 13218 }, 13219 { 13220 name: "FlagGT_UGT", 13221 argLen: 0, 13222 reg: regInfo{}, 13223 }, 13224 { 13225 name: "FlagGT_ULT", 13226 argLen: 0, 13227 reg: regInfo{}, 13228 }, 13229 { 13230 name: "InvertFlags", 13231 argLen: 1, 13232 reg: regInfo{}, 13233 }, 13234 { 13235 name: "LDAR", 13236 argLen: 2, 13237 faultOnNilArg0: true, 13238 asm: arm64.ALDAR, 13239 reg: regInfo{ 13240 inputs: []inputInfo{ 13241 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13242 }, 13243 outputs: []outputInfo{ 13244 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13245 }, 13246 }, 13247 }, 13248 { 13249 name: "LDARW", 13250 argLen: 2, 13251 faultOnNilArg0: true, 13252 asm: arm64.ALDARW, 13253 reg: regInfo{ 13254 inputs: []inputInfo{ 13255 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13256 }, 13257 outputs: []outputInfo{ 13258 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13259 }, 13260 }, 13261 }, 13262 { 13263 name: "STLR", 13264 argLen: 3, 13265 faultOnNilArg0: true, 13266 hasSideEffects: true, 13267 asm: arm64.ASTLR, 13268 reg: regInfo{ 13269 inputs: []inputInfo{ 13270 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13271 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13272 }, 13273 }, 13274 }, 13275 { 13276 name: "STLRW", 13277 argLen: 3, 13278 faultOnNilArg0: true, 13279 hasSideEffects: true, 13280 asm: arm64.ASTLRW, 13281 reg: regInfo{ 13282 inputs: []inputInfo{ 13283 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13284 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13285 }, 13286 }, 13287 }, 13288 { 13289 name: "LoweredAtomicExchange64", 13290 argLen: 3, 13291 resultNotInArgs: true, 13292 faultOnNilArg0: true, 13293 hasSideEffects: true, 13294 reg: regInfo{ 13295 inputs: []inputInfo{ 13296 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13297 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13298 }, 13299 outputs: []outputInfo{ 13300 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13301 }, 13302 }, 13303 }, 13304 { 13305 name: "LoweredAtomicExchange32", 13306 argLen: 3, 13307 resultNotInArgs: true, 13308 faultOnNilArg0: true, 13309 hasSideEffects: true, 13310 reg: regInfo{ 13311 inputs: []inputInfo{ 13312 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13313 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13314 }, 13315 outputs: []outputInfo{ 13316 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13317 }, 13318 }, 13319 }, 13320 { 13321 name: "LoweredAtomicAdd64", 13322 argLen: 3, 13323 resultNotInArgs: true, 13324 faultOnNilArg0: true, 13325 hasSideEffects: true, 13326 reg: regInfo{ 13327 inputs: []inputInfo{ 13328 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13329 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13330 }, 13331 outputs: []outputInfo{ 13332 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13333 }, 13334 }, 13335 }, 13336 { 13337 name: "LoweredAtomicAdd32", 13338 argLen: 3, 13339 resultNotInArgs: true, 13340 faultOnNilArg0: true, 13341 hasSideEffects: true, 13342 reg: regInfo{ 13343 inputs: []inputInfo{ 13344 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13345 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13346 }, 13347 outputs: []outputInfo{ 13348 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13349 }, 13350 }, 13351 }, 13352 { 13353 name: "LoweredAtomicCas64", 13354 argLen: 4, 13355 resultNotInArgs: true, 13356 clobberFlags: true, 13357 faultOnNilArg0: true, 13358 hasSideEffects: true, 13359 reg: regInfo{ 13360 inputs: []inputInfo{ 13361 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13362 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13363 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13364 }, 13365 outputs: []outputInfo{ 13366 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13367 }, 13368 }, 13369 }, 13370 { 13371 name: "LoweredAtomicCas32", 13372 argLen: 4, 13373 resultNotInArgs: true, 13374 clobberFlags: true, 13375 faultOnNilArg0: true, 13376 hasSideEffects: true, 13377 reg: regInfo{ 13378 inputs: []inputInfo{ 13379 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13380 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13381 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13382 }, 13383 outputs: []outputInfo{ 13384 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13385 }, 13386 }, 13387 }, 13388 { 13389 name: "LoweredAtomicAnd8", 13390 argLen: 3, 13391 faultOnNilArg0: true, 13392 hasSideEffects: true, 13393 asm: arm64.AAND, 13394 reg: regInfo{ 13395 inputs: []inputInfo{ 13396 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13397 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13398 }, 13399 }, 13400 }, 13401 { 13402 name: "LoweredAtomicOr8", 13403 argLen: 3, 13404 faultOnNilArg0: true, 13405 hasSideEffects: true, 13406 asm: arm64.AORR, 13407 reg: regInfo{ 13408 inputs: []inputInfo{ 13409 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13410 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13411 }, 13412 }, 13413 }, 13414 13415 { 13416 name: "ADD", 13417 argLen: 2, 13418 commutative: true, 13419 asm: mips.AADDU, 13420 reg: regInfo{ 13421 inputs: []inputInfo{ 13422 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13423 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13424 }, 13425 outputs: []outputInfo{ 13426 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13427 }, 13428 }, 13429 }, 13430 { 13431 name: "ADDconst", 13432 auxType: auxInt32, 13433 argLen: 1, 13434 asm: mips.AADDU, 13435 reg: regInfo{ 13436 inputs: []inputInfo{ 13437 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 13438 }, 13439 outputs: []outputInfo{ 13440 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13441 }, 13442 }, 13443 }, 13444 { 13445 name: "SUB", 13446 argLen: 2, 13447 asm: mips.ASUBU, 13448 reg: regInfo{ 13449 inputs: []inputInfo{ 13450 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13451 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13452 }, 13453 outputs: []outputInfo{ 13454 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13455 }, 13456 }, 13457 }, 13458 { 13459 name: "SUBconst", 13460 auxType: auxInt32, 13461 argLen: 1, 13462 asm: mips.ASUBU, 13463 reg: regInfo{ 13464 inputs: []inputInfo{ 13465 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13466 }, 13467 outputs: []outputInfo{ 13468 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13469 }, 13470 }, 13471 }, 13472 { 13473 name: "MUL", 13474 argLen: 2, 13475 commutative: true, 13476 asm: mips.AMUL, 13477 reg: regInfo{ 13478 inputs: []inputInfo{ 13479 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13480 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13481 }, 13482 clobbers: 105553116266496, // HI LO 13483 outputs: []outputInfo{ 13484 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13485 }, 13486 }, 13487 }, 13488 { 13489 name: "MULT", 13490 argLen: 2, 13491 commutative: true, 13492 asm: mips.AMUL, 13493 reg: regInfo{ 13494 inputs: []inputInfo{ 13495 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13496 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13497 }, 13498 outputs: []outputInfo{ 13499 {0, 35184372088832}, // HI 13500 {1, 70368744177664}, // LO 13501 }, 13502 }, 13503 }, 13504 { 13505 name: "MULTU", 13506 argLen: 2, 13507 commutative: true, 13508 asm: mips.AMULU, 13509 reg: regInfo{ 13510 inputs: []inputInfo{ 13511 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13512 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13513 }, 13514 outputs: []outputInfo{ 13515 {0, 35184372088832}, // HI 13516 {1, 70368744177664}, // LO 13517 }, 13518 }, 13519 }, 13520 { 13521 name: "DIV", 13522 argLen: 2, 13523 asm: mips.ADIV, 13524 reg: regInfo{ 13525 inputs: []inputInfo{ 13526 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13527 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13528 }, 13529 outputs: []outputInfo{ 13530 {0, 35184372088832}, // HI 13531 {1, 70368744177664}, // LO 13532 }, 13533 }, 13534 }, 13535 { 13536 name: "DIVU", 13537 argLen: 2, 13538 asm: mips.ADIVU, 13539 reg: regInfo{ 13540 inputs: []inputInfo{ 13541 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13542 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13543 }, 13544 outputs: []outputInfo{ 13545 {0, 35184372088832}, // HI 13546 {1, 70368744177664}, // LO 13547 }, 13548 }, 13549 }, 13550 { 13551 name: "ADDF", 13552 argLen: 2, 13553 commutative: true, 13554 asm: mips.AADDF, 13555 reg: regInfo{ 13556 inputs: []inputInfo{ 13557 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13558 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13559 }, 13560 outputs: []outputInfo{ 13561 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13562 }, 13563 }, 13564 }, 13565 { 13566 name: "ADDD", 13567 argLen: 2, 13568 commutative: true, 13569 asm: mips.AADDD, 13570 reg: regInfo{ 13571 inputs: []inputInfo{ 13572 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13573 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13574 }, 13575 outputs: []outputInfo{ 13576 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13577 }, 13578 }, 13579 }, 13580 { 13581 name: "SUBF", 13582 argLen: 2, 13583 asm: mips.ASUBF, 13584 reg: regInfo{ 13585 inputs: []inputInfo{ 13586 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13587 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13588 }, 13589 outputs: []outputInfo{ 13590 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13591 }, 13592 }, 13593 }, 13594 { 13595 name: "SUBD", 13596 argLen: 2, 13597 asm: mips.ASUBD, 13598 reg: regInfo{ 13599 inputs: []inputInfo{ 13600 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13601 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13602 }, 13603 outputs: []outputInfo{ 13604 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13605 }, 13606 }, 13607 }, 13608 { 13609 name: "MULF", 13610 argLen: 2, 13611 commutative: true, 13612 asm: mips.AMULF, 13613 reg: regInfo{ 13614 inputs: []inputInfo{ 13615 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13616 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13617 }, 13618 outputs: []outputInfo{ 13619 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13620 }, 13621 }, 13622 }, 13623 { 13624 name: "MULD", 13625 argLen: 2, 13626 commutative: true, 13627 asm: mips.AMULD, 13628 reg: regInfo{ 13629 inputs: []inputInfo{ 13630 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13631 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13632 }, 13633 outputs: []outputInfo{ 13634 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13635 }, 13636 }, 13637 }, 13638 { 13639 name: "DIVF", 13640 argLen: 2, 13641 asm: mips.ADIVF, 13642 reg: regInfo{ 13643 inputs: []inputInfo{ 13644 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13645 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13646 }, 13647 outputs: []outputInfo{ 13648 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13649 }, 13650 }, 13651 }, 13652 { 13653 name: "DIVD", 13654 argLen: 2, 13655 asm: mips.ADIVD, 13656 reg: regInfo{ 13657 inputs: []inputInfo{ 13658 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13659 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13660 }, 13661 outputs: []outputInfo{ 13662 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13663 }, 13664 }, 13665 }, 13666 { 13667 name: "AND", 13668 argLen: 2, 13669 commutative: true, 13670 asm: mips.AAND, 13671 reg: regInfo{ 13672 inputs: []inputInfo{ 13673 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13674 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13675 }, 13676 outputs: []outputInfo{ 13677 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13678 }, 13679 }, 13680 }, 13681 { 13682 name: "ANDconst", 13683 auxType: auxInt32, 13684 argLen: 1, 13685 asm: mips.AAND, 13686 reg: regInfo{ 13687 inputs: []inputInfo{ 13688 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13689 }, 13690 outputs: []outputInfo{ 13691 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13692 }, 13693 }, 13694 }, 13695 { 13696 name: "OR", 13697 argLen: 2, 13698 commutative: true, 13699 asm: mips.AOR, 13700 reg: regInfo{ 13701 inputs: []inputInfo{ 13702 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13703 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13704 }, 13705 outputs: []outputInfo{ 13706 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13707 }, 13708 }, 13709 }, 13710 { 13711 name: "ORconst", 13712 auxType: auxInt32, 13713 argLen: 1, 13714 asm: mips.AOR, 13715 reg: regInfo{ 13716 inputs: []inputInfo{ 13717 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13718 }, 13719 outputs: []outputInfo{ 13720 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13721 }, 13722 }, 13723 }, 13724 { 13725 name: "XOR", 13726 argLen: 2, 13727 commutative: true, 13728 asm: mips.AXOR, 13729 reg: regInfo{ 13730 inputs: []inputInfo{ 13731 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13732 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13733 }, 13734 outputs: []outputInfo{ 13735 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13736 }, 13737 }, 13738 }, 13739 { 13740 name: "XORconst", 13741 auxType: auxInt32, 13742 argLen: 1, 13743 asm: mips.AXOR, 13744 reg: regInfo{ 13745 inputs: []inputInfo{ 13746 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13747 }, 13748 outputs: []outputInfo{ 13749 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13750 }, 13751 }, 13752 }, 13753 { 13754 name: "NOR", 13755 argLen: 2, 13756 commutative: true, 13757 asm: mips.ANOR, 13758 reg: regInfo{ 13759 inputs: []inputInfo{ 13760 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13761 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13762 }, 13763 outputs: []outputInfo{ 13764 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13765 }, 13766 }, 13767 }, 13768 { 13769 name: "NORconst", 13770 auxType: auxInt32, 13771 argLen: 1, 13772 asm: mips.ANOR, 13773 reg: regInfo{ 13774 inputs: []inputInfo{ 13775 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13776 }, 13777 outputs: []outputInfo{ 13778 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13779 }, 13780 }, 13781 }, 13782 { 13783 name: "NEG", 13784 argLen: 1, 13785 reg: regInfo{ 13786 inputs: []inputInfo{ 13787 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13788 }, 13789 outputs: []outputInfo{ 13790 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13791 }, 13792 }, 13793 }, 13794 { 13795 name: "NEGF", 13796 argLen: 1, 13797 asm: mips.ANEGF, 13798 reg: regInfo{ 13799 inputs: []inputInfo{ 13800 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13801 }, 13802 outputs: []outputInfo{ 13803 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13804 }, 13805 }, 13806 }, 13807 { 13808 name: "NEGD", 13809 argLen: 1, 13810 asm: mips.ANEGD, 13811 reg: regInfo{ 13812 inputs: []inputInfo{ 13813 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13814 }, 13815 outputs: []outputInfo{ 13816 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13817 }, 13818 }, 13819 }, 13820 { 13821 name: "SQRTD", 13822 argLen: 1, 13823 asm: mips.ASQRTD, 13824 reg: regInfo{ 13825 inputs: []inputInfo{ 13826 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13827 }, 13828 outputs: []outputInfo{ 13829 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13830 }, 13831 }, 13832 }, 13833 { 13834 name: "SLL", 13835 argLen: 2, 13836 asm: mips.ASLL, 13837 reg: regInfo{ 13838 inputs: []inputInfo{ 13839 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13840 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13841 }, 13842 outputs: []outputInfo{ 13843 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13844 }, 13845 }, 13846 }, 13847 { 13848 name: "SLLconst", 13849 auxType: auxInt32, 13850 argLen: 1, 13851 asm: mips.ASLL, 13852 reg: regInfo{ 13853 inputs: []inputInfo{ 13854 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13855 }, 13856 outputs: []outputInfo{ 13857 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13858 }, 13859 }, 13860 }, 13861 { 13862 name: "SRL", 13863 argLen: 2, 13864 asm: mips.ASRL, 13865 reg: regInfo{ 13866 inputs: []inputInfo{ 13867 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13868 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13869 }, 13870 outputs: []outputInfo{ 13871 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13872 }, 13873 }, 13874 }, 13875 { 13876 name: "SRLconst", 13877 auxType: auxInt32, 13878 argLen: 1, 13879 asm: mips.ASRL, 13880 reg: regInfo{ 13881 inputs: []inputInfo{ 13882 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13883 }, 13884 outputs: []outputInfo{ 13885 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13886 }, 13887 }, 13888 }, 13889 { 13890 name: "SRA", 13891 argLen: 2, 13892 asm: mips.ASRA, 13893 reg: regInfo{ 13894 inputs: []inputInfo{ 13895 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13896 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13897 }, 13898 outputs: []outputInfo{ 13899 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13900 }, 13901 }, 13902 }, 13903 { 13904 name: "SRAconst", 13905 auxType: auxInt32, 13906 argLen: 1, 13907 asm: mips.ASRA, 13908 reg: regInfo{ 13909 inputs: []inputInfo{ 13910 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13911 }, 13912 outputs: []outputInfo{ 13913 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13914 }, 13915 }, 13916 }, 13917 { 13918 name: "CLZ", 13919 argLen: 1, 13920 asm: mips.ACLZ, 13921 reg: regInfo{ 13922 inputs: []inputInfo{ 13923 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13924 }, 13925 outputs: []outputInfo{ 13926 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13927 }, 13928 }, 13929 }, 13930 { 13931 name: "SGT", 13932 argLen: 2, 13933 asm: mips.ASGT, 13934 reg: regInfo{ 13935 inputs: []inputInfo{ 13936 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13937 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13938 }, 13939 outputs: []outputInfo{ 13940 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13941 }, 13942 }, 13943 }, 13944 { 13945 name: "SGTconst", 13946 auxType: auxInt32, 13947 argLen: 1, 13948 asm: mips.ASGT, 13949 reg: regInfo{ 13950 inputs: []inputInfo{ 13951 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13952 }, 13953 outputs: []outputInfo{ 13954 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13955 }, 13956 }, 13957 }, 13958 { 13959 name: "SGTzero", 13960 argLen: 1, 13961 asm: mips.ASGT, 13962 reg: regInfo{ 13963 inputs: []inputInfo{ 13964 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13965 }, 13966 outputs: []outputInfo{ 13967 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13968 }, 13969 }, 13970 }, 13971 { 13972 name: "SGTU", 13973 argLen: 2, 13974 asm: mips.ASGTU, 13975 reg: regInfo{ 13976 inputs: []inputInfo{ 13977 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13978 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13979 }, 13980 outputs: []outputInfo{ 13981 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13982 }, 13983 }, 13984 }, 13985 { 13986 name: "SGTUconst", 13987 auxType: auxInt32, 13988 argLen: 1, 13989 asm: mips.ASGTU, 13990 reg: regInfo{ 13991 inputs: []inputInfo{ 13992 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13993 }, 13994 outputs: []outputInfo{ 13995 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13996 }, 13997 }, 13998 }, 13999 { 14000 name: "SGTUzero", 14001 argLen: 1, 14002 asm: mips.ASGTU, 14003 reg: regInfo{ 14004 inputs: []inputInfo{ 14005 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14006 }, 14007 outputs: []outputInfo{ 14008 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14009 }, 14010 }, 14011 }, 14012 { 14013 name: "CMPEQF", 14014 argLen: 2, 14015 asm: mips.ACMPEQF, 14016 reg: regInfo{ 14017 inputs: []inputInfo{ 14018 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14019 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14020 }, 14021 }, 14022 }, 14023 { 14024 name: "CMPEQD", 14025 argLen: 2, 14026 asm: mips.ACMPEQD, 14027 reg: regInfo{ 14028 inputs: []inputInfo{ 14029 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14030 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14031 }, 14032 }, 14033 }, 14034 { 14035 name: "CMPGEF", 14036 argLen: 2, 14037 asm: mips.ACMPGEF, 14038 reg: regInfo{ 14039 inputs: []inputInfo{ 14040 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14041 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14042 }, 14043 }, 14044 }, 14045 { 14046 name: "CMPGED", 14047 argLen: 2, 14048 asm: mips.ACMPGED, 14049 reg: regInfo{ 14050 inputs: []inputInfo{ 14051 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14052 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14053 }, 14054 }, 14055 }, 14056 { 14057 name: "CMPGTF", 14058 argLen: 2, 14059 asm: mips.ACMPGTF, 14060 reg: regInfo{ 14061 inputs: []inputInfo{ 14062 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14063 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14064 }, 14065 }, 14066 }, 14067 { 14068 name: "CMPGTD", 14069 argLen: 2, 14070 asm: mips.ACMPGTD, 14071 reg: regInfo{ 14072 inputs: []inputInfo{ 14073 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14074 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14075 }, 14076 }, 14077 }, 14078 { 14079 name: "MOVWconst", 14080 auxType: auxInt32, 14081 argLen: 0, 14082 rematerializeable: true, 14083 asm: mips.AMOVW, 14084 reg: regInfo{ 14085 outputs: []outputInfo{ 14086 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14087 }, 14088 }, 14089 }, 14090 { 14091 name: "MOVFconst", 14092 auxType: auxFloat32, 14093 argLen: 0, 14094 rematerializeable: true, 14095 asm: mips.AMOVF, 14096 reg: regInfo{ 14097 outputs: []outputInfo{ 14098 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14099 }, 14100 }, 14101 }, 14102 { 14103 name: "MOVDconst", 14104 auxType: auxFloat64, 14105 argLen: 0, 14106 rematerializeable: true, 14107 asm: mips.AMOVD, 14108 reg: regInfo{ 14109 outputs: []outputInfo{ 14110 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14111 }, 14112 }, 14113 }, 14114 { 14115 name: "MOVWaddr", 14116 auxType: auxSymOff, 14117 argLen: 1, 14118 rematerializeable: true, 14119 symEffect: SymAddr, 14120 asm: mips.AMOVW, 14121 reg: regInfo{ 14122 inputs: []inputInfo{ 14123 {0, 140737555464192}, // SP SB 14124 }, 14125 outputs: []outputInfo{ 14126 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14127 }, 14128 }, 14129 }, 14130 { 14131 name: "MOVBload", 14132 auxType: auxSymOff, 14133 argLen: 2, 14134 faultOnNilArg0: true, 14135 symEffect: SymRead, 14136 asm: mips.AMOVB, 14137 reg: regInfo{ 14138 inputs: []inputInfo{ 14139 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14140 }, 14141 outputs: []outputInfo{ 14142 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14143 }, 14144 }, 14145 }, 14146 { 14147 name: "MOVBUload", 14148 auxType: auxSymOff, 14149 argLen: 2, 14150 faultOnNilArg0: true, 14151 symEffect: SymRead, 14152 asm: mips.AMOVBU, 14153 reg: regInfo{ 14154 inputs: []inputInfo{ 14155 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14156 }, 14157 outputs: []outputInfo{ 14158 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14159 }, 14160 }, 14161 }, 14162 { 14163 name: "MOVHload", 14164 auxType: auxSymOff, 14165 argLen: 2, 14166 faultOnNilArg0: true, 14167 symEffect: SymRead, 14168 asm: mips.AMOVH, 14169 reg: regInfo{ 14170 inputs: []inputInfo{ 14171 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14172 }, 14173 outputs: []outputInfo{ 14174 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14175 }, 14176 }, 14177 }, 14178 { 14179 name: "MOVHUload", 14180 auxType: auxSymOff, 14181 argLen: 2, 14182 faultOnNilArg0: true, 14183 symEffect: SymRead, 14184 asm: mips.AMOVHU, 14185 reg: regInfo{ 14186 inputs: []inputInfo{ 14187 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14188 }, 14189 outputs: []outputInfo{ 14190 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14191 }, 14192 }, 14193 }, 14194 { 14195 name: "MOVWload", 14196 auxType: auxSymOff, 14197 argLen: 2, 14198 faultOnNilArg0: true, 14199 symEffect: SymRead, 14200 asm: mips.AMOVW, 14201 reg: regInfo{ 14202 inputs: []inputInfo{ 14203 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14204 }, 14205 outputs: []outputInfo{ 14206 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14207 }, 14208 }, 14209 }, 14210 { 14211 name: "MOVFload", 14212 auxType: auxSymOff, 14213 argLen: 2, 14214 faultOnNilArg0: true, 14215 symEffect: SymRead, 14216 asm: mips.AMOVF, 14217 reg: regInfo{ 14218 inputs: []inputInfo{ 14219 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14220 }, 14221 outputs: []outputInfo{ 14222 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14223 }, 14224 }, 14225 }, 14226 { 14227 name: "MOVDload", 14228 auxType: auxSymOff, 14229 argLen: 2, 14230 faultOnNilArg0: true, 14231 symEffect: SymRead, 14232 asm: mips.AMOVD, 14233 reg: regInfo{ 14234 inputs: []inputInfo{ 14235 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14236 }, 14237 outputs: []outputInfo{ 14238 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14239 }, 14240 }, 14241 }, 14242 { 14243 name: "MOVBstore", 14244 auxType: auxSymOff, 14245 argLen: 3, 14246 faultOnNilArg0: true, 14247 symEffect: SymWrite, 14248 asm: mips.AMOVB, 14249 reg: regInfo{ 14250 inputs: []inputInfo{ 14251 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14252 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14253 }, 14254 }, 14255 }, 14256 { 14257 name: "MOVHstore", 14258 auxType: auxSymOff, 14259 argLen: 3, 14260 faultOnNilArg0: true, 14261 symEffect: SymWrite, 14262 asm: mips.AMOVH, 14263 reg: regInfo{ 14264 inputs: []inputInfo{ 14265 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14266 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14267 }, 14268 }, 14269 }, 14270 { 14271 name: "MOVWstore", 14272 auxType: auxSymOff, 14273 argLen: 3, 14274 faultOnNilArg0: true, 14275 symEffect: SymWrite, 14276 asm: mips.AMOVW, 14277 reg: regInfo{ 14278 inputs: []inputInfo{ 14279 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14280 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14281 }, 14282 }, 14283 }, 14284 { 14285 name: "MOVFstore", 14286 auxType: auxSymOff, 14287 argLen: 3, 14288 faultOnNilArg0: true, 14289 symEffect: SymWrite, 14290 asm: mips.AMOVF, 14291 reg: regInfo{ 14292 inputs: []inputInfo{ 14293 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14294 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14295 }, 14296 }, 14297 }, 14298 { 14299 name: "MOVDstore", 14300 auxType: auxSymOff, 14301 argLen: 3, 14302 faultOnNilArg0: true, 14303 symEffect: SymWrite, 14304 asm: mips.AMOVD, 14305 reg: regInfo{ 14306 inputs: []inputInfo{ 14307 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14308 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14309 }, 14310 }, 14311 }, 14312 { 14313 name: "MOVBstorezero", 14314 auxType: auxSymOff, 14315 argLen: 2, 14316 faultOnNilArg0: true, 14317 symEffect: SymWrite, 14318 asm: mips.AMOVB, 14319 reg: regInfo{ 14320 inputs: []inputInfo{ 14321 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14322 }, 14323 }, 14324 }, 14325 { 14326 name: "MOVHstorezero", 14327 auxType: auxSymOff, 14328 argLen: 2, 14329 faultOnNilArg0: true, 14330 symEffect: SymWrite, 14331 asm: mips.AMOVH, 14332 reg: regInfo{ 14333 inputs: []inputInfo{ 14334 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14335 }, 14336 }, 14337 }, 14338 { 14339 name: "MOVWstorezero", 14340 auxType: auxSymOff, 14341 argLen: 2, 14342 faultOnNilArg0: true, 14343 symEffect: SymWrite, 14344 asm: mips.AMOVW, 14345 reg: regInfo{ 14346 inputs: []inputInfo{ 14347 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14348 }, 14349 }, 14350 }, 14351 { 14352 name: "MOVBreg", 14353 argLen: 1, 14354 asm: mips.AMOVB, 14355 reg: regInfo{ 14356 inputs: []inputInfo{ 14357 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14358 }, 14359 outputs: []outputInfo{ 14360 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14361 }, 14362 }, 14363 }, 14364 { 14365 name: "MOVBUreg", 14366 argLen: 1, 14367 asm: mips.AMOVBU, 14368 reg: regInfo{ 14369 inputs: []inputInfo{ 14370 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14371 }, 14372 outputs: []outputInfo{ 14373 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14374 }, 14375 }, 14376 }, 14377 { 14378 name: "MOVHreg", 14379 argLen: 1, 14380 asm: mips.AMOVH, 14381 reg: regInfo{ 14382 inputs: []inputInfo{ 14383 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14384 }, 14385 outputs: []outputInfo{ 14386 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14387 }, 14388 }, 14389 }, 14390 { 14391 name: "MOVHUreg", 14392 argLen: 1, 14393 asm: mips.AMOVHU, 14394 reg: regInfo{ 14395 inputs: []inputInfo{ 14396 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14397 }, 14398 outputs: []outputInfo{ 14399 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14400 }, 14401 }, 14402 }, 14403 { 14404 name: "MOVWreg", 14405 argLen: 1, 14406 asm: mips.AMOVW, 14407 reg: regInfo{ 14408 inputs: []inputInfo{ 14409 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14410 }, 14411 outputs: []outputInfo{ 14412 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14413 }, 14414 }, 14415 }, 14416 { 14417 name: "MOVWnop", 14418 argLen: 1, 14419 resultInArg0: true, 14420 reg: regInfo{ 14421 inputs: []inputInfo{ 14422 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14423 }, 14424 outputs: []outputInfo{ 14425 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14426 }, 14427 }, 14428 }, 14429 { 14430 name: "CMOVZ", 14431 argLen: 3, 14432 resultInArg0: true, 14433 asm: mips.ACMOVZ, 14434 reg: regInfo{ 14435 inputs: []inputInfo{ 14436 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14437 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14438 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14439 }, 14440 outputs: []outputInfo{ 14441 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14442 }, 14443 }, 14444 }, 14445 { 14446 name: "CMOVZzero", 14447 argLen: 2, 14448 resultInArg0: true, 14449 asm: mips.ACMOVZ, 14450 reg: regInfo{ 14451 inputs: []inputInfo{ 14452 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14453 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14454 }, 14455 outputs: []outputInfo{ 14456 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14457 }, 14458 }, 14459 }, 14460 { 14461 name: "MOVWF", 14462 argLen: 1, 14463 asm: mips.AMOVWF, 14464 reg: regInfo{ 14465 inputs: []inputInfo{ 14466 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14467 }, 14468 outputs: []outputInfo{ 14469 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14470 }, 14471 }, 14472 }, 14473 { 14474 name: "MOVWD", 14475 argLen: 1, 14476 asm: mips.AMOVWD, 14477 reg: regInfo{ 14478 inputs: []inputInfo{ 14479 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14480 }, 14481 outputs: []outputInfo{ 14482 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14483 }, 14484 }, 14485 }, 14486 { 14487 name: "TRUNCFW", 14488 argLen: 1, 14489 asm: mips.ATRUNCFW, 14490 reg: regInfo{ 14491 inputs: []inputInfo{ 14492 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14493 }, 14494 outputs: []outputInfo{ 14495 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14496 }, 14497 }, 14498 }, 14499 { 14500 name: "TRUNCDW", 14501 argLen: 1, 14502 asm: mips.ATRUNCDW, 14503 reg: regInfo{ 14504 inputs: []inputInfo{ 14505 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14506 }, 14507 outputs: []outputInfo{ 14508 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14509 }, 14510 }, 14511 }, 14512 { 14513 name: "MOVFD", 14514 argLen: 1, 14515 asm: mips.AMOVFD, 14516 reg: regInfo{ 14517 inputs: []inputInfo{ 14518 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14519 }, 14520 outputs: []outputInfo{ 14521 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14522 }, 14523 }, 14524 }, 14525 { 14526 name: "MOVDF", 14527 argLen: 1, 14528 asm: mips.AMOVDF, 14529 reg: regInfo{ 14530 inputs: []inputInfo{ 14531 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14532 }, 14533 outputs: []outputInfo{ 14534 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14535 }, 14536 }, 14537 }, 14538 { 14539 name: "CALLstatic", 14540 auxType: auxSymOff, 14541 argLen: 1, 14542 clobberFlags: true, 14543 call: true, 14544 symEffect: SymNone, 14545 reg: regInfo{ 14546 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14547 }, 14548 }, 14549 { 14550 name: "CALLclosure", 14551 auxType: auxInt64, 14552 argLen: 3, 14553 clobberFlags: true, 14554 call: true, 14555 reg: regInfo{ 14556 inputs: []inputInfo{ 14557 {1, 4194304}, // R22 14558 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 14559 }, 14560 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14561 }, 14562 }, 14563 { 14564 name: "CALLinter", 14565 auxType: auxInt64, 14566 argLen: 2, 14567 clobberFlags: true, 14568 call: true, 14569 reg: regInfo{ 14570 inputs: []inputInfo{ 14571 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14572 }, 14573 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 14574 }, 14575 }, 14576 { 14577 name: "LoweredAtomicLoad", 14578 argLen: 2, 14579 faultOnNilArg0: true, 14580 reg: regInfo{ 14581 inputs: []inputInfo{ 14582 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14583 }, 14584 outputs: []outputInfo{ 14585 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14586 }, 14587 }, 14588 }, 14589 { 14590 name: "LoweredAtomicStore", 14591 argLen: 3, 14592 faultOnNilArg0: true, 14593 hasSideEffects: true, 14594 reg: regInfo{ 14595 inputs: []inputInfo{ 14596 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14597 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14598 }, 14599 }, 14600 }, 14601 { 14602 name: "LoweredAtomicStorezero", 14603 argLen: 2, 14604 faultOnNilArg0: true, 14605 hasSideEffects: true, 14606 reg: regInfo{ 14607 inputs: []inputInfo{ 14608 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14609 }, 14610 }, 14611 }, 14612 { 14613 name: "LoweredAtomicExchange", 14614 argLen: 3, 14615 resultNotInArgs: true, 14616 faultOnNilArg0: true, 14617 hasSideEffects: true, 14618 reg: regInfo{ 14619 inputs: []inputInfo{ 14620 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14621 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14622 }, 14623 outputs: []outputInfo{ 14624 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14625 }, 14626 }, 14627 }, 14628 { 14629 name: "LoweredAtomicAdd", 14630 argLen: 3, 14631 resultNotInArgs: true, 14632 faultOnNilArg0: true, 14633 hasSideEffects: true, 14634 reg: regInfo{ 14635 inputs: []inputInfo{ 14636 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14637 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14638 }, 14639 outputs: []outputInfo{ 14640 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14641 }, 14642 }, 14643 }, 14644 { 14645 name: "LoweredAtomicAddconst", 14646 auxType: auxInt32, 14647 argLen: 2, 14648 resultNotInArgs: true, 14649 faultOnNilArg0: true, 14650 hasSideEffects: true, 14651 reg: regInfo{ 14652 inputs: []inputInfo{ 14653 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14654 }, 14655 outputs: []outputInfo{ 14656 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14657 }, 14658 }, 14659 }, 14660 { 14661 name: "LoweredAtomicCas", 14662 argLen: 4, 14663 resultNotInArgs: true, 14664 faultOnNilArg0: true, 14665 hasSideEffects: true, 14666 reg: regInfo{ 14667 inputs: []inputInfo{ 14668 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14669 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14670 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14671 }, 14672 outputs: []outputInfo{ 14673 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14674 }, 14675 }, 14676 }, 14677 { 14678 name: "LoweredAtomicAnd", 14679 argLen: 3, 14680 faultOnNilArg0: true, 14681 hasSideEffects: true, 14682 asm: mips.AAND, 14683 reg: regInfo{ 14684 inputs: []inputInfo{ 14685 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14686 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14687 }, 14688 }, 14689 }, 14690 { 14691 name: "LoweredAtomicOr", 14692 argLen: 3, 14693 faultOnNilArg0: true, 14694 hasSideEffects: true, 14695 asm: mips.AOR, 14696 reg: regInfo{ 14697 inputs: []inputInfo{ 14698 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14699 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14700 }, 14701 }, 14702 }, 14703 { 14704 name: "LoweredZero", 14705 auxType: auxInt32, 14706 argLen: 3, 14707 faultOnNilArg0: true, 14708 reg: regInfo{ 14709 inputs: []inputInfo{ 14710 {0, 2}, // R1 14711 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14712 }, 14713 clobbers: 2, // R1 14714 }, 14715 }, 14716 { 14717 name: "LoweredMove", 14718 auxType: auxInt32, 14719 argLen: 4, 14720 faultOnNilArg0: true, 14721 faultOnNilArg1: true, 14722 reg: regInfo{ 14723 inputs: []inputInfo{ 14724 {0, 4}, // R2 14725 {1, 2}, // R1 14726 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14727 }, 14728 clobbers: 6, // R1 R2 14729 }, 14730 }, 14731 { 14732 name: "LoweredNilCheck", 14733 argLen: 2, 14734 nilCheck: true, 14735 faultOnNilArg0: true, 14736 reg: regInfo{ 14737 inputs: []inputInfo{ 14738 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14739 }, 14740 }, 14741 }, 14742 { 14743 name: "FPFlagTrue", 14744 argLen: 1, 14745 reg: regInfo{ 14746 outputs: []outputInfo{ 14747 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14748 }, 14749 }, 14750 }, 14751 { 14752 name: "FPFlagFalse", 14753 argLen: 1, 14754 reg: regInfo{ 14755 outputs: []outputInfo{ 14756 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14757 }, 14758 }, 14759 }, 14760 { 14761 name: "LoweredGetClosurePtr", 14762 argLen: 0, 14763 reg: regInfo{ 14764 outputs: []outputInfo{ 14765 {0, 4194304}, // R22 14766 }, 14767 }, 14768 }, 14769 { 14770 name: "MOVWconvert", 14771 argLen: 2, 14772 asm: mips.AMOVW, 14773 reg: regInfo{ 14774 inputs: []inputInfo{ 14775 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14776 }, 14777 outputs: []outputInfo{ 14778 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14779 }, 14780 }, 14781 }, 14782 14783 { 14784 name: "ADDV", 14785 argLen: 2, 14786 commutative: true, 14787 asm: mips.AADDVU, 14788 reg: regInfo{ 14789 inputs: []inputInfo{ 14790 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14791 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14792 }, 14793 outputs: []outputInfo{ 14794 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14795 }, 14796 }, 14797 }, 14798 { 14799 name: "ADDVconst", 14800 auxType: auxInt64, 14801 argLen: 1, 14802 asm: mips.AADDVU, 14803 reg: regInfo{ 14804 inputs: []inputInfo{ 14805 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 14806 }, 14807 outputs: []outputInfo{ 14808 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14809 }, 14810 }, 14811 }, 14812 { 14813 name: "SUBV", 14814 argLen: 2, 14815 asm: mips.ASUBVU, 14816 reg: regInfo{ 14817 inputs: []inputInfo{ 14818 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14819 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14820 }, 14821 outputs: []outputInfo{ 14822 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14823 }, 14824 }, 14825 }, 14826 { 14827 name: "SUBVconst", 14828 auxType: auxInt64, 14829 argLen: 1, 14830 asm: mips.ASUBVU, 14831 reg: regInfo{ 14832 inputs: []inputInfo{ 14833 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14834 }, 14835 outputs: []outputInfo{ 14836 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14837 }, 14838 }, 14839 }, 14840 { 14841 name: "MULV", 14842 argLen: 2, 14843 commutative: true, 14844 asm: mips.AMULV, 14845 reg: regInfo{ 14846 inputs: []inputInfo{ 14847 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14848 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14849 }, 14850 outputs: []outputInfo{ 14851 {0, 1152921504606846976}, // HI 14852 {1, 2305843009213693952}, // LO 14853 }, 14854 }, 14855 }, 14856 { 14857 name: "MULVU", 14858 argLen: 2, 14859 commutative: true, 14860 asm: mips.AMULVU, 14861 reg: regInfo{ 14862 inputs: []inputInfo{ 14863 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14864 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14865 }, 14866 outputs: []outputInfo{ 14867 {0, 1152921504606846976}, // HI 14868 {1, 2305843009213693952}, // LO 14869 }, 14870 }, 14871 }, 14872 { 14873 name: "DIVV", 14874 argLen: 2, 14875 asm: mips.ADIVV, 14876 reg: regInfo{ 14877 inputs: []inputInfo{ 14878 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14879 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14880 }, 14881 outputs: []outputInfo{ 14882 {0, 1152921504606846976}, // HI 14883 {1, 2305843009213693952}, // LO 14884 }, 14885 }, 14886 }, 14887 { 14888 name: "DIVVU", 14889 argLen: 2, 14890 asm: mips.ADIVVU, 14891 reg: regInfo{ 14892 inputs: []inputInfo{ 14893 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14894 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14895 }, 14896 outputs: []outputInfo{ 14897 {0, 1152921504606846976}, // HI 14898 {1, 2305843009213693952}, // LO 14899 }, 14900 }, 14901 }, 14902 { 14903 name: "ADDF", 14904 argLen: 2, 14905 commutative: true, 14906 asm: mips.AADDF, 14907 reg: regInfo{ 14908 inputs: []inputInfo{ 14909 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14910 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14911 }, 14912 outputs: []outputInfo{ 14913 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14914 }, 14915 }, 14916 }, 14917 { 14918 name: "ADDD", 14919 argLen: 2, 14920 commutative: true, 14921 asm: mips.AADDD, 14922 reg: regInfo{ 14923 inputs: []inputInfo{ 14924 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14925 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14926 }, 14927 outputs: []outputInfo{ 14928 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14929 }, 14930 }, 14931 }, 14932 { 14933 name: "SUBF", 14934 argLen: 2, 14935 asm: mips.ASUBF, 14936 reg: regInfo{ 14937 inputs: []inputInfo{ 14938 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14939 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14940 }, 14941 outputs: []outputInfo{ 14942 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14943 }, 14944 }, 14945 }, 14946 { 14947 name: "SUBD", 14948 argLen: 2, 14949 asm: mips.ASUBD, 14950 reg: regInfo{ 14951 inputs: []inputInfo{ 14952 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14953 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14954 }, 14955 outputs: []outputInfo{ 14956 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14957 }, 14958 }, 14959 }, 14960 { 14961 name: "MULF", 14962 argLen: 2, 14963 commutative: true, 14964 asm: mips.AMULF, 14965 reg: regInfo{ 14966 inputs: []inputInfo{ 14967 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14968 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14969 }, 14970 outputs: []outputInfo{ 14971 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14972 }, 14973 }, 14974 }, 14975 { 14976 name: "MULD", 14977 argLen: 2, 14978 commutative: true, 14979 asm: mips.AMULD, 14980 reg: regInfo{ 14981 inputs: []inputInfo{ 14982 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14983 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14984 }, 14985 outputs: []outputInfo{ 14986 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14987 }, 14988 }, 14989 }, 14990 { 14991 name: "DIVF", 14992 argLen: 2, 14993 asm: mips.ADIVF, 14994 reg: regInfo{ 14995 inputs: []inputInfo{ 14996 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14997 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14998 }, 14999 outputs: []outputInfo{ 15000 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15001 }, 15002 }, 15003 }, 15004 { 15005 name: "DIVD", 15006 argLen: 2, 15007 asm: mips.ADIVD, 15008 reg: regInfo{ 15009 inputs: []inputInfo{ 15010 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15011 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15012 }, 15013 outputs: []outputInfo{ 15014 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15015 }, 15016 }, 15017 }, 15018 { 15019 name: "AND", 15020 argLen: 2, 15021 commutative: true, 15022 asm: mips.AAND, 15023 reg: regInfo{ 15024 inputs: []inputInfo{ 15025 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15026 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15027 }, 15028 outputs: []outputInfo{ 15029 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15030 }, 15031 }, 15032 }, 15033 { 15034 name: "ANDconst", 15035 auxType: auxInt64, 15036 argLen: 1, 15037 asm: mips.AAND, 15038 reg: regInfo{ 15039 inputs: []inputInfo{ 15040 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15041 }, 15042 outputs: []outputInfo{ 15043 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15044 }, 15045 }, 15046 }, 15047 { 15048 name: "OR", 15049 argLen: 2, 15050 commutative: true, 15051 asm: mips.AOR, 15052 reg: regInfo{ 15053 inputs: []inputInfo{ 15054 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15055 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15056 }, 15057 outputs: []outputInfo{ 15058 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15059 }, 15060 }, 15061 }, 15062 { 15063 name: "ORconst", 15064 auxType: auxInt64, 15065 argLen: 1, 15066 asm: mips.AOR, 15067 reg: regInfo{ 15068 inputs: []inputInfo{ 15069 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15070 }, 15071 outputs: []outputInfo{ 15072 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15073 }, 15074 }, 15075 }, 15076 { 15077 name: "XOR", 15078 argLen: 2, 15079 commutative: true, 15080 asm: mips.AXOR, 15081 reg: regInfo{ 15082 inputs: []inputInfo{ 15083 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15084 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15085 }, 15086 outputs: []outputInfo{ 15087 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15088 }, 15089 }, 15090 }, 15091 { 15092 name: "XORconst", 15093 auxType: auxInt64, 15094 argLen: 1, 15095 asm: mips.AXOR, 15096 reg: regInfo{ 15097 inputs: []inputInfo{ 15098 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15099 }, 15100 outputs: []outputInfo{ 15101 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15102 }, 15103 }, 15104 }, 15105 { 15106 name: "NOR", 15107 argLen: 2, 15108 commutative: true, 15109 asm: mips.ANOR, 15110 reg: regInfo{ 15111 inputs: []inputInfo{ 15112 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15113 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15114 }, 15115 outputs: []outputInfo{ 15116 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15117 }, 15118 }, 15119 }, 15120 { 15121 name: "NORconst", 15122 auxType: auxInt64, 15123 argLen: 1, 15124 asm: mips.ANOR, 15125 reg: regInfo{ 15126 inputs: []inputInfo{ 15127 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15128 }, 15129 outputs: []outputInfo{ 15130 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15131 }, 15132 }, 15133 }, 15134 { 15135 name: "NEGV", 15136 argLen: 1, 15137 reg: regInfo{ 15138 inputs: []inputInfo{ 15139 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15140 }, 15141 outputs: []outputInfo{ 15142 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15143 }, 15144 }, 15145 }, 15146 { 15147 name: "NEGF", 15148 argLen: 1, 15149 asm: mips.ANEGF, 15150 reg: regInfo{ 15151 inputs: []inputInfo{ 15152 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15153 }, 15154 outputs: []outputInfo{ 15155 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15156 }, 15157 }, 15158 }, 15159 { 15160 name: "NEGD", 15161 argLen: 1, 15162 asm: mips.ANEGD, 15163 reg: regInfo{ 15164 inputs: []inputInfo{ 15165 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15166 }, 15167 outputs: []outputInfo{ 15168 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15169 }, 15170 }, 15171 }, 15172 { 15173 name: "SLLV", 15174 argLen: 2, 15175 asm: mips.ASLLV, 15176 reg: regInfo{ 15177 inputs: []inputInfo{ 15178 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15179 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15180 }, 15181 outputs: []outputInfo{ 15182 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15183 }, 15184 }, 15185 }, 15186 { 15187 name: "SLLVconst", 15188 auxType: auxInt64, 15189 argLen: 1, 15190 asm: mips.ASLLV, 15191 reg: regInfo{ 15192 inputs: []inputInfo{ 15193 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15194 }, 15195 outputs: []outputInfo{ 15196 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15197 }, 15198 }, 15199 }, 15200 { 15201 name: "SRLV", 15202 argLen: 2, 15203 asm: mips.ASRLV, 15204 reg: regInfo{ 15205 inputs: []inputInfo{ 15206 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15207 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15208 }, 15209 outputs: []outputInfo{ 15210 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15211 }, 15212 }, 15213 }, 15214 { 15215 name: "SRLVconst", 15216 auxType: auxInt64, 15217 argLen: 1, 15218 asm: mips.ASRLV, 15219 reg: regInfo{ 15220 inputs: []inputInfo{ 15221 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15222 }, 15223 outputs: []outputInfo{ 15224 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15225 }, 15226 }, 15227 }, 15228 { 15229 name: "SRAV", 15230 argLen: 2, 15231 asm: mips.ASRAV, 15232 reg: regInfo{ 15233 inputs: []inputInfo{ 15234 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15235 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15236 }, 15237 outputs: []outputInfo{ 15238 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15239 }, 15240 }, 15241 }, 15242 { 15243 name: "SRAVconst", 15244 auxType: auxInt64, 15245 argLen: 1, 15246 asm: mips.ASRAV, 15247 reg: regInfo{ 15248 inputs: []inputInfo{ 15249 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15250 }, 15251 outputs: []outputInfo{ 15252 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15253 }, 15254 }, 15255 }, 15256 { 15257 name: "SGT", 15258 argLen: 2, 15259 asm: mips.ASGT, 15260 reg: regInfo{ 15261 inputs: []inputInfo{ 15262 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15263 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15264 }, 15265 outputs: []outputInfo{ 15266 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15267 }, 15268 }, 15269 }, 15270 { 15271 name: "SGTconst", 15272 auxType: auxInt64, 15273 argLen: 1, 15274 asm: mips.ASGT, 15275 reg: regInfo{ 15276 inputs: []inputInfo{ 15277 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15278 }, 15279 outputs: []outputInfo{ 15280 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15281 }, 15282 }, 15283 }, 15284 { 15285 name: "SGTU", 15286 argLen: 2, 15287 asm: mips.ASGTU, 15288 reg: regInfo{ 15289 inputs: []inputInfo{ 15290 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15291 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15292 }, 15293 outputs: []outputInfo{ 15294 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15295 }, 15296 }, 15297 }, 15298 { 15299 name: "SGTUconst", 15300 auxType: auxInt64, 15301 argLen: 1, 15302 asm: mips.ASGTU, 15303 reg: regInfo{ 15304 inputs: []inputInfo{ 15305 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15306 }, 15307 outputs: []outputInfo{ 15308 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15309 }, 15310 }, 15311 }, 15312 { 15313 name: "CMPEQF", 15314 argLen: 2, 15315 asm: mips.ACMPEQF, 15316 reg: regInfo{ 15317 inputs: []inputInfo{ 15318 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15319 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15320 }, 15321 }, 15322 }, 15323 { 15324 name: "CMPEQD", 15325 argLen: 2, 15326 asm: mips.ACMPEQD, 15327 reg: regInfo{ 15328 inputs: []inputInfo{ 15329 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15330 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15331 }, 15332 }, 15333 }, 15334 { 15335 name: "CMPGEF", 15336 argLen: 2, 15337 asm: mips.ACMPGEF, 15338 reg: regInfo{ 15339 inputs: []inputInfo{ 15340 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15341 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15342 }, 15343 }, 15344 }, 15345 { 15346 name: "CMPGED", 15347 argLen: 2, 15348 asm: mips.ACMPGED, 15349 reg: regInfo{ 15350 inputs: []inputInfo{ 15351 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15352 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15353 }, 15354 }, 15355 }, 15356 { 15357 name: "CMPGTF", 15358 argLen: 2, 15359 asm: mips.ACMPGTF, 15360 reg: regInfo{ 15361 inputs: []inputInfo{ 15362 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15363 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15364 }, 15365 }, 15366 }, 15367 { 15368 name: "CMPGTD", 15369 argLen: 2, 15370 asm: mips.ACMPGTD, 15371 reg: regInfo{ 15372 inputs: []inputInfo{ 15373 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15374 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15375 }, 15376 }, 15377 }, 15378 { 15379 name: "MOVVconst", 15380 auxType: auxInt64, 15381 argLen: 0, 15382 rematerializeable: true, 15383 asm: mips.AMOVV, 15384 reg: regInfo{ 15385 outputs: []outputInfo{ 15386 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15387 }, 15388 }, 15389 }, 15390 { 15391 name: "MOVFconst", 15392 auxType: auxFloat64, 15393 argLen: 0, 15394 rematerializeable: true, 15395 asm: mips.AMOVF, 15396 reg: regInfo{ 15397 outputs: []outputInfo{ 15398 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15399 }, 15400 }, 15401 }, 15402 { 15403 name: "MOVDconst", 15404 auxType: auxFloat64, 15405 argLen: 0, 15406 rematerializeable: true, 15407 asm: mips.AMOVD, 15408 reg: regInfo{ 15409 outputs: []outputInfo{ 15410 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15411 }, 15412 }, 15413 }, 15414 { 15415 name: "MOVVaddr", 15416 auxType: auxSymOff, 15417 argLen: 1, 15418 rematerializeable: true, 15419 symEffect: SymAddr, 15420 asm: mips.AMOVV, 15421 reg: regInfo{ 15422 inputs: []inputInfo{ 15423 {0, 4611686018460942336}, // SP SB 15424 }, 15425 outputs: []outputInfo{ 15426 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15427 }, 15428 }, 15429 }, 15430 { 15431 name: "MOVBload", 15432 auxType: auxSymOff, 15433 argLen: 2, 15434 faultOnNilArg0: true, 15435 symEffect: SymRead, 15436 asm: mips.AMOVB, 15437 reg: regInfo{ 15438 inputs: []inputInfo{ 15439 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15440 }, 15441 outputs: []outputInfo{ 15442 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15443 }, 15444 }, 15445 }, 15446 { 15447 name: "MOVBUload", 15448 auxType: auxSymOff, 15449 argLen: 2, 15450 faultOnNilArg0: true, 15451 symEffect: SymRead, 15452 asm: mips.AMOVBU, 15453 reg: regInfo{ 15454 inputs: []inputInfo{ 15455 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15456 }, 15457 outputs: []outputInfo{ 15458 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15459 }, 15460 }, 15461 }, 15462 { 15463 name: "MOVHload", 15464 auxType: auxSymOff, 15465 argLen: 2, 15466 faultOnNilArg0: true, 15467 symEffect: SymRead, 15468 asm: mips.AMOVH, 15469 reg: regInfo{ 15470 inputs: []inputInfo{ 15471 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15472 }, 15473 outputs: []outputInfo{ 15474 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15475 }, 15476 }, 15477 }, 15478 { 15479 name: "MOVHUload", 15480 auxType: auxSymOff, 15481 argLen: 2, 15482 faultOnNilArg0: true, 15483 symEffect: SymRead, 15484 asm: mips.AMOVHU, 15485 reg: regInfo{ 15486 inputs: []inputInfo{ 15487 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15488 }, 15489 outputs: []outputInfo{ 15490 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15491 }, 15492 }, 15493 }, 15494 { 15495 name: "MOVWload", 15496 auxType: auxSymOff, 15497 argLen: 2, 15498 faultOnNilArg0: true, 15499 symEffect: SymRead, 15500 asm: mips.AMOVW, 15501 reg: regInfo{ 15502 inputs: []inputInfo{ 15503 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15504 }, 15505 outputs: []outputInfo{ 15506 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15507 }, 15508 }, 15509 }, 15510 { 15511 name: "MOVWUload", 15512 auxType: auxSymOff, 15513 argLen: 2, 15514 faultOnNilArg0: true, 15515 symEffect: SymRead, 15516 asm: mips.AMOVWU, 15517 reg: regInfo{ 15518 inputs: []inputInfo{ 15519 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15520 }, 15521 outputs: []outputInfo{ 15522 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15523 }, 15524 }, 15525 }, 15526 { 15527 name: "MOVVload", 15528 auxType: auxSymOff, 15529 argLen: 2, 15530 faultOnNilArg0: true, 15531 symEffect: SymRead, 15532 asm: mips.AMOVV, 15533 reg: regInfo{ 15534 inputs: []inputInfo{ 15535 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15536 }, 15537 outputs: []outputInfo{ 15538 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15539 }, 15540 }, 15541 }, 15542 { 15543 name: "MOVFload", 15544 auxType: auxSymOff, 15545 argLen: 2, 15546 faultOnNilArg0: true, 15547 symEffect: SymRead, 15548 asm: mips.AMOVF, 15549 reg: regInfo{ 15550 inputs: []inputInfo{ 15551 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15552 }, 15553 outputs: []outputInfo{ 15554 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15555 }, 15556 }, 15557 }, 15558 { 15559 name: "MOVDload", 15560 auxType: auxSymOff, 15561 argLen: 2, 15562 faultOnNilArg0: true, 15563 symEffect: SymRead, 15564 asm: mips.AMOVD, 15565 reg: regInfo{ 15566 inputs: []inputInfo{ 15567 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15568 }, 15569 outputs: []outputInfo{ 15570 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15571 }, 15572 }, 15573 }, 15574 { 15575 name: "MOVBstore", 15576 auxType: auxSymOff, 15577 argLen: 3, 15578 faultOnNilArg0: true, 15579 symEffect: SymWrite, 15580 asm: mips.AMOVB, 15581 reg: regInfo{ 15582 inputs: []inputInfo{ 15583 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15584 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15585 }, 15586 }, 15587 }, 15588 { 15589 name: "MOVHstore", 15590 auxType: auxSymOff, 15591 argLen: 3, 15592 faultOnNilArg0: true, 15593 symEffect: SymWrite, 15594 asm: mips.AMOVH, 15595 reg: regInfo{ 15596 inputs: []inputInfo{ 15597 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15598 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15599 }, 15600 }, 15601 }, 15602 { 15603 name: "MOVWstore", 15604 auxType: auxSymOff, 15605 argLen: 3, 15606 faultOnNilArg0: true, 15607 symEffect: SymWrite, 15608 asm: mips.AMOVW, 15609 reg: regInfo{ 15610 inputs: []inputInfo{ 15611 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15612 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15613 }, 15614 }, 15615 }, 15616 { 15617 name: "MOVVstore", 15618 auxType: auxSymOff, 15619 argLen: 3, 15620 faultOnNilArg0: true, 15621 symEffect: SymWrite, 15622 asm: mips.AMOVV, 15623 reg: regInfo{ 15624 inputs: []inputInfo{ 15625 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15626 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15627 }, 15628 }, 15629 }, 15630 { 15631 name: "MOVFstore", 15632 auxType: auxSymOff, 15633 argLen: 3, 15634 faultOnNilArg0: true, 15635 symEffect: SymWrite, 15636 asm: mips.AMOVF, 15637 reg: regInfo{ 15638 inputs: []inputInfo{ 15639 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15640 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15641 }, 15642 }, 15643 }, 15644 { 15645 name: "MOVDstore", 15646 auxType: auxSymOff, 15647 argLen: 3, 15648 faultOnNilArg0: true, 15649 symEffect: SymWrite, 15650 asm: mips.AMOVD, 15651 reg: regInfo{ 15652 inputs: []inputInfo{ 15653 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15654 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15655 }, 15656 }, 15657 }, 15658 { 15659 name: "MOVBstorezero", 15660 auxType: auxSymOff, 15661 argLen: 2, 15662 faultOnNilArg0: true, 15663 symEffect: SymWrite, 15664 asm: mips.AMOVB, 15665 reg: regInfo{ 15666 inputs: []inputInfo{ 15667 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15668 }, 15669 }, 15670 }, 15671 { 15672 name: "MOVHstorezero", 15673 auxType: auxSymOff, 15674 argLen: 2, 15675 faultOnNilArg0: true, 15676 symEffect: SymWrite, 15677 asm: mips.AMOVH, 15678 reg: regInfo{ 15679 inputs: []inputInfo{ 15680 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15681 }, 15682 }, 15683 }, 15684 { 15685 name: "MOVWstorezero", 15686 auxType: auxSymOff, 15687 argLen: 2, 15688 faultOnNilArg0: true, 15689 symEffect: SymWrite, 15690 asm: mips.AMOVW, 15691 reg: regInfo{ 15692 inputs: []inputInfo{ 15693 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15694 }, 15695 }, 15696 }, 15697 { 15698 name: "MOVVstorezero", 15699 auxType: auxSymOff, 15700 argLen: 2, 15701 faultOnNilArg0: true, 15702 symEffect: SymWrite, 15703 asm: mips.AMOVV, 15704 reg: regInfo{ 15705 inputs: []inputInfo{ 15706 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15707 }, 15708 }, 15709 }, 15710 { 15711 name: "MOVBreg", 15712 argLen: 1, 15713 asm: mips.AMOVB, 15714 reg: regInfo{ 15715 inputs: []inputInfo{ 15716 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15717 }, 15718 outputs: []outputInfo{ 15719 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15720 }, 15721 }, 15722 }, 15723 { 15724 name: "MOVBUreg", 15725 argLen: 1, 15726 asm: mips.AMOVBU, 15727 reg: regInfo{ 15728 inputs: []inputInfo{ 15729 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15730 }, 15731 outputs: []outputInfo{ 15732 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15733 }, 15734 }, 15735 }, 15736 { 15737 name: "MOVHreg", 15738 argLen: 1, 15739 asm: mips.AMOVH, 15740 reg: regInfo{ 15741 inputs: []inputInfo{ 15742 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15743 }, 15744 outputs: []outputInfo{ 15745 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15746 }, 15747 }, 15748 }, 15749 { 15750 name: "MOVHUreg", 15751 argLen: 1, 15752 asm: mips.AMOVHU, 15753 reg: regInfo{ 15754 inputs: []inputInfo{ 15755 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15756 }, 15757 outputs: []outputInfo{ 15758 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15759 }, 15760 }, 15761 }, 15762 { 15763 name: "MOVWreg", 15764 argLen: 1, 15765 asm: mips.AMOVW, 15766 reg: regInfo{ 15767 inputs: []inputInfo{ 15768 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15769 }, 15770 outputs: []outputInfo{ 15771 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15772 }, 15773 }, 15774 }, 15775 { 15776 name: "MOVWUreg", 15777 argLen: 1, 15778 asm: mips.AMOVWU, 15779 reg: regInfo{ 15780 inputs: []inputInfo{ 15781 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15782 }, 15783 outputs: []outputInfo{ 15784 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15785 }, 15786 }, 15787 }, 15788 { 15789 name: "MOVVreg", 15790 argLen: 1, 15791 asm: mips.AMOVV, 15792 reg: regInfo{ 15793 inputs: []inputInfo{ 15794 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15795 }, 15796 outputs: []outputInfo{ 15797 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15798 }, 15799 }, 15800 }, 15801 { 15802 name: "MOVVnop", 15803 argLen: 1, 15804 resultInArg0: true, 15805 reg: regInfo{ 15806 inputs: []inputInfo{ 15807 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15808 }, 15809 outputs: []outputInfo{ 15810 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15811 }, 15812 }, 15813 }, 15814 { 15815 name: "MOVWF", 15816 argLen: 1, 15817 asm: mips.AMOVWF, 15818 reg: regInfo{ 15819 inputs: []inputInfo{ 15820 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15821 }, 15822 outputs: []outputInfo{ 15823 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15824 }, 15825 }, 15826 }, 15827 { 15828 name: "MOVWD", 15829 argLen: 1, 15830 asm: mips.AMOVWD, 15831 reg: regInfo{ 15832 inputs: []inputInfo{ 15833 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15834 }, 15835 outputs: []outputInfo{ 15836 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15837 }, 15838 }, 15839 }, 15840 { 15841 name: "MOVVF", 15842 argLen: 1, 15843 asm: mips.AMOVVF, 15844 reg: regInfo{ 15845 inputs: []inputInfo{ 15846 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15847 }, 15848 outputs: []outputInfo{ 15849 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15850 }, 15851 }, 15852 }, 15853 { 15854 name: "MOVVD", 15855 argLen: 1, 15856 asm: mips.AMOVVD, 15857 reg: regInfo{ 15858 inputs: []inputInfo{ 15859 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15860 }, 15861 outputs: []outputInfo{ 15862 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15863 }, 15864 }, 15865 }, 15866 { 15867 name: "TRUNCFW", 15868 argLen: 1, 15869 asm: mips.ATRUNCFW, 15870 reg: regInfo{ 15871 inputs: []inputInfo{ 15872 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15873 }, 15874 outputs: []outputInfo{ 15875 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15876 }, 15877 }, 15878 }, 15879 { 15880 name: "TRUNCDW", 15881 argLen: 1, 15882 asm: mips.ATRUNCDW, 15883 reg: regInfo{ 15884 inputs: []inputInfo{ 15885 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15886 }, 15887 outputs: []outputInfo{ 15888 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15889 }, 15890 }, 15891 }, 15892 { 15893 name: "TRUNCFV", 15894 argLen: 1, 15895 asm: mips.ATRUNCFV, 15896 reg: regInfo{ 15897 inputs: []inputInfo{ 15898 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15899 }, 15900 outputs: []outputInfo{ 15901 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15902 }, 15903 }, 15904 }, 15905 { 15906 name: "TRUNCDV", 15907 argLen: 1, 15908 asm: mips.ATRUNCDV, 15909 reg: regInfo{ 15910 inputs: []inputInfo{ 15911 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15912 }, 15913 outputs: []outputInfo{ 15914 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15915 }, 15916 }, 15917 }, 15918 { 15919 name: "MOVFD", 15920 argLen: 1, 15921 asm: mips.AMOVFD, 15922 reg: regInfo{ 15923 inputs: []inputInfo{ 15924 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15925 }, 15926 outputs: []outputInfo{ 15927 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15928 }, 15929 }, 15930 }, 15931 { 15932 name: "MOVDF", 15933 argLen: 1, 15934 asm: mips.AMOVDF, 15935 reg: regInfo{ 15936 inputs: []inputInfo{ 15937 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15938 }, 15939 outputs: []outputInfo{ 15940 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15941 }, 15942 }, 15943 }, 15944 { 15945 name: "CALLstatic", 15946 auxType: auxSymOff, 15947 argLen: 1, 15948 clobberFlags: true, 15949 call: true, 15950 symEffect: SymNone, 15951 reg: regInfo{ 15952 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15953 }, 15954 }, 15955 { 15956 name: "CALLclosure", 15957 auxType: auxInt64, 15958 argLen: 3, 15959 clobberFlags: true, 15960 call: true, 15961 reg: regInfo{ 15962 inputs: []inputInfo{ 15963 {1, 4194304}, // R22 15964 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 15965 }, 15966 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15967 }, 15968 }, 15969 { 15970 name: "CALLinter", 15971 auxType: auxInt64, 15972 argLen: 2, 15973 clobberFlags: true, 15974 call: true, 15975 reg: regInfo{ 15976 inputs: []inputInfo{ 15977 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15978 }, 15979 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15980 }, 15981 }, 15982 { 15983 name: "DUFFZERO", 15984 auxType: auxInt64, 15985 argLen: 2, 15986 faultOnNilArg0: true, 15987 reg: regInfo{ 15988 inputs: []inputInfo{ 15989 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15990 }, 15991 clobbers: 134217730, // R1 R31 15992 }, 15993 }, 15994 { 15995 name: "LoweredZero", 15996 auxType: auxInt64, 15997 argLen: 3, 15998 clobberFlags: true, 15999 faultOnNilArg0: true, 16000 reg: regInfo{ 16001 inputs: []inputInfo{ 16002 {0, 2}, // R1 16003 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16004 }, 16005 clobbers: 2, // R1 16006 }, 16007 }, 16008 { 16009 name: "LoweredMove", 16010 auxType: auxInt64, 16011 argLen: 4, 16012 clobberFlags: true, 16013 faultOnNilArg0: true, 16014 faultOnNilArg1: true, 16015 reg: regInfo{ 16016 inputs: []inputInfo{ 16017 {0, 4}, // R2 16018 {1, 2}, // R1 16019 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16020 }, 16021 clobbers: 6, // R1 R2 16022 }, 16023 }, 16024 { 16025 name: "LoweredNilCheck", 16026 argLen: 2, 16027 nilCheck: true, 16028 faultOnNilArg0: true, 16029 reg: regInfo{ 16030 inputs: []inputInfo{ 16031 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16032 }, 16033 }, 16034 }, 16035 { 16036 name: "FPFlagTrue", 16037 argLen: 1, 16038 reg: regInfo{ 16039 outputs: []outputInfo{ 16040 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16041 }, 16042 }, 16043 }, 16044 { 16045 name: "FPFlagFalse", 16046 argLen: 1, 16047 reg: regInfo{ 16048 outputs: []outputInfo{ 16049 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16050 }, 16051 }, 16052 }, 16053 { 16054 name: "LoweredGetClosurePtr", 16055 argLen: 0, 16056 reg: regInfo{ 16057 outputs: []outputInfo{ 16058 {0, 4194304}, // R22 16059 }, 16060 }, 16061 }, 16062 { 16063 name: "MOVVconvert", 16064 argLen: 2, 16065 asm: mips.AMOVV, 16066 reg: regInfo{ 16067 inputs: []inputInfo{ 16068 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16069 }, 16070 outputs: []outputInfo{ 16071 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16072 }, 16073 }, 16074 }, 16075 16076 { 16077 name: "ADD", 16078 argLen: 2, 16079 commutative: true, 16080 asm: ppc64.AADD, 16081 reg: regInfo{ 16082 inputs: []inputInfo{ 16083 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16084 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16085 }, 16086 outputs: []outputInfo{ 16087 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16088 }, 16089 }, 16090 }, 16091 { 16092 name: "ADDconst", 16093 auxType: auxSymOff, 16094 argLen: 1, 16095 symEffect: SymAddr, 16096 asm: ppc64.AADD, 16097 reg: regInfo{ 16098 inputs: []inputInfo{ 16099 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16100 }, 16101 outputs: []outputInfo{ 16102 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16103 }, 16104 }, 16105 }, 16106 { 16107 name: "FADD", 16108 argLen: 2, 16109 commutative: true, 16110 asm: ppc64.AFADD, 16111 reg: regInfo{ 16112 inputs: []inputInfo{ 16113 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16114 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16115 }, 16116 outputs: []outputInfo{ 16117 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16118 }, 16119 }, 16120 }, 16121 { 16122 name: "FADDS", 16123 argLen: 2, 16124 commutative: true, 16125 asm: ppc64.AFADDS, 16126 reg: regInfo{ 16127 inputs: []inputInfo{ 16128 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16129 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16130 }, 16131 outputs: []outputInfo{ 16132 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16133 }, 16134 }, 16135 }, 16136 { 16137 name: "SUB", 16138 argLen: 2, 16139 asm: ppc64.ASUB, 16140 reg: regInfo{ 16141 inputs: []inputInfo{ 16142 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16143 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16144 }, 16145 outputs: []outputInfo{ 16146 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16147 }, 16148 }, 16149 }, 16150 { 16151 name: "FSUB", 16152 argLen: 2, 16153 asm: ppc64.AFSUB, 16154 reg: regInfo{ 16155 inputs: []inputInfo{ 16156 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16157 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16158 }, 16159 outputs: []outputInfo{ 16160 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16161 }, 16162 }, 16163 }, 16164 { 16165 name: "FSUBS", 16166 argLen: 2, 16167 asm: ppc64.AFSUBS, 16168 reg: regInfo{ 16169 inputs: []inputInfo{ 16170 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16171 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16172 }, 16173 outputs: []outputInfo{ 16174 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16175 }, 16176 }, 16177 }, 16178 { 16179 name: "MULLD", 16180 argLen: 2, 16181 commutative: true, 16182 asm: ppc64.AMULLD, 16183 reg: regInfo{ 16184 inputs: []inputInfo{ 16185 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16186 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16187 }, 16188 outputs: []outputInfo{ 16189 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16190 }, 16191 }, 16192 }, 16193 { 16194 name: "MULLW", 16195 argLen: 2, 16196 commutative: true, 16197 asm: ppc64.AMULLW, 16198 reg: regInfo{ 16199 inputs: []inputInfo{ 16200 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16201 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16202 }, 16203 outputs: []outputInfo{ 16204 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16205 }, 16206 }, 16207 }, 16208 { 16209 name: "MULHD", 16210 argLen: 2, 16211 commutative: true, 16212 asm: ppc64.AMULHD, 16213 reg: regInfo{ 16214 inputs: []inputInfo{ 16215 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16216 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16217 }, 16218 outputs: []outputInfo{ 16219 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16220 }, 16221 }, 16222 }, 16223 { 16224 name: "MULHW", 16225 argLen: 2, 16226 commutative: true, 16227 asm: ppc64.AMULHW, 16228 reg: regInfo{ 16229 inputs: []inputInfo{ 16230 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16231 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16232 }, 16233 outputs: []outputInfo{ 16234 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16235 }, 16236 }, 16237 }, 16238 { 16239 name: "MULHDU", 16240 argLen: 2, 16241 commutative: true, 16242 asm: ppc64.AMULHDU, 16243 reg: regInfo{ 16244 inputs: []inputInfo{ 16245 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16246 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16247 }, 16248 outputs: []outputInfo{ 16249 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16250 }, 16251 }, 16252 }, 16253 { 16254 name: "MULHWU", 16255 argLen: 2, 16256 commutative: true, 16257 asm: ppc64.AMULHWU, 16258 reg: regInfo{ 16259 inputs: []inputInfo{ 16260 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16261 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16262 }, 16263 outputs: []outputInfo{ 16264 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16265 }, 16266 }, 16267 }, 16268 { 16269 name: "FMUL", 16270 argLen: 2, 16271 commutative: true, 16272 asm: ppc64.AFMUL, 16273 reg: regInfo{ 16274 inputs: []inputInfo{ 16275 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16276 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16277 }, 16278 outputs: []outputInfo{ 16279 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16280 }, 16281 }, 16282 }, 16283 { 16284 name: "FMULS", 16285 argLen: 2, 16286 commutative: true, 16287 asm: ppc64.AFMULS, 16288 reg: regInfo{ 16289 inputs: []inputInfo{ 16290 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16291 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16292 }, 16293 outputs: []outputInfo{ 16294 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16295 }, 16296 }, 16297 }, 16298 { 16299 name: "FMADD", 16300 argLen: 3, 16301 asm: ppc64.AFMADD, 16302 reg: regInfo{ 16303 inputs: []inputInfo{ 16304 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16305 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16306 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16307 }, 16308 outputs: []outputInfo{ 16309 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16310 }, 16311 }, 16312 }, 16313 { 16314 name: "FMADDS", 16315 argLen: 3, 16316 asm: ppc64.AFMADDS, 16317 reg: regInfo{ 16318 inputs: []inputInfo{ 16319 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16320 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16321 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16322 }, 16323 outputs: []outputInfo{ 16324 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16325 }, 16326 }, 16327 }, 16328 { 16329 name: "FMSUB", 16330 argLen: 3, 16331 asm: ppc64.AFMSUB, 16332 reg: regInfo{ 16333 inputs: []inputInfo{ 16334 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16335 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16336 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16337 }, 16338 outputs: []outputInfo{ 16339 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16340 }, 16341 }, 16342 }, 16343 { 16344 name: "FMSUBS", 16345 argLen: 3, 16346 asm: ppc64.AFMSUBS, 16347 reg: regInfo{ 16348 inputs: []inputInfo{ 16349 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16350 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16351 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16352 }, 16353 outputs: []outputInfo{ 16354 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16355 }, 16356 }, 16357 }, 16358 { 16359 name: "SRAD", 16360 argLen: 2, 16361 asm: ppc64.ASRAD, 16362 reg: regInfo{ 16363 inputs: []inputInfo{ 16364 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16365 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16366 }, 16367 outputs: []outputInfo{ 16368 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16369 }, 16370 }, 16371 }, 16372 { 16373 name: "SRAW", 16374 argLen: 2, 16375 asm: ppc64.ASRAW, 16376 reg: regInfo{ 16377 inputs: []inputInfo{ 16378 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16379 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16380 }, 16381 outputs: []outputInfo{ 16382 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16383 }, 16384 }, 16385 }, 16386 { 16387 name: "SRD", 16388 argLen: 2, 16389 asm: ppc64.ASRD, 16390 reg: regInfo{ 16391 inputs: []inputInfo{ 16392 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16393 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16394 }, 16395 outputs: []outputInfo{ 16396 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16397 }, 16398 }, 16399 }, 16400 { 16401 name: "SRW", 16402 argLen: 2, 16403 asm: ppc64.ASRW, 16404 reg: regInfo{ 16405 inputs: []inputInfo{ 16406 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16407 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16408 }, 16409 outputs: []outputInfo{ 16410 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16411 }, 16412 }, 16413 }, 16414 { 16415 name: "SLD", 16416 argLen: 2, 16417 asm: ppc64.ASLD, 16418 reg: regInfo{ 16419 inputs: []inputInfo{ 16420 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16421 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16422 }, 16423 outputs: []outputInfo{ 16424 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16425 }, 16426 }, 16427 }, 16428 { 16429 name: "SLW", 16430 argLen: 2, 16431 asm: ppc64.ASLW, 16432 reg: regInfo{ 16433 inputs: []inputInfo{ 16434 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16435 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16436 }, 16437 outputs: []outputInfo{ 16438 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16439 }, 16440 }, 16441 }, 16442 { 16443 name: "ADDconstForCarry", 16444 auxType: auxInt16, 16445 argLen: 1, 16446 asm: ppc64.AADDC, 16447 reg: regInfo{ 16448 inputs: []inputInfo{ 16449 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16450 }, 16451 clobbers: 2147483648, // R31 16452 }, 16453 }, 16454 { 16455 name: "MaskIfNotCarry", 16456 argLen: 1, 16457 asm: ppc64.AADDME, 16458 reg: regInfo{ 16459 outputs: []outputInfo{ 16460 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16461 }, 16462 }, 16463 }, 16464 { 16465 name: "SRADconst", 16466 auxType: auxInt64, 16467 argLen: 1, 16468 asm: ppc64.ASRAD, 16469 reg: regInfo{ 16470 inputs: []inputInfo{ 16471 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16472 }, 16473 outputs: []outputInfo{ 16474 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16475 }, 16476 }, 16477 }, 16478 { 16479 name: "SRAWconst", 16480 auxType: auxInt64, 16481 argLen: 1, 16482 asm: ppc64.ASRAW, 16483 reg: regInfo{ 16484 inputs: []inputInfo{ 16485 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16486 }, 16487 outputs: []outputInfo{ 16488 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16489 }, 16490 }, 16491 }, 16492 { 16493 name: "SRDconst", 16494 auxType: auxInt64, 16495 argLen: 1, 16496 asm: ppc64.ASRD, 16497 reg: regInfo{ 16498 inputs: []inputInfo{ 16499 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16500 }, 16501 outputs: []outputInfo{ 16502 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16503 }, 16504 }, 16505 }, 16506 { 16507 name: "SRWconst", 16508 auxType: auxInt64, 16509 argLen: 1, 16510 asm: ppc64.ASRW, 16511 reg: regInfo{ 16512 inputs: []inputInfo{ 16513 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16514 }, 16515 outputs: []outputInfo{ 16516 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16517 }, 16518 }, 16519 }, 16520 { 16521 name: "SLDconst", 16522 auxType: auxInt64, 16523 argLen: 1, 16524 asm: ppc64.ASLD, 16525 reg: regInfo{ 16526 inputs: []inputInfo{ 16527 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16528 }, 16529 outputs: []outputInfo{ 16530 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16531 }, 16532 }, 16533 }, 16534 { 16535 name: "SLWconst", 16536 auxType: auxInt64, 16537 argLen: 1, 16538 asm: ppc64.ASLW, 16539 reg: regInfo{ 16540 inputs: []inputInfo{ 16541 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16542 }, 16543 outputs: []outputInfo{ 16544 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16545 }, 16546 }, 16547 }, 16548 { 16549 name: "ROTLconst", 16550 auxType: auxInt64, 16551 argLen: 1, 16552 asm: ppc64.AROTL, 16553 reg: regInfo{ 16554 inputs: []inputInfo{ 16555 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16556 }, 16557 outputs: []outputInfo{ 16558 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16559 }, 16560 }, 16561 }, 16562 { 16563 name: "ROTLWconst", 16564 auxType: auxInt64, 16565 argLen: 1, 16566 asm: ppc64.AROTLW, 16567 reg: regInfo{ 16568 inputs: []inputInfo{ 16569 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16570 }, 16571 outputs: []outputInfo{ 16572 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16573 }, 16574 }, 16575 }, 16576 { 16577 name: "CNTLZD", 16578 argLen: 1, 16579 clobberFlags: true, 16580 asm: ppc64.ACNTLZD, 16581 reg: regInfo{ 16582 inputs: []inputInfo{ 16583 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16584 }, 16585 outputs: []outputInfo{ 16586 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16587 }, 16588 }, 16589 }, 16590 { 16591 name: "CNTLZW", 16592 argLen: 1, 16593 clobberFlags: true, 16594 asm: ppc64.ACNTLZW, 16595 reg: regInfo{ 16596 inputs: []inputInfo{ 16597 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16598 }, 16599 outputs: []outputInfo{ 16600 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16601 }, 16602 }, 16603 }, 16604 { 16605 name: "POPCNTD", 16606 argLen: 1, 16607 asm: ppc64.APOPCNTD, 16608 reg: regInfo{ 16609 inputs: []inputInfo{ 16610 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16611 }, 16612 outputs: []outputInfo{ 16613 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16614 }, 16615 }, 16616 }, 16617 { 16618 name: "POPCNTW", 16619 argLen: 1, 16620 asm: ppc64.APOPCNTW, 16621 reg: regInfo{ 16622 inputs: []inputInfo{ 16623 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16624 }, 16625 outputs: []outputInfo{ 16626 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16627 }, 16628 }, 16629 }, 16630 { 16631 name: "POPCNTB", 16632 argLen: 1, 16633 asm: ppc64.APOPCNTB, 16634 reg: regInfo{ 16635 inputs: []inputInfo{ 16636 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16637 }, 16638 outputs: []outputInfo{ 16639 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16640 }, 16641 }, 16642 }, 16643 { 16644 name: "FDIV", 16645 argLen: 2, 16646 asm: ppc64.AFDIV, 16647 reg: regInfo{ 16648 inputs: []inputInfo{ 16649 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16650 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16651 }, 16652 outputs: []outputInfo{ 16653 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16654 }, 16655 }, 16656 }, 16657 { 16658 name: "FDIVS", 16659 argLen: 2, 16660 asm: ppc64.AFDIVS, 16661 reg: regInfo{ 16662 inputs: []inputInfo{ 16663 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16664 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16665 }, 16666 outputs: []outputInfo{ 16667 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16668 }, 16669 }, 16670 }, 16671 { 16672 name: "DIVD", 16673 argLen: 2, 16674 asm: ppc64.ADIVD, 16675 reg: regInfo{ 16676 inputs: []inputInfo{ 16677 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16678 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16679 }, 16680 outputs: []outputInfo{ 16681 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16682 }, 16683 }, 16684 }, 16685 { 16686 name: "DIVW", 16687 argLen: 2, 16688 asm: ppc64.ADIVW, 16689 reg: regInfo{ 16690 inputs: []inputInfo{ 16691 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16692 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16693 }, 16694 outputs: []outputInfo{ 16695 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16696 }, 16697 }, 16698 }, 16699 { 16700 name: "DIVDU", 16701 argLen: 2, 16702 asm: ppc64.ADIVDU, 16703 reg: regInfo{ 16704 inputs: []inputInfo{ 16705 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16706 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16707 }, 16708 outputs: []outputInfo{ 16709 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16710 }, 16711 }, 16712 }, 16713 { 16714 name: "DIVWU", 16715 argLen: 2, 16716 asm: ppc64.ADIVWU, 16717 reg: regInfo{ 16718 inputs: []inputInfo{ 16719 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16720 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16721 }, 16722 outputs: []outputInfo{ 16723 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16724 }, 16725 }, 16726 }, 16727 { 16728 name: "FCTIDZ", 16729 argLen: 1, 16730 asm: ppc64.AFCTIDZ, 16731 reg: regInfo{ 16732 inputs: []inputInfo{ 16733 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16734 }, 16735 outputs: []outputInfo{ 16736 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16737 }, 16738 }, 16739 }, 16740 { 16741 name: "FCTIWZ", 16742 argLen: 1, 16743 asm: ppc64.AFCTIWZ, 16744 reg: regInfo{ 16745 inputs: []inputInfo{ 16746 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16747 }, 16748 outputs: []outputInfo{ 16749 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16750 }, 16751 }, 16752 }, 16753 { 16754 name: "FCFID", 16755 argLen: 1, 16756 asm: ppc64.AFCFID, 16757 reg: regInfo{ 16758 inputs: []inputInfo{ 16759 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16760 }, 16761 outputs: []outputInfo{ 16762 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16763 }, 16764 }, 16765 }, 16766 { 16767 name: "FRSP", 16768 argLen: 1, 16769 asm: ppc64.AFRSP, 16770 reg: regInfo{ 16771 inputs: []inputInfo{ 16772 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16773 }, 16774 outputs: []outputInfo{ 16775 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16776 }, 16777 }, 16778 }, 16779 { 16780 name: "Xf2i64", 16781 argLen: 1, 16782 reg: regInfo{ 16783 inputs: []inputInfo{ 16784 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16785 }, 16786 outputs: []outputInfo{ 16787 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16788 }, 16789 }, 16790 }, 16791 { 16792 name: "Xi2f64", 16793 argLen: 1, 16794 reg: regInfo{ 16795 inputs: []inputInfo{ 16796 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16797 }, 16798 outputs: []outputInfo{ 16799 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16800 }, 16801 }, 16802 }, 16803 { 16804 name: "AND", 16805 argLen: 2, 16806 commutative: true, 16807 asm: ppc64.AAND, 16808 reg: regInfo{ 16809 inputs: []inputInfo{ 16810 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16811 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16812 }, 16813 outputs: []outputInfo{ 16814 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16815 }, 16816 }, 16817 }, 16818 { 16819 name: "ANDN", 16820 argLen: 2, 16821 asm: ppc64.AANDN, 16822 reg: regInfo{ 16823 inputs: []inputInfo{ 16824 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16825 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16826 }, 16827 outputs: []outputInfo{ 16828 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16829 }, 16830 }, 16831 }, 16832 { 16833 name: "OR", 16834 argLen: 2, 16835 commutative: true, 16836 asm: ppc64.AOR, 16837 reg: regInfo{ 16838 inputs: []inputInfo{ 16839 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16840 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16841 }, 16842 outputs: []outputInfo{ 16843 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16844 }, 16845 }, 16846 }, 16847 { 16848 name: "ORN", 16849 argLen: 2, 16850 asm: ppc64.AORN, 16851 reg: regInfo{ 16852 inputs: []inputInfo{ 16853 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16854 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16855 }, 16856 outputs: []outputInfo{ 16857 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16858 }, 16859 }, 16860 }, 16861 { 16862 name: "NOR", 16863 argLen: 2, 16864 commutative: true, 16865 asm: ppc64.ANOR, 16866 reg: regInfo{ 16867 inputs: []inputInfo{ 16868 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16869 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16870 }, 16871 outputs: []outputInfo{ 16872 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16873 }, 16874 }, 16875 }, 16876 { 16877 name: "XOR", 16878 argLen: 2, 16879 commutative: true, 16880 asm: ppc64.AXOR, 16881 reg: regInfo{ 16882 inputs: []inputInfo{ 16883 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16884 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16885 }, 16886 outputs: []outputInfo{ 16887 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16888 }, 16889 }, 16890 }, 16891 { 16892 name: "EQV", 16893 argLen: 2, 16894 commutative: true, 16895 asm: ppc64.AEQV, 16896 reg: regInfo{ 16897 inputs: []inputInfo{ 16898 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16899 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16900 }, 16901 outputs: []outputInfo{ 16902 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16903 }, 16904 }, 16905 }, 16906 { 16907 name: "NEG", 16908 argLen: 1, 16909 asm: ppc64.ANEG, 16910 reg: regInfo{ 16911 inputs: []inputInfo{ 16912 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16913 }, 16914 outputs: []outputInfo{ 16915 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16916 }, 16917 }, 16918 }, 16919 { 16920 name: "FNEG", 16921 argLen: 1, 16922 asm: ppc64.AFNEG, 16923 reg: regInfo{ 16924 inputs: []inputInfo{ 16925 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16926 }, 16927 outputs: []outputInfo{ 16928 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16929 }, 16930 }, 16931 }, 16932 { 16933 name: "FSQRT", 16934 argLen: 1, 16935 asm: ppc64.AFSQRT, 16936 reg: regInfo{ 16937 inputs: []inputInfo{ 16938 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16939 }, 16940 outputs: []outputInfo{ 16941 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16942 }, 16943 }, 16944 }, 16945 { 16946 name: "FSQRTS", 16947 argLen: 1, 16948 asm: ppc64.AFSQRTS, 16949 reg: regInfo{ 16950 inputs: []inputInfo{ 16951 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16952 }, 16953 outputs: []outputInfo{ 16954 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16955 }, 16956 }, 16957 }, 16958 { 16959 name: "ORconst", 16960 auxType: auxInt64, 16961 argLen: 1, 16962 asm: ppc64.AOR, 16963 reg: regInfo{ 16964 inputs: []inputInfo{ 16965 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16966 }, 16967 outputs: []outputInfo{ 16968 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16969 }, 16970 }, 16971 }, 16972 { 16973 name: "XORconst", 16974 auxType: auxInt64, 16975 argLen: 1, 16976 asm: ppc64.AXOR, 16977 reg: regInfo{ 16978 inputs: []inputInfo{ 16979 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16980 }, 16981 outputs: []outputInfo{ 16982 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16983 }, 16984 }, 16985 }, 16986 { 16987 name: "ANDconst", 16988 auxType: auxInt64, 16989 argLen: 1, 16990 clobberFlags: true, 16991 asm: ppc64.AANDCC, 16992 reg: regInfo{ 16993 inputs: []inputInfo{ 16994 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16995 }, 16996 outputs: []outputInfo{ 16997 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16998 }, 16999 }, 17000 }, 17001 { 17002 name: "ANDCCconst", 17003 auxType: auxInt64, 17004 argLen: 1, 17005 asm: ppc64.AANDCC, 17006 reg: regInfo{ 17007 inputs: []inputInfo{ 17008 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17009 }, 17010 }, 17011 }, 17012 { 17013 name: "MOVBreg", 17014 argLen: 1, 17015 asm: ppc64.AMOVB, 17016 reg: regInfo{ 17017 inputs: []inputInfo{ 17018 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17019 }, 17020 outputs: []outputInfo{ 17021 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17022 }, 17023 }, 17024 }, 17025 { 17026 name: "MOVBZreg", 17027 argLen: 1, 17028 asm: ppc64.AMOVBZ, 17029 reg: regInfo{ 17030 inputs: []inputInfo{ 17031 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17032 }, 17033 outputs: []outputInfo{ 17034 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17035 }, 17036 }, 17037 }, 17038 { 17039 name: "MOVHreg", 17040 argLen: 1, 17041 asm: ppc64.AMOVH, 17042 reg: regInfo{ 17043 inputs: []inputInfo{ 17044 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17045 }, 17046 outputs: []outputInfo{ 17047 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17048 }, 17049 }, 17050 }, 17051 { 17052 name: "MOVHZreg", 17053 argLen: 1, 17054 asm: ppc64.AMOVHZ, 17055 reg: regInfo{ 17056 inputs: []inputInfo{ 17057 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17058 }, 17059 outputs: []outputInfo{ 17060 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17061 }, 17062 }, 17063 }, 17064 { 17065 name: "MOVWreg", 17066 argLen: 1, 17067 asm: ppc64.AMOVW, 17068 reg: regInfo{ 17069 inputs: []inputInfo{ 17070 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17071 }, 17072 outputs: []outputInfo{ 17073 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17074 }, 17075 }, 17076 }, 17077 { 17078 name: "MOVWZreg", 17079 argLen: 1, 17080 asm: ppc64.AMOVWZ, 17081 reg: regInfo{ 17082 inputs: []inputInfo{ 17083 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17084 }, 17085 outputs: []outputInfo{ 17086 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17087 }, 17088 }, 17089 }, 17090 { 17091 name: "MOVBZload", 17092 auxType: auxSymOff, 17093 argLen: 2, 17094 faultOnNilArg0: true, 17095 symEffect: SymRead, 17096 asm: ppc64.AMOVBZ, 17097 reg: regInfo{ 17098 inputs: []inputInfo{ 17099 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17100 }, 17101 outputs: []outputInfo{ 17102 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17103 }, 17104 }, 17105 }, 17106 { 17107 name: "MOVHload", 17108 auxType: auxSymOff, 17109 argLen: 2, 17110 faultOnNilArg0: true, 17111 symEffect: SymRead, 17112 asm: ppc64.AMOVH, 17113 reg: regInfo{ 17114 inputs: []inputInfo{ 17115 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17116 }, 17117 outputs: []outputInfo{ 17118 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17119 }, 17120 }, 17121 }, 17122 { 17123 name: "MOVHZload", 17124 auxType: auxSymOff, 17125 argLen: 2, 17126 faultOnNilArg0: true, 17127 symEffect: SymRead, 17128 asm: ppc64.AMOVHZ, 17129 reg: regInfo{ 17130 inputs: []inputInfo{ 17131 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17132 }, 17133 outputs: []outputInfo{ 17134 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17135 }, 17136 }, 17137 }, 17138 { 17139 name: "MOVWload", 17140 auxType: auxSymOff, 17141 argLen: 2, 17142 faultOnNilArg0: true, 17143 symEffect: SymRead, 17144 asm: ppc64.AMOVW, 17145 reg: regInfo{ 17146 inputs: []inputInfo{ 17147 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17148 }, 17149 outputs: []outputInfo{ 17150 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17151 }, 17152 }, 17153 }, 17154 { 17155 name: "MOVWZload", 17156 auxType: auxSymOff, 17157 argLen: 2, 17158 faultOnNilArg0: true, 17159 symEffect: SymRead, 17160 asm: ppc64.AMOVWZ, 17161 reg: regInfo{ 17162 inputs: []inputInfo{ 17163 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17164 }, 17165 outputs: []outputInfo{ 17166 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17167 }, 17168 }, 17169 }, 17170 { 17171 name: "MOVDload", 17172 auxType: auxSymOff, 17173 argLen: 2, 17174 faultOnNilArg0: true, 17175 symEffect: SymRead, 17176 asm: ppc64.AMOVD, 17177 reg: regInfo{ 17178 inputs: []inputInfo{ 17179 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17180 }, 17181 outputs: []outputInfo{ 17182 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17183 }, 17184 }, 17185 }, 17186 { 17187 name: "FMOVDload", 17188 auxType: auxSymOff, 17189 argLen: 2, 17190 faultOnNilArg0: true, 17191 symEffect: SymRead, 17192 asm: ppc64.AFMOVD, 17193 reg: regInfo{ 17194 inputs: []inputInfo{ 17195 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17196 }, 17197 outputs: []outputInfo{ 17198 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17199 }, 17200 }, 17201 }, 17202 { 17203 name: "FMOVSload", 17204 auxType: auxSymOff, 17205 argLen: 2, 17206 faultOnNilArg0: true, 17207 symEffect: SymRead, 17208 asm: ppc64.AFMOVS, 17209 reg: regInfo{ 17210 inputs: []inputInfo{ 17211 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17212 }, 17213 outputs: []outputInfo{ 17214 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17215 }, 17216 }, 17217 }, 17218 { 17219 name: "MOVBstore", 17220 auxType: auxSymOff, 17221 argLen: 3, 17222 faultOnNilArg0: true, 17223 symEffect: SymWrite, 17224 asm: ppc64.AMOVB, 17225 reg: regInfo{ 17226 inputs: []inputInfo{ 17227 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17228 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17229 }, 17230 }, 17231 }, 17232 { 17233 name: "MOVHstore", 17234 auxType: auxSymOff, 17235 argLen: 3, 17236 faultOnNilArg0: true, 17237 symEffect: SymWrite, 17238 asm: ppc64.AMOVH, 17239 reg: regInfo{ 17240 inputs: []inputInfo{ 17241 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17242 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17243 }, 17244 }, 17245 }, 17246 { 17247 name: "MOVWstore", 17248 auxType: auxSymOff, 17249 argLen: 3, 17250 faultOnNilArg0: true, 17251 symEffect: SymWrite, 17252 asm: ppc64.AMOVW, 17253 reg: regInfo{ 17254 inputs: []inputInfo{ 17255 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17256 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17257 }, 17258 }, 17259 }, 17260 { 17261 name: "MOVDstore", 17262 auxType: auxSymOff, 17263 argLen: 3, 17264 faultOnNilArg0: true, 17265 symEffect: SymWrite, 17266 asm: ppc64.AMOVD, 17267 reg: regInfo{ 17268 inputs: []inputInfo{ 17269 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17270 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17271 }, 17272 }, 17273 }, 17274 { 17275 name: "FMOVDstore", 17276 auxType: auxSymOff, 17277 argLen: 3, 17278 faultOnNilArg0: true, 17279 symEffect: SymWrite, 17280 asm: ppc64.AFMOVD, 17281 reg: regInfo{ 17282 inputs: []inputInfo{ 17283 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17284 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17285 }, 17286 }, 17287 }, 17288 { 17289 name: "FMOVSstore", 17290 auxType: auxSymOff, 17291 argLen: 3, 17292 faultOnNilArg0: true, 17293 symEffect: SymWrite, 17294 asm: ppc64.AFMOVS, 17295 reg: regInfo{ 17296 inputs: []inputInfo{ 17297 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17298 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17299 }, 17300 }, 17301 }, 17302 { 17303 name: "MOVBstorezero", 17304 auxType: auxSymOff, 17305 argLen: 2, 17306 faultOnNilArg0: true, 17307 symEffect: SymWrite, 17308 asm: ppc64.AMOVB, 17309 reg: regInfo{ 17310 inputs: []inputInfo{ 17311 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17312 }, 17313 }, 17314 }, 17315 { 17316 name: "MOVHstorezero", 17317 auxType: auxSymOff, 17318 argLen: 2, 17319 faultOnNilArg0: true, 17320 symEffect: SymWrite, 17321 asm: ppc64.AMOVH, 17322 reg: regInfo{ 17323 inputs: []inputInfo{ 17324 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17325 }, 17326 }, 17327 }, 17328 { 17329 name: "MOVWstorezero", 17330 auxType: auxSymOff, 17331 argLen: 2, 17332 faultOnNilArg0: true, 17333 symEffect: SymWrite, 17334 asm: ppc64.AMOVW, 17335 reg: regInfo{ 17336 inputs: []inputInfo{ 17337 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17338 }, 17339 }, 17340 }, 17341 { 17342 name: "MOVDstorezero", 17343 auxType: auxSymOff, 17344 argLen: 2, 17345 faultOnNilArg0: true, 17346 symEffect: SymWrite, 17347 asm: ppc64.AMOVD, 17348 reg: regInfo{ 17349 inputs: []inputInfo{ 17350 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17351 }, 17352 }, 17353 }, 17354 { 17355 name: "MOVDaddr", 17356 auxType: auxSymOff, 17357 argLen: 1, 17358 rematerializeable: true, 17359 symEffect: SymAddr, 17360 asm: ppc64.AMOVD, 17361 reg: regInfo{ 17362 inputs: []inputInfo{ 17363 {0, 6}, // SP SB 17364 }, 17365 outputs: []outputInfo{ 17366 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17367 }, 17368 }, 17369 }, 17370 { 17371 name: "MOVDconst", 17372 auxType: auxInt64, 17373 argLen: 0, 17374 rematerializeable: true, 17375 asm: ppc64.AMOVD, 17376 reg: regInfo{ 17377 outputs: []outputInfo{ 17378 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17379 }, 17380 }, 17381 }, 17382 { 17383 name: "FMOVDconst", 17384 auxType: auxFloat64, 17385 argLen: 0, 17386 rematerializeable: true, 17387 asm: ppc64.AFMOVD, 17388 reg: regInfo{ 17389 outputs: []outputInfo{ 17390 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17391 }, 17392 }, 17393 }, 17394 { 17395 name: "FMOVSconst", 17396 auxType: auxFloat32, 17397 argLen: 0, 17398 rematerializeable: true, 17399 asm: ppc64.AFMOVS, 17400 reg: regInfo{ 17401 outputs: []outputInfo{ 17402 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17403 }, 17404 }, 17405 }, 17406 { 17407 name: "FCMPU", 17408 argLen: 2, 17409 asm: ppc64.AFCMPU, 17410 reg: regInfo{ 17411 inputs: []inputInfo{ 17412 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17413 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17414 }, 17415 }, 17416 }, 17417 { 17418 name: "CMP", 17419 argLen: 2, 17420 asm: ppc64.ACMP, 17421 reg: regInfo{ 17422 inputs: []inputInfo{ 17423 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17424 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17425 }, 17426 }, 17427 }, 17428 { 17429 name: "CMPU", 17430 argLen: 2, 17431 asm: ppc64.ACMPU, 17432 reg: regInfo{ 17433 inputs: []inputInfo{ 17434 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17435 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17436 }, 17437 }, 17438 }, 17439 { 17440 name: "CMPW", 17441 argLen: 2, 17442 asm: ppc64.ACMPW, 17443 reg: regInfo{ 17444 inputs: []inputInfo{ 17445 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17446 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17447 }, 17448 }, 17449 }, 17450 { 17451 name: "CMPWU", 17452 argLen: 2, 17453 asm: ppc64.ACMPWU, 17454 reg: regInfo{ 17455 inputs: []inputInfo{ 17456 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17457 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17458 }, 17459 }, 17460 }, 17461 { 17462 name: "CMPconst", 17463 auxType: auxInt64, 17464 argLen: 1, 17465 asm: ppc64.ACMP, 17466 reg: regInfo{ 17467 inputs: []inputInfo{ 17468 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17469 }, 17470 }, 17471 }, 17472 { 17473 name: "CMPUconst", 17474 auxType: auxInt64, 17475 argLen: 1, 17476 asm: ppc64.ACMPU, 17477 reg: regInfo{ 17478 inputs: []inputInfo{ 17479 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17480 }, 17481 }, 17482 }, 17483 { 17484 name: "CMPWconst", 17485 auxType: auxInt32, 17486 argLen: 1, 17487 asm: ppc64.ACMPW, 17488 reg: regInfo{ 17489 inputs: []inputInfo{ 17490 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17491 }, 17492 }, 17493 }, 17494 { 17495 name: "CMPWUconst", 17496 auxType: auxInt32, 17497 argLen: 1, 17498 asm: ppc64.ACMPWU, 17499 reg: regInfo{ 17500 inputs: []inputInfo{ 17501 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17502 }, 17503 }, 17504 }, 17505 { 17506 name: "Equal", 17507 argLen: 1, 17508 reg: regInfo{ 17509 outputs: []outputInfo{ 17510 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17511 }, 17512 }, 17513 }, 17514 { 17515 name: "NotEqual", 17516 argLen: 1, 17517 reg: regInfo{ 17518 outputs: []outputInfo{ 17519 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17520 }, 17521 }, 17522 }, 17523 { 17524 name: "LessThan", 17525 argLen: 1, 17526 reg: regInfo{ 17527 outputs: []outputInfo{ 17528 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17529 }, 17530 }, 17531 }, 17532 { 17533 name: "FLessThan", 17534 argLen: 1, 17535 reg: regInfo{ 17536 outputs: []outputInfo{ 17537 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17538 }, 17539 }, 17540 }, 17541 { 17542 name: "LessEqual", 17543 argLen: 1, 17544 reg: regInfo{ 17545 outputs: []outputInfo{ 17546 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17547 }, 17548 }, 17549 }, 17550 { 17551 name: "FLessEqual", 17552 argLen: 1, 17553 reg: regInfo{ 17554 outputs: []outputInfo{ 17555 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17556 }, 17557 }, 17558 }, 17559 { 17560 name: "GreaterThan", 17561 argLen: 1, 17562 reg: regInfo{ 17563 outputs: []outputInfo{ 17564 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17565 }, 17566 }, 17567 }, 17568 { 17569 name: "FGreaterThan", 17570 argLen: 1, 17571 reg: regInfo{ 17572 outputs: []outputInfo{ 17573 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17574 }, 17575 }, 17576 }, 17577 { 17578 name: "GreaterEqual", 17579 argLen: 1, 17580 reg: regInfo{ 17581 outputs: []outputInfo{ 17582 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17583 }, 17584 }, 17585 }, 17586 { 17587 name: "FGreaterEqual", 17588 argLen: 1, 17589 reg: regInfo{ 17590 outputs: []outputInfo{ 17591 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17592 }, 17593 }, 17594 }, 17595 { 17596 name: "LoweredGetClosurePtr", 17597 argLen: 0, 17598 reg: regInfo{ 17599 outputs: []outputInfo{ 17600 {0, 2048}, // R11 17601 }, 17602 }, 17603 }, 17604 { 17605 name: "LoweredNilCheck", 17606 argLen: 2, 17607 clobberFlags: true, 17608 nilCheck: true, 17609 faultOnNilArg0: true, 17610 reg: regInfo{ 17611 inputs: []inputInfo{ 17612 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17613 }, 17614 clobbers: 2147483648, // R31 17615 }, 17616 }, 17617 { 17618 name: "LoweredRound32F", 17619 argLen: 1, 17620 resultInArg0: true, 17621 reg: regInfo{ 17622 inputs: []inputInfo{ 17623 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17624 }, 17625 outputs: []outputInfo{ 17626 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17627 }, 17628 }, 17629 }, 17630 { 17631 name: "LoweredRound64F", 17632 argLen: 1, 17633 resultInArg0: true, 17634 reg: regInfo{ 17635 inputs: []inputInfo{ 17636 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17637 }, 17638 outputs: []outputInfo{ 17639 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17640 }, 17641 }, 17642 }, 17643 { 17644 name: "MOVDconvert", 17645 argLen: 2, 17646 asm: ppc64.AMOVD, 17647 reg: regInfo{ 17648 inputs: []inputInfo{ 17649 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17650 }, 17651 outputs: []outputInfo{ 17652 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17653 }, 17654 }, 17655 }, 17656 { 17657 name: "CALLstatic", 17658 auxType: auxSymOff, 17659 argLen: 1, 17660 clobberFlags: true, 17661 call: true, 17662 symEffect: SymNone, 17663 reg: regInfo{ 17664 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17665 }, 17666 }, 17667 { 17668 name: "CALLclosure", 17669 auxType: auxInt64, 17670 argLen: 3, 17671 clobberFlags: true, 17672 call: true, 17673 reg: regInfo{ 17674 inputs: []inputInfo{ 17675 {1, 2048}, // R11 17676 {0, 1073733626}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17677 }, 17678 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17679 }, 17680 }, 17681 { 17682 name: "CALLinter", 17683 auxType: auxInt64, 17684 argLen: 2, 17685 clobberFlags: true, 17686 call: true, 17687 reg: regInfo{ 17688 inputs: []inputInfo{ 17689 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17690 }, 17691 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17692 }, 17693 }, 17694 { 17695 name: "LoweredZero", 17696 auxType: auxInt64, 17697 argLen: 2, 17698 clobberFlags: true, 17699 faultOnNilArg0: true, 17700 reg: regInfo{ 17701 inputs: []inputInfo{ 17702 {0, 8}, // R3 17703 }, 17704 clobbers: 8, // R3 17705 }, 17706 }, 17707 { 17708 name: "LoweredMove", 17709 auxType: auxInt64, 17710 argLen: 3, 17711 clobberFlags: true, 17712 faultOnNilArg0: true, 17713 faultOnNilArg1: true, 17714 reg: regInfo{ 17715 inputs: []inputInfo{ 17716 {0, 8}, // R3 17717 {1, 16}, // R4 17718 }, 17719 clobbers: 1944, // R3 R4 R7 R8 R9 R10 17720 }, 17721 }, 17722 { 17723 name: "LoweredAtomicStore32", 17724 argLen: 3, 17725 faultOnNilArg0: true, 17726 hasSideEffects: true, 17727 reg: regInfo{ 17728 inputs: []inputInfo{ 17729 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17730 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17731 }, 17732 }, 17733 }, 17734 { 17735 name: "LoweredAtomicStore64", 17736 argLen: 3, 17737 faultOnNilArg0: true, 17738 hasSideEffects: true, 17739 reg: regInfo{ 17740 inputs: []inputInfo{ 17741 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17742 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17743 }, 17744 }, 17745 }, 17746 { 17747 name: "LoweredAtomicLoad32", 17748 argLen: 2, 17749 clobberFlags: true, 17750 faultOnNilArg0: true, 17751 reg: regInfo{ 17752 inputs: []inputInfo{ 17753 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17754 }, 17755 outputs: []outputInfo{ 17756 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17757 }, 17758 }, 17759 }, 17760 { 17761 name: "LoweredAtomicLoad64", 17762 argLen: 2, 17763 clobberFlags: true, 17764 faultOnNilArg0: true, 17765 reg: regInfo{ 17766 inputs: []inputInfo{ 17767 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17768 }, 17769 outputs: []outputInfo{ 17770 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17771 }, 17772 }, 17773 }, 17774 { 17775 name: "LoweredAtomicLoadPtr", 17776 argLen: 2, 17777 clobberFlags: true, 17778 faultOnNilArg0: true, 17779 reg: regInfo{ 17780 inputs: []inputInfo{ 17781 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17782 }, 17783 outputs: []outputInfo{ 17784 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17785 }, 17786 }, 17787 }, 17788 { 17789 name: "LoweredAtomicAdd32", 17790 argLen: 3, 17791 resultNotInArgs: true, 17792 clobberFlags: true, 17793 faultOnNilArg0: true, 17794 hasSideEffects: true, 17795 reg: regInfo{ 17796 inputs: []inputInfo{ 17797 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17798 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17799 }, 17800 outputs: []outputInfo{ 17801 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17802 }, 17803 }, 17804 }, 17805 { 17806 name: "LoweredAtomicAdd64", 17807 argLen: 3, 17808 resultNotInArgs: true, 17809 clobberFlags: true, 17810 faultOnNilArg0: true, 17811 hasSideEffects: true, 17812 reg: regInfo{ 17813 inputs: []inputInfo{ 17814 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17815 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17816 }, 17817 outputs: []outputInfo{ 17818 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17819 }, 17820 }, 17821 }, 17822 { 17823 name: "LoweredAtomicExchange32", 17824 argLen: 3, 17825 resultNotInArgs: true, 17826 clobberFlags: true, 17827 faultOnNilArg0: true, 17828 hasSideEffects: true, 17829 reg: regInfo{ 17830 inputs: []inputInfo{ 17831 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17832 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17833 }, 17834 outputs: []outputInfo{ 17835 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17836 }, 17837 }, 17838 }, 17839 { 17840 name: "LoweredAtomicExchange64", 17841 argLen: 3, 17842 resultNotInArgs: true, 17843 clobberFlags: true, 17844 faultOnNilArg0: true, 17845 hasSideEffects: true, 17846 reg: regInfo{ 17847 inputs: []inputInfo{ 17848 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17849 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17850 }, 17851 outputs: []outputInfo{ 17852 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17853 }, 17854 }, 17855 }, 17856 { 17857 name: "LoweredAtomicCas64", 17858 argLen: 4, 17859 resultNotInArgs: true, 17860 clobberFlags: true, 17861 faultOnNilArg0: true, 17862 hasSideEffects: true, 17863 reg: regInfo{ 17864 inputs: []inputInfo{ 17865 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17866 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17867 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17868 }, 17869 outputs: []outputInfo{ 17870 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17871 }, 17872 }, 17873 }, 17874 { 17875 name: "LoweredAtomicCas32", 17876 argLen: 4, 17877 resultNotInArgs: true, 17878 clobberFlags: true, 17879 faultOnNilArg0: true, 17880 hasSideEffects: true, 17881 reg: regInfo{ 17882 inputs: []inputInfo{ 17883 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17884 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17885 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17886 }, 17887 outputs: []outputInfo{ 17888 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17889 }, 17890 }, 17891 }, 17892 { 17893 name: "LoweredAtomicAnd8", 17894 argLen: 3, 17895 faultOnNilArg0: true, 17896 hasSideEffects: true, 17897 asm: ppc64.AAND, 17898 reg: regInfo{ 17899 inputs: []inputInfo{ 17900 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17901 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17902 }, 17903 }, 17904 }, 17905 { 17906 name: "LoweredAtomicOr8", 17907 argLen: 3, 17908 faultOnNilArg0: true, 17909 hasSideEffects: true, 17910 asm: ppc64.AOR, 17911 reg: regInfo{ 17912 inputs: []inputInfo{ 17913 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17914 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17915 }, 17916 }, 17917 }, 17918 { 17919 name: "InvertFlags", 17920 argLen: 1, 17921 reg: regInfo{}, 17922 }, 17923 { 17924 name: "FlagEQ", 17925 argLen: 0, 17926 reg: regInfo{}, 17927 }, 17928 { 17929 name: "FlagLT", 17930 argLen: 0, 17931 reg: regInfo{}, 17932 }, 17933 { 17934 name: "FlagGT", 17935 argLen: 0, 17936 reg: regInfo{}, 17937 }, 17938 17939 { 17940 name: "FADDS", 17941 argLen: 2, 17942 commutative: true, 17943 resultInArg0: true, 17944 clobberFlags: true, 17945 asm: s390x.AFADDS, 17946 reg: regInfo{ 17947 inputs: []inputInfo{ 17948 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17949 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17950 }, 17951 outputs: []outputInfo{ 17952 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17953 }, 17954 }, 17955 }, 17956 { 17957 name: "FADD", 17958 argLen: 2, 17959 commutative: true, 17960 resultInArg0: true, 17961 clobberFlags: true, 17962 asm: s390x.AFADD, 17963 reg: regInfo{ 17964 inputs: []inputInfo{ 17965 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17966 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17967 }, 17968 outputs: []outputInfo{ 17969 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17970 }, 17971 }, 17972 }, 17973 { 17974 name: "FSUBS", 17975 argLen: 2, 17976 resultInArg0: true, 17977 clobberFlags: true, 17978 asm: s390x.AFSUBS, 17979 reg: regInfo{ 17980 inputs: []inputInfo{ 17981 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17982 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17983 }, 17984 outputs: []outputInfo{ 17985 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17986 }, 17987 }, 17988 }, 17989 { 17990 name: "FSUB", 17991 argLen: 2, 17992 resultInArg0: true, 17993 clobberFlags: true, 17994 asm: s390x.AFSUB, 17995 reg: regInfo{ 17996 inputs: []inputInfo{ 17997 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17998 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17999 }, 18000 outputs: []outputInfo{ 18001 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18002 }, 18003 }, 18004 }, 18005 { 18006 name: "FMULS", 18007 argLen: 2, 18008 commutative: true, 18009 resultInArg0: true, 18010 asm: s390x.AFMULS, 18011 reg: regInfo{ 18012 inputs: []inputInfo{ 18013 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18014 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18015 }, 18016 outputs: []outputInfo{ 18017 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18018 }, 18019 }, 18020 }, 18021 { 18022 name: "FMUL", 18023 argLen: 2, 18024 commutative: true, 18025 resultInArg0: true, 18026 asm: s390x.AFMUL, 18027 reg: regInfo{ 18028 inputs: []inputInfo{ 18029 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18030 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18031 }, 18032 outputs: []outputInfo{ 18033 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18034 }, 18035 }, 18036 }, 18037 { 18038 name: "FDIVS", 18039 argLen: 2, 18040 resultInArg0: true, 18041 asm: s390x.AFDIVS, 18042 reg: regInfo{ 18043 inputs: []inputInfo{ 18044 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18045 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18046 }, 18047 outputs: []outputInfo{ 18048 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18049 }, 18050 }, 18051 }, 18052 { 18053 name: "FDIV", 18054 argLen: 2, 18055 resultInArg0: true, 18056 asm: s390x.AFDIV, 18057 reg: regInfo{ 18058 inputs: []inputInfo{ 18059 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18060 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18061 }, 18062 outputs: []outputInfo{ 18063 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18064 }, 18065 }, 18066 }, 18067 { 18068 name: "FNEGS", 18069 argLen: 1, 18070 clobberFlags: true, 18071 asm: s390x.AFNEGS, 18072 reg: regInfo{ 18073 inputs: []inputInfo{ 18074 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18075 }, 18076 outputs: []outputInfo{ 18077 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18078 }, 18079 }, 18080 }, 18081 { 18082 name: "FNEG", 18083 argLen: 1, 18084 clobberFlags: true, 18085 asm: s390x.AFNEG, 18086 reg: regInfo{ 18087 inputs: []inputInfo{ 18088 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18089 }, 18090 outputs: []outputInfo{ 18091 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18092 }, 18093 }, 18094 }, 18095 { 18096 name: "FMADDS", 18097 argLen: 3, 18098 resultInArg0: true, 18099 asm: s390x.AFMADDS, 18100 reg: regInfo{ 18101 inputs: []inputInfo{ 18102 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18103 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18104 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18105 }, 18106 outputs: []outputInfo{ 18107 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18108 }, 18109 }, 18110 }, 18111 { 18112 name: "FMADD", 18113 argLen: 3, 18114 resultInArg0: true, 18115 asm: s390x.AFMADD, 18116 reg: regInfo{ 18117 inputs: []inputInfo{ 18118 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18119 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18120 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18121 }, 18122 outputs: []outputInfo{ 18123 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18124 }, 18125 }, 18126 }, 18127 { 18128 name: "FMSUBS", 18129 argLen: 3, 18130 resultInArg0: true, 18131 asm: s390x.AFMSUBS, 18132 reg: regInfo{ 18133 inputs: []inputInfo{ 18134 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18135 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18136 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18137 }, 18138 outputs: []outputInfo{ 18139 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18140 }, 18141 }, 18142 }, 18143 { 18144 name: "FMSUB", 18145 argLen: 3, 18146 resultInArg0: true, 18147 asm: s390x.AFMSUB, 18148 reg: regInfo{ 18149 inputs: []inputInfo{ 18150 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18151 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18152 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18153 }, 18154 outputs: []outputInfo{ 18155 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18156 }, 18157 }, 18158 }, 18159 { 18160 name: "FMOVSload", 18161 auxType: auxSymOff, 18162 argLen: 2, 18163 faultOnNilArg0: true, 18164 symEffect: SymRead, 18165 asm: s390x.AFMOVS, 18166 reg: regInfo{ 18167 inputs: []inputInfo{ 18168 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18169 }, 18170 outputs: []outputInfo{ 18171 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18172 }, 18173 }, 18174 }, 18175 { 18176 name: "FMOVDload", 18177 auxType: auxSymOff, 18178 argLen: 2, 18179 faultOnNilArg0: true, 18180 symEffect: SymRead, 18181 asm: s390x.AFMOVD, 18182 reg: regInfo{ 18183 inputs: []inputInfo{ 18184 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18185 }, 18186 outputs: []outputInfo{ 18187 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18188 }, 18189 }, 18190 }, 18191 { 18192 name: "FMOVSconst", 18193 auxType: auxFloat32, 18194 argLen: 0, 18195 rematerializeable: true, 18196 asm: s390x.AFMOVS, 18197 reg: regInfo{ 18198 outputs: []outputInfo{ 18199 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18200 }, 18201 }, 18202 }, 18203 { 18204 name: "FMOVDconst", 18205 auxType: auxFloat64, 18206 argLen: 0, 18207 rematerializeable: true, 18208 asm: s390x.AFMOVD, 18209 reg: regInfo{ 18210 outputs: []outputInfo{ 18211 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18212 }, 18213 }, 18214 }, 18215 { 18216 name: "FMOVSloadidx", 18217 auxType: auxSymOff, 18218 argLen: 3, 18219 symEffect: SymRead, 18220 asm: s390x.AFMOVS, 18221 reg: regInfo{ 18222 inputs: []inputInfo{ 18223 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18224 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18225 }, 18226 outputs: []outputInfo{ 18227 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18228 }, 18229 }, 18230 }, 18231 { 18232 name: "FMOVDloadidx", 18233 auxType: auxSymOff, 18234 argLen: 3, 18235 symEffect: SymRead, 18236 asm: s390x.AFMOVD, 18237 reg: regInfo{ 18238 inputs: []inputInfo{ 18239 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18240 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18241 }, 18242 outputs: []outputInfo{ 18243 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18244 }, 18245 }, 18246 }, 18247 { 18248 name: "FMOVSstore", 18249 auxType: auxSymOff, 18250 argLen: 3, 18251 faultOnNilArg0: true, 18252 symEffect: SymWrite, 18253 asm: s390x.AFMOVS, 18254 reg: regInfo{ 18255 inputs: []inputInfo{ 18256 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18257 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18258 }, 18259 }, 18260 }, 18261 { 18262 name: "FMOVDstore", 18263 auxType: auxSymOff, 18264 argLen: 3, 18265 faultOnNilArg0: true, 18266 symEffect: SymWrite, 18267 asm: s390x.AFMOVD, 18268 reg: regInfo{ 18269 inputs: []inputInfo{ 18270 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18271 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18272 }, 18273 }, 18274 }, 18275 { 18276 name: "FMOVSstoreidx", 18277 auxType: auxSymOff, 18278 argLen: 4, 18279 symEffect: SymWrite, 18280 asm: s390x.AFMOVS, 18281 reg: regInfo{ 18282 inputs: []inputInfo{ 18283 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18284 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18285 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18286 }, 18287 }, 18288 }, 18289 { 18290 name: "FMOVDstoreidx", 18291 auxType: auxSymOff, 18292 argLen: 4, 18293 symEffect: SymWrite, 18294 asm: s390x.AFMOVD, 18295 reg: regInfo{ 18296 inputs: []inputInfo{ 18297 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18298 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18299 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18300 }, 18301 }, 18302 }, 18303 { 18304 name: "ADD", 18305 argLen: 2, 18306 commutative: true, 18307 clobberFlags: true, 18308 asm: s390x.AADD, 18309 reg: regInfo{ 18310 inputs: []inputInfo{ 18311 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18312 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18313 }, 18314 outputs: []outputInfo{ 18315 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18316 }, 18317 }, 18318 }, 18319 { 18320 name: "ADDW", 18321 argLen: 2, 18322 commutative: true, 18323 clobberFlags: true, 18324 asm: s390x.AADDW, 18325 reg: regInfo{ 18326 inputs: []inputInfo{ 18327 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18328 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18329 }, 18330 outputs: []outputInfo{ 18331 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18332 }, 18333 }, 18334 }, 18335 { 18336 name: "ADDconst", 18337 auxType: auxInt64, 18338 argLen: 1, 18339 clobberFlags: true, 18340 asm: s390x.AADD, 18341 reg: regInfo{ 18342 inputs: []inputInfo{ 18343 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18344 }, 18345 outputs: []outputInfo{ 18346 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18347 }, 18348 }, 18349 }, 18350 { 18351 name: "ADDWconst", 18352 auxType: auxInt32, 18353 argLen: 1, 18354 clobberFlags: true, 18355 asm: s390x.AADDW, 18356 reg: regInfo{ 18357 inputs: []inputInfo{ 18358 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18359 }, 18360 outputs: []outputInfo{ 18361 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18362 }, 18363 }, 18364 }, 18365 { 18366 name: "ADDload", 18367 auxType: auxSymOff, 18368 argLen: 3, 18369 resultInArg0: true, 18370 clobberFlags: true, 18371 faultOnNilArg1: true, 18372 symEffect: SymRead, 18373 asm: s390x.AADD, 18374 reg: regInfo{ 18375 inputs: []inputInfo{ 18376 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18377 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18378 }, 18379 outputs: []outputInfo{ 18380 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18381 }, 18382 }, 18383 }, 18384 { 18385 name: "ADDWload", 18386 auxType: auxSymOff, 18387 argLen: 3, 18388 resultInArg0: true, 18389 clobberFlags: true, 18390 faultOnNilArg1: true, 18391 symEffect: SymRead, 18392 asm: s390x.AADDW, 18393 reg: regInfo{ 18394 inputs: []inputInfo{ 18395 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18396 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18397 }, 18398 outputs: []outputInfo{ 18399 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18400 }, 18401 }, 18402 }, 18403 { 18404 name: "SUB", 18405 argLen: 2, 18406 clobberFlags: true, 18407 asm: s390x.ASUB, 18408 reg: regInfo{ 18409 inputs: []inputInfo{ 18410 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18411 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18412 }, 18413 outputs: []outputInfo{ 18414 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18415 }, 18416 }, 18417 }, 18418 { 18419 name: "SUBW", 18420 argLen: 2, 18421 clobberFlags: true, 18422 asm: s390x.ASUBW, 18423 reg: regInfo{ 18424 inputs: []inputInfo{ 18425 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18426 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18427 }, 18428 outputs: []outputInfo{ 18429 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18430 }, 18431 }, 18432 }, 18433 { 18434 name: "SUBconst", 18435 auxType: auxInt64, 18436 argLen: 1, 18437 resultInArg0: true, 18438 clobberFlags: true, 18439 asm: s390x.ASUB, 18440 reg: regInfo{ 18441 inputs: []inputInfo{ 18442 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18443 }, 18444 outputs: []outputInfo{ 18445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18446 }, 18447 }, 18448 }, 18449 { 18450 name: "SUBWconst", 18451 auxType: auxInt32, 18452 argLen: 1, 18453 resultInArg0: true, 18454 clobberFlags: true, 18455 asm: s390x.ASUBW, 18456 reg: regInfo{ 18457 inputs: []inputInfo{ 18458 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18459 }, 18460 outputs: []outputInfo{ 18461 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18462 }, 18463 }, 18464 }, 18465 { 18466 name: "SUBload", 18467 auxType: auxSymOff, 18468 argLen: 3, 18469 resultInArg0: true, 18470 clobberFlags: true, 18471 faultOnNilArg1: true, 18472 symEffect: SymRead, 18473 asm: s390x.ASUB, 18474 reg: regInfo{ 18475 inputs: []inputInfo{ 18476 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18477 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18478 }, 18479 outputs: []outputInfo{ 18480 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18481 }, 18482 }, 18483 }, 18484 { 18485 name: "SUBWload", 18486 auxType: auxSymOff, 18487 argLen: 3, 18488 resultInArg0: true, 18489 clobberFlags: true, 18490 faultOnNilArg1: true, 18491 symEffect: SymRead, 18492 asm: s390x.ASUBW, 18493 reg: regInfo{ 18494 inputs: []inputInfo{ 18495 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18496 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18497 }, 18498 outputs: []outputInfo{ 18499 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18500 }, 18501 }, 18502 }, 18503 { 18504 name: "MULLD", 18505 argLen: 2, 18506 commutative: true, 18507 resultInArg0: true, 18508 clobberFlags: true, 18509 asm: s390x.AMULLD, 18510 reg: regInfo{ 18511 inputs: []inputInfo{ 18512 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18513 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18514 }, 18515 outputs: []outputInfo{ 18516 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18517 }, 18518 }, 18519 }, 18520 { 18521 name: "MULLW", 18522 argLen: 2, 18523 commutative: true, 18524 resultInArg0: true, 18525 clobberFlags: true, 18526 asm: s390x.AMULLW, 18527 reg: regInfo{ 18528 inputs: []inputInfo{ 18529 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18530 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18531 }, 18532 outputs: []outputInfo{ 18533 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18534 }, 18535 }, 18536 }, 18537 { 18538 name: "MULLDconst", 18539 auxType: auxInt64, 18540 argLen: 1, 18541 resultInArg0: true, 18542 clobberFlags: true, 18543 asm: s390x.AMULLD, 18544 reg: regInfo{ 18545 inputs: []inputInfo{ 18546 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18547 }, 18548 outputs: []outputInfo{ 18549 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18550 }, 18551 }, 18552 }, 18553 { 18554 name: "MULLWconst", 18555 auxType: auxInt32, 18556 argLen: 1, 18557 resultInArg0: true, 18558 clobberFlags: true, 18559 asm: s390x.AMULLW, 18560 reg: regInfo{ 18561 inputs: []inputInfo{ 18562 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18563 }, 18564 outputs: []outputInfo{ 18565 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18566 }, 18567 }, 18568 }, 18569 { 18570 name: "MULLDload", 18571 auxType: auxSymOff, 18572 argLen: 3, 18573 resultInArg0: true, 18574 clobberFlags: true, 18575 faultOnNilArg1: true, 18576 symEffect: SymRead, 18577 asm: s390x.AMULLD, 18578 reg: regInfo{ 18579 inputs: []inputInfo{ 18580 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18581 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18582 }, 18583 outputs: []outputInfo{ 18584 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18585 }, 18586 }, 18587 }, 18588 { 18589 name: "MULLWload", 18590 auxType: auxSymOff, 18591 argLen: 3, 18592 resultInArg0: true, 18593 clobberFlags: true, 18594 faultOnNilArg1: true, 18595 symEffect: SymRead, 18596 asm: s390x.AMULLW, 18597 reg: regInfo{ 18598 inputs: []inputInfo{ 18599 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18600 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18601 }, 18602 outputs: []outputInfo{ 18603 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18604 }, 18605 }, 18606 }, 18607 { 18608 name: "MULHD", 18609 argLen: 2, 18610 commutative: true, 18611 resultInArg0: true, 18612 clobberFlags: true, 18613 asm: s390x.AMULHD, 18614 reg: regInfo{ 18615 inputs: []inputInfo{ 18616 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18617 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18618 }, 18619 outputs: []outputInfo{ 18620 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18621 }, 18622 }, 18623 }, 18624 { 18625 name: "MULHDU", 18626 argLen: 2, 18627 commutative: true, 18628 resultInArg0: true, 18629 clobberFlags: true, 18630 asm: s390x.AMULHDU, 18631 reg: regInfo{ 18632 inputs: []inputInfo{ 18633 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18634 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18635 }, 18636 outputs: []outputInfo{ 18637 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18638 }, 18639 }, 18640 }, 18641 { 18642 name: "DIVD", 18643 argLen: 2, 18644 resultInArg0: true, 18645 clobberFlags: true, 18646 asm: s390x.ADIVD, 18647 reg: regInfo{ 18648 inputs: []inputInfo{ 18649 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18650 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18651 }, 18652 outputs: []outputInfo{ 18653 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18654 }, 18655 }, 18656 }, 18657 { 18658 name: "DIVW", 18659 argLen: 2, 18660 resultInArg0: true, 18661 clobberFlags: true, 18662 asm: s390x.ADIVW, 18663 reg: regInfo{ 18664 inputs: []inputInfo{ 18665 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18666 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18667 }, 18668 outputs: []outputInfo{ 18669 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18670 }, 18671 }, 18672 }, 18673 { 18674 name: "DIVDU", 18675 argLen: 2, 18676 resultInArg0: true, 18677 clobberFlags: true, 18678 asm: s390x.ADIVDU, 18679 reg: regInfo{ 18680 inputs: []inputInfo{ 18681 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18682 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18683 }, 18684 outputs: []outputInfo{ 18685 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18686 }, 18687 }, 18688 }, 18689 { 18690 name: "DIVWU", 18691 argLen: 2, 18692 resultInArg0: true, 18693 clobberFlags: true, 18694 asm: s390x.ADIVWU, 18695 reg: regInfo{ 18696 inputs: []inputInfo{ 18697 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18698 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18699 }, 18700 outputs: []outputInfo{ 18701 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18702 }, 18703 }, 18704 }, 18705 { 18706 name: "MODD", 18707 argLen: 2, 18708 resultInArg0: true, 18709 clobberFlags: true, 18710 asm: s390x.AMODD, 18711 reg: regInfo{ 18712 inputs: []inputInfo{ 18713 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18714 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18715 }, 18716 outputs: []outputInfo{ 18717 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18718 }, 18719 }, 18720 }, 18721 { 18722 name: "MODW", 18723 argLen: 2, 18724 resultInArg0: true, 18725 clobberFlags: true, 18726 asm: s390x.AMODW, 18727 reg: regInfo{ 18728 inputs: []inputInfo{ 18729 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18730 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18731 }, 18732 outputs: []outputInfo{ 18733 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18734 }, 18735 }, 18736 }, 18737 { 18738 name: "MODDU", 18739 argLen: 2, 18740 resultInArg0: true, 18741 clobberFlags: true, 18742 asm: s390x.AMODDU, 18743 reg: regInfo{ 18744 inputs: []inputInfo{ 18745 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18746 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18747 }, 18748 outputs: []outputInfo{ 18749 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18750 }, 18751 }, 18752 }, 18753 { 18754 name: "MODWU", 18755 argLen: 2, 18756 resultInArg0: true, 18757 clobberFlags: true, 18758 asm: s390x.AMODWU, 18759 reg: regInfo{ 18760 inputs: []inputInfo{ 18761 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18762 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18763 }, 18764 outputs: []outputInfo{ 18765 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18766 }, 18767 }, 18768 }, 18769 { 18770 name: "AND", 18771 argLen: 2, 18772 commutative: true, 18773 clobberFlags: true, 18774 asm: s390x.AAND, 18775 reg: regInfo{ 18776 inputs: []inputInfo{ 18777 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18778 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18779 }, 18780 outputs: []outputInfo{ 18781 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18782 }, 18783 }, 18784 }, 18785 { 18786 name: "ANDW", 18787 argLen: 2, 18788 commutative: true, 18789 clobberFlags: true, 18790 asm: s390x.AANDW, 18791 reg: regInfo{ 18792 inputs: []inputInfo{ 18793 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18794 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18795 }, 18796 outputs: []outputInfo{ 18797 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18798 }, 18799 }, 18800 }, 18801 { 18802 name: "ANDconst", 18803 auxType: auxInt64, 18804 argLen: 1, 18805 resultInArg0: true, 18806 clobberFlags: true, 18807 asm: s390x.AAND, 18808 reg: regInfo{ 18809 inputs: []inputInfo{ 18810 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18811 }, 18812 outputs: []outputInfo{ 18813 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18814 }, 18815 }, 18816 }, 18817 { 18818 name: "ANDWconst", 18819 auxType: auxInt32, 18820 argLen: 1, 18821 resultInArg0: true, 18822 clobberFlags: true, 18823 asm: s390x.AANDW, 18824 reg: regInfo{ 18825 inputs: []inputInfo{ 18826 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18827 }, 18828 outputs: []outputInfo{ 18829 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18830 }, 18831 }, 18832 }, 18833 { 18834 name: "ANDload", 18835 auxType: auxSymOff, 18836 argLen: 3, 18837 resultInArg0: true, 18838 clobberFlags: true, 18839 faultOnNilArg1: true, 18840 symEffect: SymRead, 18841 asm: s390x.AAND, 18842 reg: regInfo{ 18843 inputs: []inputInfo{ 18844 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18845 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18846 }, 18847 outputs: []outputInfo{ 18848 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18849 }, 18850 }, 18851 }, 18852 { 18853 name: "ANDWload", 18854 auxType: auxSymOff, 18855 argLen: 3, 18856 resultInArg0: true, 18857 clobberFlags: true, 18858 faultOnNilArg1: true, 18859 symEffect: SymRead, 18860 asm: s390x.AANDW, 18861 reg: regInfo{ 18862 inputs: []inputInfo{ 18863 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18864 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18865 }, 18866 outputs: []outputInfo{ 18867 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18868 }, 18869 }, 18870 }, 18871 { 18872 name: "OR", 18873 argLen: 2, 18874 commutative: true, 18875 clobberFlags: true, 18876 asm: s390x.AOR, 18877 reg: regInfo{ 18878 inputs: []inputInfo{ 18879 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18880 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18881 }, 18882 outputs: []outputInfo{ 18883 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18884 }, 18885 }, 18886 }, 18887 { 18888 name: "ORW", 18889 argLen: 2, 18890 commutative: true, 18891 clobberFlags: true, 18892 asm: s390x.AORW, 18893 reg: regInfo{ 18894 inputs: []inputInfo{ 18895 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18896 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18897 }, 18898 outputs: []outputInfo{ 18899 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18900 }, 18901 }, 18902 }, 18903 { 18904 name: "ORconst", 18905 auxType: auxInt64, 18906 argLen: 1, 18907 resultInArg0: true, 18908 clobberFlags: true, 18909 asm: s390x.AOR, 18910 reg: regInfo{ 18911 inputs: []inputInfo{ 18912 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18913 }, 18914 outputs: []outputInfo{ 18915 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18916 }, 18917 }, 18918 }, 18919 { 18920 name: "ORWconst", 18921 auxType: auxInt32, 18922 argLen: 1, 18923 resultInArg0: true, 18924 clobberFlags: true, 18925 asm: s390x.AORW, 18926 reg: regInfo{ 18927 inputs: []inputInfo{ 18928 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18929 }, 18930 outputs: []outputInfo{ 18931 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18932 }, 18933 }, 18934 }, 18935 { 18936 name: "ORload", 18937 auxType: auxSymOff, 18938 argLen: 3, 18939 resultInArg0: true, 18940 clobberFlags: true, 18941 faultOnNilArg1: true, 18942 symEffect: SymRead, 18943 asm: s390x.AOR, 18944 reg: regInfo{ 18945 inputs: []inputInfo{ 18946 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18947 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18948 }, 18949 outputs: []outputInfo{ 18950 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18951 }, 18952 }, 18953 }, 18954 { 18955 name: "ORWload", 18956 auxType: auxSymOff, 18957 argLen: 3, 18958 resultInArg0: true, 18959 clobberFlags: true, 18960 faultOnNilArg1: true, 18961 symEffect: SymRead, 18962 asm: s390x.AORW, 18963 reg: regInfo{ 18964 inputs: []inputInfo{ 18965 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18966 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18967 }, 18968 outputs: []outputInfo{ 18969 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18970 }, 18971 }, 18972 }, 18973 { 18974 name: "XOR", 18975 argLen: 2, 18976 commutative: true, 18977 clobberFlags: true, 18978 asm: s390x.AXOR, 18979 reg: regInfo{ 18980 inputs: []inputInfo{ 18981 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18982 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18983 }, 18984 outputs: []outputInfo{ 18985 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18986 }, 18987 }, 18988 }, 18989 { 18990 name: "XORW", 18991 argLen: 2, 18992 commutative: true, 18993 clobberFlags: true, 18994 asm: s390x.AXORW, 18995 reg: regInfo{ 18996 inputs: []inputInfo{ 18997 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18998 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18999 }, 19000 outputs: []outputInfo{ 19001 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19002 }, 19003 }, 19004 }, 19005 { 19006 name: "XORconst", 19007 auxType: auxInt64, 19008 argLen: 1, 19009 resultInArg0: true, 19010 clobberFlags: true, 19011 asm: s390x.AXOR, 19012 reg: regInfo{ 19013 inputs: []inputInfo{ 19014 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19015 }, 19016 outputs: []outputInfo{ 19017 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19018 }, 19019 }, 19020 }, 19021 { 19022 name: "XORWconst", 19023 auxType: auxInt32, 19024 argLen: 1, 19025 resultInArg0: true, 19026 clobberFlags: true, 19027 asm: s390x.AXORW, 19028 reg: regInfo{ 19029 inputs: []inputInfo{ 19030 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19031 }, 19032 outputs: []outputInfo{ 19033 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19034 }, 19035 }, 19036 }, 19037 { 19038 name: "XORload", 19039 auxType: auxSymOff, 19040 argLen: 3, 19041 resultInArg0: true, 19042 clobberFlags: true, 19043 faultOnNilArg1: true, 19044 symEffect: SymRead, 19045 asm: s390x.AXOR, 19046 reg: regInfo{ 19047 inputs: []inputInfo{ 19048 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19049 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19050 }, 19051 outputs: []outputInfo{ 19052 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19053 }, 19054 }, 19055 }, 19056 { 19057 name: "XORWload", 19058 auxType: auxSymOff, 19059 argLen: 3, 19060 resultInArg0: true, 19061 clobberFlags: true, 19062 faultOnNilArg1: true, 19063 symEffect: SymRead, 19064 asm: s390x.AXORW, 19065 reg: regInfo{ 19066 inputs: []inputInfo{ 19067 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19068 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19069 }, 19070 outputs: []outputInfo{ 19071 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19072 }, 19073 }, 19074 }, 19075 { 19076 name: "CMP", 19077 argLen: 2, 19078 asm: s390x.ACMP, 19079 reg: regInfo{ 19080 inputs: []inputInfo{ 19081 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19082 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19083 }, 19084 }, 19085 }, 19086 { 19087 name: "CMPW", 19088 argLen: 2, 19089 asm: s390x.ACMPW, 19090 reg: regInfo{ 19091 inputs: []inputInfo{ 19092 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19093 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19094 }, 19095 }, 19096 }, 19097 { 19098 name: "CMPU", 19099 argLen: 2, 19100 asm: s390x.ACMPU, 19101 reg: regInfo{ 19102 inputs: []inputInfo{ 19103 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19104 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19105 }, 19106 }, 19107 }, 19108 { 19109 name: "CMPWU", 19110 argLen: 2, 19111 asm: s390x.ACMPWU, 19112 reg: regInfo{ 19113 inputs: []inputInfo{ 19114 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19115 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19116 }, 19117 }, 19118 }, 19119 { 19120 name: "CMPconst", 19121 auxType: auxInt64, 19122 argLen: 1, 19123 asm: s390x.ACMP, 19124 reg: regInfo{ 19125 inputs: []inputInfo{ 19126 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19127 }, 19128 }, 19129 }, 19130 { 19131 name: "CMPWconst", 19132 auxType: auxInt32, 19133 argLen: 1, 19134 asm: s390x.ACMPW, 19135 reg: regInfo{ 19136 inputs: []inputInfo{ 19137 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19138 }, 19139 }, 19140 }, 19141 { 19142 name: "CMPUconst", 19143 auxType: auxInt64, 19144 argLen: 1, 19145 asm: s390x.ACMPU, 19146 reg: regInfo{ 19147 inputs: []inputInfo{ 19148 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19149 }, 19150 }, 19151 }, 19152 { 19153 name: "CMPWUconst", 19154 auxType: auxInt32, 19155 argLen: 1, 19156 asm: s390x.ACMPWU, 19157 reg: regInfo{ 19158 inputs: []inputInfo{ 19159 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19160 }, 19161 }, 19162 }, 19163 { 19164 name: "FCMPS", 19165 argLen: 2, 19166 asm: s390x.ACEBR, 19167 reg: regInfo{ 19168 inputs: []inputInfo{ 19169 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19170 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19171 }, 19172 }, 19173 }, 19174 { 19175 name: "FCMP", 19176 argLen: 2, 19177 asm: s390x.AFCMPU, 19178 reg: regInfo{ 19179 inputs: []inputInfo{ 19180 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19181 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19182 }, 19183 }, 19184 }, 19185 { 19186 name: "SLD", 19187 argLen: 2, 19188 asm: s390x.ASLD, 19189 reg: regInfo{ 19190 inputs: []inputInfo{ 19191 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19192 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19193 }, 19194 outputs: []outputInfo{ 19195 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19196 }, 19197 }, 19198 }, 19199 { 19200 name: "SLW", 19201 argLen: 2, 19202 asm: s390x.ASLW, 19203 reg: regInfo{ 19204 inputs: []inputInfo{ 19205 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19206 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19207 }, 19208 outputs: []outputInfo{ 19209 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19210 }, 19211 }, 19212 }, 19213 { 19214 name: "SLDconst", 19215 auxType: auxInt8, 19216 argLen: 1, 19217 asm: s390x.ASLD, 19218 reg: regInfo{ 19219 inputs: []inputInfo{ 19220 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19221 }, 19222 outputs: []outputInfo{ 19223 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19224 }, 19225 }, 19226 }, 19227 { 19228 name: "SLWconst", 19229 auxType: auxInt8, 19230 argLen: 1, 19231 asm: s390x.ASLW, 19232 reg: regInfo{ 19233 inputs: []inputInfo{ 19234 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19235 }, 19236 outputs: []outputInfo{ 19237 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19238 }, 19239 }, 19240 }, 19241 { 19242 name: "SRD", 19243 argLen: 2, 19244 asm: s390x.ASRD, 19245 reg: regInfo{ 19246 inputs: []inputInfo{ 19247 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19248 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19249 }, 19250 outputs: []outputInfo{ 19251 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19252 }, 19253 }, 19254 }, 19255 { 19256 name: "SRW", 19257 argLen: 2, 19258 asm: s390x.ASRW, 19259 reg: regInfo{ 19260 inputs: []inputInfo{ 19261 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19262 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19263 }, 19264 outputs: []outputInfo{ 19265 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19266 }, 19267 }, 19268 }, 19269 { 19270 name: "SRDconst", 19271 auxType: auxInt8, 19272 argLen: 1, 19273 asm: s390x.ASRD, 19274 reg: regInfo{ 19275 inputs: []inputInfo{ 19276 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19277 }, 19278 outputs: []outputInfo{ 19279 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19280 }, 19281 }, 19282 }, 19283 { 19284 name: "SRWconst", 19285 auxType: auxInt8, 19286 argLen: 1, 19287 asm: s390x.ASRW, 19288 reg: regInfo{ 19289 inputs: []inputInfo{ 19290 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19291 }, 19292 outputs: []outputInfo{ 19293 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19294 }, 19295 }, 19296 }, 19297 { 19298 name: "SRAD", 19299 argLen: 2, 19300 clobberFlags: true, 19301 asm: s390x.ASRAD, 19302 reg: regInfo{ 19303 inputs: []inputInfo{ 19304 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19305 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19306 }, 19307 outputs: []outputInfo{ 19308 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19309 }, 19310 }, 19311 }, 19312 { 19313 name: "SRAW", 19314 argLen: 2, 19315 clobberFlags: true, 19316 asm: s390x.ASRAW, 19317 reg: regInfo{ 19318 inputs: []inputInfo{ 19319 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19320 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19321 }, 19322 outputs: []outputInfo{ 19323 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19324 }, 19325 }, 19326 }, 19327 { 19328 name: "SRADconst", 19329 auxType: auxInt8, 19330 argLen: 1, 19331 clobberFlags: true, 19332 asm: s390x.ASRAD, 19333 reg: regInfo{ 19334 inputs: []inputInfo{ 19335 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19336 }, 19337 outputs: []outputInfo{ 19338 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19339 }, 19340 }, 19341 }, 19342 { 19343 name: "SRAWconst", 19344 auxType: auxInt8, 19345 argLen: 1, 19346 clobberFlags: true, 19347 asm: s390x.ASRAW, 19348 reg: regInfo{ 19349 inputs: []inputInfo{ 19350 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19351 }, 19352 outputs: []outputInfo{ 19353 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19354 }, 19355 }, 19356 }, 19357 { 19358 name: "RLLGconst", 19359 auxType: auxInt8, 19360 argLen: 1, 19361 asm: s390x.ARLLG, 19362 reg: regInfo{ 19363 inputs: []inputInfo{ 19364 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19365 }, 19366 outputs: []outputInfo{ 19367 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19368 }, 19369 }, 19370 }, 19371 { 19372 name: "RLLconst", 19373 auxType: auxInt8, 19374 argLen: 1, 19375 asm: s390x.ARLL, 19376 reg: regInfo{ 19377 inputs: []inputInfo{ 19378 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19379 }, 19380 outputs: []outputInfo{ 19381 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19382 }, 19383 }, 19384 }, 19385 { 19386 name: "NEG", 19387 argLen: 1, 19388 clobberFlags: true, 19389 asm: s390x.ANEG, 19390 reg: regInfo{ 19391 inputs: []inputInfo{ 19392 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19393 }, 19394 outputs: []outputInfo{ 19395 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19396 }, 19397 }, 19398 }, 19399 { 19400 name: "NEGW", 19401 argLen: 1, 19402 clobberFlags: true, 19403 asm: s390x.ANEGW, 19404 reg: regInfo{ 19405 inputs: []inputInfo{ 19406 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19407 }, 19408 outputs: []outputInfo{ 19409 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19410 }, 19411 }, 19412 }, 19413 { 19414 name: "NOT", 19415 argLen: 1, 19416 resultInArg0: true, 19417 clobberFlags: true, 19418 reg: regInfo{ 19419 inputs: []inputInfo{ 19420 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19421 }, 19422 outputs: []outputInfo{ 19423 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19424 }, 19425 }, 19426 }, 19427 { 19428 name: "NOTW", 19429 argLen: 1, 19430 resultInArg0: true, 19431 clobberFlags: true, 19432 reg: regInfo{ 19433 inputs: []inputInfo{ 19434 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19435 }, 19436 outputs: []outputInfo{ 19437 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19438 }, 19439 }, 19440 }, 19441 { 19442 name: "FSQRT", 19443 argLen: 1, 19444 asm: s390x.AFSQRT, 19445 reg: regInfo{ 19446 inputs: []inputInfo{ 19447 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19448 }, 19449 outputs: []outputInfo{ 19450 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19451 }, 19452 }, 19453 }, 19454 { 19455 name: "SUBEcarrymask", 19456 argLen: 1, 19457 asm: s390x.ASUBE, 19458 reg: regInfo{ 19459 outputs: []outputInfo{ 19460 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19461 }, 19462 }, 19463 }, 19464 { 19465 name: "SUBEWcarrymask", 19466 argLen: 1, 19467 asm: s390x.ASUBE, 19468 reg: regInfo{ 19469 outputs: []outputInfo{ 19470 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19471 }, 19472 }, 19473 }, 19474 { 19475 name: "MOVDEQ", 19476 argLen: 3, 19477 resultInArg0: true, 19478 asm: s390x.AMOVDEQ, 19479 reg: regInfo{ 19480 inputs: []inputInfo{ 19481 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19482 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19483 }, 19484 outputs: []outputInfo{ 19485 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19486 }, 19487 }, 19488 }, 19489 { 19490 name: "MOVDNE", 19491 argLen: 3, 19492 resultInArg0: true, 19493 asm: s390x.AMOVDNE, 19494 reg: regInfo{ 19495 inputs: []inputInfo{ 19496 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19497 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19498 }, 19499 outputs: []outputInfo{ 19500 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19501 }, 19502 }, 19503 }, 19504 { 19505 name: "MOVDLT", 19506 argLen: 3, 19507 resultInArg0: true, 19508 asm: s390x.AMOVDLT, 19509 reg: regInfo{ 19510 inputs: []inputInfo{ 19511 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19512 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19513 }, 19514 outputs: []outputInfo{ 19515 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19516 }, 19517 }, 19518 }, 19519 { 19520 name: "MOVDLE", 19521 argLen: 3, 19522 resultInArg0: true, 19523 asm: s390x.AMOVDLE, 19524 reg: regInfo{ 19525 inputs: []inputInfo{ 19526 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19527 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19528 }, 19529 outputs: []outputInfo{ 19530 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19531 }, 19532 }, 19533 }, 19534 { 19535 name: "MOVDGT", 19536 argLen: 3, 19537 resultInArg0: true, 19538 asm: s390x.AMOVDGT, 19539 reg: regInfo{ 19540 inputs: []inputInfo{ 19541 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19542 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19543 }, 19544 outputs: []outputInfo{ 19545 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19546 }, 19547 }, 19548 }, 19549 { 19550 name: "MOVDGE", 19551 argLen: 3, 19552 resultInArg0: true, 19553 asm: s390x.AMOVDGE, 19554 reg: regInfo{ 19555 inputs: []inputInfo{ 19556 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19557 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19558 }, 19559 outputs: []outputInfo{ 19560 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19561 }, 19562 }, 19563 }, 19564 { 19565 name: "MOVDGTnoinv", 19566 argLen: 3, 19567 resultInArg0: true, 19568 asm: s390x.AMOVDGT, 19569 reg: regInfo{ 19570 inputs: []inputInfo{ 19571 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19572 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19573 }, 19574 outputs: []outputInfo{ 19575 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19576 }, 19577 }, 19578 }, 19579 { 19580 name: "MOVDGEnoinv", 19581 argLen: 3, 19582 resultInArg0: true, 19583 asm: s390x.AMOVDGE, 19584 reg: regInfo{ 19585 inputs: []inputInfo{ 19586 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19587 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19588 }, 19589 outputs: []outputInfo{ 19590 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19591 }, 19592 }, 19593 }, 19594 { 19595 name: "MOVBreg", 19596 argLen: 1, 19597 asm: s390x.AMOVB, 19598 reg: regInfo{ 19599 inputs: []inputInfo{ 19600 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19601 }, 19602 outputs: []outputInfo{ 19603 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19604 }, 19605 }, 19606 }, 19607 { 19608 name: "MOVBZreg", 19609 argLen: 1, 19610 asm: s390x.AMOVBZ, 19611 reg: regInfo{ 19612 inputs: []inputInfo{ 19613 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19614 }, 19615 outputs: []outputInfo{ 19616 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19617 }, 19618 }, 19619 }, 19620 { 19621 name: "MOVHreg", 19622 argLen: 1, 19623 asm: s390x.AMOVH, 19624 reg: regInfo{ 19625 inputs: []inputInfo{ 19626 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19627 }, 19628 outputs: []outputInfo{ 19629 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19630 }, 19631 }, 19632 }, 19633 { 19634 name: "MOVHZreg", 19635 argLen: 1, 19636 asm: s390x.AMOVHZ, 19637 reg: regInfo{ 19638 inputs: []inputInfo{ 19639 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19640 }, 19641 outputs: []outputInfo{ 19642 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19643 }, 19644 }, 19645 }, 19646 { 19647 name: "MOVWreg", 19648 argLen: 1, 19649 asm: s390x.AMOVW, 19650 reg: regInfo{ 19651 inputs: []inputInfo{ 19652 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19653 }, 19654 outputs: []outputInfo{ 19655 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19656 }, 19657 }, 19658 }, 19659 { 19660 name: "MOVWZreg", 19661 argLen: 1, 19662 asm: s390x.AMOVWZ, 19663 reg: regInfo{ 19664 inputs: []inputInfo{ 19665 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19666 }, 19667 outputs: []outputInfo{ 19668 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19669 }, 19670 }, 19671 }, 19672 { 19673 name: "MOVDreg", 19674 argLen: 1, 19675 asm: s390x.AMOVD, 19676 reg: regInfo{ 19677 inputs: []inputInfo{ 19678 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19679 }, 19680 outputs: []outputInfo{ 19681 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19682 }, 19683 }, 19684 }, 19685 { 19686 name: "MOVDnop", 19687 argLen: 1, 19688 resultInArg0: true, 19689 reg: regInfo{ 19690 inputs: []inputInfo{ 19691 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19692 }, 19693 outputs: []outputInfo{ 19694 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19695 }, 19696 }, 19697 }, 19698 { 19699 name: "MOVDconst", 19700 auxType: auxInt64, 19701 argLen: 0, 19702 rematerializeable: true, 19703 asm: s390x.AMOVD, 19704 reg: regInfo{ 19705 outputs: []outputInfo{ 19706 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19707 }, 19708 }, 19709 }, 19710 { 19711 name: "CFDBRA", 19712 argLen: 1, 19713 asm: s390x.ACFDBRA, 19714 reg: regInfo{ 19715 inputs: []inputInfo{ 19716 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19717 }, 19718 outputs: []outputInfo{ 19719 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19720 }, 19721 }, 19722 }, 19723 { 19724 name: "CGDBRA", 19725 argLen: 1, 19726 asm: s390x.ACGDBRA, 19727 reg: regInfo{ 19728 inputs: []inputInfo{ 19729 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19730 }, 19731 outputs: []outputInfo{ 19732 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19733 }, 19734 }, 19735 }, 19736 { 19737 name: "CFEBRA", 19738 argLen: 1, 19739 asm: s390x.ACFEBRA, 19740 reg: regInfo{ 19741 inputs: []inputInfo{ 19742 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19743 }, 19744 outputs: []outputInfo{ 19745 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19746 }, 19747 }, 19748 }, 19749 { 19750 name: "CGEBRA", 19751 argLen: 1, 19752 asm: s390x.ACGEBRA, 19753 reg: regInfo{ 19754 inputs: []inputInfo{ 19755 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19756 }, 19757 outputs: []outputInfo{ 19758 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19759 }, 19760 }, 19761 }, 19762 { 19763 name: "CEFBRA", 19764 argLen: 1, 19765 asm: s390x.ACEFBRA, 19766 reg: regInfo{ 19767 inputs: []inputInfo{ 19768 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19769 }, 19770 outputs: []outputInfo{ 19771 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19772 }, 19773 }, 19774 }, 19775 { 19776 name: "CDFBRA", 19777 argLen: 1, 19778 asm: s390x.ACDFBRA, 19779 reg: regInfo{ 19780 inputs: []inputInfo{ 19781 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19782 }, 19783 outputs: []outputInfo{ 19784 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19785 }, 19786 }, 19787 }, 19788 { 19789 name: "CEGBRA", 19790 argLen: 1, 19791 asm: s390x.ACEGBRA, 19792 reg: regInfo{ 19793 inputs: []inputInfo{ 19794 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19795 }, 19796 outputs: []outputInfo{ 19797 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19798 }, 19799 }, 19800 }, 19801 { 19802 name: "CDGBRA", 19803 argLen: 1, 19804 asm: s390x.ACDGBRA, 19805 reg: regInfo{ 19806 inputs: []inputInfo{ 19807 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19808 }, 19809 outputs: []outputInfo{ 19810 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19811 }, 19812 }, 19813 }, 19814 { 19815 name: "LEDBR", 19816 argLen: 1, 19817 asm: s390x.ALEDBR, 19818 reg: regInfo{ 19819 inputs: []inputInfo{ 19820 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19821 }, 19822 outputs: []outputInfo{ 19823 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19824 }, 19825 }, 19826 }, 19827 { 19828 name: "LDEBR", 19829 argLen: 1, 19830 asm: s390x.ALDEBR, 19831 reg: regInfo{ 19832 inputs: []inputInfo{ 19833 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19834 }, 19835 outputs: []outputInfo{ 19836 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19837 }, 19838 }, 19839 }, 19840 { 19841 name: "MOVDaddr", 19842 auxType: auxSymOff, 19843 argLen: 1, 19844 rematerializeable: true, 19845 clobberFlags: true, 19846 symEffect: SymRead, 19847 reg: regInfo{ 19848 inputs: []inputInfo{ 19849 {0, 4295000064}, // SP SB 19850 }, 19851 outputs: []outputInfo{ 19852 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19853 }, 19854 }, 19855 }, 19856 { 19857 name: "MOVDaddridx", 19858 auxType: auxSymOff, 19859 argLen: 2, 19860 clobberFlags: true, 19861 symEffect: SymRead, 19862 reg: regInfo{ 19863 inputs: []inputInfo{ 19864 {0, 4295000064}, // SP SB 19865 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19866 }, 19867 outputs: []outputInfo{ 19868 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19869 }, 19870 }, 19871 }, 19872 { 19873 name: "MOVBZload", 19874 auxType: auxSymOff, 19875 argLen: 2, 19876 clobberFlags: true, 19877 faultOnNilArg0: true, 19878 symEffect: SymRead, 19879 asm: s390x.AMOVBZ, 19880 reg: regInfo{ 19881 inputs: []inputInfo{ 19882 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19883 }, 19884 outputs: []outputInfo{ 19885 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19886 }, 19887 }, 19888 }, 19889 { 19890 name: "MOVBload", 19891 auxType: auxSymOff, 19892 argLen: 2, 19893 clobberFlags: true, 19894 faultOnNilArg0: true, 19895 symEffect: SymRead, 19896 asm: s390x.AMOVB, 19897 reg: regInfo{ 19898 inputs: []inputInfo{ 19899 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19900 }, 19901 outputs: []outputInfo{ 19902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19903 }, 19904 }, 19905 }, 19906 { 19907 name: "MOVHZload", 19908 auxType: auxSymOff, 19909 argLen: 2, 19910 clobberFlags: true, 19911 faultOnNilArg0: true, 19912 symEffect: SymRead, 19913 asm: s390x.AMOVHZ, 19914 reg: regInfo{ 19915 inputs: []inputInfo{ 19916 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19917 }, 19918 outputs: []outputInfo{ 19919 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19920 }, 19921 }, 19922 }, 19923 { 19924 name: "MOVHload", 19925 auxType: auxSymOff, 19926 argLen: 2, 19927 clobberFlags: true, 19928 faultOnNilArg0: true, 19929 symEffect: SymRead, 19930 asm: s390x.AMOVH, 19931 reg: regInfo{ 19932 inputs: []inputInfo{ 19933 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19934 }, 19935 outputs: []outputInfo{ 19936 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19937 }, 19938 }, 19939 }, 19940 { 19941 name: "MOVWZload", 19942 auxType: auxSymOff, 19943 argLen: 2, 19944 clobberFlags: true, 19945 faultOnNilArg0: true, 19946 symEffect: SymRead, 19947 asm: s390x.AMOVWZ, 19948 reg: regInfo{ 19949 inputs: []inputInfo{ 19950 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19951 }, 19952 outputs: []outputInfo{ 19953 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19954 }, 19955 }, 19956 }, 19957 { 19958 name: "MOVWload", 19959 auxType: auxSymOff, 19960 argLen: 2, 19961 clobberFlags: true, 19962 faultOnNilArg0: true, 19963 symEffect: SymRead, 19964 asm: s390x.AMOVW, 19965 reg: regInfo{ 19966 inputs: []inputInfo{ 19967 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19968 }, 19969 outputs: []outputInfo{ 19970 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19971 }, 19972 }, 19973 }, 19974 { 19975 name: "MOVDload", 19976 auxType: auxSymOff, 19977 argLen: 2, 19978 clobberFlags: true, 19979 faultOnNilArg0: true, 19980 symEffect: SymRead, 19981 asm: s390x.AMOVD, 19982 reg: regInfo{ 19983 inputs: []inputInfo{ 19984 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19985 }, 19986 outputs: []outputInfo{ 19987 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19988 }, 19989 }, 19990 }, 19991 { 19992 name: "MOVWBR", 19993 argLen: 1, 19994 asm: s390x.AMOVWBR, 19995 reg: regInfo{ 19996 inputs: []inputInfo{ 19997 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19998 }, 19999 outputs: []outputInfo{ 20000 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20001 }, 20002 }, 20003 }, 20004 { 20005 name: "MOVDBR", 20006 argLen: 1, 20007 asm: s390x.AMOVDBR, 20008 reg: regInfo{ 20009 inputs: []inputInfo{ 20010 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20011 }, 20012 outputs: []outputInfo{ 20013 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20014 }, 20015 }, 20016 }, 20017 { 20018 name: "MOVHBRload", 20019 auxType: auxSymOff, 20020 argLen: 2, 20021 clobberFlags: true, 20022 faultOnNilArg0: true, 20023 symEffect: SymRead, 20024 asm: s390x.AMOVHBR, 20025 reg: regInfo{ 20026 inputs: []inputInfo{ 20027 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20028 }, 20029 outputs: []outputInfo{ 20030 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20031 }, 20032 }, 20033 }, 20034 { 20035 name: "MOVWBRload", 20036 auxType: auxSymOff, 20037 argLen: 2, 20038 clobberFlags: true, 20039 faultOnNilArg0: true, 20040 symEffect: SymRead, 20041 asm: s390x.AMOVWBR, 20042 reg: regInfo{ 20043 inputs: []inputInfo{ 20044 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20045 }, 20046 outputs: []outputInfo{ 20047 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20048 }, 20049 }, 20050 }, 20051 { 20052 name: "MOVDBRload", 20053 auxType: auxSymOff, 20054 argLen: 2, 20055 clobberFlags: true, 20056 faultOnNilArg0: true, 20057 symEffect: SymRead, 20058 asm: s390x.AMOVDBR, 20059 reg: regInfo{ 20060 inputs: []inputInfo{ 20061 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20062 }, 20063 outputs: []outputInfo{ 20064 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20065 }, 20066 }, 20067 }, 20068 { 20069 name: "MOVBstore", 20070 auxType: auxSymOff, 20071 argLen: 3, 20072 clobberFlags: true, 20073 faultOnNilArg0: true, 20074 symEffect: SymWrite, 20075 asm: s390x.AMOVB, 20076 reg: regInfo{ 20077 inputs: []inputInfo{ 20078 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20079 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20080 }, 20081 }, 20082 }, 20083 { 20084 name: "MOVHstore", 20085 auxType: auxSymOff, 20086 argLen: 3, 20087 clobberFlags: true, 20088 faultOnNilArg0: true, 20089 symEffect: SymWrite, 20090 asm: s390x.AMOVH, 20091 reg: regInfo{ 20092 inputs: []inputInfo{ 20093 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20094 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20095 }, 20096 }, 20097 }, 20098 { 20099 name: "MOVWstore", 20100 auxType: auxSymOff, 20101 argLen: 3, 20102 clobberFlags: true, 20103 faultOnNilArg0: true, 20104 symEffect: SymWrite, 20105 asm: s390x.AMOVW, 20106 reg: regInfo{ 20107 inputs: []inputInfo{ 20108 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20109 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20110 }, 20111 }, 20112 }, 20113 { 20114 name: "MOVDstore", 20115 auxType: auxSymOff, 20116 argLen: 3, 20117 clobberFlags: true, 20118 faultOnNilArg0: true, 20119 symEffect: SymWrite, 20120 asm: s390x.AMOVD, 20121 reg: regInfo{ 20122 inputs: []inputInfo{ 20123 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20124 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20125 }, 20126 }, 20127 }, 20128 { 20129 name: "MOVHBRstore", 20130 auxType: auxSymOff, 20131 argLen: 3, 20132 clobberFlags: true, 20133 faultOnNilArg0: true, 20134 symEffect: SymWrite, 20135 asm: s390x.AMOVHBR, 20136 reg: regInfo{ 20137 inputs: []inputInfo{ 20138 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20139 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20140 }, 20141 }, 20142 }, 20143 { 20144 name: "MOVWBRstore", 20145 auxType: auxSymOff, 20146 argLen: 3, 20147 clobberFlags: true, 20148 faultOnNilArg0: true, 20149 symEffect: SymWrite, 20150 asm: s390x.AMOVWBR, 20151 reg: regInfo{ 20152 inputs: []inputInfo{ 20153 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20154 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20155 }, 20156 }, 20157 }, 20158 { 20159 name: "MOVDBRstore", 20160 auxType: auxSymOff, 20161 argLen: 3, 20162 clobberFlags: true, 20163 faultOnNilArg0: true, 20164 symEffect: SymWrite, 20165 asm: s390x.AMOVDBR, 20166 reg: regInfo{ 20167 inputs: []inputInfo{ 20168 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20169 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20170 }, 20171 }, 20172 }, 20173 { 20174 name: "MVC", 20175 auxType: auxSymValAndOff, 20176 argLen: 3, 20177 clobberFlags: true, 20178 faultOnNilArg0: true, 20179 faultOnNilArg1: true, 20180 symEffect: SymNone, 20181 asm: s390x.AMVC, 20182 reg: regInfo{ 20183 inputs: []inputInfo{ 20184 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20185 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20186 }, 20187 }, 20188 }, 20189 { 20190 name: "MOVBZloadidx", 20191 auxType: auxSymOff, 20192 argLen: 3, 20193 commutative: true, 20194 clobberFlags: true, 20195 symEffect: SymRead, 20196 asm: s390x.AMOVBZ, 20197 reg: regInfo{ 20198 inputs: []inputInfo{ 20199 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20200 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20201 }, 20202 outputs: []outputInfo{ 20203 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20204 }, 20205 }, 20206 }, 20207 { 20208 name: "MOVHZloadidx", 20209 auxType: auxSymOff, 20210 argLen: 3, 20211 commutative: true, 20212 clobberFlags: true, 20213 symEffect: SymRead, 20214 asm: s390x.AMOVHZ, 20215 reg: regInfo{ 20216 inputs: []inputInfo{ 20217 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20218 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20219 }, 20220 outputs: []outputInfo{ 20221 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20222 }, 20223 }, 20224 }, 20225 { 20226 name: "MOVWZloadidx", 20227 auxType: auxSymOff, 20228 argLen: 3, 20229 commutative: true, 20230 clobberFlags: true, 20231 symEffect: SymRead, 20232 asm: s390x.AMOVWZ, 20233 reg: regInfo{ 20234 inputs: []inputInfo{ 20235 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20236 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20237 }, 20238 outputs: []outputInfo{ 20239 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20240 }, 20241 }, 20242 }, 20243 { 20244 name: "MOVDloadidx", 20245 auxType: auxSymOff, 20246 argLen: 3, 20247 commutative: true, 20248 clobberFlags: true, 20249 symEffect: SymRead, 20250 asm: s390x.AMOVD, 20251 reg: regInfo{ 20252 inputs: []inputInfo{ 20253 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20254 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20255 }, 20256 outputs: []outputInfo{ 20257 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20258 }, 20259 }, 20260 }, 20261 { 20262 name: "MOVHBRloadidx", 20263 auxType: auxSymOff, 20264 argLen: 3, 20265 commutative: true, 20266 clobberFlags: true, 20267 symEffect: SymRead, 20268 asm: s390x.AMOVHBR, 20269 reg: regInfo{ 20270 inputs: []inputInfo{ 20271 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20272 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20273 }, 20274 outputs: []outputInfo{ 20275 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20276 }, 20277 }, 20278 }, 20279 { 20280 name: "MOVWBRloadidx", 20281 auxType: auxSymOff, 20282 argLen: 3, 20283 commutative: true, 20284 clobberFlags: true, 20285 symEffect: SymRead, 20286 asm: s390x.AMOVWBR, 20287 reg: regInfo{ 20288 inputs: []inputInfo{ 20289 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20290 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20291 }, 20292 outputs: []outputInfo{ 20293 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20294 }, 20295 }, 20296 }, 20297 { 20298 name: "MOVDBRloadidx", 20299 auxType: auxSymOff, 20300 argLen: 3, 20301 commutative: true, 20302 clobberFlags: true, 20303 symEffect: SymRead, 20304 asm: s390x.AMOVDBR, 20305 reg: regInfo{ 20306 inputs: []inputInfo{ 20307 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20308 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20309 }, 20310 outputs: []outputInfo{ 20311 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20312 }, 20313 }, 20314 }, 20315 { 20316 name: "MOVBstoreidx", 20317 auxType: auxSymOff, 20318 argLen: 4, 20319 commutative: true, 20320 clobberFlags: true, 20321 symEffect: SymWrite, 20322 asm: s390x.AMOVB, 20323 reg: regInfo{ 20324 inputs: []inputInfo{ 20325 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20326 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20327 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20328 }, 20329 }, 20330 }, 20331 { 20332 name: "MOVHstoreidx", 20333 auxType: auxSymOff, 20334 argLen: 4, 20335 commutative: true, 20336 clobberFlags: true, 20337 symEffect: SymWrite, 20338 asm: s390x.AMOVH, 20339 reg: regInfo{ 20340 inputs: []inputInfo{ 20341 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20342 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20343 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20344 }, 20345 }, 20346 }, 20347 { 20348 name: "MOVWstoreidx", 20349 auxType: auxSymOff, 20350 argLen: 4, 20351 commutative: true, 20352 clobberFlags: true, 20353 symEffect: SymWrite, 20354 asm: s390x.AMOVW, 20355 reg: regInfo{ 20356 inputs: []inputInfo{ 20357 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20358 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20359 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20360 }, 20361 }, 20362 }, 20363 { 20364 name: "MOVDstoreidx", 20365 auxType: auxSymOff, 20366 argLen: 4, 20367 commutative: true, 20368 clobberFlags: true, 20369 symEffect: SymWrite, 20370 asm: s390x.AMOVD, 20371 reg: regInfo{ 20372 inputs: []inputInfo{ 20373 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20374 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20375 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20376 }, 20377 }, 20378 }, 20379 { 20380 name: "MOVHBRstoreidx", 20381 auxType: auxSymOff, 20382 argLen: 4, 20383 commutative: true, 20384 clobberFlags: true, 20385 symEffect: SymWrite, 20386 asm: s390x.AMOVHBR, 20387 reg: regInfo{ 20388 inputs: []inputInfo{ 20389 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20390 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20391 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20392 }, 20393 }, 20394 }, 20395 { 20396 name: "MOVWBRstoreidx", 20397 auxType: auxSymOff, 20398 argLen: 4, 20399 commutative: true, 20400 clobberFlags: true, 20401 symEffect: SymWrite, 20402 asm: s390x.AMOVWBR, 20403 reg: regInfo{ 20404 inputs: []inputInfo{ 20405 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20406 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20407 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20408 }, 20409 }, 20410 }, 20411 { 20412 name: "MOVDBRstoreidx", 20413 auxType: auxSymOff, 20414 argLen: 4, 20415 commutative: true, 20416 clobberFlags: true, 20417 symEffect: SymWrite, 20418 asm: s390x.AMOVDBR, 20419 reg: regInfo{ 20420 inputs: []inputInfo{ 20421 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20422 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20423 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20424 }, 20425 }, 20426 }, 20427 { 20428 name: "MOVBstoreconst", 20429 auxType: auxSymValAndOff, 20430 argLen: 2, 20431 faultOnNilArg0: true, 20432 symEffect: SymWrite, 20433 asm: s390x.AMOVB, 20434 reg: regInfo{ 20435 inputs: []inputInfo{ 20436 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20437 }, 20438 }, 20439 }, 20440 { 20441 name: "MOVHstoreconst", 20442 auxType: auxSymValAndOff, 20443 argLen: 2, 20444 faultOnNilArg0: true, 20445 symEffect: SymWrite, 20446 asm: s390x.AMOVH, 20447 reg: regInfo{ 20448 inputs: []inputInfo{ 20449 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20450 }, 20451 }, 20452 }, 20453 { 20454 name: "MOVWstoreconst", 20455 auxType: auxSymValAndOff, 20456 argLen: 2, 20457 faultOnNilArg0: true, 20458 symEffect: SymWrite, 20459 asm: s390x.AMOVW, 20460 reg: regInfo{ 20461 inputs: []inputInfo{ 20462 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20463 }, 20464 }, 20465 }, 20466 { 20467 name: "MOVDstoreconst", 20468 auxType: auxSymValAndOff, 20469 argLen: 2, 20470 faultOnNilArg0: true, 20471 symEffect: SymWrite, 20472 asm: s390x.AMOVD, 20473 reg: regInfo{ 20474 inputs: []inputInfo{ 20475 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20476 }, 20477 }, 20478 }, 20479 { 20480 name: "CLEAR", 20481 auxType: auxSymValAndOff, 20482 argLen: 2, 20483 clobberFlags: true, 20484 faultOnNilArg0: true, 20485 symEffect: SymWrite, 20486 asm: s390x.ACLEAR, 20487 reg: regInfo{ 20488 inputs: []inputInfo{ 20489 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20490 }, 20491 }, 20492 }, 20493 { 20494 name: "CALLstatic", 20495 auxType: auxSymOff, 20496 argLen: 1, 20497 clobberFlags: true, 20498 call: true, 20499 symEffect: SymNone, 20500 reg: regInfo{ 20501 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20502 }, 20503 }, 20504 { 20505 name: "CALLclosure", 20506 auxType: auxInt64, 20507 argLen: 3, 20508 clobberFlags: true, 20509 call: true, 20510 reg: regInfo{ 20511 inputs: []inputInfo{ 20512 {1, 4096}, // R12 20513 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20514 }, 20515 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20516 }, 20517 }, 20518 { 20519 name: "CALLinter", 20520 auxType: auxInt64, 20521 argLen: 2, 20522 clobberFlags: true, 20523 call: true, 20524 reg: regInfo{ 20525 inputs: []inputInfo{ 20526 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20527 }, 20528 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20529 }, 20530 }, 20531 { 20532 name: "InvertFlags", 20533 argLen: 1, 20534 reg: regInfo{}, 20535 }, 20536 { 20537 name: "LoweredGetG", 20538 argLen: 1, 20539 reg: regInfo{ 20540 outputs: []outputInfo{ 20541 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20542 }, 20543 }, 20544 }, 20545 { 20546 name: "LoweredGetClosurePtr", 20547 argLen: 0, 20548 reg: regInfo{ 20549 outputs: []outputInfo{ 20550 {0, 4096}, // R12 20551 }, 20552 }, 20553 }, 20554 { 20555 name: "LoweredNilCheck", 20556 argLen: 2, 20557 clobberFlags: true, 20558 nilCheck: true, 20559 faultOnNilArg0: true, 20560 reg: regInfo{ 20561 inputs: []inputInfo{ 20562 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20563 }, 20564 }, 20565 }, 20566 { 20567 name: "LoweredRound32F", 20568 argLen: 1, 20569 resultInArg0: true, 20570 reg: regInfo{ 20571 inputs: []inputInfo{ 20572 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20573 }, 20574 outputs: []outputInfo{ 20575 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20576 }, 20577 }, 20578 }, 20579 { 20580 name: "LoweredRound64F", 20581 argLen: 1, 20582 resultInArg0: true, 20583 reg: regInfo{ 20584 inputs: []inputInfo{ 20585 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20586 }, 20587 outputs: []outputInfo{ 20588 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20589 }, 20590 }, 20591 }, 20592 { 20593 name: "MOVDconvert", 20594 argLen: 2, 20595 asm: s390x.AMOVD, 20596 reg: regInfo{ 20597 inputs: []inputInfo{ 20598 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20599 }, 20600 outputs: []outputInfo{ 20601 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20602 }, 20603 }, 20604 }, 20605 { 20606 name: "FlagEQ", 20607 argLen: 0, 20608 reg: regInfo{}, 20609 }, 20610 { 20611 name: "FlagLT", 20612 argLen: 0, 20613 reg: regInfo{}, 20614 }, 20615 { 20616 name: "FlagGT", 20617 argLen: 0, 20618 reg: regInfo{}, 20619 }, 20620 { 20621 name: "MOVWZatomicload", 20622 auxType: auxSymOff, 20623 argLen: 2, 20624 faultOnNilArg0: true, 20625 symEffect: SymRead, 20626 asm: s390x.AMOVWZ, 20627 reg: regInfo{ 20628 inputs: []inputInfo{ 20629 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20630 }, 20631 outputs: []outputInfo{ 20632 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20633 }, 20634 }, 20635 }, 20636 { 20637 name: "MOVDatomicload", 20638 auxType: auxSymOff, 20639 argLen: 2, 20640 faultOnNilArg0: true, 20641 symEffect: SymRead, 20642 asm: s390x.AMOVD, 20643 reg: regInfo{ 20644 inputs: []inputInfo{ 20645 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20646 }, 20647 outputs: []outputInfo{ 20648 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20649 }, 20650 }, 20651 }, 20652 { 20653 name: "MOVWatomicstore", 20654 auxType: auxSymOff, 20655 argLen: 3, 20656 clobberFlags: true, 20657 faultOnNilArg0: true, 20658 hasSideEffects: true, 20659 symEffect: SymWrite, 20660 asm: s390x.AMOVW, 20661 reg: regInfo{ 20662 inputs: []inputInfo{ 20663 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20664 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20665 }, 20666 }, 20667 }, 20668 { 20669 name: "MOVDatomicstore", 20670 auxType: auxSymOff, 20671 argLen: 3, 20672 clobberFlags: true, 20673 faultOnNilArg0: true, 20674 hasSideEffects: true, 20675 symEffect: SymWrite, 20676 asm: s390x.AMOVD, 20677 reg: regInfo{ 20678 inputs: []inputInfo{ 20679 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20680 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20681 }, 20682 }, 20683 }, 20684 { 20685 name: "LAA", 20686 auxType: auxSymOff, 20687 argLen: 3, 20688 faultOnNilArg0: true, 20689 hasSideEffects: true, 20690 symEffect: SymRdWr, 20691 asm: s390x.ALAA, 20692 reg: regInfo{ 20693 inputs: []inputInfo{ 20694 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20695 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20696 }, 20697 outputs: []outputInfo{ 20698 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20699 }, 20700 }, 20701 }, 20702 { 20703 name: "LAAG", 20704 auxType: auxSymOff, 20705 argLen: 3, 20706 faultOnNilArg0: true, 20707 hasSideEffects: true, 20708 symEffect: SymRdWr, 20709 asm: s390x.ALAAG, 20710 reg: regInfo{ 20711 inputs: []inputInfo{ 20712 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20713 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20714 }, 20715 outputs: []outputInfo{ 20716 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20717 }, 20718 }, 20719 }, 20720 { 20721 name: "AddTupleFirst32", 20722 argLen: 2, 20723 reg: regInfo{}, 20724 }, 20725 { 20726 name: "AddTupleFirst64", 20727 argLen: 2, 20728 reg: regInfo{}, 20729 }, 20730 { 20731 name: "LoweredAtomicCas32", 20732 auxType: auxSymOff, 20733 argLen: 4, 20734 clobberFlags: true, 20735 faultOnNilArg0: true, 20736 hasSideEffects: true, 20737 symEffect: SymRdWr, 20738 asm: s390x.ACS, 20739 reg: regInfo{ 20740 inputs: []inputInfo{ 20741 {1, 1}, // R0 20742 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20743 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20744 }, 20745 clobbers: 1, // R0 20746 outputs: []outputInfo{ 20747 {1, 0}, 20748 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20749 }, 20750 }, 20751 }, 20752 { 20753 name: "LoweredAtomicCas64", 20754 auxType: auxSymOff, 20755 argLen: 4, 20756 clobberFlags: true, 20757 faultOnNilArg0: true, 20758 hasSideEffects: true, 20759 symEffect: SymRdWr, 20760 asm: s390x.ACSG, 20761 reg: regInfo{ 20762 inputs: []inputInfo{ 20763 {1, 1}, // R0 20764 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20765 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20766 }, 20767 clobbers: 1, // R0 20768 outputs: []outputInfo{ 20769 {1, 0}, 20770 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20771 }, 20772 }, 20773 }, 20774 { 20775 name: "LoweredAtomicExchange32", 20776 auxType: auxSymOff, 20777 argLen: 3, 20778 clobberFlags: true, 20779 faultOnNilArg0: true, 20780 hasSideEffects: true, 20781 symEffect: SymRdWr, 20782 asm: s390x.ACS, 20783 reg: regInfo{ 20784 inputs: []inputInfo{ 20785 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20786 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20787 }, 20788 outputs: []outputInfo{ 20789 {1, 0}, 20790 {0, 1}, // R0 20791 }, 20792 }, 20793 }, 20794 { 20795 name: "LoweredAtomicExchange64", 20796 auxType: auxSymOff, 20797 argLen: 3, 20798 clobberFlags: true, 20799 faultOnNilArg0: true, 20800 hasSideEffects: true, 20801 symEffect: SymRdWr, 20802 asm: s390x.ACSG, 20803 reg: regInfo{ 20804 inputs: []inputInfo{ 20805 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20806 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20807 }, 20808 outputs: []outputInfo{ 20809 {1, 0}, 20810 {0, 1}, // R0 20811 }, 20812 }, 20813 }, 20814 { 20815 name: "FLOGR", 20816 argLen: 1, 20817 clobberFlags: true, 20818 asm: s390x.AFLOGR, 20819 reg: regInfo{ 20820 inputs: []inputInfo{ 20821 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20822 }, 20823 clobbers: 2, // R1 20824 outputs: []outputInfo{ 20825 {0, 1}, // R0 20826 }, 20827 }, 20828 }, 20829 { 20830 name: "STMG2", 20831 auxType: auxSymOff, 20832 argLen: 4, 20833 faultOnNilArg0: true, 20834 symEffect: SymWrite, 20835 asm: s390x.ASTMG, 20836 reg: regInfo{ 20837 inputs: []inputInfo{ 20838 {1, 2}, // R1 20839 {2, 4}, // R2 20840 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20841 }, 20842 }, 20843 }, 20844 { 20845 name: "STMG3", 20846 auxType: auxSymOff, 20847 argLen: 5, 20848 faultOnNilArg0: true, 20849 symEffect: SymWrite, 20850 asm: s390x.ASTMG, 20851 reg: regInfo{ 20852 inputs: []inputInfo{ 20853 {1, 2}, // R1 20854 {2, 4}, // R2 20855 {3, 8}, // R3 20856 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20857 }, 20858 }, 20859 }, 20860 { 20861 name: "STMG4", 20862 auxType: auxSymOff, 20863 argLen: 6, 20864 faultOnNilArg0: true, 20865 symEffect: SymWrite, 20866 asm: s390x.ASTMG, 20867 reg: regInfo{ 20868 inputs: []inputInfo{ 20869 {1, 2}, // R1 20870 {2, 4}, // R2 20871 {3, 8}, // R3 20872 {4, 16}, // R4 20873 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20874 }, 20875 }, 20876 }, 20877 { 20878 name: "STM2", 20879 auxType: auxSymOff, 20880 argLen: 4, 20881 faultOnNilArg0: true, 20882 symEffect: SymWrite, 20883 asm: s390x.ASTMY, 20884 reg: regInfo{ 20885 inputs: []inputInfo{ 20886 {1, 2}, // R1 20887 {2, 4}, // R2 20888 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20889 }, 20890 }, 20891 }, 20892 { 20893 name: "STM3", 20894 auxType: auxSymOff, 20895 argLen: 5, 20896 faultOnNilArg0: true, 20897 symEffect: SymWrite, 20898 asm: s390x.ASTMY, 20899 reg: regInfo{ 20900 inputs: []inputInfo{ 20901 {1, 2}, // R1 20902 {2, 4}, // R2 20903 {3, 8}, // R3 20904 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20905 }, 20906 }, 20907 }, 20908 { 20909 name: "STM4", 20910 auxType: auxSymOff, 20911 argLen: 6, 20912 faultOnNilArg0: true, 20913 symEffect: SymWrite, 20914 asm: s390x.ASTMY, 20915 reg: regInfo{ 20916 inputs: []inputInfo{ 20917 {1, 2}, // R1 20918 {2, 4}, // R2 20919 {3, 8}, // R3 20920 {4, 16}, // R4 20921 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20922 }, 20923 }, 20924 }, 20925 { 20926 name: "LoweredMove", 20927 auxType: auxInt64, 20928 argLen: 4, 20929 clobberFlags: true, 20930 faultOnNilArg0: true, 20931 faultOnNilArg1: true, 20932 reg: regInfo{ 20933 inputs: []inputInfo{ 20934 {0, 2}, // R1 20935 {1, 4}, // R2 20936 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20937 }, 20938 clobbers: 6, // R1 R2 20939 }, 20940 }, 20941 { 20942 name: "LoweredZero", 20943 auxType: auxInt64, 20944 argLen: 3, 20945 clobberFlags: true, 20946 faultOnNilArg0: true, 20947 reg: regInfo{ 20948 inputs: []inputInfo{ 20949 {0, 2}, // R1 20950 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20951 }, 20952 clobbers: 2, // R1 20953 }, 20954 }, 20955 20956 { 20957 name: "Add8", 20958 argLen: 2, 20959 commutative: true, 20960 generic: true, 20961 }, 20962 { 20963 name: "Add16", 20964 argLen: 2, 20965 commutative: true, 20966 generic: true, 20967 }, 20968 { 20969 name: "Add32", 20970 argLen: 2, 20971 commutative: true, 20972 generic: true, 20973 }, 20974 { 20975 name: "Add64", 20976 argLen: 2, 20977 commutative: true, 20978 generic: true, 20979 }, 20980 { 20981 name: "AddPtr", 20982 argLen: 2, 20983 generic: true, 20984 }, 20985 { 20986 name: "Add32F", 20987 argLen: 2, 20988 commutative: true, 20989 generic: true, 20990 }, 20991 { 20992 name: "Add64F", 20993 argLen: 2, 20994 commutative: true, 20995 generic: true, 20996 }, 20997 { 20998 name: "Sub8", 20999 argLen: 2, 21000 generic: true, 21001 }, 21002 { 21003 name: "Sub16", 21004 argLen: 2, 21005 generic: true, 21006 }, 21007 { 21008 name: "Sub32", 21009 argLen: 2, 21010 generic: true, 21011 }, 21012 { 21013 name: "Sub64", 21014 argLen: 2, 21015 generic: true, 21016 }, 21017 { 21018 name: "SubPtr", 21019 argLen: 2, 21020 generic: true, 21021 }, 21022 { 21023 name: "Sub32F", 21024 argLen: 2, 21025 generic: true, 21026 }, 21027 { 21028 name: "Sub64F", 21029 argLen: 2, 21030 generic: true, 21031 }, 21032 { 21033 name: "Mul8", 21034 argLen: 2, 21035 commutative: true, 21036 generic: true, 21037 }, 21038 { 21039 name: "Mul16", 21040 argLen: 2, 21041 commutative: true, 21042 generic: true, 21043 }, 21044 { 21045 name: "Mul32", 21046 argLen: 2, 21047 commutative: true, 21048 generic: true, 21049 }, 21050 { 21051 name: "Mul64", 21052 argLen: 2, 21053 commutative: true, 21054 generic: true, 21055 }, 21056 { 21057 name: "Mul32F", 21058 argLen: 2, 21059 commutative: true, 21060 generic: true, 21061 }, 21062 { 21063 name: "Mul64F", 21064 argLen: 2, 21065 commutative: true, 21066 generic: true, 21067 }, 21068 { 21069 name: "Div32F", 21070 argLen: 2, 21071 generic: true, 21072 }, 21073 { 21074 name: "Div64F", 21075 argLen: 2, 21076 generic: true, 21077 }, 21078 { 21079 name: "Hmul32", 21080 argLen: 2, 21081 commutative: true, 21082 generic: true, 21083 }, 21084 { 21085 name: "Hmul32u", 21086 argLen: 2, 21087 commutative: true, 21088 generic: true, 21089 }, 21090 { 21091 name: "Hmul64", 21092 argLen: 2, 21093 commutative: true, 21094 generic: true, 21095 }, 21096 { 21097 name: "Hmul64u", 21098 argLen: 2, 21099 commutative: true, 21100 generic: true, 21101 }, 21102 { 21103 name: "Mul32uhilo", 21104 argLen: 2, 21105 commutative: true, 21106 generic: true, 21107 }, 21108 { 21109 name: "Mul64uhilo", 21110 argLen: 2, 21111 commutative: true, 21112 generic: true, 21113 }, 21114 { 21115 name: "Avg32u", 21116 argLen: 2, 21117 generic: true, 21118 }, 21119 { 21120 name: "Avg64u", 21121 argLen: 2, 21122 generic: true, 21123 }, 21124 { 21125 name: "Div8", 21126 argLen: 2, 21127 generic: true, 21128 }, 21129 { 21130 name: "Div8u", 21131 argLen: 2, 21132 generic: true, 21133 }, 21134 { 21135 name: "Div16", 21136 argLen: 2, 21137 generic: true, 21138 }, 21139 { 21140 name: "Div16u", 21141 argLen: 2, 21142 generic: true, 21143 }, 21144 { 21145 name: "Div32", 21146 argLen: 2, 21147 generic: true, 21148 }, 21149 { 21150 name: "Div32u", 21151 argLen: 2, 21152 generic: true, 21153 }, 21154 { 21155 name: "Div64", 21156 argLen: 2, 21157 generic: true, 21158 }, 21159 { 21160 name: "Div64u", 21161 argLen: 2, 21162 generic: true, 21163 }, 21164 { 21165 name: "Div128u", 21166 argLen: 3, 21167 generic: true, 21168 }, 21169 { 21170 name: "Mod8", 21171 argLen: 2, 21172 generic: true, 21173 }, 21174 { 21175 name: "Mod8u", 21176 argLen: 2, 21177 generic: true, 21178 }, 21179 { 21180 name: "Mod16", 21181 argLen: 2, 21182 generic: true, 21183 }, 21184 { 21185 name: "Mod16u", 21186 argLen: 2, 21187 generic: true, 21188 }, 21189 { 21190 name: "Mod32", 21191 argLen: 2, 21192 generic: true, 21193 }, 21194 { 21195 name: "Mod32u", 21196 argLen: 2, 21197 generic: true, 21198 }, 21199 { 21200 name: "Mod64", 21201 argLen: 2, 21202 generic: true, 21203 }, 21204 { 21205 name: "Mod64u", 21206 argLen: 2, 21207 generic: true, 21208 }, 21209 { 21210 name: "And8", 21211 argLen: 2, 21212 commutative: true, 21213 generic: true, 21214 }, 21215 { 21216 name: "And16", 21217 argLen: 2, 21218 commutative: true, 21219 generic: true, 21220 }, 21221 { 21222 name: "And32", 21223 argLen: 2, 21224 commutative: true, 21225 generic: true, 21226 }, 21227 { 21228 name: "And64", 21229 argLen: 2, 21230 commutative: true, 21231 generic: true, 21232 }, 21233 { 21234 name: "Or8", 21235 argLen: 2, 21236 commutative: true, 21237 generic: true, 21238 }, 21239 { 21240 name: "Or16", 21241 argLen: 2, 21242 commutative: true, 21243 generic: true, 21244 }, 21245 { 21246 name: "Or32", 21247 argLen: 2, 21248 commutative: true, 21249 generic: true, 21250 }, 21251 { 21252 name: "Or64", 21253 argLen: 2, 21254 commutative: true, 21255 generic: true, 21256 }, 21257 { 21258 name: "Xor8", 21259 argLen: 2, 21260 commutative: true, 21261 generic: true, 21262 }, 21263 { 21264 name: "Xor16", 21265 argLen: 2, 21266 commutative: true, 21267 generic: true, 21268 }, 21269 { 21270 name: "Xor32", 21271 argLen: 2, 21272 commutative: true, 21273 generic: true, 21274 }, 21275 { 21276 name: "Xor64", 21277 argLen: 2, 21278 commutative: true, 21279 generic: true, 21280 }, 21281 { 21282 name: "Lsh8x8", 21283 argLen: 2, 21284 generic: true, 21285 }, 21286 { 21287 name: "Lsh8x16", 21288 argLen: 2, 21289 generic: true, 21290 }, 21291 { 21292 name: "Lsh8x32", 21293 argLen: 2, 21294 generic: true, 21295 }, 21296 { 21297 name: "Lsh8x64", 21298 argLen: 2, 21299 generic: true, 21300 }, 21301 { 21302 name: "Lsh16x8", 21303 argLen: 2, 21304 generic: true, 21305 }, 21306 { 21307 name: "Lsh16x16", 21308 argLen: 2, 21309 generic: true, 21310 }, 21311 { 21312 name: "Lsh16x32", 21313 argLen: 2, 21314 generic: true, 21315 }, 21316 { 21317 name: "Lsh16x64", 21318 argLen: 2, 21319 generic: true, 21320 }, 21321 { 21322 name: "Lsh32x8", 21323 argLen: 2, 21324 generic: true, 21325 }, 21326 { 21327 name: "Lsh32x16", 21328 argLen: 2, 21329 generic: true, 21330 }, 21331 { 21332 name: "Lsh32x32", 21333 argLen: 2, 21334 generic: true, 21335 }, 21336 { 21337 name: "Lsh32x64", 21338 argLen: 2, 21339 generic: true, 21340 }, 21341 { 21342 name: "Lsh64x8", 21343 argLen: 2, 21344 generic: true, 21345 }, 21346 { 21347 name: "Lsh64x16", 21348 argLen: 2, 21349 generic: true, 21350 }, 21351 { 21352 name: "Lsh64x32", 21353 argLen: 2, 21354 generic: true, 21355 }, 21356 { 21357 name: "Lsh64x64", 21358 argLen: 2, 21359 generic: true, 21360 }, 21361 { 21362 name: "Rsh8x8", 21363 argLen: 2, 21364 generic: true, 21365 }, 21366 { 21367 name: "Rsh8x16", 21368 argLen: 2, 21369 generic: true, 21370 }, 21371 { 21372 name: "Rsh8x32", 21373 argLen: 2, 21374 generic: true, 21375 }, 21376 { 21377 name: "Rsh8x64", 21378 argLen: 2, 21379 generic: true, 21380 }, 21381 { 21382 name: "Rsh16x8", 21383 argLen: 2, 21384 generic: true, 21385 }, 21386 { 21387 name: "Rsh16x16", 21388 argLen: 2, 21389 generic: true, 21390 }, 21391 { 21392 name: "Rsh16x32", 21393 argLen: 2, 21394 generic: true, 21395 }, 21396 { 21397 name: "Rsh16x64", 21398 argLen: 2, 21399 generic: true, 21400 }, 21401 { 21402 name: "Rsh32x8", 21403 argLen: 2, 21404 generic: true, 21405 }, 21406 { 21407 name: "Rsh32x16", 21408 argLen: 2, 21409 generic: true, 21410 }, 21411 { 21412 name: "Rsh32x32", 21413 argLen: 2, 21414 generic: true, 21415 }, 21416 { 21417 name: "Rsh32x64", 21418 argLen: 2, 21419 generic: true, 21420 }, 21421 { 21422 name: "Rsh64x8", 21423 argLen: 2, 21424 generic: true, 21425 }, 21426 { 21427 name: "Rsh64x16", 21428 argLen: 2, 21429 generic: true, 21430 }, 21431 { 21432 name: "Rsh64x32", 21433 argLen: 2, 21434 generic: true, 21435 }, 21436 { 21437 name: "Rsh64x64", 21438 argLen: 2, 21439 generic: true, 21440 }, 21441 { 21442 name: "Rsh8Ux8", 21443 argLen: 2, 21444 generic: true, 21445 }, 21446 { 21447 name: "Rsh8Ux16", 21448 argLen: 2, 21449 generic: true, 21450 }, 21451 { 21452 name: "Rsh8Ux32", 21453 argLen: 2, 21454 generic: true, 21455 }, 21456 { 21457 name: "Rsh8Ux64", 21458 argLen: 2, 21459 generic: true, 21460 }, 21461 { 21462 name: "Rsh16Ux8", 21463 argLen: 2, 21464 generic: true, 21465 }, 21466 { 21467 name: "Rsh16Ux16", 21468 argLen: 2, 21469 generic: true, 21470 }, 21471 { 21472 name: "Rsh16Ux32", 21473 argLen: 2, 21474 generic: true, 21475 }, 21476 { 21477 name: "Rsh16Ux64", 21478 argLen: 2, 21479 generic: true, 21480 }, 21481 { 21482 name: "Rsh32Ux8", 21483 argLen: 2, 21484 generic: true, 21485 }, 21486 { 21487 name: "Rsh32Ux16", 21488 argLen: 2, 21489 generic: true, 21490 }, 21491 { 21492 name: "Rsh32Ux32", 21493 argLen: 2, 21494 generic: true, 21495 }, 21496 { 21497 name: "Rsh32Ux64", 21498 argLen: 2, 21499 generic: true, 21500 }, 21501 { 21502 name: "Rsh64Ux8", 21503 argLen: 2, 21504 generic: true, 21505 }, 21506 { 21507 name: "Rsh64Ux16", 21508 argLen: 2, 21509 generic: true, 21510 }, 21511 { 21512 name: "Rsh64Ux32", 21513 argLen: 2, 21514 generic: true, 21515 }, 21516 { 21517 name: "Rsh64Ux64", 21518 argLen: 2, 21519 generic: true, 21520 }, 21521 { 21522 name: "Eq8", 21523 argLen: 2, 21524 commutative: true, 21525 generic: true, 21526 }, 21527 { 21528 name: "Eq16", 21529 argLen: 2, 21530 commutative: true, 21531 generic: true, 21532 }, 21533 { 21534 name: "Eq32", 21535 argLen: 2, 21536 commutative: true, 21537 generic: true, 21538 }, 21539 { 21540 name: "Eq64", 21541 argLen: 2, 21542 commutative: true, 21543 generic: true, 21544 }, 21545 { 21546 name: "EqPtr", 21547 argLen: 2, 21548 commutative: true, 21549 generic: true, 21550 }, 21551 { 21552 name: "EqInter", 21553 argLen: 2, 21554 generic: true, 21555 }, 21556 { 21557 name: "EqSlice", 21558 argLen: 2, 21559 generic: true, 21560 }, 21561 { 21562 name: "Eq32F", 21563 argLen: 2, 21564 commutative: true, 21565 generic: true, 21566 }, 21567 { 21568 name: "Eq64F", 21569 argLen: 2, 21570 commutative: true, 21571 generic: true, 21572 }, 21573 { 21574 name: "Neq8", 21575 argLen: 2, 21576 commutative: true, 21577 generic: true, 21578 }, 21579 { 21580 name: "Neq16", 21581 argLen: 2, 21582 commutative: true, 21583 generic: true, 21584 }, 21585 { 21586 name: "Neq32", 21587 argLen: 2, 21588 commutative: true, 21589 generic: true, 21590 }, 21591 { 21592 name: "Neq64", 21593 argLen: 2, 21594 commutative: true, 21595 generic: true, 21596 }, 21597 { 21598 name: "NeqPtr", 21599 argLen: 2, 21600 commutative: true, 21601 generic: true, 21602 }, 21603 { 21604 name: "NeqInter", 21605 argLen: 2, 21606 generic: true, 21607 }, 21608 { 21609 name: "NeqSlice", 21610 argLen: 2, 21611 generic: true, 21612 }, 21613 { 21614 name: "Neq32F", 21615 argLen: 2, 21616 commutative: true, 21617 generic: true, 21618 }, 21619 { 21620 name: "Neq64F", 21621 argLen: 2, 21622 commutative: true, 21623 generic: true, 21624 }, 21625 { 21626 name: "Less8", 21627 argLen: 2, 21628 generic: true, 21629 }, 21630 { 21631 name: "Less8U", 21632 argLen: 2, 21633 generic: true, 21634 }, 21635 { 21636 name: "Less16", 21637 argLen: 2, 21638 generic: true, 21639 }, 21640 { 21641 name: "Less16U", 21642 argLen: 2, 21643 generic: true, 21644 }, 21645 { 21646 name: "Less32", 21647 argLen: 2, 21648 generic: true, 21649 }, 21650 { 21651 name: "Less32U", 21652 argLen: 2, 21653 generic: true, 21654 }, 21655 { 21656 name: "Less64", 21657 argLen: 2, 21658 generic: true, 21659 }, 21660 { 21661 name: "Less64U", 21662 argLen: 2, 21663 generic: true, 21664 }, 21665 { 21666 name: "Less32F", 21667 argLen: 2, 21668 generic: true, 21669 }, 21670 { 21671 name: "Less64F", 21672 argLen: 2, 21673 generic: true, 21674 }, 21675 { 21676 name: "Leq8", 21677 argLen: 2, 21678 generic: true, 21679 }, 21680 { 21681 name: "Leq8U", 21682 argLen: 2, 21683 generic: true, 21684 }, 21685 { 21686 name: "Leq16", 21687 argLen: 2, 21688 generic: true, 21689 }, 21690 { 21691 name: "Leq16U", 21692 argLen: 2, 21693 generic: true, 21694 }, 21695 { 21696 name: "Leq32", 21697 argLen: 2, 21698 generic: true, 21699 }, 21700 { 21701 name: "Leq32U", 21702 argLen: 2, 21703 generic: true, 21704 }, 21705 { 21706 name: "Leq64", 21707 argLen: 2, 21708 generic: true, 21709 }, 21710 { 21711 name: "Leq64U", 21712 argLen: 2, 21713 generic: true, 21714 }, 21715 { 21716 name: "Leq32F", 21717 argLen: 2, 21718 generic: true, 21719 }, 21720 { 21721 name: "Leq64F", 21722 argLen: 2, 21723 generic: true, 21724 }, 21725 { 21726 name: "Greater8", 21727 argLen: 2, 21728 generic: true, 21729 }, 21730 { 21731 name: "Greater8U", 21732 argLen: 2, 21733 generic: true, 21734 }, 21735 { 21736 name: "Greater16", 21737 argLen: 2, 21738 generic: true, 21739 }, 21740 { 21741 name: "Greater16U", 21742 argLen: 2, 21743 generic: true, 21744 }, 21745 { 21746 name: "Greater32", 21747 argLen: 2, 21748 generic: true, 21749 }, 21750 { 21751 name: "Greater32U", 21752 argLen: 2, 21753 generic: true, 21754 }, 21755 { 21756 name: "Greater64", 21757 argLen: 2, 21758 generic: true, 21759 }, 21760 { 21761 name: "Greater64U", 21762 argLen: 2, 21763 generic: true, 21764 }, 21765 { 21766 name: "Greater32F", 21767 argLen: 2, 21768 generic: true, 21769 }, 21770 { 21771 name: "Greater64F", 21772 argLen: 2, 21773 generic: true, 21774 }, 21775 { 21776 name: "Geq8", 21777 argLen: 2, 21778 generic: true, 21779 }, 21780 { 21781 name: "Geq8U", 21782 argLen: 2, 21783 generic: true, 21784 }, 21785 { 21786 name: "Geq16", 21787 argLen: 2, 21788 generic: true, 21789 }, 21790 { 21791 name: "Geq16U", 21792 argLen: 2, 21793 generic: true, 21794 }, 21795 { 21796 name: "Geq32", 21797 argLen: 2, 21798 generic: true, 21799 }, 21800 { 21801 name: "Geq32U", 21802 argLen: 2, 21803 generic: true, 21804 }, 21805 { 21806 name: "Geq64", 21807 argLen: 2, 21808 generic: true, 21809 }, 21810 { 21811 name: "Geq64U", 21812 argLen: 2, 21813 generic: true, 21814 }, 21815 { 21816 name: "Geq32F", 21817 argLen: 2, 21818 generic: true, 21819 }, 21820 { 21821 name: "Geq64F", 21822 argLen: 2, 21823 generic: true, 21824 }, 21825 { 21826 name: "AndB", 21827 argLen: 2, 21828 commutative: true, 21829 generic: true, 21830 }, 21831 { 21832 name: "OrB", 21833 argLen: 2, 21834 commutative: true, 21835 generic: true, 21836 }, 21837 { 21838 name: "EqB", 21839 argLen: 2, 21840 commutative: true, 21841 generic: true, 21842 }, 21843 { 21844 name: "NeqB", 21845 argLen: 2, 21846 commutative: true, 21847 generic: true, 21848 }, 21849 { 21850 name: "Not", 21851 argLen: 1, 21852 generic: true, 21853 }, 21854 { 21855 name: "Neg8", 21856 argLen: 1, 21857 generic: true, 21858 }, 21859 { 21860 name: "Neg16", 21861 argLen: 1, 21862 generic: true, 21863 }, 21864 { 21865 name: "Neg32", 21866 argLen: 1, 21867 generic: true, 21868 }, 21869 { 21870 name: "Neg64", 21871 argLen: 1, 21872 generic: true, 21873 }, 21874 { 21875 name: "Neg32F", 21876 argLen: 1, 21877 generic: true, 21878 }, 21879 { 21880 name: "Neg64F", 21881 argLen: 1, 21882 generic: true, 21883 }, 21884 { 21885 name: "Com8", 21886 argLen: 1, 21887 generic: true, 21888 }, 21889 { 21890 name: "Com16", 21891 argLen: 1, 21892 generic: true, 21893 }, 21894 { 21895 name: "Com32", 21896 argLen: 1, 21897 generic: true, 21898 }, 21899 { 21900 name: "Com64", 21901 argLen: 1, 21902 generic: true, 21903 }, 21904 { 21905 name: "Ctz32", 21906 argLen: 1, 21907 generic: true, 21908 }, 21909 { 21910 name: "Ctz64", 21911 argLen: 1, 21912 generic: true, 21913 }, 21914 { 21915 name: "BitLen32", 21916 argLen: 1, 21917 generic: true, 21918 }, 21919 { 21920 name: "BitLen64", 21921 argLen: 1, 21922 generic: true, 21923 }, 21924 { 21925 name: "Bswap32", 21926 argLen: 1, 21927 generic: true, 21928 }, 21929 { 21930 name: "Bswap64", 21931 argLen: 1, 21932 generic: true, 21933 }, 21934 { 21935 name: "BitRev8", 21936 argLen: 1, 21937 generic: true, 21938 }, 21939 { 21940 name: "BitRev16", 21941 argLen: 1, 21942 generic: true, 21943 }, 21944 { 21945 name: "BitRev32", 21946 argLen: 1, 21947 generic: true, 21948 }, 21949 { 21950 name: "BitRev64", 21951 argLen: 1, 21952 generic: true, 21953 }, 21954 { 21955 name: "PopCount8", 21956 argLen: 1, 21957 generic: true, 21958 }, 21959 { 21960 name: "PopCount16", 21961 argLen: 1, 21962 generic: true, 21963 }, 21964 { 21965 name: "PopCount32", 21966 argLen: 1, 21967 generic: true, 21968 }, 21969 { 21970 name: "PopCount64", 21971 argLen: 1, 21972 generic: true, 21973 }, 21974 { 21975 name: "Sqrt", 21976 argLen: 1, 21977 generic: true, 21978 }, 21979 { 21980 name: "Phi", 21981 argLen: -1, 21982 generic: true, 21983 }, 21984 { 21985 name: "Copy", 21986 argLen: 1, 21987 generic: true, 21988 }, 21989 { 21990 name: "Convert", 21991 argLen: 2, 21992 generic: true, 21993 }, 21994 { 21995 name: "ConstBool", 21996 auxType: auxBool, 21997 argLen: 0, 21998 generic: true, 21999 }, 22000 { 22001 name: "ConstString", 22002 auxType: auxString, 22003 argLen: 0, 22004 generic: true, 22005 }, 22006 { 22007 name: "ConstNil", 22008 argLen: 0, 22009 generic: true, 22010 }, 22011 { 22012 name: "Const8", 22013 auxType: auxInt8, 22014 argLen: 0, 22015 generic: true, 22016 }, 22017 { 22018 name: "Const16", 22019 auxType: auxInt16, 22020 argLen: 0, 22021 generic: true, 22022 }, 22023 { 22024 name: "Const32", 22025 auxType: auxInt32, 22026 argLen: 0, 22027 generic: true, 22028 }, 22029 { 22030 name: "Const64", 22031 auxType: auxInt64, 22032 argLen: 0, 22033 generic: true, 22034 }, 22035 { 22036 name: "Const32F", 22037 auxType: auxFloat32, 22038 argLen: 0, 22039 generic: true, 22040 }, 22041 { 22042 name: "Const64F", 22043 auxType: auxFloat64, 22044 argLen: 0, 22045 generic: true, 22046 }, 22047 { 22048 name: "ConstInterface", 22049 argLen: 0, 22050 generic: true, 22051 }, 22052 { 22053 name: "ConstSlice", 22054 argLen: 0, 22055 generic: true, 22056 }, 22057 { 22058 name: "InitMem", 22059 argLen: 0, 22060 generic: true, 22061 }, 22062 { 22063 name: "Arg", 22064 auxType: auxSymOff, 22065 argLen: 0, 22066 symEffect: SymNone, 22067 generic: true, 22068 }, 22069 { 22070 name: "Addr", 22071 auxType: auxSym, 22072 argLen: 1, 22073 symEffect: SymAddr, 22074 generic: true, 22075 }, 22076 { 22077 name: "SP", 22078 argLen: 0, 22079 generic: true, 22080 }, 22081 { 22082 name: "SB", 22083 argLen: 0, 22084 generic: true, 22085 }, 22086 { 22087 name: "Load", 22088 argLen: 2, 22089 generic: true, 22090 }, 22091 { 22092 name: "Store", 22093 auxType: auxTyp, 22094 argLen: 3, 22095 generic: true, 22096 }, 22097 { 22098 name: "Move", 22099 auxType: auxTypSize, 22100 argLen: 3, 22101 generic: true, 22102 }, 22103 { 22104 name: "Zero", 22105 auxType: auxTypSize, 22106 argLen: 2, 22107 generic: true, 22108 }, 22109 { 22110 name: "StoreWB", 22111 auxType: auxTyp, 22112 argLen: 3, 22113 generic: true, 22114 }, 22115 { 22116 name: "MoveWB", 22117 auxType: auxTypSize, 22118 argLen: 3, 22119 generic: true, 22120 }, 22121 { 22122 name: "ZeroWB", 22123 auxType: auxTypSize, 22124 argLen: 2, 22125 generic: true, 22126 }, 22127 { 22128 name: "ClosureCall", 22129 auxType: auxInt64, 22130 argLen: 3, 22131 call: true, 22132 generic: true, 22133 }, 22134 { 22135 name: "StaticCall", 22136 auxType: auxSymOff, 22137 argLen: 1, 22138 call: true, 22139 symEffect: SymNone, 22140 generic: true, 22141 }, 22142 { 22143 name: "InterCall", 22144 auxType: auxInt64, 22145 argLen: 2, 22146 call: true, 22147 generic: true, 22148 }, 22149 { 22150 name: "SignExt8to16", 22151 argLen: 1, 22152 generic: true, 22153 }, 22154 { 22155 name: "SignExt8to32", 22156 argLen: 1, 22157 generic: true, 22158 }, 22159 { 22160 name: "SignExt8to64", 22161 argLen: 1, 22162 generic: true, 22163 }, 22164 { 22165 name: "SignExt16to32", 22166 argLen: 1, 22167 generic: true, 22168 }, 22169 { 22170 name: "SignExt16to64", 22171 argLen: 1, 22172 generic: true, 22173 }, 22174 { 22175 name: "SignExt32to64", 22176 argLen: 1, 22177 generic: true, 22178 }, 22179 { 22180 name: "ZeroExt8to16", 22181 argLen: 1, 22182 generic: true, 22183 }, 22184 { 22185 name: "ZeroExt8to32", 22186 argLen: 1, 22187 generic: true, 22188 }, 22189 { 22190 name: "ZeroExt8to64", 22191 argLen: 1, 22192 generic: true, 22193 }, 22194 { 22195 name: "ZeroExt16to32", 22196 argLen: 1, 22197 generic: true, 22198 }, 22199 { 22200 name: "ZeroExt16to64", 22201 argLen: 1, 22202 generic: true, 22203 }, 22204 { 22205 name: "ZeroExt32to64", 22206 argLen: 1, 22207 generic: true, 22208 }, 22209 { 22210 name: "Trunc16to8", 22211 argLen: 1, 22212 generic: true, 22213 }, 22214 { 22215 name: "Trunc32to8", 22216 argLen: 1, 22217 generic: true, 22218 }, 22219 { 22220 name: "Trunc32to16", 22221 argLen: 1, 22222 generic: true, 22223 }, 22224 { 22225 name: "Trunc64to8", 22226 argLen: 1, 22227 generic: true, 22228 }, 22229 { 22230 name: "Trunc64to16", 22231 argLen: 1, 22232 generic: true, 22233 }, 22234 { 22235 name: "Trunc64to32", 22236 argLen: 1, 22237 generic: true, 22238 }, 22239 { 22240 name: "Cvt32to32F", 22241 argLen: 1, 22242 generic: true, 22243 }, 22244 { 22245 name: "Cvt32to64F", 22246 argLen: 1, 22247 generic: true, 22248 }, 22249 { 22250 name: "Cvt64to32F", 22251 argLen: 1, 22252 generic: true, 22253 }, 22254 { 22255 name: "Cvt64to64F", 22256 argLen: 1, 22257 generic: true, 22258 }, 22259 { 22260 name: "Cvt32Fto32", 22261 argLen: 1, 22262 generic: true, 22263 }, 22264 { 22265 name: "Cvt32Fto64", 22266 argLen: 1, 22267 generic: true, 22268 }, 22269 { 22270 name: "Cvt64Fto32", 22271 argLen: 1, 22272 generic: true, 22273 }, 22274 { 22275 name: "Cvt64Fto64", 22276 argLen: 1, 22277 generic: true, 22278 }, 22279 { 22280 name: "Cvt32Fto64F", 22281 argLen: 1, 22282 generic: true, 22283 }, 22284 { 22285 name: "Cvt64Fto32F", 22286 argLen: 1, 22287 generic: true, 22288 }, 22289 { 22290 name: "Round32F", 22291 argLen: 1, 22292 generic: true, 22293 }, 22294 { 22295 name: "Round64F", 22296 argLen: 1, 22297 generic: true, 22298 }, 22299 { 22300 name: "IsNonNil", 22301 argLen: 1, 22302 generic: true, 22303 }, 22304 { 22305 name: "IsInBounds", 22306 argLen: 2, 22307 generic: true, 22308 }, 22309 { 22310 name: "IsSliceInBounds", 22311 argLen: 2, 22312 generic: true, 22313 }, 22314 { 22315 name: "NilCheck", 22316 argLen: 2, 22317 generic: true, 22318 }, 22319 { 22320 name: "GetG", 22321 argLen: 1, 22322 generic: true, 22323 }, 22324 { 22325 name: "GetClosurePtr", 22326 argLen: 0, 22327 generic: true, 22328 }, 22329 { 22330 name: "PtrIndex", 22331 argLen: 2, 22332 generic: true, 22333 }, 22334 { 22335 name: "OffPtr", 22336 auxType: auxInt64, 22337 argLen: 1, 22338 generic: true, 22339 }, 22340 { 22341 name: "SliceMake", 22342 argLen: 3, 22343 generic: true, 22344 }, 22345 { 22346 name: "SlicePtr", 22347 argLen: 1, 22348 generic: true, 22349 }, 22350 { 22351 name: "SliceLen", 22352 argLen: 1, 22353 generic: true, 22354 }, 22355 { 22356 name: "SliceCap", 22357 argLen: 1, 22358 generic: true, 22359 }, 22360 { 22361 name: "ComplexMake", 22362 argLen: 2, 22363 generic: true, 22364 }, 22365 { 22366 name: "ComplexReal", 22367 argLen: 1, 22368 generic: true, 22369 }, 22370 { 22371 name: "ComplexImag", 22372 argLen: 1, 22373 generic: true, 22374 }, 22375 { 22376 name: "StringMake", 22377 argLen: 2, 22378 generic: true, 22379 }, 22380 { 22381 name: "StringPtr", 22382 argLen: 1, 22383 generic: true, 22384 }, 22385 { 22386 name: "StringLen", 22387 argLen: 1, 22388 generic: true, 22389 }, 22390 { 22391 name: "IMake", 22392 argLen: 2, 22393 generic: true, 22394 }, 22395 { 22396 name: "ITab", 22397 argLen: 1, 22398 generic: true, 22399 }, 22400 { 22401 name: "IData", 22402 argLen: 1, 22403 generic: true, 22404 }, 22405 { 22406 name: "StructMake0", 22407 argLen: 0, 22408 generic: true, 22409 }, 22410 { 22411 name: "StructMake1", 22412 argLen: 1, 22413 generic: true, 22414 }, 22415 { 22416 name: "StructMake2", 22417 argLen: 2, 22418 generic: true, 22419 }, 22420 { 22421 name: "StructMake3", 22422 argLen: 3, 22423 generic: true, 22424 }, 22425 { 22426 name: "StructMake4", 22427 argLen: 4, 22428 generic: true, 22429 }, 22430 { 22431 name: "StructSelect", 22432 auxType: auxInt64, 22433 argLen: 1, 22434 generic: true, 22435 }, 22436 { 22437 name: "ArrayMake0", 22438 argLen: 0, 22439 generic: true, 22440 }, 22441 { 22442 name: "ArrayMake1", 22443 argLen: 1, 22444 generic: true, 22445 }, 22446 { 22447 name: "ArraySelect", 22448 auxType: auxInt64, 22449 argLen: 1, 22450 generic: true, 22451 }, 22452 { 22453 name: "StoreReg", 22454 argLen: 1, 22455 generic: true, 22456 }, 22457 { 22458 name: "LoadReg", 22459 argLen: 1, 22460 generic: true, 22461 }, 22462 { 22463 name: "FwdRef", 22464 auxType: auxSym, 22465 argLen: 0, 22466 symEffect: SymNone, 22467 generic: true, 22468 }, 22469 { 22470 name: "Unknown", 22471 argLen: 0, 22472 generic: true, 22473 }, 22474 { 22475 name: "VarDef", 22476 auxType: auxSym, 22477 argLen: 1, 22478 symEffect: SymNone, 22479 generic: true, 22480 }, 22481 { 22482 name: "VarKill", 22483 auxType: auxSym, 22484 argLen: 1, 22485 symEffect: SymNone, 22486 generic: true, 22487 }, 22488 { 22489 name: "VarLive", 22490 auxType: auxSym, 22491 argLen: 1, 22492 symEffect: SymNone, 22493 generic: true, 22494 }, 22495 { 22496 name: "KeepAlive", 22497 argLen: 2, 22498 generic: true, 22499 }, 22500 { 22501 name: "Int64Make", 22502 argLen: 2, 22503 generic: true, 22504 }, 22505 { 22506 name: "Int64Hi", 22507 argLen: 1, 22508 generic: true, 22509 }, 22510 { 22511 name: "Int64Lo", 22512 argLen: 1, 22513 generic: true, 22514 }, 22515 { 22516 name: "Add32carry", 22517 argLen: 2, 22518 commutative: true, 22519 generic: true, 22520 }, 22521 { 22522 name: "Add32withcarry", 22523 argLen: 3, 22524 commutative: true, 22525 generic: true, 22526 }, 22527 { 22528 name: "Sub32carry", 22529 argLen: 2, 22530 generic: true, 22531 }, 22532 { 22533 name: "Sub32withcarry", 22534 argLen: 3, 22535 generic: true, 22536 }, 22537 { 22538 name: "Signmask", 22539 argLen: 1, 22540 generic: true, 22541 }, 22542 { 22543 name: "Zeromask", 22544 argLen: 1, 22545 generic: true, 22546 }, 22547 { 22548 name: "Slicemask", 22549 argLen: 1, 22550 generic: true, 22551 }, 22552 { 22553 name: "Cvt32Uto32F", 22554 argLen: 1, 22555 generic: true, 22556 }, 22557 { 22558 name: "Cvt32Uto64F", 22559 argLen: 1, 22560 generic: true, 22561 }, 22562 { 22563 name: "Cvt32Fto32U", 22564 argLen: 1, 22565 generic: true, 22566 }, 22567 { 22568 name: "Cvt64Fto32U", 22569 argLen: 1, 22570 generic: true, 22571 }, 22572 { 22573 name: "Cvt64Uto32F", 22574 argLen: 1, 22575 generic: true, 22576 }, 22577 { 22578 name: "Cvt64Uto64F", 22579 argLen: 1, 22580 generic: true, 22581 }, 22582 { 22583 name: "Cvt32Fto64U", 22584 argLen: 1, 22585 generic: true, 22586 }, 22587 { 22588 name: "Cvt64Fto64U", 22589 argLen: 1, 22590 generic: true, 22591 }, 22592 { 22593 name: "Select0", 22594 argLen: 1, 22595 generic: true, 22596 }, 22597 { 22598 name: "Select1", 22599 argLen: 1, 22600 generic: true, 22601 }, 22602 { 22603 name: "AtomicLoad32", 22604 argLen: 2, 22605 generic: true, 22606 }, 22607 { 22608 name: "AtomicLoad64", 22609 argLen: 2, 22610 generic: true, 22611 }, 22612 { 22613 name: "AtomicLoadPtr", 22614 argLen: 2, 22615 generic: true, 22616 }, 22617 { 22618 name: "AtomicStore32", 22619 argLen: 3, 22620 hasSideEffects: true, 22621 generic: true, 22622 }, 22623 { 22624 name: "AtomicStore64", 22625 argLen: 3, 22626 hasSideEffects: true, 22627 generic: true, 22628 }, 22629 { 22630 name: "AtomicStorePtrNoWB", 22631 argLen: 3, 22632 hasSideEffects: true, 22633 generic: true, 22634 }, 22635 { 22636 name: "AtomicExchange32", 22637 argLen: 3, 22638 hasSideEffects: true, 22639 generic: true, 22640 }, 22641 { 22642 name: "AtomicExchange64", 22643 argLen: 3, 22644 hasSideEffects: true, 22645 generic: true, 22646 }, 22647 { 22648 name: "AtomicAdd32", 22649 argLen: 3, 22650 hasSideEffects: true, 22651 generic: true, 22652 }, 22653 { 22654 name: "AtomicAdd64", 22655 argLen: 3, 22656 hasSideEffects: true, 22657 generic: true, 22658 }, 22659 { 22660 name: "AtomicCompareAndSwap32", 22661 argLen: 4, 22662 hasSideEffects: true, 22663 generic: true, 22664 }, 22665 { 22666 name: "AtomicCompareAndSwap64", 22667 argLen: 4, 22668 hasSideEffects: true, 22669 generic: true, 22670 }, 22671 { 22672 name: "AtomicAnd8", 22673 argLen: 3, 22674 hasSideEffects: true, 22675 generic: true, 22676 }, 22677 { 22678 name: "AtomicOr8", 22679 argLen: 3, 22680 hasSideEffects: true, 22681 generic: true, 22682 }, 22683 { 22684 name: "Clobber", 22685 auxType: auxSymOff, 22686 argLen: 0, 22687 symEffect: SymNone, 22688 generic: true, 22689 }, 22690 } 22691 22692 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 22693 func (o Op) String() string { return opcodeTable[o].name } 22694 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 22695 func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } 22696 func (o Op) IsCall() bool { return opcodeTable[o].call } 22697 22698 var registers386 = [...]Register{ 22699 {0, x86.REG_AX, "AX"}, 22700 {1, x86.REG_CX, "CX"}, 22701 {2, x86.REG_DX, "DX"}, 22702 {3, x86.REG_BX, "BX"}, 22703 {4, x86.REGSP, "SP"}, 22704 {5, x86.REG_BP, "BP"}, 22705 {6, x86.REG_SI, "SI"}, 22706 {7, x86.REG_DI, "DI"}, 22707 {8, x86.REG_X0, "X0"}, 22708 {9, x86.REG_X1, "X1"}, 22709 {10, x86.REG_X2, "X2"}, 22710 {11, x86.REG_X3, "X3"}, 22711 {12, x86.REG_X4, "X4"}, 22712 {13, x86.REG_X5, "X5"}, 22713 {14, x86.REG_X6, "X6"}, 22714 {15, x86.REG_X7, "X7"}, 22715 {16, 0, "SB"}, 22716 } 22717 var gpRegMask386 = regMask(239) 22718 var fpRegMask386 = regMask(65280) 22719 var specialRegMask386 = regMask(0) 22720 var framepointerReg386 = int8(5) 22721 var linkReg386 = int8(-1) 22722 var registersAMD64 = [...]Register{ 22723 {0, x86.REG_AX, "AX"}, 22724 {1, x86.REG_CX, "CX"}, 22725 {2, x86.REG_DX, "DX"}, 22726 {3, x86.REG_BX, "BX"}, 22727 {4, x86.REGSP, "SP"}, 22728 {5, x86.REG_BP, "BP"}, 22729 {6, x86.REG_SI, "SI"}, 22730 {7, x86.REG_DI, "DI"}, 22731 {8, x86.REG_R8, "R8"}, 22732 {9, x86.REG_R9, "R9"}, 22733 {10, x86.REG_R10, "R10"}, 22734 {11, x86.REG_R11, "R11"}, 22735 {12, x86.REG_R12, "R12"}, 22736 {13, x86.REG_R13, "R13"}, 22737 {14, x86.REG_R14, "R14"}, 22738 {15, x86.REG_R15, "R15"}, 22739 {16, x86.REG_X0, "X0"}, 22740 {17, x86.REG_X1, "X1"}, 22741 {18, x86.REG_X2, "X2"}, 22742 {19, x86.REG_X3, "X3"}, 22743 {20, x86.REG_X4, "X4"}, 22744 {21, x86.REG_X5, "X5"}, 22745 {22, x86.REG_X6, "X6"}, 22746 {23, x86.REG_X7, "X7"}, 22747 {24, x86.REG_X8, "X8"}, 22748 {25, x86.REG_X9, "X9"}, 22749 {26, x86.REG_X10, "X10"}, 22750 {27, x86.REG_X11, "X11"}, 22751 {28, x86.REG_X12, "X12"}, 22752 {29, x86.REG_X13, "X13"}, 22753 {30, x86.REG_X14, "X14"}, 22754 {31, x86.REG_X15, "X15"}, 22755 {32, 0, "SB"}, 22756 } 22757 var gpRegMaskAMD64 = regMask(65519) 22758 var fpRegMaskAMD64 = regMask(4294901760) 22759 var specialRegMaskAMD64 = regMask(0) 22760 var framepointerRegAMD64 = int8(5) 22761 var linkRegAMD64 = int8(-1) 22762 var registersARM = [...]Register{ 22763 {0, arm.REG_R0, "R0"}, 22764 {1, arm.REG_R1, "R1"}, 22765 {2, arm.REG_R2, "R2"}, 22766 {3, arm.REG_R3, "R3"}, 22767 {4, arm.REG_R4, "R4"}, 22768 {5, arm.REG_R5, "R5"}, 22769 {6, arm.REG_R6, "R6"}, 22770 {7, arm.REG_R7, "R7"}, 22771 {8, arm.REG_R8, "R8"}, 22772 {9, arm.REG_R9, "R9"}, 22773 {10, arm.REGG, "g"}, 22774 {11, arm.REG_R11, "R11"}, 22775 {12, arm.REG_R12, "R12"}, 22776 {13, arm.REGSP, "SP"}, 22777 {14, arm.REG_R14, "R14"}, 22778 {15, arm.REG_R15, "R15"}, 22779 {16, arm.REG_F0, "F0"}, 22780 {17, arm.REG_F1, "F1"}, 22781 {18, arm.REG_F2, "F2"}, 22782 {19, arm.REG_F3, "F3"}, 22783 {20, arm.REG_F4, "F4"}, 22784 {21, arm.REG_F5, "F5"}, 22785 {22, arm.REG_F6, "F6"}, 22786 {23, arm.REG_F7, "F7"}, 22787 {24, arm.REG_F8, "F8"}, 22788 {25, arm.REG_F9, "F9"}, 22789 {26, arm.REG_F10, "F10"}, 22790 {27, arm.REG_F11, "F11"}, 22791 {28, arm.REG_F12, "F12"}, 22792 {29, arm.REG_F13, "F13"}, 22793 {30, arm.REG_F14, "F14"}, 22794 {31, arm.REG_F15, "F15"}, 22795 {32, 0, "SB"}, 22796 } 22797 var gpRegMaskARM = regMask(21503) 22798 var fpRegMaskARM = regMask(4294901760) 22799 var specialRegMaskARM = regMask(0) 22800 var framepointerRegARM = int8(-1) 22801 var linkRegARM = int8(14) 22802 var registersARM64 = [...]Register{ 22803 {0, arm64.REG_R0, "R0"}, 22804 {1, arm64.REG_R1, "R1"}, 22805 {2, arm64.REG_R2, "R2"}, 22806 {3, arm64.REG_R3, "R3"}, 22807 {4, arm64.REG_R4, "R4"}, 22808 {5, arm64.REG_R5, "R5"}, 22809 {6, arm64.REG_R6, "R6"}, 22810 {7, arm64.REG_R7, "R7"}, 22811 {8, arm64.REG_R8, "R8"}, 22812 {9, arm64.REG_R9, "R9"}, 22813 {10, arm64.REG_R10, "R10"}, 22814 {11, arm64.REG_R11, "R11"}, 22815 {12, arm64.REG_R12, "R12"}, 22816 {13, arm64.REG_R13, "R13"}, 22817 {14, arm64.REG_R14, "R14"}, 22818 {15, arm64.REG_R15, "R15"}, 22819 {16, arm64.REG_R16, "R16"}, 22820 {17, arm64.REG_R17, "R17"}, 22821 {18, arm64.REG_R18, "R18"}, 22822 {19, arm64.REG_R19, "R19"}, 22823 {20, arm64.REG_R20, "R20"}, 22824 {21, arm64.REG_R21, "R21"}, 22825 {22, arm64.REG_R22, "R22"}, 22826 {23, arm64.REG_R23, "R23"}, 22827 {24, arm64.REG_R24, "R24"}, 22828 {25, arm64.REG_R25, "R25"}, 22829 {26, arm64.REG_R26, "R26"}, 22830 {27, arm64.REGG, "g"}, 22831 {28, arm64.REG_R29, "R29"}, 22832 {29, arm64.REG_R30, "R30"}, 22833 {30, arm64.REGSP, "SP"}, 22834 {31, arm64.REG_F0, "F0"}, 22835 {32, arm64.REG_F1, "F1"}, 22836 {33, arm64.REG_F2, "F2"}, 22837 {34, arm64.REG_F3, "F3"}, 22838 {35, arm64.REG_F4, "F4"}, 22839 {36, arm64.REG_F5, "F5"}, 22840 {37, arm64.REG_F6, "F6"}, 22841 {38, arm64.REG_F7, "F7"}, 22842 {39, arm64.REG_F8, "F8"}, 22843 {40, arm64.REG_F9, "F9"}, 22844 {41, arm64.REG_F10, "F10"}, 22845 {42, arm64.REG_F11, "F11"}, 22846 {43, arm64.REG_F12, "F12"}, 22847 {44, arm64.REG_F13, "F13"}, 22848 {45, arm64.REG_F14, "F14"}, 22849 {46, arm64.REG_F15, "F15"}, 22850 {47, arm64.REG_F16, "F16"}, 22851 {48, arm64.REG_F17, "F17"}, 22852 {49, arm64.REG_F18, "F18"}, 22853 {50, arm64.REG_F19, "F19"}, 22854 {51, arm64.REG_F20, "F20"}, 22855 {52, arm64.REG_F21, "F21"}, 22856 {53, arm64.REG_F22, "F22"}, 22857 {54, arm64.REG_F23, "F23"}, 22858 {55, arm64.REG_F24, "F24"}, 22859 {56, arm64.REG_F25, "F25"}, 22860 {57, arm64.REG_F26, "F26"}, 22861 {58, arm64.REG_F27, "F27"}, 22862 {59, arm64.REG_F28, "F28"}, 22863 {60, arm64.REG_F29, "F29"}, 22864 {61, arm64.REG_F30, "F30"}, 22865 {62, arm64.REG_F31, "F31"}, 22866 {63, 0, "SB"}, 22867 } 22868 var gpRegMaskARM64 = regMask(670826495) 22869 var fpRegMaskARM64 = regMask(9223372034707292160) 22870 var specialRegMaskARM64 = regMask(0) 22871 var framepointerRegARM64 = int8(-1) 22872 var linkRegARM64 = int8(29) 22873 var registersMIPS = [...]Register{ 22874 {0, mips.REG_R0, "R0"}, 22875 {1, mips.REG_R1, "R1"}, 22876 {2, mips.REG_R2, "R2"}, 22877 {3, mips.REG_R3, "R3"}, 22878 {4, mips.REG_R4, "R4"}, 22879 {5, mips.REG_R5, "R5"}, 22880 {6, mips.REG_R6, "R6"}, 22881 {7, mips.REG_R7, "R7"}, 22882 {8, mips.REG_R8, "R8"}, 22883 {9, mips.REG_R9, "R9"}, 22884 {10, mips.REG_R10, "R10"}, 22885 {11, mips.REG_R11, "R11"}, 22886 {12, mips.REG_R12, "R12"}, 22887 {13, mips.REG_R13, "R13"}, 22888 {14, mips.REG_R14, "R14"}, 22889 {15, mips.REG_R15, "R15"}, 22890 {16, mips.REG_R16, "R16"}, 22891 {17, mips.REG_R17, "R17"}, 22892 {18, mips.REG_R18, "R18"}, 22893 {19, mips.REG_R19, "R19"}, 22894 {20, mips.REG_R20, "R20"}, 22895 {21, mips.REG_R21, "R21"}, 22896 {22, mips.REG_R22, "R22"}, 22897 {23, mips.REG_R24, "R24"}, 22898 {24, mips.REG_R25, "R25"}, 22899 {25, mips.REG_R28, "R28"}, 22900 {26, mips.REGSP, "SP"}, 22901 {27, mips.REGG, "g"}, 22902 {28, mips.REG_R31, "R31"}, 22903 {29, mips.REG_F0, "F0"}, 22904 {30, mips.REG_F2, "F2"}, 22905 {31, mips.REG_F4, "F4"}, 22906 {32, mips.REG_F6, "F6"}, 22907 {33, mips.REG_F8, "F8"}, 22908 {34, mips.REG_F10, "F10"}, 22909 {35, mips.REG_F12, "F12"}, 22910 {36, mips.REG_F14, "F14"}, 22911 {37, mips.REG_F16, "F16"}, 22912 {38, mips.REG_F18, "F18"}, 22913 {39, mips.REG_F20, "F20"}, 22914 {40, mips.REG_F22, "F22"}, 22915 {41, mips.REG_F24, "F24"}, 22916 {42, mips.REG_F26, "F26"}, 22917 {43, mips.REG_F28, "F28"}, 22918 {44, mips.REG_F30, "F30"}, 22919 {45, mips.REG_HI, "HI"}, 22920 {46, mips.REG_LO, "LO"}, 22921 {47, 0, "SB"}, 22922 } 22923 var gpRegMaskMIPS = regMask(335544318) 22924 var fpRegMaskMIPS = regMask(35183835217920) 22925 var specialRegMaskMIPS = regMask(105553116266496) 22926 var framepointerRegMIPS = int8(-1) 22927 var linkRegMIPS = int8(28) 22928 var registersMIPS64 = [...]Register{ 22929 {0, mips.REG_R0, "R0"}, 22930 {1, mips.REG_R1, "R1"}, 22931 {2, mips.REG_R2, "R2"}, 22932 {3, mips.REG_R3, "R3"}, 22933 {4, mips.REG_R4, "R4"}, 22934 {5, mips.REG_R5, "R5"}, 22935 {6, mips.REG_R6, "R6"}, 22936 {7, mips.REG_R7, "R7"}, 22937 {8, mips.REG_R8, "R8"}, 22938 {9, mips.REG_R9, "R9"}, 22939 {10, mips.REG_R10, "R10"}, 22940 {11, mips.REG_R11, "R11"}, 22941 {12, mips.REG_R12, "R12"}, 22942 {13, mips.REG_R13, "R13"}, 22943 {14, mips.REG_R14, "R14"}, 22944 {15, mips.REG_R15, "R15"}, 22945 {16, mips.REG_R16, "R16"}, 22946 {17, mips.REG_R17, "R17"}, 22947 {18, mips.REG_R18, "R18"}, 22948 {19, mips.REG_R19, "R19"}, 22949 {20, mips.REG_R20, "R20"}, 22950 {21, mips.REG_R21, "R21"}, 22951 {22, mips.REG_R22, "R22"}, 22952 {23, mips.REG_R24, "R24"}, 22953 {24, mips.REG_R25, "R25"}, 22954 {25, mips.REGSP, "SP"}, 22955 {26, mips.REGG, "g"}, 22956 {27, mips.REG_R31, "R31"}, 22957 {28, mips.REG_F0, "F0"}, 22958 {29, mips.REG_F1, "F1"}, 22959 {30, mips.REG_F2, "F2"}, 22960 {31, mips.REG_F3, "F3"}, 22961 {32, mips.REG_F4, "F4"}, 22962 {33, mips.REG_F5, "F5"}, 22963 {34, mips.REG_F6, "F6"}, 22964 {35, mips.REG_F7, "F7"}, 22965 {36, mips.REG_F8, "F8"}, 22966 {37, mips.REG_F9, "F9"}, 22967 {38, mips.REG_F10, "F10"}, 22968 {39, mips.REG_F11, "F11"}, 22969 {40, mips.REG_F12, "F12"}, 22970 {41, mips.REG_F13, "F13"}, 22971 {42, mips.REG_F14, "F14"}, 22972 {43, mips.REG_F15, "F15"}, 22973 {44, mips.REG_F16, "F16"}, 22974 {45, mips.REG_F17, "F17"}, 22975 {46, mips.REG_F18, "F18"}, 22976 {47, mips.REG_F19, "F19"}, 22977 {48, mips.REG_F20, "F20"}, 22978 {49, mips.REG_F21, "F21"}, 22979 {50, mips.REG_F22, "F22"}, 22980 {51, mips.REG_F23, "F23"}, 22981 {52, mips.REG_F24, "F24"}, 22982 {53, mips.REG_F25, "F25"}, 22983 {54, mips.REG_F26, "F26"}, 22984 {55, mips.REG_F27, "F27"}, 22985 {56, mips.REG_F28, "F28"}, 22986 {57, mips.REG_F29, "F29"}, 22987 {58, mips.REG_F30, "F30"}, 22988 {59, mips.REG_F31, "F31"}, 22989 {60, mips.REG_HI, "HI"}, 22990 {61, mips.REG_LO, "LO"}, 22991 {62, 0, "SB"}, 22992 } 22993 var gpRegMaskMIPS64 = regMask(167772158) 22994 var fpRegMaskMIPS64 = regMask(1152921504338411520) 22995 var specialRegMaskMIPS64 = regMask(3458764513820540928) 22996 var framepointerRegMIPS64 = int8(-1) 22997 var linkRegMIPS64 = int8(27) 22998 var registersPPC64 = [...]Register{ 22999 {0, ppc64.REG_R0, "R0"}, 23000 {1, ppc64.REGSP, "SP"}, 23001 {2, 0, "SB"}, 23002 {3, ppc64.REG_R3, "R3"}, 23003 {4, ppc64.REG_R4, "R4"}, 23004 {5, ppc64.REG_R5, "R5"}, 23005 {6, ppc64.REG_R6, "R6"}, 23006 {7, ppc64.REG_R7, "R7"}, 23007 {8, ppc64.REG_R8, "R8"}, 23008 {9, ppc64.REG_R9, "R9"}, 23009 {10, ppc64.REG_R10, "R10"}, 23010 {11, ppc64.REG_R11, "R11"}, 23011 {12, ppc64.REG_R12, "R12"}, 23012 {13, ppc64.REG_R13, "R13"}, 23013 {14, ppc64.REG_R14, "R14"}, 23014 {15, ppc64.REG_R15, "R15"}, 23015 {16, ppc64.REG_R16, "R16"}, 23016 {17, ppc64.REG_R17, "R17"}, 23017 {18, ppc64.REG_R18, "R18"}, 23018 {19, ppc64.REG_R19, "R19"}, 23019 {20, ppc64.REG_R20, "R20"}, 23020 {21, ppc64.REG_R21, "R21"}, 23021 {22, ppc64.REG_R22, "R22"}, 23022 {23, ppc64.REG_R23, "R23"}, 23023 {24, ppc64.REG_R24, "R24"}, 23024 {25, ppc64.REG_R25, "R25"}, 23025 {26, ppc64.REG_R26, "R26"}, 23026 {27, ppc64.REG_R27, "R27"}, 23027 {28, ppc64.REG_R28, "R28"}, 23028 {29, ppc64.REG_R29, "R29"}, 23029 {30, ppc64.REGG, "g"}, 23030 {31, ppc64.REG_R31, "R31"}, 23031 {32, ppc64.REG_F0, "F0"}, 23032 {33, ppc64.REG_F1, "F1"}, 23033 {34, ppc64.REG_F2, "F2"}, 23034 {35, ppc64.REG_F3, "F3"}, 23035 {36, ppc64.REG_F4, "F4"}, 23036 {37, ppc64.REG_F5, "F5"}, 23037 {38, ppc64.REG_F6, "F6"}, 23038 {39, ppc64.REG_F7, "F7"}, 23039 {40, ppc64.REG_F8, "F8"}, 23040 {41, ppc64.REG_F9, "F9"}, 23041 {42, ppc64.REG_F10, "F10"}, 23042 {43, ppc64.REG_F11, "F11"}, 23043 {44, ppc64.REG_F12, "F12"}, 23044 {45, ppc64.REG_F13, "F13"}, 23045 {46, ppc64.REG_F14, "F14"}, 23046 {47, ppc64.REG_F15, "F15"}, 23047 {48, ppc64.REG_F16, "F16"}, 23048 {49, ppc64.REG_F17, "F17"}, 23049 {50, ppc64.REG_F18, "F18"}, 23050 {51, ppc64.REG_F19, "F19"}, 23051 {52, ppc64.REG_F20, "F20"}, 23052 {53, ppc64.REG_F21, "F21"}, 23053 {54, ppc64.REG_F22, "F22"}, 23054 {55, ppc64.REG_F23, "F23"}, 23055 {56, ppc64.REG_F24, "F24"}, 23056 {57, ppc64.REG_F25, "F25"}, 23057 {58, ppc64.REG_F26, "F26"}, 23058 {59, ppc64.REG_F27, "F27"}, 23059 {60, ppc64.REG_F28, "F28"}, 23060 {61, ppc64.REG_F29, "F29"}, 23061 {62, ppc64.REG_F30, "F30"}, 23062 {63, ppc64.REG_F31, "F31"}, 23063 } 23064 var gpRegMaskPPC64 = regMask(1073733624) 23065 var fpRegMaskPPC64 = regMask(576460743713488896) 23066 var specialRegMaskPPC64 = regMask(0) 23067 var framepointerRegPPC64 = int8(1) 23068 var linkRegPPC64 = int8(-1) 23069 var registersS390X = [...]Register{ 23070 {0, s390x.REG_R0, "R0"}, 23071 {1, s390x.REG_R1, "R1"}, 23072 {2, s390x.REG_R2, "R2"}, 23073 {3, s390x.REG_R3, "R3"}, 23074 {4, s390x.REG_R4, "R4"}, 23075 {5, s390x.REG_R5, "R5"}, 23076 {6, s390x.REG_R6, "R6"}, 23077 {7, s390x.REG_R7, "R7"}, 23078 {8, s390x.REG_R8, "R8"}, 23079 {9, s390x.REG_R9, "R9"}, 23080 {10, s390x.REG_R10, "R10"}, 23081 {11, s390x.REG_R11, "R11"}, 23082 {12, s390x.REG_R12, "R12"}, 23083 {13, s390x.REGG, "g"}, 23084 {14, s390x.REG_R14, "R14"}, 23085 {15, s390x.REGSP, "SP"}, 23086 {16, s390x.REG_F0, "F0"}, 23087 {17, s390x.REG_F1, "F1"}, 23088 {18, s390x.REG_F2, "F2"}, 23089 {19, s390x.REG_F3, "F3"}, 23090 {20, s390x.REG_F4, "F4"}, 23091 {21, s390x.REG_F5, "F5"}, 23092 {22, s390x.REG_F6, "F6"}, 23093 {23, s390x.REG_F7, "F7"}, 23094 {24, s390x.REG_F8, "F8"}, 23095 {25, s390x.REG_F9, "F9"}, 23096 {26, s390x.REG_F10, "F10"}, 23097 {27, s390x.REG_F11, "F11"}, 23098 {28, s390x.REG_F12, "F12"}, 23099 {29, s390x.REG_F13, "F13"}, 23100 {30, s390x.REG_F14, "F14"}, 23101 {31, s390x.REG_F15, "F15"}, 23102 {32, 0, "SB"}, 23103 } 23104 var gpRegMaskS390X = regMask(21503) 23105 var fpRegMaskS390X = regMask(4294901760) 23106 var specialRegMaskS390X = regMask(0) 23107 var framepointerRegS390X = int8(-1) 23108 var linkRegS390X = int8(14)