github.com/zebozhuang/go@v0.0.0-20200207033046-f8a98f6f5c5d/src/cmd/internal/obj/s390x/asmz.go (about) 1 // Based on cmd/internal/obj/ppc64/asm9.go. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package s390x 31 32 import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "log" 36 "math" 37 "sort" 38 ) 39 40 // ctxtz holds state while assembling a single function. 41 // Each function gets a fresh ctxtz. 42 // This allows for multiple functions to be safely concurrently assembled. 43 type ctxtz struct { 44 ctxt *obj.Link 45 newprog obj.ProgAlloc 46 cursym *obj.LSym 47 autosize int32 48 instoffset int64 49 pc int64 50 } 51 52 // instruction layout. 53 const ( 54 funcAlign = 16 55 ) 56 57 type Optab struct { 58 as obj.As // opcode 59 a1 uint8 // From 60 a2 uint8 // Reg 61 a3 uint8 // From3 62 a4 uint8 // To 63 type_ int8 64 param int16 // REGSP for auto variables 65 } 66 67 var optab = []Optab{ 68 // instruction, From, Reg, From3, To, type, param 69 Optab{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0}, 70 Optab{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0}, 71 72 // move register 73 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 74 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 75 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 76 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 77 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 78 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 1, 0}, 79 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 80 81 // load constant 82 Optab{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 83 Optab{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 84 Optab{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 85 Optab{AMOVD, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 86 Optab{AMOVW, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 87 Optab{AMOVWZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 88 Optab{AMOVB, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 89 Optab{AMOVBZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 90 91 // store constant 92 Optab{AMOVD, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 93 Optab{AMOVD, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 94 Optab{AMOVW, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 95 Optab{AMOVW, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 96 Optab{AMOVWZ, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 97 Optab{AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 98 Optab{AMOVB, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 99 Optab{AMOVB, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 100 Optab{AMOVBZ, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 101 Optab{AMOVBZ, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 102 Optab{AMOVD, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 103 Optab{AMOVD, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 104 Optab{AMOVW, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 105 Optab{AMOVW, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 106 Optab{AMOVWZ, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 107 Optab{AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 108 Optab{AMOVB, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 109 Optab{AMOVB, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 110 Optab{AMOVBZ, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 111 Optab{AMOVBZ, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 112 113 // store 114 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 115 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 116 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 117 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 118 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 119 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 120 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 121 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 122 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 123 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 124 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 125 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 126 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 127 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 128 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 129 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 130 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 131 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 132 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 133 134 // load 135 Optab{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 136 Optab{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 137 Optab{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 138 Optab{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 139 Optab{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 140 Optab{AMOVDBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 141 Optab{AMOVHBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 142 Optab{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 143 Optab{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 144 Optab{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 145 Optab{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 146 Optab{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 147 Optab{AMOVDBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 148 Optab{AMOVHBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 149 Optab{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 150 Optab{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 151 Optab{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 152 Optab{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 153 Optab{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 154 155 // interlocked load and op 156 Optab{ALAAG, C_REG, C_REG, C_NONE, C_LOREG, 99, 0}, 157 158 // integer arithmetic 159 Optab{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 160 Optab{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 161 Optab{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 0}, 162 Optab{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 0}, 163 Optab{AADD, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 164 Optab{AADD, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 165 Optab{ASUB, C_LCON, C_REG, C_NONE, C_REG, 21, 0}, 166 Optab{ASUB, C_LCON, C_NONE, C_NONE, C_REG, 21, 0}, 167 Optab{ASUB, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 168 Optab{ASUB, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 169 Optab{AMULHD, C_REG, C_NONE, C_NONE, C_REG, 4, 0}, 170 Optab{AMULHD, C_REG, C_REG, C_NONE, C_REG, 4, 0}, 171 Optab{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 172 Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 173 Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0}, 174 Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0}, 175 Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0}, 176 Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0}, 177 178 // integer logical 179 Optab{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 180 Optab{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 181 Optab{AAND, C_LCON, C_NONE, C_NONE, C_REG, 23, 0}, 182 Optab{AAND, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 183 Optab{AAND, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 184 Optab{AANDW, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 185 Optab{AANDW, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 186 Optab{AANDW, C_LCON, C_NONE, C_NONE, C_REG, 24, 0}, 187 Optab{AANDW, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 188 Optab{AANDW, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 189 Optab{ASLD, C_REG, C_NONE, C_NONE, C_REG, 7, 0}, 190 Optab{ASLD, C_REG, C_REG, C_NONE, C_REG, 7, 0}, 191 Optab{ASLD, C_SCON, C_REG, C_NONE, C_REG, 7, 0}, 192 Optab{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 7, 0}, 193 194 // compare and swap 195 Optab{ACSG, C_REG, C_REG, C_NONE, C_SOREG, 79, 0}, 196 197 // floating point 198 Optab{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 199 Optab{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 0}, 200 Optab{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 0}, 201 Optab{AFMADD, C_FREG, C_FREG, C_NONE, C_FREG, 34, 0}, 202 Optab{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 203 Optab{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, REGSP}, 204 Optab{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 0}, 205 Optab{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 0}, 206 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 207 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 0}, 208 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 0}, 209 Optab{AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 67, 0}, 210 Optab{ALDGR, C_REG, C_NONE, C_NONE, C_FREG, 81, 0}, 211 Optab{ALGDR, C_FREG, C_NONE, C_NONE, C_REG, 81, 0}, 212 Optab{ACEFBRA, C_REG, C_NONE, C_NONE, C_FREG, 82, 0}, 213 Optab{ACFEBRA, C_FREG, C_NONE, C_NONE, C_REG, 83, 0}, 214 Optab{AFIEBR, C_SCON, C_FREG, C_NONE, C_FREG, 48, 0}, 215 216 // load symbol address (plus offset) 217 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_REG, 19, 0}, 218 Optab{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 93, 0}, 219 Optab{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 94, 0}, 220 Optab{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 95, 0}, 221 222 // system call 223 Optab{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 0}, 224 Optab{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 0}, 225 226 // branch 227 Optab{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 0}, 228 Optab{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 0}, 229 Optab{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 16, 0}, 230 Optab{ABR, C_NONE, C_NONE, C_NONE, C_REG, 18, 0}, 231 Optab{ABR, C_REG, C_NONE, C_NONE, C_REG, 18, 0}, 232 Optab{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 233 Optab{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 234 Optab{ACMPBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 235 Optab{ACMPBEQ, C_REG, C_NONE, C_ADDCON, C_SBRA, 90, 0}, 236 Optab{ACMPBEQ, C_REG, C_NONE, C_SCON, C_SBRA, 90, 0}, 237 Optab{ACMPUBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 238 Optab{ACMPUBEQ, C_REG, C_NONE, C_ANDCON, C_SBRA, 90, 0}, 239 240 // move on condition 241 Optab{AMOVDEQ, C_REG, C_NONE, C_NONE, C_REG, 17, 0}, 242 243 // find leftmost one 244 Optab{AFLOGR, C_REG, C_NONE, C_NONE, C_REG, 8, 0}, 245 246 // compare 247 Optab{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 248 Optab{ACMP, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 249 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 250 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 251 Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0}, 252 Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0}, 253 254 // 32-bit access registers 255 Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 256 Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 257 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 258 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 259 260 // macros 261 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LOREG, 96, 0}, 262 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LAUTO, 96, REGSP}, 263 264 // load/store multiple 265 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LOREG, 97, 0}, 266 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LAUTO, 97, REGSP}, 267 Optab{ALMG, C_LOREG, C_REG, C_NONE, C_REG, 98, 0}, 268 Optab{ALMG, C_LAUTO, C_REG, C_NONE, C_REG, 98, REGSP}, 269 270 // bytes 271 Optab{ABYTE, C_SCON, C_NONE, C_NONE, C_NONE, 40, 0}, 272 Optab{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 0}, 273 Optab{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 0}, 274 Optab{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 0}, 275 276 // fast synchronization 277 Optab{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 80, 0}, 278 279 // store clock 280 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SAUTO, 88, REGSP}, 281 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SOREG, 88, 0}, 282 283 // storage and storage 284 Optab{AMVC, C_SCON, C_NONE, C_LOREG, C_LOREG, 84, 0}, 285 Optab{AMVC, C_SCON, C_NONE, C_LOREG, C_LAUTO, 84, REGSP}, 286 Optab{AMVC, C_SCON, C_NONE, C_LAUTO, C_LAUTO, 84, REGSP}, 287 288 // address 289 Optab{ALARL, C_LCON, C_NONE, C_NONE, C_REG, 85, 0}, 290 Optab{ALARL, C_SYMADDR, C_NONE, C_NONE, C_REG, 85, 0}, 291 Optab{ALA, C_SOREG, C_NONE, C_NONE, C_REG, 86, 0}, 292 Optab{ALA, C_SAUTO, C_NONE, C_NONE, C_REG, 86, REGSP}, 293 Optab{AEXRL, C_SYMADDR, C_NONE, C_NONE, C_REG, 87, 0}, 294 295 // misc 296 Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 0}, 297 Optab{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0}, 298 Optab{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0}, 299 Optab{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0}, 300 Optab{obj.ANOP, C_SAUTO, C_NONE, C_NONE, C_NONE, 0, 0}, 301 302 // vector instructions 303 304 // VRX store 305 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SOREG, 100, 0}, 306 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SAUTO, 100, REGSP}, 307 Optab{AVSTEG, C_SCON, C_VREG, C_NONE, C_SOREG, 100, 0}, 308 Optab{AVSTEG, C_SCON, C_VREG, C_NONE, C_SAUTO, 100, REGSP}, 309 310 // VRX load 311 Optab{AVL, C_SOREG, C_NONE, C_NONE, C_VREG, 101, 0}, 312 Optab{AVL, C_SAUTO, C_NONE, C_NONE, C_VREG, 101, REGSP}, 313 Optab{AVLEG, C_SCON, C_NONE, C_SOREG, C_VREG, 101, 0}, 314 Optab{AVLEG, C_SCON, C_NONE, C_SAUTO, C_VREG, 101, REGSP}, 315 316 // VRV scatter 317 Optab{AVSCEG, C_SCON, C_VREG, C_NONE, C_SOREG, 102, 0}, 318 Optab{AVSCEG, C_SCON, C_VREG, C_NONE, C_SAUTO, 102, REGSP}, 319 320 // VRV gather 321 Optab{AVGEG, C_SCON, C_NONE, C_SOREG, C_VREG, 103, 0}, 322 Optab{AVGEG, C_SCON, C_NONE, C_SAUTO, C_VREG, 103, REGSP}, 323 324 // VRS element shift/rotate and load gr to/from vr element 325 Optab{AVESLG, C_SCON, C_VREG, C_NONE, C_VREG, 104, 0}, 326 Optab{AVESLG, C_REG, C_VREG, C_NONE, C_VREG, 104, 0}, 327 Optab{AVESLG, C_SCON, C_NONE, C_NONE, C_VREG, 104, 0}, 328 Optab{AVESLG, C_REG, C_NONE, C_NONE, C_VREG, 104, 0}, 329 Optab{AVLGVG, C_SCON, C_VREG, C_NONE, C_REG, 104, 0}, 330 Optab{AVLGVG, C_REG, C_VREG, C_NONE, C_REG, 104, 0}, 331 Optab{AVLVGG, C_SCON, C_REG, C_NONE, C_VREG, 104, 0}, 332 Optab{AVLVGG, C_REG, C_REG, C_NONE, C_VREG, 104, 0}, 333 334 // VRS store multiple 335 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SOREG, 105, 0}, 336 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SAUTO, 105, REGSP}, 337 338 // VRS load multiple 339 Optab{AVLM, C_SOREG, C_VREG, C_NONE, C_VREG, 106, 0}, 340 Optab{AVLM, C_SAUTO, C_VREG, C_NONE, C_VREG, 106, REGSP}, 341 342 // VRS store with length 343 Optab{AVSTL, C_REG, C_VREG, C_NONE, C_SOREG, 107, 0}, 344 Optab{AVSTL, C_REG, C_VREG, C_NONE, C_SAUTO, 107, REGSP}, 345 346 // VRS load with length 347 Optab{AVLL, C_REG, C_NONE, C_SOREG, C_VREG, 108, 0}, 348 Optab{AVLL, C_REG, C_NONE, C_SAUTO, C_VREG, 108, REGSP}, 349 350 // VRI-a 351 Optab{AVGBM, C_ANDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 352 Optab{AVZERO, C_NONE, C_NONE, C_NONE, C_VREG, 109, 0}, 353 Optab{AVREPIG, C_ADDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 354 Optab{AVREPIG, C_SCON, C_NONE, C_NONE, C_VREG, 109, 0}, 355 Optab{AVLEIG, C_SCON, C_NONE, C_ADDCON, C_VREG, 109, 0}, 356 Optab{AVLEIG, C_SCON, C_NONE, C_SCON, C_VREG, 109, 0}, 357 358 // VRI-b generate mask 359 Optab{AVGMG, C_SCON, C_NONE, C_SCON, C_VREG, 110, 0}, 360 361 // VRI-c replicate 362 Optab{AVREPG, C_UCON, C_VREG, C_NONE, C_VREG, 111, 0}, 363 364 // VRI-d element rotate and insert under mask and 365 // shift left double by byte 366 Optab{AVERIMG, C_SCON, C_VREG, C_VREG, C_VREG, 112, 0}, 367 Optab{AVSLDB, C_SCON, C_VREG, C_VREG, C_VREG, 112, 0}, 368 369 // VRI-d fp test data class immediate 370 Optab{AVFTCIDB, C_SCON, C_VREG, C_NONE, C_VREG, 113, 0}, 371 372 // VRR-a load reg 373 Optab{AVLR, C_VREG, C_NONE, C_NONE, C_VREG, 114, 0}, 374 375 // VRR-a compare 376 Optab{AVECG, C_VREG, C_NONE, C_NONE, C_VREG, 115, 0}, 377 378 // VRR-b 379 Optab{AVCEQG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 380 Optab{AVFAEF, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 381 Optab{AVPKSG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 382 383 // VRR-c 384 Optab{AVAQ, C_VREG, C_VREG, C_NONE, C_VREG, 118, 0}, 385 Optab{AVAQ, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 386 Optab{AVNOT, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 387 Optab{AVPDI, C_SCON, C_VREG, C_VREG, C_VREG, 123, 0}, 388 389 // VRR-c shifts 390 Optab{AVERLLVG, C_VREG, C_VREG, C_NONE, C_VREG, 119, 0}, 391 Optab{AVERLLVG, C_VREG, C_NONE, C_NONE, C_VREG, 119, 0}, 392 393 // VRR-d 394 // 2 3 1 4 395 Optab{AVACQ, C_VREG, C_VREG, C_VREG, C_VREG, 120, 0}, 396 397 // VRR-e 398 Optab{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 121, 0}, 399 400 // VRR-f 401 Optab{AVLVGP, C_REG, C_REG, C_NONE, C_VREG, 122, 0}, 402 } 403 404 var oprange [ALAST & obj.AMask][]Optab 405 406 var xcmp [C_NCLASS][C_NCLASS]bool 407 408 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 409 p := cursym.Func.Text 410 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 411 return 412 } 413 414 if oprange[AORW&obj.AMask] == nil { 415 ctxt.Diag("s390x ops not initialized, call s390x.buildop first") 416 } 417 418 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 419 420 buffer := make([]byte, 0) 421 changed := true 422 loop := 0 423 for changed { 424 if loop > 10 { 425 c.ctxt.Diag("stuck in spanz loop") 426 break 427 } 428 changed = false 429 buffer = buffer[:0] 430 c.cursym.R = make([]obj.Reloc, 0) 431 for p := c.cursym.Func.Text; p != nil; p = p.Link { 432 pc := int64(len(buffer)) 433 if pc != p.Pc { 434 changed = true 435 } 436 p.Pc = pc 437 c.pc = p.Pc 438 c.asmout(p, &buffer) 439 if pc == int64(len(buffer)) { 440 switch p.As { 441 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 442 // ok 443 default: 444 c.ctxt.Diag("zero-width instruction\n%v", p) 445 } 446 } 447 } 448 loop++ 449 } 450 451 c.cursym.Size = int64(len(buffer)) 452 if c.cursym.Size%funcAlign != 0 { 453 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign) 454 } 455 c.cursym.Grow(c.cursym.Size) 456 copy(c.cursym.P, buffer) 457 } 458 459 func isint32(v int64) bool { 460 return int64(int32(v)) == v 461 } 462 463 func isuint32(v uint64) bool { 464 return uint64(uint32(v)) == v 465 } 466 467 func (c *ctxtz) aclass(a *obj.Addr) int { 468 switch a.Type { 469 case obj.TYPE_NONE: 470 return C_NONE 471 472 case obj.TYPE_REG: 473 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 474 return C_REG 475 } 476 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 477 return C_FREG 478 } 479 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 480 return C_AREG 481 } 482 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 483 return C_VREG 484 } 485 return C_GOK 486 487 case obj.TYPE_MEM: 488 switch a.Name { 489 case obj.NAME_EXTERN, 490 obj.NAME_STATIC: 491 if a.Sym == nil { 492 // must have a symbol 493 break 494 } 495 c.instoffset = a.Offset 496 if a.Sym.Type == objabi.STLSBSS { 497 if c.ctxt.Flag_shared { 498 return C_TLS_IE // initial exec model 499 } 500 return C_TLS_LE // local exec model 501 } 502 return C_ADDR 503 504 case obj.NAME_GOTREF: 505 return C_GOTADDR 506 507 case obj.NAME_AUTO: 508 if a.Reg == REGSP { 509 // unset base register for better printing, since 510 // a.Offset is still relative to pseudo-SP. 511 a.Reg = obj.REG_NONE 512 } 513 c.instoffset = int64(c.autosize) + a.Offset 514 if c.instoffset >= -BIG && c.instoffset < BIG { 515 return C_SAUTO 516 } 517 return C_LAUTO 518 519 case obj.NAME_PARAM: 520 if a.Reg == REGSP { 521 // unset base register for better printing, since 522 // a.Offset is still relative to pseudo-FP. 523 a.Reg = obj.REG_NONE 524 } 525 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 526 if c.instoffset >= -BIG && c.instoffset < BIG { 527 return C_SAUTO 528 } 529 return C_LAUTO 530 531 case obj.NAME_NONE: 532 c.instoffset = a.Offset 533 if c.instoffset == 0 { 534 return C_ZOREG 535 } 536 if c.instoffset >= -BIG && c.instoffset < BIG { 537 return C_SOREG 538 } 539 return C_LOREG 540 } 541 542 return C_GOK 543 544 case obj.TYPE_TEXTSIZE: 545 return C_TEXTSIZE 546 547 case obj.TYPE_FCONST: 548 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 549 return C_ZCON 550 } 551 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val) 552 553 case obj.TYPE_CONST, 554 obj.TYPE_ADDR: 555 switch a.Name { 556 case obj.NAME_NONE: 557 c.instoffset = a.Offset 558 if a.Reg != 0 { 559 if -BIG <= c.instoffset && c.instoffset <= BIG { 560 return C_SACON 561 } 562 if isint32(c.instoffset) { 563 return C_LACON 564 } 565 return C_DACON 566 } 567 goto consize 568 569 case obj.NAME_EXTERN, 570 obj.NAME_STATIC: 571 s := a.Sym 572 if s == nil { 573 break 574 } 575 c.instoffset = a.Offset 576 577 return C_SYMADDR 578 579 case obj.NAME_AUTO: 580 if a.Reg == REGSP { 581 // unset base register for better printing, since 582 // a.Offset is still relative to pseudo-SP. 583 a.Reg = obj.REG_NONE 584 } 585 c.instoffset = int64(c.autosize) + a.Offset 586 if c.instoffset >= -BIG && c.instoffset < BIG { 587 return C_SACON 588 } 589 return C_LACON 590 591 case obj.NAME_PARAM: 592 if a.Reg == REGSP { 593 // unset base register for better printing, since 594 // a.Offset is still relative to pseudo-FP. 595 a.Reg = obj.REG_NONE 596 } 597 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 598 if c.instoffset >= -BIG && c.instoffset < BIG { 599 return C_SACON 600 } 601 return C_LACON 602 } 603 604 return C_GOK 605 606 consize: 607 if c.instoffset == 0 { 608 return C_ZCON 609 } 610 if c.instoffset >= 0 { 611 if c.instoffset <= 0x7fff { 612 return C_SCON 613 } 614 if c.instoffset <= 0xffff { 615 return C_ANDCON 616 } 617 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 618 return C_UCON 619 } 620 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 621 return C_LCON 622 } 623 return C_DCON 624 } 625 626 if c.instoffset >= -0x8000 { 627 return C_ADDCON 628 } 629 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 630 return C_UCON 631 } 632 if isint32(c.instoffset) { 633 return C_LCON 634 } 635 return C_DCON 636 637 case obj.TYPE_BRANCH: 638 return C_SBRA 639 } 640 641 return C_GOK 642 } 643 644 func (c *ctxtz) oplook(p *obj.Prog) *Optab { 645 a1 := int(p.Optab) 646 if a1 != 0 { 647 return &optab[a1-1] 648 } 649 a1 = int(p.From.Class) 650 if a1 == 0 { 651 a1 = c.aclass(&p.From) + 1 652 p.From.Class = int8(a1) 653 } 654 655 a1-- 656 a3 := C_NONE + 1 657 if p.From3 != nil { 658 a3 = int(p.From3.Class) 659 if a3 == 0 { 660 a3 = c.aclass(p.From3) + 1 661 p.From3.Class = int8(a3) 662 } 663 } 664 665 a3-- 666 a4 := int(p.To.Class) 667 if a4 == 0 { 668 a4 = c.aclass(&p.To) + 1 669 p.To.Class = int8(a4) 670 } 671 672 a4-- 673 a2 := C_NONE 674 if p.Reg != 0 { 675 if REG_R0 <= p.Reg && p.Reg <= REG_R15 { 676 a2 = C_REG 677 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 678 a2 = C_VREG 679 } else if REG_F0 <= p.Reg && p.Reg <= REG_F15 { 680 a2 = C_FREG 681 } else if REG_AR0 <= p.Reg && p.Reg <= REG_AR15 { 682 a2 = C_AREG 683 } 684 } 685 686 ops := oprange[p.As&obj.AMask] 687 c1 := &xcmp[a1] 688 c2 := &xcmp[a2] 689 c3 := &xcmp[a3] 690 c4 := &xcmp[a4] 691 for i := range ops { 692 op := &ops[i] 693 if (int(op.a2) == a2 || c2[op.a2]) && c4[op.a4] && c1[op.a1] && c3[op.a3] { 694 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 695 return op 696 } 697 } 698 699 // cannot find a case; abort 700 c.ctxt.Diag("illegal combination %v %v %v %v %v\n", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 701 c.ctxt.Diag("prog: %v\n", p) 702 return nil 703 } 704 705 func cmp(a int, b int) bool { 706 if a == b { 707 return true 708 } 709 switch a { 710 case C_DCON: 711 if b == C_LCON { 712 return true 713 } 714 fallthrough 715 case C_LCON: 716 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 717 return true 718 } 719 720 case C_ADDCON: 721 if b == C_ZCON || b == C_SCON { 722 return true 723 } 724 725 case C_ANDCON: 726 if b == C_ZCON || b == C_SCON { 727 return true 728 } 729 730 case C_UCON: 731 if b == C_ZCON || b == C_SCON { 732 return true 733 } 734 735 case C_SCON: 736 if b == C_ZCON { 737 return true 738 } 739 740 case C_LACON: 741 if b == C_SACON { 742 return true 743 } 744 745 case C_LBRA: 746 if b == C_SBRA { 747 return true 748 } 749 750 case C_LAUTO: 751 if b == C_SAUTO { 752 return true 753 } 754 755 case C_LOREG: 756 if b == C_ZOREG || b == C_SOREG { 757 return true 758 } 759 760 case C_SOREG: 761 if b == C_ZOREG { 762 return true 763 } 764 765 case C_ANY: 766 return true 767 } 768 769 return false 770 } 771 772 type ocmp []Optab 773 774 func (x ocmp) Len() int { 775 return len(x) 776 } 777 778 func (x ocmp) Swap(i, j int) { 779 x[i], x[j] = x[j], x[i] 780 } 781 782 func (x ocmp) Less(i, j int) bool { 783 p1 := &x[i] 784 p2 := &x[j] 785 n := int(p1.as) - int(p2.as) 786 if n != 0 { 787 return n < 0 788 } 789 n = int(p1.a1) - int(p2.a1) 790 if n != 0 { 791 return n < 0 792 } 793 n = int(p1.a2) - int(p2.a2) 794 if n != 0 { 795 return n < 0 796 } 797 n = int(p1.a3) - int(p2.a3) 798 if n != 0 { 799 return n < 0 800 } 801 n = int(p1.a4) - int(p2.a4) 802 if n != 0 { 803 return n < 0 804 } 805 return false 806 } 807 func opset(a, b obj.As) { 808 oprange[a&obj.AMask] = oprange[b&obj.AMask] 809 } 810 811 func buildop(ctxt *obj.Link) { 812 if oprange[AORW&obj.AMask] != nil { 813 // Already initialized; stop now. 814 // This happens in the cmd/asm tests, 815 // each of which re-initializes the arch. 816 return 817 } 818 819 for i := 0; i < C_NCLASS; i++ { 820 for n := 0; n < C_NCLASS; n++ { 821 if cmp(n, i) { 822 xcmp[i][n] = true 823 } 824 } 825 } 826 sort.Sort(ocmp(optab)) 827 for i := 0; i < len(optab); i++ { 828 r := optab[i].as 829 start := i 830 for ; i+1 < len(optab); i++ { 831 if optab[i+1].as != r { 832 break 833 } 834 } 835 oprange[r&obj.AMask] = optab[start : i+1] 836 837 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 838 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 839 switch r { 840 case AADD: 841 opset(AADDC, r) 842 opset(AADDW, r) 843 opset(AMULLD, r) 844 opset(AMULLW, r) 845 case ADIVW: 846 opset(AADDE, r) 847 opset(ADIVD, r) 848 opset(ADIVDU, r) 849 opset(ADIVWU, r) 850 opset(AMODD, r) 851 opset(AMODDU, r) 852 opset(AMODW, r) 853 opset(AMODWU, r) 854 case AMULHD: 855 opset(AMULHDU, r) 856 case AMOVBZ: 857 opset(AMOVH, r) 858 opset(AMOVHZ, r) 859 case ALA: 860 opset(ALAY, r) 861 case AMVC: 862 opset(ACLC, r) 863 opset(AXC, r) 864 opset(AOC, r) 865 opset(ANC, r) 866 case ASTCK: 867 opset(ASTCKC, r) 868 opset(ASTCKE, r) 869 opset(ASTCKF, r) 870 case ALAAG: 871 opset(ALAA, r) 872 opset(ALAAL, r) 873 opset(ALAALG, r) 874 opset(ALAN, r) 875 opset(ALANG, r) 876 opset(ALAX, r) 877 opset(ALAXG, r) 878 opset(ALAO, r) 879 opset(ALAOG, r) 880 case ASTMG: 881 opset(ASTMY, r) 882 case ALMG: 883 opset(ALMY, r) 884 case ABEQ: 885 opset(ABGE, r) 886 opset(ABGT, r) 887 opset(ABLE, r) 888 opset(ABLT, r) 889 opset(ABNE, r) 890 opset(ABVC, r) 891 opset(ABVS, r) 892 opset(ABLEU, r) 893 opset(ABLTU, r) 894 case ABR: 895 opset(ABL, r) 896 case ABC: 897 opset(ABCL, r) 898 case AFABS: 899 opset(AFNABS, r) 900 opset(AFNEG, r) 901 opset(AFNEGS, r) 902 opset(ALEDBR, r) 903 opset(ALDEBR, r) 904 opset(AFSQRT, r) 905 opset(AFSQRTS, r) 906 case AFADD: 907 opset(AFADDS, r) 908 opset(AFDIV, r) 909 opset(AFDIVS, r) 910 opset(AFSUB, r) 911 opset(AFSUBS, r) 912 case AFMADD: 913 opset(AFMADDS, r) 914 opset(AFMSUB, r) 915 opset(AFMSUBS, r) 916 case AFMUL: 917 opset(AFMULS, r) 918 case AFCMPO: 919 opset(AFCMPU, r) 920 opset(ACEBR, r) 921 case AAND: 922 opset(AOR, r) 923 opset(AXOR, r) 924 case AANDW: 925 opset(AORW, r) 926 opset(AXORW, r) 927 case ASLD: 928 opset(ASRD, r) 929 opset(ASLW, r) 930 opset(ASRW, r) 931 opset(ASRAD, r) 932 opset(ASRAW, r) 933 opset(ARLL, r) 934 opset(ARLLG, r) 935 case ACSG: 936 opset(ACS, r) 937 case ASUB: 938 opset(ASUBC, r) 939 opset(ASUBE, r) 940 opset(ASUBW, r) 941 case ANEG: 942 opset(ANEGW, r) 943 case AFMOVD: 944 opset(AFMOVS, r) 945 case AMOVDBR: 946 opset(AMOVWBR, r) 947 case ACMP: 948 opset(ACMPW, r) 949 case ACMPU: 950 opset(ACMPWU, r) 951 case ACEFBRA: 952 opset(ACDFBRA, r) 953 opset(ACEGBRA, r) 954 opset(ACDGBRA, r) 955 opset(ACELFBR, r) 956 opset(ACDLFBR, r) 957 opset(ACELGBR, r) 958 opset(ACDLGBR, r) 959 case ACFEBRA: 960 opset(ACFDBRA, r) 961 opset(ACGEBRA, r) 962 opset(ACGDBRA, r) 963 opset(ACLFEBR, r) 964 opset(ACLFDBR, r) 965 opset(ACLGEBR, r) 966 opset(ACLGDBR, r) 967 case AFIEBR: 968 opset(AFIDBR, r) 969 case ACMPBEQ: 970 opset(ACMPBGE, r) 971 opset(ACMPBGT, r) 972 opset(ACMPBLE, r) 973 opset(ACMPBLT, r) 974 opset(ACMPBNE, r) 975 case ACMPUBEQ: 976 opset(ACMPUBGE, r) 977 opset(ACMPUBGT, r) 978 opset(ACMPUBLE, r) 979 opset(ACMPUBLT, r) 980 opset(ACMPUBNE, r) 981 case AMOVDEQ: 982 opset(AMOVDGE, r) 983 opset(AMOVDGT, r) 984 opset(AMOVDLE, r) 985 opset(AMOVDLT, r) 986 opset(AMOVDNE, r) 987 case AVL: 988 opset(AVLLEZB, r) 989 opset(AVLLEZH, r) 990 opset(AVLLEZF, r) 991 opset(AVLLEZG, r) 992 opset(AVLREPB, r) 993 opset(AVLREPH, r) 994 opset(AVLREPF, r) 995 opset(AVLREPG, r) 996 case AVLEG: 997 opset(AVLBB, r) 998 opset(AVLEB, r) 999 opset(AVLEH, r) 1000 opset(AVLEF, r) 1001 opset(AVLEG, r) 1002 opset(AVLREP, r) 1003 case AVSTEG: 1004 opset(AVSTEB, r) 1005 opset(AVSTEH, r) 1006 opset(AVSTEF, r) 1007 case AVSCEG: 1008 opset(AVSCEF, r) 1009 case AVGEG: 1010 opset(AVGEF, r) 1011 case AVESLG: 1012 opset(AVESLB, r) 1013 opset(AVESLH, r) 1014 opset(AVESLF, r) 1015 opset(AVERLLB, r) 1016 opset(AVERLLH, r) 1017 opset(AVERLLF, r) 1018 opset(AVERLLG, r) 1019 opset(AVESRAB, r) 1020 opset(AVESRAH, r) 1021 opset(AVESRAF, r) 1022 opset(AVESRAG, r) 1023 opset(AVESRLB, r) 1024 opset(AVESRLH, r) 1025 opset(AVESRLF, r) 1026 opset(AVESRLG, r) 1027 case AVLGVG: 1028 opset(AVLGVB, r) 1029 opset(AVLGVH, r) 1030 opset(AVLGVF, r) 1031 case AVLVGG: 1032 opset(AVLVGB, r) 1033 opset(AVLVGH, r) 1034 opset(AVLVGF, r) 1035 case AVZERO: 1036 opset(AVONE, r) 1037 case AVREPIG: 1038 opset(AVREPIB, r) 1039 opset(AVREPIH, r) 1040 opset(AVREPIF, r) 1041 case AVLEIG: 1042 opset(AVLEIB, r) 1043 opset(AVLEIH, r) 1044 opset(AVLEIF, r) 1045 case AVGMG: 1046 opset(AVGMB, r) 1047 opset(AVGMH, r) 1048 opset(AVGMF, r) 1049 case AVREPG: 1050 opset(AVREPB, r) 1051 opset(AVREPH, r) 1052 opset(AVREPF, r) 1053 case AVERIMG: 1054 opset(AVERIMB, r) 1055 opset(AVERIMH, r) 1056 opset(AVERIMF, r) 1057 case AVFTCIDB: 1058 opset(AWFTCIDB, r) 1059 case AVLR: 1060 opset(AVUPHB, r) 1061 opset(AVUPHH, r) 1062 opset(AVUPHF, r) 1063 opset(AVUPLHB, r) 1064 opset(AVUPLHH, r) 1065 opset(AVUPLHF, r) 1066 opset(AVUPLB, r) 1067 opset(AVUPLHW, r) 1068 opset(AVUPLF, r) 1069 opset(AVUPLLB, r) 1070 opset(AVUPLLH, r) 1071 opset(AVUPLLF, r) 1072 opset(AVCLZB, r) 1073 opset(AVCLZH, r) 1074 opset(AVCLZF, r) 1075 opset(AVCLZG, r) 1076 opset(AVCTZB, r) 1077 opset(AVCTZH, r) 1078 opset(AVCTZF, r) 1079 opset(AVCTZG, r) 1080 opset(AVLDEB, r) 1081 opset(AWLDEB, r) 1082 opset(AVFLCDB, r) 1083 opset(AWFLCDB, r) 1084 opset(AVFLNDB, r) 1085 opset(AWFLNDB, r) 1086 opset(AVFLPDB, r) 1087 opset(AWFLPDB, r) 1088 opset(AVFSQDB, r) 1089 opset(AWFSQDB, r) 1090 opset(AVISTRB, r) 1091 opset(AVISTRH, r) 1092 opset(AVISTRF, r) 1093 opset(AVISTRBS, r) 1094 opset(AVISTRHS, r) 1095 opset(AVISTRFS, r) 1096 opset(AVLCB, r) 1097 opset(AVLCH, r) 1098 opset(AVLCF, r) 1099 opset(AVLCG, r) 1100 opset(AVLPB, r) 1101 opset(AVLPH, r) 1102 opset(AVLPF, r) 1103 opset(AVLPG, r) 1104 opset(AVPOPCT, r) 1105 opset(AVSEGB, r) 1106 opset(AVSEGH, r) 1107 opset(AVSEGF, r) 1108 case AVECG: 1109 opset(AVECB, r) 1110 opset(AVECH, r) 1111 opset(AVECF, r) 1112 opset(AVECLB, r) 1113 opset(AVECLH, r) 1114 opset(AVECLF, r) 1115 opset(AVECLG, r) 1116 opset(AWFCDB, r) 1117 opset(AWFKDB, r) 1118 case AVCEQG: 1119 opset(AVCEQB, r) 1120 opset(AVCEQH, r) 1121 opset(AVCEQF, r) 1122 opset(AVCEQBS, r) 1123 opset(AVCEQHS, r) 1124 opset(AVCEQFS, r) 1125 opset(AVCEQGS, r) 1126 opset(AVCHB, r) 1127 opset(AVCHH, r) 1128 opset(AVCHF, r) 1129 opset(AVCHG, r) 1130 opset(AVCHBS, r) 1131 opset(AVCHHS, r) 1132 opset(AVCHFS, r) 1133 opset(AVCHGS, r) 1134 opset(AVCHLB, r) 1135 opset(AVCHLH, r) 1136 opset(AVCHLF, r) 1137 opset(AVCHLG, r) 1138 opset(AVCHLBS, r) 1139 opset(AVCHLHS, r) 1140 opset(AVCHLFS, r) 1141 opset(AVCHLGS, r) 1142 case AVFAEF: 1143 opset(AVFAEB, r) 1144 opset(AVFAEH, r) 1145 opset(AVFAEBS, r) 1146 opset(AVFAEHS, r) 1147 opset(AVFAEFS, r) 1148 opset(AVFAEZB, r) 1149 opset(AVFAEZH, r) 1150 opset(AVFAEZF, r) 1151 opset(AVFAEZBS, r) 1152 opset(AVFAEZHS, r) 1153 opset(AVFAEZFS, r) 1154 opset(AVFEEB, r) 1155 opset(AVFEEH, r) 1156 opset(AVFEEF, r) 1157 opset(AVFEEBS, r) 1158 opset(AVFEEHS, r) 1159 opset(AVFEEFS, r) 1160 opset(AVFEEZB, r) 1161 opset(AVFEEZH, r) 1162 opset(AVFEEZF, r) 1163 opset(AVFEEZBS, r) 1164 opset(AVFEEZHS, r) 1165 opset(AVFEEZFS, r) 1166 opset(AVFENEB, r) 1167 opset(AVFENEH, r) 1168 opset(AVFENEF, r) 1169 opset(AVFENEBS, r) 1170 opset(AVFENEHS, r) 1171 opset(AVFENEFS, r) 1172 opset(AVFENEZB, r) 1173 opset(AVFENEZH, r) 1174 opset(AVFENEZF, r) 1175 opset(AVFENEZBS, r) 1176 opset(AVFENEZHS, r) 1177 opset(AVFENEZFS, r) 1178 case AVPKSG: 1179 opset(AVPKSH, r) 1180 opset(AVPKSF, r) 1181 opset(AVPKSHS, r) 1182 opset(AVPKSFS, r) 1183 opset(AVPKSGS, r) 1184 opset(AVPKLSH, r) 1185 opset(AVPKLSF, r) 1186 opset(AVPKLSG, r) 1187 opset(AVPKLSHS, r) 1188 opset(AVPKLSFS, r) 1189 opset(AVPKLSGS, r) 1190 case AVAQ: 1191 opset(AVAB, r) 1192 opset(AVAH, r) 1193 opset(AVAF, r) 1194 opset(AVAG, r) 1195 opset(AVACCB, r) 1196 opset(AVACCH, r) 1197 opset(AVACCF, r) 1198 opset(AVACCG, r) 1199 opset(AVACCQ, r) 1200 opset(AVN, r) 1201 opset(AVNC, r) 1202 opset(AVAVGB, r) 1203 opset(AVAVGH, r) 1204 opset(AVAVGF, r) 1205 opset(AVAVGG, r) 1206 opset(AVAVGLB, r) 1207 opset(AVAVGLH, r) 1208 opset(AVAVGLF, r) 1209 opset(AVAVGLG, r) 1210 opset(AVCKSM, r) 1211 opset(AVX, r) 1212 opset(AVFADB, r) 1213 opset(AWFADB, r) 1214 opset(AVFCEDB, r) 1215 opset(AVFCEDBS, r) 1216 opset(AWFCEDB, r) 1217 opset(AWFCEDBS, r) 1218 opset(AVFCHDB, r) 1219 opset(AVFCHDBS, r) 1220 opset(AWFCHDB, r) 1221 opset(AWFCHDBS, r) 1222 opset(AVFCHEDB, r) 1223 opset(AVFCHEDBS, r) 1224 opset(AWFCHEDB, r) 1225 opset(AWFCHEDBS, r) 1226 opset(AVFMDB, r) 1227 opset(AWFMDB, r) 1228 opset(AVGFMB, r) 1229 opset(AVGFMH, r) 1230 opset(AVGFMF, r) 1231 opset(AVGFMG, r) 1232 opset(AVMXB, r) 1233 opset(AVMXH, r) 1234 opset(AVMXF, r) 1235 opset(AVMXG, r) 1236 opset(AVMXLB, r) 1237 opset(AVMXLH, r) 1238 opset(AVMXLF, r) 1239 opset(AVMXLG, r) 1240 opset(AVMNB, r) 1241 opset(AVMNH, r) 1242 opset(AVMNF, r) 1243 opset(AVMNG, r) 1244 opset(AVMNLB, r) 1245 opset(AVMNLH, r) 1246 opset(AVMNLF, r) 1247 opset(AVMNLG, r) 1248 opset(AVMRHB, r) 1249 opset(AVMRHH, r) 1250 opset(AVMRHF, r) 1251 opset(AVMRHG, r) 1252 opset(AVMRLB, r) 1253 opset(AVMRLH, r) 1254 opset(AVMRLF, r) 1255 opset(AVMRLG, r) 1256 opset(AVMEB, r) 1257 opset(AVMEH, r) 1258 opset(AVMEF, r) 1259 opset(AVMLEB, r) 1260 opset(AVMLEH, r) 1261 opset(AVMLEF, r) 1262 opset(AVMOB, r) 1263 opset(AVMOH, r) 1264 opset(AVMOF, r) 1265 opset(AVMLOB, r) 1266 opset(AVMLOH, r) 1267 opset(AVMLOF, r) 1268 opset(AVMHB, r) 1269 opset(AVMHH, r) 1270 opset(AVMHF, r) 1271 opset(AVMLHB, r) 1272 opset(AVMLHH, r) 1273 opset(AVMLHF, r) 1274 opset(AVMLH, r) 1275 opset(AVMLHW, r) 1276 opset(AVMLF, r) 1277 opset(AVNO, r) 1278 opset(AVO, r) 1279 opset(AVPKH, r) 1280 opset(AVPKF, r) 1281 opset(AVPKG, r) 1282 opset(AVSUMGH, r) 1283 opset(AVSUMGF, r) 1284 opset(AVSUMQF, r) 1285 opset(AVSUMQG, r) 1286 opset(AVSUMB, r) 1287 opset(AVSUMH, r) 1288 case AVERLLVG: 1289 opset(AVERLLVB, r) 1290 opset(AVERLLVH, r) 1291 opset(AVERLLVF, r) 1292 opset(AVESLVB, r) 1293 opset(AVESLVH, r) 1294 opset(AVESLVF, r) 1295 opset(AVESLVG, r) 1296 opset(AVESRAVB, r) 1297 opset(AVESRAVH, r) 1298 opset(AVESRAVF, r) 1299 opset(AVESRAVG, r) 1300 opset(AVESRLVB, r) 1301 opset(AVESRLVH, r) 1302 opset(AVESRLVF, r) 1303 opset(AVESRLVG, r) 1304 opset(AVFDDB, r) 1305 opset(AWFDDB, r) 1306 opset(AVFSDB, r) 1307 opset(AWFSDB, r) 1308 opset(AVSL, r) 1309 opset(AVSLB, r) 1310 opset(AVSRA, r) 1311 opset(AVSRAB, r) 1312 opset(AVSRL, r) 1313 opset(AVSRLB, r) 1314 opset(AVSF, r) 1315 opset(AVSG, r) 1316 opset(AVSQ, r) 1317 opset(AVSCBIB, r) 1318 opset(AVSCBIH, r) 1319 opset(AVSCBIF, r) 1320 opset(AVSCBIG, r) 1321 opset(AVSCBIQ, r) 1322 case AVACQ: 1323 opset(AVACCCQ, r) 1324 opset(AVGFMAB, r) 1325 opset(AVGFMAH, r) 1326 opset(AVGFMAF, r) 1327 opset(AVGFMAG, r) 1328 opset(AVMALB, r) 1329 opset(AVMALHW, r) 1330 opset(AVMALF, r) 1331 opset(AVMAHB, r) 1332 opset(AVMAHH, r) 1333 opset(AVMAHF, r) 1334 opset(AVMALHB, r) 1335 opset(AVMALHH, r) 1336 opset(AVMALHF, r) 1337 opset(AVMAEB, r) 1338 opset(AVMAEH, r) 1339 opset(AVMAEF, r) 1340 opset(AVMALEB, r) 1341 opset(AVMALEH, r) 1342 opset(AVMALEF, r) 1343 opset(AVMAOB, r) 1344 opset(AVMAOH, r) 1345 opset(AVMAOF, r) 1346 opset(AVMALOB, r) 1347 opset(AVMALOH, r) 1348 opset(AVMALOF, r) 1349 opset(AVSTRCB, r) 1350 opset(AVSTRCH, r) 1351 opset(AVSTRCF, r) 1352 opset(AVSTRCBS, r) 1353 opset(AVSTRCHS, r) 1354 opset(AVSTRCFS, r) 1355 opset(AVSTRCZB, r) 1356 opset(AVSTRCZH, r) 1357 opset(AVSTRCZF, r) 1358 opset(AVSTRCZBS, r) 1359 opset(AVSTRCZHS, r) 1360 opset(AVSTRCZFS, r) 1361 opset(AVSBCBIQ, r) 1362 opset(AVSBIQ, r) 1363 case AVSEL: 1364 opset(AVFMADB, r) 1365 opset(AWFMADB, r) 1366 opset(AVFMSDB, r) 1367 opset(AWFMSDB, r) 1368 opset(AVPERM, r) 1369 } 1370 } 1371 } 1372 1373 const ( 1374 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1375 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1376 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1377 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1378 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1379 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1380 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1381 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1382 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1383 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1384 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1385 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1386 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1387 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1388 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1389 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1390 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1391 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1392 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1393 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1394 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1395 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1396 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1397 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1398 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1399 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1400 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1401 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1402 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1403 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1404 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1405 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1406 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1407 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1408 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1409 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1410 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1411 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1412 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1413 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1414 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1415 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1416 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1417 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1418 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1419 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1420 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1421 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1422 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1423 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1424 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1425 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1426 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1427 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1428 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1429 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1430 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1431 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1432 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1433 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1434 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1435 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1436 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1437 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1438 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1439 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1440 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1441 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1442 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1443 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1444 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1445 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1446 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1447 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1448 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1449 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1450 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1451 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1452 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1453 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1454 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1455 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1456 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1457 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1458 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1459 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1460 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1461 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1462 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1463 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1464 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1465 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1466 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1467 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1468 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1469 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1470 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1471 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1472 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1473 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1474 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1475 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1476 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1477 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1478 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1479 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1480 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1481 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1482 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1483 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1484 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1485 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1486 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1487 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1488 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1489 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1490 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1491 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1492 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1493 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1494 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1495 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1496 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1497 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1498 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1499 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1500 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1501 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1502 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1503 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1504 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1505 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1506 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1507 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1508 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1509 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1510 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1511 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1512 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1513 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1514 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1515 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1516 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1517 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1518 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1519 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1520 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1521 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1522 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1523 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1524 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1525 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1526 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1527 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1528 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1529 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1530 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1531 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1532 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1533 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1534 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1535 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1536 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1537 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1538 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1539 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1540 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1541 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1542 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1543 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1544 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1545 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1546 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1547 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1548 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1549 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1550 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1551 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1552 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1553 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1554 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1555 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1556 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1557 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1558 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1559 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1560 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1561 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1562 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1563 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1564 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1565 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1566 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1567 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1568 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1569 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1570 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1571 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1572 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1573 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1574 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1575 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1576 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1577 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1578 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1579 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1580 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1581 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1582 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1583 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1584 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1585 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1586 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1587 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1588 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1589 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1590 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1591 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1592 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1593 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1594 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1595 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1596 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1597 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1598 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1599 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1600 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1601 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1602 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1603 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1604 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1605 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1606 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1607 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1608 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1609 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1610 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1611 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1612 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1613 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1614 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1615 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1616 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1617 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1618 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1619 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1620 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1621 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1622 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1623 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1624 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1625 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1626 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1627 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1628 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1629 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1630 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1631 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1632 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1633 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1634 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1635 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1636 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1637 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1638 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1639 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1640 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1641 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1642 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1643 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1644 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1645 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1646 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1647 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1648 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1649 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1650 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1651 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1652 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1653 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1654 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1655 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1656 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1657 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1658 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1659 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1660 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1661 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1662 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1663 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1664 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1665 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1666 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1667 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1668 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1669 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1670 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1671 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1672 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1673 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1674 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1675 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1676 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1677 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1678 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1679 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1680 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1681 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1682 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1683 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1684 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1685 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1686 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1687 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1688 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1689 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1690 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1691 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1692 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1693 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1694 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1695 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1696 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1697 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1698 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1699 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1700 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1701 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1702 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1703 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1704 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1705 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1706 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1707 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1708 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1709 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1710 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1711 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1712 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1713 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1714 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1715 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1716 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1717 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1718 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1719 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1720 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1721 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1722 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1723 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1724 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1725 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1726 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1727 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1728 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1729 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1730 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1731 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1732 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1733 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1734 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1735 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1736 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1737 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1738 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1739 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1740 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1741 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1742 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1743 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1744 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1745 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1746 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1747 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1748 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1749 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1750 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1751 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1752 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1753 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1754 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1755 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1756 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1757 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1758 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1759 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1760 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1761 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1762 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1763 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1764 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1765 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1766 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1767 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1768 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1769 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1770 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1771 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1772 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1773 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1774 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1775 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1776 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1777 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1778 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1779 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1780 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1781 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1782 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1783 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1784 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1785 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1786 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1787 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1788 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1789 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1790 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1791 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1792 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1793 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1794 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1795 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1796 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1797 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1798 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1799 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1800 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1801 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1802 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1803 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1804 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1805 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1806 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1807 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1808 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1809 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1810 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1811 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1812 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1813 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1814 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1815 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1816 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1817 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1818 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1819 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1820 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1821 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1822 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1823 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1824 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1825 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1826 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1827 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1828 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1829 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1830 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1831 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1832 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1833 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1834 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1835 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1836 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1837 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1838 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1839 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1840 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1841 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1842 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1843 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1844 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1845 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1846 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1847 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1848 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1849 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1850 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1851 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1852 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1853 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1854 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1855 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1856 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1857 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1858 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1859 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1860 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1861 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1862 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1863 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1864 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1865 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1866 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 1867 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 1868 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 1869 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 1870 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 1871 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 1872 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 1873 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 1874 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 1875 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 1876 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 1877 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 1878 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 1879 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 1880 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 1881 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 1882 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 1883 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 1884 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 1885 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 1886 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 1887 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 1888 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 1889 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 1890 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 1891 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 1892 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 1893 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 1894 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 1895 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 1896 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 1897 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 1898 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 1899 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 1900 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 1901 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 1902 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 1903 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 1904 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 1905 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 1906 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 1907 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 1908 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 1909 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 1910 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 1911 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 1912 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 1913 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 1914 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 1915 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 1916 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 1917 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 1918 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 1919 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 1920 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 1921 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 1922 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 1923 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 1924 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 1925 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1926 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1927 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 1928 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 1929 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 1930 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 1931 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 1932 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 1933 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 1934 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 1935 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 1936 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 1937 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 1938 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 1939 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 1940 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 1941 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 1942 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 1943 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 1944 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 1945 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 1946 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 1947 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 1948 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 1949 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 1950 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 1951 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 1952 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 1953 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 1954 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 1955 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 1956 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 1957 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 1958 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 1959 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 1960 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 1961 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 1962 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 1963 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 1964 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 1965 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 1966 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 1967 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 1968 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 1969 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 1970 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 1971 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 1972 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1973 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1974 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1975 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1976 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1977 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1978 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 1979 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 1980 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 1981 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 1982 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1983 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 1984 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 1985 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1986 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 1987 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1988 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1989 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1990 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 1991 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 1992 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 1993 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 1994 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1995 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 1996 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 1997 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 1998 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 1999 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 2000 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 2001 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 2002 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 2003 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 2004 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 2005 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 2006 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 2007 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 2008 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 2009 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 2010 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 2011 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 2012 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 2013 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 2014 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 2015 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 2016 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 2017 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 2018 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 2019 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 2020 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 2021 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 2022 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 2023 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 2024 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 2025 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 2026 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 2027 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 2028 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 2029 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 2030 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 2031 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 2032 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 2033 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 2034 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 2035 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 2036 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 2037 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 2038 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 2039 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 2040 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 2041 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 2042 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 2043 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 2044 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 2045 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 2046 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 2047 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 2048 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 2049 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 2050 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 2051 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 2052 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2053 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2054 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 2055 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 2056 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 2057 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 2058 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 2059 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 2060 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 2061 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 2062 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 2063 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 2064 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 2065 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 2066 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 2067 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 2068 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 2069 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 2070 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2071 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2072 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2073 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2074 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2075 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2076 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2077 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2078 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2079 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2080 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2081 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2082 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2083 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2084 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2085 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2086 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2087 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2088 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2089 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2090 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2091 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2092 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2093 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2094 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2095 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2096 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2097 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2098 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2099 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2100 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2101 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2102 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2103 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2104 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2105 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2106 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2107 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2108 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2109 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2110 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2111 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2112 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2113 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2114 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2115 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2116 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2117 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2118 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2119 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2120 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2121 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2122 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2123 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2124 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2125 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2126 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2127 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2128 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2129 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2130 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2131 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2132 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2133 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2134 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2135 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2136 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2137 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2138 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2139 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2140 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2141 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2142 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2143 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2144 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2145 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2146 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2147 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2148 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2149 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2150 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2151 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2152 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2153 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2154 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2155 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2156 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2157 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2158 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2159 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2160 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2161 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2162 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2163 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2164 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2165 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2166 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2167 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2168 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2169 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2170 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2171 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2172 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2173 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2174 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2175 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2176 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2177 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2178 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2179 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2180 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2181 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2182 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2183 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2184 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2185 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2186 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2187 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2188 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2189 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2190 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2191 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2192 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2193 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2194 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2195 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2196 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2197 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2198 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2199 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2200 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2201 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2202 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2203 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2204 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2205 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2206 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2207 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2208 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2209 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2210 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2211 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2212 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2213 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2214 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2215 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2216 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2217 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2218 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2219 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2220 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2221 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2222 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2223 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2224 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2225 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2226 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2227 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2228 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2229 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2230 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2231 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2232 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2233 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2234 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2235 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2236 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2237 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2238 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2239 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2240 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2241 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2242 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2243 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2244 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2245 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2246 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2247 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2248 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2249 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2250 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2251 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2252 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2253 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2254 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2255 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2256 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2257 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2258 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2259 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2260 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2261 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2262 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2263 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2264 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2265 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2266 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2267 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2268 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2269 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2270 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2271 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2272 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2273 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2274 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2275 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2276 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2277 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2278 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2279 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2280 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2281 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2282 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2283 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2284 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2285 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2286 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2287 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2288 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2289 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2290 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2291 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2292 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2293 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2294 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2295 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2296 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2297 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2298 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2299 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2300 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2301 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2302 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2303 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2304 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2305 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2306 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2307 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2308 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2309 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2310 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2311 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2312 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2313 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2314 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2315 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2316 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2317 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2318 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2319 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2320 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2321 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2322 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2323 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2324 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2325 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2326 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2327 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2328 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2329 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2330 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2331 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2332 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2333 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2334 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2335 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2336 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2337 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2338 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2339 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2340 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2341 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2342 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2343 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2344 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2345 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2346 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2347 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2348 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2349 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2350 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2351 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2352 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2353 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2354 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2355 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2356 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2357 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2358 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2359 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2360 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2361 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2362 2363 // added in z13 2364 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2365 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2366 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2367 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2368 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2369 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2370 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2371 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2372 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2373 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2374 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2375 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2376 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2377 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2378 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2379 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2380 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2381 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2382 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2383 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2384 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2385 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2386 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2387 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2388 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2389 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2390 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2391 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2392 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2393 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2394 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2395 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2396 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2397 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2398 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2399 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2400 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2401 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2402 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2403 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2404 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2405 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2406 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2407 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2408 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2409 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2410 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2411 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2412 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2413 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2414 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2415 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2416 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2417 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2418 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2419 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2420 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2421 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2422 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2423 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2424 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2425 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2426 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2427 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2428 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2429 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2430 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2431 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2432 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2433 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2434 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2435 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2436 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2437 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2438 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2439 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2440 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2441 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2442 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2443 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2444 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2445 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2446 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2447 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2448 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2449 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2450 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2451 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2452 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2453 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2454 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2455 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2456 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2457 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2458 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2459 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2460 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2461 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2462 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2463 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2464 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2465 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2466 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2467 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2468 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2469 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2470 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2471 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2472 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2473 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2474 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2475 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2476 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2477 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2478 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2479 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2480 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2481 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2482 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2483 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2484 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2485 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2486 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2487 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2488 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2489 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2490 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2491 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2492 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2493 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2494 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2495 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2496 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2497 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2498 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2499 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2500 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2501 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2502 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2503 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2504 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2505 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2506 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2507 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2508 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2509 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2510 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2511 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2512 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2513 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2514 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2515 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2516 ) 2517 2518 func oclass(a *obj.Addr) int { 2519 return int(a.Class) - 1 2520 } 2521 2522 // Add a relocation for the immediate in a RIL style instruction. 2523 // The addend will be adjusted as required. 2524 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) *obj.Reloc { 2525 if sym == nil { 2526 c.ctxt.Diag("require symbol to apply relocation") 2527 } 2528 offset := int64(2) // relocation offset from start of instruction 2529 rel := obj.Addrel(c.cursym) 2530 rel.Off = int32(c.pc + offset) 2531 rel.Siz = 4 2532 rel.Sym = sym 2533 rel.Add = add + offset + int64(rel.Siz) 2534 rel.Type = objabi.R_PCRELDBL 2535 return rel 2536 } 2537 2538 func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) *obj.Reloc { 2539 if sym == nil { 2540 c.ctxt.Diag("require symbol to apply relocation") 2541 } 2542 offset += int64(2) // relocation offset from start of instruction 2543 rel := obj.Addrel(c.cursym) 2544 rel.Off = int32(c.pc + offset) 2545 rel.Siz = 4 2546 rel.Sym = sym 2547 rel.Add = add + offset + int64(rel.Siz) 2548 rel.Type = objabi.R_PCRELDBL 2549 return rel 2550 } 2551 2552 // Add a CALL relocation for the immediate in a RIL style instruction. 2553 // The addend will be adjusted as required. 2554 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) *obj.Reloc { 2555 if sym == nil { 2556 c.ctxt.Diag("require symbol to apply relocation") 2557 } 2558 offset := int64(2) // relocation offset from start of instruction 2559 rel := obj.Addrel(c.cursym) 2560 rel.Off = int32(c.pc + offset) 2561 rel.Siz = 4 2562 rel.Sym = sym 2563 rel.Add = add + offset + int64(rel.Siz) 2564 rel.Type = objabi.R_CALL 2565 return rel 2566 } 2567 2568 func (c *ctxtz) branchMask(p *obj.Prog) uint32 { 2569 switch p.As { 2570 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ: 2571 return 0x8 2572 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE: 2573 return 0xA 2574 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT: 2575 return 0x2 2576 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE: 2577 return 0xC 2578 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT: 2579 return 0x4 2580 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE: 2581 return 0x7 2582 case ABLEU: // LE or unordered 2583 return 0xD 2584 case ABLTU: // LT or unordered 2585 return 0x5 2586 case ABVC: 2587 return 0x0 // needs extra instruction 2588 case ABVS: 2589 return 0x1 // unordered 2590 } 2591 c.ctxt.Diag("unknown conditional branch %v", p.As) 2592 return 0xF 2593 } 2594 2595 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) { 2596 o := c.oplook(p) 2597 2598 switch o.type_ { 2599 default: 2600 c.ctxt.Diag("unknown type %d", o.type_) 2601 2602 case 0: // PSEUDO OPS 2603 break 2604 2605 case 1: // mov reg reg 2606 switch p.As { 2607 default: 2608 c.ctxt.Diag("unhandled operation: %v", p.As) 2609 case AMOVD: 2610 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2611 // sign extend 2612 case AMOVW: 2613 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2614 case AMOVH: 2615 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2616 case AMOVB: 2617 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2618 // zero extend 2619 case AMOVWZ: 2620 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2621 case AMOVHZ: 2622 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2623 case AMOVBZ: 2624 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2625 // reverse bytes 2626 case AMOVDBR: 2627 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2628 case AMOVWBR: 2629 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2630 // floating point 2631 case AFMOVD, AFMOVS: 2632 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2633 } 2634 2635 case 2: // arithmetic op reg [reg] reg 2636 r := p.Reg 2637 if r == 0 { 2638 r = p.To.Reg 2639 } 2640 2641 var opcode uint32 2642 2643 switch p.As { 2644 default: 2645 c.ctxt.Diag("invalid opcode") 2646 case AADD: 2647 opcode = op_AGRK 2648 case AADDC: 2649 opcode = op_ALGRK 2650 case AADDE: 2651 opcode = op_ALCGR 2652 case AADDW: 2653 opcode = op_ARK 2654 case AMULLW: 2655 opcode = op_MSGFR 2656 case AMULLD: 2657 opcode = op_MSGR 2658 case ADIVW, AMODW: 2659 opcode = op_DSGFR 2660 case ADIVWU, AMODWU: 2661 opcode = op_DLR 2662 case ADIVD, AMODD: 2663 opcode = op_DSGR 2664 case ADIVDU, AMODDU: 2665 opcode = op_DLGR 2666 } 2667 2668 switch p.As { 2669 default: 2670 2671 case AADD, AADDC, AADDW: 2672 if p.As == AADDW && r == p.To.Reg { 2673 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2674 } else { 2675 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2676 } 2677 2678 case AADDE, AMULLW, AMULLD: 2679 if r == p.To.Reg { 2680 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2681 } else if p.From.Reg == p.To.Reg { 2682 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2683 } else { 2684 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2685 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2686 } 2687 2688 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2689 if p.As == ADIVWU || p.As == ADIVDU { 2690 zRI(op_LGHI, REGTMP, 0, asm) 2691 } 2692 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2693 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2694 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2695 2696 case AMODW, AMODWU, AMODD, AMODDU: 2697 if p.As == AMODWU || p.As == AMODDU { 2698 zRI(op_LGHI, REGTMP, 0, asm) 2699 } 2700 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2701 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2702 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2703 2704 } 2705 2706 case 3: // mov $constant reg 2707 v := c.vregoff(&p.From) 2708 switch p.As { 2709 case AMOVBZ: 2710 v = int64(uint8(v)) 2711 case AMOVHZ: 2712 v = int64(uint16(v)) 2713 case AMOVWZ: 2714 v = int64(uint32(v)) 2715 case AMOVB: 2716 v = int64(int8(v)) 2717 case AMOVH: 2718 v = int64(int16(v)) 2719 case AMOVW: 2720 v = int64(int32(v)) 2721 } 2722 if int64(int16(v)) == v { 2723 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2724 } else if v&0xffff0000 == v { 2725 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2726 } else if v&0xffff00000000 == v { 2727 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2728 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2729 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2730 } else if int64(int32(v)) == v { 2731 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2732 } else if int64(uint32(v)) == v { 2733 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2734 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2735 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2736 } else { 2737 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2738 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2739 } 2740 2741 case 4: // multiply high (a*b)>>64 2742 r := p.Reg 2743 if r == 0 { 2744 r = p.To.Reg 2745 } 2746 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2747 zRRE(op_MLGR, REGTMP, uint32(p.From.Reg), asm) 2748 switch p.As { 2749 case AMULHDU: 2750 // Unsigned: move result into correct register. 2751 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2752 case AMULHD: 2753 // Signed: need to convert result. 2754 // See Hacker's Delight 8-3. 2755 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm) 2756 zRRE(op_NGR, REGTMP2, uint32(r), asm) 2757 zRRE(op_SGR, REGTMP, REGTMP2, asm) 2758 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm) 2759 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm) 2760 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), REGTMP, asm) 2761 } 2762 2763 case 5: // syscall 2764 zI(op_SVC, 0, asm) 2765 2766 case 6: // logical op reg [reg] reg 2767 var oprr, oprre, oprrf uint32 2768 switch p.As { 2769 case AAND: 2770 oprre = op_NGR 2771 oprrf = op_NGRK 2772 case AANDW: 2773 oprr = op_NR 2774 oprrf = op_NRK 2775 case AOR: 2776 oprre = op_OGR 2777 oprrf = op_OGRK 2778 case AORW: 2779 oprr = op_OR 2780 oprrf = op_ORK 2781 case AXOR: 2782 oprre = op_XGR 2783 oprrf = op_XGRK 2784 case AXORW: 2785 oprr = op_XR 2786 oprrf = op_XRK 2787 } 2788 if p.Reg == 0 { 2789 if oprr != 0 { 2790 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2791 } else { 2792 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2793 } 2794 } else { 2795 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2796 } 2797 2798 case 7: // shift/rotate reg [reg] reg 2799 d2 := c.vregoff(&p.From) 2800 b2 := p.From.Reg 2801 r3 := p.Reg 2802 if r3 == 0 { 2803 r3 = p.To.Reg 2804 } 2805 r1 := p.To.Reg 2806 var opcode uint32 2807 switch p.As { 2808 default: 2809 case ASLD: 2810 opcode = op_SLLG 2811 case ASRD: 2812 opcode = op_SRLG 2813 case ASLW: 2814 opcode = op_SLLK 2815 case ASRW: 2816 opcode = op_SRLK 2817 case ARLL: 2818 opcode = op_RLL 2819 case ARLLG: 2820 opcode = op_RLLG 2821 case ASRAW: 2822 opcode = op_SRAK 2823 case ASRAD: 2824 opcode = op_SRAG 2825 } 2826 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2827 2828 case 8: // find leftmost one 2829 if p.To.Reg&1 != 0 { 2830 c.ctxt.Diag("target must be an even-numbered register") 2831 } 2832 // FLOGR also writes a mask to p.To.Reg+1. 2833 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2834 2835 case 10: // subtract reg [reg] reg 2836 r := int(p.Reg) 2837 2838 switch p.As { 2839 default: 2840 case ASUB: 2841 if r == 0 { 2842 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2843 } else { 2844 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2845 } 2846 case ASUBC: 2847 if r == 0 { 2848 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2849 } else { 2850 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2851 } 2852 case ASUBE: 2853 if r == 0 { 2854 r = int(p.To.Reg) 2855 } 2856 if r == int(p.To.Reg) { 2857 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2858 } else if p.From.Reg == p.To.Reg { 2859 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 2860 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2861 zRRE(op_SLBGR, uint32(p.To.Reg), REGTMP, asm) 2862 } else { 2863 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2864 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2865 } 2866 case ASUBW: 2867 if r == 0 { 2868 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2869 } else { 2870 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2871 } 2872 } 2873 2874 case 11: // br/bl 2875 v := int32(0) 2876 2877 if p.Pcond != nil { 2878 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2879 } 2880 2881 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 2882 zRI(op_BRC, 0xF, uint32(v), asm) 2883 } else { 2884 if p.As == ABL { 2885 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 2886 } else { 2887 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 2888 } 2889 if p.To.Sym != nil { 2890 c.addcallreloc(p.To.Sym, p.To.Offset) 2891 } 2892 } 2893 2894 case 12: 2895 r1 := p.To.Reg 2896 d2 := c.vregoff(&p.From) 2897 b2 := p.From.Reg 2898 if b2 == 0 { 2899 b2 = o.param 2900 } 2901 x2 := p.From.Index 2902 if -DISP20/2 > d2 || d2 >= DISP20/2 { 2903 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 2904 if x2 != 0 { 2905 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 2906 } 2907 x2 = REGTMP 2908 d2 = 0 2909 } 2910 var opx, opxy uint32 2911 switch p.As { 2912 case AADD: 2913 opxy = op_AG 2914 case AADDC: 2915 opxy = op_ALG 2916 case AADDW: 2917 opx = op_A 2918 opxy = op_AY 2919 case AMULLW: 2920 opx = op_MS 2921 opxy = op_MSY 2922 case AMULLD: 2923 opxy = op_MSG 2924 case ASUB: 2925 opxy = op_SG 2926 case ASUBC: 2927 opxy = op_SLG 2928 case ASUBE: 2929 opxy = op_SLBG 2930 case ASUBW: 2931 opx = op_S 2932 opxy = op_SY 2933 case AAND: 2934 opxy = op_NG 2935 case AANDW: 2936 opx = op_N 2937 opxy = op_NY 2938 case AOR: 2939 opxy = op_OG 2940 case AORW: 2941 opx = op_O 2942 opxy = op_OY 2943 case AXOR: 2944 opxy = op_XG 2945 case AXORW: 2946 opx = op_X 2947 opxy = op_XY 2948 } 2949 if opx != 0 && 0 <= d2 && d2 < DISP12 { 2950 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2951 } else { 2952 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2953 } 2954 2955 case 15: // br/bl (reg) 2956 r := p.To.Reg 2957 if p.As == ABCL || p.As == ABL { 2958 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 2959 } else { 2960 zRR(op_BCR, 0xF, uint32(r), asm) 2961 } 2962 2963 case 16: // conditional branch 2964 v := int32(0) 2965 if p.Pcond != nil { 2966 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2967 } 2968 mask := c.branchMask(p) 2969 if p.To.Sym == nil && int32(int16(v)) == v { 2970 zRI(op_BRC, mask, uint32(v), asm) 2971 } else { 2972 zRIL(_c, op_BRCL, mask, uint32(v), asm) 2973 } 2974 if p.To.Sym != nil { 2975 c.addrilreloc(p.To.Sym, p.To.Offset) 2976 } 2977 2978 case 17: // move on condition 2979 m3 := c.branchMask(p) 2980 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2981 2982 case 18: // br/bl reg 2983 if p.As == ABL { 2984 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 2985 } else { 2986 zRR(op_BCR, 0xF, uint32(p.To.Reg), asm) 2987 } 2988 2989 case 19: // mov $sym+n(SB) reg 2990 d := c.vregoff(&p.From) 2991 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 2992 if d&1 != 0 { 2993 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 2994 d -= 1 2995 } 2996 c.addrilreloc(p.From.Sym, d) 2997 2998 case 21: // subtract $constant [reg] reg 2999 v := c.vregoff(&p.From) 3000 r := p.Reg 3001 if r == 0 { 3002 r = p.To.Reg 3003 } 3004 switch p.As { 3005 case ASUB: 3006 zRIL(_a, op_LGFI, uint32(REGTMP), uint32(v), asm) 3007 zRRF(op_SLGRK, uint32(REGTMP), 0, uint32(p.To.Reg), uint32(r), asm) 3008 case ASUBC: 3009 if r != p.To.Reg { 3010 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3011 } 3012 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm) 3013 case ASUBW: 3014 if r != p.To.Reg { 3015 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3016 } 3017 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm) 3018 } 3019 3020 case 22: // add/multiply $constant [reg] reg 3021 v := c.vregoff(&p.From) 3022 r := p.Reg 3023 if r == 0 { 3024 r = p.To.Reg 3025 } 3026 var opri, opril, oprie uint32 3027 switch p.As { 3028 case AADD: 3029 opri = op_AGHI 3030 opril = op_AGFI 3031 oprie = op_AGHIK 3032 case AADDC: 3033 opril = op_ALGFI 3034 oprie = op_ALGHSIK 3035 case AADDW: 3036 opri = op_AHI 3037 opril = op_AFI 3038 oprie = op_AHIK 3039 case AMULLW: 3040 opri = op_MHI 3041 opril = op_MSFI 3042 case AMULLD: 3043 opri = op_MGHI 3044 opril = op_MSGFI 3045 } 3046 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) { 3047 switch p.As { 3048 case AADD, AADDC, AMULLD: 3049 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3050 case AADDW, AMULLW: 3051 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3052 } 3053 r = p.To.Reg 3054 } 3055 if r == p.To.Reg { 3056 if opri != 0 && int64(int16(v)) == v { 3057 zRI(opri, uint32(p.To.Reg), uint32(v), asm) 3058 } else { 3059 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm) 3060 } 3061 } else { 3062 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 3063 } 3064 3065 case 23: // 64-bit logical op $constant reg 3066 // TODO(mundaym): merge with case 24. 3067 v := c.vregoff(&p.From) 3068 switch p.As { 3069 default: 3070 c.ctxt.Diag("%v is not supported", p) 3071 case AAND: 3072 if v >= 0 { // needs zero extend 3073 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3074 zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm) 3075 } else if int64(int16(v)) == v { 3076 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3077 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 3078 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3079 } 3080 case AOR: 3081 if int64(uint32(v)) != v { // needs sign extend 3082 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3083 zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm) 3084 } else if int64(uint16(v)) == v { 3085 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3086 } else { 3087 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3088 } 3089 case AXOR: 3090 if int64(uint32(v)) != v { // needs sign extend 3091 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3092 zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm) 3093 } else { 3094 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3095 } 3096 } 3097 3098 case 24: // 32-bit logical op $constant reg 3099 v := c.vregoff(&p.From) 3100 switch p.As { 3101 case AANDW: 3102 if uint32(v&0xffff0000) == 0xffff0000 { 3103 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3104 } else if uint32(v&0x0000ffff) == 0x0000ffff { 3105 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3106 } else { 3107 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3108 } 3109 case AORW: 3110 if uint32(v&0xffff0000) == 0 { 3111 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3112 } else if uint32(v&0x0000ffff) == 0 { 3113 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3114 } else { 3115 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3116 } 3117 case AXORW: 3118 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3119 } 3120 3121 case 26: // MOVD $offset(base)(index), reg 3122 v := c.regoff(&p.From) 3123 r := p.From.Reg 3124 if r == 0 { 3125 r = o.param 3126 } 3127 i := p.From.Index 3128 if v >= 0 && v < DISP12 { 3129 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3130 } else if v >= -DISP20/2 && v < DISP20/2 { 3131 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3132 } else { 3133 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3134 zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, uint32(i), asm) 3135 } 3136 3137 case 31: // dword 3138 wd := uint64(c.vregoff(&p.From)) 3139 *asm = append(*asm, 3140 uint8(wd>>56), 3141 uint8(wd>>48), 3142 uint8(wd>>40), 3143 uint8(wd>>32), 3144 uint8(wd>>24), 3145 uint8(wd>>16), 3146 uint8(wd>>8), 3147 uint8(wd)) 3148 3149 case 32: // float op freg freg 3150 var opcode uint32 3151 switch p.As { 3152 default: 3153 c.ctxt.Diag("invalid opcode") 3154 case AFADD: 3155 opcode = op_ADBR 3156 case AFADDS: 3157 opcode = op_AEBR 3158 case AFDIV: 3159 opcode = op_DDBR 3160 case AFDIVS: 3161 opcode = op_DEBR 3162 case AFMUL: 3163 opcode = op_MDBR 3164 case AFMULS: 3165 opcode = op_MEEBR 3166 case AFSUB: 3167 opcode = op_SDBR 3168 case AFSUBS: 3169 opcode = op_SEBR 3170 } 3171 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3172 3173 case 33: // float op [freg] freg 3174 r := p.From.Reg 3175 if oclass(&p.From) == C_NONE { 3176 r = p.To.Reg 3177 } 3178 var opcode uint32 3179 switch p.As { 3180 default: 3181 case AFABS: 3182 opcode = op_LPDBR 3183 case AFNABS: 3184 opcode = op_LNDBR 3185 case AFNEG: 3186 opcode = op_LCDFR 3187 case AFNEGS: 3188 opcode = op_LCEBR 3189 case ALEDBR: 3190 opcode = op_LEDBR 3191 case ALDEBR: 3192 opcode = op_LDEBR 3193 case AFSQRT: 3194 opcode = op_SQDBR 3195 case AFSQRTS: 3196 opcode = op_SQEBR 3197 } 3198 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3199 3200 case 34: // float multiply-add freg freg freg 3201 var opcode uint32 3202 switch p.As { 3203 default: 3204 c.ctxt.Diag("invalid opcode") 3205 case AFMADD: 3206 opcode = op_MADBR 3207 case AFMADDS: 3208 opcode = op_MAEBR 3209 case AFMSUB: 3210 opcode = op_MSDBR 3211 case AFMSUBS: 3212 opcode = op_MSEBR 3213 } 3214 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 3215 3216 case 35: // mov reg mem (no relocation) 3217 d2 := c.regoff(&p.To) 3218 b2 := p.To.Reg 3219 if b2 == 0 { 3220 b2 = o.param 3221 } 3222 x2 := p.To.Index 3223 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3224 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3225 if x2 != 0 { 3226 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3227 } 3228 x2 = REGTMP 3229 d2 = 0 3230 } 3231 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3232 3233 case 36: // mov mem reg (no relocation) 3234 d2 := c.regoff(&p.From) 3235 b2 := p.From.Reg 3236 if b2 == 0 { 3237 b2 = o.param 3238 } 3239 x2 := p.From.Index 3240 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3241 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3242 if x2 != 0 { 3243 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3244 } 3245 x2 = REGTMP 3246 d2 = 0 3247 } 3248 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3249 3250 case 40: // word/byte 3251 wd := uint32(c.regoff(&p.From)) 3252 if p.As == AWORD { //WORD 3253 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3254 } else { //BYTE 3255 *asm = append(*asm, uint8(wd)) 3256 } 3257 3258 case 47: // negate [reg] reg 3259 r := p.From.Reg 3260 if r == 0 { 3261 r = p.To.Reg 3262 } 3263 switch p.As { 3264 case ANEG: 3265 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3266 case ANEGW: 3267 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm) 3268 } 3269 3270 case 48: // floating-point round to integer 3271 m3 := c.vregoff(&p.From) 3272 if 0 > m3 || m3 > 7 { 3273 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3) 3274 } 3275 var opcode uint32 3276 switch p.As { 3277 case AFIEBR: 3278 opcode = op_FIEBR 3279 case AFIDBR: 3280 opcode = op_FIDBR 3281 } 3282 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3283 3284 case 67: // fmov $0 freg 3285 var opcode uint32 3286 switch p.As { 3287 case AFMOVS: 3288 opcode = op_LZER 3289 case AFMOVD: 3290 opcode = op_LZDR 3291 } 3292 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3293 3294 case 68: // movw areg reg 3295 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3296 3297 case 69: // movw reg areg 3298 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3299 3300 case 70: // cmp reg reg 3301 if p.As == ACMPW || p.As == ACMPWU { 3302 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3303 } else { 3304 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3305 } 3306 3307 case 71: // cmp reg $constant 3308 v := c.vregoff(&p.To) 3309 switch p.As { 3310 case ACMP, ACMPW: 3311 if int64(int32(v)) != v { 3312 c.ctxt.Diag("%v overflows an int32", v) 3313 } 3314 case ACMPU, ACMPWU: 3315 if int64(uint32(v)) != v { 3316 c.ctxt.Diag("%v overflows a uint32", v) 3317 } 3318 } 3319 if p.As == ACMP && int64(int16(v)) == v { 3320 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm) 3321 } else if p.As == ACMPW && int64(int16(v)) == v { 3322 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm) 3323 } else { 3324 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm) 3325 } 3326 3327 case 72: // mov $constant mem 3328 v := c.regoff(&p.From) 3329 d := c.regoff(&p.To) 3330 r := p.To.Reg 3331 if p.To.Index != 0 { 3332 c.ctxt.Diag("cannot use index register") 3333 } 3334 if r == 0 { 3335 r = o.param 3336 } 3337 var opcode uint32 3338 switch p.As { 3339 case AMOVD: 3340 opcode = op_MVGHI 3341 case AMOVW, AMOVWZ: 3342 opcode = op_MVHI 3343 case AMOVH, AMOVHZ: 3344 opcode = op_MVHHI 3345 case AMOVB, AMOVBZ: 3346 opcode = op_MVI 3347 } 3348 if d < 0 || d >= DISP12 { 3349 if r == REGTMP { 3350 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r) 3351 } 3352 if d >= -DISP20/2 && d < DISP20/2 { 3353 if opcode == op_MVI { 3354 opcode = op_MVIY 3355 } else { 3356 zRXY(op_LAY, uint32(REGTMP), 0, uint32(r), uint32(d), asm) 3357 r = REGTMP 3358 d = 0 3359 } 3360 } else { 3361 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3362 zRX(op_LA, REGTMP, REGTMP, uint32(r), 0, asm) 3363 r = REGTMP 3364 d = 0 3365 } 3366 } 3367 switch opcode { 3368 case op_MVI: 3369 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3370 case op_MVIY: 3371 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm) 3372 default: 3373 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3374 } 3375 3376 case 74: // mov reg addr (including relocation) 3377 i2 := c.regoff(&p.To) 3378 switch p.As { 3379 case AMOVD: 3380 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3381 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3382 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3383 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3384 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3385 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3386 zRIL(_b, op_LARL, REGTMP, 0, asm) 3387 adj := uint32(0) // adjustment needed for odd addresses 3388 if i2&1 != 0 { 3389 i2 -= 1 3390 adj = 1 3391 } 3392 zRX(op_STC, uint32(p.From.Reg), 0, REGTMP, adj, asm) 3393 case AFMOVD: 3394 zRIL(_b, op_LARL, REGTMP, 0, asm) 3395 zRX(op_STD, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3396 case AFMOVS: 3397 zRIL(_b, op_LARL, REGTMP, 0, asm) 3398 zRX(op_STE, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3399 } 3400 c.addrilreloc(p.To.Sym, int64(i2)) 3401 3402 case 75: // mov addr reg (including relocation) 3403 i2 := c.regoff(&p.From) 3404 switch p.As { 3405 case AMOVD: 3406 if i2&1 != 0 { 3407 zRIL(_b, op_LARL, REGTMP, 0, asm) 3408 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 1, asm) 3409 i2 -= 1 3410 } else { 3411 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3412 } 3413 case AMOVW: 3414 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3415 case AMOVWZ: 3416 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3417 case AMOVH: 3418 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3419 case AMOVHZ: 3420 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3421 case AMOVB, AMOVBZ: 3422 zRIL(_b, op_LARL, REGTMP, 0, asm) 3423 adj := uint32(0) // adjustment needed for odd addresses 3424 if i2&1 != 0 { 3425 i2 -= 1 3426 adj = 1 3427 } 3428 switch p.As { 3429 case AMOVB: 3430 zRXY(op_LGB, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3431 case AMOVBZ: 3432 zRXY(op_LLGC, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3433 } 3434 case AFMOVD: 3435 zRIL(_a, op_LARL, REGTMP, 0, asm) 3436 zRX(op_LD, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3437 case AFMOVS: 3438 zRIL(_a, op_LARL, REGTMP, 0, asm) 3439 zRX(op_LE, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3440 } 3441 c.addrilreloc(p.From.Sym, int64(i2)) 3442 3443 case 77: // syscall $constant 3444 if p.From.Offset > 255 || p.From.Offset < 1 { 3445 c.ctxt.Diag("illegal system call; system call number out of range: %v", p) 3446 zE(op_TRAP2, asm) // trap always 3447 } else { 3448 zI(op_SVC, uint32(p.From.Offset), asm) 3449 } 3450 3451 case 78: // undef 3452 // "An instruction consisting entirely of binary 0s is guaranteed 3453 // always to be an illegal instruction." 3454 *asm = append(*asm, 0, 0, 0, 0) 3455 3456 case 79: // compare and swap reg reg reg 3457 v := c.regoff(&p.To) 3458 if v < 0 { 3459 v = 0 3460 } 3461 if p.As == ACS { 3462 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3463 } else if p.As == ACSG { 3464 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3465 } 3466 3467 case 80: // sync 3468 zRR(op_BCR, 0xE, 0, asm) 3469 3470 case 81: // float to fixed and fixed to float moves (no conversion) 3471 switch p.As { 3472 case ALDGR: 3473 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3474 case ALGDR: 3475 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3476 } 3477 3478 case 82: // fixed to float conversion 3479 var opcode uint32 3480 switch p.As { 3481 default: 3482 log.Fatalf("unexpected opcode %v", p.As) 3483 case ACEFBRA: 3484 opcode = op_CEFBRA 3485 case ACDFBRA: 3486 opcode = op_CDFBRA 3487 case ACEGBRA: 3488 opcode = op_CEGBRA 3489 case ACDGBRA: 3490 opcode = op_CDGBRA 3491 case ACELFBR: 3492 opcode = op_CELFBR 3493 case ACDLFBR: 3494 opcode = op_CDLFBR 3495 case ACELGBR: 3496 opcode = op_CELGBR 3497 case ACDLGBR: 3498 opcode = op_CDLGBR 3499 } 3500 // set immediate operand M3 to 0 to use the default BFP rounding mode 3501 // (usually round to nearest, ties to even) 3502 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3503 // M4 is reserved and must be 0 3504 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3505 3506 case 83: // float to fixed conversion 3507 var opcode uint32 3508 switch p.As { 3509 default: 3510 log.Fatalf("unexpected opcode %v", p.As) 3511 case ACFEBRA: 3512 opcode = op_CFEBRA 3513 case ACFDBRA: 3514 opcode = op_CFDBRA 3515 case ACGEBRA: 3516 opcode = op_CGEBRA 3517 case ACGDBRA: 3518 opcode = op_CGDBRA 3519 case ACLFEBR: 3520 opcode = op_CLFEBR 3521 case ACLFDBR: 3522 opcode = op_CLFDBR 3523 case ACLGEBR: 3524 opcode = op_CLGEBR 3525 case ACLGDBR: 3526 opcode = op_CLGDBR 3527 } 3528 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3529 // M4 is reserved and must be 0 3530 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3531 3532 case 84: // storage-and-storage operations $length mem mem 3533 l := c.regoff(&p.From) 3534 if l < 1 || l > 256 { 3535 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3536 } 3537 if p.From3.Index != 0 || p.To.Index != 0 { 3538 c.ctxt.Diag("cannot use index reg") 3539 } 3540 b1 := p.To.Reg 3541 b2 := p.From3.Reg 3542 if b1 == 0 { 3543 b1 = o.param 3544 } 3545 if b2 == 0 { 3546 b2 = o.param 3547 } 3548 d1 := c.regoff(&p.To) 3549 d2 := c.regoff(p.From3) 3550 if d1 < 0 || d1 >= DISP12 { 3551 if b2 == REGTMP { 3552 c.ctxt.Diag("REGTMP conflict") 3553 } 3554 if b1 != REGTMP { 3555 zRRE(op_LGR, REGTMP, uint32(b1), asm) 3556 } 3557 zRIL(_a, op_AGFI, REGTMP, uint32(d1), asm) 3558 if d1 == d2 && b1 == b2 { 3559 d2 = 0 3560 b2 = REGTMP 3561 } 3562 d1 = 0 3563 b1 = REGTMP 3564 } 3565 if d2 < 0 || d2 >= DISP12 { 3566 if b1 == REGTMP2 { 3567 c.ctxt.Diag("REGTMP2 conflict") 3568 } 3569 if b2 != REGTMP2 { 3570 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3571 } 3572 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3573 d2 = 0 3574 b2 = REGTMP2 3575 } 3576 var opcode uint32 3577 switch p.As { 3578 default: 3579 c.ctxt.Diag("unexpected opcode %v", p.As) 3580 case AMVC: 3581 opcode = op_MVC 3582 case ACLC: 3583 opcode = op_CLC 3584 // swap operand order for CLC so that it matches CMP 3585 b1, b2 = b2, b1 3586 d1, d2 = d2, d1 3587 case AXC: 3588 opcode = op_XC 3589 case AOC: 3590 opcode = op_OC 3591 case ANC: 3592 opcode = op_NC 3593 } 3594 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3595 3596 case 85: // load address relative long 3597 v := c.regoff(&p.From) 3598 if p.From.Sym == nil { 3599 if (v & 1) != 0 { 3600 c.ctxt.Diag("cannot use LARL with odd offset: %v", v) 3601 } 3602 } else { 3603 c.addrilreloc(p.From.Sym, int64(v)) 3604 v = 0 3605 } 3606 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3607 3608 case 86: // load address 3609 d := c.vregoff(&p.From) 3610 x := p.From.Index 3611 b := p.From.Reg 3612 if b == 0 { 3613 b = o.param 3614 } 3615 switch p.As { 3616 case ALA: 3617 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3618 case ALAY: 3619 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3620 } 3621 3622 case 87: // execute relative long 3623 v := c.vregoff(&p.From) 3624 if p.From.Sym == nil { 3625 if v&1 != 0 { 3626 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3627 } 3628 } else { 3629 c.addrilreloc(p.From.Sym, v) 3630 v = 0 3631 } 3632 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3633 3634 case 88: // store clock 3635 var opcode uint32 3636 switch p.As { 3637 case ASTCK: 3638 opcode = op_STCK 3639 case ASTCKC: 3640 opcode = op_STCKC 3641 case ASTCKE: 3642 opcode = op_STCKE 3643 case ASTCKF: 3644 opcode = op_STCKF 3645 } 3646 v := c.vregoff(&p.To) 3647 r := int(p.To.Reg) 3648 if r == 0 { 3649 r = int(o.param) 3650 } 3651 zS(opcode, uint32(r), uint32(v), asm) 3652 3653 case 89: // compare and branch reg reg 3654 var v int32 3655 if p.Pcond != nil { 3656 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3657 } 3658 var opcode, opcode2 uint32 3659 switch p.As { 3660 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3661 opcode = op_CGRJ 3662 opcode2 = op_CGR 3663 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3664 opcode = op_CLGRJ 3665 opcode2 = op_CLGR 3666 } 3667 mask := c.branchMask(p) 3668 if int32(int16(v)) != v { 3669 zRRE(opcode2, uint32(p.From.Reg), uint32(p.Reg), asm) 3670 zRIL(_c, op_BRCL, mask, uint32(v-sizeRRE/2), asm) 3671 } else { 3672 zRIE(_b, opcode, uint32(p.From.Reg), uint32(p.Reg), uint32(v), 0, 0, mask, 0, asm) 3673 } 3674 3675 case 90: // compare and branch reg $constant 3676 var v int32 3677 if p.Pcond != nil { 3678 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3679 } 3680 var opcode, opcode2 uint32 3681 switch p.As { 3682 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3683 opcode = op_CGIJ 3684 opcode2 = op_CGFI 3685 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3686 opcode = op_CLGIJ 3687 opcode2 = op_CLGFI 3688 } 3689 mask := c.branchMask(p) 3690 if int32(int16(v)) != v { 3691 zRIL(_a, opcode2, uint32(p.From.Reg), uint32(c.regoff(p.From3)), asm) 3692 zRIL(_c, op_BRCL, mask, uint32(v-sizeRIL/2), asm) 3693 } else { 3694 zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(c.regoff(p.From3)), asm) 3695 } 3696 3697 case 93: // GOT lookup 3698 v := c.vregoff(&p.To) 3699 if v != 0 { 3700 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3701 } 3702 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3703 rel := obj.Addrel(c.cursym) 3704 rel.Off = int32(c.pc + 2) 3705 rel.Siz = 4 3706 rel.Sym = p.From.Sym 3707 rel.Type = objabi.R_GOTPCREL 3708 rel.Add = 2 + int64(rel.Siz) 3709 3710 case 94: // TLS local exec model 3711 zRIL(_b, op_LARL, REGTMP, (sizeRIL+sizeRXY+sizeRI)>>1, asm) 3712 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3713 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 3714 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 3715 rel := obj.Addrel(c.cursym) 3716 rel.Off = int32(c.pc + sizeRIL + sizeRXY + sizeRI) 3717 rel.Siz = 8 3718 rel.Sym = p.From.Sym 3719 rel.Type = objabi.R_TLS_LE 3720 rel.Add = 0 3721 3722 case 95: // TLS initial exec model 3723 // Assembly | Relocation symbol | Done Here? 3724 // -------------------------------------------------------------- 3725 // ear %r11, %a0 | | 3726 // sllg %r11, %r11, 32 | | 3727 // ear %r11, %a1 | | 3728 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 3729 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 3730 // la %r10, 0(%r10, %r11) | | 3731 // -------------------------------------------------------------- 3732 3733 // R_390_TLS_IEENT 3734 zRIL(_b, op_LARL, REGTMP, 0, asm) 3735 ieent := obj.Addrel(c.cursym) 3736 ieent.Off = int32(c.pc + 2) 3737 ieent.Siz = 4 3738 ieent.Sym = p.From.Sym 3739 ieent.Type = objabi.R_TLS_IE 3740 ieent.Add = 2 + int64(ieent.Siz) 3741 3742 // R_390_TLS_LOAD 3743 zRXY(op_LGF, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3744 // TODO(mundaym): add R_390_TLS_LOAD relocation here 3745 // not strictly required but might allow the linker to optimize 3746 3747 case 96: // clear macro 3748 length := c.vregoff(&p.From) 3749 offset := c.vregoff(&p.To) 3750 reg := p.To.Reg 3751 if reg == 0 { 3752 reg = o.param 3753 } 3754 if length <= 0 { 3755 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 3756 } 3757 for length > 0 { 3758 if offset < 0 || offset >= DISP12 { 3759 if offset >= -DISP20/2 && offset < DISP20/2 { 3760 zRXY(op_LAY, REGTMP, uint32(reg), 0, uint32(offset), asm) 3761 } else { 3762 if reg != REGTMP { 3763 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3764 } 3765 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3766 } 3767 reg = REGTMP 3768 offset = 0 3769 } 3770 size := length 3771 if size > 256 { 3772 size = 256 3773 } 3774 3775 switch size { 3776 case 1: 3777 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 3778 case 2: 3779 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 3780 case 4: 3781 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 3782 case 8: 3783 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 3784 default: 3785 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 3786 } 3787 3788 length -= size 3789 offset += size 3790 } 3791 3792 case 97: // store multiple 3793 rstart := p.From.Reg 3794 rend := p.Reg 3795 offset := c.regoff(&p.To) 3796 reg := p.To.Reg 3797 if reg == 0 { 3798 reg = o.param 3799 } 3800 if offset < -DISP20/2 || offset >= DISP20/2 { 3801 if reg != REGTMP { 3802 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3803 } 3804 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3805 reg = REGTMP 3806 offset = 0 3807 } 3808 switch p.As { 3809 case ASTMY: 3810 if offset >= 0 && offset < DISP12 { 3811 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3812 } else { 3813 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3814 } 3815 case ASTMG: 3816 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3817 } 3818 3819 case 98: // load multiple 3820 rstart := p.Reg 3821 rend := p.To.Reg 3822 offset := c.regoff(&p.From) 3823 reg := p.From.Reg 3824 if reg == 0 { 3825 reg = o.param 3826 } 3827 if offset < -DISP20/2 || offset >= DISP20/2 { 3828 if reg != REGTMP { 3829 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3830 } 3831 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3832 reg = REGTMP 3833 offset = 0 3834 } 3835 switch p.As { 3836 case ALMY: 3837 if offset >= 0 && offset < DISP12 { 3838 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3839 } else { 3840 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3841 } 3842 case ALMG: 3843 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3844 } 3845 3846 case 99: // interlocked load and op 3847 if p.To.Index != 0 { 3848 c.ctxt.Diag("cannot use indexed address") 3849 } 3850 offset := c.regoff(&p.To) 3851 if offset < -DISP20/2 || offset >= DISP20/2 { 3852 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset) 3853 } 3854 var opcode uint32 3855 switch p.As { 3856 case ALAA: 3857 opcode = op_LAA 3858 case ALAAG: 3859 opcode = op_LAAG 3860 case ALAAL: 3861 opcode = op_LAAL 3862 case ALAALG: 3863 opcode = op_LAALG 3864 case ALAN: 3865 opcode = op_LAN 3866 case ALANG: 3867 opcode = op_LANG 3868 case ALAX: 3869 opcode = op_LAX 3870 case ALAXG: 3871 opcode = op_LAXG 3872 case ALAO: 3873 opcode = op_LAO 3874 case ALAOG: 3875 opcode = op_LAOG 3876 } 3877 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm) 3878 3879 case 100: // VRX STORE 3880 op, m3, _ := vop(p.As) 3881 v1 := p.From.Reg 3882 if p.Reg != 0 { 3883 m3 = uint32(c.vregoff(&p.From)) 3884 v1 = p.Reg 3885 } 3886 b2 := p.To.Reg 3887 if b2 == 0 { 3888 b2 = o.param 3889 } 3890 d2 := uint32(c.vregoff(&p.To)) 3891 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3892 3893 case 101: // VRX LOAD 3894 op, m3, _ := vop(p.As) 3895 src := &p.From 3896 if p.From3 != nil { 3897 m3 = uint32(c.vregoff(&p.From)) 3898 src = p.From3 3899 } 3900 b2 := src.Reg 3901 if b2 == 0 { 3902 b2 = o.param 3903 } 3904 d2 := uint32(c.vregoff(src)) 3905 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm) 3906 3907 case 102: // VRV SCATTER 3908 op, _, _ := vop(p.As) 3909 m3 := uint32(c.vregoff(&p.From)) 3910 b2 := p.To.Reg 3911 if b2 == 0 { 3912 b2 = o.param 3913 } 3914 d2 := uint32(c.vregoff(&p.To)) 3915 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3916 3917 case 103: // VRV GATHER 3918 op, _, _ := vop(p.As) 3919 m3 := uint32(c.vregoff(&p.From)) 3920 b2 := p.From3.Reg 3921 if b2 == 0 { 3922 b2 = o.param 3923 } 3924 d2 := uint32(c.vregoff(p.From3)) 3925 zVRV(op, uint32(p.To.Reg), uint32(p.From3.Index), uint32(b2), d2, m3, asm) 3926 3927 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 3928 op, m4, _ := vop(p.As) 3929 fr := p.Reg 3930 if fr == 0 { 3931 fr = p.To.Reg 3932 } 3933 bits := uint32(c.vregoff(&p.From)) 3934 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 3935 3936 case 105: // VRS STORE MULTIPLE 3937 op, _, _ := vop(p.As) 3938 offset := uint32(c.vregoff(&p.To)) 3939 reg := p.To.Reg 3940 if reg == 0 { 3941 reg = o.param 3942 } 3943 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 3944 3945 case 106: // VRS LOAD MULTIPLE 3946 op, _, _ := vop(p.As) 3947 offset := uint32(c.vregoff(&p.From)) 3948 reg := p.From.Reg 3949 if reg == 0 { 3950 reg = o.param 3951 } 3952 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 3953 3954 case 107: // VRS STORE WITH LENGTH 3955 op, _, _ := vop(p.As) 3956 offset := uint32(c.vregoff(&p.To)) 3957 reg := p.To.Reg 3958 if reg == 0 { 3959 reg = o.param 3960 } 3961 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 3962 3963 case 108: // VRS LOAD WITH LENGTH 3964 op, _, _ := vop(p.As) 3965 offset := uint32(c.vregoff(p.From3)) 3966 reg := p.From3.Reg 3967 if reg == 0 { 3968 reg = o.param 3969 } 3970 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm) 3971 3972 case 109: // VRI-a 3973 op, m3, _ := vop(p.As) 3974 i2 := uint32(c.vregoff(&p.From)) 3975 if p.From3 != nil { 3976 m3 = uint32(c.vregoff(&p.From)) 3977 i2 = uint32(c.vregoff(p.From3)) 3978 } 3979 switch p.As { 3980 case AVZERO: 3981 i2 = 0 3982 case AVONE: 3983 i2 = 0xffff 3984 } 3985 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 3986 3987 case 110: 3988 op, m4, _ := vop(p.As) 3989 i2 := uint32(c.vregoff(&p.From)) 3990 i3 := uint32(c.vregoff(p.From3)) 3991 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 3992 3993 case 111: 3994 op, m4, _ := vop(p.As) 3995 i2 := uint32(c.vregoff(&p.From)) 3996 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 3997 3998 case 112: 3999 op, m5, _ := vop(p.As) 4000 i4 := uint32(c.vregoff(&p.From)) 4001 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), i4, m5, asm) 4002 4003 case 113: 4004 op, m4, _ := vop(p.As) 4005 m5 := singleElementMask(p.As) 4006 i3 := uint32(c.vregoff(&p.From)) 4007 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 4008 4009 case 114: // VRR-a 4010 op, m3, m5 := vop(p.As) 4011 m4 := singleElementMask(p.As) 4012 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 4013 4014 case 115: // VRR-a COMPARE 4015 op, m3, m5 := vop(p.As) 4016 m4 := singleElementMask(p.As) 4017 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 4018 4019 case 117: // VRR-b 4020 op, m4, m5 := vop(p.As) 4021 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 4022 4023 case 118: // VRR-c 4024 op, m4, m6 := vop(p.As) 4025 m5 := singleElementMask(p.As) 4026 v3 := p.Reg 4027 if v3 == 0 { 4028 v3 = p.To.Reg 4029 } 4030 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 4031 4032 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 4033 op, m4, m6 := vop(p.As) 4034 m5 := singleElementMask(p.As) 4035 v2 := p.Reg 4036 if v2 == 0 { 4037 v2 = p.To.Reg 4038 } 4039 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 4040 4041 case 120: // VRR-d 4042 op, m6, _ := vop(p.As) 4043 m5 := singleElementMask(p.As) 4044 v1 := uint32(p.To.Reg) 4045 v2 := uint32(p.From.Reg) 4046 v3 := uint32(p.Reg) 4047 v4 := uint32(p.From3.Reg) 4048 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 4049 4050 case 121: // VRR-e 4051 op, m6, _ := vop(p.As) 4052 m5 := singleElementMask(p.As) 4053 v1 := uint32(p.To.Reg) 4054 v2 := uint32(p.From.Reg) 4055 v3 := uint32(p.Reg) 4056 v4 := uint32(p.From3.Reg) 4057 zVRRe(op, v1, v2, v3, m6, m5, v4, asm) 4058 4059 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 4060 op, _, _ := vop(p.As) 4061 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 4062 4063 case 123: // VPDI $m4, V2, V3, V1 4064 op, _, _ := vop(p.As) 4065 m4 := c.regoff(&p.From) 4066 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), 0, 0, uint32(m4), asm) 4067 } 4068 } 4069 4070 func (c *ctxtz) vregoff(a *obj.Addr) int64 { 4071 c.instoffset = 0 4072 if a != nil { 4073 c.aclass(a) 4074 } 4075 return c.instoffset 4076 } 4077 4078 func (c *ctxtz) regoff(a *obj.Addr) int32 { 4079 return int32(c.vregoff(a)) 4080 } 4081 4082 // zopload returns the RXY op for the given load 4083 func (c *ctxtz) zopload(a obj.As) uint32 { 4084 switch a { 4085 // fixed point load 4086 case AMOVD: 4087 return op_LG 4088 case AMOVW: 4089 return op_LGF 4090 case AMOVWZ: 4091 return op_LLGF 4092 case AMOVH: 4093 return op_LGH 4094 case AMOVHZ: 4095 return op_LLGH 4096 case AMOVB: 4097 return op_LGB 4098 case AMOVBZ: 4099 return op_LLGC 4100 4101 // floating point load 4102 case AFMOVD: 4103 return op_LDY 4104 case AFMOVS: 4105 return op_LEY 4106 4107 // byte reversed load 4108 case AMOVDBR: 4109 return op_LRVG 4110 case AMOVWBR: 4111 return op_LRV 4112 case AMOVHBR: 4113 return op_LRVH 4114 } 4115 4116 c.ctxt.Diag("unknown store opcode %v", a) 4117 return 0 4118 } 4119 4120 // zopstore returns the RXY op for the given store 4121 func (c *ctxtz) zopstore(a obj.As) uint32 { 4122 switch a { 4123 // fixed point store 4124 case AMOVD: 4125 return op_STG 4126 case AMOVW, AMOVWZ: 4127 return op_STY 4128 case AMOVH, AMOVHZ: 4129 return op_STHY 4130 case AMOVB, AMOVBZ: 4131 return op_STCY 4132 4133 // floating point store 4134 case AFMOVD: 4135 return op_STDY 4136 case AFMOVS: 4137 return op_STEY 4138 4139 // byte reversed store 4140 case AMOVDBR: 4141 return op_STRVG 4142 case AMOVWBR: 4143 return op_STRV 4144 case AMOVHBR: 4145 return op_STRVH 4146 } 4147 4148 c.ctxt.Diag("unknown store opcode %v", a) 4149 return 0 4150 } 4151 4152 // zoprre returns the RRE op for the given a 4153 func (c *ctxtz) zoprre(a obj.As) uint32 { 4154 switch a { 4155 case ACMP: 4156 return op_CGR 4157 case ACMPU: 4158 return op_CLGR 4159 case AFCMPO: //ordered 4160 return op_KDBR 4161 case AFCMPU: //unordered 4162 return op_CDBR 4163 case ACEBR: 4164 return op_CEBR 4165 } 4166 c.ctxt.Diag("unknown rre opcode %v", a) 4167 return 0 4168 } 4169 4170 // zoprr returns the RR op for the given a 4171 func (c *ctxtz) zoprr(a obj.As) uint32 { 4172 switch a { 4173 case ACMPW: 4174 return op_CR 4175 case ACMPWU: 4176 return op_CLR 4177 } 4178 c.ctxt.Diag("unknown rr opcode %v", a) 4179 return 0 4180 } 4181 4182 // zopril returns the RIL op for the given a 4183 func (c *ctxtz) zopril(a obj.As) uint32 { 4184 switch a { 4185 case ACMP: 4186 return op_CGFI 4187 case ACMPU: 4188 return op_CLGFI 4189 case ACMPW: 4190 return op_CFI 4191 case ACMPWU: 4192 return op_CLFI 4193 } 4194 c.ctxt.Diag("unknown ril opcode %v", a) 4195 return 0 4196 } 4197 4198 // z instructions sizes 4199 const ( 4200 sizeE = 2 4201 sizeI = 2 4202 sizeIE = 4 4203 sizeMII = 6 4204 sizeRI = 4 4205 sizeRI1 = 4 4206 sizeRI2 = 4 4207 sizeRI3 = 4 4208 sizeRIE = 6 4209 sizeRIE1 = 6 4210 sizeRIE2 = 6 4211 sizeRIE3 = 6 4212 sizeRIE4 = 6 4213 sizeRIE5 = 6 4214 sizeRIE6 = 6 4215 sizeRIL = 6 4216 sizeRIL1 = 6 4217 sizeRIL2 = 6 4218 sizeRIL3 = 6 4219 sizeRIS = 6 4220 sizeRR = 2 4221 sizeRRD = 4 4222 sizeRRE = 4 4223 sizeRRF = 4 4224 sizeRRF1 = 4 4225 sizeRRF2 = 4 4226 sizeRRF3 = 4 4227 sizeRRF4 = 4 4228 sizeRRF5 = 4 4229 sizeRRR = 2 4230 sizeRRS = 6 4231 sizeRS = 4 4232 sizeRS1 = 4 4233 sizeRS2 = 4 4234 sizeRSI = 4 4235 sizeRSL = 6 4236 sizeRSY = 6 4237 sizeRSY1 = 6 4238 sizeRSY2 = 6 4239 sizeRX = 4 4240 sizeRX1 = 4 4241 sizeRX2 = 4 4242 sizeRXE = 6 4243 sizeRXF = 6 4244 sizeRXY = 6 4245 sizeRXY1 = 6 4246 sizeRXY2 = 6 4247 sizeS = 4 4248 sizeSI = 4 4249 sizeSIL = 6 4250 sizeSIY = 6 4251 sizeSMI = 6 4252 sizeSS = 6 4253 sizeSS1 = 6 4254 sizeSS2 = 6 4255 sizeSS3 = 6 4256 sizeSS4 = 6 4257 sizeSS5 = 6 4258 sizeSS6 = 6 4259 sizeSSE = 6 4260 sizeSSF = 6 4261 ) 4262 4263 // instruction format variations 4264 type form int 4265 4266 const ( 4267 _a form = iota 4268 _b 4269 _c 4270 _d 4271 _e 4272 _f 4273 ) 4274 4275 func zE(op uint32, asm *[]byte) { 4276 *asm = append(*asm, uint8(op>>8), uint8(op)) 4277 } 4278 4279 func zI(op, i1 uint32, asm *[]byte) { 4280 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4281 } 4282 4283 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4284 *asm = append(*asm, 4285 uint8(op>>8), 4286 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4287 uint8(ri2), 4288 uint8(ri3>>16), 4289 uint8(ri3>>8), 4290 uint8(ri3)) 4291 } 4292 4293 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4294 *asm = append(*asm, 4295 uint8(op>>8), 4296 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4297 uint8(i2_ri2>>8), 4298 uint8(i2_ri2)) 4299 } 4300 4301 // Expected argument values for the instruction formats. 4302 // 4303 // Format a1 a2 a3 a4 a5 a6 a7 4304 // ------------------------------------ 4305 // a r1, 0, i2, 0, 0, m3, 0 4306 // b r1, r2, ri4, 0, 0, m3, 0 4307 // c r1, m3, ri4, 0, 0, 0, i2 4308 // d r1, r3, i2, 0, 0, 0, 0 4309 // e r1, r3, ri2, 0, 0, 0, 0 4310 // f r1, r2, 0, i3, i4, 0, i5 4311 // g r1, m3, i2, 0, 0, 0, 0 4312 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4313 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4314 4315 switch f { 4316 default: 4317 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4318 case _f: 4319 *asm = append(*asm, uint8(i3), uint8(i4)) 4320 } 4321 4322 switch f { 4323 case _a, _b: 4324 *asm = append(*asm, uint8(m3)<<4) 4325 default: 4326 *asm = append(*asm, uint8(i2_i5)) 4327 } 4328 4329 *asm = append(*asm, uint8(op)) 4330 } 4331 4332 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4333 if f == _a || f == _b { 4334 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4335 } 4336 *asm = append(*asm, 4337 uint8(op>>8), 4338 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4339 uint8(i2_ri2>>24), 4340 uint8(i2_ri2>>16), 4341 uint8(i2_ri2>>8), 4342 uint8(i2_ri2)) 4343 } 4344 4345 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4346 *asm = append(*asm, 4347 uint8(op>>8), 4348 (uint8(r1)<<4)|uint8(m3&0x0F), 4349 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4350 uint8(d4), 4351 uint8(i2), 4352 uint8(op)) 4353 } 4354 4355 func zRR(op, r1, r2 uint32, asm *[]byte) { 4356 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4357 } 4358 4359 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4360 *asm = append(*asm, 4361 uint8(op>>8), 4362 uint8(op), 4363 uint8(r1)<<4, 4364 (uint8(r3)<<4)|uint8(r2&0x0F)) 4365 } 4366 4367 func zRRE(op, r1, r2 uint32, asm *[]byte) { 4368 *asm = append(*asm, 4369 uint8(op>>8), 4370 uint8(op), 4371 0, 4372 (uint8(r1)<<4)|uint8(r2&0x0F)) 4373 } 4374 4375 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4376 *asm = append(*asm, 4377 uint8(op>>8), 4378 uint8(op), 4379 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4380 (uint8(r1)<<4)|uint8(r2&0x0F)) 4381 } 4382 4383 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4384 *asm = append(*asm, 4385 uint8(op>>8), 4386 (uint8(r1)<<4)|uint8(r2&0x0F), 4387 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4388 uint8(d4), 4389 uint8(m3)<<4, 4390 uint8(op)) 4391 } 4392 4393 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4394 *asm = append(*asm, 4395 uint8(op>>8), 4396 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4397 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4398 uint8(d2)) 4399 } 4400 4401 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4402 *asm = append(*asm, 4403 uint8(op>>8), 4404 (uint8(r1)<<4)|uint8(r3&0x0F), 4405 uint8(ri2>>8), 4406 uint8(ri2)) 4407 } 4408 4409 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4410 *asm = append(*asm, 4411 uint8(op>>8), 4412 uint8(l1), 4413 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4414 uint8(d2), 4415 uint8(op)) 4416 } 4417 4418 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4419 dl2 := uint16(d2) & 0x0FFF 4420 *asm = append(*asm, 4421 uint8(op>>8), 4422 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4423 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4424 uint8(dl2), 4425 uint8(d2>>12), 4426 uint8(op)) 4427 } 4428 4429 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4430 *asm = append(*asm, 4431 uint8(op>>8), 4432 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4433 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4434 uint8(d2)) 4435 } 4436 4437 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4438 *asm = append(*asm, 4439 uint8(op>>8), 4440 (uint8(r1)<<4)|uint8(x2&0x0F), 4441 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4442 uint8(d2), 4443 uint8(m3)<<4, 4444 uint8(op)) 4445 } 4446 4447 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4448 *asm = append(*asm, 4449 uint8(op>>8), 4450 (uint8(r3)<<4)|uint8(x2&0x0F), 4451 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4452 uint8(d2), 4453 uint8(m1)<<4, 4454 uint8(op)) 4455 } 4456 4457 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4458 dl2 := uint16(d2) & 0x0FFF 4459 *asm = append(*asm, 4460 uint8(op>>8), 4461 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4462 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4463 uint8(dl2), 4464 uint8(d2>>12), 4465 uint8(op)) 4466 } 4467 4468 func zS(op, b2, d2 uint32, asm *[]byte) { 4469 *asm = append(*asm, 4470 uint8(op>>8), 4471 uint8(op), 4472 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4473 uint8(d2)) 4474 } 4475 4476 func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4477 *asm = append(*asm, 4478 uint8(op>>8), 4479 uint8(i2), 4480 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4481 uint8(d1)) 4482 } 4483 4484 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4485 *asm = append(*asm, 4486 uint8(op>>8), 4487 uint8(op), 4488 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4489 uint8(d1), 4490 uint8(i2>>8), 4491 uint8(i2)) 4492 } 4493 4494 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4495 dl1 := uint16(d1) & 0x0FFF 4496 *asm = append(*asm, 4497 uint8(op>>8), 4498 uint8(i2), 4499 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4500 uint8(dl1), 4501 uint8(d1>>12), 4502 uint8(op)) 4503 } 4504 4505 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4506 *asm = append(*asm, 4507 uint8(op>>8), 4508 uint8(m1)<<4, 4509 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4510 uint8(d3), 4511 uint8(ri2>>8), 4512 uint8(ri2)) 4513 } 4514 4515 // Expected argument values for the instruction formats. 4516 // 4517 // Format a1 a2 a3 a4 a5 a6 4518 // ------------------------------- 4519 // a l1, 0, b1, d1, b2, d2 4520 // b l1, l2, b1, d1, b2, d2 4521 // c l1, i3, b1, d1, b2, d2 4522 // d r1, r3, b1, d1, b2, d2 4523 // e r1, r3, b2, d2, b4, d4 4524 // f 0, l2, b1, d1, b2, d2 4525 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4526 *asm = append(*asm, uint8(op>>8)) 4527 4528 switch f { 4529 case _a: 4530 *asm = append(*asm, uint8(l1_r1)) 4531 case _b, _c, _d, _e: 4532 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4533 case _f: 4534 *asm = append(*asm, uint8(l2_i3_r3)) 4535 } 4536 4537 *asm = append(*asm, 4538 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4539 uint8(d1_d2), 4540 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4541 uint8(d2_d4)) 4542 } 4543 4544 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4545 *asm = append(*asm, 4546 uint8(op>>8), 4547 uint8(op), 4548 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4549 uint8(d1), 4550 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4551 uint8(d2)) 4552 } 4553 4554 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4555 *asm = append(*asm, 4556 uint8(op>>8), 4557 (uint8(r3)<<4)|(uint8(op)&0x0F), 4558 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4559 uint8(d1), 4560 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4561 uint8(d2)) 4562 } 4563 4564 func rxb(va, vb, vc, vd uint32) uint8 { 4565 mask := uint8(0) 4566 if va >= REG_V16 && va <= REG_V31 { 4567 mask |= 0x8 4568 } 4569 if vb >= REG_V16 && vb <= REG_V31 { 4570 mask |= 0x4 4571 } 4572 if vc >= REG_V16 && vc <= REG_V31 { 4573 mask |= 0x2 4574 } 4575 if vd >= REG_V16 && vd <= REG_V31 { 4576 mask |= 0x1 4577 } 4578 return mask 4579 } 4580 4581 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 4582 *asm = append(*asm, 4583 uint8(op>>8), 4584 (uint8(v1)<<4)|(uint8(x2)&0xf), 4585 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4586 uint8(d2), 4587 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4588 uint8(op)) 4589 } 4590 4591 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 4592 *asm = append(*asm, 4593 uint8(op>>8), 4594 (uint8(v1)<<4)|(uint8(v2)&0xf), 4595 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4596 uint8(d2), 4597 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4598 uint8(op)) 4599 } 4600 4601 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 4602 *asm = append(*asm, 4603 uint8(op>>8), 4604 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 4605 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4606 uint8(d2), 4607 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 4608 uint8(op)) 4609 } 4610 4611 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 4612 *asm = append(*asm, 4613 uint8(op>>8), 4614 (uint8(v1)<<4)|(uint8(v2)&0xf), 4615 0, 4616 (uint8(m5)<<4)|(uint8(m4)&0xf), 4617 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4618 uint8(op)) 4619 } 4620 4621 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 4622 *asm = append(*asm, 4623 uint8(op>>8), 4624 (uint8(v1)<<4)|(uint8(v2)&0xf), 4625 uint8(v3)<<4, 4626 uint8(m5)<<4, 4627 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4628 uint8(op)) 4629 } 4630 4631 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 4632 *asm = append(*asm, 4633 uint8(op>>8), 4634 (uint8(v1)<<4)|(uint8(v2)&0xf), 4635 uint8(v3)<<4, 4636 (uint8(m6)<<4)|(uint8(m5)&0xf), 4637 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4638 uint8(op)) 4639 } 4640 4641 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 4642 *asm = append(*asm, 4643 uint8(op>>8), 4644 (uint8(v1)<<4)|(uint8(v2)&0xf), 4645 (uint8(v3)<<4)|(uint8(m5)&0xf), 4646 uint8(m6)<<4, 4647 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4648 uint8(op)) 4649 } 4650 4651 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 4652 *asm = append(*asm, 4653 uint8(op>>8), 4654 (uint8(v1)<<4)|(uint8(v2)&0xf), 4655 (uint8(v3)<<4)|(uint8(m6)&0xf), 4656 uint8(m5), 4657 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4658 uint8(op)) 4659 } 4660 4661 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 4662 *asm = append(*asm, 4663 uint8(op>>8), 4664 (uint8(v1)<<4)|(uint8(r2)&0xf), 4665 uint8(r3)<<4, 4666 0, 4667 rxb(v1, 0, 0, 0), 4668 uint8(op)) 4669 } 4670 4671 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 4672 *asm = append(*asm, 4673 uint8(op>>8), 4674 uint8(v1)<<4, 4675 uint8(i2>>8), 4676 uint8(i2), 4677 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4678 uint8(op)) 4679 } 4680 4681 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 4682 *asm = append(*asm, 4683 uint8(op>>8), 4684 uint8(v1)<<4, 4685 uint8(i2), 4686 uint8(i3), 4687 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 4688 uint8(op)) 4689 } 4690 4691 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 4692 *asm = append(*asm, 4693 uint8(op>>8), 4694 (uint8(v1)<<4)|(uint8(v3)&0xf), 4695 uint8(i2>>8), 4696 uint8(i2), 4697 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 4698 uint8(op)) 4699 } 4700 4701 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 4702 *asm = append(*asm, 4703 uint8(op>>8), 4704 (uint8(v1)<<4)|(uint8(v2)&0xf), 4705 uint8(v3)<<4, 4706 uint8(i4), 4707 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 4708 uint8(op)) 4709 } 4710 4711 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 4712 *asm = append(*asm, 4713 uint8(op>>8), 4714 (uint8(v1)<<4)|(uint8(v2)&0xf), 4715 uint8(i3>>4), 4716 (uint8(i3)<<4)|(uint8(m5)&0xf), 4717 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 4718 uint8(op)) 4719 }