github.com/zxy12/go_duplicate_1_12@v0.0.0-20200217043740-b1636fc0368b/src/cmd/internal/obj/ppc64/a.out.go (about) 1 // cmd/9c/9.out.h from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import "cmd/internal/obj" 33 34 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64 35 36 /* 37 * powerpc 64 38 */ 39 const ( 40 NSNAME = 8 41 NSYM = 50 42 NREG = 32 /* number of general registers */ 43 NFREG = 32 /* number of floating point registers */ 44 ) 45 46 const ( 47 /* RBasePPC64 = 4096 */ 48 /* R0=4096 ... R31=4127 */ 49 REG_R0 = obj.RBasePPC64 + iota 50 REG_R1 51 REG_R2 52 REG_R3 53 REG_R4 54 REG_R5 55 REG_R6 56 REG_R7 57 REG_R8 58 REG_R9 59 REG_R10 60 REG_R11 61 REG_R12 62 REG_R13 63 REG_R14 64 REG_R15 65 REG_R16 66 REG_R17 67 REG_R18 68 REG_R19 69 REG_R20 70 REG_R21 71 REG_R22 72 REG_R23 73 REG_R24 74 REG_R25 75 REG_R26 76 REG_R27 77 REG_R28 78 REG_R29 79 REG_R30 80 REG_R31 81 82 /* F0=4128 ... F31=4159 */ 83 REG_F0 84 REG_F1 85 REG_F2 86 REG_F3 87 REG_F4 88 REG_F5 89 REG_F6 90 REG_F7 91 REG_F8 92 REG_F9 93 REG_F10 94 REG_F11 95 REG_F12 96 REG_F13 97 REG_F14 98 REG_F15 99 REG_F16 100 REG_F17 101 REG_F18 102 REG_F19 103 REG_F20 104 REG_F21 105 REG_F22 106 REG_F23 107 REG_F24 108 REG_F25 109 REG_F26 110 REG_F27 111 REG_F28 112 REG_F29 113 REG_F30 114 REG_F31 115 116 /* V0=4160 ... V31=4191 */ 117 REG_V0 118 REG_V1 119 REG_V2 120 REG_V3 121 REG_V4 122 REG_V5 123 REG_V6 124 REG_V7 125 REG_V8 126 REG_V9 127 REG_V10 128 REG_V11 129 REG_V12 130 REG_V13 131 REG_V14 132 REG_V15 133 REG_V16 134 REG_V17 135 REG_V18 136 REG_V19 137 REG_V20 138 REG_V21 139 REG_V22 140 REG_V23 141 REG_V24 142 REG_V25 143 REG_V26 144 REG_V27 145 REG_V28 146 REG_V29 147 REG_V30 148 REG_V31 149 150 /* VS0=4192 ... VS63=4255 */ 151 REG_VS0 152 REG_VS1 153 REG_VS2 154 REG_VS3 155 REG_VS4 156 REG_VS5 157 REG_VS6 158 REG_VS7 159 REG_VS8 160 REG_VS9 161 REG_VS10 162 REG_VS11 163 REG_VS12 164 REG_VS13 165 REG_VS14 166 REG_VS15 167 REG_VS16 168 REG_VS17 169 REG_VS18 170 REG_VS19 171 REG_VS20 172 REG_VS21 173 REG_VS22 174 REG_VS23 175 REG_VS24 176 REG_VS25 177 REG_VS26 178 REG_VS27 179 REG_VS28 180 REG_VS29 181 REG_VS30 182 REG_VS31 183 REG_VS32 184 REG_VS33 185 REG_VS34 186 REG_VS35 187 REG_VS36 188 REG_VS37 189 REG_VS38 190 REG_VS39 191 REG_VS40 192 REG_VS41 193 REG_VS42 194 REG_VS43 195 REG_VS44 196 REG_VS45 197 REG_VS46 198 REG_VS47 199 REG_VS48 200 REG_VS49 201 REG_VS50 202 REG_VS51 203 REG_VS52 204 REG_VS53 205 REG_VS54 206 REG_VS55 207 REG_VS56 208 REG_VS57 209 REG_VS58 210 REG_VS59 211 REG_VS60 212 REG_VS61 213 REG_VS62 214 REG_VS63 215 216 REG_CR0 217 REG_CR1 218 REG_CR2 219 REG_CR3 220 REG_CR4 221 REG_CR5 222 REG_CR6 223 REG_CR7 224 225 REG_MSR 226 REG_FPSCR 227 REG_CR 228 229 REG_SPECIAL = REG_CR0 230 231 REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers 232 REG_DCR0 = obj.RBasePPC64 + 2048 // first of 1024 registers 233 234 REG_XER = REG_SPR0 + 1 235 REG_LR = REG_SPR0 + 8 236 REG_CTR = REG_SPR0 + 9 237 238 REGZERO = REG_R0 /* set to zero */ 239 REGSP = REG_R1 240 REGSB = REG_R2 241 REGRET = REG_R3 242 REGARG = -1 /* -1 disables passing the first argument in register */ 243 REGRT1 = REG_R3 /* reserved for runtime, duffzero and duffcopy */ 244 REGRT2 = REG_R4 /* reserved for runtime, duffcopy */ 245 REGMIN = REG_R7 /* register variables allocated from here to REGMAX */ 246 REGCTXT = REG_R11 /* context for closures */ 247 REGTLS = REG_R13 /* C ABI TLS base pointer */ 248 REGMAX = REG_R27 249 REGEXT = REG_R30 /* external registers allocated from here down */ 250 REGG = REG_R30 /* G */ 251 REGTMP = REG_R31 /* used by the linker */ 252 FREGRET = REG_F0 253 FREGMIN = REG_F17 /* first register variable */ 254 FREGMAX = REG_F26 /* last register variable for 9g only */ 255 FREGEXT = REG_F26 /* first external register */ 256 ) 257 258 // OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI 259 // https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture 260 var PPC64DWARFRegisters = map[int16]int16{} 261 262 func init() { 263 // f assigns dwarfregister[from:to] = (base):(to-from+base) 264 f := func(from, to, base int16) { 265 for r := int16(from); r <= to; r++ { 266 PPC64DWARFRegisters[r] = r - from + base 267 } 268 } 269 f(REG_R0, REG_R31, 0) 270 f(REG_F0, REG_F31, 32) 271 f(REG_V0, REG_V31, 77) 272 f(REG_CR0, REG_CR7, 68) 273 274 f(REG_VS0, REG_VS31, 32) // overlaps F0-F31 275 f(REG_VS32, REG_VS63, 77) // overlaps V0-V31 276 PPC64DWARFRegisters[REG_LR] = 65 277 PPC64DWARFRegisters[REG_CTR] = 66 278 PPC64DWARFRegisters[REG_XER] = 76 279 } 280 281 /* 282 * GENERAL: 283 * 284 * compiler allocates R3 up as temps 285 * compiler allocates register variables R7-R27 286 * compiler allocates external registers R30 down 287 * 288 * compiler allocates register variables F17-F26 289 * compiler allocates external registers F26 down 290 */ 291 const ( 292 BIG = 32768 - 8 293 ) 294 295 const ( 296 /* mark flags */ 297 LABEL = 1 << 0 298 LEAF = 1 << 1 299 FLOAT = 1 << 2 300 BRANCH = 1 << 3 301 LOAD = 1 << 4 302 FCMP = 1 << 5 303 SYNC = 1 << 6 304 LIST = 1 << 7 305 FOLL = 1 << 8 306 NOSCHED = 1 << 9 307 ) 308 309 // Values for use in branch instruction BC 310 // BC B0,BI,label 311 // BO is type of branch + likely bits described below 312 // BI is CR value + branch type 313 // ex: BEQ CR2,label is BC 12,10,label 314 // 12 = BO_BCR 315 // 10 = BI_CR2 + BI_EQ 316 317 const ( 318 BI_CR0 = 0 319 BI_CR1 = 4 320 BI_CR2 = 8 321 BI_CR3 = 12 322 BI_CR4 = 16 323 BI_CR5 = 20 324 BI_CR6 = 24 325 BI_CR7 = 28 326 BI_LT = 0 327 BI_GT = 1 328 BI_EQ = 2 329 BI_OVF = 3 330 ) 331 332 // Values for the BO field. Add the branch type to 333 // the likely bits, if a likely setting is known. 334 // If branch likely or unlikely is not known, don't set it. 335 // e.g. branch on cr+likely = 15 336 337 const ( 338 BO_BCTR = 16 // branch on ctr value 339 BO_BCR = 12 // branch on cr value 340 BO_BCRBCTR = 8 // branch on ctr and cr value 341 BO_NOTBCR = 4 // branch on not cr value 342 BO_UNLIKELY = 2 // value for unlikely 343 BO_LIKELY = 3 // value for likely 344 ) 345 346 // Bit settings from the CR 347 348 const ( 349 C_COND_LT = iota // 0 result is negative 350 C_COND_GT // 1 result is positive 351 C_COND_EQ // 2 result is zero 352 C_COND_SO // 3 summary overflow or FP compare w/ NaN 353 ) 354 355 const ( 356 C_NONE = iota 357 C_REG 358 C_FREG 359 C_VREG 360 C_VSREG 361 C_CREG 362 C_SPR /* special processor register */ 363 C_ZCON 364 C_SCON /* 16 bit signed */ 365 C_UCON /* 32 bit signed, low 16 bits 0 */ 366 C_ADDCON /* -0x8000 <= v < 0 */ 367 C_ANDCON /* 0 < v <= 0xFFFF */ 368 C_LCON /* other 32 */ 369 C_DCON /* other 64 (could subdivide further) */ 370 C_SACON /* $n(REG) where n <= int16 */ 371 C_SECON 372 C_LACON /* $n(REG) where int16 < n <= int32 */ 373 C_LECON 374 C_DACON /* $n(REG) where int32 < n */ 375 C_SBRA 376 C_LBRA 377 C_LBRAPIC 378 C_SAUTO 379 C_LAUTO 380 C_SEXT 381 C_LEXT 382 C_ZOREG // conjecture: either (1) register + zeroed offset, or (2) "R0" implies zero or C_REG 383 C_SOREG // register + signed offset 384 C_LOREG 385 C_FPSCR 386 C_MSR 387 C_XER 388 C_LR 389 C_CTR 390 C_ANY 391 C_GOK 392 C_ADDR 393 C_GOTADDR 394 C_TOCADDR 395 C_TLS_LE 396 C_TLS_IE 397 C_TEXTSIZE 398 399 C_NCLASS /* must be the last */ 400 ) 401 402 const ( 403 AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota 404 AADDCC 405 AADDIS 406 AADDV 407 AADDVCC 408 AADDC 409 AADDCCC 410 AADDCV 411 AADDCVCC 412 AADDME 413 AADDMECC 414 AADDMEVCC 415 AADDMEV 416 AADDE 417 AADDECC 418 AADDEVCC 419 AADDEV 420 AADDZE 421 AADDZECC 422 AADDZEVCC 423 AADDZEV 424 AADDEX 425 AAND 426 AANDCC 427 AANDN 428 AANDNCC 429 AANDISCC 430 ABC 431 ABCL 432 ABEQ 433 ABGE // not LT = G/E/U 434 ABGT 435 ABLE // not GT = L/E/U 436 ABLT 437 ABNE // not EQ = L/G/U 438 ABVC // Unordered-clear 439 ABVS // Unordered-set 440 ACMP 441 ACMPU 442 ACMPEQB 443 ACNTLZW 444 ACNTLZWCC 445 ACRAND 446 ACRANDN 447 ACREQV 448 ACRNAND 449 ACRNOR 450 ACROR 451 ACRORN 452 ACRXOR 453 ADIVW 454 ADIVWCC 455 ADIVWVCC 456 ADIVWV 457 ADIVWU 458 ADIVWUCC 459 ADIVWUVCC 460 ADIVWUV 461 AEQV 462 AEQVCC 463 AEXTSB 464 AEXTSBCC 465 AEXTSH 466 AEXTSHCC 467 AFABS 468 AFABSCC 469 AFADD 470 AFADDCC 471 AFADDS 472 AFADDSCC 473 AFCMPO 474 AFCMPU 475 AFCTIW 476 AFCTIWCC 477 AFCTIWZ 478 AFCTIWZCC 479 AFDIV 480 AFDIVCC 481 AFDIVS 482 AFDIVSCC 483 AFMADD 484 AFMADDCC 485 AFMADDS 486 AFMADDSCC 487 AFMOVD 488 AFMOVDCC 489 AFMOVDU 490 AFMOVS 491 AFMOVSU 492 AFMOVSX 493 AFMOVSZ 494 AFMSUB 495 AFMSUBCC 496 AFMSUBS 497 AFMSUBSCC 498 AFMUL 499 AFMULCC 500 AFMULS 501 AFMULSCC 502 AFNABS 503 AFNABSCC 504 AFNEG 505 AFNEGCC 506 AFNMADD 507 AFNMADDCC 508 AFNMADDS 509 AFNMADDSCC 510 AFNMSUB 511 AFNMSUBCC 512 AFNMSUBS 513 AFNMSUBSCC 514 AFRSP 515 AFRSPCC 516 AFSUB 517 AFSUBCC 518 AFSUBS 519 AFSUBSCC 520 AISEL 521 AMOVMW 522 ALBAR 523 ALHAR 524 ALSW 525 ALWAR 526 ALWSYNC 527 AMOVDBR 528 AMOVWBR 529 AMOVB 530 AMOVBU 531 AMOVBZ 532 AMOVBZU 533 AMOVH 534 AMOVHBR 535 AMOVHU 536 AMOVHZ 537 AMOVHZU 538 AMOVW 539 AMOVWU 540 AMOVFL 541 AMOVCRFS 542 AMTFSB0 543 AMTFSB0CC 544 AMTFSB1 545 AMTFSB1CC 546 AMULHW 547 AMULHWCC 548 AMULHWU 549 AMULHWUCC 550 AMULLW 551 AMULLWCC 552 AMULLWVCC 553 AMULLWV 554 ANAND 555 ANANDCC 556 ANEG 557 ANEGCC 558 ANEGVCC 559 ANEGV 560 ANOR 561 ANORCC 562 AOR 563 AORCC 564 AORN 565 AORNCC 566 AORIS 567 AREM 568 AREMCC 569 AREMV 570 AREMVCC 571 AREMU 572 AREMUCC 573 AREMUV 574 AREMUVCC 575 ARFI 576 ARLWMI 577 ARLWMICC 578 ARLWNM 579 ARLWNMCC 580 ASLW 581 ASLWCC 582 ASRW 583 ASRAW 584 ASRAWCC 585 ASRWCC 586 ASTBCCC 587 ASTSW 588 ASTWCCC 589 ASUB 590 ASUBCC 591 ASUBVCC 592 ASUBC 593 ASUBCCC 594 ASUBCV 595 ASUBCVCC 596 ASUBME 597 ASUBMECC 598 ASUBMEVCC 599 ASUBMEV 600 ASUBV 601 ASUBE 602 ASUBECC 603 ASUBEV 604 ASUBEVCC 605 ASUBZE 606 ASUBZECC 607 ASUBZEVCC 608 ASUBZEV 609 ASYNC 610 AXOR 611 AXORCC 612 AXORIS 613 614 ADCBF 615 ADCBI 616 ADCBST 617 ADCBT 618 ADCBTST 619 ADCBZ 620 AECIWX 621 AECOWX 622 AEIEIO 623 AICBI 624 AISYNC 625 APTESYNC 626 ATLBIE 627 ATLBIEL 628 ATLBSYNC 629 ATW 630 631 ASYSCALL 632 AWORD 633 634 ARFCI 635 636 AFCPSGN 637 AFCPSGNCC 638 /* optional on 32-bit */ 639 AFRES 640 AFRESCC 641 AFRIM 642 AFRIMCC 643 AFRIP 644 AFRIPCC 645 AFRIZ 646 AFRIZCC 647 AFRIN 648 AFRINCC 649 AFRSQRTE 650 AFRSQRTECC 651 AFSEL 652 AFSELCC 653 AFSQRT 654 AFSQRTCC 655 AFSQRTS 656 AFSQRTSCC 657 658 /* 64-bit */ 659 660 ACNTLZD 661 ACNTLZDCC 662 ACMPW /* CMP with L=0 */ 663 ACMPWU 664 ACMPB 665 AFTDIV 666 AFTSQRT 667 ADIVD 668 ADIVDCC 669 ADIVDE 670 ADIVDECC 671 ADIVDEU 672 ADIVDEUCC 673 ADIVDVCC 674 ADIVDV 675 ADIVDU 676 ADIVDUCC 677 ADIVDUVCC 678 ADIVDUV 679 AEXTSW 680 AEXTSWCC 681 /* AFCFIW; AFCFIWCC */ 682 AFCFID 683 AFCFIDCC 684 AFCFIDU 685 AFCFIDUCC 686 AFCFIDS 687 AFCFIDSCC 688 AFCTID 689 AFCTIDCC 690 AFCTIDZ 691 AFCTIDZCC 692 ALDAR 693 AMOVD 694 AMOVDU 695 AMOVWZ 696 AMOVWZU 697 AMULHD 698 AMULHDCC 699 AMULHDU 700 AMULHDUCC 701 AMULLD 702 AMULLDCC 703 AMULLDVCC 704 AMULLDV 705 ARFID 706 ARLDMI 707 ARLDMICC 708 ARLDIMI 709 ARLDIMICC 710 ARLDC 711 ARLDCCC 712 ARLDCR 713 ARLDCRCC 714 ARLDICR 715 ARLDICRCC 716 ARLDCL 717 ARLDCLCC 718 ARLDICL 719 ARLDICLCC 720 AROTL 721 AROTLW 722 ASLBIA 723 ASLBIE 724 ASLBMFEE 725 ASLBMFEV 726 ASLBMTE 727 ASLD 728 ASLDCC 729 ASRD 730 ASRAD 731 ASRADCC 732 ASRDCC 733 ASTDCCC 734 ATD 735 736 /* 64-bit pseudo operation */ 737 ADWORD 738 AREMD 739 AREMDCC 740 AREMDV 741 AREMDVCC 742 AREMDU 743 AREMDUCC 744 AREMDUV 745 AREMDUVCC 746 747 /* more 64-bit operations */ 748 AHRFID 749 APOPCNTD 750 APOPCNTW 751 APOPCNTB 752 ACOPY 753 APASTECC 754 ADARN 755 ALDMX 756 AMADDHD 757 AMADDHDU 758 AMADDLD 759 760 /* Vector */ 761 ALV 762 ALVEBX 763 ALVEHX 764 ALVEWX 765 ALVX 766 ALVXL 767 ALVSL 768 ALVSR 769 ASTV 770 ASTVEBX 771 ASTVEHX 772 ASTVEWX 773 ASTVX 774 ASTVXL 775 AVAND 776 AVANDC 777 AVNAND 778 AVOR 779 AVORC 780 AVNOR 781 AVXOR 782 AVEQV 783 AVADDUM 784 AVADDUBM 785 AVADDUHM 786 AVADDUWM 787 AVADDUDM 788 AVADDUQM 789 AVADDCU 790 AVADDCUQ 791 AVADDCUW 792 AVADDUS 793 AVADDUBS 794 AVADDUHS 795 AVADDUWS 796 AVADDSS 797 AVADDSBS 798 AVADDSHS 799 AVADDSWS 800 AVADDE 801 AVADDEUQM 802 AVADDECUQ 803 AVSUBUM 804 AVSUBUBM 805 AVSUBUHM 806 AVSUBUWM 807 AVSUBUDM 808 AVSUBUQM 809 AVSUBCU 810 AVSUBCUQ 811 AVSUBCUW 812 AVSUBUS 813 AVSUBUBS 814 AVSUBUHS 815 AVSUBUWS 816 AVSUBSS 817 AVSUBSBS 818 AVSUBSHS 819 AVSUBSWS 820 AVSUBE 821 AVSUBEUQM 822 AVSUBECUQ 823 AVMULESB 824 AVMULOSB 825 AVMULEUB 826 AVMULOUB 827 AVMULESH 828 AVMULOSH 829 AVMULEUH 830 AVMULOUH 831 AVMULESW 832 AVMULOSW 833 AVMULEUW 834 AVMULOUW 835 AVMULUWM 836 AVPMSUM 837 AVPMSUMB 838 AVPMSUMH 839 AVPMSUMW 840 AVPMSUMD 841 AVMSUMUDM 842 AVR 843 AVRLB 844 AVRLH 845 AVRLW 846 AVRLD 847 AVS 848 AVSLB 849 AVSLH 850 AVSLW 851 AVSL 852 AVSLO 853 AVSRB 854 AVSRH 855 AVSRW 856 AVSR 857 AVSRO 858 AVSLD 859 AVSRD 860 AVSA 861 AVSRAB 862 AVSRAH 863 AVSRAW 864 AVSRAD 865 AVSOI 866 AVSLDOI 867 AVCLZ 868 AVCLZB 869 AVCLZH 870 AVCLZW 871 AVCLZD 872 AVPOPCNT 873 AVPOPCNTB 874 AVPOPCNTH 875 AVPOPCNTW 876 AVPOPCNTD 877 AVCMPEQ 878 AVCMPEQUB 879 AVCMPEQUBCC 880 AVCMPEQUH 881 AVCMPEQUHCC 882 AVCMPEQUW 883 AVCMPEQUWCC 884 AVCMPEQUD 885 AVCMPEQUDCC 886 AVCMPGT 887 AVCMPGTUB 888 AVCMPGTUBCC 889 AVCMPGTUH 890 AVCMPGTUHCC 891 AVCMPGTUW 892 AVCMPGTUWCC 893 AVCMPGTUD 894 AVCMPGTUDCC 895 AVCMPGTSB 896 AVCMPGTSBCC 897 AVCMPGTSH 898 AVCMPGTSHCC 899 AVCMPGTSW 900 AVCMPGTSWCC 901 AVCMPGTSD 902 AVCMPGTSDCC 903 AVCMPNEZB 904 AVCMPNEZBCC 905 AVPERM 906 AVPERMXOR 907 AVBPERMQ 908 AVBPERMD 909 AVSEL 910 AVSPLT 911 AVSPLTB 912 AVSPLTH 913 AVSPLTW 914 AVSPLTI 915 AVSPLTISB 916 AVSPLTISH 917 AVSPLTISW 918 AVCIPH 919 AVCIPHER 920 AVCIPHERLAST 921 AVNCIPH 922 AVNCIPHER 923 AVNCIPHERLAST 924 AVSBOX 925 AVSHASIGMA 926 AVSHASIGMAW 927 AVSHASIGMAD 928 929 /* VSX */ 930 ALXV 931 ALXVD2X 932 ALXVDSX 933 ALXVW4X 934 ASTXV 935 ASTXVD2X 936 ASTXVW4X 937 ALXS 938 ALXSDX 939 ASTXS 940 ASTXSDX 941 ALXSI 942 ALXSIWAX 943 ALXSIWZX 944 ASTXSI 945 ASTXSIWX 946 AMFVSR 947 AMFVSRD 948 AMFFPRD 949 AMFVRD 950 AMFVSRWZ 951 AMFVSRLD 952 AMTVSR 953 AMTVSRD 954 AMTFPRD 955 AMTVRD 956 AMTVSRWA 957 AMTVSRWZ 958 AMTVSRDD 959 AMTVSRWS 960 AXXLAND 961 AXXLANDQ 962 AXXLANDC 963 AXXLEQV 964 AXXLNAND 965 AXXLOR 966 AXXLORC 967 AXXLNOR 968 AXXLORQ 969 AXXLXOR 970 AXXSEL 971 AXXMRG 972 AXXMRGHW 973 AXXMRGLW 974 AXXSPLT 975 AXXSPLTW 976 AXXPERM 977 AXXPERMDI 978 AXXSI 979 AXXSLDWI 980 AXSCV 981 AXSCVDPSP 982 AXSCVSPDP 983 AXSCVDPSPN 984 AXSCVSPDPN 985 AXVCV 986 AXVCVDPSP 987 AXVCVSPDP 988 AXSCVX 989 AXSCVDPSXDS 990 AXSCVDPSXWS 991 AXSCVDPUXDS 992 AXSCVDPUXWS 993 AXSCVXP 994 AXSCVSXDDP 995 AXSCVUXDDP 996 AXSCVSXDSP 997 AXSCVUXDSP 998 AXVCVX 999 AXVCVDPSXDS 1000 AXVCVDPSXWS 1001 AXVCVDPUXDS 1002 AXVCVDPUXWS 1003 AXVCVSPSXDS 1004 AXVCVSPSXWS 1005 AXVCVSPUXDS 1006 AXVCVSPUXWS 1007 AXVCVXP 1008 AXVCVSXDDP 1009 AXVCVSXWDP 1010 AXVCVUXDDP 1011 AXVCVUXWDP 1012 AXVCVSXDSP 1013 AXVCVSXWSP 1014 AXVCVUXDSP 1015 AXVCVUXWSP 1016 1017 ALAST 1018 1019 // aliases 1020 ABR = obj.AJMP 1021 ABL = obj.ACALL 1022 )