golang.org/x/arch@v0.17.0/riscv64/riscv64asm/inst.go (about) 1 // Copyright 2024 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 package riscv64asm 6 7 import ( 8 "fmt" 9 "strings" 10 ) 11 12 // An Op is a RISC-V opcode. 13 type Op uint16 14 15 // NOTE: The actual Op values are defined in tables.go. 16 func (op Op) String() string { 17 if op >= Op(len(opstr)) || opstr[op] == "" { 18 return fmt.Sprintf("Op(%d)", op) 19 } 20 21 return opstr[op] 22 } 23 24 // An Arg is a single instruction argument. 25 type Arg interface { 26 String() string 27 } 28 29 // An Args holds the instruction arguments. 30 // If an instruction has fewer than 6 arguments, 31 // the final elements in the array are nil. 32 type Args [6]Arg 33 34 // An Inst is a single instruction. 35 type Inst struct { 36 Op Op // Opcode mnemonic. 37 Enc uint32 // Raw encoding bits. 38 Args Args // Instruction arguments, in RISC-V mamual order. 39 Len int // Length of encoded instruction in bytes 40 } 41 42 func (i Inst) String() string { 43 var args []string 44 for _, arg := range i.Args { 45 if arg == nil { 46 break 47 } 48 args = append(args, arg.String()) 49 } 50 51 if len(args) == 0 { 52 return i.Op.String() 53 } 54 return i.Op.String() + " " + strings.Join(args, ",") 55 } 56 57 // A Reg is a single register. 58 // The zero value denotes X0, not the absence of a register. 59 type Reg uint16 60 61 const ( 62 // General-purpose register 63 X0 Reg = iota 64 X1 65 X2 66 X3 67 X4 68 X5 69 X6 70 X7 71 X8 72 X9 73 X10 74 X11 75 X12 76 X13 77 X14 78 X15 79 X16 80 X17 81 X18 82 X19 83 X20 84 X21 85 X22 86 X23 87 X24 88 X25 89 X26 90 X27 91 X28 92 X29 93 X30 94 X31 95 96 //Float point register 97 F0 98 F1 99 F2 100 F3 101 F4 102 F5 103 F6 104 F7 105 F8 106 F9 107 F10 108 F11 109 F12 110 F13 111 F14 112 F15 113 F16 114 F17 115 F18 116 F19 117 F20 118 F21 119 F22 120 F23 121 F24 122 F25 123 F26 124 F27 125 F28 126 F29 127 F30 128 F31 129 ) 130 131 func (r Reg) String() string { 132 switch { 133 case r >= X0 && r <= X31: 134 return fmt.Sprintf("x%d", r) 135 136 case r >= F0 && r <= F31: 137 return fmt.Sprintf("f%d", r-F0) 138 139 default: 140 return fmt.Sprintf("Unknown(%d)", r) 141 } 142 } 143 144 // A CSR is a single control and status register. 145 // Use stringer to generate CSR match table. 146 // 147 //go:generate stringer -type=CSR 148 type CSR uint16 149 150 const ( 151 // Control status register 152 USTATUS CSR = 0x0000 153 FFLAGS CSR = 0x0001 154 FRM CSR = 0x0002 155 FCSR CSR = 0x0003 156 UIE CSR = 0x0004 157 UTVEC CSR = 0x0005 158 UTVT CSR = 0x0007 159 VSTART CSR = 0x0008 160 VXSAT CSR = 0x0009 161 VXRM CSR = 0x000a 162 VCSR CSR = 0x000f 163 USCRATCH CSR = 0x0040 164 UEPC CSR = 0x0041 165 UCAUSE CSR = 0x0042 166 UTVAL CSR = 0x0043 167 UIP CSR = 0x0044 168 UNXTI CSR = 0x0045 169 UINTSTATUS CSR = 0x0046 170 USCRATCHCSW CSR = 0x0048 171 USCRATCHCSWL CSR = 0x0049 172 SSTATUS CSR = 0x0100 173 SEDELEG CSR = 0x0102 174 SIDELEG CSR = 0x0103 175 SIE CSR = 0x0104 176 STVEC CSR = 0x0105 177 SCOUNTEREN CSR = 0x0106 178 STVT CSR = 0x0107 179 SSCRATCH CSR = 0x0140 180 SEPC CSR = 0x0141 181 SCAUSE CSR = 0x0142 182 STVAL CSR = 0x0143 183 SIP CSR = 0x0144 184 SNXTI CSR = 0x0145 185 SINTSTATUS CSR = 0x0146 186 SSCRATCHCSW CSR = 0x0148 187 SSCRATCHCSWL CSR = 0x0149 188 SATP CSR = 0x0180 189 VSSTATUS CSR = 0x0200 190 VSIE CSR = 0x0204 191 VSTVEC CSR = 0x0205 192 VSSCRATCH CSR = 0x0240 193 VSEPC CSR = 0x0241 194 VSCAUSE CSR = 0x0242 195 VSTVAL CSR = 0x0243 196 VSIP CSR = 0x0244 197 VSATP CSR = 0x0280 198 MSTATUS CSR = 0x0300 199 MISA CSR = 0x0301 200 MEDELEG CSR = 0x0302 201 MIDELEG CSR = 0x0303 202 MIE CSR = 0x0304 203 MTVEC CSR = 0x0305 204 MCOUNTEREN CSR = 0x0306 205 MTVT CSR = 0x0307 206 MSTATUSH CSR = 0x0310 207 MCOUNTINHIBIT CSR = 0x0320 208 MHPMEVENT3 CSR = 0x0323 209 MHPMEVENT4 CSR = 0x0324 210 MHPMEVENT5 CSR = 0x0325 211 MHPMEVENT6 CSR = 0x0326 212 MHPMEVENT7 CSR = 0x0327 213 MHPMEVENT8 CSR = 0x0328 214 MHPMEVENT9 CSR = 0x0329 215 MHPMEVENT10 CSR = 0x032a 216 MHPMEVENT11 CSR = 0x032b 217 MHPMEVENT12 CSR = 0x032c 218 MHPMEVENT13 CSR = 0x032d 219 MHPMEVENT14 CSR = 0x032e 220 MHPMEVENT15 CSR = 0x032f 221 MHPMEVENT16 CSR = 0x0330 222 MHPMEVENT17 CSR = 0x0331 223 MHPMEVENT18 CSR = 0x0332 224 MHPMEVENT19 CSR = 0x0333 225 MHPMEVENT20 CSR = 0x0334 226 MHPMEVENT21 CSR = 0x0335 227 MHPMEVENT22 CSR = 0x0336 228 MHPMEVENT23 CSR = 0x0337 229 MHPMEVENT24 CSR = 0x0338 230 MHPMEVENT25 CSR = 0x0339 231 MHPMEVENT26 CSR = 0x033a 232 MHPMEVENT27 CSR = 0x033b 233 MHPMEVENT28 CSR = 0x033c 234 MHPMEVENT29 CSR = 0x033d 235 MHPMEVENT30 CSR = 0x033e 236 MHPMEVENT31 CSR = 0x033f 237 MSCRATCH CSR = 0x0340 238 MEPC CSR = 0x0341 239 MCAUSE CSR = 0x0342 240 MTVAL CSR = 0x0343 241 MIP CSR = 0x0344 242 MNXTI CSR = 0x0345 243 MINTSTATUS CSR = 0x0346 244 MSCRATCHCSW CSR = 0x0348 245 MSCRATCHCSWL CSR = 0x0349 246 MTINST CSR = 0x034a 247 MTVAL2 CSR = 0x034b 248 PMPCFG0 CSR = 0x03a0 249 PMPCFG1 CSR = 0x03a1 250 PMPCFG2 CSR = 0x03a2 251 PMPCFG3 CSR = 0x03a3 252 PMPADDR0 CSR = 0x03b0 253 PMPADDR1 CSR = 0x03b1 254 PMPADDR2 CSR = 0x03b2 255 PMPADDR3 CSR = 0x03b3 256 PMPADDR4 CSR = 0x03b4 257 PMPADDR5 CSR = 0x03b5 258 PMPADDR6 CSR = 0x03b6 259 PMPADDR7 CSR = 0x03b7 260 PMPADDR8 CSR = 0x03b8 261 PMPADDR9 CSR = 0x03b9 262 PMPADDR10 CSR = 0x03ba 263 PMPADDR11 CSR = 0x03bb 264 PMPADDR12 CSR = 0x03bc 265 PMPADDR13 CSR = 0x03bd 266 PMPADDR14 CSR = 0x03be 267 PMPADDR15 CSR = 0x03bf 268 HSTATUS CSR = 0x0600 269 HEDELEG CSR = 0x0602 270 HIDELEG CSR = 0x0603 271 HIE CSR = 0x0604 272 HTIMEDELTA CSR = 0x0605 273 HCOUNTEREN CSR = 0x0606 274 HGEIE CSR = 0x0607 275 HTIMEDELTAH CSR = 0x0615 276 HTVAL CSR = 0x0643 277 HIP CSR = 0x0644 278 HVIP CSR = 0x0645 279 HTINST CSR = 0x064a 280 HGATP CSR = 0x0680 281 TSELECT CSR = 0x07a0 282 TDATA1 CSR = 0x07a1 283 TDATA2 CSR = 0x07a2 284 TDATA3 CSR = 0x07a3 285 TINFO CSR = 0x07a4 286 TCONTROL CSR = 0x07a5 287 MCONTEXT CSR = 0x07a8 288 MNOISE CSR = 0x07a9 289 SCONTEXT CSR = 0x07aa 290 DCSR CSR = 0x07b0 291 DPC CSR = 0x07b1 292 DSCRATCH0 CSR = 0x07b2 293 DSCRATCH1 CSR = 0x07b3 294 MCYCLE CSR = 0x0b00 295 MINSTRET CSR = 0x0b02 296 MHPMCOUNTER3 CSR = 0x0b03 297 MHPMCOUNTER4 CSR = 0x0b04 298 MHPMCOUNTER5 CSR = 0x0b05 299 MHPMCOUNTER6 CSR = 0x0b06 300 MHPMCOUNTER7 CSR = 0x0b07 301 MHPMCOUNTER8 CSR = 0x0b08 302 MHPMCOUNTER9 CSR = 0x0b09 303 MHPMCOUNTER10 CSR = 0x0b0a 304 MHPMCOUNTER11 CSR = 0x0b0b 305 MHPMCOUNTER12 CSR = 0x0b0c 306 MHPMCOUNTER13 CSR = 0x0b0d 307 MHPMCOUNTER14 CSR = 0x0b0e 308 MHPMCOUNTER15 CSR = 0x0b0f 309 MHPMCOUNTER16 CSR = 0x0b10 310 MHPMCOUNTER17 CSR = 0x0b11 311 MHPMCOUNTER18 CSR = 0x0b12 312 MHPMCOUNTER19 CSR = 0x0b13 313 MHPMCOUNTER20 CSR = 0x0b14 314 MHPMCOUNTER21 CSR = 0x0b15 315 MHPMCOUNTER22 CSR = 0x0b16 316 MHPMCOUNTER23 CSR = 0x0b17 317 MHPMCOUNTER24 CSR = 0x0b18 318 MHPMCOUNTER25 CSR = 0x0b19 319 MHPMCOUNTER26 CSR = 0x0b1a 320 MHPMCOUNTER27 CSR = 0x0b1b 321 MHPMCOUNTER28 CSR = 0x0b1c 322 MHPMCOUNTER29 CSR = 0x0b1d 323 MHPMCOUNTER30 CSR = 0x0b1e 324 MHPMCOUNTER31 CSR = 0x0b1f 325 MCYCLEH CSR = 0x0b80 326 MINSTRETH CSR = 0x0b82 327 MHPMCOUNTER3H CSR = 0x0b83 328 MHPMCOUNTER4H CSR = 0x0b84 329 MHPMCOUNTER5H CSR = 0x0b85 330 MHPMCOUNTER6H CSR = 0x0b86 331 MHPMCOUNTER7H CSR = 0x0b87 332 MHPMCOUNTER8H CSR = 0x0b88 333 MHPMCOUNTER9H CSR = 0x0b89 334 MHPMCOUNTER10H CSR = 0x0b8a 335 MHPMCOUNTER11H CSR = 0x0b8b 336 MHPMCOUNTER12H CSR = 0x0b8c 337 MHPMCOUNTER13H CSR = 0x0b8d 338 MHPMCOUNTER14H CSR = 0x0b8e 339 MHPMCOUNTER15H CSR = 0x0b8f 340 MHPMCOUNTER16H CSR = 0x0b90 341 MHPMCOUNTER17H CSR = 0x0b91 342 MHPMCOUNTER18H CSR = 0x0b92 343 MHPMCOUNTER19H CSR = 0x0b93 344 MHPMCOUNTER20H CSR = 0x0b94 345 MHPMCOUNTER21H CSR = 0x0b95 346 MHPMCOUNTER22H CSR = 0x0b96 347 MHPMCOUNTER23H CSR = 0x0b97 348 MHPMCOUNTER24H CSR = 0x0b98 349 MHPMCOUNTER25H CSR = 0x0b99 350 MHPMCOUNTER26H CSR = 0x0b9a 351 MHPMCOUNTER27H CSR = 0x0b9b 352 MHPMCOUNTER28H CSR = 0x0b9c 353 MHPMCOUNTER29H CSR = 0x0b9d 354 MHPMCOUNTER30H CSR = 0x0b9e 355 MHPMCOUNTER31H CSR = 0x0b9f 356 CYCLE CSR = 0x0c00 357 TIME CSR = 0x0c01 358 INSTRET CSR = 0x0c02 359 HPMCOUNTER3 CSR = 0x0c03 360 HPMCOUNTER4 CSR = 0x0c04 361 HPMCOUNTER5 CSR = 0x0c05 362 HPMCOUNTER6 CSR = 0x0c06 363 HPMCOUNTER7 CSR = 0x0c07 364 HPMCOUNTER8 CSR = 0x0c08 365 HPMCOUNTER9 CSR = 0x0c09 366 HPMCOUNTER10 CSR = 0x0c0a 367 HPMCOUNTER11 CSR = 0x0c0b 368 HPMCOUNTER12 CSR = 0x0c0c 369 HPMCOUNTER13 CSR = 0x0c0d 370 HPMCOUNTER14 CSR = 0x0c0e 371 HPMCOUNTER15 CSR = 0x0c0f 372 HPMCOUNTER16 CSR = 0x0c10 373 HPMCOUNTER17 CSR = 0x0c11 374 HPMCOUNTER18 CSR = 0x0c12 375 HPMCOUNTER19 CSR = 0x0c13 376 HPMCOUNTER20 CSR = 0x0c14 377 HPMCOUNTER21 CSR = 0x0c15 378 HPMCOUNTER22 CSR = 0x0c16 379 HPMCOUNTER23 CSR = 0x0c17 380 HPMCOUNTER24 CSR = 0x0c18 381 HPMCOUNTER25 CSR = 0x0c19 382 HPMCOUNTER26 CSR = 0x0c1a 383 HPMCOUNTER27 CSR = 0x0c1b 384 HPMCOUNTER28 CSR = 0x0c1c 385 HPMCOUNTER29 CSR = 0x0c1d 386 HPMCOUNTER30 CSR = 0x0c1e 387 HPMCOUNTER31 CSR = 0x0c1f 388 VL CSR = 0x0c20 389 VTYPE CSR = 0x0c21 390 VLENB CSR = 0x0c22 391 CYCLEH CSR = 0x0c80 392 TIMEH CSR = 0x0c81 393 INSTRETH CSR = 0x0c82 394 HPMCOUNTER3H CSR = 0x0c83 395 HPMCOUNTER4H CSR = 0x0c84 396 HPMCOUNTER5H CSR = 0x0c85 397 HPMCOUNTER6H CSR = 0x0c86 398 HPMCOUNTER7H CSR = 0x0c87 399 HPMCOUNTER8H CSR = 0x0c88 400 HPMCOUNTER9H CSR = 0x0c89 401 HPMCOUNTER10H CSR = 0x0c8a 402 HPMCOUNTER11H CSR = 0x0c8b 403 HPMCOUNTER12H CSR = 0x0c8c 404 HPMCOUNTER13H CSR = 0x0c8d 405 HPMCOUNTER14H CSR = 0x0c8e 406 HPMCOUNTER15H CSR = 0x0c8f 407 HPMCOUNTER16H CSR = 0x0c90 408 HPMCOUNTER17H CSR = 0x0c91 409 HPMCOUNTER18H CSR = 0x0c92 410 HPMCOUNTER19H CSR = 0x0c93 411 HPMCOUNTER20H CSR = 0x0c94 412 HPMCOUNTER21H CSR = 0x0c95 413 HPMCOUNTER22H CSR = 0x0c96 414 HPMCOUNTER23H CSR = 0x0c97 415 HPMCOUNTER24H CSR = 0x0c98 416 HPMCOUNTER25H CSR = 0x0c99 417 HPMCOUNTER26H CSR = 0x0c9a 418 HPMCOUNTER27H CSR = 0x0c9b 419 HPMCOUNTER28H CSR = 0x0c9c 420 HPMCOUNTER29H CSR = 0x0c9d 421 HPMCOUNTER30H CSR = 0x0c9e 422 HPMCOUNTER31H CSR = 0x0c9f 423 HGEIP CSR = 0x0e12 424 MVENDORID CSR = 0x0f11 425 MARCHID CSR = 0x0f12 426 MIMPID CSR = 0x0f13 427 MHARTID CSR = 0x0f14 428 MENTROPY CSR = 0x0f15 429 ) 430 431 // An Uimm is an unsigned immediate number 432 type Uimm struct { 433 Imm uint32 // 32-bit unsigned integer 434 Decimal bool // Print format of the immediate, either decimal or hexadecimal 435 } 436 437 func (ui Uimm) String() string { 438 if ui.Decimal { 439 return fmt.Sprintf("%d", ui.Imm) 440 } 441 return fmt.Sprintf("%#x", ui.Imm) 442 } 443 444 // A Simm is a signed immediate number 445 type Simm struct { 446 Imm int32 // 32-bit signed integer 447 Decimal bool // Print format of the immediate, either decimal or hexadecimal 448 Width uint8 // Actual width of the Simm 449 } 450 451 func (si Simm) String() string { 452 if si.Decimal { 453 return fmt.Sprintf("%d", si.Imm) 454 } 455 return fmt.Sprintf("%#x", si.Imm) 456 } 457 458 // An AmoReg is an atomic address register used in AMO instructions 459 type AmoReg struct { 460 reg Reg // Avoid promoted String method 461 } 462 463 func (amoReg AmoReg) String() string { 464 return fmt.Sprintf("(%s)", amoReg.reg) 465 } 466 467 // A RegOffset is a register with offset value 468 type RegOffset struct { 469 OfsReg Reg 470 Ofs Simm 471 } 472 473 func (regofs RegOffset) String() string { 474 return fmt.Sprintf("%s(%s)", regofs.Ofs, regofs.OfsReg) 475 } 476 477 // A MemOrder is a memory order hint in fence instruction 478 type MemOrder uint8 479 480 func (memOrder MemOrder) String() string { 481 var str string 482 if memOrder<<7>>7 == 1 { 483 str += "i" 484 } 485 if memOrder>>1<<7>>7 == 1 { 486 str += "o" 487 } 488 if memOrder>>2<<7>>7 == 1 { 489 str += "r" 490 } 491 if memOrder>>3<<7>>7 == 1 { 492 str += "w" 493 } 494 return str 495 }