golang.org/x/arch@v0.17.0/riscv64/riscv64asm/tables.go (about) 1 // Code generated by riscv64spec riscv-opcodes 2 // DO NOT EDIT 3 4 // Copyright 2024 The Go Authors. All rights reserved. 5 // Use of this source code is governed by a BSD-style 6 // license that can be found in the LICENSE file. 7 8 package riscv64asm 9 10 const ( 11 _ Op = iota 12 ADD 13 ADDI 14 ADDIW 15 ADDW 16 ADD_UW 17 AMOADD_D 18 AMOADD_D_AQ 19 AMOADD_D_AQRL 20 AMOADD_D_RL 21 AMOADD_W 22 AMOADD_W_AQ 23 AMOADD_W_AQRL 24 AMOADD_W_RL 25 AMOAND_D 26 AMOAND_D_AQ 27 AMOAND_D_AQRL 28 AMOAND_D_RL 29 AMOAND_W 30 AMOAND_W_AQ 31 AMOAND_W_AQRL 32 AMOAND_W_RL 33 AMOMAXU_D 34 AMOMAXU_D_AQ 35 AMOMAXU_D_AQRL 36 AMOMAXU_D_RL 37 AMOMAXU_W 38 AMOMAXU_W_AQ 39 AMOMAXU_W_AQRL 40 AMOMAXU_W_RL 41 AMOMAX_D 42 AMOMAX_D_AQ 43 AMOMAX_D_AQRL 44 AMOMAX_D_RL 45 AMOMAX_W 46 AMOMAX_W_AQ 47 AMOMAX_W_AQRL 48 AMOMAX_W_RL 49 AMOMINU_D 50 AMOMINU_D_AQ 51 AMOMINU_D_AQRL 52 AMOMINU_D_RL 53 AMOMINU_W 54 AMOMINU_W_AQ 55 AMOMINU_W_AQRL 56 AMOMINU_W_RL 57 AMOMIN_D 58 AMOMIN_D_AQ 59 AMOMIN_D_AQRL 60 AMOMIN_D_RL 61 AMOMIN_W 62 AMOMIN_W_AQ 63 AMOMIN_W_AQRL 64 AMOMIN_W_RL 65 AMOOR_D 66 AMOOR_D_AQ 67 AMOOR_D_AQRL 68 AMOOR_D_RL 69 AMOOR_W 70 AMOOR_W_AQ 71 AMOOR_W_AQRL 72 AMOOR_W_RL 73 AMOSWAP_D 74 AMOSWAP_D_AQ 75 AMOSWAP_D_AQRL 76 AMOSWAP_D_RL 77 AMOSWAP_W 78 AMOSWAP_W_AQ 79 AMOSWAP_W_AQRL 80 AMOSWAP_W_RL 81 AMOXOR_D 82 AMOXOR_D_AQ 83 AMOXOR_D_AQRL 84 AMOXOR_D_RL 85 AMOXOR_W 86 AMOXOR_W_AQ 87 AMOXOR_W_AQRL 88 AMOXOR_W_RL 89 AND 90 ANDI 91 ANDN 92 AUIPC 93 BCLR 94 BCLRI 95 BEQ 96 BEXT 97 BEXTI 98 BGE 99 BGEU 100 BINV 101 BINVI 102 BLT 103 BLTU 104 BNE 105 BSET 106 BSETI 107 CLZ 108 CLZW 109 CPOP 110 CPOPW 111 CSRRC 112 CSRRCI 113 CSRRS 114 CSRRSI 115 CSRRW 116 CSRRWI 117 CTZ 118 CTZW 119 C_ADD 120 C_ADDI 121 C_ADDI16SP 122 C_ADDI4SPN 123 C_ADDIW 124 C_ADDW 125 C_AND 126 C_ANDI 127 C_BEQZ 128 C_BNEZ 129 C_EBREAK 130 C_FLD 131 C_FLDSP 132 C_FSD 133 C_FSDSP 134 C_J 135 C_JALR 136 C_JR 137 C_LD 138 C_LDSP 139 C_LI 140 C_LUI 141 C_LW 142 C_LWSP 143 C_MV 144 C_NOP 145 C_OR 146 C_SD 147 C_SDSP 148 C_SLLI 149 C_SRAI 150 C_SRLI 151 C_SUB 152 C_SUBW 153 C_SW 154 C_SWSP 155 C_UNIMP 156 C_XOR 157 DIV 158 DIVU 159 DIVUW 160 DIVW 161 EBREAK 162 ECALL 163 FADD_D 164 FADD_H 165 FADD_Q 166 FADD_S 167 FCLASS_D 168 FCLASS_H 169 FCLASS_Q 170 FCLASS_S 171 FCVT_D_L 172 FCVT_D_LU 173 FCVT_D_Q 174 FCVT_D_S 175 FCVT_D_W 176 FCVT_D_WU 177 FCVT_H_L 178 FCVT_H_LU 179 FCVT_H_S 180 FCVT_H_W 181 FCVT_H_WU 182 FCVT_LU_D 183 FCVT_LU_H 184 FCVT_LU_Q 185 FCVT_LU_S 186 FCVT_L_D 187 FCVT_L_H 188 FCVT_L_Q 189 FCVT_L_S 190 FCVT_Q_D 191 FCVT_Q_L 192 FCVT_Q_LU 193 FCVT_Q_S 194 FCVT_Q_W 195 FCVT_Q_WU 196 FCVT_S_D 197 FCVT_S_H 198 FCVT_S_L 199 FCVT_S_LU 200 FCVT_S_Q 201 FCVT_S_W 202 FCVT_S_WU 203 FCVT_WU_D 204 FCVT_WU_H 205 FCVT_WU_Q 206 FCVT_WU_S 207 FCVT_W_D 208 FCVT_W_H 209 FCVT_W_Q 210 FCVT_W_S 211 FDIV_D 212 FDIV_H 213 FDIV_Q 214 FDIV_S 215 FENCE 216 FENCE_I 217 FEQ_D 218 FEQ_H 219 FEQ_Q 220 FEQ_S 221 FLD 222 FLE_D 223 FLE_H 224 FLE_Q 225 FLE_S 226 FLH 227 FLQ 228 FLT_D 229 FLT_H 230 FLT_Q 231 FLT_S 232 FLW 233 FMADD_D 234 FMADD_H 235 FMADD_Q 236 FMADD_S 237 FMAX_D 238 FMAX_H 239 FMAX_Q 240 FMAX_S 241 FMIN_D 242 FMIN_H 243 FMIN_Q 244 FMIN_S 245 FMSUB_D 246 FMSUB_H 247 FMSUB_Q 248 FMSUB_S 249 FMUL_D 250 FMUL_H 251 FMUL_Q 252 FMUL_S 253 FMV_D_X 254 FMV_H_X 255 FMV_W_X 256 FMV_X_D 257 FMV_X_H 258 FMV_X_W 259 FNMADD_D 260 FNMADD_H 261 FNMADD_Q 262 FNMADD_S 263 FNMSUB_D 264 FNMSUB_H 265 FNMSUB_Q 266 FNMSUB_S 267 FSD 268 FSGNJN_D 269 FSGNJN_H 270 FSGNJN_Q 271 FSGNJN_S 272 FSGNJX_D 273 FSGNJX_H 274 FSGNJX_Q 275 FSGNJX_S 276 FSGNJ_D 277 FSGNJ_H 278 FSGNJ_Q 279 FSGNJ_S 280 FSH 281 FSQ 282 FSQRT_D 283 FSQRT_H 284 FSQRT_Q 285 FSQRT_S 286 FSUB_D 287 FSUB_H 288 FSUB_Q 289 FSUB_S 290 FSW 291 JAL 292 JALR 293 LB 294 LBU 295 LD 296 LH 297 LHU 298 LR_D 299 LR_D_AQ 300 LR_D_AQRL 301 LR_D_RL 302 LR_W 303 LR_W_AQ 304 LR_W_AQRL 305 LR_W_RL 306 LUI 307 LW 308 LWU 309 MAX 310 MAXU 311 MIN 312 MINU 313 MUL 314 MULH 315 MULHSU 316 MULHU 317 MULW 318 OR 319 ORC_B 320 ORI 321 ORN 322 REM 323 REMU 324 REMUW 325 REMW 326 REV8 327 ROL 328 ROLW 329 ROR 330 RORI 331 RORIW 332 RORW 333 SB 334 SC_D 335 SC_D_AQ 336 SC_D_AQRL 337 SC_D_RL 338 SC_W 339 SC_W_AQ 340 SC_W_AQRL 341 SC_W_RL 342 SD 343 SEXT_B 344 SEXT_H 345 SH 346 SH1ADD 347 SH1ADD_UW 348 SH2ADD 349 SH2ADD_UW 350 SH3ADD 351 SH3ADD_UW 352 SLL 353 SLLI 354 SLLIW 355 SLLI_UW 356 SLLW 357 SLT 358 SLTI 359 SLTIU 360 SLTU 361 SRA 362 SRAI 363 SRAIW 364 SRAW 365 SRL 366 SRLI 367 SRLIW 368 SRLW 369 SUB 370 SUBW 371 SW 372 XNOR 373 XOR 374 XORI 375 ZEXT_H 376 ) 377 378 var opstr = [...]string{ 379 ADD: "ADD", 380 ADDI: "ADDI", 381 ADDIW: "ADDIW", 382 ADDW: "ADDW", 383 ADD_UW: "ADD.UW", 384 AMOADD_D: "AMOADD.D", 385 AMOADD_D_AQ: "AMOADD.D.AQ", 386 AMOADD_D_AQRL: "AMOADD.D.AQRL", 387 AMOADD_D_RL: "AMOADD.D.RL", 388 AMOADD_W: "AMOADD.W", 389 AMOADD_W_AQ: "AMOADD.W.AQ", 390 AMOADD_W_AQRL: "AMOADD.W.AQRL", 391 AMOADD_W_RL: "AMOADD.W.RL", 392 AMOAND_D: "AMOAND.D", 393 AMOAND_D_AQ: "AMOAND.D.AQ", 394 AMOAND_D_AQRL: "AMOAND.D.AQRL", 395 AMOAND_D_RL: "AMOAND.D.RL", 396 AMOAND_W: "AMOAND.W", 397 AMOAND_W_AQ: "AMOAND.W.AQ", 398 AMOAND_W_AQRL: "AMOAND.W.AQRL", 399 AMOAND_W_RL: "AMOAND.W.RL", 400 AMOMAXU_D: "AMOMAXU.D", 401 AMOMAXU_D_AQ: "AMOMAXU.D.AQ", 402 AMOMAXU_D_AQRL: "AMOMAXU.D.AQRL", 403 AMOMAXU_D_RL: "AMOMAXU.D.RL", 404 AMOMAXU_W: "AMOMAXU.W", 405 AMOMAXU_W_AQ: "AMOMAXU.W.AQ", 406 AMOMAXU_W_AQRL: "AMOMAXU.W.AQRL", 407 AMOMAXU_W_RL: "AMOMAXU.W.RL", 408 AMOMAX_D: "AMOMAX.D", 409 AMOMAX_D_AQ: "AMOMAX.D.AQ", 410 AMOMAX_D_AQRL: "AMOMAX.D.AQRL", 411 AMOMAX_D_RL: "AMOMAX.D.RL", 412 AMOMAX_W: "AMOMAX.W", 413 AMOMAX_W_AQ: "AMOMAX.W.AQ", 414 AMOMAX_W_AQRL: "AMOMAX.W.AQRL", 415 AMOMAX_W_RL: "AMOMAX.W.RL", 416 AMOMINU_D: "AMOMINU.D", 417 AMOMINU_D_AQ: "AMOMINU.D.AQ", 418 AMOMINU_D_AQRL: "AMOMINU.D.AQRL", 419 AMOMINU_D_RL: "AMOMINU.D.RL", 420 AMOMINU_W: "AMOMINU.W", 421 AMOMINU_W_AQ: "AMOMINU.W.AQ", 422 AMOMINU_W_AQRL: "AMOMINU.W.AQRL", 423 AMOMINU_W_RL: "AMOMINU.W.RL", 424 AMOMIN_D: "AMOMIN.D", 425 AMOMIN_D_AQ: "AMOMIN.D.AQ", 426 AMOMIN_D_AQRL: "AMOMIN.D.AQRL", 427 AMOMIN_D_RL: "AMOMIN.D.RL", 428 AMOMIN_W: "AMOMIN.W", 429 AMOMIN_W_AQ: "AMOMIN.W.AQ", 430 AMOMIN_W_AQRL: "AMOMIN.W.AQRL", 431 AMOMIN_W_RL: "AMOMIN.W.RL", 432 AMOOR_D: "AMOOR.D", 433 AMOOR_D_AQ: "AMOOR.D.AQ", 434 AMOOR_D_AQRL: "AMOOR.D.AQRL", 435 AMOOR_D_RL: "AMOOR.D.RL", 436 AMOOR_W: "AMOOR.W", 437 AMOOR_W_AQ: "AMOOR.W.AQ", 438 AMOOR_W_AQRL: "AMOOR.W.AQRL", 439 AMOOR_W_RL: "AMOOR.W.RL", 440 AMOSWAP_D: "AMOSWAP.D", 441 AMOSWAP_D_AQ: "AMOSWAP.D.AQ", 442 AMOSWAP_D_AQRL: "AMOSWAP.D.AQRL", 443 AMOSWAP_D_RL: "AMOSWAP.D.RL", 444 AMOSWAP_W: "AMOSWAP.W", 445 AMOSWAP_W_AQ: "AMOSWAP.W.AQ", 446 AMOSWAP_W_AQRL: "AMOSWAP.W.AQRL", 447 AMOSWAP_W_RL: "AMOSWAP.W.RL", 448 AMOXOR_D: "AMOXOR.D", 449 AMOXOR_D_AQ: "AMOXOR.D.AQ", 450 AMOXOR_D_AQRL: "AMOXOR.D.AQRL", 451 AMOXOR_D_RL: "AMOXOR.D.RL", 452 AMOXOR_W: "AMOXOR.W", 453 AMOXOR_W_AQ: "AMOXOR.W.AQ", 454 AMOXOR_W_AQRL: "AMOXOR.W.AQRL", 455 AMOXOR_W_RL: "AMOXOR.W.RL", 456 AND: "AND", 457 ANDI: "ANDI", 458 ANDN: "ANDN", 459 AUIPC: "AUIPC", 460 BCLR: "BCLR", 461 BCLRI: "BCLRI", 462 BEQ: "BEQ", 463 BEXT: "BEXT", 464 BEXTI: "BEXTI", 465 BGE: "BGE", 466 BGEU: "BGEU", 467 BINV: "BINV", 468 BINVI: "BINVI", 469 BLT: "BLT", 470 BLTU: "BLTU", 471 BNE: "BNE", 472 BSET: "BSET", 473 BSETI: "BSETI", 474 CLZ: "CLZ", 475 CLZW: "CLZW", 476 CPOP: "CPOP", 477 CPOPW: "CPOPW", 478 CSRRC: "CSRRC", 479 CSRRCI: "CSRRCI", 480 CSRRS: "CSRRS", 481 CSRRSI: "CSRRSI", 482 CSRRW: "CSRRW", 483 CSRRWI: "CSRRWI", 484 CTZ: "CTZ", 485 CTZW: "CTZW", 486 C_ADD: "C.ADD", 487 C_ADDI: "C.ADDI", 488 C_ADDI16SP: "C.ADDI16SP", 489 C_ADDI4SPN: "C.ADDI4SPN", 490 C_ADDIW: "C.ADDIW", 491 C_ADDW: "C.ADDW", 492 C_AND: "C.AND", 493 C_ANDI: "C.ANDI", 494 C_BEQZ: "C.BEQZ", 495 C_BNEZ: "C.BNEZ", 496 C_EBREAK: "C.EBREAK", 497 C_FLD: "C.FLD", 498 C_FLDSP: "C.FLDSP", 499 C_FSD: "C.FSD", 500 C_FSDSP: "C.FSDSP", 501 C_J: "C.J", 502 C_JALR: "C.JALR", 503 C_JR: "C.JR", 504 C_LD: "C.LD", 505 C_LDSP: "C.LDSP", 506 C_LI: "C.LI", 507 C_LUI: "C.LUI", 508 C_LW: "C.LW", 509 C_LWSP: "C.LWSP", 510 C_MV: "C.MV", 511 C_NOP: "C.NOP", 512 C_OR: "C.OR", 513 C_SD: "C.SD", 514 C_SDSP: "C.SDSP", 515 C_SLLI: "C.SLLI", 516 C_SRAI: "C.SRAI", 517 C_SRLI: "C.SRLI", 518 C_SUB: "C.SUB", 519 C_SUBW: "C.SUBW", 520 C_SW: "C.SW", 521 C_SWSP: "C.SWSP", 522 C_UNIMP: "C.UNIMP", 523 C_XOR: "C.XOR", 524 DIV: "DIV", 525 DIVU: "DIVU", 526 DIVUW: "DIVUW", 527 DIVW: "DIVW", 528 EBREAK: "EBREAK", 529 ECALL: "ECALL", 530 FADD_D: "FADD.D", 531 FADD_H: "FADD.H", 532 FADD_Q: "FADD.Q", 533 FADD_S: "FADD.S", 534 FCLASS_D: "FCLASS.D", 535 FCLASS_H: "FCLASS.H", 536 FCLASS_Q: "FCLASS.Q", 537 FCLASS_S: "FCLASS.S", 538 FCVT_D_L: "FCVT.D.L", 539 FCVT_D_LU: "FCVT.D.LU", 540 FCVT_D_Q: "FCVT.D.Q", 541 FCVT_D_S: "FCVT.D.S", 542 FCVT_D_W: "FCVT.D.W", 543 FCVT_D_WU: "FCVT.D.WU", 544 FCVT_H_L: "FCVT.H.L", 545 FCVT_H_LU: "FCVT.H.LU", 546 FCVT_H_S: "FCVT.H.S", 547 FCVT_H_W: "FCVT.H.W", 548 FCVT_H_WU: "FCVT.H.WU", 549 FCVT_LU_D: "FCVT.LU.D", 550 FCVT_LU_H: "FCVT.LU.H", 551 FCVT_LU_Q: "FCVT.LU.Q", 552 FCVT_LU_S: "FCVT.LU.S", 553 FCVT_L_D: "FCVT.L.D", 554 FCVT_L_H: "FCVT.L.H", 555 FCVT_L_Q: "FCVT.L.Q", 556 FCVT_L_S: "FCVT.L.S", 557 FCVT_Q_D: "FCVT.Q.D", 558 FCVT_Q_L: "FCVT.Q.L", 559 FCVT_Q_LU: "FCVT.Q.LU", 560 FCVT_Q_S: "FCVT.Q.S", 561 FCVT_Q_W: "FCVT.Q.W", 562 FCVT_Q_WU: "FCVT.Q.WU", 563 FCVT_S_D: "FCVT.S.D", 564 FCVT_S_H: "FCVT.S.H", 565 FCVT_S_L: "FCVT.S.L", 566 FCVT_S_LU: "FCVT.S.LU", 567 FCVT_S_Q: "FCVT.S.Q", 568 FCVT_S_W: "FCVT.S.W", 569 FCVT_S_WU: "FCVT.S.WU", 570 FCVT_WU_D: "FCVT.WU.D", 571 FCVT_WU_H: "FCVT.WU.H", 572 FCVT_WU_Q: "FCVT.WU.Q", 573 FCVT_WU_S: "FCVT.WU.S", 574 FCVT_W_D: "FCVT.W.D", 575 FCVT_W_H: "FCVT.W.H", 576 FCVT_W_Q: "FCVT.W.Q", 577 FCVT_W_S: "FCVT.W.S", 578 FDIV_D: "FDIV.D", 579 FDIV_H: "FDIV.H", 580 FDIV_Q: "FDIV.Q", 581 FDIV_S: "FDIV.S", 582 FENCE: "FENCE", 583 FENCE_I: "FENCE.I", 584 FEQ_D: "FEQ.D", 585 FEQ_H: "FEQ.H", 586 FEQ_Q: "FEQ.Q", 587 FEQ_S: "FEQ.S", 588 FLD: "FLD", 589 FLE_D: "FLE.D", 590 FLE_H: "FLE.H", 591 FLE_Q: "FLE.Q", 592 FLE_S: "FLE.S", 593 FLH: "FLH", 594 FLQ: "FLQ", 595 FLT_D: "FLT.D", 596 FLT_H: "FLT.H", 597 FLT_Q: "FLT.Q", 598 FLT_S: "FLT.S", 599 FLW: "FLW", 600 FMADD_D: "FMADD.D", 601 FMADD_H: "FMADD.H", 602 FMADD_Q: "FMADD.Q", 603 FMADD_S: "FMADD.S", 604 FMAX_D: "FMAX.D", 605 FMAX_H: "FMAX.H", 606 FMAX_Q: "FMAX.Q", 607 FMAX_S: "FMAX.S", 608 FMIN_D: "FMIN.D", 609 FMIN_H: "FMIN.H", 610 FMIN_Q: "FMIN.Q", 611 FMIN_S: "FMIN.S", 612 FMSUB_D: "FMSUB.D", 613 FMSUB_H: "FMSUB.H", 614 FMSUB_Q: "FMSUB.Q", 615 FMSUB_S: "FMSUB.S", 616 FMUL_D: "FMUL.D", 617 FMUL_H: "FMUL.H", 618 FMUL_Q: "FMUL.Q", 619 FMUL_S: "FMUL.S", 620 FMV_D_X: "FMV.D.X", 621 FMV_H_X: "FMV.H.X", 622 FMV_W_X: "FMV.W.X", 623 FMV_X_D: "FMV.X.D", 624 FMV_X_H: "FMV.X.H", 625 FMV_X_W: "FMV.X.W", 626 FNMADD_D: "FNMADD.D", 627 FNMADD_H: "FNMADD.H", 628 FNMADD_Q: "FNMADD.Q", 629 FNMADD_S: "FNMADD.S", 630 FNMSUB_D: "FNMSUB.D", 631 FNMSUB_H: "FNMSUB.H", 632 FNMSUB_Q: "FNMSUB.Q", 633 FNMSUB_S: "FNMSUB.S", 634 FSD: "FSD", 635 FSGNJN_D: "FSGNJN.D", 636 FSGNJN_H: "FSGNJN.H", 637 FSGNJN_Q: "FSGNJN.Q", 638 FSGNJN_S: "FSGNJN.S", 639 FSGNJX_D: "FSGNJX.D", 640 FSGNJX_H: "FSGNJX.H", 641 FSGNJX_Q: "FSGNJX.Q", 642 FSGNJX_S: "FSGNJX.S", 643 FSGNJ_D: "FSGNJ.D", 644 FSGNJ_H: "FSGNJ.H", 645 FSGNJ_Q: "FSGNJ.Q", 646 FSGNJ_S: "FSGNJ.S", 647 FSH: "FSH", 648 FSQ: "FSQ", 649 FSQRT_D: "FSQRT.D", 650 FSQRT_H: "FSQRT.H", 651 FSQRT_Q: "FSQRT.Q", 652 FSQRT_S: "FSQRT.S", 653 FSUB_D: "FSUB.D", 654 FSUB_H: "FSUB.H", 655 FSUB_Q: "FSUB.Q", 656 FSUB_S: "FSUB.S", 657 FSW: "FSW", 658 JAL: "JAL", 659 JALR: "JALR", 660 LB: "LB", 661 LBU: "LBU", 662 LD: "LD", 663 LH: "LH", 664 LHU: "LHU", 665 LR_D: "LR.D", 666 LR_D_AQ: "LR.D.AQ", 667 LR_D_AQRL: "LR.D.AQRL", 668 LR_D_RL: "LR.D.RL", 669 LR_W: "LR.W", 670 LR_W_AQ: "LR.W.AQ", 671 LR_W_AQRL: "LR.W.AQRL", 672 LR_W_RL: "LR.W.RL", 673 LUI: "LUI", 674 LW: "LW", 675 LWU: "LWU", 676 MAX: "MAX", 677 MAXU: "MAXU", 678 MIN: "MIN", 679 MINU: "MINU", 680 MUL: "MUL", 681 MULH: "MULH", 682 MULHSU: "MULHSU", 683 MULHU: "MULHU", 684 MULW: "MULW", 685 OR: "OR", 686 ORC_B: "ORC.B", 687 ORI: "ORI", 688 ORN: "ORN", 689 REM: "REM", 690 REMU: "REMU", 691 REMUW: "REMUW", 692 REMW: "REMW", 693 REV8: "REV8", 694 ROL: "ROL", 695 ROLW: "ROLW", 696 ROR: "ROR", 697 RORI: "RORI", 698 RORIW: "RORIW", 699 RORW: "RORW", 700 SB: "SB", 701 SC_D: "SC.D", 702 SC_D_AQ: "SC.D.AQ", 703 SC_D_AQRL: "SC.D.AQRL", 704 SC_D_RL: "SC.D.RL", 705 SC_W: "SC.W", 706 SC_W_AQ: "SC.W.AQ", 707 SC_W_AQRL: "SC.W.AQRL", 708 SC_W_RL: "SC.W.RL", 709 SD: "SD", 710 SEXT_B: "SEXT.B", 711 SEXT_H: "SEXT.H", 712 SH: "SH", 713 SH1ADD: "SH1ADD", 714 SH1ADD_UW: "SH1ADD.UW", 715 SH2ADD: "SH2ADD", 716 SH2ADD_UW: "SH2ADD.UW", 717 SH3ADD: "SH3ADD", 718 SH3ADD_UW: "SH3ADD.UW", 719 SLL: "SLL", 720 SLLI: "SLLI", 721 SLLIW: "SLLIW", 722 SLLI_UW: "SLLI.UW", 723 SLLW: "SLLW", 724 SLT: "SLT", 725 SLTI: "SLTI", 726 SLTIU: "SLTIU", 727 SLTU: "SLTU", 728 SRA: "SRA", 729 SRAI: "SRAI", 730 SRAIW: "SRAIW", 731 SRAW: "SRAW", 732 SRL: "SRL", 733 SRLI: "SRLI", 734 SRLIW: "SRLIW", 735 SRLW: "SRLW", 736 SUB: "SUB", 737 SUBW: "SUBW", 738 SW: "SW", 739 XNOR: "XNOR", 740 XOR: "XOR", 741 XORI: "XORI", 742 ZEXT_H: "ZEXT.H", 743 } 744 745 var instFormats = [...]instFormat{ 746 // ADD rd, rs1, rs2 747 {mask: 0xfe00707f, value: 0x00000033, op: ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 748 // ADDI rd, rs1, imm12 749 {mask: 0x0000707f, value: 0x00000013, op: ADDI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, 750 // ADDIW rd, rs1, imm12 751 {mask: 0x0000707f, value: 0x0000001b, op: ADDIW, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, 752 // ADDW rd, rs1, rs2 753 {mask: 0xfe00707f, value: 0x0000003b, op: ADDW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 754 // ADD.UW rd, rs1, rs2 755 {mask: 0xfe00707f, value: 0x0800003b, op: ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 756 // AMOADD.D rd, rs2, rs1_amo 757 {mask: 0xfe00707f, value: 0x0000302f, op: AMOADD_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 758 // AMOADD.D.AQ rd, rs2, rs1_amo 759 {mask: 0xfe00707f, value: 0x0400302f, op: AMOADD_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 760 // AMOADD.D.AQRL rd, rs2, rs1_amo 761 {mask: 0xfe00707f, value: 0x0600302f, op: AMOADD_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 762 // AMOADD.D.RL rd, rs2, rs1_amo 763 {mask: 0xfe00707f, value: 0x0200302f, op: AMOADD_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 764 // AMOADD.W rd, rs2, rs1_amo 765 {mask: 0xfe00707f, value: 0x0000202f, op: AMOADD_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 766 // AMOADD.W.AQ rd, rs2, rs1_amo 767 {mask: 0xfe00707f, value: 0x0400202f, op: AMOADD_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 768 // AMOADD.W.AQRL rd, rs2, rs1_amo 769 {mask: 0xfe00707f, value: 0x0600202f, op: AMOADD_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 770 // AMOADD.W.RL rd, rs2, rs1_amo 771 {mask: 0xfe00707f, value: 0x0200202f, op: AMOADD_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 772 // AMOAND.D rd, rs2, rs1_amo 773 {mask: 0xfe00707f, value: 0x6000302f, op: AMOAND_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 774 // AMOAND.D.AQ rd, rs2, rs1_amo 775 {mask: 0xfe00707f, value: 0x6400302f, op: AMOAND_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 776 // AMOAND.D.AQRL rd, rs2, rs1_amo 777 {mask: 0xfe00707f, value: 0x6600302f, op: AMOAND_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 778 // AMOAND.D.RL rd, rs2, rs1_amo 779 {mask: 0xfe00707f, value: 0x6200302f, op: AMOAND_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 780 // AMOAND.W rd, rs2, rs1_amo 781 {mask: 0xfe00707f, value: 0x6000202f, op: AMOAND_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 782 // AMOAND.W.AQ rd, rs2, rs1_amo 783 {mask: 0xfe00707f, value: 0x6400202f, op: AMOAND_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 784 // AMOAND.W.AQRL rd, rs2, rs1_amo 785 {mask: 0xfe00707f, value: 0x6600202f, op: AMOAND_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 786 // AMOAND.W.RL rd, rs2, rs1_amo 787 {mask: 0xfe00707f, value: 0x6200202f, op: AMOAND_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 788 // AMOMAXU.D rd, rs2, rs1_amo 789 {mask: 0xfe00707f, value: 0xe000302f, op: AMOMAXU_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 790 // AMOMAXU.D.AQ rd, rs2, rs1_amo 791 {mask: 0xfe00707f, value: 0xe400302f, op: AMOMAXU_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 792 // AMOMAXU.D.AQRL rd, rs2, rs1_amo 793 {mask: 0xfe00707f, value: 0xe600302f, op: AMOMAXU_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 794 // AMOMAXU.D.RL rd, rs2, rs1_amo 795 {mask: 0xfe00707f, value: 0xe200302f, op: AMOMAXU_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 796 // AMOMAXU.W rd, rs2, rs1_amo 797 {mask: 0xfe00707f, value: 0xe000202f, op: AMOMAXU_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 798 // AMOMAXU.W.AQ rd, rs2, rs1_amo 799 {mask: 0xfe00707f, value: 0xe400202f, op: AMOMAXU_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 800 // AMOMAXU.W.AQRL rd, rs2, rs1_amo 801 {mask: 0xfe00707f, value: 0xe600202f, op: AMOMAXU_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 802 // AMOMAXU.W.RL rd, rs2, rs1_amo 803 {mask: 0xfe00707f, value: 0xe200202f, op: AMOMAXU_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 804 // AMOMAX.D rd, rs2, rs1_amo 805 {mask: 0xfe00707f, value: 0xa000302f, op: AMOMAX_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 806 // AMOMAX.D.AQ rd, rs2, rs1_amo 807 {mask: 0xfe00707f, value: 0xa400302f, op: AMOMAX_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 808 // AMOMAX.D.AQRL rd, rs2, rs1_amo 809 {mask: 0xfe00707f, value: 0xa600302f, op: AMOMAX_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 810 // AMOMAX.D.RL rd, rs2, rs1_amo 811 {mask: 0xfe00707f, value: 0xa200302f, op: AMOMAX_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 812 // AMOMAX.W rd, rs2, rs1_amo 813 {mask: 0xfe00707f, value: 0xa000202f, op: AMOMAX_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 814 // AMOMAX.W.AQ rd, rs2, rs1_amo 815 {mask: 0xfe00707f, value: 0xa400202f, op: AMOMAX_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 816 // AMOMAX.W.AQRL rd, rs2, rs1_amo 817 {mask: 0xfe00707f, value: 0xa600202f, op: AMOMAX_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 818 // AMOMAX.W.RL rd, rs2, rs1_amo 819 {mask: 0xfe00707f, value: 0xa200202f, op: AMOMAX_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 820 // AMOMINU.D rd, rs2, rs1_amo 821 {mask: 0xfe00707f, value: 0xc000302f, op: AMOMINU_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 822 // AMOMINU.D.AQ rd, rs2, rs1_amo 823 {mask: 0xfe00707f, value: 0xc400302f, op: AMOMINU_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 824 // AMOMINU.D.AQRL rd, rs2, rs1_amo 825 {mask: 0xfe00707f, value: 0xc600302f, op: AMOMINU_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 826 // AMOMINU.D.RL rd, rs2, rs1_amo 827 {mask: 0xfe00707f, value: 0xc200302f, op: AMOMINU_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 828 // AMOMINU.W rd, rs2, rs1_amo 829 {mask: 0xfe00707f, value: 0xc000202f, op: AMOMINU_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 830 // AMOMINU.W.AQ rd, rs2, rs1_amo 831 {mask: 0xfe00707f, value: 0xc400202f, op: AMOMINU_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 832 // AMOMINU.W.AQRL rd, rs2, rs1_amo 833 {mask: 0xfe00707f, value: 0xc600202f, op: AMOMINU_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 834 // AMOMINU.W.RL rd, rs2, rs1_amo 835 {mask: 0xfe00707f, value: 0xc200202f, op: AMOMINU_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 836 // AMOMIN.D rd, rs2, rs1_amo 837 {mask: 0xfe00707f, value: 0x8000302f, op: AMOMIN_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 838 // AMOMIN.D.AQ rd, rs2, rs1_amo 839 {mask: 0xfe00707f, value: 0x8400302f, op: AMOMIN_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 840 // AMOMIN.D.AQRL rd, rs2, rs1_amo 841 {mask: 0xfe00707f, value: 0x8600302f, op: AMOMIN_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 842 // AMOMIN.D.RL rd, rs2, rs1_amo 843 {mask: 0xfe00707f, value: 0x8200302f, op: AMOMIN_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 844 // AMOMIN.W rd, rs2, rs1_amo 845 {mask: 0xfe00707f, value: 0x8000202f, op: AMOMIN_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 846 // AMOMIN.W.AQ rd, rs2, rs1_amo 847 {mask: 0xfe00707f, value: 0x8400202f, op: AMOMIN_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 848 // AMOMIN.W.AQRL rd, rs2, rs1_amo 849 {mask: 0xfe00707f, value: 0x8600202f, op: AMOMIN_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 850 // AMOMIN.W.RL rd, rs2, rs1_amo 851 {mask: 0xfe00707f, value: 0x8200202f, op: AMOMIN_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 852 // AMOOR.D rd, rs2, rs1_amo 853 {mask: 0xfe00707f, value: 0x4000302f, op: AMOOR_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 854 // AMOOR.D.AQ rd, rs2, rs1_amo 855 {mask: 0xfe00707f, value: 0x4400302f, op: AMOOR_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 856 // AMOOR.D.AQRL rd, rs2, rs1_amo 857 {mask: 0xfe00707f, value: 0x4600302f, op: AMOOR_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 858 // AMOOR.D.RL rd, rs2, rs1_amo 859 {mask: 0xfe00707f, value: 0x4200302f, op: AMOOR_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 860 // AMOOR.W rd, rs2, rs1_amo 861 {mask: 0xfe00707f, value: 0x4000202f, op: AMOOR_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 862 // AMOOR.W.AQ rd, rs2, rs1_amo 863 {mask: 0xfe00707f, value: 0x4400202f, op: AMOOR_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 864 // AMOOR.W.AQRL rd, rs2, rs1_amo 865 {mask: 0xfe00707f, value: 0x4600202f, op: AMOOR_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 866 // AMOOR.W.RL rd, rs2, rs1_amo 867 {mask: 0xfe00707f, value: 0x4200202f, op: AMOOR_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 868 // AMOSWAP.D rd, rs2, rs1_amo 869 {mask: 0xfe00707f, value: 0x0800302f, op: AMOSWAP_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 870 // AMOSWAP.D.AQ rd, rs2, rs1_amo 871 {mask: 0xfe00707f, value: 0x0c00302f, op: AMOSWAP_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 872 // AMOSWAP.D.AQRL rd, rs2, rs1_amo 873 {mask: 0xfe00707f, value: 0x0e00302f, op: AMOSWAP_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 874 // AMOSWAP.D.RL rd, rs2, rs1_amo 875 {mask: 0xfe00707f, value: 0x0a00302f, op: AMOSWAP_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 876 // AMOSWAP.W rd, rs2, rs1_amo 877 {mask: 0xfe00707f, value: 0x0800202f, op: AMOSWAP_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 878 // AMOSWAP.W.AQ rd, rs2, rs1_amo 879 {mask: 0xfe00707f, value: 0x0c00202f, op: AMOSWAP_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 880 // AMOSWAP.W.AQRL rd, rs2, rs1_amo 881 {mask: 0xfe00707f, value: 0x0e00202f, op: AMOSWAP_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 882 // AMOSWAP.W.RL rd, rs2, rs1_amo 883 {mask: 0xfe00707f, value: 0x0a00202f, op: AMOSWAP_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 884 // AMOXOR.D rd, rs2, rs1_amo 885 {mask: 0xfe00707f, value: 0x2000302f, op: AMOXOR_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 886 // AMOXOR.D.AQ rd, rs2, rs1_amo 887 {mask: 0xfe00707f, value: 0x2400302f, op: AMOXOR_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 888 // AMOXOR.D.AQRL rd, rs2, rs1_amo 889 {mask: 0xfe00707f, value: 0x2600302f, op: AMOXOR_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 890 // AMOXOR.D.RL rd, rs2, rs1_amo 891 {mask: 0xfe00707f, value: 0x2200302f, op: AMOXOR_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 892 // AMOXOR.W rd, rs2, rs1_amo 893 {mask: 0xfe00707f, value: 0x2000202f, op: AMOXOR_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 894 // AMOXOR.W.AQ rd, rs2, rs1_amo 895 {mask: 0xfe00707f, value: 0x2400202f, op: AMOXOR_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 896 // AMOXOR.W.AQRL rd, rs2, rs1_amo 897 {mask: 0xfe00707f, value: 0x2600202f, op: AMOXOR_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 898 // AMOXOR.W.RL rd, rs2, rs1_amo 899 {mask: 0xfe00707f, value: 0x2200202f, op: AMOXOR_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 900 // AND rd, rs1, rs2 901 {mask: 0xfe00707f, value: 0x00007033, op: AND, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 902 // ANDI rd, rs1, imm12 903 {mask: 0x0000707f, value: 0x00007013, op: ANDI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, 904 // ANDN rd, rs1, rs2 905 {mask: 0xfe00707f, value: 0x40007033, op: ANDN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 906 // AUIPC rd, imm20 907 {mask: 0x0000007f, value: 0x00000017, op: AUIPC, args: argTypeList{arg_rd, arg_imm20}}, 908 // BCLR rd, rs1, rs2 909 {mask: 0xfe00707f, value: 0x48001033, op: BCLR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 910 // BCLRI rd, rs1, shamt6 911 {mask: 0xfc00707f, value: 0x48001013, op: BCLRI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, 912 // BEQ rs1, rs2, bimm12 913 {mask: 0x0000707f, value: 0x00000063, op: BEQ, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, 914 // BEXT rd, rs1, rs2 915 {mask: 0xfe00707f, value: 0x48005033, op: BEXT, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 916 // BEXTI rd, rs1, shamt6 917 {mask: 0xfc00707f, value: 0x48005013, op: BEXTI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, 918 // BGE rs1, rs2, bimm12 919 {mask: 0x0000707f, value: 0x00005063, op: BGE, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, 920 // BGEU rs1, rs2, bimm12 921 {mask: 0x0000707f, value: 0x00007063, op: BGEU, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, 922 // BINV rd, rs1, rs2 923 {mask: 0xfe00707f, value: 0x68001033, op: BINV, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 924 // BINVI rd, rs1, shamt6 925 {mask: 0xfc00707f, value: 0x68001013, op: BINVI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, 926 // BLT rs1, rs2, bimm12 927 {mask: 0x0000707f, value: 0x00004063, op: BLT, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, 928 // BLTU rs1, rs2, bimm12 929 {mask: 0x0000707f, value: 0x00006063, op: BLTU, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, 930 // BNE rs1, rs2, bimm12 931 {mask: 0x0000707f, value: 0x00001063, op: BNE, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, 932 // BSET rd, rs1, rs2 933 {mask: 0xfe00707f, value: 0x28001033, op: BSET, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 934 // BSETI rd, rs1, shamt6 935 {mask: 0xfc00707f, value: 0x28001013, op: BSETI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, 936 // CLZ rd, rs1 937 {mask: 0xfff0707f, value: 0x60001013, op: CLZ, args: argTypeList{arg_rd, arg_rs1}}, 938 // CLZW rd, rs1 939 {mask: 0xfff0707f, value: 0x6000101b, op: CLZW, args: argTypeList{arg_rd, arg_rs1}}, 940 // CPOP rd, rs1 941 {mask: 0xfff0707f, value: 0x60201013, op: CPOP, args: argTypeList{arg_rd, arg_rs1}}, 942 // CPOPW rd, rs1 943 {mask: 0xfff0707f, value: 0x6020101b, op: CPOPW, args: argTypeList{arg_rd, arg_rs1}}, 944 // CSRRC rd, csr, rs1 945 {mask: 0x0000707f, value: 0x00003073, op: CSRRC, args: argTypeList{arg_rd, arg_csr, arg_rs1}}, 946 // CSRRCI rd, csr, zimm 947 {mask: 0x0000707f, value: 0x00007073, op: CSRRCI, args: argTypeList{arg_rd, arg_csr, arg_zimm}}, 948 // CSRRS rd, csr, rs1 949 {mask: 0x0000707f, value: 0x00002073, op: CSRRS, args: argTypeList{arg_rd, arg_csr, arg_rs1}}, 950 // CSRRSI rd, csr, zimm 951 {mask: 0x0000707f, value: 0x00006073, op: CSRRSI, args: argTypeList{arg_rd, arg_csr, arg_zimm}}, 952 // CSRRW rd, csr, rs1 953 {mask: 0x0000707f, value: 0x00001073, op: CSRRW, args: argTypeList{arg_rd, arg_csr, arg_rs1}}, 954 // CSRRWI rd, csr, zimm 955 {mask: 0x0000707f, value: 0x00005073, op: CSRRWI, args: argTypeList{arg_rd, arg_csr, arg_zimm}}, 956 // CTZ rd, rs1 957 {mask: 0xfff0707f, value: 0x60101013, op: CTZ, args: argTypeList{arg_rd, arg_rs1}}, 958 // CTZW rd, rs1 959 {mask: 0xfff0707f, value: 0x6010101b, op: CTZW, args: argTypeList{arg_rd, arg_rs1}}, 960 // C.ADD rd_rs1_n0, c_rs2_n0 961 {mask: 0x0000f003, value: 0x00009002, op: C_ADD, args: argTypeList{arg_rd_rs1_n0, arg_c_rs2_n0}}, 962 // C.ADDI rd_rs1_n0, c_nzimm6 963 {mask: 0x0000e003, value: 0x00000001, op: C_ADDI, args: argTypeList{arg_rd_rs1_n0, arg_c_nzimm6}}, 964 // C.ADDI16SP c_nzimm10 965 {mask: 0x0000ef83, value: 0x00006101, op: C_ADDI16SP, args: argTypeList{arg_c_nzimm10}}, 966 // C.ADDI4SPN rd_p, c_nzuimm10 967 {mask: 0x0000e003, value: 0x00000000, op: C_ADDI4SPN, args: argTypeList{arg_rd_p, arg_c_nzuimm10}}, 968 // C.ADDIW rd_rs1_n0, c_imm6 969 {mask: 0x0000e003, value: 0x00002001, op: C_ADDIW, args: argTypeList{arg_rd_rs1_n0, arg_c_imm6}}, 970 // C.ADDW rd_rs1_p, rs2_p 971 {mask: 0x0000fc63, value: 0x00009c21, op: C_ADDW, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, 972 // C.AND rd_rs1_p, rs2_p 973 {mask: 0x0000fc63, value: 0x00008c61, op: C_AND, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, 974 // C.ANDI rd_rs1_p, c_imm6 975 {mask: 0x0000ec03, value: 0x00008801, op: C_ANDI, args: argTypeList{arg_rd_rs1_p, arg_c_imm6}}, 976 // C.BEQZ rs1_p, c_bimm9 977 {mask: 0x0000e003, value: 0x0000c001, op: C_BEQZ, args: argTypeList{arg_rs1_p, arg_c_bimm9}}, 978 // C.BNEZ rs1_p, c_bimm9 979 {mask: 0x0000e003, value: 0x0000e001, op: C_BNEZ, args: argTypeList{arg_rs1_p, arg_c_bimm9}}, 980 // C.EBREAK 981 {mask: 0x0000ffff, value: 0x00009002, op: C_EBREAK, args: argTypeList{}}, 982 // C.FLD fd_p, rs1_p, c_uimm8 983 {mask: 0x0000e003, value: 0x00002000, op: C_FLD, args: argTypeList{arg_fd_p, arg_rs1_p, arg_c_uimm8}}, 984 // C.FLDSP fd, c_uimm9sp 985 {mask: 0x0000e003, value: 0x00002002, op: C_FLDSP, args: argTypeList{arg_fd, arg_c_uimm9sp}}, 986 // C.FSD rs1_p, fs2_p, c_uimm8 987 {mask: 0x0000e003, value: 0x0000a000, op: C_FSD, args: argTypeList{arg_rs1_p, arg_fs2_p, arg_c_uimm8}}, 988 // C.FSDSP c_fs2, c_uimm9sp_s 989 {mask: 0x0000e003, value: 0x0000a002, op: C_FSDSP, args: argTypeList{arg_c_fs2, arg_c_uimm9sp_s}}, 990 // C.J c_imm12 991 {mask: 0x0000e003, value: 0x0000a001, op: C_J, args: argTypeList{arg_c_imm12}}, 992 // C.JALR c_rs1_n0 993 {mask: 0x0000f07f, value: 0x00009002, op: C_JALR, args: argTypeList{arg_c_rs1_n0}}, 994 // C.JR rs1_n0 995 {mask: 0x0000f07f, value: 0x00008002, op: C_JR, args: argTypeList{arg_rs1_n0}}, 996 // C.LD rd_p, rs1_p, c_uimm8 997 {mask: 0x0000e003, value: 0x00006000, op: C_LD, args: argTypeList{arg_rd_p, arg_rs1_p, arg_c_uimm8}}, 998 // C.LDSP rd_n0, c_uimm9sp 999 {mask: 0x0000e003, value: 0x00006002, op: C_LDSP, args: argTypeList{arg_rd_n0, arg_c_uimm9sp}}, 1000 // C.LI rd_n0, c_imm6 1001 {mask: 0x0000e003, value: 0x00004001, op: C_LI, args: argTypeList{arg_rd_n0, arg_c_imm6}}, 1002 // C.LUI rd_n2, c_nzimm18 1003 {mask: 0x0000e003, value: 0x00006001, op: C_LUI, args: argTypeList{arg_rd_n2, arg_c_nzimm18}}, 1004 // C.LW rd_p, rs1_p, c_uimm7 1005 {mask: 0x0000e003, value: 0x00004000, op: C_LW, args: argTypeList{arg_rd_p, arg_rs1_p, arg_c_uimm7}}, 1006 // C.LWSP rd_n0, c_uimm8sp 1007 {mask: 0x0000e003, value: 0x00004002, op: C_LWSP, args: argTypeList{arg_rd_n0, arg_c_uimm8sp}}, 1008 // C.MV rd_n0, c_rs2_n0 1009 {mask: 0x0000f003, value: 0x00008002, op: C_MV, args: argTypeList{arg_rd_n0, arg_c_rs2_n0}}, 1010 // C.NOP c_nzimm6 1011 {mask: 0x0000ef83, value: 0x00000001, op: C_NOP, args: argTypeList{arg_c_nzimm6}}, 1012 // C.OR rd_rs1_p, rs2_p 1013 {mask: 0x0000fc63, value: 0x00008c41, op: C_OR, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, 1014 // C.SD rs1_p, rs2_p, c_uimm8 1015 {mask: 0x0000e003, value: 0x0000e000, op: C_SD, args: argTypeList{arg_rs1_p, arg_rs2_p, arg_c_uimm8}}, 1016 // C.SDSP c_rs2, c_uimm9sp_s 1017 {mask: 0x0000e003, value: 0x0000e002, op: C_SDSP, args: argTypeList{arg_c_rs2, arg_c_uimm9sp_s}}, 1018 // C.SLLI rd_rs1_n0, c_nzuimm6 1019 {mask: 0x0000e003, value: 0x00000002, op: C_SLLI, args: argTypeList{arg_rd_rs1_n0, arg_c_nzuimm6}}, 1020 // C.SRAI rd_rs1_p, c_nzuimm6 1021 {mask: 0x0000ec03, value: 0x00008401, op: C_SRAI, args: argTypeList{arg_rd_rs1_p, arg_c_nzuimm6}}, 1022 // C.SRLI rd_rs1_p, c_nzuimm6 1023 {mask: 0x0000ec03, value: 0x00008001, op: C_SRLI, args: argTypeList{arg_rd_rs1_p, arg_c_nzuimm6}}, 1024 // C.SUB rd_rs1_p, rs2_p 1025 {mask: 0x0000fc63, value: 0x00008c01, op: C_SUB, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, 1026 // C.SUBW rd_rs1_p, rs2_p 1027 {mask: 0x0000fc63, value: 0x00009c01, op: C_SUBW, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, 1028 // C.SW rs1_p, rs2_p, c_uimm7 1029 {mask: 0x0000e003, value: 0x0000c000, op: C_SW, args: argTypeList{arg_rs1_p, arg_rs2_p, arg_c_uimm7}}, 1030 // C.SWSP c_rs2, c_uimm8sp_s 1031 {mask: 0x0000e003, value: 0x0000c002, op: C_SWSP, args: argTypeList{arg_c_rs2, arg_c_uimm8sp_s}}, 1032 // C.UNIMP 1033 {mask: 0x0000ffff, value: 0x00000000, op: C_UNIMP, args: argTypeList{}}, 1034 // C.XOR rd_rs1_p, rs2_p 1035 {mask: 0x0000fc63, value: 0x00008c21, op: C_XOR, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, 1036 // DIV rd, rs1, rs2 1037 {mask: 0xfe00707f, value: 0x02004033, op: DIV, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1038 // DIVU rd, rs1, rs2 1039 {mask: 0xfe00707f, value: 0x02005033, op: DIVU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1040 // DIVUW rd, rs1, rs2 1041 {mask: 0xfe00707f, value: 0x0200503b, op: DIVUW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1042 // DIVW rd, rs1, rs2 1043 {mask: 0xfe00707f, value: 0x0200403b, op: DIVW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1044 // EBREAK 1045 {mask: 0xffffffff, value: 0x00100073, op: EBREAK, args: argTypeList{}}, 1046 // ECALL 1047 {mask: 0xffffffff, value: 0x00000073, op: ECALL, args: argTypeList{}}, 1048 // FADD.D fd, fs1, fs2 1049 {mask: 0xfe00007f, value: 0x02000053, op: FADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1050 // FADD.H fd, fs1, fs2 1051 {mask: 0xfe00007f, value: 0x04000053, op: FADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1052 // FADD.Q fd, fs1, fs2 1053 {mask: 0xfe00007f, value: 0x06000053, op: FADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1054 // FADD.S fd, fs1, fs2 1055 {mask: 0xfe00007f, value: 0x00000053, op: FADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1056 // FCLASS.D rd, fs1 1057 {mask: 0xfff0707f, value: 0xe2001053, op: FCLASS_D, args: argTypeList{arg_rd, arg_fs1}}, 1058 // FCLASS.H rd, fs1 1059 {mask: 0xfff0707f, value: 0xe4001053, op: FCLASS_H, args: argTypeList{arg_rd, arg_fs1}}, 1060 // FCLASS.Q rd, fs1 1061 {mask: 0xfff0707f, value: 0xe6001053, op: FCLASS_Q, args: argTypeList{arg_rd, arg_fs1}}, 1062 // FCLASS.S rd, fs1 1063 {mask: 0xfff0707f, value: 0xe0001053, op: FCLASS_S, args: argTypeList{arg_rd, arg_fs1}}, 1064 // FCVT.D.L fd, rs1 1065 {mask: 0xfff0007f, value: 0xd2200053, op: FCVT_D_L, args: argTypeList{arg_fd, arg_rs1}}, 1066 // FCVT.D.LU fd, rs1 1067 {mask: 0xfff0007f, value: 0xd2300053, op: FCVT_D_LU, args: argTypeList{arg_fd, arg_rs1}}, 1068 // FCVT.D.Q fd, fs1 1069 {mask: 0xfff0007f, value: 0x42300053, op: FCVT_D_Q, args: argTypeList{arg_fd, arg_fs1}}, 1070 // FCVT.D.S fd, fs1 1071 {mask: 0xfff0007f, value: 0x42000053, op: FCVT_D_S, args: argTypeList{arg_fd, arg_fs1}}, 1072 // FCVT.D.W fd, rs1 1073 {mask: 0xfff0007f, value: 0xd2000053, op: FCVT_D_W, args: argTypeList{arg_fd, arg_rs1}}, 1074 // FCVT.D.WU fd, rs1 1075 {mask: 0xfff0007f, value: 0xd2100053, op: FCVT_D_WU, args: argTypeList{arg_fd, arg_rs1}}, 1076 // FCVT.H.L fd, rs1 1077 {mask: 0xfff0007f, value: 0xd4200053, op: FCVT_H_L, args: argTypeList{arg_fd, arg_rs1}}, 1078 // FCVT.H.LU fd, rs1 1079 {mask: 0xfff0007f, value: 0xd4300053, op: FCVT_H_LU, args: argTypeList{arg_fd, arg_rs1}}, 1080 // FCVT.H.S fd, fs1 1081 {mask: 0xfff0007f, value: 0x44000053, op: FCVT_H_S, args: argTypeList{arg_fd, arg_fs1}}, 1082 // FCVT.H.W fd, rs1 1083 {mask: 0xfff0007f, value: 0xd4000053, op: FCVT_H_W, args: argTypeList{arg_fd, arg_rs1}}, 1084 // FCVT.H.WU fd, rs1 1085 {mask: 0xfff0007f, value: 0xd4100053, op: FCVT_H_WU, args: argTypeList{arg_fd, arg_rs1}}, 1086 // FCVT.LU.D rd, fs1 1087 {mask: 0xfff0007f, value: 0xc2300053, op: FCVT_LU_D, args: argTypeList{arg_rd, arg_fs1}}, 1088 // FCVT.LU.H rd, fs1 1089 {mask: 0xfff0007f, value: 0xc4300053, op: FCVT_LU_H, args: argTypeList{arg_rd, arg_fs1}}, 1090 // FCVT.LU.Q rd, fs1 1091 {mask: 0xfff0007f, value: 0xc6300053, op: FCVT_LU_Q, args: argTypeList{arg_rd, arg_fs1}}, 1092 // FCVT.LU.S rd, fs1 1093 {mask: 0xfff0007f, value: 0xc0300053, op: FCVT_LU_S, args: argTypeList{arg_rd, arg_fs1}}, 1094 // FCVT.L.D rd, fs1 1095 {mask: 0xfff0007f, value: 0xc2200053, op: FCVT_L_D, args: argTypeList{arg_rd, arg_fs1}}, 1096 // FCVT.L.H rd, fs1 1097 {mask: 0xfff0007f, value: 0xc4200053, op: FCVT_L_H, args: argTypeList{arg_rd, arg_fs1}}, 1098 // FCVT.L.Q rd, fs1 1099 {mask: 0xfff0007f, value: 0xc6200053, op: FCVT_L_Q, args: argTypeList{arg_rd, arg_fs1}}, 1100 // FCVT.L.S rd, fs1 1101 {mask: 0xfff0007f, value: 0xc0200053, op: FCVT_L_S, args: argTypeList{arg_rd, arg_fs1}}, 1102 // FCVT.Q.D fd, fs1 1103 {mask: 0xfff0007f, value: 0x46100053, op: FCVT_Q_D, args: argTypeList{arg_fd, arg_fs1}}, 1104 // FCVT.Q.L fd, rs1 1105 {mask: 0xfff0007f, value: 0xd6200053, op: FCVT_Q_L, args: argTypeList{arg_fd, arg_rs1}}, 1106 // FCVT.Q.LU fd, rs1 1107 {mask: 0xfff0007f, value: 0xd6300053, op: FCVT_Q_LU, args: argTypeList{arg_fd, arg_rs1}}, 1108 // FCVT.Q.S fd, fs1 1109 {mask: 0xfff0007f, value: 0x46000053, op: FCVT_Q_S, args: argTypeList{arg_fd, arg_fs1}}, 1110 // FCVT.Q.W fd, rs1 1111 {mask: 0xfff0007f, value: 0xd6000053, op: FCVT_Q_W, args: argTypeList{arg_fd, arg_rs1}}, 1112 // FCVT.Q.WU fd, rs1 1113 {mask: 0xfff0007f, value: 0xd6100053, op: FCVT_Q_WU, args: argTypeList{arg_fd, arg_rs1}}, 1114 // FCVT.S.D fd, fs1 1115 {mask: 0xfff0007f, value: 0x40100053, op: FCVT_S_D, args: argTypeList{arg_fd, arg_fs1}}, 1116 // FCVT.S.H fd, fs1 1117 {mask: 0xfff0007f, value: 0x40200053, op: FCVT_S_H, args: argTypeList{arg_fd, arg_fs1}}, 1118 // FCVT.S.L fd, rs1 1119 {mask: 0xfff0007f, value: 0xd0200053, op: FCVT_S_L, args: argTypeList{arg_fd, arg_rs1}}, 1120 // FCVT.S.LU fd, rs1 1121 {mask: 0xfff0007f, value: 0xd0300053, op: FCVT_S_LU, args: argTypeList{arg_fd, arg_rs1}}, 1122 // FCVT.S.Q fd, fs1 1123 {mask: 0xfff0007f, value: 0x40300053, op: FCVT_S_Q, args: argTypeList{arg_fd, arg_fs1}}, 1124 // FCVT.S.W fd, rs1 1125 {mask: 0xfff0007f, value: 0xd0000053, op: FCVT_S_W, args: argTypeList{arg_fd, arg_rs1}}, 1126 // FCVT.S.WU fd, rs1 1127 {mask: 0xfff0007f, value: 0xd0100053, op: FCVT_S_WU, args: argTypeList{arg_fd, arg_rs1}}, 1128 // FCVT.WU.D rd, fs1 1129 {mask: 0xfff0007f, value: 0xc2100053, op: FCVT_WU_D, args: argTypeList{arg_rd, arg_fs1}}, 1130 // FCVT.WU.H rd, fs1 1131 {mask: 0xfff0007f, value: 0xc4100053, op: FCVT_WU_H, args: argTypeList{arg_rd, arg_fs1}}, 1132 // FCVT.WU.Q rd, fs1 1133 {mask: 0xfff0007f, value: 0xc6100053, op: FCVT_WU_Q, args: argTypeList{arg_rd, arg_fs1}}, 1134 // FCVT.WU.S rd, fs1 1135 {mask: 0xfff0007f, value: 0xc0100053, op: FCVT_WU_S, args: argTypeList{arg_rd, arg_fs1}}, 1136 // FCVT.W.D rd, fs1 1137 {mask: 0xfff0007f, value: 0xc2000053, op: FCVT_W_D, args: argTypeList{arg_rd, arg_fs1}}, 1138 // FCVT.W.H rd, fs1 1139 {mask: 0xfff0007f, value: 0xc4000053, op: FCVT_W_H, args: argTypeList{arg_rd, arg_fs1}}, 1140 // FCVT.W.Q rd, fs1 1141 {mask: 0xfff0007f, value: 0xc6000053, op: FCVT_W_Q, args: argTypeList{arg_rd, arg_fs1}}, 1142 // FCVT.W.S rd, fs1 1143 {mask: 0xfff0007f, value: 0xc0000053, op: FCVT_W_S, args: argTypeList{arg_rd, arg_fs1}}, 1144 // FDIV.D fd, fs1, fs2 1145 {mask: 0xfe00007f, value: 0x1a000053, op: FDIV_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1146 // FDIV.H fd, fs1, fs2 1147 {mask: 0xfe00007f, value: 0x1c000053, op: FDIV_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1148 // FDIV.Q fd, fs1, fs2 1149 {mask: 0xfe00007f, value: 0x1e000053, op: FDIV_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1150 // FDIV.S fd, fs1, fs2 1151 {mask: 0xfe00007f, value: 0x18000053, op: FDIV_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1152 // FENCE pred, succ 1153 {mask: 0x0000707f, value: 0x0000000f, op: FENCE, args: argTypeList{arg_pred, arg_succ}}, 1154 // FENCE.I 1155 {mask: 0x0000707f, value: 0x0000100f, op: FENCE_I, args: argTypeList{}}, 1156 // FEQ.D rd, fs1, fs2 1157 {mask: 0xfe00707f, value: 0xa2002053, op: FEQ_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, 1158 // FEQ.H rd, fs1, fs2 1159 {mask: 0xfe00707f, value: 0xa4002053, op: FEQ_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, 1160 // FEQ.Q rd, fs1, fs2 1161 {mask: 0xfe00707f, value: 0xa6002053, op: FEQ_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, 1162 // FEQ.S rd, fs1, fs2 1163 {mask: 0xfe00707f, value: 0xa0002053, op: FEQ_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, 1164 // FLD fd, rs1_mem 1165 {mask: 0x0000707f, value: 0x00003007, op: FLD, args: argTypeList{arg_fd, arg_rs1_mem}}, 1166 // FLE.D rd, fs1, fs2 1167 {mask: 0xfe00707f, value: 0xa2000053, op: FLE_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, 1168 // FLE.H rd, fs1, fs2 1169 {mask: 0xfe00707f, value: 0xa4000053, op: FLE_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, 1170 // FLE.Q rd, fs1, fs2 1171 {mask: 0xfe00707f, value: 0xa6000053, op: FLE_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, 1172 // FLE.S rd, fs1, fs2 1173 {mask: 0xfe00707f, value: 0xa0000053, op: FLE_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, 1174 // FLH fd, rs1_mem 1175 {mask: 0x0000707f, value: 0x00001007, op: FLH, args: argTypeList{arg_fd, arg_rs1_mem}}, 1176 // FLQ fd, rs1_mem 1177 {mask: 0x0000707f, value: 0x00004007, op: FLQ, args: argTypeList{arg_fd, arg_rs1_mem}}, 1178 // FLT.D rd, fs1, fs2 1179 {mask: 0xfe00707f, value: 0xa2001053, op: FLT_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, 1180 // FLT.H rd, fs1, fs2 1181 {mask: 0xfe00707f, value: 0xa4001053, op: FLT_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, 1182 // FLT.Q rd, fs1, fs2 1183 {mask: 0xfe00707f, value: 0xa6001053, op: FLT_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, 1184 // FLT.S rd, fs1, fs2 1185 {mask: 0xfe00707f, value: 0xa0001053, op: FLT_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, 1186 // FLW fd, rs1_mem 1187 {mask: 0x0000707f, value: 0x00002007, op: FLW, args: argTypeList{arg_fd, arg_rs1_mem}}, 1188 // FMADD.D fd, fs1, fs2, fs3 1189 {mask: 0x0600007f, value: 0x02000043, op: FMADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1190 // FMADD.H fd, fs1, fs2, fs3 1191 {mask: 0x0600007f, value: 0x04000043, op: FMADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1192 // FMADD.Q fd, fs1, fs2, fs3 1193 {mask: 0x0600007f, value: 0x06000043, op: FMADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1194 // FMADD.S fd, fs1, fs2, fs3 1195 {mask: 0x0600007f, value: 0x00000043, op: FMADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1196 // FMAX.D fd, fs1, fs2 1197 {mask: 0xfe00707f, value: 0x2a001053, op: FMAX_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1198 // FMAX.H fd, fs1, fs2 1199 {mask: 0xfe00707f, value: 0x2c001053, op: FMAX_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1200 // FMAX.Q fd, fs1, fs2 1201 {mask: 0xfe00707f, value: 0x2e001053, op: FMAX_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1202 // FMAX.S fd, fs1, fs2 1203 {mask: 0xfe00707f, value: 0x28001053, op: FMAX_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1204 // FMIN.D fd, fs1, fs2 1205 {mask: 0xfe00707f, value: 0x2a000053, op: FMIN_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1206 // FMIN.H fd, fs1, fs2 1207 {mask: 0xfe00707f, value: 0x2c000053, op: FMIN_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1208 // FMIN.Q fd, fs1, fs2 1209 {mask: 0xfe00707f, value: 0x2e000053, op: FMIN_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1210 // FMIN.S fd, fs1, fs2 1211 {mask: 0xfe00707f, value: 0x28000053, op: FMIN_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1212 // FMSUB.D fd, fs1, fs2, fs3 1213 {mask: 0x0600007f, value: 0x02000047, op: FMSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1214 // FMSUB.H fd, fs1, fs2, fs3 1215 {mask: 0x0600007f, value: 0x04000047, op: FMSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1216 // FMSUB.Q fd, fs1, fs2, fs3 1217 {mask: 0x0600007f, value: 0x06000047, op: FMSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1218 // FMSUB.S fd, fs1, fs2, fs3 1219 {mask: 0x0600007f, value: 0x00000047, op: FMSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1220 // FMUL.D fd, fs1, fs2 1221 {mask: 0xfe00007f, value: 0x12000053, op: FMUL_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1222 // FMUL.H fd, fs1, fs2 1223 {mask: 0xfe00007f, value: 0x14000053, op: FMUL_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1224 // FMUL.Q fd, fs1, fs2 1225 {mask: 0xfe00007f, value: 0x16000053, op: FMUL_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1226 // FMUL.S fd, fs1, fs2 1227 {mask: 0xfe00007f, value: 0x10000053, op: FMUL_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1228 // FMV.D.X fd, rs1 1229 {mask: 0xfff0707f, value: 0xf2000053, op: FMV_D_X, args: argTypeList{arg_fd, arg_rs1}}, 1230 // FMV.H.X fd, rs1 1231 {mask: 0xfff0707f, value: 0xf4000053, op: FMV_H_X, args: argTypeList{arg_fd, arg_rs1}}, 1232 // FMV.W.X fd, rs1 1233 {mask: 0xfff0707f, value: 0xf0000053, op: FMV_W_X, args: argTypeList{arg_fd, arg_rs1}}, 1234 // FMV.X.D rd, fs1 1235 {mask: 0xfff0707f, value: 0xe2000053, op: FMV_X_D, args: argTypeList{arg_rd, arg_fs1}}, 1236 // FMV.X.H rd, fs1 1237 {mask: 0xfff0707f, value: 0xe4000053, op: FMV_X_H, args: argTypeList{arg_rd, arg_fs1}}, 1238 // FMV.X.W rd, fs1 1239 {mask: 0xfff0707f, value: 0xe0000053, op: FMV_X_W, args: argTypeList{arg_rd, arg_fs1}}, 1240 // FNMADD.D fd, fs1, fs2, fs3 1241 {mask: 0x0600007f, value: 0x0200004f, op: FNMADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1242 // FNMADD.H fd, fs1, fs2, fs3 1243 {mask: 0x0600007f, value: 0x0400004f, op: FNMADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1244 // FNMADD.Q fd, fs1, fs2, fs3 1245 {mask: 0x0600007f, value: 0x0600004f, op: FNMADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1246 // FNMADD.S fd, fs1, fs2, fs3 1247 {mask: 0x0600007f, value: 0x0000004f, op: FNMADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1248 // FNMSUB.D fd, fs1, fs2, fs3 1249 {mask: 0x0600007f, value: 0x0200004b, op: FNMSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1250 // FNMSUB.H fd, fs1, fs2, fs3 1251 {mask: 0x0600007f, value: 0x0400004b, op: FNMSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1252 // FNMSUB.Q fd, fs1, fs2, fs3 1253 {mask: 0x0600007f, value: 0x0600004b, op: FNMSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1254 // FNMSUB.S fd, fs1, fs2, fs3 1255 {mask: 0x0600007f, value: 0x0000004b, op: FNMSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, 1256 // FSD fs2, rs1_store 1257 {mask: 0x0000707f, value: 0x00003027, op: FSD, args: argTypeList{arg_fs2, arg_rs1_store}}, 1258 // FSGNJN.D fd, fs1, fs2 1259 {mask: 0xfe00707f, value: 0x22001053, op: FSGNJN_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1260 // FSGNJN.H fd, fs1, fs2 1261 {mask: 0xfe00707f, value: 0x24001053, op: FSGNJN_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1262 // FSGNJN.Q fd, fs1, fs2 1263 {mask: 0xfe00707f, value: 0x26001053, op: FSGNJN_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1264 // FSGNJN.S fd, fs1, fs2 1265 {mask: 0xfe00707f, value: 0x20001053, op: FSGNJN_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1266 // FSGNJX.D fd, fs1, fs2 1267 {mask: 0xfe00707f, value: 0x22002053, op: FSGNJX_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1268 // FSGNJX.H fd, fs1, fs2 1269 {mask: 0xfe00707f, value: 0x24002053, op: FSGNJX_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1270 // FSGNJX.Q fd, fs1, fs2 1271 {mask: 0xfe00707f, value: 0x26002053, op: FSGNJX_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1272 // FSGNJX.S fd, fs1, fs2 1273 {mask: 0xfe00707f, value: 0x20002053, op: FSGNJX_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1274 // FSGNJ.D fd, fs1, fs2 1275 {mask: 0xfe00707f, value: 0x22000053, op: FSGNJ_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1276 // FSGNJ.H fd, fs1, fs2 1277 {mask: 0xfe00707f, value: 0x24000053, op: FSGNJ_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1278 // FSGNJ.Q fd, fs1, fs2 1279 {mask: 0xfe00707f, value: 0x26000053, op: FSGNJ_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1280 // FSGNJ.S fd, fs1, fs2 1281 {mask: 0xfe00707f, value: 0x20000053, op: FSGNJ_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1282 // FSH fs2, rs1_store 1283 {mask: 0x0000707f, value: 0x00001027, op: FSH, args: argTypeList{arg_fs2, arg_rs1_store}}, 1284 // FSQ fs2, rs1_store 1285 {mask: 0x0000707f, value: 0x00004027, op: FSQ, args: argTypeList{arg_fs2, arg_rs1_store}}, 1286 // FSQRT.D fd, fs1 1287 {mask: 0xfff0007f, value: 0x5a000053, op: FSQRT_D, args: argTypeList{arg_fd, arg_fs1}}, 1288 // FSQRT.H fd, fs1 1289 {mask: 0xfff0007f, value: 0x5c000053, op: FSQRT_H, args: argTypeList{arg_fd, arg_fs1}}, 1290 // FSQRT.Q fd, fs1 1291 {mask: 0xfff0007f, value: 0x5e000053, op: FSQRT_Q, args: argTypeList{arg_fd, arg_fs1}}, 1292 // FSQRT.S fd, fs1 1293 {mask: 0xfff0007f, value: 0x58000053, op: FSQRT_S, args: argTypeList{arg_fd, arg_fs1}}, 1294 // FSUB.D fd, fs1, fs2 1295 {mask: 0xfe00007f, value: 0x0a000053, op: FSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1296 // FSUB.H fd, fs1, fs2 1297 {mask: 0xfe00007f, value: 0x0c000053, op: FSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1298 // FSUB.Q fd, fs1, fs2 1299 {mask: 0xfe00007f, value: 0x0e000053, op: FSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1300 // FSUB.S fd, fs1, fs2 1301 {mask: 0xfe00007f, value: 0x08000053, op: FSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, 1302 // FSW fs2, rs1_store 1303 {mask: 0x0000707f, value: 0x00002027, op: FSW, args: argTypeList{arg_fs2, arg_rs1_store}}, 1304 // JAL rd, jimm20 1305 {mask: 0x0000007f, value: 0x0000006f, op: JAL, args: argTypeList{arg_rd, arg_jimm20}}, 1306 // JALR rd, rs1_mem 1307 {mask: 0x0000707f, value: 0x00000067, op: JALR, args: argTypeList{arg_rd, arg_rs1_mem}}, 1308 // LB rd, rs1_mem 1309 {mask: 0x0000707f, value: 0x00000003, op: LB, args: argTypeList{arg_rd, arg_rs1_mem}}, 1310 // LBU rd, rs1_mem 1311 {mask: 0x0000707f, value: 0x00004003, op: LBU, args: argTypeList{arg_rd, arg_rs1_mem}}, 1312 // LD rd, rs1_mem 1313 {mask: 0x0000707f, value: 0x00003003, op: LD, args: argTypeList{arg_rd, arg_rs1_mem}}, 1314 // LH rd, rs1_mem 1315 {mask: 0x0000707f, value: 0x00001003, op: LH, args: argTypeList{arg_rd, arg_rs1_mem}}, 1316 // LHU rd, rs1_mem 1317 {mask: 0x0000707f, value: 0x00005003, op: LHU, args: argTypeList{arg_rd, arg_rs1_mem}}, 1318 // LR.D rd, rs1_amo 1319 {mask: 0xfff0707f, value: 0x1000302f, op: LR_D, args: argTypeList{arg_rd, arg_rs1_amo}}, 1320 // LR.D.AQ rd, rs1_amo 1321 {mask: 0xfff0707f, value: 0x1400302f, op: LR_D_AQ, args: argTypeList{arg_rd, arg_rs1_amo}}, 1322 // LR.D.AQRL rd, rs1_amo 1323 {mask: 0xfff0707f, value: 0x1600302f, op: LR_D_AQRL, args: argTypeList{arg_rd, arg_rs1_amo}}, 1324 // LR.D.RL rd, rs1_amo 1325 {mask: 0xfff0707f, value: 0x1200302f, op: LR_D_RL, args: argTypeList{arg_rd, arg_rs1_amo}}, 1326 // LR.W rd, rs1_amo 1327 {mask: 0xfff0707f, value: 0x1000202f, op: LR_W, args: argTypeList{arg_rd, arg_rs1_amo}}, 1328 // LR.W.AQ rd, rs1_amo 1329 {mask: 0xfff0707f, value: 0x1400202f, op: LR_W_AQ, args: argTypeList{arg_rd, arg_rs1_amo}}, 1330 // LR.W.AQRL rd, rs1_amo 1331 {mask: 0xfff0707f, value: 0x1600202f, op: LR_W_AQRL, args: argTypeList{arg_rd, arg_rs1_amo}}, 1332 // LR.W.RL rd, rs1_amo 1333 {mask: 0xfff0707f, value: 0x1200202f, op: LR_W_RL, args: argTypeList{arg_rd, arg_rs1_amo}}, 1334 // LUI rd, imm20 1335 {mask: 0x0000007f, value: 0x00000037, op: LUI, args: argTypeList{arg_rd, arg_imm20}}, 1336 // LW rd, rs1_mem 1337 {mask: 0x0000707f, value: 0x00002003, op: LW, args: argTypeList{arg_rd, arg_rs1_mem}}, 1338 // LWU rd, rs1_mem 1339 {mask: 0x0000707f, value: 0x00006003, op: LWU, args: argTypeList{arg_rd, arg_rs1_mem}}, 1340 // MAX rd, rs1, rs2 1341 {mask: 0xfe00707f, value: 0x0a006033, op: MAX, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1342 // MAXU rd, rs1, rs2 1343 {mask: 0xfe00707f, value: 0x0a007033, op: MAXU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1344 // MIN rd, rs1, rs2 1345 {mask: 0xfe00707f, value: 0x0a004033, op: MIN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1346 // MINU rd, rs1, rs2 1347 {mask: 0xfe00707f, value: 0x0a005033, op: MINU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1348 // MUL rd, rs1, rs2 1349 {mask: 0xfe00707f, value: 0x02000033, op: MUL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1350 // MULH rd, rs1, rs2 1351 {mask: 0xfe00707f, value: 0x02001033, op: MULH, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1352 // MULHSU rd, rs1, rs2 1353 {mask: 0xfe00707f, value: 0x02002033, op: MULHSU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1354 // MULHU rd, rs1, rs2 1355 {mask: 0xfe00707f, value: 0x02003033, op: MULHU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1356 // MULW rd, rs1, rs2 1357 {mask: 0xfe00707f, value: 0x0200003b, op: MULW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1358 // OR rd, rs1, rs2 1359 {mask: 0xfe00707f, value: 0x00006033, op: OR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1360 // ORC.B rd, rs1 1361 {mask: 0xfff0707f, value: 0x28705013, op: ORC_B, args: argTypeList{arg_rd, arg_rs1}}, 1362 // ORI rd, rs1, imm12 1363 {mask: 0x0000707f, value: 0x00006013, op: ORI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, 1364 // ORN rd, rs1, rs2 1365 {mask: 0xfe00707f, value: 0x40006033, op: ORN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1366 // REM rd, rs1, rs2 1367 {mask: 0xfe00707f, value: 0x02006033, op: REM, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1368 // REMU rd, rs1, rs2 1369 {mask: 0xfe00707f, value: 0x02007033, op: REMU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1370 // REMUW rd, rs1, rs2 1371 {mask: 0xfe00707f, value: 0x0200703b, op: REMUW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1372 // REMW rd, rs1, rs2 1373 {mask: 0xfe00707f, value: 0x0200603b, op: REMW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1374 // REV8 rd, rs1 1375 {mask: 0xfff0707f, value: 0x6b805013, op: REV8, args: argTypeList{arg_rd, arg_rs1}}, 1376 // ROL rd, rs1, rs2 1377 {mask: 0xfe00707f, value: 0x60001033, op: ROL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1378 // ROLW rd, rs1, rs2 1379 {mask: 0xfe00707f, value: 0x6000103b, op: ROLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1380 // ROR rd, rs1, rs2 1381 {mask: 0xfe00707f, value: 0x60005033, op: ROR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1382 // RORI rd, rs1, shamt6 1383 {mask: 0xfc00707f, value: 0x60005013, op: RORI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, 1384 // RORIW rd, rs1, shamt5 1385 {mask: 0xfe00707f, value: 0x6000501b, op: RORIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}}, 1386 // RORW rd, rs1, rs2 1387 {mask: 0xfe00707f, value: 0x6000503b, op: RORW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1388 // SB rs2, rs1_store 1389 {mask: 0x0000707f, value: 0x00000023, op: SB, args: argTypeList{arg_rs2, arg_rs1_store}}, 1390 // SC.D rd, rs2, rs1_amo 1391 {mask: 0xfe00707f, value: 0x1800302f, op: SC_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 1392 // SC.D.AQ rd, rs2, rs1_amo 1393 {mask: 0xfe00707f, value: 0x1c00302f, op: SC_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 1394 // SC.D.AQRL rd, rs2, rs1_amo 1395 {mask: 0xfe00707f, value: 0x1e00302f, op: SC_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 1396 // SC.D.RL rd, rs2, rs1_amo 1397 {mask: 0xfe00707f, value: 0x1a00302f, op: SC_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 1398 // SC.W rd, rs2, rs1_amo 1399 {mask: 0xfe00707f, value: 0x1800202f, op: SC_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 1400 // SC.W.AQ rd, rs2, rs1_amo 1401 {mask: 0xfe00707f, value: 0x1c00202f, op: SC_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 1402 // SC.W.AQRL rd, rs2, rs1_amo 1403 {mask: 0xfe00707f, value: 0x1e00202f, op: SC_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 1404 // SC.W.RL rd, rs2, rs1_amo 1405 {mask: 0xfe00707f, value: 0x1a00202f, op: SC_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, 1406 // SD rs2, rs1_store 1407 {mask: 0x0000707f, value: 0x00003023, op: SD, args: argTypeList{arg_rs2, arg_rs1_store}}, 1408 // SEXT.B rd, rs1 1409 {mask: 0xfff0707f, value: 0x60401013, op: SEXT_B, args: argTypeList{arg_rd, arg_rs1}}, 1410 // SEXT.H rd, rs1 1411 {mask: 0xfff0707f, value: 0x60501013, op: SEXT_H, args: argTypeList{arg_rd, arg_rs1}}, 1412 // SH rs2, rs1_store 1413 {mask: 0x0000707f, value: 0x00001023, op: SH, args: argTypeList{arg_rs2, arg_rs1_store}}, 1414 // SH1ADD rd, rs1, rs2 1415 {mask: 0xfe00707f, value: 0x20002033, op: SH1ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1416 // SH1ADD.UW rd, rs1, rs2 1417 {mask: 0xfe00707f, value: 0x2000203b, op: SH1ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1418 // SH2ADD rd, rs1, rs2 1419 {mask: 0xfe00707f, value: 0x20004033, op: SH2ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1420 // SH2ADD.UW rd, rs1, rs2 1421 {mask: 0xfe00707f, value: 0x2000403b, op: SH2ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1422 // SH3ADD rd, rs1, rs2 1423 {mask: 0xfe00707f, value: 0x20006033, op: SH3ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1424 // SH3ADD.UW rd, rs1, rs2 1425 {mask: 0xfe00707f, value: 0x2000603b, op: SH3ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1426 // SLL rd, rs1, rs2 1427 {mask: 0xfe00707f, value: 0x00001033, op: SLL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1428 // SLLI rd, rs1, shamt6 1429 {mask: 0xfc00707f, value: 0x00001013, op: SLLI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, 1430 // SLLIW rd, rs1, shamt5 1431 {mask: 0xfe00707f, value: 0x0000101b, op: SLLIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}}, 1432 // SLLI.UW rd, rs1, shamt6 1433 {mask: 0xfc00707f, value: 0x0800101b, op: SLLI_UW, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, 1434 // SLLW rd, rs1, rs2 1435 {mask: 0xfe00707f, value: 0x0000103b, op: SLLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1436 // SLT rd, rs1, rs2 1437 {mask: 0xfe00707f, value: 0x00002033, op: SLT, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1438 // SLTI rd, rs1, imm12 1439 {mask: 0x0000707f, value: 0x00002013, op: SLTI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, 1440 // SLTIU rd, rs1, imm12 1441 {mask: 0x0000707f, value: 0x00003013, op: SLTIU, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, 1442 // SLTU rd, rs1, rs2 1443 {mask: 0xfe00707f, value: 0x00003033, op: SLTU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1444 // SRA rd, rs1, rs2 1445 {mask: 0xfe00707f, value: 0x40005033, op: SRA, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1446 // SRAI rd, rs1, shamt6 1447 {mask: 0xfc00707f, value: 0x40005013, op: SRAI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, 1448 // SRAIW rd, rs1, shamt5 1449 {mask: 0xfe00707f, value: 0x4000501b, op: SRAIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}}, 1450 // SRAW rd, rs1, rs2 1451 {mask: 0xfe00707f, value: 0x4000503b, op: SRAW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1452 // SRL rd, rs1, rs2 1453 {mask: 0xfe00707f, value: 0x00005033, op: SRL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1454 // SRLI rd, rs1, shamt6 1455 {mask: 0xfc00707f, value: 0x00005013, op: SRLI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, 1456 // SRLIW rd, rs1, shamt5 1457 {mask: 0xfe00707f, value: 0x0000501b, op: SRLIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}}, 1458 // SRLW rd, rs1, rs2 1459 {mask: 0xfe00707f, value: 0x0000503b, op: SRLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1460 // SUB rd, rs1, rs2 1461 {mask: 0xfe00707f, value: 0x40000033, op: SUB, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1462 // SUBW rd, rs1, rs2 1463 {mask: 0xfe00707f, value: 0x4000003b, op: SUBW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1464 // SW rs2, rs1_store 1465 {mask: 0x0000707f, value: 0x00002023, op: SW, args: argTypeList{arg_rs2, arg_rs1_store}}, 1466 // XNOR rd, rs1, rs2 1467 {mask: 0xfe00707f, value: 0x40004033, op: XNOR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1468 // XOR rd, rs1, rs2 1469 {mask: 0xfe00707f, value: 0x00004033, op: XOR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, 1470 // XORI rd, rs1, imm12 1471 {mask: 0x0000707f, value: 0x00004013, op: XORI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, 1472 // ZEXT.H rd, rs1 1473 {mask: 0xfff0707f, value: 0x0800403b, op: ZEXT_H, args: argTypeList{arg_rd, arg_rs1}}, 1474 }