golang.org/x/arch@v0.17.0/x86/x86avxgen/testdata/xedpath/all-dec-instructions.txt (about) 1 AVX_INSTRUCTIONS():: 2 3 { 4 ICLASS: VFMADDSUBPS 5 CPL: 3 6 CATEGORY: FMA4 7 ISA_SET: FMA4 8 EXTENSION: FMA4 9 ATTRIBUTES: MXCSR AMDONLY 10 11 PATTERN: VV1 0x5C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 12 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 13 14 PATTERN: VV1 0x5C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 15 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 16 17 PATTERN: VV1 0x5C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 18 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 19 20 PATTERN: VV1 0x5C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 21 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 22 23 PATTERN: VV1 0x5C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 24 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 25 26 PATTERN: VV1 0x5C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 27 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 28 29 PATTERN: VV1 0x5C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 30 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 31 32 PATTERN: VV1 0x5C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 33 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 34 } 35 36 { 37 ICLASS: VFMADDSUBPD 38 CPL: 3 39 CATEGORY: FMA4 40 ISA_SET: FMA4 41 EXTENSION: FMA4 42 ATTRIBUTES: MXCSR AMDONLY 43 44 PATTERN: VV1 0x5D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 45 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 46 47 PATTERN: VV1 0x5D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 48 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 49 50 PATTERN: VV1 0x5D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 51 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 52 53 PATTERN: VV1 0x5D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 54 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 55 56 PATTERN: VV1 0x5D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 57 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 58 59 PATTERN: VV1 0x5D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 60 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 61 62 PATTERN: VV1 0x5D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 63 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 64 65 PATTERN: VV1 0x5D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 66 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 67 } 68 69 { 70 ICLASS: VFMSUBADDPS 71 CPL: 3 72 CATEGORY: FMA4 73 ISA_SET: FMA4 74 EXTENSION: FMA4 75 ATTRIBUTES: MXCSR AMDONLY 76 77 PATTERN: VV1 0x5E V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 78 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 79 80 PATTERN: VV1 0x5E V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 81 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 82 83 PATTERN: VV1 0x5E V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 84 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 85 86 PATTERN: VV1 0x5E V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 87 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 88 89 PATTERN: VV1 0x5E V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 90 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 91 92 PATTERN: VV1 0x5E V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 93 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 94 95 PATTERN: VV1 0x5E V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 96 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 97 98 PATTERN: VV1 0x5E V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 99 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 100 } 101 102 { 103 ICLASS: VFMSUBADDPD 104 CPL: 3 105 CATEGORY: FMA4 106 ISA_SET: FMA4 107 EXTENSION: FMA4 108 ATTRIBUTES: MXCSR AMDONLY 109 110 PATTERN: VV1 0x5F V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 111 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 112 113 PATTERN: VV1 0x5F V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 114 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 115 116 PATTERN: VV1 0x5F V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 117 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 118 119 PATTERN: VV1 0x5F V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 120 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 121 122 PATTERN: VV1 0x5F V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 123 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 124 125 PATTERN: VV1 0x5F V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 126 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 127 128 PATTERN: VV1 0x5F V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 129 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 130 131 PATTERN: VV1 0x5F V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 132 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 133 } 134 135 { 136 ICLASS: VFMADDPS 137 CPL: 3 138 CATEGORY: FMA4 139 ISA_SET: FMA4 140 EXTENSION: FMA4 141 ATTRIBUTES: MXCSR AMDONLY 142 143 PATTERN: VV1 0x68 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 144 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 145 146 PATTERN: VV1 0x68 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 147 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 148 149 PATTERN: VV1 0x68 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 150 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 151 152 PATTERN: VV1 0x68 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 153 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 154 155 PATTERN: VV1 0x68 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 156 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 157 158 PATTERN: VV1 0x68 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 159 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 160 161 PATTERN: VV1 0x68 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 162 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 163 164 PATTERN: VV1 0x68 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 165 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 166 } 167 168 { 169 ICLASS: VFMADDPD 170 CPL: 3 171 CATEGORY: FMA4 172 ISA_SET: FMA4 173 EXTENSION: FMA4 174 ATTRIBUTES: MXCSR AMDONLY 175 176 PATTERN: VV1 0x69 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 177 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 178 179 PATTERN: VV1 0x69 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 180 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 181 182 PATTERN: VV1 0x69 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 183 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 184 185 PATTERN: VV1 0x69 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 186 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 187 188 PATTERN: VV1 0x69 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 189 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 190 191 PATTERN: VV1 0x69 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 192 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 193 194 PATTERN: VV1 0x69 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 195 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 196 197 PATTERN: VV1 0x69 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 198 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 199 } 200 201 { 202 ICLASS: VFMADDSS 203 CPL: 3 204 CATEGORY: FMA4 205 ISA_SET: FMA4 206 EXTENSION: FMA4 207 ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY 208 209 PATTERN: VV1 0x6A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 210 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 211 212 PATTERN: VV1 0x6A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 213 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 214 215 PATTERN: VV1 0x6A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 216 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 217 218 PATTERN: VV1 0x6A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 219 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 220 } 221 222 { 223 ICLASS: VFMADDSD 224 CPL: 3 225 CATEGORY: FMA4 226 ISA_SET: FMA4 227 EXTENSION: FMA4 228 ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY 229 230 PATTERN: VV1 0x6B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 231 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 232 233 PATTERN: VV1 0x6B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 234 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 235 236 PATTERN: VV1 0x6B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 237 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 238 239 PATTERN: VV1 0x6B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 240 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 241 } 242 243 { 244 ICLASS: VFMSUBPS 245 CPL: 3 246 CATEGORY: FMA4 247 ISA_SET: FMA4 248 EXTENSION: FMA4 249 ATTRIBUTES: MXCSR AMDONLY 250 251 PATTERN: VV1 0x6C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 252 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 253 254 PATTERN: VV1 0x6C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 255 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 256 257 PATTERN: VV1 0x6C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 258 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 259 260 PATTERN: VV1 0x6C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 261 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 262 263 PATTERN: VV1 0x6C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 264 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 265 266 PATTERN: VV1 0x6C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 267 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 268 269 PATTERN: VV1 0x6C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 270 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 271 272 PATTERN: VV1 0x6C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 273 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 274 } 275 276 { 277 ICLASS: VFMSUBPD 278 CPL: 3 279 CATEGORY: FMA4 280 ISA_SET: FMA4 281 EXTENSION: FMA4 282 ATTRIBUTES: MXCSR AMDONLY 283 284 PATTERN: VV1 0x6D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 285 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 286 287 PATTERN: VV1 0x6D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 288 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 289 290 PATTERN: VV1 0x6D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 291 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 292 293 PATTERN: VV1 0x6D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 294 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 295 296 PATTERN: VV1 0x6D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 297 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 298 299 PATTERN: VV1 0x6D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 300 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 301 302 PATTERN: VV1 0x6D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 303 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 304 305 PATTERN: VV1 0x6D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 306 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 307 } 308 309 { 310 ICLASS: VFMSUBSS 311 CPL: 3 312 CATEGORY: FMA4 313 ISA_SET: FMA4 314 EXTENSION: FMA4 315 ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY 316 317 PATTERN: VV1 0x6E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 318 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 319 320 PATTERN: VV1 0x6E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 321 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 322 323 PATTERN: VV1 0x6E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 324 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 325 326 PATTERN: VV1 0x6E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 327 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 328 } 329 330 { 331 ICLASS: VFMSUBSD 332 CPL: 3 333 CATEGORY: FMA4 334 ISA_SET: FMA4 335 EXTENSION: FMA4 336 ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY 337 338 PATTERN: VV1 0x6F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 339 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 340 341 PATTERN: VV1 0x6F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 342 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 343 344 PATTERN: VV1 0x6F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 345 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 346 347 PATTERN: VV1 0x6F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 348 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 349 } 350 351 { 352 ICLASS: VFNMADDPS 353 CPL: 3 354 CATEGORY: FMA4 355 ISA_SET: FMA4 356 EXTENSION: FMA4 357 ATTRIBUTES: MXCSR AMDONLY 358 359 PATTERN: VV1 0x78 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 360 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 361 362 PATTERN: VV1 0x78 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 363 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 364 365 PATTERN: VV1 0x78 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 366 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 367 368 PATTERN: VV1 0x78 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 369 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 370 371 PATTERN: VV1 0x78 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 372 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 373 374 PATTERN: VV1 0x78 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 375 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 376 377 PATTERN: VV1 0x78 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 378 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 379 380 PATTERN: VV1 0x78 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 381 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 382 } 383 384 { 385 ICLASS: VFNMADDPD 386 CPL: 3 387 CATEGORY: FMA4 388 ISA_SET: FMA4 389 EXTENSION: FMA4 390 ATTRIBUTES: MXCSR AMDONLY 391 392 PATTERN: VV1 0x79 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 393 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 394 395 PATTERN: VV1 0x79 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 396 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 397 398 PATTERN: VV1 0x79 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 399 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 400 401 PATTERN: VV1 0x79 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 402 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 403 404 PATTERN: VV1 0x79 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 405 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 406 407 PATTERN: VV1 0x79 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 408 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 409 410 PATTERN: VV1 0x79 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 411 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 412 413 PATTERN: VV1 0x79 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 414 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 415 } 416 417 { 418 ICLASS: VFNMADDSS 419 CPL: 3 420 CATEGORY: FMA4 421 ISA_SET: FMA4 422 EXTENSION: FMA4 423 ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY 424 425 PATTERN: VV1 0x7A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 426 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 427 428 PATTERN: VV1 0x7A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 429 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 430 431 PATTERN: VV1 0x7A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 432 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 433 434 PATTERN: VV1 0x7A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 435 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 436 } 437 438 { 439 ICLASS: VFNMADDSD 440 CPL: 3 441 CATEGORY: FMA4 442 ISA_SET: FMA4 443 EXTENSION: FMA4 444 ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY 445 446 PATTERN: VV1 0x7B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 447 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 448 449 PATTERN: VV1 0x7B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 450 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 451 452 PATTERN: VV1 0x7B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 453 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 454 455 PATTERN: VV1 0x7B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 456 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 457 } 458 459 { 460 ICLASS: VFNMSUBPS 461 CPL: 3 462 CATEGORY: FMA4 463 ISA_SET: FMA4 464 EXTENSION: FMA4 465 ATTRIBUTES: MXCSR AMDONLY 466 467 PATTERN: VV1 0x7C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 468 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 469 470 PATTERN: VV1 0x7C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 471 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 472 473 PATTERN: VV1 0x7C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 474 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 475 476 PATTERN: VV1 0x7C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 477 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 478 479 PATTERN: VV1 0x7C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 480 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 481 482 PATTERN: VV1 0x7C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 483 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 484 485 PATTERN: VV1 0x7C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 486 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 487 488 PATTERN: VV1 0x7C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 489 OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 490 } 491 492 { 493 ICLASS: VFNMSUBPD 494 CPL: 3 495 CATEGORY: FMA4 496 ISA_SET: FMA4 497 EXTENSION: FMA4 498 ATTRIBUTES: MXCSR AMDONLY 499 500 PATTERN: VV1 0x7D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 501 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 502 503 PATTERN: VV1 0x7D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 504 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 505 506 PATTERN: VV1 0x7D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 507 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 508 509 PATTERN: VV1 0x7D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 510 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 511 512 PATTERN: VV1 0x7D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 513 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 514 515 PATTERN: VV1 0x7D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 516 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 517 518 PATTERN: VV1 0x7D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 519 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 520 521 PATTERN: VV1 0x7D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 522 OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 523 } 524 525 { 526 ICLASS: VFNMSUBSS 527 CPL: 3 528 CATEGORY: FMA4 529 ISA_SET: FMA4 530 EXTENSION: FMA4 531 ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY 532 533 PATTERN: VV1 0x7E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 534 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 REG2=XMM_SE():r:dq:f32 535 536 PATTERN: VV1 0x7E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 537 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:dq:f32 538 539 PATTERN: VV1 0x7E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 540 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:d:f32 541 542 PATTERN: VV1 0x7E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 543 OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:d:f32 544 } 545 546 { 547 ICLASS: VFNMSUBSD 548 CPL: 3 549 CATEGORY: FMA4 550 ISA_SET: FMA4 551 EXTENSION: FMA4 552 ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY 553 554 PATTERN: VV1 0x7F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 555 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 REG2=XMM_SE():r:dq:f64 556 557 PATTERN: VV1 0x7F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 558 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:dq:f64 559 560 PATTERN: VV1 0x7F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 561 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:q:f64 562 563 PATTERN: VV1 0x7F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 564 OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:q:f64 565 } 566 567 568 ###FILE: ./datafiles/amdxop/amd-vpermil2-isa.txt 569 570 #BEGIN_LEGAL 571 # 572 #Copyright (c) 2016 Intel Corporation 573 # 574 # Licensed under the Apache License, Version 2.0 (the "License"); 575 # you may not use this file except in compliance with the License. 576 # You may obtain a copy of the License at 577 # 578 # http://www.apache.org/licenses/LICENSE-2.0 579 # 580 # Unless required by applicable law or agreed to in writing, software 581 # distributed under the License is distributed on an "AS IS" BASIS, 582 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 583 # See the License for the specific language governing permissions and 584 # limitations under the License. 585 # 586 #END_LEGAL 587 588 AVX_INSTRUCTIONS():: 589 590 591 { 592 ICLASS : VPERMIL2PS 593 CPL : 3 594 CATEGORY : XOP 595 EXTENSION : XOP 596 ISA_SET : XOP 597 ATTRIBUTES : AMDONLY 598 599 # 128b W0 600 PATTERN : VV1 0x48 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 601 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 IMM0:r:b 602 603 PATTERN : VV1 0x48 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 604 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 IMM0:r:b 605 606 # 256b W0 607 PATTERN : VV1 0x48 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 608 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 IMM0:r:b 609 610 PATTERN : VV1 0x48 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 611 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 IMM0:r:b 612 613 # 128b W1 614 PATTERN : VV1 0x48 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 615 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b 616 617 PATTERN : VV1 0x48 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 618 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 IMM0:r:b 619 620 # 256b W1 621 PATTERN : VV1 0x48 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 622 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b 623 624 PATTERN : VV1 0x48 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 625 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 IMM0:r:b 626 627 } 628 629 630 631 { 632 ICLASS : VPERMIL2PD 633 CPL : 3 634 CATEGORY : XOP 635 EXTENSION : XOP 636 ISA_SET : XOP 637 ATTRIBUTES : AMDONLY 638 639 # 128b W0 640 PATTERN : VV1 0x49 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 641 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 IMM0:r:b 642 643 PATTERN : VV1 0x49 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 644 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 IMM0:r:b 645 646 # 256b W0 647 PATTERN : VV1 0x49 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 648 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 IMM0:r:b 649 650 PATTERN : VV1 0x49 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 651 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 IMM0:r:b 652 653 # 128b W1 654 PATTERN : VV1 0x49 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 655 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b 656 657 PATTERN : VV1 0x49 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 658 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 IMM0:r:b 659 660 # 256b W1 661 PATTERN : VV1 0x49 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 662 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b 663 664 PATTERN : VV1 0x49 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 665 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 IMM0:r:b 666 667 } 668 669 670 671 ###FILE: ./datafiles/xsaveopt/xsaveopt-isa.txt 672 673 #BEGIN_LEGAL 674 # 675 #Copyright (c) 2016 Intel Corporation 676 # 677 # Licensed under the Apache License, Version 2.0 (the "License"); 678 # you may not use this file except in compliance with the License. 679 # You may obtain a copy of the License at 680 # 681 # http://www.apache.org/licenses/LICENSE-2.0 682 # 683 # Unless required by applicable law or agreed to in writing, software 684 # distributed under the License is distributed on an "AS IS" BASIS, 685 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 686 # See the License for the specific language governing permissions and 687 # limitations under the License. 688 # 689 #END_LEGAL 690 INSTRUCTIONS():: 691 692 { 693 ICLASS : XSAVEOPT 694 CPL : 3 695 CATEGORY : XSAVEOPT 696 EXTENSION : XSAVEOPT 697 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX 698 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM() 699 #FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR 700 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 701 } 702 703 704 { 705 ICLASS : XSAVEOPT64 706 CPL : 3 707 CATEGORY : XSAVEOPT 708 EXTENSION : XSAVEOPT 709 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX 710 711 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM() 712 #FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR 713 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 714 } 715 716 717 718 ###FILE: ./datafiles/mpx/mpx-isa.txt 719 720 #BEGIN_LEGAL 721 # 722 #Copyright (c) 2016 Intel Corporation 723 # 724 # Licensed under the Apache License, Version 2.0 (the "License"); 725 # you may not use this file except in compliance with the License. 726 # You may obtain a copy of the License at 727 # 728 # http://www.apache.org/licenses/LICENSE-2.0 729 # 730 # Unless required by applicable law or agreed to in writing, software 731 # distributed under the License is distributed on an "AS IS" BASIS, 732 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 733 # See the License for the specific language governing permissions and 734 # limitations under the License. 735 # 736 #END_LEGAL 737 738 739 INSTRUCTIONS():: 740 741 742 UDELETE: NOP0F1A 743 UDELETE: NOP0F1B 744 745 746 747 { 748 ICLASS: BNDMK 749 EXTENSION: MPX 750 CATEGORY: MPX 751 ISA_SET: MPX 752 ATTRIBUTES: NO_RIP_REL 753 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix 754 OPERANDS: REG0=BND_R():w AGEN:r 755 } 756 757 758 759 760 { 761 ICLASS: BNDCL 762 EXTENSION: MPX 763 CATEGORY: MPX 764 ISA_SET: MPX 765 ATTRIBUTES: EXCEPTION_BR 766 COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. 767 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix 768 OPERANDS: REG0=BND_R():r AGEN:r 769 770 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64 771 OPERANDS: REG0=BND_R():r REG1=GPR64_B():r 772 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64 773 OPERANDS: REG0=BND_R():r REG1=GPR32_B():r 774 } 775 776 { 777 ICLASS: BNDCU 778 EXTENSION: MPX 779 CATEGORY: MPX 780 ISA_SET: MPX 781 ATTRIBUTES: EXCEPTION_BR 782 COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. 783 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix 784 OPERANDS: REG0=BND_R():r AGEN:r 785 786 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 787 OPERANDS: REG0=BND_R():r REG1=GPR64_B():r 788 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 789 OPERANDS: REG0=BND_R():r REG1=GPR32_B():r 790 } 791 792 { 793 ICLASS: BNDCN 794 EXTENSION: MPX 795 CATEGORY: MPX 796 ISA_SET: MPX 797 ATTRIBUTES: EXCEPTION_BR 798 COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. 799 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix 800 OPERANDS: REG0=BND_R():r AGEN:r 801 802 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 803 OPERANDS: REG0=BND_R():r REG1=GPR64_B():r 804 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 805 OPERANDS: REG0=BND_R():r REG1=GPR32_B():r 806 807 } 808 809 { 810 ICLASS: BNDMOV 811 EXTENSION: MPX 812 CATEGORY: MPX 813 ISA_SET: MPX 814 ATTRIBUTES: 815 COMMENT: load form 816 817 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() 818 OPERANDS: REG0=BND_R():w REG1=BND_B():r 819 820 # 16b refs 64b memop (2x32b) but only if EASZ=32b! 821 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 822 OPERANDS: REG0=BND_R():w MEM0:r:q:u32 823 824 # 32b refs 64b memop (2x32b) 825 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32 826 OPERANDS: REG0=BND_R():w MEM0:r:q:u32 827 828 # 64b refs 128b memop (2x64b) 829 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 830 OPERANDS: REG0=BND_R():w MEM0:r:dq:u64 831 832 833 834 } 835 836 { 837 ICLASS: BNDMOV 838 EXTENSION: MPX 839 CATEGORY: MPX 840 ISA_SET: MPX 841 ATTRIBUTES: 842 COMMENT: store form 843 844 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() 845 OPERANDS: REG0=BND_B():w REG1=BND_R():r 846 847 # 16b refs 64b memop (2x32b) but only if EASZ=32b! 848 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 849 OPERANDS: MEM0:w:q:u32 REG0=BND_R():r 850 851 # 32b refs 64b memop (2x32b) 852 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 853 OPERANDS: MEM0:w:q:u32 REG0=BND_R():r 854 855 # 64b refs 128b memop (2x64b) 856 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 857 OPERANDS: MEM0:w:dq:u64 REG0=BND_R():r 858 } 859 860 861 { 862 ICLASS: BNDLDX 863 EXTENSION: MPX 864 CATEGORY: MPX 865 ISA_SET: MPX 866 ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL 867 COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only 868 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 869 OPERANDS: REG0=BND_R():w MEM0:r:bnd32 870 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 871 OPERANDS: REG0=BND_R():w MEM0:r:bnd64 872 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 873 OPERANDS: REG0=BND_R():w MEM0:r:bnd64 874 PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 875 OPERANDS: REG0=BND_R():w MEM0:r:bnd64 876 } 877 878 { 879 ICLASS: BNDSTX 880 EXTENSION: MPX 881 CATEGORY: MPX 882 ISA_SET: MPX 883 ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL 884 COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only 885 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 886 OPERANDS: MEM0:w:bnd32 REG0=BND_R():r 887 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 888 OPERANDS: MEM0:w:bnd64 REG0=BND_R():r 889 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 890 OPERANDS: MEM0:w:bnd64 REG0=BND_R():r 891 PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 892 OPERANDS: MEM0:w:bnd64 REG0=BND_R():r 893 } 894 895 { 896 ICLASS : NOP 897 CPL : 3 898 CATEGORY : WIDENOP 899 ATTRIBUTES: NOP 900 EXTENSION : BASE 901 ISA_SET : PPRO 902 COMMENT : MPXMODE=1: some of the reg/reg forms of these NOPs are still NOPs. 903 904 PATTERN : 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 905 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 906 IFORM : NOP_GPRv_GPRv_0F1A 907 908 PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 909 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 910 IFORM : NOP_GPRv_GPRv_0F1B 911 912 PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix 913 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 914 IFORM : NOP_GPRv_GPRv_0F1B 915 } 916 917 918 { 919 ICLASS : NOP 920 CPL : 3 921 CATEGORY : WIDENOP 922 ATTRIBUTES: NOP 923 EXTENSION : BASE 924 ISA_SET : PPRO 925 COMMENT : For MPXMODE=0 operation 926 927 PATTERN : 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 928 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 929 IFORM : NOP_GPRv_GPRv_0F1A 930 931 PATTERN : 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 932 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 933 IFORM : NOP_GPRv_GPRv_0F1B 934 935 PATTERN : 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 936 OPERANDS : REG0=GPRv_B():r MEM0:r:v 937 IFORM : NOP_GPRv_MEMv_0F1A 938 939 PATTERN : 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 940 OPERANDS : REG0=GPRv_B():r MEM0:r:v 941 IFORM : NOP_GPRv_MEM_0F1B 942 } 943 944 945 946 947 ###FILE: ./datafiles/cet/cet-nop-remove.xed.txt 948 949 #BEGIN_LEGAL 950 # 951 #Copyright (c) 2017 Intel Corporation 952 # 953 # Licensed under the Apache License, Version 2.0 (the "License"); 954 # you may not use this file except in compliance with the License. 955 # You may obtain a copy of the License at 956 # 957 # http://www.apache.org/licenses/LICENSE-2.0 958 # 959 # Unless required by applicable law or agreed to in writing, software 960 # distributed under the License is distributed on an "AS IS" BASIS, 961 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 962 # See the License for the specific language governing permissions and 963 # limitations under the License. 964 # 965 #END_LEGAL 966 967 968 INSTRUCTIONS():: 969 970 UDELETE: NOP0F1E 971 972 { 973 ICLASS : NOP 974 #UNAME : NOP0F1E 975 CPL : 3 976 CATEGORY : WIDENOP 977 EXTENSION : BASE 978 ATTRIBUTES: NOP 979 ISA_SET : PPRO 980 COMMENT : reg form MODRM.MOD=3 & MODRM.REG=0b001 f3 prefix is RDSSP{D,Q} 981 982 # mem forms 983 984 PATTERN : 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 985 OPERANDS : MEM0:r:v REG0=GPRv_R():r 986 IFORM : NOP_MEMv_GPRv_0F1E 987 988 989 # reg forms 990 991 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 992 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 993 IFORM : NOP_GPRv_GPRv_0F1E 994 995 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix 996 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 997 IFORM : NOP_GPRv_GPRv_0F1E 998 999 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix 1000 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1001 IFORM : NOP_GPRv_GPRv_0F1E 1002 1003 1004 1005 1006 1007 1008 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix 1009 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1010 IFORM : NOP_GPRv_GPRv_0F1E 1011 1012 # ... 1013 # F3 with MODRM.REG=0b001 is for CET for all values of RM. 1014 # ... 1015 1016 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix 1017 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1018 IFORM : NOP_GPRv_GPRv_0F1E 1019 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix 1020 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1021 IFORM : NOP_GPRv_GPRv_0F1E 1022 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix 1023 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1024 IFORM : NOP_GPRv_GPRv_0F1E 1025 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix 1026 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1027 IFORM : NOP_GPRv_GPRv_0F1E 1028 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix 1029 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1030 IFORM : NOP_GPRv_GPRv_0F1E 1031 1032 1033 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix 1034 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1035 IFORM : NOP_GPRv_GPRv_0F1E 1036 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix 1037 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1038 IFORM : NOP_GPRv_GPRv_0F1E 1039 1040 # ... 1041 # F3 with MODRM.REG=0b111 with RM=2 or RM=3 is for CET 1042 # ... 1043 1044 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix 1045 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1046 IFORM : NOP_GPRv_GPRv_0F1E 1047 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix 1048 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1049 IFORM : NOP_GPRv_GPRv_0F1E 1050 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix 1051 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1052 IFORM : NOP_GPRv_GPRv_0F1E 1053 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix 1054 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1055 IFORM : NOP_GPRv_GPRv_0F1E 1056 1057 1058 } 1059 1060 1061 # REPLACE CERTAIN NOPS WITH MODAL OPTIONS basd on CET=0/1 1062 { 1063 ICLASS : NOP 1064 #UNAME : NOP0F1E 1065 CPL : 3 1066 CATEGORY : WIDENOP 1067 EXTENSION : BASE 1068 ATTRIBUTES: NOP 1069 ISA_SET : PPRO 1070 1071 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0 1072 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1073 IFORM : NOP_GPRv_GPRv_0F1E 1074 1075 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0 1076 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1077 IFORM : NOP_GPRv_GPRv_0F1E 1078 } 1079 1080 1081 { 1082 ICLASS : NOP 1083 #UNAME : NOP0F1E 1084 CPL : 3 1085 CATEGORY : WIDENOP 1086 EXTENSION : BASE 1087 ATTRIBUTES: NOP 1088 ISA_SET : PPRO 1089 1090 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0 1091 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1092 IFORM : NOP_GPRv_GPRv_0F1E 1093 1094 PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0 1095 OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r 1096 IFORM : NOP_GPRv_GPRv_0F1E 1097 } 1098 1099 1100 ###FILE: ./datafiles/cet/cet-isa.xed.txt 1101 1102 #BEGIN_LEGAL 1103 # 1104 #Copyright (c) 2017 Intel Corporation 1105 # 1106 # Licensed under the Apache License, Version 2.0 (the "License"); 1107 # you may not use this file except in compliance with the License. 1108 # You may obtain a copy of the License at 1109 # 1110 # http://www.apache.org/licenses/LICENSE-2.0 1111 # 1112 # Unless required by applicable law or agreed to in writing, software 1113 # distributed under the License is distributed on an "AS IS" BASIS, 1114 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 1115 # See the License for the specific language governing permissions and 1116 # limitations under the License. 1117 # 1118 #END_LEGAL 1119 # 1120 # 1121 # 1122 # ***** GENERATED FILE -- DO NOT EDIT! ***** 1123 # ***** GENERATED FILE -- DO NOT EDIT! ***** 1124 # ***** GENERATED FILE -- DO NOT EDIT! ***** 1125 # 1126 # 1127 # 1128 INSTRUCTIONS():: 1129 # EMITTING CLRSSBSY (CLRSSBSY-N/A-1) 1130 { 1131 ICLASS: CLRSSBSY 1132 CPL: 3 1133 CATEGORY: CET 1134 EXTENSION: CET 1135 ISA_SET: CET 1136 REAL_OPCODE: Y 1137 PATTERN: 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM() 1138 OPERANDS: MEM0:w:q:u64 1139 IFORM: CLRSSBSY_MEMu64 1140 } 1141 1142 1143 # EMITTING ENDBR32 (ENDBR32-N/A-1) 1144 { 1145 ICLASS: ENDBR32 1146 CPL: 3 1147 CATEGORY: CET 1148 EXTENSION: CET 1149 ISA_SET: CET 1150 REAL_OPCODE: Y 1151 PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1 1152 OPERANDS: 1153 IFORM: ENDBR32 1154 } 1155 1156 1157 # EMITTING ENDBR64 (ENDBR64-N/A-1) 1158 { 1159 ICLASS: ENDBR64 1160 CPL: 3 1161 CATEGORY: CET 1162 EXTENSION: CET 1163 ISA_SET: CET 1164 REAL_OPCODE: Y 1165 PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1 1166 OPERANDS: 1167 IFORM: ENDBR64 1168 } 1169 1170 1171 # EMITTING INCSSPD (INCSSPD-N/A-1) 1172 { 1173 ICLASS: INCSSPD 1174 CPL: 3 1175 CATEGORY: CET 1176 EXTENSION: CET 1177 ISA_SET: CET 1178 REAL_OPCODE: Y 1179 PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W0 1180 OPERANDS: REG0=GPR32_B():r:d:u8 REG1=XED_REG_SSP:rw:SUPP:u64 1181 IFORM: INCSSPD_GPR32u8 1182 } 1183 1184 1185 # EMITTING INCSSPQ (INCSSPQ-N/A-1) 1186 { 1187 ICLASS: INCSSPQ 1188 CPL: 3 1189 CATEGORY: CET 1190 EXTENSION: CET 1191 ISA_SET: CET 1192 REAL_OPCODE: Y 1193 PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W1 mode64 1194 OPERANDS: REG0=GPR64_B():r:q:u8 REG1=XED_REG_SSP:rw:SUPP:u64 1195 IFORM: INCSSPQ_GPR64u8 1196 } 1197 1198 1199 # EMITTING RDSSPD (RDSSPD-N/A-1) 1200 { 1201 ICLASS: RDSSPD 1202 CPL: 3 1203 CATEGORY: CET 1204 EXTENSION: CET 1205 ISA_SET: CET 1206 REAL_OPCODE: Y 1207 PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1 1208 OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XED_REG_SSP:r:SUPP:u64 1209 IFORM: RDSSPD_GPR32u32 1210 } 1211 1212 1213 # EMITTING RDSSPQ (RDSSPQ-N/A-1) 1214 { 1215 ICLASS: RDSSPQ 1216 CPL: 3 1217 CATEGORY: CET 1218 EXTENSION: CET 1219 ISA_SET: CET 1220 REAL_OPCODE: Y 1221 PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1 1222 OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XED_REG_SSP:r:SUPP:u64 1223 IFORM: RDSSPQ_GPR64u64 1224 } 1225 1226 1227 # EMITTING RSTORSSP (RSTORSSP-N/A-1) 1228 { 1229 ICLASS: RSTORSSP 1230 CPL: 3 1231 CATEGORY: CET 1232 EXTENSION: CET 1233 ISA_SET: CET 1234 REAL_OPCODE: Y 1235 PATTERN: 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix 1236 OPERANDS: MEM0:rw:q:u64 REG0=XED_REG_SSP:w:SUPP:u64 1237 IFORM: RSTORSSP_MEMu64 1238 } 1239 1240 1241 # EMITTING SAVESSP (SAVESSP-N/A-1) 1242 { 1243 ICLASS: SAVESSP 1244 CPL: 3 1245 CATEGORY: CET 1246 EXTENSION: CET 1247 ISA_SET: CET 1248 REAL_OPCODE: Y 1249 PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix 1250 OPERANDS: REG0=XED_REG_SSP:r:SUPP:u64 1251 IFORM: SAVESSP 1252 } 1253 1254 1255 # EMITTING SETSSBSY (SETSSBSY-N/A-1) 1256 { 1257 ICLASS: SETSSBSY 1258 CPL: 3 1259 CATEGORY: CET 1260 EXTENSION: CET 1261 ISA_SET: CET 1262 REAL_OPCODE: Y 1263 PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix 1264 OPERANDS: 1265 IFORM: SETSSBSY 1266 } 1267 1268 1269 # EMITTING WRSSD (WRSSD-N/A-1) 1270 { 1271 ICLASS: WRSSD 1272 CPL: 3 1273 CATEGORY: CET 1274 EXTENSION: CET 1275 ISA_SET: CET 1276 REAL_OPCODE: Y 1277 PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W0 1278 OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32 1279 IFORM: WRSSD_MEMu32_GPR32u32 1280 } 1281 1282 1283 # EMITTING WRSSQ (WRSSQ-N/A-1) 1284 { 1285 ICLASS: WRSSQ 1286 CPL: 3 1287 CATEGORY: CET 1288 EXTENSION: CET 1289 ISA_SET: CET 1290 REAL_OPCODE: Y 1291 PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W1 mode64 1292 OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64 1293 IFORM: WRSSQ_MEMu64_GPR64u64 1294 } 1295 1296 1297 # EMITTING WRUSSD (WRUSSD-N/A-1) 1298 { 1299 ICLASS: WRUSSD 1300 CPL: 3 1301 CATEGORY: CET 1302 EXTENSION: CET 1303 ISA_SET: CET 1304 REAL_OPCODE: Y 1305 PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 1306 OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32 1307 IFORM: WRUSSD_MEMu32_GPR32u32 1308 } 1309 1310 1311 # EMITTING WRUSSQ (WRUSSQ-N/A-1) 1312 { 1313 ICLASS: WRUSSQ 1314 CPL: 3 1315 CATEGORY: CET 1316 EXTENSION: CET 1317 ISA_SET: CET 1318 REAL_OPCODE: Y 1319 PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 mode64 1320 OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64 1321 IFORM: WRUSSQ_MEMu64_GPR64u64 1322 } 1323 1324 1325 1326 1327 ###FILE: ./datafiles/sha/sha-isa.xed.txt 1328 1329 #BEGIN_LEGAL 1330 # 1331 #Copyright (c) 2016 Intel Corporation 1332 # 1333 # Licensed under the Apache License, Version 2.0 (the "License"); 1334 # you may not use this file except in compliance with the License. 1335 # You may obtain a copy of the License at 1336 # 1337 # http://www.apache.org/licenses/LICENSE-2.0 1338 # 1339 # Unless required by applicable law or agreed to in writing, software 1340 # distributed under the License is distributed on an "AS IS" BASIS, 1341 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 1342 # See the License for the specific language governing permissions and 1343 # limitations under the License. 1344 # 1345 #END_LEGAL 1346 # 1347 # 1348 # 1349 # ***** GENERATED FILE -- DO NOT EDIT! ***** 1350 # ***** GENERATED FILE -- DO NOT EDIT! ***** 1351 # ***** GENERATED FILE -- DO NOT EDIT! ***** 1352 # 1353 # 1354 # 1355 INSTRUCTIONS():: 1356 # EMITTING SHA1MSG1 (SHA1MSG1-N/A-1) 1357 { 1358 ICLASS: SHA1MSG1 1359 CPL: 3 1360 CATEGORY: SHA 1361 EXTENSION: SHA 1362 ISA_SET: SHA 1363 EXCEPTIONS: SSE_TYPE_4 1364 REAL_OPCODE: Y 1365 PATTERN: 0x0F 0x38 0xC9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 1366 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 1367 IFORM: SHA1MSG1_XMMi32_XMMi32_SHA 1368 } 1369 1370 { 1371 ICLASS: SHA1MSG1 1372 CPL: 3 1373 CATEGORY: SHA 1374 EXTENSION: SHA 1375 ISA_SET: SHA 1376 EXCEPTIONS: SSE_TYPE_4 1377 REAL_OPCODE: Y 1378 ATTRIBUTES: REQUIRES_ALIGNMENT 1379 PATTERN: 0x0F 0x38 0xC9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix 1380 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 1381 IFORM: SHA1MSG1_XMMi32_MEMi32_SHA 1382 } 1383 1384 1385 # EMITTING SHA1MSG2 (SHA1MSG2-N/A-1) 1386 { 1387 ICLASS: SHA1MSG2 1388 CPL: 3 1389 CATEGORY: SHA 1390 EXTENSION: SHA 1391 ISA_SET: SHA 1392 EXCEPTIONS: SSE_TYPE_4 1393 REAL_OPCODE: Y 1394 PATTERN: 0x0F 0x38 0xCA MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 1395 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 1396 IFORM: SHA1MSG2_XMMi32_XMMi32_SHA 1397 } 1398 1399 { 1400 ICLASS: SHA1MSG2 1401 CPL: 3 1402 CATEGORY: SHA 1403 EXTENSION: SHA 1404 ISA_SET: SHA 1405 EXCEPTIONS: SSE_TYPE_4 1406 REAL_OPCODE: Y 1407 ATTRIBUTES: REQUIRES_ALIGNMENT 1408 PATTERN: 0x0F 0x38 0xCA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix 1409 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 1410 IFORM: SHA1MSG2_XMMi32_MEMi32_SHA 1411 } 1412 1413 1414 # EMITTING SHA1NEXTE (SHA1NEXTE-N/A-1) 1415 { 1416 ICLASS: SHA1NEXTE 1417 CPL: 3 1418 CATEGORY: SHA 1419 EXTENSION: SHA 1420 ISA_SET: SHA 1421 EXCEPTIONS: SSE_TYPE_4 1422 REAL_OPCODE: Y 1423 PATTERN: 0x0F 0x38 0xC8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 1424 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 1425 IFORM: SHA1NEXTE_XMMi32_XMMi32_SHA 1426 } 1427 1428 { 1429 ICLASS: SHA1NEXTE 1430 CPL: 3 1431 CATEGORY: SHA 1432 EXTENSION: SHA 1433 ISA_SET: SHA 1434 EXCEPTIONS: SSE_TYPE_4 1435 REAL_OPCODE: Y 1436 ATTRIBUTES: REQUIRES_ALIGNMENT 1437 PATTERN: 0x0F 0x38 0xC8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix 1438 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 1439 IFORM: SHA1NEXTE_XMMi32_MEMi32_SHA 1440 } 1441 1442 1443 # EMITTING SHA1RNDS4 (SHA1RNDS4-N/A-1) 1444 { 1445 ICLASS: SHA1RNDS4 1446 CPL: 3 1447 CATEGORY: SHA 1448 EXTENSION: SHA 1449 ISA_SET: SHA 1450 EXCEPTIONS: SSE_TYPE_4 1451 REAL_OPCODE: Y 1452 PATTERN: 0x0F 0x3A 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix UIMM8() 1453 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 IMM0:r:b 1454 IFORM: SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA 1455 } 1456 1457 { 1458 ICLASS: SHA1RNDS4 1459 CPL: 3 1460 CATEGORY: SHA 1461 EXTENSION: SHA 1462 ISA_SET: SHA 1463 EXCEPTIONS: SSE_TYPE_4 1464 REAL_OPCODE: Y 1465 ATTRIBUTES: REQUIRES_ALIGNMENT 1466 PATTERN: 0x0F 0x3A 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix UIMM8() 1467 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 IMM0:r:b 1468 IFORM: SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA 1469 } 1470 1471 1472 # EMITTING SHA256MSG1 (SHA256MSG1-N/A-1) 1473 { 1474 ICLASS: SHA256MSG1 1475 CPL: 3 1476 CATEGORY: SHA 1477 EXTENSION: SHA 1478 ISA_SET: SHA 1479 EXCEPTIONS: SSE_TYPE_4 1480 REAL_OPCODE: Y 1481 PATTERN: 0x0F 0x38 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 1482 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 1483 IFORM: SHA256MSG1_XMMi32_XMMi32_SHA 1484 } 1485 1486 { 1487 ICLASS: SHA256MSG1 1488 CPL: 3 1489 CATEGORY: SHA 1490 EXTENSION: SHA 1491 ISA_SET: SHA 1492 EXCEPTIONS: SSE_TYPE_4 1493 REAL_OPCODE: Y 1494 ATTRIBUTES: REQUIRES_ALIGNMENT 1495 PATTERN: 0x0F 0x38 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix 1496 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 1497 IFORM: SHA256MSG1_XMMi32_MEMi32_SHA 1498 } 1499 1500 1501 # EMITTING SHA256MSG2 (SHA256MSG2-N/A-1) 1502 { 1503 ICLASS: SHA256MSG2 1504 CPL: 3 1505 CATEGORY: SHA 1506 EXTENSION: SHA 1507 ISA_SET: SHA 1508 EXCEPTIONS: SSE_TYPE_4 1509 REAL_OPCODE: Y 1510 PATTERN: 0x0F 0x38 0xCD MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 1511 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 1512 IFORM: SHA256MSG2_XMMi32_XMMi32_SHA 1513 } 1514 1515 { 1516 ICLASS: SHA256MSG2 1517 CPL: 3 1518 CATEGORY: SHA 1519 EXTENSION: SHA 1520 ISA_SET: SHA 1521 EXCEPTIONS: SSE_TYPE_4 1522 REAL_OPCODE: Y 1523 ATTRIBUTES: REQUIRES_ALIGNMENT 1524 PATTERN: 0x0F 0x38 0xCD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix 1525 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 1526 IFORM: SHA256MSG2_XMMi32_MEMi32_SHA 1527 } 1528 1529 1530 # EMITTING SHA256RNDS2 (SHA256RNDS2-N/A-1) 1531 { 1532 ICLASS: SHA256RNDS2 1533 CPL: 3 1534 CATEGORY: SHA 1535 EXTENSION: SHA 1536 ISA_SET: SHA 1537 EXCEPTIONS: SSE_TYPE_4 1538 REAL_OPCODE: Y 1539 PATTERN: 0x0F 0x38 0xCB MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix 1540 OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 REG2=XED_REG_XMM0:r:SUPP:dq:u8 1541 IFORM: SHA256RNDS2_XMMi32_XMMi32_SHA 1542 } 1543 1544 { 1545 ICLASS: SHA256RNDS2 1546 CPL: 3 1547 CATEGORY: SHA 1548 EXTENSION: SHA 1549 ISA_SET: SHA 1550 EXCEPTIONS: SSE_TYPE_4 1551 REAL_OPCODE: Y 1552 ATTRIBUTES: REQUIRES_ALIGNMENT 1553 PATTERN: 0x0F 0x38 0xCB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix 1554 OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 REG1=XED_REG_XMM0:r:SUPP:dq:u8 1555 IFORM: SHA256RNDS2_XMMi32_MEMi32_SHA 1556 } 1557 1558 1559 1560 1561 ###FILE: ./datafiles/ivbint/ivb-int-isa.txt 1562 1563 #BEGIN_LEGAL 1564 # 1565 #Copyright (c) 2016 Intel Corporation 1566 # 1567 # Licensed under the Apache License, Version 2.0 (the "License"); 1568 # you may not use this file except in compliance with the License. 1569 # You may obtain a copy of the License at 1570 # 1571 # http://www.apache.org/licenses/LICENSE-2.0 1572 # 1573 # Unless required by applicable law or agreed to in writing, software 1574 # distributed under the License is distributed on an "AS IS" BASIS, 1575 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 1576 # See the License for the specific language governing permissions and 1577 # limitations under the License. 1578 # 1579 #END_LEGAL 1580 INSTRUCTIONS():: 1581 1582 { 1583 ICLASS : RDRAND 1584 CPL : 3 1585 CATEGORY : RDRAND 1586 EXTENSION : RDRAND 1587 ISA_SET : RDRAND 1588 FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] 1589 PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining 1590 OPERANDS : REG0=GPRv_B():w 1591 } 1592 1593 1594 1595 ###FILE: ./datafiles/ivbint/fsgsbase-isa.txt 1596 1597 #BEGIN_LEGAL 1598 # 1599 #Copyright (c) 2016 Intel Corporation 1600 # 1601 # Licensed under the Apache License, Version 2.0 (the "License"); 1602 # you may not use this file except in compliance with the License. 1603 # You may obtain a copy of the License at 1604 # 1605 # http://www.apache.org/licenses/LICENSE-2.0 1606 # 1607 # Unless required by applicable law or agreed to in writing, software 1608 # distributed under the License is distributed on an "AS IS" BASIS, 1609 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 1610 # See the License for the specific language governing permissions and 1611 # limitations under the License. 1612 # 1613 #END_LEGAL 1614 INSTRUCTIONS():: 1615 1616 1617 { 1618 ICLASS : RDFSBASE 1619 CPL : 3 1620 CATEGORY : RDWRFSGS 1621 EXTENSION : RDWRFSGS 1622 1623 PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix 1624 OPERANDS : REG0=GPRy_B():w REG1=XED_REG_FSBASE:r:SUPP:y 1625 1626 } 1627 { 1628 ICLASS : RDGSBASE 1629 CPL : 3 1630 CATEGORY : RDWRFSGS 1631 EXTENSION : RDWRFSGS 1632 1633 PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix 1634 OPERANDS : REG0=GPRy_B():w REG1=XED_REG_GSBASE:r:SUPP:y 1635 1636 } 1637 1638 1639 1640 { 1641 ICLASS : WRFSBASE 1642 CPL : 3 1643 CATEGORY : RDWRFSGS 1644 EXTENSION : RDWRFSGS 1645 ATTRIBUTES: NOTSX 1646 1647 PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix 1648 OPERANDS : REG0=GPRy_B():r REG1=XED_REG_FSBASE:w:SUPP:y 1649 1650 } 1651 { 1652 ICLASS : WRGSBASE 1653 CPL : 3 1654 CATEGORY : RDWRFSGS 1655 EXTENSION : RDWRFSGS 1656 ATTRIBUTES: NOTSX 1657 1658 PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix 1659 OPERANDS : REG0=GPRy_B():r REG1=XED_REG_GSBASE:w:SUPP:y 1660 1661 } 1662 1663 1664 ###FILE: ./datafiles/xsaves/xsaves-isa.txt 1665 1666 #BEGIN_LEGAL 1667 # 1668 #Copyright (c) 2016 Intel Corporation 1669 # 1670 # Licensed under the Apache License, Version 2.0 (the "License"); 1671 # you may not use this file except in compliance with the License. 1672 # You may obtain a copy of the License at 1673 # 1674 # http://www.apache.org/licenses/LICENSE-2.0 1675 # 1676 # Unless required by applicable law or agreed to in writing, software 1677 # distributed under the License is distributed on an "AS IS" BASIS, 1678 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 1679 # See the License for the specific language governing permissions and 1680 # limitations under the License. 1681 # 1682 #END_LEGAL 1683 INSTRUCTIONS():: 1684 1685 { 1686 ICLASS : XSAVES 1687 CPL : 0 1688 CATEGORY : XSAVE 1689 EXTENSION : XSAVES 1690 COMMENT : variable length load and conditianal reg write 1691 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED 1692 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix 1693 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 1694 } 1695 1696 1697 { 1698 ICLASS : XSAVES64 1699 CPL : 0 1700 CATEGORY : XSAVE 1701 EXTENSION : XSAVES 1702 COMMENT : variable length load and conditianal reg write 1703 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED 1704 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix 1705 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 1706 } 1707 1708 1709 1710 1711 1712 { 1713 ICLASS : XRSTORS 1714 CPL : 0 1715 CATEGORY : XSAVE 1716 EXTENSION : XSAVES 1717 COMMENT : variable length load and conditianal reg write 1718 ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED 1719 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix 1720 OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 1721 } 1722 1723 1724 { 1725 ICLASS : XRSTORS64 1726 CPL : 0 1727 CATEGORY : XSAVE 1728 EXTENSION : XSAVES 1729 COMMENT : variable length load and conditianal reg write 1730 ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED 1731 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix 1732 OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 1733 } 1734 1735 1736 1737 ###FILE: ./datafiles/xsavec/xsavec-isa.txt 1738 1739 #BEGIN_LEGAL 1740 # 1741 #Copyright (c) 2016 Intel Corporation 1742 # 1743 # Licensed under the Apache License, Version 2.0 (the "License"); 1744 # you may not use this file except in compliance with the License. 1745 # You may obtain a copy of the License at 1746 # 1747 # http://www.apache.org/licenses/LICENSE-2.0 1748 # 1749 # Unless required by applicable law or agreed to in writing, software 1750 # distributed under the License is distributed on an "AS IS" BASIS, 1751 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 1752 # See the License for the specific language governing permissions and 1753 # limitations under the License. 1754 # 1755 #END_LEGAL 1756 INSTRUCTIONS():: 1757 1758 { 1759 ICLASS : XSAVEC 1760 CPL : 3 1761 CATEGORY : XSAVE 1762 EXTENSION : XSAVEC 1763 COMMENT : variable length store 1764 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED 1765 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix 1766 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 1767 } 1768 1769 1770 1771 { 1772 ICLASS : XSAVEC64 1773 CPL : 3 1774 CATEGORY : XSAVE 1775 EXTENSION : XSAVEC 1776 COMMENT : variable length store 1777 ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED 1778 PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix 1779 OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP 1780 } 1781 1782 1783 1784 1785 ###FILE: ./datafiles/avx/avx-isa.txt 1786 1787 #BEGIN_LEGAL 1788 # 1789 #Copyright (c) 2016 Intel Corporation 1790 # 1791 # Licensed under the Apache License, Version 2.0 (the "License"); 1792 # you may not use this file except in compliance with the License. 1793 # You may obtain a copy of the License at 1794 # 1795 # http://www.apache.org/licenses/LICENSE-2.0 1796 # 1797 # Unless required by applicable law or agreed to in writing, software 1798 # distributed under the License is distributed on an "AS IS" BASIS, 1799 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 1800 # See the License for the specific language governing permissions and 1801 # limitations under the License. 1802 # 1803 #END_LEGAL 1804 1805 # The neat thing is we can just end a nonterminal by starting a new one. 1806 1807 AVX_INSTRUCTIONS():: 1808 { 1809 ICLASS : VADDPD 1810 EXCEPTIONS: avx-type-2 1811 CPL : 3 1812 CATEGORY : AVX 1813 EXTENSION : AVX 1814 ATTRIBUTES: MXCSR 1815 PATTERN : VV1 0x58 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1816 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 1817 1818 PATTERN : VV1 0x58 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1819 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 1820 1821 PATTERN : VV1 0x58 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1822 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 1823 1824 PATTERN : VV1 0x58 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1825 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 1826 } 1827 1828 1829 { 1830 ICLASS : VADDPS 1831 EXCEPTIONS: avx-type-2 1832 CPL : 3 1833 CATEGORY : AVX 1834 EXTENSION : AVX 1835 ATTRIBUTES: MXCSR 1836 PATTERN : VV1 0x58 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1837 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 1838 1839 PATTERN : VV1 0x58 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1840 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 1841 1842 PATTERN : VV1 0x58 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1843 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 1844 1845 PATTERN : VV1 0x58 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1846 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 1847 } 1848 1849 1850 { 1851 ICLASS : VADDSD 1852 EXCEPTIONS: avx-type-3 1853 CPL : 3 1854 ATTRIBUTES : simd_scalar MXCSR 1855 CATEGORY : AVX 1856 EXTENSION : AVX 1857 PATTERN : VV1 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1858 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 1859 1860 PATTERN : VV1 0x58 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1861 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 1862 } 1863 1864 { 1865 ICLASS : VADDSS 1866 EXCEPTIONS: avx-type-3 1867 CPL : 3 1868 ATTRIBUTES : simd_scalar MXCSR 1869 CATEGORY : AVX 1870 EXTENSION : AVX 1871 PATTERN : VV1 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1872 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 1873 1874 PATTERN : VV1 0x58 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1875 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 1876 } 1877 1878 1879 { 1880 ICLASS : VADDSUBPD 1881 EXCEPTIONS: avx-type-2 1882 CPL : 3 1883 CATEGORY : AVX 1884 EXTENSION : AVX 1885 ATTRIBUTES: MXCSR 1886 PATTERN : VV1 0xD0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1887 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 1888 1889 PATTERN : VV1 0xD0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1890 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 1891 1892 PATTERN : VV1 0xD0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1893 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 1894 1895 PATTERN : VV1 0xD0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1896 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 1897 } 1898 1899 { 1900 ICLASS : VADDSUBPS 1901 EXCEPTIONS: avx-type-2 1902 CPL : 3 1903 CATEGORY : AVX 1904 EXTENSION : AVX 1905 ATTRIBUTES: MXCSR 1906 PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1907 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 1908 1909 PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1910 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 1911 1912 PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1913 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 1914 1915 PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1916 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 1917 } 1918 1919 1920 { 1921 ICLASS : VANDPD 1922 EXCEPTIONS: avx-type-4 1923 CPL : 3 1924 CATEGORY : LOGICAL_FP 1925 EXTENSION : AVX 1926 PATTERN : VV1 0x54 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1927 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 1928 1929 PATTERN : VV1 0x54 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1930 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 1931 1932 PATTERN : VV1 0x54 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1933 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 1934 1935 PATTERN : VV1 0x54 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1936 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 1937 } 1938 1939 1940 1941 { 1942 ICLASS : VANDPS 1943 EXCEPTIONS: avx-type-4 1944 CPL : 3 1945 CATEGORY : LOGICAL_FP 1946 EXTENSION : AVX 1947 PATTERN : VV1 0x54 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1948 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 1949 1950 PATTERN : VV1 0x54 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1951 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 1952 1953 PATTERN : VV1 0x54 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1954 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 1955 1956 PATTERN : VV1 0x54 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1957 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 1958 } 1959 1960 1961 { 1962 ICLASS : VANDNPD 1963 EXCEPTIONS: avx-type-4 1964 CPL : 3 1965 CATEGORY : LOGICAL_FP 1966 EXTENSION : AVX 1967 PATTERN : VV1 0x55 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1968 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 1969 1970 PATTERN : VV1 0x55 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1971 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 1972 1973 PATTERN : VV1 0x55 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1974 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 1975 1976 PATTERN : VV1 0x55 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1977 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 1978 } 1979 1980 1981 1982 { 1983 ICLASS : VANDNPS 1984 EXCEPTIONS: avx-type-4 1985 CPL : 3 1986 CATEGORY : LOGICAL_FP 1987 EXTENSION : AVX 1988 PATTERN : VV1 0x55 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1989 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 1990 1991 PATTERN : VV1 0x55 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1992 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 1993 1994 PATTERN : VV1 0x55 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 1995 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 1996 1997 PATTERN : VV1 0x55 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 1998 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 1999 } 2000 2001 2002 2003 { 2004 ICLASS : VBLENDPD 2005 EXCEPTIONS: avx-type-4 2006 CPL : 3 2007 CATEGORY : AVX 2008 EXTENSION : AVX 2009 PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2010 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b 2011 2012 PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2013 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b 2014 2015 PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2016 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b 2017 2018 PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2019 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b 2020 } 2021 2022 2023 { 2024 ICLASS : VBLENDPS 2025 EXCEPTIONS: avx-type-4 2026 CPL : 3 2027 CATEGORY : AVX 2028 EXTENSION : AVX 2029 PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2030 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b 2031 2032 PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2033 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b 2034 2035 PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2036 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b 2037 2038 PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2039 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b 2040 } 2041 2042 2043 2044 2045 2046 2047 { 2048 ICLASS : VCMPPD 2049 EXCEPTIONS: avx-type-2 2050 CPL : 3 2051 CATEGORY : AVX 2052 EXTENSION : AVX 2053 ATTRIBUTES: MXCSR 2054 PATTERN : VV1 0xC2 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2055 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b 2056 2057 PATTERN : VV1 0xC2 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2058 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b 2059 2060 PATTERN : VV1 0xC2 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2061 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b 2062 2063 PATTERN : VV1 0xC2 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2064 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b 2065 } 2066 2067 2068 2069 { 2070 ICLASS : VCMPPS 2071 EXCEPTIONS: avx-type-2 2072 CPL : 3 2073 CATEGORY : AVX 2074 EXTENSION : AVX 2075 ATTRIBUTES: MXCSR 2076 PATTERN : VV1 0xC2 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2077 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b 2078 2079 PATTERN : VV1 0xC2 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2080 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b 2081 2082 PATTERN : VV1 0xC2 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2083 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b 2084 2085 PATTERN : VV1 0xC2 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2086 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b 2087 } 2088 2089 2090 2091 { 2092 ICLASS : VCMPSD 2093 EXCEPTIONS: avx-type-3 2094 CPL : 3 2095 CATEGORY : AVX 2096 EXTENSION : AVX 2097 ATTRIBUTES : simd_scalar MXCSR 2098 PATTERN : VV1 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2099 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 2100 2101 PATTERN : VV1 0xC2 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2102 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b 2103 } 2104 2105 2106 2107 { 2108 ICLASS : VCMPSS 2109 EXCEPTIONS: avx-type-3 2110 CPL : 3 2111 CATEGORY : AVX 2112 EXTENSION : AVX 2113 2114 ATTRIBUTES : simd_scalar MXCSR 2115 2116 PATTERN : VV1 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2117 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 2118 2119 PATTERN : VV1 0xC2 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2120 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b 2121 } 2122 2123 2124 { 2125 ICLASS : VCOMISD 2126 EXCEPTIONS: avx-type-3 2127 CPL : 3 2128 CATEGORY : AVX 2129 EXTENSION : AVX 2130 ATTRIBUTES : simd_scalar MXCSR 2131 2132 FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] 2133 PATTERN : VV1 0x2F V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2134 OPERANDS : REG0=XMM_R():r:q:f64 MEM0:r:q:f64 2135 2136 PATTERN : VV1 0x2F V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2137 OPERANDS : REG0=XMM_R():r:q:f64 REG1=XMM_B():r:q:f64 2138 } 2139 2140 { 2141 ICLASS : VCOMISS 2142 EXCEPTIONS: avx-type-3 2143 CPL : 3 2144 CATEGORY : AVX 2145 EXTENSION : AVX 2146 ATTRIBUTES : simd_scalar MXCSR 2147 2148 FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] 2149 PATTERN : VV1 0x2F VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2150 OPERANDS : REG0=XMM_R():r:d:f32 MEM0:r:d:f32 2151 2152 PATTERN : VV1 0x2F VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2153 OPERANDS : REG0=XMM_R():r:d:f32 REG1=XMM_B():r:d:f32 2154 } 2155 2156 2157 { 2158 ICLASS : VCVTDQ2PD 2159 EXCEPTIONS: avx-type-5 2160 CPL : 3 2161 CATEGORY : CONVERT 2162 EXTENSION : AVX 2163 ATTRIBUTES: MXCSR 2164 PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2165 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:i32 2166 2167 PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2168 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:i32 2169 2170 PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2171 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:i32 2172 2173 PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2174 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:i32 2175 } 2176 2177 { 2178 ICLASS : VCVTDQ2PS 2179 EXCEPTIONS: avx-type-2 2180 CPL : 3 2181 CATEGORY : CONVERT 2182 EXTENSION : AVX 2183 ATTRIBUTES: MXCSR 2184 PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2185 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:i32 2186 2187 PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2188 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:i32 2189 2190 PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2191 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:i32 2192 2193 PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2194 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:i32 2195 } 2196 2197 { 2198 ICLASS : VCVTPD2DQ 2199 EXCEPTIONS: avx-type-2 2200 CPL : 3 2201 CATEGORY : CONVERT 2202 EXTENSION : AVX 2203 ATTRIBUTES: MXCSR 2204 PATTERN : VV1 0xE6 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2205 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64 2206 2207 PATTERN : VV1 0xE6 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2208 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f64 2209 2210 PATTERN : VV1 0xE6 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2211 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:qq:f64 2212 2213 PATTERN : VV1 0xE6 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2214 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=YMM_B():r:qq:f64 2215 } 2216 2217 2218 { 2219 ICLASS : VCVTTPD2DQ 2220 EXCEPTIONS: avx-type-2 2221 CPL : 3 2222 CATEGORY : CONVERT 2223 EXTENSION : AVX 2224 ATTRIBUTES: MXCSR 2225 PATTERN : VV1 0xE6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2226 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64 2227 2228 PATTERN : VV1 0xE6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2229 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f64 2230 2231 PATTERN : VV1 0xE6 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2232 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:qq:f64 2233 2234 PATTERN : VV1 0xE6 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2235 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=YMM_B():r:qq:f64 2236 } 2237 2238 2239 { 2240 ICLASS : VCVTPD2PS 2241 EXCEPTIONS: avx-type-2 2242 CPL : 3 2243 CATEGORY : CONVERT 2244 EXTENSION : AVX 2245 ATTRIBUTES: MXCSR 2246 PATTERN : VV1 0x5A V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2247 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f64 2248 2249 PATTERN : VV1 0x5A V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2250 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f64 2251 2252 PATTERN : VV1 0x5A V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2253 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:qq:f64 2254 2255 PATTERN : VV1 0x5A V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2256 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=YMM_B():r:qq:f64 2257 } 2258 2259 { 2260 ICLASS : VCVTPS2DQ 2261 EXCEPTIONS: avx-type-2 2262 CPL : 3 2263 CATEGORY : CONVERT 2264 EXTENSION : AVX 2265 ATTRIBUTES: MXCSR 2266 PATTERN : VV1 0x5B VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2267 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f32 2268 2269 PATTERN : VV1 0x5B VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2270 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f32 2271 2272 PATTERN : VV1 0x5B VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2273 OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:qq:f32 2274 2275 PATTERN : VV1 0x5B VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2276 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_B():r:qq:f32 2277 } 2278 2279 { 2280 ICLASS : VCVTTPS2DQ 2281 EXCEPTIONS: avx-type-2 2282 CPL : 3 2283 CATEGORY : CONVERT 2284 EXTENSION : AVX 2285 ATTRIBUTES: MXCSR 2286 PATTERN : VV1 0x5B VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2287 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f32 2288 2289 PATTERN : VV1 0x5B VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2290 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f32 2291 2292 PATTERN : VV1 0x5B VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2293 OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:qq:f32 2294 2295 PATTERN : VV1 0x5B VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2296 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_B():r:qq:f32 2297 } 2298 2299 { 2300 ICLASS : VCVTPS2PD 2301 EXCEPTIONS: avx-type-3 2302 CPL : 3 2303 CATEGORY : CONVERT 2304 EXTENSION : AVX 2305 ATTRIBUTES: MXCSR 2306 PATTERN : VV1 0x5A VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2307 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f32 2308 2309 PATTERN : VV1 0x5A VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2310 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f32 2311 2312 PATTERN : VV1 0x5A VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2313 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:f32 2314 2315 PATTERN : VV1 0x5A VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2316 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f32 2317 } 2318 2319 2320 2321 2322 { 2323 ICLASS : VCVTSD2SI 2324 EXCEPTIONS: avx-type-3 2325 CPL : 3 2326 CATEGORY : CONVERT 2327 EXTENSION : AVX 2328 ATTRIBUTES : simd_scalar MXCSR 2329 COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG 2330 2331 PATTERN : VV1 0x2D VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2332 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 2333 2334 PATTERN : VV1 0x2D VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2335 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 2336 2337 2338 PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2339 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 2340 2341 PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2342 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 2343 2344 2345 2346 PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2347 OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 2348 2349 PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2350 OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64 2351 } 2352 2353 { 2354 ICLASS : VCVTTSD2SI 2355 EXCEPTIONS: avx-type-3 2356 CPL : 3 2357 CATEGORY : CONVERT 2358 EXTENSION : AVX 2359 ATTRIBUTES : simd_scalar MXCSR 2360 COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG 2361 2362 2363 PATTERN : VV1 0x2C VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2364 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 2365 2366 PATTERN : VV1 0x2C VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2367 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 2368 2369 2370 2371 PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2372 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 2373 2374 PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2375 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 2376 2377 2378 2379 PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2380 OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 2381 2382 PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2383 OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64 2384 } 2385 2386 2387 2388 2389 { 2390 ICLASS : VCVTSS2SI 2391 EXCEPTIONS: avx-type-3 2392 CPL : 3 2393 CATEGORY : CONVERT 2394 EXTENSION : AVX 2395 ATTRIBUTES : simd_scalar MXCSR 2396 COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG 2397 2398 PATTERN : VV1 0x2D VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2399 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 2400 2401 PATTERN : VV1 0x2D VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2402 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 2403 2404 2405 2406 PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2407 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 2408 2409 PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2410 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 2411 2412 2413 PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2414 OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 2415 2416 PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2417 OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32 2418 } 2419 2420 { 2421 ICLASS : VCVTTSS2SI 2422 EXCEPTIONS: avx-type-3 2423 CPL : 3 2424 CATEGORY : CONVERT 2425 EXTENSION : AVX 2426 ATTRIBUTES : simd_scalar MXCSR 2427 COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG 2428 2429 PATTERN : VV1 0x2C VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2430 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 2431 2432 PATTERN : VV1 0x2C VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2433 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 2434 2435 2436 2437 PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2438 OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 2439 2440 PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2441 OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 2442 2443 2444 2445 2446 PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2447 OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 2448 2449 PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2450 OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32 2451 } 2452 2453 2454 2455 2456 { 2457 ICLASS : VCVTSD2SS 2458 EXCEPTIONS: avx-type-3 2459 CPL : 3 2460 CATEGORY : CONVERT 2461 EXTENSION : AVX 2462 ATTRIBUTES : simd_scalar MXCSR 2463 2464 PATTERN : VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2465 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:f64 2466 2467 PATTERN : VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2468 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:q:f64 2469 2470 } 2471 2472 2473 { 2474 ICLASS : VCVTSI2SD 2475 EXCEPTIONS: avx-type-3 2476 CPL : 3 2477 CATEGORY : CONVERT 2478 EXTENSION : AVX 2479 ATTRIBUTES : simd_scalar MXCSR 2480 2481 PATTERN : VV1 0x2A VF2 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2482 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:i32 2483 2484 PATTERN : VV1 0x2A VF2 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2485 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR32_B():r:d:i32 2486 2487 2488 2489 PATTERN : VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2490 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:i32 2491 2492 PATTERN : VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2493 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR32_B():r:d:i32 2494 2495 2496 2497 PATTERN : VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2498 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:i64 2499 2500 PATTERN : VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2501 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR64_B():r:q:i64 2502 } 2503 2504 2505 { 2506 ICLASS : VCVTSI2SS 2507 EXCEPTIONS: avx-type-3 2508 CPL : 3 2509 CATEGORY : CONVERT 2510 EXTENSION : AVX 2511 ATTRIBUTES : simd_scalar MXCSR 2512 2513 PATTERN : VV1 0x2A VF3 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2514 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 2515 2516 PATTERN : VV1 0x2A VF3 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2517 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR32_B():r:d:i32 2518 2519 2520 2521 PATTERN : VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2522 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 2523 2524 PATTERN : VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2525 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR32_B():r:d:i32 2526 2527 2528 2529 PATTERN : VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2530 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:i64 2531 2532 PATTERN : VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2533 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR64_B():r:q:i64 2534 } 2535 2536 2537 { 2538 ICLASS : VCVTSS2SD 2539 EXCEPTIONS: avx-type-3 2540 CPL : 3 2541 CATEGORY : CONVERT 2542 EXTENSION : AVX 2543 ATTRIBUTES : simd_scalar MXCSR 2544 2545 PATTERN : VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2546 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:f32 2547 2548 PATTERN : VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2549 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:d:f32 2550 } 2551 2552 2553 { 2554 ICLASS : VDIVPD 2555 EXCEPTIONS: avx-type-2 2556 CPL : 3 2557 CATEGORY : AVX 2558 EXTENSION : AVX 2559 ATTRIBUTES: MXCSR 2560 PATTERN : VV1 0x5E V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2561 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 2562 2563 PATTERN : VV1 0x5E V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2564 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 2565 2566 PATTERN : VV1 0x5E V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2567 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 2568 2569 PATTERN : VV1 0x5E V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2570 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 2571 } 2572 2573 2574 { 2575 ICLASS : VDIVPS 2576 EXCEPTIONS: avx-type-2 2577 CPL : 3 2578 CATEGORY : AVX 2579 EXTENSION : AVX 2580 ATTRIBUTES: MXCSR 2581 PATTERN : VV1 0x5E VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2582 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 2583 2584 PATTERN : VV1 0x5E VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2585 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 2586 2587 PATTERN : VV1 0x5E VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2588 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 2589 2590 PATTERN : VV1 0x5E VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2591 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 2592 } 2593 2594 2595 2596 { 2597 ICLASS : VDIVSD 2598 EXCEPTIONS: avx-type-3 2599 CPL : 3 2600 CATEGORY : AVX 2601 EXTENSION : AVX 2602 ATTRIBUTES : simd_scalar MXCSR 2603 2604 PATTERN : VV1 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2605 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 2606 2607 PATTERN : VV1 0x5E VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2608 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 2609 } 2610 2611 { 2612 ICLASS : VDIVSS 2613 EXCEPTIONS: avx-type-3 2614 CPL : 3 2615 CATEGORY : AVX 2616 EXTENSION : AVX 2617 ATTRIBUTES : simd_scalar MXCSR 2618 2619 PATTERN : VV1 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2620 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 2621 2622 PATTERN : VV1 0x5E VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2623 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 2624 } 2625 2626 2627 { 2628 ICLASS : VEXTRACTF128 2629 EXCEPTIONS: avx-type-6 2630 CPL : 3 2631 CATEGORY : AVX 2632 EXTENSION : AVX 2633 PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2634 OPERANDS : MEM0:w:dq:f64 REG0=YMM_R():r:dq:f64 IMM0:r:b 2635 2636 PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2637 OPERANDS : REG0=XMM_B():w:dq:f64 REG1=YMM_R():r:dq:f64 IMM0:r:b 2638 } 2639 2640 2641 2642 { 2643 ICLASS : VDPPD 2644 EXCEPTIONS: avx-type-2D 2645 CPL : 3 2646 CATEGORY : AVX 2647 EXTENSION : AVX 2648 ATTRIBUTES: MXCSR 2649 PATTERN : VV1 0x41 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2650 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b 2651 2652 PATTERN : VV1 0x41 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2653 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b 2654 } 2655 2656 { 2657 ICLASS : VDPPS 2658 EXCEPTIONS: avx-type-2D 2659 CPL : 3 2660 CATEGORY : AVX 2661 EXTENSION : AVX 2662 ATTRIBUTES: MXCSR 2663 PATTERN : VV1 0x40 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2664 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b 2665 2666 PATTERN : VV1 0x40 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2667 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b 2668 2669 PATTERN : VV1 0x40 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2670 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b 2671 2672 PATTERN : VV1 0x40 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2673 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b 2674 } 2675 2676 2677 { 2678 ICLASS : VEXTRACTPS 2679 EXCEPTIONS: avx-type-5 2680 CPL : 3 2681 CATEGORY : AVX 2682 EXTENSION : AVX 2683 PATTERN : VV1 0x17 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2684 OPERANDS : MEM0:w:d:f32 REG0=XMM_R():r:dq:f32 IMM0:r:b 2685 2686 PATTERN : VV1 0x17 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2687 OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:dq:f32 IMM0:r:b 2688 } 2689 2690 2691 { 2692 ICLASS : VZEROALL 2693 EXCEPTIONS: avx-type-8 2694 CPL : 3 2695 CATEGORY : AVX 2696 EXTENSION : AVX 2697 ATTRIBUTES : xmm_state_w 2698 2699 PATTERN : VV1 0x77 VNP V0F VL256 NOVSR 2700 OPERANDS: 2701 2702 } 2703 2704 # FIXME: how to denote partial upper clobber! 2705 { 2706 ICLASS : VZEROUPPER 2707 EXCEPTIONS: avx-type-8 2708 CPL : 3 2709 CATEGORY : AVX 2710 EXTENSION : AVX 2711 ATTRIBUTES : xmm_state_w NOTSX # FIXME: should be ymm_state_w? 2712 2713 PATTERN : VV1 0x77 VNP V0F VL128 NOVSR 2714 OPERANDS: 2715 } 2716 2717 2718 { 2719 ICLASS : VHADDPD 2720 EXCEPTIONS: avx-type-2 2721 CPL : 3 2722 CATEGORY : AVX 2723 EXTENSION : AVX 2724 ATTRIBUTES: MXCSR 2725 PATTERN : VV1 0x7C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2726 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 2727 2728 PATTERN : VV1 0x7C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2729 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 2730 2731 PATTERN : VV1 0x7C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2732 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 2733 2734 PATTERN : VV1 0x7C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2735 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 2736 } 2737 2738 2739 { 2740 ICLASS : VHADDPS 2741 EXCEPTIONS: avx-type-2 2742 CPL : 3 2743 CATEGORY : AVX 2744 EXTENSION : AVX 2745 ATTRIBUTES: MXCSR 2746 PATTERN : VV1 0x7C VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2747 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 2748 2749 PATTERN : VV1 0x7C VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2750 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 2751 2752 PATTERN : VV1 0x7C VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2753 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 2754 2755 PATTERN : VV1 0x7C VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2756 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 2757 } 2758 2759 2760 { 2761 ICLASS : VHSUBPD 2762 EXCEPTIONS: avx-type-2 2763 CPL : 3 2764 CATEGORY : AVX 2765 EXTENSION : AVX 2766 ATTRIBUTES: MXCSR 2767 PATTERN : VV1 0x7D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2768 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 2769 2770 PATTERN : VV1 0x7D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2771 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 2772 2773 PATTERN : VV1 0x7D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2774 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 2775 2776 PATTERN : VV1 0x7D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2777 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 2778 } 2779 2780 2781 { 2782 ICLASS : VHSUBPS 2783 EXCEPTIONS: avx-type-2 2784 CPL : 3 2785 CATEGORY : AVX 2786 EXTENSION : AVX 2787 ATTRIBUTES: MXCSR 2788 PATTERN : VV1 0x7D VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2789 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 2790 2791 PATTERN : VV1 0x7D VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2792 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 2793 2794 PATTERN : VV1 0x7D VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2795 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 2796 2797 PATTERN : VV1 0x7D VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2798 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 2799 } 2800 2801 2802 2803 { 2804 ICLASS : VPERMILPD 2805 EXCEPTIONS: avx-type-6 2806 CPL : 3 2807 CATEGORY : AVX 2808 EXTENSION : AVX 2809 # 2008-02-01 moved norexw_prefix to after V0F38 to avoid graph build conflict with VBLENDPD 2810 PATTERN : VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2811 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:u64 2812 2813 PATTERN : VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2814 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:u64 2815 2816 PATTERN : VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2817 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:u64 2818 2819 PATTERN : VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2820 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:u64 2821 2822 ######################################## 2823 # IMMEDIATE FORM 2824 ######################################## 2825 2826 # 2008-02-01 moved norexw_prefix to after V0F3A to avoid a graph build conflict with VPHSUBW 2827 PATTERN : VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2828 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 IMM0:r:b 2829 2830 PATTERN : VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2831 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b 2832 2833 PATTERN : VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2834 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b 2835 2836 PATTERN : VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2837 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b 2838 } 2839 2840 2841 { 2842 ICLASS : VPERMILPS 2843 EXCEPTIONS: avx-type-6 2844 CPL : 3 2845 CATEGORY : AVX 2846 EXTENSION : AVX 2847 # moved norexw_prefix to after V0F38 to avoid graph build conflict with VBLENDPS 2848 PATTERN : VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2849 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:u32 2850 2851 PATTERN : VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2852 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:u32 2853 2854 PATTERN : VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2855 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:u32 2856 2857 PATTERN : VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] 2858 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:u32 2859 2860 ######################################## 2861 # IMMEDIATE FORM 2862 ######################################## 2863 2864 # 2008-02-01: moved norexw_prefix after V0F3A due to graph-build collision with VPMADDUBSW 2865 PATTERN : VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2866 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 IMM0:r:b 2867 2868 PATTERN : VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2869 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b 2870 2871 PATTERN : VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2872 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 IMM0:r:b 2873 2874 PATTERN : VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2875 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 IMM0:r:b 2876 } 2877 2878 2879 { 2880 ICLASS : VPERM2F128 2881 EXCEPTIONS: avx-type-6 2882 CPL : 3 2883 CATEGORY : AVX 2884 EXTENSION : AVX 2885 2886 # 2008-02-01 moved norexw_prefix to after V0F3A to avoid conflict with VPHSUBD 2887 PATTERN : VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2888 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b 2889 2890 PATTERN : VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2891 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b 2892 } 2893 2894 2895 2896 { 2897 ICLASS : VBROADCASTSS 2898 EXCEPTIONS: avx-type-6 2899 CPL : 3 2900 CATEGORY : BROADCAST 2901 EXTENSION : AVX 2902 PATTERN : VV1 0x18 norexw_prefix VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2903 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 EMX_BROADCAST_1TO4_32 2904 2905 PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2906 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:d:f32 EMX_BROADCAST_1TO8_32 2907 } 2908 { 2909 ICLASS : VBROADCASTSD 2910 EXCEPTIONS: avx-type-6 2911 CPL : 3 2912 CATEGORY : BROADCAST 2913 EXTENSION : AVX 2914 PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2915 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:q:f64 EMX_BROADCAST_1TO4_64 2916 } 2917 2918 { 2919 ICLASS : VBROADCASTF128 2920 EXCEPTIONS: avx-type-6 2921 CPL : 3 2922 CATEGORY : BROADCAST 2923 EXTENSION : AVX 2924 COMMENT : There is no F128 type. I just set these to f64 for lack of anything better. 2925 PATTERN : VV1 0x1A norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2926 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64 2927 } 2928 2929 2930 { 2931 ICLASS : VINSERTF128 2932 EXCEPTIONS: avx-type-6 2933 CPL : 3 2934 CATEGORY : AVX 2935 EXTENSION : AVX 2936 PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2937 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b EMX_BROADCAST_2TO4_64 2938 2939 PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2940 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b EMX_BROADCAST_2TO4_64 2941 } 2942 2943 { 2944 ICLASS : VINSERTPS 2945 EXCEPTIONS: avx-type-5 2946 CPL : 3 2947 CATEGORY : AVX 2948 EXTENSION : AVX 2949 PATTERN : VV1 0x21 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 2950 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 2951 2952 PATTERN : VV1 0x21 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 2953 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b 2954 } 2955 2956 2957 2958 2959 2960 { 2961 ICLASS : VLDDQU 2962 EXCEPTIONS: avx-type-4 2963 CPL : 3 2964 CATEGORY : AVX 2965 EXTENSION : AVX 2966 PATTERN : VV1 0xF0 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2967 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 2968 2969 PATTERN : VV1 0xF0 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2970 OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq 2971 } 2972 2973 2974 2975 2976 2977 2978 { 2979 ICLASS : VMASKMOVPS 2980 EXCEPTIONS: avx-type-6 2981 CPL : 3 2982 CATEGORY : AVX 2983 EXTENSION : AVX 2984 ATTRIBUTES : maskop NONTEMPORAL 2985 # load forms 2986 PATTERN : VV1 0x2C V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2987 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq MEM0:r:dq:f32 2988 2989 PATTERN : VV1 0x2C V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2990 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq MEM0:r:qq:f32 2991 2992 # store forms 2993 PATTERN : VV1 0x2E V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2994 OPERANDS : MEM0:w:dq:f32 REG0=XMM_N():r:dq REG1=XMM_R():r:dq:f32 2995 2996 PATTERN : VV1 0x2E V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 2997 OPERANDS : MEM0:w:qq:f32 REG0=YMM_N():r:qq REG1=YMM_R():r:qq:f32 2998 } 2999 3000 { 3001 ICLASS : VMASKMOVPD 3002 EXCEPTIONS: avx-type-6 3003 CPL : 3 3004 CATEGORY : AVX 3005 EXTENSION : AVX 3006 ATTRIBUTES : maskop 3007 # load forms 3008 PATTERN : VV1 0x2D V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3009 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:f64 3010 3011 PATTERN : VV1 0x2D V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3012 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:f64 3013 3014 # store forms 3015 PATTERN : VV1 0x2F V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3016 OPERANDS : MEM0:w:dq:f64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:f64 3017 3018 PATTERN : VV1 0x2F V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3019 OPERANDS : MEM0:w:qq:f64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:f64 3020 } 3021 3022 { 3023 ICLASS : VPTEST 3024 EXCEPTIONS: avx-type-4 3025 CPL : 3 3026 CATEGORY : LOGICAL 3027 EXTENSION : AVX 3028 FLAGS : MUST [ zf-mod cf-mod ] 3029 PATTERN : VV1 0x17 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3030 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq 3031 3032 PATTERN : VV1 0x17 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3033 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq 3034 3035 PATTERN : VV1 0x17 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3036 OPERANDS : REG0=YMM_R():r:qq MEM0:r:qq 3037 3038 PATTERN : VV1 0x17 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3039 OPERANDS : REG0=YMM_R():r:qq REG1=YMM_B():r:qq 3040 } 3041 3042 { 3043 ICLASS : VTESTPS 3044 EXCEPTIONS: avx-type-4 3045 CPL : 3 3046 CATEGORY : LOGICAL_FP 3047 EXTENSION : AVX 3048 FLAGS : MUST [ zf-mod cf-mod ] 3049 PATTERN : VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3050 OPERANDS : REG0=XMM_R():r:dq:f32 MEM0:r:dq:f32 3051 3052 PATTERN : VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3053 OPERANDS : REG0=XMM_R():r:dq:f32 REG1=XMM_B():r:dq:f32 3054 3055 PATTERN : VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3056 OPERANDS : REG0=YMM_R():r:qq:f32 MEM0:r:qq:f32 3057 3058 PATTERN : VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3059 OPERANDS : REG0=YMM_R():r:qq:f32 REG1=YMM_B():r:qq:f32 3060 } 3061 3062 { 3063 ICLASS : VTESTPD 3064 EXCEPTIONS: avx-type-4 3065 CPL : 3 3066 CATEGORY : LOGICAL_FP 3067 EXTENSION : AVX 3068 FLAGS : MUST [ zf-mod cf-mod ] 3069 PATTERN : VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3070 OPERANDS : REG0=XMM_R():r:dq:f64 MEM0:r:dq:f64 3071 3072 PATTERN : VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3073 OPERANDS : REG0=XMM_R():r:dq:f64 REG1=XMM_B():r:dq:f64 3074 3075 PATTERN : VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3076 OPERANDS : REG0=YMM_R():r:qq:f64 MEM0:r:qq:f64 3077 3078 PATTERN : VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3079 OPERANDS : REG0=YMM_R():r:qq:f64 REG1=YMM_B():r:qq:f64 3080 } 3081 3082 3083 { 3084 ICLASS : VMAXPD 3085 EXCEPTIONS: avx-type-2 3086 CPL : 3 3087 CATEGORY : AVX 3088 EXTENSION : AVX 3089 ATTRIBUTES: MXCSR 3090 PATTERN : VV1 0x5F V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3091 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 3092 3093 PATTERN : VV1 0x5F V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3094 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 3095 3096 PATTERN : VV1 0x5F V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3097 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 3098 3099 PATTERN : VV1 0x5F V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3100 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 3101 } 3102 3103 { 3104 ICLASS : VMAXPS 3105 EXCEPTIONS: avx-type-2 3106 CPL : 3 3107 CATEGORY : AVX 3108 EXTENSION : AVX 3109 ATTRIBUTES: MXCSR 3110 PATTERN : VV1 0x5F VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3111 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 3112 3113 PATTERN : VV1 0x5F VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3114 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 3115 3116 PATTERN : VV1 0x5F VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3117 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 3118 3119 PATTERN : VV1 0x5F VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3120 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 3121 } 3122 3123 3124 3125 { 3126 ICLASS : VMAXSD 3127 EXCEPTIONS: avx-type-3 3128 CPL : 3 3129 CATEGORY : AVX 3130 EXTENSION : AVX 3131 ATTRIBUTES : simd_scalar MXCSR 3132 3133 PATTERN : VV1 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3134 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 3135 3136 PATTERN : VV1 0x5F VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3137 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 3138 } 3139 3140 { 3141 ICLASS : VMAXSS 3142 EXCEPTIONS: avx-type-3 3143 CPL : 3 3144 CATEGORY : AVX 3145 EXTENSION : AVX 3146 ATTRIBUTES : simd_scalar MXCSR 3147 3148 PATTERN : VV1 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3149 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 3150 3151 PATTERN : VV1 0x5F VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3152 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 3153 } 3154 3155 { 3156 ICLASS : VMINPD 3157 EXCEPTIONS: avx-type-2 3158 CPL : 3 3159 CATEGORY : AVX 3160 EXTENSION : AVX 3161 ATTRIBUTES: MXCSR 3162 PATTERN : VV1 0x5D V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3163 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 3164 3165 PATTERN : VV1 0x5D V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3166 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 3167 3168 PATTERN : VV1 0x5D V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3169 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 3170 3171 PATTERN : VV1 0x5D V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3172 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 3173 } 3174 3175 { 3176 ICLASS : VMINPS 3177 EXCEPTIONS: avx-type-2 3178 CPL : 3 3179 CATEGORY : AVX 3180 EXTENSION : AVX 3181 ATTRIBUTES: MXCSR 3182 PATTERN : VV1 0x5D VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3183 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 3184 3185 PATTERN : VV1 0x5D VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3186 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 3187 3188 PATTERN : VV1 0x5D VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3189 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 3190 3191 PATTERN : VV1 0x5D VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3192 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 3193 } 3194 3195 3196 3197 { 3198 ICLASS : VMINSD 3199 EXCEPTIONS: avx-type-3 3200 CPL : 3 3201 CATEGORY : AVX 3202 EXTENSION : AVX 3203 ATTRIBUTES : simd_scalar MXCSR 3204 3205 PATTERN : VV1 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3206 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 3207 3208 PATTERN : VV1 0x5D VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3209 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 3210 } 3211 3212 { 3213 ICLASS : VMINSS 3214 EXCEPTIONS: avx-type-3 3215 CPL : 3 3216 CATEGORY : AVX 3217 EXTENSION : AVX 3218 ATTRIBUTES : simd_scalar MXCSR 3219 3220 PATTERN : VV1 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3221 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 3222 3223 PATTERN : VV1 0x5D VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3224 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 3225 } 3226 3227 3228 { 3229 ICLASS : VMOVAPD 3230 EXCEPTIONS: avx-type-1 3231 CPL : 3 3232 CATEGORY : DATAXFER 3233 EXTENSION : AVX 3234 ATTRIBUTES : REQUIRES_ALIGNMENT 3235 3236 # 128b load 3237 3238 PATTERN : VV1 0x28 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3239 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 3240 3241 PATTERN : VV1 0x28 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3242 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 3243 IFORM : VMOVAPD_XMMdq_XMMdq_28 3244 3245 # 128b store 3246 3247 PATTERN : VV1 0x29 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3248 OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 3249 3250 PATTERN : VV1 0x29 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3251 OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64 3252 IFORM : VMOVAPD_XMMdq_XMMdq_29 3253 3254 # 256b load 3255 3256 PATTERN : VV1 0x28 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3257 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 3258 3259 PATTERN : VV1 0x28 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3260 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 3261 IFORM : VMOVAPD_YMMqq_YMMqq_28 3262 3263 # 256b store 3264 3265 PATTERN : VV1 0x29 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3266 OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 3267 3268 PATTERN : VV1 0x29 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3269 OPERANDS : REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64 3270 IFORM : VMOVAPD_YMMqq_YMMqq_29 3271 } 3272 3273 3274 3275 { 3276 ICLASS : VMOVAPS 3277 EXCEPTIONS: avx-type-1 3278 CPL : 3 3279 CATEGORY : DATAXFER 3280 EXTENSION : AVX 3281 ATTRIBUTES : REQUIRES_ALIGNMENT 3282 3283 # 128b load 3284 3285 PATTERN : VV1 0x28 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3286 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 3287 3288 PATTERN : VV1 0x28 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3289 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 3290 IFORM : VMOVAPS_XMMdq_XMMdq_28 3291 # 128b store 3292 3293 PATTERN : VV1 0x29 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3294 OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 3295 3296 PATTERN : VV1 0x29 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3297 OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_R():r:dq:f32 3298 IFORM : VMOVAPS_XMMdq_XMMdq_29 3299 3300 # 256b load 3301 3302 PATTERN : VV1 0x28 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3303 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 3304 3305 PATTERN : VV1 0x28 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3306 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 3307 IFORM : VMOVAPS_YMMqq_YMMqq_28 3308 3309 # 256b store 3310 3311 PATTERN : VV1 0x29 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3312 OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 3313 3314 PATTERN : VV1 0x29 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3315 OPERANDS : REG0=YMM_B():w:qq:f32 REG1=YMM_R():r:qq:f32 3316 IFORM : VMOVAPS_YMMqq_YMMqq_29 3317 } 3318 3319 3320 3321 { 3322 ICLASS : VMOVD 3323 EXCEPTIONS: avx-type-5 3324 CPL : 3 3325 CATEGORY : DATAXFER 3326 EXTENSION : AVX 3327 3328 # 32b load 3329 PATTERN : VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3330 OPERANDS : REG0=XMM_R():w:dq MEM0:r:d 3331 3332 PATTERN : VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3333 OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r:d 3334 3335 # 32b store 3336 PATTERN : VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3337 OPERANDS : MEM0:w:d REG0=XMM_R():r:d 3338 3339 PATTERN : VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3340 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:d 3341 3342 3343 3344 # 32b load 3345 PATTERN : VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3346 OPERANDS : REG0=XMM_R():w:dq MEM0:r:d 3347 3348 PATTERN : VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3349 OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r:d 3350 3351 # 32b store 3352 PATTERN : VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3353 OPERANDS : MEM0:w:d REG0=XMM_R():r:d 3354 3355 PATTERN : VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3356 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:d 3357 3358 3359 } 3360 3361 { 3362 ICLASS : VMOVQ 3363 EXCEPTIONS: avx-type-5 3364 CPL : 3 3365 CATEGORY : DATAXFER 3366 EXTENSION : AVX 3367 3368 # 64b load 3369 PATTERN : VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3370 OPERANDS : REG0=XMM_R():w:dq MEM0:r:q 3371 IFORM : VMOVQ_XMMdq_MEMq_6E 3372 3373 PATTERN : VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3374 OPERANDS : REG0=XMM_R():w:dq REG1=GPR64_B():r:q 3375 3376 # 64b store 3377 PATTERN : VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3378 OPERANDS : MEM0:w:q REG0=XMM_R():r:q 3379 IFORM : VMOVQ_MEMq_XMMq_7E 3380 3381 PATTERN : VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3382 OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:q 3383 3384 3385 # 2nd page of MOVQ forms 3386 PATTERN : VV1 0x7E VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3387 OPERANDS : REG0=XMM_R():w:dq MEM0:r:q 3388 IFORM : VMOVQ_XMMdq_MEMq_7E 3389 3390 PATTERN : VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3391 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q 3392 IFORM : VMOVQ_XMMdq_XMMq_7E 3393 3394 PATTERN : VV1 0xD6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3395 OPERANDS : MEM0:w:q REG0=XMM_R():r:q 3396 IFORM : VMOVQ_MEMq_XMMq_D6 3397 3398 PATTERN : VV1 0xD6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3399 OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:q 3400 IFORM : VMOVQ_XMMdq_XMMq_D6 3401 3402 } 3403 3404 3405 3406 3407 { 3408 ICLASS : VMOVDDUP 3409 EXCEPTIONS: avx-type-5 3410 CPL : 3 3411 CATEGORY : DATAXFER 3412 EXTENSION : AVX 3413 3414 PATTERN : VV1 0x12 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3415 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 3416 3417 PATTERN : VV1 0x12 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3418 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 3419 3420 3421 PATTERN : VV1 0x12 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3422 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 3423 3424 PATTERN : VV1 0x12 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3425 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 3426 } 3427 3428 3429 3430 { 3431 ICLASS : VMOVDQA 3432 EXCEPTIONS: avx-type-1 3433 CPL : 3 3434 CATEGORY : DATAXFER 3435 EXTENSION : AVX 3436 ATTRIBUTES : REQUIRES_ALIGNMENT 3437 3438 # LOAD XMM 3439 3440 PATTERN : VV1 0x6F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3441 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 3442 3443 PATTERN : VV1 0x6F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3444 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq 3445 IFORM : VMOVDQA_XMMdq_XMMdq_6F 3446 3447 # STORE XMM 3448 3449 PATTERN : VV1 0x7F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3450 OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq 3451 3452 PATTERN : VV1 0x7F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3453 OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq 3454 IFORM : VMOVDQA_XMMdq_XMMdq_7F 3455 3456 # LOAD YMM 3457 3458 PATTERN : VV1 0x6F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3459 OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq 3460 3461 PATTERN : VV1 0x6F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3462 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_B():r:qq 3463 IFORM : VMOVDQA_YMMqq_YMMqq_6F 3464 3465 3466 # STORE YMM 3467 3468 PATTERN : VV1 0x7F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3469 OPERANDS : MEM0:w:qq REG0=YMM_R():r:qq 3470 3471 PATTERN : VV1 0x7F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3472 OPERANDS : REG0=YMM_B():w:qq REG1=YMM_R():r:qq 3473 IFORM : VMOVDQA_YMMqq_YMMqq_7F 3474 } 3475 3476 3477 { 3478 ICLASS : VMOVDQU 3479 EXCEPTIONS: avx-type-4M 3480 CPL : 3 3481 CATEGORY : DATAXFER 3482 EXTENSION : AVX 3483 3484 # LOAD XMM 3485 3486 PATTERN : VV1 0x6F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3487 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 3488 3489 PATTERN : VV1 0x6F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3490 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq 3491 IFORM : VMOVDQU_XMMdq_XMMdq_6F 3492 3493 # LOAD YMM 3494 3495 PATTERN : VV1 0x6F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3496 OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq 3497 3498 PATTERN : VV1 0x6F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3499 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_B():r:qq 3500 IFORM : VMOVDQU_YMMqq_YMMqq_6F 3501 3502 # STORE XMM 3503 3504 PATTERN : VV1 0x7F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3505 OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq 3506 3507 PATTERN : VV1 0x7F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3508 OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq 3509 IFORM : VMOVDQU_XMMdq_XMMdq_7F 3510 3511 # STORE YMM 3512 3513 PATTERN : VV1 0x7F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3514 OPERANDS : MEM0:w:qq REG0=YMM_R():r:qq 3515 3516 PATTERN : VV1 0x7F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3517 OPERANDS : REG0=YMM_B():w:qq REG1=YMM_R():r:qq 3518 IFORM : VMOVDQU_YMMqq_YMMqq_7F 3519 } 3520 3521 ################################################# 3522 ## skipping to the end 3523 ################################################# 3524 3525 ################################################# 3526 ## MACROS 3527 ################################################# 3528 { 3529 ICLASS : VMOVSHDUP 3530 EXCEPTIONS: avx-type-4 3531 CPL : 3 3532 CATEGORY : DATAXFER 3533 EXTENSION : AVX 3534 PATTERN : VV1 0x16 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3535 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 3536 3537 PATTERN : VV1 0x16 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3538 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 3539 3540 PATTERN : VV1 0x16 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3541 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 3542 3543 PATTERN : VV1 0x16 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3544 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 3545 } 3546 { 3547 ICLASS : VMOVSLDUP 3548 EXCEPTIONS: avx-type-4 3549 CPL : 3 3550 CATEGORY : DATAXFER 3551 EXTENSION : AVX 3552 PATTERN : VV1 0x12 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3553 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 3554 3555 PATTERN : VV1 0x12 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3556 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 3557 3558 PATTERN : VV1 0x12 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3559 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 3560 3561 PATTERN : VV1 0x12 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3562 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 3563 } 3564 3565 3566 3567 { 3568 ICLASS : VPOR 3569 EXCEPTIONS: avx-type-4 3570 CPL : 3 3571 CATEGORY : LOGICAL 3572 EXTENSION : AVX 3573 PATTERN : VV1 0xEB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3574 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 3575 3576 PATTERN : VV1 0xEB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3577 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 3578 } 3579 { 3580 ICLASS : VPAND 3581 EXCEPTIONS: avx-type-4 3582 CPL : 3 3583 CATEGORY : LOGICAL 3584 EXTENSION : AVX 3585 PATTERN : VV1 0xDB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3586 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 3587 3588 PATTERN : VV1 0xDB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3589 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 3590 } 3591 { 3592 ICLASS : VPANDN 3593 EXCEPTIONS: avx-type-4 3594 CPL : 3 3595 CATEGORY : LOGICAL 3596 EXTENSION : AVX 3597 PATTERN : VV1 0xDF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3598 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 3599 3600 PATTERN : VV1 0xDF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3601 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 3602 } 3603 { 3604 ICLASS : VPXOR 3605 EXCEPTIONS: avx-type-4 3606 CPL : 3 3607 CATEGORY : LOGICAL 3608 EXTENSION : AVX 3609 PATTERN : VV1 0xEF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3610 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 3611 3612 PATTERN : VV1 0xEF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3613 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 3614 } 3615 3616 3617 { 3618 ICLASS : VPABSB 3619 EXCEPTIONS: avx-type-4 3620 CPL : 3 3621 CATEGORY : AVX 3622 EXTENSION : AVX 3623 PATTERN : VV1 0x1C V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3624 OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:dq:i8 3625 3626 PATTERN : VV1 0x1C V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3627 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:i8 3628 } 3629 { 3630 ICLASS : VPABSW 3631 EXCEPTIONS: avx-type-4 3632 CPL : 3 3633 CATEGORY : AVX 3634 EXTENSION : AVX 3635 PATTERN : VV1 0x1D V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3636 OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:i16 3637 3638 PATTERN : VV1 0x1D V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3639 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:i16 3640 } 3641 { 3642 ICLASS : VPABSD 3643 EXCEPTIONS: avx-type-4 3644 CPL : 3 3645 CATEGORY : AVX 3646 EXTENSION : AVX 3647 PATTERN : VV1 0x1E V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3648 OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:dq:i32 3649 3650 PATTERN : VV1 0x1E V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3651 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:i32 3652 } 3653 3654 { 3655 ICLASS : VPHMINPOSUW 3656 EXCEPTIONS: avx-type-4 3657 CPL : 3 3658 CATEGORY : AVX 3659 EXTENSION : AVX 3660 PATTERN : VV1 0x41 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3661 OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 3662 3663 PATTERN : VV1 0x41 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3664 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 3665 } 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 { 3677 ICLASS : VPSHUFD 3678 EXCEPTIONS: avx-type-4 3679 CPL : 3 3680 CATEGORY : AVX 3681 EXTENSION : AVX 3682 PATTERN : VV1 0x70 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 3683 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b 3684 3685 PATTERN : VV1 0x70 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 3686 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b 3687 } 3688 { 3689 ICLASS : VPSHUFHW 3690 EXCEPTIONS: avx-type-4 3691 CPL : 3 3692 CATEGORY : AVX 3693 EXTENSION : AVX 3694 PATTERN : VV1 0x70 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 3695 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b 3696 3697 PATTERN : VV1 0x70 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 3698 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b 3699 } 3700 { 3701 ICLASS : VPSHUFLW 3702 EXCEPTIONS: avx-type-4 3703 CPL : 3 3704 CATEGORY : AVX 3705 EXTENSION : AVX 3706 PATTERN : VV1 0x70 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 3707 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b 3708 3709 PATTERN : VV1 0x70 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 3710 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b 3711 } 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 { 3726 ICLASS : VPACKSSWB 3727 EXCEPTIONS: avx-type-4 3728 CPL : 3 3729 CATEGORY : AVX 3730 EXTENSION : AVX 3731 PATTERN : VV1 0x63 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3732 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 3733 3734 PATTERN : VV1 0x63 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3735 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 3736 } 3737 { 3738 ICLASS : VPACKSSDW 3739 EXCEPTIONS: avx-type-4 3740 CPL : 3 3741 CATEGORY : AVX 3742 EXTENSION : AVX 3743 PATTERN : VV1 0x6B VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3744 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 3745 3746 PATTERN : VV1 0x6B VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3747 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 3748 } 3749 { 3750 ICLASS : VPACKUSWB 3751 EXCEPTIONS: avx-type-4 3752 CPL : 3 3753 CATEGORY : AVX 3754 EXTENSION : AVX 3755 PATTERN : VV1 0x67 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3756 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 3757 3758 PATTERN : VV1 0x67 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3759 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 3760 } 3761 { 3762 ICLASS : VPACKUSDW 3763 EXCEPTIONS: avx-type-4 3764 CPL : 3 3765 CATEGORY : AVX 3766 EXTENSION : AVX 3767 PATTERN : VV1 0x2B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3768 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 3769 3770 PATTERN : VV1 0x2B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3771 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 3772 } 3773 3774 { 3775 ICLASS : VPSLLW 3776 EXCEPTIONS: avx-type-7 3777 CPL : 3 3778 CATEGORY : AVX 3779 EXTENSION : AVX 3780 PATTERN : VV1 0xF1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3781 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u64 3782 3783 PATTERN : VV1 0xF1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3784 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u64 3785 } 3786 { 3787 ICLASS : VPSLLD 3788 EXCEPTIONS: avx-type-7 3789 CPL : 3 3790 CATEGORY : AVX 3791 EXTENSION : AVX 3792 PATTERN : VV1 0xF2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3793 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u64 3794 3795 PATTERN : VV1 0xF2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3796 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u64 3797 } 3798 { 3799 ICLASS : VPSLLQ 3800 EXCEPTIONS: avx-type-7 3801 CPL : 3 3802 CATEGORY : AVX 3803 EXTENSION : AVX 3804 PATTERN : VV1 0xF3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3805 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 3806 3807 PATTERN : VV1 0xF3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3808 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 3809 } 3810 3811 { 3812 ICLASS : VPSRLW 3813 EXCEPTIONS: avx-type-7 3814 CPL : 3 3815 CATEGORY : AVX 3816 EXTENSION : AVX 3817 PATTERN : VV1 0xD1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3818 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u64 3819 3820 PATTERN : VV1 0xD1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3821 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u64 3822 } 3823 { 3824 ICLASS : VPSRLD 3825 EXCEPTIONS: avx-type-7 3826 CPL : 3 3827 CATEGORY : AVX 3828 EXTENSION : AVX 3829 PATTERN : VV1 0xD2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3830 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u64 3831 3832 PATTERN : VV1 0xD2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3833 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u64 3834 } 3835 { 3836 ICLASS : VPSRLQ 3837 EXCEPTIONS: avx-type-7 3838 CPL : 3 3839 CATEGORY : AVX 3840 EXTENSION : AVX 3841 PATTERN : VV1 0xD3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3842 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 3843 3844 PATTERN : VV1 0xD3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3845 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 3846 } 3847 3848 { 3849 ICLASS : VPSRAW 3850 EXCEPTIONS: avx-type-7 3851 CPL : 3 3852 CATEGORY : AVX 3853 EXTENSION : AVX 3854 PATTERN : VV1 0xE1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3855 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:u64 3856 3857 PATTERN : VV1 0xE1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3858 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:u64 3859 } 3860 { 3861 ICLASS : VPSRAD 3862 EXCEPTIONS: avx-type-7 3863 CPL : 3 3864 CATEGORY : AVX 3865 EXTENSION : AVX 3866 PATTERN : VV1 0xE2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3867 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:u64 3868 3869 PATTERN : VV1 0xE2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3870 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:u64 3871 } 3872 3873 { 3874 ICLASS : VPADDB 3875 EXCEPTIONS: avx-type-4 3876 CPL : 3 3877 CATEGORY : AVX 3878 EXTENSION : AVX 3879 PATTERN : VV1 0xFC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3880 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 3881 3882 PATTERN : VV1 0xFC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3883 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 3884 } 3885 { 3886 ICLASS : VPADDW 3887 EXCEPTIONS: avx-type-4 3888 CPL : 3 3889 CATEGORY : AVX 3890 EXTENSION : AVX 3891 PATTERN : VV1 0xFD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3892 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 3893 3894 PATTERN : VV1 0xFD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3895 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 3896 } 3897 { 3898 ICLASS : VPADDD 3899 EXCEPTIONS: avx-type-4 3900 CPL : 3 3901 CATEGORY : AVX 3902 EXTENSION : AVX 3903 PATTERN : VV1 0xFE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3904 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 3905 3906 PATTERN : VV1 0xFE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3907 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 3908 } 3909 { 3910 ICLASS : VPADDQ 3911 EXCEPTIONS: avx-type-4 3912 CPL : 3 3913 CATEGORY : AVX 3914 EXTENSION : AVX 3915 PATTERN : VV1 0xD4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3916 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 3917 3918 PATTERN : VV1 0xD4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3919 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 3920 } 3921 3922 { 3923 ICLASS : VPADDSB 3924 EXCEPTIONS: avx-type-4 3925 CPL : 3 3926 CATEGORY : AVX 3927 EXTENSION : AVX 3928 PATTERN : VV1 0xEC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3929 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 3930 3931 PATTERN : VV1 0xEC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3932 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 3933 } 3934 { 3935 ICLASS : VPADDSW 3936 EXCEPTIONS: avx-type-4 3937 CPL : 3 3938 CATEGORY : AVX 3939 EXTENSION : AVX 3940 PATTERN : VV1 0xED VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3941 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 3942 3943 PATTERN : VV1 0xED VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3944 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 3945 } 3946 3947 { 3948 ICLASS : VPADDUSB 3949 EXCEPTIONS: avx-type-4 3950 CPL : 3 3951 CATEGORY : AVX 3952 EXTENSION : AVX 3953 PATTERN : VV1 0xDC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3954 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 3955 3956 PATTERN : VV1 0xDC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3957 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 3958 } 3959 { 3960 ICLASS : VPADDUSW 3961 EXCEPTIONS: avx-type-4 3962 CPL : 3 3963 CATEGORY : AVX 3964 EXTENSION : AVX 3965 PATTERN : VV1 0xDD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3966 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 3967 3968 PATTERN : VV1 0xDD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3969 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 3970 } 3971 3972 { 3973 ICLASS : VPAVGB 3974 EXCEPTIONS: avx-type-4 3975 CPL : 3 3976 CATEGORY : AVX 3977 EXTENSION : AVX 3978 PATTERN : VV1 0xE0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3979 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 3980 3981 PATTERN : VV1 0xE0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3982 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 3983 } 3984 { 3985 ICLASS : VPAVGW 3986 EXCEPTIONS: avx-type-4 3987 CPL : 3 3988 CATEGORY : AVX 3989 EXTENSION : AVX 3990 PATTERN : VV1 0xE3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 3991 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 3992 3993 PATTERN : VV1 0xE3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 3994 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 3995 } 3996 3997 { 3998 ICLASS : VPCMPEQB 3999 EXCEPTIONS: avx-type-4 4000 CPL : 3 4001 CATEGORY : AVX 4002 EXTENSION : AVX 4003 PATTERN : VV1 0x74 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4004 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 4005 4006 PATTERN : VV1 0x74 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4007 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 4008 } 4009 { 4010 ICLASS : VPCMPEQW 4011 EXCEPTIONS: avx-type-4 4012 CPL : 3 4013 CATEGORY : AVX 4014 EXTENSION : AVX 4015 PATTERN : VV1 0x75 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4016 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 4017 4018 PATTERN : VV1 0x75 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4019 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 4020 } 4021 { 4022 ICLASS : VPCMPEQD 4023 EXCEPTIONS: avx-type-4 4024 CPL : 3 4025 CATEGORY : AVX 4026 EXTENSION : AVX 4027 PATTERN : VV1 0x76 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4028 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 4029 4030 PATTERN : VV1 0x76 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4031 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 4032 } 4033 { 4034 ICLASS : VPCMPEQQ 4035 EXCEPTIONS: avx-type-4 4036 CPL : 3 4037 CATEGORY : AVX 4038 EXTENSION : AVX 4039 PATTERN : VV1 0x29 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4040 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 4041 4042 PATTERN : VV1 0x29 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4043 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 4044 } 4045 4046 { 4047 ICLASS : VPCMPGTB 4048 EXCEPTIONS: avx-type-4 4049 CPL : 3 4050 CATEGORY : AVX 4051 EXTENSION : AVX 4052 PATTERN : VV1 0x64 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4053 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 4054 4055 PATTERN : VV1 0x64 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4056 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 4057 } 4058 { 4059 ICLASS : VPCMPGTW 4060 EXCEPTIONS: avx-type-4 4061 CPL : 3 4062 CATEGORY : AVX 4063 EXTENSION : AVX 4064 PATTERN : VV1 0x65 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4065 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 4066 4067 PATTERN : VV1 0x65 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4068 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 4069 } 4070 { 4071 ICLASS : VPCMPGTD 4072 EXCEPTIONS: avx-type-4 4073 CPL : 3 4074 CATEGORY : AVX 4075 EXTENSION : AVX 4076 PATTERN : VV1 0x66 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4077 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 4078 4079 PATTERN : VV1 0x66 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4080 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 4081 } 4082 { 4083 ICLASS : VPCMPGTQ 4084 EXCEPTIONS: avx-type-4 4085 CPL : 3 4086 CATEGORY : AVX 4087 EXTENSION : AVX 4088 PATTERN : VV1 0x37 V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4089 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 4090 4091 PATTERN : VV1 0x37 V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4092 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 4093 } 4094 4095 { 4096 ICLASS : VPHADDW 4097 EXCEPTIONS: avx-type-4 4098 CPL : 3 4099 CATEGORY : AVX 4100 EXTENSION : AVX 4101 PATTERN : VV1 0x01 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4102 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 4103 4104 PATTERN : VV1 0x01 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4105 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 4106 } 4107 { 4108 ICLASS : VPHADDD 4109 EXCEPTIONS: avx-type-4 4110 CPL : 3 4111 CATEGORY : AVX 4112 EXTENSION : AVX 4113 PATTERN : VV1 0x02 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4114 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 4115 4116 PATTERN : VV1 0x02 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4117 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 4118 } 4119 { 4120 ICLASS : VPHADDSW 4121 EXCEPTIONS: avx-type-4 4122 CPL : 3 4123 CATEGORY : AVX 4124 EXTENSION : AVX 4125 PATTERN : VV1 0x03 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4126 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 4127 4128 PATTERN : VV1 0x03 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4129 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 4130 } 4131 { 4132 ICLASS : VPHSUBW 4133 EXCEPTIONS: avx-type-4 4134 CPL : 3 4135 CATEGORY : AVX 4136 EXTENSION : AVX 4137 PATTERN : VV1 0x05 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4138 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 4139 4140 PATTERN : VV1 0x05 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4141 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 4142 } 4143 { 4144 ICLASS : VPHSUBD 4145 EXCEPTIONS: avx-type-4 4146 CPL : 3 4147 CATEGORY : AVX 4148 EXTENSION : AVX 4149 PATTERN : VV1 0x06 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4150 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 4151 4152 PATTERN : VV1 0x06 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4153 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 4154 } 4155 { 4156 ICLASS : VPHSUBSW 4157 EXCEPTIONS: avx-type-4 4158 CPL : 3 4159 CATEGORY : AVX 4160 EXTENSION : AVX 4161 PATTERN : VV1 0x07 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4162 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 4163 4164 PATTERN : VV1 0x07 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4165 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 4166 } 4167 4168 { 4169 ICLASS : VPMULHUW 4170 EXCEPTIONS: avx-type-4 4171 CPL : 3 4172 CATEGORY : AVX 4173 EXTENSION : AVX 4174 PATTERN : VV1 0xE4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4175 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 4176 4177 PATTERN : VV1 0xE4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4178 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 4179 } 4180 { 4181 ICLASS : VPMULHRSW 4182 EXCEPTIONS: avx-type-4 4183 CPL : 3 4184 CATEGORY : AVX 4185 EXTENSION : AVX 4186 PATTERN : VV1 0x0B VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4187 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 4188 4189 PATTERN : VV1 0x0B VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4190 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 4191 } 4192 { 4193 ICLASS : VPMULHW 4194 EXCEPTIONS: avx-type-4 4195 CPL : 3 4196 CATEGORY : AVX 4197 EXTENSION : AVX 4198 PATTERN : VV1 0xE5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4199 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 4200 4201 PATTERN : VV1 0xE5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4202 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 4203 } 4204 { 4205 ICLASS : VPMULLW 4206 EXCEPTIONS: avx-type-4 4207 CPL : 3 4208 CATEGORY : AVX 4209 EXTENSION : AVX 4210 PATTERN : VV1 0xD5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4211 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 4212 4213 PATTERN : VV1 0xD5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4214 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 4215 } 4216 { 4217 ICLASS : VPMULLD 4218 EXCEPTIONS: avx-type-4 4219 CPL : 3 4220 CATEGORY : AVX 4221 EXTENSION : AVX 4222 PATTERN : VV1 0x40 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4223 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 4224 4225 PATTERN : VV1 0x40 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4226 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 4227 } 4228 4229 { 4230 ICLASS : VPMULUDQ 4231 EXCEPTIONS: avx-type-4 4232 CPL : 3 4233 CATEGORY : AVX 4234 EXTENSION : AVX 4235 PATTERN : VV1 0xF4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4236 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 4237 4238 PATTERN : VV1 0xF4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4239 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 4240 } 4241 { 4242 ICLASS : VPMULDQ 4243 EXCEPTIONS: avx-type-4 4244 CPL : 3 4245 CATEGORY : AVX 4246 EXTENSION : AVX 4247 PATTERN : VV1 0x28 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4248 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 4249 4250 PATTERN : VV1 0x28 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4251 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 4252 } 4253 4254 { 4255 ICLASS : VPSADBW 4256 EXCEPTIONS: avx-type-4 4257 CPL : 3 4258 CATEGORY : AVX 4259 EXTENSION : AVX 4260 PATTERN : VV1 0xF6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4261 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 4262 4263 PATTERN : VV1 0xF6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4264 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 4265 } 4266 { 4267 ICLASS : VPSHUFB 4268 EXCEPTIONS: avx-type-4 4269 CPL : 3 4270 CATEGORY : AVX 4271 EXTENSION : AVX 4272 PATTERN : VV1 0x00 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4273 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 4274 4275 PATTERN : VV1 0x00 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4276 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 4277 } 4278 4279 { 4280 ICLASS : VPSIGNB 4281 EXCEPTIONS: avx-type-4 4282 CPL : 3 4283 CATEGORY : AVX 4284 EXTENSION : AVX 4285 PATTERN : VV1 0x08 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4286 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 4287 4288 PATTERN : VV1 0x08 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4289 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 4290 } 4291 { 4292 ICLASS : VPSIGNW 4293 EXCEPTIONS: avx-type-4 4294 CPL : 3 4295 CATEGORY : AVX 4296 EXTENSION : AVX 4297 PATTERN : VV1 0x09 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4298 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 4299 4300 PATTERN : VV1 0x09 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4301 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 4302 } 4303 { 4304 ICLASS : VPSIGND 4305 EXCEPTIONS: avx-type-4 4306 CPL : 3 4307 CATEGORY : AVX 4308 EXTENSION : AVX 4309 PATTERN : VV1 0x0A VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4310 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 4311 4312 PATTERN : VV1 0x0A VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4313 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 4314 } 4315 4316 { 4317 ICLASS : VPSUBSB 4318 EXCEPTIONS: avx-type-4 4319 CPL : 3 4320 CATEGORY : AVX 4321 EXTENSION : AVX 4322 PATTERN : VV1 0xE8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4323 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 4324 4325 PATTERN : VV1 0xE8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4326 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 4327 } 4328 { 4329 ICLASS : VPSUBSW 4330 EXCEPTIONS: avx-type-4 4331 CPL : 3 4332 CATEGORY : AVX 4333 EXTENSION : AVX 4334 PATTERN : VV1 0xE9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4335 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 4336 4337 PATTERN : VV1 0xE9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4338 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 4339 } 4340 4341 { 4342 ICLASS : VPSUBUSB 4343 EXCEPTIONS: avx-type-4 4344 CPL : 3 4345 CATEGORY : AVX 4346 EXTENSION : AVX 4347 PATTERN : VV1 0xD8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4348 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 4349 4350 PATTERN : VV1 0xD8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4351 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 4352 } 4353 { 4354 ICLASS : VPSUBUSW 4355 EXCEPTIONS: avx-type-4 4356 CPL : 3 4357 CATEGORY : AVX 4358 EXTENSION : AVX 4359 PATTERN : VV1 0xD9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4360 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 4361 4362 PATTERN : VV1 0xD9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4363 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 4364 } 4365 4366 { 4367 ICLASS : VPSUBB 4368 EXCEPTIONS: avx-type-4 4369 CPL : 3 4370 CATEGORY : AVX 4371 EXTENSION : AVX 4372 PATTERN : VV1 0xF8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4373 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 4374 4375 PATTERN : VV1 0xF8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4376 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 4377 } 4378 { 4379 ICLASS : VPSUBW 4380 EXCEPTIONS: avx-type-4 4381 CPL : 3 4382 CATEGORY : AVX 4383 EXTENSION : AVX 4384 PATTERN : VV1 0xF9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4385 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 4386 4387 PATTERN : VV1 0xF9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4388 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 4389 } 4390 { 4391 ICLASS : VPSUBD 4392 EXCEPTIONS: avx-type-4 4393 CPL : 3 4394 CATEGORY : AVX 4395 EXTENSION : AVX 4396 PATTERN : VV1 0xFA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4397 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 4398 4399 PATTERN : VV1 0xFA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4400 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 4401 } 4402 { 4403 ICLASS : VPSUBQ 4404 EXCEPTIONS: avx-type-4 4405 CPL : 3 4406 CATEGORY : AVX 4407 EXTENSION : AVX 4408 PATTERN : VV1 0xFB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4409 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 4410 4411 PATTERN : VV1 0xFB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4412 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 4413 } 4414 4415 { 4416 ICLASS : VPUNPCKHBW 4417 EXCEPTIONS: avx-type-4 4418 CPL : 3 4419 CATEGORY : AVX 4420 EXTENSION : AVX 4421 PATTERN : VV1 0x68 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4422 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 4423 4424 PATTERN : VV1 0x68 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4425 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 4426 } 4427 { 4428 ICLASS : VPUNPCKHWD 4429 EXCEPTIONS: avx-type-4 4430 CPL : 3 4431 CATEGORY : AVX 4432 EXTENSION : AVX 4433 PATTERN : VV1 0x69 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4434 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 4435 4436 PATTERN : VV1 0x69 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4437 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 4438 } 4439 { 4440 ICLASS : VPUNPCKHDQ 4441 EXCEPTIONS: avx-type-4 4442 CPL : 3 4443 CATEGORY : AVX 4444 EXTENSION : AVX 4445 PATTERN : VV1 0x6A VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4446 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 4447 4448 PATTERN : VV1 0x6A VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4449 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 4450 } 4451 { 4452 ICLASS : VPUNPCKHQDQ 4453 EXCEPTIONS: avx-type-4 4454 CPL : 3 4455 CATEGORY : AVX 4456 EXTENSION : AVX 4457 PATTERN : VV1 0x6D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4458 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 4459 4460 PATTERN : VV1 0x6D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4461 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 4462 } 4463 4464 { 4465 ICLASS : VPUNPCKLBW 4466 EXCEPTIONS: avx-type-4 4467 CPL : 3 4468 CATEGORY : AVX 4469 EXTENSION : AVX 4470 PATTERN : VV1 0x60 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4471 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 4472 4473 PATTERN : VV1 0x60 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4474 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 4475 } 4476 { 4477 ICLASS : VPUNPCKLWD 4478 EXCEPTIONS: avx-type-4 4479 CPL : 3 4480 CATEGORY : AVX 4481 EXTENSION : AVX 4482 PATTERN : VV1 0x61 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4483 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 4484 4485 PATTERN : VV1 0x61 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4486 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 4487 } 4488 { 4489 ICLASS : VPUNPCKLDQ 4490 EXCEPTIONS: avx-type-4 4491 CPL : 3 4492 CATEGORY : AVX 4493 EXTENSION : AVX 4494 PATTERN : VV1 0x62 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4495 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 4496 4497 PATTERN : VV1 0x62 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4498 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 4499 } 4500 { 4501 ICLASS : VPUNPCKLQDQ 4502 EXCEPTIONS: avx-type-4 4503 CPL : 3 4504 CATEGORY : AVX 4505 EXTENSION : AVX 4506 PATTERN : VV1 0x6C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4507 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 4508 4509 PATTERN : VV1 0x6C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4510 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 4511 } 4512 4513 4514 4515 { 4516 ICLASS : VPSRLDQ 4517 EXCEPTIONS: avx-type-7 4518 CPL : 3 4519 CATEGORY : AVX 4520 EXTENSION : AVX 4521 PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() 4522 OPERANDS : REG0=XMM_N():w:dq:u128 REG1=XMM_B():r:dq:u128 IMM0:r:b # NDD 4523 } 4524 { 4525 ICLASS : VPSLLDQ 4526 EXCEPTIONS: avx-type-7 4527 CPL : 3 4528 CATEGORY : AVX 4529 EXTENSION : AVX 4530 PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() 4531 OPERANDS : REG0=XMM_N():w:dq:u128 REG1=XMM_B():r:dq:u128 IMM0:r:b # NDD 4532 } 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 { 4554 ICLASS : VMOVLHPS 4555 EXCEPTIONS: avx-type-7 4556 CPL : 3 4557 CATEGORY : DATAXFER 4558 EXTENSION : AVX 4559 PATTERN : VV1 0x16 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4560 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:q:f32 REG2=XMM_B():r:q:f32 4561 } 4562 { 4563 ICLASS : VMOVHLPS 4564 EXCEPTIONS: avx-type-7 4565 CPL : 3 4566 CATEGORY : DATAXFER 4567 EXTENSION : AVX 4568 PATTERN : VV1 0x12 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4569 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 4570 } 4571 4572 4573 4574 4575 4576 4577 4578 { 4579 ICLASS : VPALIGNR 4580 EXCEPTIONS: avx-type-4 4581 CPL : 3 4582 CATEGORY : AVX 4583 EXTENSION : AVX 4584 PATTERN : VV1 0x0F VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 4585 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b 4586 4587 PATTERN : VV1 0x0F VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 4588 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b 4589 } 4590 { 4591 ICLASS : VPBLENDW 4592 EXCEPTIONS: avx-type-4 4593 CPL : 3 4594 CATEGORY : AVX 4595 EXTENSION : AVX 4596 PATTERN : VV1 0x0E VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 4597 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b 4598 4599 PATTERN : VV1 0x0E VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 4600 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b 4601 } 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 ############################################################ 4615 { 4616 ICLASS : VROUNDPD 4617 EXCEPTIONS: avx-type-2 4618 CPL : 3 4619 CATEGORY : AVX 4620 EXTENSION : AVX 4621 ATTRIBUTES: MXCSR 4622 PATTERN : VV1 0x09 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 4623 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 IMM0:r:b 4624 4625 PATTERN : VV1 0x09 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 4626 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b 4627 4628 PATTERN : VV1 0x09 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 4629 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b 4630 4631 PATTERN : VV1 0x09 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 4632 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b 4633 } 4634 { 4635 ICLASS : VROUNDPS 4636 EXCEPTIONS: avx-type-2 4637 CPL : 3 4638 CATEGORY : AVX 4639 EXTENSION : AVX 4640 ATTRIBUTES: MXCSR 4641 PATTERN : VV1 0x08 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 4642 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 IMM0:r:b 4643 4644 PATTERN : VV1 0x08 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 4645 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b 4646 4647 PATTERN : VV1 0x08 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 4648 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 IMM0:r:b 4649 4650 PATTERN : VV1 0x08 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 4651 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 IMM0:r:b 4652 } 4653 { 4654 ICLASS : VROUNDSD 4655 EXCEPTIONS: avx-type-3 4656 CPL : 3 4657 CATEGORY : AVX 4658 EXTENSION : AVX 4659 ATTRIBUTES: MXCSR simd_scalar 4660 PATTERN : VV1 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 4661 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 4662 4663 PATTERN : VV1 0x0B V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 4664 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b 4665 } 4666 { 4667 ICLASS : VROUNDSS 4668 EXCEPTIONS: avx-type-3 4669 CPL : 3 4670 CATEGORY : AVX 4671 EXTENSION : AVX 4672 ATTRIBUTES: MXCSR simd_scalar 4673 PATTERN : VV1 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 4674 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 4675 4676 PATTERN : VV1 0x0A V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 4677 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b 4678 } 4679 4680 { 4681 ICLASS : VSHUFPD 4682 EXCEPTIONS: avx-type-4 4683 CPL : 3 4684 CATEGORY : AVX 4685 EXTENSION : AVX 4686 PATTERN : VV1 0xC6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 4687 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b 4688 4689 PATTERN : VV1 0xC6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 4690 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b 4691 4692 PATTERN : VV1 0xC6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 4693 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b 4694 4695 PATTERN : VV1 0xC6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 4696 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b 4697 } 4698 { 4699 ICLASS : VSHUFPS 4700 EXCEPTIONS: avx-type-4 4701 CPL : 3 4702 CATEGORY : AVX 4703 EXTENSION : AVX 4704 PATTERN : VV1 0xC6 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 4705 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b 4706 4707 PATTERN : VV1 0xC6 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 4708 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b 4709 4710 PATTERN : VV1 0xC6 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 4711 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b 4712 4713 PATTERN : VV1 0xC6 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 4714 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b 4715 } 4716 4717 { 4718 ICLASS : VRCPPS 4719 EXCEPTIONS: avx-type-4 4720 CPL : 3 4721 CATEGORY : AVX 4722 EXTENSION : AVX 4723 PATTERN : VV1 0x53 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4724 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 4725 4726 PATTERN : VV1 0x53 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4727 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 4728 4729 PATTERN : VV1 0x53 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4730 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 4731 4732 PATTERN : VV1 0x53 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4733 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 4734 } 4735 { 4736 ICLASS : VRCPSS 4737 EXCEPTIONS: avx-type-5 4738 CPL : 3 4739 CATEGORY : AVX 4740 EXTENSION : AVX 4741 ATTRIBUTES: simd_scalar 4742 PATTERN : VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4743 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 4744 4745 PATTERN : VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4746 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 4747 } 4748 4749 { 4750 ICLASS : VRSQRTPS 4751 EXCEPTIONS: avx-type-4 4752 CPL : 3 4753 CATEGORY : AVX 4754 EXTENSION : AVX 4755 PATTERN : VV1 0x52 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4756 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 4757 4758 PATTERN : VV1 0x52 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4759 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 4760 4761 PATTERN : VV1 0x52 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4762 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 4763 4764 PATTERN : VV1 0x52 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4765 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 4766 } 4767 { 4768 ICLASS : VRSQRTSS 4769 EXCEPTIONS: avx-type-5 4770 CPL : 3 4771 CATEGORY : AVX 4772 EXTENSION : AVX 4773 ATTRIBUTES: simd_scalar 4774 PATTERN : VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4775 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 4776 4777 PATTERN : VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4778 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 4779 } 4780 4781 { 4782 ICLASS : VSQRTPD 4783 EXCEPTIONS: avx-type-2 4784 CPL : 3 4785 CATEGORY : AVX 4786 EXTENSION : AVX 4787 ATTRIBUTES: MXCSR 4788 PATTERN : VV1 0x51 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4789 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 4790 4791 PATTERN : VV1 0x51 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4792 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 4793 4794 PATTERN : VV1 0x51 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4795 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 4796 4797 PATTERN : VV1 0x51 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4798 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 4799 } 4800 { 4801 ICLASS : VSQRTPS 4802 EXCEPTIONS: avx-type-2 4803 CPL : 3 4804 CATEGORY : AVX 4805 EXTENSION : AVX 4806 ATTRIBUTES: MXCSR 4807 PATTERN : VV1 0x51 VL128 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4808 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 4809 4810 PATTERN : VV1 0x51 VL128 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4811 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 4812 4813 PATTERN : VV1 0x51 VL256 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4814 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 4815 4816 PATTERN : VV1 0x51 VL256 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4817 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 4818 } 4819 { 4820 ICLASS : VSQRTSD 4821 EXCEPTIONS: avx-type-3 4822 CPL : 3 4823 CATEGORY : AVX 4824 EXTENSION : AVX 4825 ATTRIBUTES : MXCSR simd_scalar 4826 PATTERN : VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4827 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 4828 4829 PATTERN : VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4830 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 4831 } 4832 { 4833 ICLASS : VSQRTSS 4834 EXCEPTIONS: avx-type-3 4835 CPL : 3 4836 CATEGORY : AVX 4837 EXTENSION : AVX 4838 ATTRIBUTES: MXCSR simd_scalar 4839 PATTERN : VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4840 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 4841 4842 PATTERN : VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4843 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 4844 } 4845 4846 4847 { 4848 ICLASS : VUNPCKHPD 4849 EXCEPTIONS: avx-type-4 4850 CPL : 3 4851 CATEGORY : AVX 4852 EXTENSION : AVX 4853 PATTERN : VV1 0x15 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4854 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 4855 4856 PATTERN : VV1 0x15 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4857 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 4858 4859 PATTERN : VV1 0x15 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4860 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 4861 4862 PATTERN : VV1 0x15 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4863 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 4864 } 4865 { 4866 ICLASS : VUNPCKHPS 4867 EXCEPTIONS: avx-type-4 4868 CPL : 3 4869 CATEGORY : AVX 4870 EXTENSION : AVX 4871 PATTERN : VV1 0x15 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4872 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 4873 4874 PATTERN : VV1 0x15 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4875 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 4876 4877 PATTERN : VV1 0x15 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4878 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 4879 4880 PATTERN : VV1 0x15 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4881 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 4882 } 4883 4884 4885 4886 { 4887 ICLASS : VSUBPD 4888 EXCEPTIONS: avx-type-2 4889 CPL : 3 4890 CATEGORY : AVX 4891 EXTENSION : AVX 4892 ATTRIBUTES: MXCSR 4893 PATTERN : VV1 0x5C V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4894 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 4895 4896 PATTERN : VV1 0x5C V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4897 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 4898 4899 PATTERN : VV1 0x5C V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4900 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 4901 4902 PATTERN : VV1 0x5C V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4903 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 4904 } 4905 { 4906 ICLASS : VSUBPS 4907 EXCEPTIONS: avx-type-2 4908 CPL : 3 4909 CATEGORY : AVX 4910 EXTENSION : AVX 4911 ATTRIBUTES: MXCSR 4912 PATTERN : VV1 0x5C VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4913 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 4914 4915 PATTERN : VV1 0x5C VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4916 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 4917 4918 PATTERN : VV1 0x5C VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4919 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 4920 4921 PATTERN : VV1 0x5C VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4922 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 4923 } 4924 { 4925 ICLASS : VSUBSD 4926 EXCEPTIONS: avx-type-3 4927 CPL : 3 4928 CATEGORY : AVX 4929 EXTENSION : AVX 4930 ATTRIBUTES : MXCSR SIMD_SCALAR 4931 PATTERN : VV1 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4932 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 4933 4934 PATTERN : VV1 0x5C VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4935 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 4936 } 4937 { 4938 ICLASS : VSUBSS 4939 EXCEPTIONS: avx-type-3 4940 CPL : 3 4941 CATEGORY : AVX 4942 EXTENSION : AVX 4943 ATTRIBUTES: MXCSR simd_scalar 4944 PATTERN : VV1 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4945 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 4946 4947 PATTERN : VV1 0x5C VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4948 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 4949 } 4950 4951 { 4952 ICLASS : VMULPD 4953 EXCEPTIONS: avx-type-2 4954 CPL : 3 4955 CATEGORY : AVX 4956 EXTENSION : AVX 4957 ATTRIBUTES: MXCSR 4958 PATTERN : VV1 0x59 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4959 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 4960 4961 PATTERN : VV1 0x59 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4962 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 4963 4964 PATTERN : VV1 0x59 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4965 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 4966 4967 PATTERN : VV1 0x59 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4968 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 4969 } 4970 { 4971 ICLASS : VMULPS 4972 EXCEPTIONS: avx-type-2 4973 CPL : 3 4974 CATEGORY : AVX 4975 EXTENSION : AVX 4976 ATTRIBUTES: MXCSR 4977 PATTERN : VV1 0x59 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4978 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 4979 4980 PATTERN : VV1 0x59 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4981 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 4982 4983 PATTERN : VV1 0x59 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4984 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 4985 4986 PATTERN : VV1 0x59 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 4987 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 4988 } 4989 { 4990 ICLASS : VMULSD 4991 EXCEPTIONS: avx-type-3 4992 CPL : 3 4993 CATEGORY : AVX 4994 EXTENSION : AVX 4995 ATTRIBUTES : MXCSR simd_scalar 4996 PATTERN : VV1 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 4997 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 4998 4999 PATTERN : VV1 0x59 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5000 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 5001 } 5002 { 5003 ICLASS : VMULSS 5004 EXCEPTIONS: avx-type-3 5005 CPL : 3 5006 CATEGORY : AVX 5007 EXTENSION : AVX 5008 ATTRIBUTES: MXCSR simd_scalar 5009 PATTERN : VV1 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5010 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 5011 5012 PATTERN : VV1 0x59 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5013 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 5014 } 5015 5016 { 5017 ICLASS : VORPD 5018 EXCEPTIONS: avx-type-4 5019 CPL : 3 5020 CATEGORY : LOGICAL_FP 5021 EXTENSION : AVX 5022 PATTERN : VV1 0x56 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5023 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 5024 5025 PATTERN : VV1 0x56 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5026 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 5027 5028 PATTERN : VV1 0x56 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5029 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 5030 5031 PATTERN : VV1 0x56 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5032 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 5033 } 5034 { 5035 ICLASS : VORPS 5036 EXCEPTIONS: avx-type-4 5037 CPL : 3 5038 CATEGORY : LOGICAL_FP 5039 EXTENSION : AVX 5040 PATTERN : VV1 0x56 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5041 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 5042 5043 PATTERN : VV1 0x56 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5044 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 5045 5046 PATTERN : VV1 0x56 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5047 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 5048 5049 PATTERN : VV1 0x56 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5050 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 5051 } 5052 5053 { 5054 ICLASS : VPMAXSB 5055 EXCEPTIONS: avx-type-4 5056 CPL : 3 5057 CATEGORY : AVX 5058 EXTENSION : AVX 5059 PATTERN : VV1 0x3C VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5060 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 5061 5062 PATTERN : VV1 0x3C VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5063 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 5064 } 5065 { 5066 ICLASS : VPMAXSW 5067 EXCEPTIONS: avx-type-4 5068 CPL : 3 5069 CATEGORY : AVX 5070 EXTENSION : AVX 5071 PATTERN : VV1 0xEE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5072 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 5073 5074 PATTERN : VV1 0xEE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5075 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 5076 } 5077 { 5078 ICLASS : VPMAXSD 5079 EXCEPTIONS: avx-type-4 5080 CPL : 3 5081 CATEGORY : AVX 5082 EXTENSION : AVX 5083 PATTERN : VV1 0x3D VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5084 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 5085 5086 PATTERN : VV1 0x3D VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5087 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 5088 } 5089 5090 { 5091 ICLASS : VPMAXUB 5092 EXCEPTIONS: avx-type-4 5093 CPL : 3 5094 CATEGORY : AVX 5095 EXTENSION : AVX 5096 PATTERN : VV1 0xDE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5097 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 5098 5099 PATTERN : VV1 0xDE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5100 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 5101 } 5102 { 5103 ICLASS : VPMAXUW 5104 EXCEPTIONS: avx-type-4 5105 CPL : 3 5106 CATEGORY : AVX 5107 EXTENSION : AVX 5108 PATTERN : VV1 0x3E VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5109 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 5110 5111 PATTERN : VV1 0x3E VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5112 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 5113 } 5114 { 5115 ICLASS : VPMAXUD 5116 EXCEPTIONS: avx-type-4 5117 CPL : 3 5118 CATEGORY : AVX 5119 EXTENSION : AVX 5120 PATTERN : VV1 0x3F VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5121 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 5122 5123 PATTERN : VV1 0x3F VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5124 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 5125 } 5126 5127 { 5128 ICLASS : VPMINSB 5129 EXCEPTIONS: avx-type-4 5130 CPL : 3 5131 CATEGORY : AVX 5132 EXTENSION : AVX 5133 PATTERN : VV1 0x38 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5134 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 5135 5136 PATTERN : VV1 0x38 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5137 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 5138 } 5139 { 5140 ICLASS : VPMINSW 5141 EXCEPTIONS: avx-type-4 5142 CPL : 3 5143 CATEGORY : AVX 5144 EXTENSION : AVX 5145 PATTERN : VV1 0xEA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5146 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 5147 5148 PATTERN : VV1 0xEA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5149 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 5150 } 5151 { 5152 ICLASS : VPMINSD 5153 EXCEPTIONS: avx-type-4 5154 CPL : 3 5155 CATEGORY : AVX 5156 EXTENSION : AVX 5157 PATTERN : VV1 0x39 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5158 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 5159 5160 PATTERN : VV1 0x39 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5161 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 5162 } 5163 5164 { 5165 ICLASS : VPMINUB 5166 EXCEPTIONS: avx-type-4 5167 CPL : 3 5168 CATEGORY : AVX 5169 EXTENSION : AVX 5170 PATTERN : VV1 0xDA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5171 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 5172 5173 PATTERN : VV1 0xDA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5174 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 5175 } 5176 { 5177 ICLASS : VPMINUW 5178 EXCEPTIONS: avx-type-4 5179 CPL : 3 5180 CATEGORY : AVX 5181 EXTENSION : AVX 5182 PATTERN : VV1 0x3A V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5183 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 5184 5185 PATTERN : VV1 0x3A V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5186 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 5187 } 5188 { 5189 ICLASS : VPMINUD 5190 EXCEPTIONS: avx-type-4 5191 CPL : 3 5192 CATEGORY : AVX 5193 EXTENSION : AVX 5194 PATTERN : VV1 0x3B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5195 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 5196 5197 PATTERN : VV1 0x3B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5198 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 5199 } 5200 5201 5202 { 5203 ICLASS : VPMADDWD 5204 EXCEPTIONS: avx-type-4 5205 CPL : 3 5206 CATEGORY : AVX 5207 EXTENSION : AVX 5208 PATTERN : VV1 0xF5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5209 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 5210 5211 PATTERN : VV1 0xF5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5212 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 5213 } 5214 { 5215 ICLASS : VPMADDUBSW 5216 EXCEPTIONS: avx-type-4 5217 CPL : 3 5218 CATEGORY : AVX 5219 EXTENSION : AVX 5220 PATTERN : VV1 0x04 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5221 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:i8 5222 5223 PATTERN : VV1 0x04 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5224 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:i8 5225 } 5226 5227 5228 { 5229 ICLASS : VMPSADBW 5230 EXCEPTIONS: avx-type-4 5231 CPL : 3 5232 CATEGORY : AVX 5233 EXTENSION : AVX 5234 PATTERN : VV1 0x42 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5235 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b 5236 5237 PATTERN : VV1 0x42 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5238 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b 5239 } 5240 5241 5242 ############################################################ 5243 { 5244 ICLASS : VPSLLW 5245 EXCEPTIONS: avx-type-7 5246 CPL : 3 5247 CATEGORY : AVX 5248 EXTENSION : AVX 5249 PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 5250 OPERANDS : REG0=XMM_N():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b # NDD 5251 } 5252 { 5253 ICLASS : VPSLLD 5254 EXCEPTIONS: avx-type-7 5255 CPL : 3 5256 CATEGORY : AVX 5257 EXTENSION : AVX 5258 PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 5259 OPERANDS : REG0=XMM_N():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b #NDD 5260 } 5261 { 5262 ICLASS : VPSLLQ 5263 EXCEPTIONS: avx-type-7 5264 CPL : 3 5265 CATEGORY : AVX 5266 EXTENSION : AVX 5267 PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 5268 OPERANDS : REG0=XMM_N():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b # NDD 5269 } 5270 5271 { 5272 ICLASS : VPSRAW 5273 EXCEPTIONS: avx-type-7 5274 CPL : 3 5275 CATEGORY : AVX 5276 EXTENSION : AVX 5277 PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 5278 OPERANDS : REG0=XMM_N():w:dq:i16 REG1=XMM_B():r:dq:i16 IMM0:r:b # NDD 5279 } 5280 { 5281 ICLASS : VPSRAD 5282 EXCEPTIONS: avx-type-7 5283 CPL : 3 5284 CATEGORY : AVX 5285 EXTENSION : AVX 5286 PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 5287 OPERANDS : REG0=XMM_N():w:dq:i32 REG1=XMM_B():r:dq:i32 IMM0:r:b # NDD 5288 } 5289 { 5290 ICLASS : VPSRLW 5291 EXCEPTIONS: avx-type-7 5292 CPL : 3 5293 CATEGORY : AVX 5294 EXTENSION : AVX 5295 PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 5296 OPERANDS : REG0=XMM_N():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b # NDD 5297 } 5298 { 5299 ICLASS : VPSRLD 5300 EXCEPTIONS: avx-type-7 5301 CPL : 3 5302 CATEGORY : AVX 5303 EXTENSION : AVX 5304 PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 5305 OPERANDS : REG0=XMM_N():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b # NDD 5306 } 5307 { 5308 ICLASS : VPSRLQ 5309 EXCEPTIONS: avx-type-7 5310 CPL : 3 5311 CATEGORY : AVX 5312 EXTENSION : AVX 5313 PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 5314 OPERANDS : REG0=XMM_N():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b # NDD 5315 } 5316 5317 5318 { 5319 ICLASS : VUCOMISD 5320 EXCEPTIONS: avx-type-3 5321 CPL : 3 5322 CATEGORY : AVX 5323 EXTENSION : AVX 5324 ATTRIBUTES : simd_scalar MXCSR 5325 5326 FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] 5327 5328 PATTERN : VV1 0x2E V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5329 OPERANDS : REG0=XMM_R():r:dq:f64 MEM0:r:q:f64 5330 5331 PATTERN : VV1 0x2E V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5332 OPERANDS : REG0=XMM_R():r:dq:f64 REG1=XMM_B():r:q:f64 5333 } 5334 5335 { 5336 ICLASS : VUCOMISS 5337 EXCEPTIONS: avx-type-3 5338 CPL : 3 5339 CATEGORY : AVX 5340 EXTENSION : AVX 5341 ATTRIBUTES : simd_scalar MXCSR 5342 5343 FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] 5344 5345 PATTERN : VV1 0x2E VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5346 OPERANDS : REG0=XMM_R():r:dq:f32 MEM0:r:d:f32 5347 5348 PATTERN : VV1 0x2E VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5349 OPERANDS : REG0=XMM_R():r:dq:f32 REG1=XMM_B():r:d:f32 5350 } 5351 5352 ############################################### 5353 5354 5355 { 5356 ICLASS : VUNPCKLPD 5357 EXCEPTIONS: avx-type-4 5358 CPL : 3 5359 CATEGORY : AVX 5360 EXTENSION : AVX 5361 PATTERN : VV1 0x14 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5362 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 5363 5364 PATTERN : VV1 0x14 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5365 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 5366 5367 PATTERN : VV1 0x14 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5368 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 5369 5370 PATTERN : VV1 0x14 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5371 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 5372 } 5373 5374 5375 { 5376 ICLASS : VUNPCKLPS 5377 EXCEPTIONS: avx-type-4 5378 CPL : 3 5379 CATEGORY : AVX 5380 EXTENSION : AVX 5381 PATTERN : VV1 0x14 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5382 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 5383 5384 PATTERN : VV1 0x14 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5385 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 5386 5387 PATTERN : VV1 0x14 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5388 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 5389 5390 PATTERN : VV1 0x14 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5391 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 5392 } 5393 5394 5395 5396 5397 { 5398 ICLASS : VXORPD 5399 EXCEPTIONS: avx-type-4 5400 CPL : 3 5401 CATEGORY : LOGICAL_FP 5402 EXTENSION : AVX 5403 PATTERN : VV1 0x57 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5404 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 5405 5406 PATTERN : VV1 0x57 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5407 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 5408 5409 PATTERN : VV1 0x57 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5410 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 5411 5412 PATTERN : VV1 0x57 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5413 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 5414 } 5415 5416 5417 { 5418 ICLASS : VXORPS 5419 EXCEPTIONS: avx-type-4 5420 CPL : 3 5421 CATEGORY : LOGICAL_FP 5422 EXTENSION : AVX 5423 PATTERN : VV1 0x57 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5424 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 5425 5426 PATTERN : VV1 0x57 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5427 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 5428 5429 PATTERN : VV1 0x57 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5430 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 5431 5432 PATTERN : VV1 0x57 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5433 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 5434 } 5435 5436 5437 ############################################################################ 5438 5439 { 5440 ICLASS : VMOVSS 5441 EXCEPTIONS: avx-type-5 5442 CPL : 3 5443 CATEGORY : DATAXFER 5444 EXTENSION : AVX 5445 ATTRIBUTES : simd_scalar 5446 5447 # NOTE: REG1 is ignored!!! 5448 PATTERN : VV1 0x10 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() 5449 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 5450 5451 PATTERN : VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5452 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 5453 IFORM : VMOVSS_XMMdq_XMMdq_XMMd_10 5454 5455 PATTERN : VV1 0x11 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() 5456 OPERANDS : MEM0:w:d:f32 REG0=XMM_R():r:d:f32 5457 5458 PATTERN : VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5459 OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_R():r:d:f32 5460 IFORM : VMOVSS_XMMdq_XMMdq_XMMd_11 5461 } 5462 ############################################################################ 5463 { 5464 ICLASS : VMOVSD 5465 EXCEPTIONS: avx-type-5 5466 CPL : 3 5467 CATEGORY : DATAXFER 5468 EXTENSION : AVX 5469 ATTRIBUTES : simd_scalar 5470 5471 # NOTE: REG1 is ignored!!! 5472 PATTERN : VV1 0x10 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() 5473 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 5474 5475 PATTERN : VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5476 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 5477 IFORM : VMOVSD_XMMdq_XMMdq_XMMq_10 5478 5479 PATTERN : VV1 0x11 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() 5480 OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:q:f64 5481 5482 PATTERN : VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5483 OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_R():r:q:f64 5484 IFORM : VMOVSD_XMMdq_XMMdq_XMMq_11 5485 } 5486 ############################################################################ 5487 { 5488 ICLASS : VMOVUPD 5489 EXCEPTIONS: avx-type-4M 5490 CPL : 3 5491 CATEGORY : DATAXFER 5492 EXTENSION : AVX 5493 5494 PATTERN : VV1 0x10 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5495 OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 5496 5497 PATTERN : VV1 0x10 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5498 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 5499 IFORM : VMOVUPD_XMMdq_XMMdq_10 5500 5501 PATTERN : VV1 0x11 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5502 OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 5503 5504 PATTERN : VV1 0x11 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5505 OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64 5506 IFORM : VMOVUPD_XMMdq_XMMdq_11 5507 5508 # 256b versions 5509 5510 PATTERN : VV1 0x10 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5511 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 5512 5513 PATTERN : VV1 0x10 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5514 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 5515 IFORM : VMOVUPD_YMMqq_YMMqq_10 5516 5517 PATTERN : VV1 0x11 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5518 OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 5519 5520 PATTERN : VV1 0x11 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5521 OPERANDS : REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64 5522 IFORM : VMOVUPD_YMMqq_YMMqq_11 5523 } 5524 5525 ############################################################################ 5526 { 5527 ICLASS : VMOVUPS 5528 EXCEPTIONS: avx-type-4M 5529 CPL : 3 5530 CATEGORY : DATAXFER 5531 EXTENSION : AVX 5532 5533 PATTERN : VV1 0x10 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5534 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 5535 5536 PATTERN : VV1 0x10 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5537 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 5538 IFORM : VMOVUPS_XMMdq_XMMdq_10 5539 5540 PATTERN : VV1 0x11 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5541 OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 5542 5543 PATTERN : VV1 0x11 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5544 OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_R():r:dq:f32 5545 IFORM : VMOVUPS_XMMdq_XMMdq_11 5546 5547 # 256b versions 5548 5549 PATTERN : VV1 0x10 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5550 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 5551 5552 PATTERN : VV1 0x10 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5553 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 5554 IFORM : VMOVUPS_YMMqq_YMMqq_10 5555 5556 PATTERN : VV1 0x11 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5557 OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 5558 5559 PATTERN : VV1 0x11 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5560 OPERANDS : REG0=YMM_B():w:qq:f32 REG1=YMM_R():r:qq:f32 5561 IFORM : VMOVUPS_YMMqq_YMMqq_11 5562 } 5563 5564 5565 ############################################################################ 5566 { 5567 ICLASS : VMOVLPD 5568 EXCEPTIONS: avx-type-5 5569 CPL : 3 5570 CATEGORY : DATAXFER 5571 EXTENSION : AVX 5572 COMMENT: 3op version uses high part of XMM_N 5573 PATTERN : VV1 0x12 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5574 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 5575 5576 PATTERN : VV1 0x13 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5577 OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:q:f64 5578 } 5579 5580 { 5581 ICLASS : VMOVLPS 5582 EXCEPTIONS: avx-type-5 5583 CPL : 3 5584 CATEGORY : DATAXFER 5585 EXTENSION : AVX 5586 5587 COMMENT: 3op version uses high part of XMM_N 5588 PATTERN : VV1 0x12 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5589 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:f32 5590 5591 PATTERN : VV1 0x13 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5592 OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:q:f32 5593 } 5594 5595 { 5596 ICLASS : VMOVHPD 5597 EXCEPTIONS: avx-type-5 5598 CPL : 3 5599 CATEGORY : DATAXFER 5600 EXTENSION : AVX 5601 COMMENT: 3op form use low bits of REG1, 2op form uses high bits of REG0 5602 PATTERN : VV1 0x16 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5603 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 5604 5605 PATTERN : VV1 0x17 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5606 OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:dq:f64 5607 } 5608 5609 { 5610 ICLASS : VMOVHPS 5611 EXCEPTIONS: avx-type-5 5612 CPL : 3 5613 CATEGORY : DATAXFER 5614 EXTENSION : AVX 5615 5616 COMMENT: 3op form use low bits of REG1, 2op form uses high bits of REG0 5617 PATTERN : VV1 0x16 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5618 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:q:f32 MEM0:r:q:f32 5619 5620 PATTERN : VV1 0x17 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5621 OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:dq:f32 5622 } 5623 ############################################################################ 5624 5625 { 5626 ICLASS : VMOVMSKPD 5627 EXCEPTIONS: avx-type-7 5628 CPL : 3 5629 CATEGORY : DATAXFER 5630 EXTENSION : AVX 5631 PATTERN : VV1 0x50 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5632 OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:f64 5633 5634 # 256b versions 5635 5636 PATTERN : VV1 0x50 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5637 OPERANDS : REG0=GPR32_R():w:d REG1=YMM_B():r:qq:f64 5638 } 5639 5640 { 5641 ICLASS : VMOVMSKPS 5642 EXCEPTIONS: avx-type-7 5643 CPL : 3 5644 CATEGORY : DATAXFER 5645 EXTENSION : AVX 5646 PATTERN : VV1 0x50 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5647 OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:f32 5648 5649 # 256b versions 5650 5651 PATTERN : VV1 0x50 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5652 OPERANDS : REG0=GPR32_R():w:d REG1=YMM_B():r:qq:f32 5653 } 5654 5655 ############################################################################ 5656 { 5657 ICLASS : VPMOVMSKB 5658 EXCEPTIONS: avx-type-7 5659 CPL : 3 5660 CATEGORY : AVX 5661 EXTENSION : AVX 5662 PATTERN : VV1 0xD7 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5663 OPERANDS : REG0=GPR32_R():w:d:u32 REG1=XMM_B():r:dq:i8 5664 } 5665 5666 ############################################################################ 5667 5668 ############################################################################ 5669 # SX versions 5670 ############################################################################ 5671 5672 { 5673 ICLASS : VPMOVSXBW 5674 EXCEPTIONS: avx-type-5 5675 CPL : 3 5676 CATEGORY : AVX 5677 EXTENSION : AVX 5678 PATTERN : VV1 0x20 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5679 OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:q:i8 5680 PATTERN : VV1 0x20 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5681 OPERANDS : REG0=XMM_R():w:dq:i16 MEM0:r:q:i8 5682 } 5683 5684 ############################################################################ 5685 { 5686 ICLASS : VPMOVSXBD 5687 EXCEPTIONS: avx-type-5 5688 CPL : 3 5689 CATEGORY : AVX 5690 EXTENSION : AVX 5691 PATTERN : VV1 0x21 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5692 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:d:i8 5693 PATTERN : VV1 0x21 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5694 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:d:i8 5695 } 5696 ############################################################################ 5697 { 5698 ICLASS : VPMOVSXBQ 5699 EXCEPTIONS: avx-type-5 5700 CPL : 3 5701 CATEGORY : AVX 5702 EXTENSION : AVX 5703 PATTERN : VV1 0x22 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5704 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:w:i8 5705 PATTERN : VV1 0x22 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5706 OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:w:i8 5707 } 5708 ############################################################################ 5709 { 5710 ICLASS : VPMOVSXWD 5711 EXCEPTIONS: avx-type-5 5712 CPL : 3 5713 CATEGORY : AVX 5714 EXTENSION : AVX 5715 PATTERN : VV1 0x23 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5716 OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:q:i16 5717 PATTERN : VV1 0x23 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5718 OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:q:i16 5719 } 5720 ############################################################################ 5721 { 5722 ICLASS : VPMOVSXWQ 5723 EXCEPTIONS: avx-type-5 5724 CPL : 3 5725 CATEGORY : AVX 5726 EXTENSION : AVX 5727 PATTERN : VV1 0x24 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5728 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:d:i16 5729 PATTERN : VV1 0x24 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5730 OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:d:i16 5731 } 5732 ############################################################################ 5733 { 5734 ICLASS : VPMOVSXDQ 5735 EXCEPTIONS: avx-type-5 5736 CPL : 3 5737 CATEGORY : AVX 5738 EXTENSION : AVX 5739 PATTERN : VV1 0x25 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5740 OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:q:i32 5741 PATTERN : VV1 0x25 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5742 OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:q:i32 5743 } 5744 5745 5746 5747 5748 5749 ############################################################################ 5750 # ZX versions 5751 ############################################################################ 5752 5753 { 5754 ICLASS : VPMOVZXBW 5755 EXCEPTIONS: avx-type-5 5756 CPL : 3 5757 CATEGORY : AVX 5758 EXTENSION : AVX 5759 PATTERN : VV1 0x30 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5760 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:q:u8 5761 PATTERN : VV1 0x30 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5762 OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:q:u8 5763 } 5764 5765 ############################################################################ 5766 { 5767 ICLASS : VPMOVZXBD 5768 EXCEPTIONS: avx-type-5 5769 CPL : 3 5770 CATEGORY : AVX 5771 EXTENSION : AVX 5772 PATTERN : VV1 0x31 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5773 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u8 5774 PATTERN : VV1 0x31 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5775 OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u8 5776 } 5777 ############################################################################ 5778 { 5779 ICLASS : VPMOVZXBQ 5780 EXCEPTIONS: avx-type-5 5781 CPL : 3 5782 CATEGORY : AVX 5783 EXTENSION : AVX 5784 PATTERN : VV1 0x32 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5785 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:w:u8 5786 PATTERN : VV1 0x32 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5787 OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:w:u8 5788 } 5789 ############################################################################ 5790 { 5791 ICLASS : VPMOVZXWD 5792 EXCEPTIONS: avx-type-5 5793 CPL : 3 5794 CATEGORY : AVX 5795 EXTENSION : AVX 5796 PATTERN : VV1 0x33 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5797 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:q:u16 5798 PATTERN : VV1 0x33 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5799 OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:q:u16 5800 } 5801 ############################################################################ 5802 { 5803 ICLASS : VPMOVZXWQ 5804 EXCEPTIONS: avx-type-5 5805 CPL : 3 5806 CATEGORY : AVX 5807 EXTENSION : AVX 5808 PATTERN : VV1 0x34 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5809 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:d:u16 5810 PATTERN : VV1 0x34 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5811 OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:d:u16 5812 } 5813 ############################################################################ 5814 { 5815 ICLASS : VPMOVZXDQ 5816 EXCEPTIONS: avx-type-5 5817 CPL : 3 5818 CATEGORY : AVX 5819 EXTENSION : AVX 5820 PATTERN : VV1 0x35 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 5821 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u32 5822 PATTERN : VV1 0x35 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 5823 OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u32 5824 } 5825 5826 5827 5828 ############################################################################ 5829 ############################################################################ 5830 { 5831 ICLASS : VPEXTRB 5832 EXCEPTIONS: avx-type-5 5833 CPL : 3 5834 CATEGORY : AVX 5835 EXTENSION : AVX 5836 COMMENT: WIG 5837 PATTERN : VV1 0x14 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5838 OPERANDS : MEM0:w:b REG0=XMM_R():r:dq:u8 IMM0:r:b 5839 5840 PATTERN : VV1 0x14 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5841 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u8 IMM0:r:b 5842 } 5843 ############################################################################ 5844 { 5845 ICLASS : VPEXTRW 5846 EXCEPTIONS: avx-type-5 5847 CPL : 3 5848 CATEGORY : AVX 5849 EXTENSION : AVX 5850 COMMENT: WIG 5851 5852 PATTERN : VV1 0x15 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5853 OPERANDS : MEM0:w:w REG0=XMM_R():r:dq:u16 IMM0:r:b 5854 5855 PATTERN : VV1 0x15 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5856 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u16 IMM0:r:b 5857 IFORM : VPEXTRW_GPR32d_XMMdq_IMMb_15 5858 5859 # special C5 reg-only versions from SSE2: 5860 5861 PATTERN : VV1 0xC5 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5862 OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:u16 IMM0:r:b 5863 IFORM : VPEXTRW_GPR32d_XMMdq_IMMb_C5 5864 } 5865 ############################################################################ 5866 { 5867 ICLASS : VPEXTRQ 5868 EXCEPTIONS: avx-type-5 5869 CPL : 3 5870 CATEGORY : AVX 5871 EXTENSION : AVX 5872 PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5873 OPERANDS : MEM0:w:q REG0=XMM_R():r:dq:u64 IMM0:r:b 5874 PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5875 OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:dq:u64 IMM0:r:b 5876 } 5877 ############################################################################ 5878 { 5879 ICLASS : VPEXTRD 5880 EXCEPTIONS: avx-type-5 5881 CPL : 3 5882 CATEGORY : AVX 5883 EXTENSION : AVX 5884 COMMENT : SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode. Not modeled. 5885 5886 # 64b mode 5887 PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5888 OPERANDS : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b 5889 PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5890 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b 5891 5892 # not64b mode 5893 PATTERN : VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5894 OPERANDS : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b 5895 PATTERN : VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5896 OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b 5897 5898 } 5899 ############################################################################ 5900 5901 5902 5903 5904 5905 5906 { 5907 ICLASS : VPINSRB 5908 EXCEPTIONS: avx-type-5 5909 CPL : 3 5910 CATEGORY : AVX 5911 EXTENSION : AVX 5912 COMMENT: WIG 5913 PATTERN : VV1 0x20 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5914 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:b:u8 IMM0:r:b 5915 PATTERN : VV1 0x20 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5916 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b 5917 } 5918 5919 { 5920 ICLASS : VPINSRW 5921 EXCEPTIONS: avx-type-5 5922 CPL : 3 5923 CATEGORY : AVX 5924 EXTENSION : AVX 5925 COMMENT : WIG 5926 PATTERN : VV1 0xC4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5927 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:w:u16 IMM0:r:b 5928 5929 PATTERN : VV1 0xC4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5930 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b 5931 } 5932 5933 { 5934 ICLASS : VPINSRD 5935 EXCEPTIONS: avx-type-5 5936 CPL : 3 5937 CATEGORY : AVX 5938 EXTENSION : AVX 5939 COMMENT : SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode. Not modeled 5940 # 64b mode 5941 PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5942 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:d:u32 IMM0:r:b 5943 PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5944 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b 5945 5946 # 32b mode 5947 PATTERN : VV1 0x22 VL128 V66 V0F3A not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5948 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:d:u32 IMM0:r:b 5949 PATTERN : VV1 0x22 VL128 V66 V0F3A not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5950 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b 5951 } 5952 { 5953 ICLASS : VPINSRQ 5954 EXCEPTIONS: avx-type-5 5955 CPL : 3 5956 CATEGORY : AVX 5957 EXTENSION : AVX 5958 PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5959 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:q:u64 IMM0:r:b 5960 PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5961 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b 5962 } 5963 5964 ############################################################################ 5965 5966 5967 5968 5969 5970 { 5971 ICLASS : VPCMPESTRI 5972 EXCEPTIONS: avx-type-4 5973 CPL : 3 5974 CATEGORY : STTNI 5975 EXTENSION : AVX 5976 FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] 5977 5978 # outside of 64b mode, vex.w is ignored for this instr 5979 PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5980 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP 5981 PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5982 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP 5983 5984 # in 64b mode, vex.w changes the behavior for GPRs 5985 PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5986 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP 5987 PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5988 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP 5989 5990 PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 5991 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP 5992 PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 5993 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP 5994 } 5995 { 5996 ICLASS : VPCMPISTRI 5997 EXCEPTIONS: avx-type-4 5998 CPL : 3 5999 CATEGORY : STTNI 6000 EXTENSION : AVX 6001 FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] 6002 6003 # outside of 64b mode, vex.w is ignored for this instr 6004 PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 6005 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP 6006 PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 6007 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP 6008 6009 # in 64b mode, vex.w changes the behavior for GPRs 6010 PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 6011 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP 6012 PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 6013 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP 6014 6015 PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 6016 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RCX:w:SUPP 6017 PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 6018 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP 6019 } 6020 6021 { 6022 ICLASS : VPCMPESTRM 6023 EXCEPTIONS: avx-type-4 6024 CPL : 3 6025 CATEGORY : STTNI 6026 EXTENSION : AVX 6027 FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] 6028 6029 # outside of 64b mode, vex.w is ignored for this instr 6030 PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 6031 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP 6032 PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 6033 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP 6034 6035 # in 64b mode, vex.w changes the behavior for GPRs 6036 PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 6037 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP 6038 PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 6039 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP 6040 6041 PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 6042 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP 6043 PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 6044 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP 6045 } 6046 6047 { 6048 ICLASS : VPCMPISTRM 6049 EXCEPTIONS: avx-type-4 6050 CPL : 3 6051 CATEGORY : STTNI 6052 EXTENSION : AVX 6053 FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] 6054 PATTERN : VV1 0x62 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 6055 OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_XMM0:w:dq:SUPP 6056 PATTERN : VV1 0x62 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 6057 OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w:dq:SUPP 6058 } 6059 #################################################################################### 6060 6061 6062 6063 #################################################################################### 6064 { 6065 ICLASS : VMASKMOVDQU 6066 EXCEPTIONS: avx-type-4 6067 CPL : 3 6068 6069 CATEGORY : AVX 6070 EXTENSION : AVX 6071 ATTRIBUTES : maskop fixed_base0 NOTSX NONTEMPORAL 6072 PATTERN : VV1 0xF7 V0F V66 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6073 OPERANDS : REG0=XMM_R():r:dq:u8 REG1=XMM_B():r:dq:u8 MEM0:w:SUPP:dq:u8 BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP 6074 } 6075 6076 #################################################################################### 6077 { 6078 ICLASS : VLDMXCSR 6079 EXCEPTIONS: avx-type-5L 6080 CPL : 3 6081 CATEGORY : AVX 6082 EXTENSION : AVX 6083 ATTRIBUTES: MXCSR 6084 PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM() 6085 OPERANDS : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP 6086 } 6087 { 6088 ICLASS : VSTMXCSR 6089 EXCEPTIONS: avx-type-5 6090 CPL : 3 6091 CATEGORY : AVX 6092 EXTENSION : AVX 6093 ATTRIBUTES: MXCSR_RD 6094 PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM() 6095 OPERANDS : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP 6096 } 6097 ####################################################################################### 6098 6099 { 6100 ICLASS : VPBLENDVB 6101 EXCEPTIONS: avx-type-4 6102 CPL : 3 6103 CATEGORY : AVX 6104 EXTENSION : AVX 6105 6106 # W0 (modrm.rm memory op 2nd to last) 6107 PATTERN : VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 6108 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 REG2=XMM_SE():r:dq:i8 6109 6110 PATTERN : VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 6111 OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 REG3=XMM_SE():r:dq:i8 6112 } 6113 6114 { 6115 ICLASS : VBLENDVPD 6116 EXCEPTIONS: avx-type-4 6117 CPL : 3 6118 CATEGORY : AVX 6119 EXTENSION : AVX 6120 6121 # W0 (modrm.rm memory op 2nd to last) 6122 PATTERN : VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 6123 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:u64 6124 6125 PATTERN : VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 6126 OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:u64 6127 6128 PATTERN : VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 6129 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:u64 6130 6131 PATTERN : VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 6132 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:u64 6133 6134 } 6135 6136 { 6137 ICLASS : VBLENDVPS 6138 EXCEPTIONS: avx-type-4 6139 CPL : 3 6140 CATEGORY : AVX 6141 EXTENSION : AVX 6142 6143 # W0 (modrm.rm memory op 2nd to last) 6144 PATTERN : VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 6145 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:u32 6146 6147 PATTERN : VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 6148 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:u32 6149 6150 PATTERN : VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 6151 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:u32 6152 6153 PATTERN : VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 6154 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:u32 6155 6156 6157 } 6158 6159 ####################################################################################### 6160 6161 6162 6163 { 6164 ICLASS : VMOVNTDQA 6165 EXCEPTIONS: avx-type-1 6166 CPL : 3 6167 CATEGORY : DATAXFER 6168 EXTENSION : AVX 6169 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL 6170 6171 PATTERN : VV1 0x2A V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6172 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 6173 } 6174 6175 6176 6177 6178 6179 { 6180 ICLASS : VMOVNTDQ 6181 EXCEPTIONS: avx-type-1 6182 CPL : 3 6183 CATEGORY : DATAXFER 6184 EXTENSION : AVX 6185 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL 6186 PATTERN : VV1 0xE7 V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6187 OPERANDS : MEM0:w:dq:i32 REG0=XMM_R():r:dq:i32 6188 6189 } 6190 { 6191 ICLASS : VMOVNTPD 6192 EXCEPTIONS: avx-type-1 6193 CPL : 3 6194 CATEGORY : DATAXFER 6195 EXTENSION : AVX 6196 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL 6197 PATTERN : VV1 0x2B V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6198 OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 6199 6200 } 6201 { 6202 ICLASS : VMOVNTPS 6203 EXCEPTIONS: avx-type-1 6204 CPL : 3 6205 CATEGORY : DATAXFER 6206 EXTENSION : AVX 6207 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL 6208 PATTERN : VV1 0x2B VNP V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6209 OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 6210 6211 } 6212 6213 6214 6215 ###FILE: ./datafiles/avx/avx-movnt-store.txt 6216 6217 #BEGIN_LEGAL 6218 # 6219 #Copyright (c) 2016 Intel Corporation 6220 # 6221 # Licensed under the Apache License, Version 2.0 (the "License"); 6222 # you may not use this file except in compliance with the License. 6223 # You may obtain a copy of the License at 6224 # 6225 # http://www.apache.org/licenses/LICENSE-2.0 6226 # 6227 # Unless required by applicable law or agreed to in writing, software 6228 # distributed under the License is distributed on an "AS IS" BASIS, 6229 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 6230 # See the License for the specific language governing permissions and 6231 # limitations under the License. 6232 # 6233 #END_LEGAL 6234 AVX_INSTRUCTIONS():: 6235 6236 6237 { 6238 ICLASS : VMOVNTDQ 6239 EXCEPTIONS: avx-type-1 6240 CPL : 3 6241 CATEGORY : DATAXFER 6242 EXTENSION : AVX 6243 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL 6244 PATTERN : VV1 0xE7 V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6245 OPERANDS : MEM0:w:qq:i32 REG0=YMM_R():r:qq:i32 6246 6247 } 6248 { 6249 ICLASS : VMOVNTPD 6250 EXCEPTIONS: avx-type-1 6251 CPL : 3 6252 CATEGORY : DATAXFER 6253 EXTENSION : AVX 6254 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL 6255 PATTERN : VV1 0x2B V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6256 OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 6257 6258 } 6259 { 6260 ICLASS : VMOVNTPS 6261 EXCEPTIONS: avx-type-1 6262 CPL : 3 6263 CATEGORY : DATAXFER 6264 EXTENSION : AVX 6265 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL 6266 PATTERN : VV1 0x2B VNP V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6267 OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 6268 6269 } 6270 6271 6272 6273 ###FILE: ./datafiles/avx/avx-aes-isa.txt 6274 6275 #BEGIN_LEGAL 6276 # 6277 #Copyright (c) 2016 Intel Corporation 6278 # 6279 # Licensed under the Apache License, Version 2.0 (the "License"); 6280 # you may not use this file except in compliance with the License. 6281 # You may obtain a copy of the License at 6282 # 6283 # http://www.apache.org/licenses/LICENSE-2.0 6284 # 6285 # Unless required by applicable law or agreed to in writing, software 6286 # distributed under the License is distributed on an "AS IS" BASIS, 6287 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 6288 # See the License for the specific language governing permissions and 6289 # limitations under the License. 6290 # 6291 #END_LEGAL 6292 AVX_INSTRUCTIONS():: 6293 6294 { 6295 ICLASS : VAESKEYGENASSIST 6296 EXCEPTIONS: avx-type-4 6297 CPL : 3 6298 CATEGORY : AES 6299 EXTENSION : AVXAES 6300 PATTERN : VV1 0xDF VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 6301 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b 6302 PATTERN : VV1 0xDF VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 6303 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b 6304 } 6305 { 6306 ICLASS : VAESENC 6307 EXCEPTIONS: avx-type-4 6308 CPL : 3 6309 CATEGORY : AES 6310 EXTENSION : AVXAES 6311 PATTERN : VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 6312 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 6313 PATTERN : VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 6314 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 6315 } 6316 { 6317 ICLASS : VAESENCLAST 6318 EXCEPTIONS: avx-type-4 6319 CPL : 3 6320 CATEGORY : AES 6321 EXTENSION : AVXAES 6322 PATTERN : VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 6323 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 6324 PATTERN : VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 6325 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 6326 } 6327 { 6328 ICLASS : VAESDEC 6329 EXCEPTIONS: avx-type-4 6330 CPL : 3 6331 CATEGORY : AES 6332 EXTENSION : AVXAES 6333 PATTERN : VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 6334 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 6335 PATTERN : VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 6336 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 6337 } 6338 { 6339 ICLASS : VAESDECLAST 6340 EXCEPTIONS: avx-type-4 6341 CPL : 3 6342 CATEGORY : AES 6343 EXTENSION : AVXAES 6344 PATTERN : VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 6345 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 6346 PATTERN : VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 6347 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 6348 } 6349 { 6350 ICLASS : VAESIMC 6351 EXCEPTIONS: avx-type-4 6352 CPL : 3 6353 CATEGORY : AES 6354 EXTENSION : AVXAES 6355 PATTERN : VV1 0xDB VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6356 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq 6357 PATTERN : VV1 0xDB VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6358 OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq 6359 } 6360 6361 6362 6363 ###FILE: ./datafiles/avx/avx-pclmul-isa.txt 6364 6365 #BEGIN_LEGAL 6366 # 6367 #Copyright (c) 2016 Intel Corporation 6368 # 6369 # Licensed under the Apache License, Version 2.0 (the "License"); 6370 # you may not use this file except in compliance with the License. 6371 # You may obtain a copy of the License at 6372 # 6373 # http://www.apache.org/licenses/LICENSE-2.0 6374 # 6375 # Unless required by applicable law or agreed to in writing, software 6376 # distributed under the License is distributed on an "AS IS" BASIS, 6377 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 6378 # See the License for the specific language governing permissions and 6379 # limitations under the License. 6380 # 6381 #END_LEGAL 6382 AVX_INSTRUCTIONS():: 6383 { 6384 ICLASS : VPCLMULQDQ 6385 EXCEPTIONS: avx-type-4 6386 CPL : 3 6387 CATEGORY : AVX 6388 EXTENSION : AVX 6389 PATTERN : VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 UIMM8() 6390 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b 6391 PATTERN : VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 UIMM8() 6392 OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b 6393 } 6394 6395 6396 ###FILE: ./datafiles/ivbavx/fp16-isa.txt 6397 6398 #BEGIN_LEGAL 6399 # 6400 #Copyright (c) 2016 Intel Corporation 6401 # 6402 # Licensed under the Apache License, Version 2.0 (the "License"); 6403 # you may not use this file except in compliance with the License. 6404 # You may obtain a copy of the License at 6405 # 6406 # http://www.apache.org/licenses/LICENSE-2.0 6407 # 6408 # Unless required by applicable law or agreed to in writing, software 6409 # distributed under the License is distributed on an "AS IS" BASIS, 6410 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 6411 # See the License for the specific language governing permissions and 6412 # limitations under the License. 6413 # 6414 #END_LEGAL 6415 AVX_INSTRUCTIONS():: 6416 { 6417 ICLASS : VCVTPH2PS 6418 COMMENT : UPCONVERT -- NO IMMEDIATE 6419 CPL : 3 6420 CATEGORY : CONVERT 6421 EXTENSION : F16C 6422 ATTRIBUTES : MXCSR 6423 EXCEPTIONS: avx-type-11 6424 # 128b form 6425 6426 PATTERN : VV1 0x13 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 6427 OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:q:f16 6428 6429 PATTERN : VV1 0x13 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 6430 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:q:f16 6431 6432 6433 # 256b form 6434 6435 PATTERN : VV1 0x13 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 6436 OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:dq:f16 6437 6438 PATTERN : VV1 0x13 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 6439 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f16 6440 } 6441 6442 6443 { 6444 ICLASS : VCVTPS2PH 6445 COMMENT : DOWNCONVERT -- HAS IMMEDIATE 6446 CPL : 3 6447 CATEGORY : CONVERT 6448 EXTENSION : F16C 6449 ATTRIBUTES : MXCSR 6450 EXCEPTIONS: avx-type-11 6451 # 128b imm8 form 6452 6453 PATTERN : VV1 0x1D VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0 6454 OPERANDS : MEM0:w:q:f16 REG0=XMM_R():r:dq:f32 IMM0:r:b 6455 6456 PATTERN : VV1 0x1D VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0 6457 OPERANDS : REG0=XMM_B():w:q:f16 REG1=XMM_R():r:dq:f32 IMM0:r:b 6458 6459 # 256b imm8 form 6460 6461 PATTERN : VV1 0x1D VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0 6462 OPERANDS : MEM0:w:dq:f16 REG0=YMM_R():r:qq:f32 IMM0:r:b 6463 6464 PATTERN : VV1 0x1D VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0 6465 OPERANDS : REG0=XMM_B():w:dq:f16 REG1=YMM_R():r:qq:f32 IMM0:r:b 6466 6467 } 6468 6469 6470 6471 ###FILE: ./datafiles/avxhsw/gather-isa.txt 6472 6473 #BEGIN_LEGAL 6474 # 6475 #Copyright (c) 2016 Intel Corporation 6476 # 6477 # Licensed under the Apache License, Version 2.0 (the "License"); 6478 # you may not use this file except in compliance with the License. 6479 # You may obtain a copy of the License at 6480 # 6481 # http://www.apache.org/licenses/LICENSE-2.0 6482 # 6483 # Unless required by applicable law or agreed to in writing, software 6484 # distributed under the License is distributed on an "AS IS" BASIS, 6485 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 6486 # See the License for the specific language governing permissions and 6487 # limitations under the License. 6488 # 6489 #END_LEGAL 6490 AVX_INSTRUCTIONS():: 6491 6492 6493 # DEST in MODRM.REG 6494 # BASE in SIB.base 6495 # INDEX in SIB.index 6496 # MASK in VEX.VVVV -- NOTE mask is a signed integer!!! 6497 6498 # VL = 128 VL = 256 6499 # dest/mask index memsz dest/mask index memsz 6500 # qps/qd xmm xmm 2*32=64b xmm* ymm* 4*32=128b 6501 # dps/dd xmm xmm 4*32=128b ymm ymm 8*32=256b 6502 # dpd/dq xmm xmm 2*64=128b ymm* xmm* 4*64=256b 6503 # qpd/qq xmm xmm 2*64=128b ymm ymm 4*64=256b 6504 6505 6506 6507 { 6508 ICLASS : VGATHERDPD 6509 CPL : 3 6510 CATEGORY : AVX2GATHER 6511 EXTENSION : AVX2GATHER 6512 ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED 6513 EXCEPTIONS: avx-type-12 6514 6515 6516 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 6517 PATTERN : VV1 0x92 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 6518 OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:q:f64 REG1=YMM_N():rw:qq:i64 6519 IFORM: VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 6520 6521 # VL = 128 - index, mask and dest are all XMMs 6522 PATTERN : VV1 0x92 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 6523 OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:q:f64 REG1=XMM_N():rw:dq:i64 6524 IFORM: VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 6525 6526 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 6527 } 6528 { 6529 ICLASS : VGATHERDPS 6530 CPL : 3 6531 CATEGORY : AVX2GATHER 6532 EXTENSION : AVX2GATHER 6533 ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED 6534 EXCEPTIONS: avx-type-12 6535 6536 6537 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 6538 PATTERN : VV1 0x92 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 6539 OPERANDS : REG0=YMM_R():crw:qq:f32 MEM0:r:d:f32 REG1=YMM_N():rw:qq:i32 6540 IFORM: VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 6541 6542 # VL = 128 - index, mask and dest are all XMMs 6543 PATTERN : VV1 0x92 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 6544 OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:d:f32 REG1=XMM_N():rw:dq:i32 6545 IFORM: VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 6546 6547 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 6548 } 6549 { 6550 ICLASS : VGATHERQPD 6551 CPL : 3 6552 CATEGORY : AVX2GATHER 6553 EXTENSION : AVX2GATHER 6554 ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED 6555 EXCEPTIONS: avx-type-12 6556 6557 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 6558 PATTERN : VV1 0x93 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 6559 OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:q:f64 REG1=YMM_N():rw:qq:i64 6560 IFORM: VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 6561 6562 # VL = 128 - index, mask and dest are all XMMs 6563 PATTERN : VV1 0x93 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 6564 OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:q:f64 REG1=XMM_N():rw:dq:i64 6565 IFORM: VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 6566 6567 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 6568 } 6569 { 6570 ICLASS : VGATHERQPS 6571 CPL : 3 6572 CATEGORY : AVX2GATHER 6573 EXTENSION : AVX2GATHER 6574 ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED 6575 EXCEPTIONS: avx-type-12 6576 6577 6578 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 6579 PATTERN : VV1 0x93 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 6580 OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:d:f32 REG1=XMM_N():rw:dq:i32 6581 IFORM: VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 6582 6583 # VL = 128 - index, mask and dest are all XMMs 6584 PATTERN : VV1 0x93 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 6585 OPERANDS : REG0=XMM_R():crw:q:f32 MEM0:r:d:f32 REG1=XMM_N():rw:q:i32 6586 IFORM: VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 6587 6588 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 6589 } 6590 6591 { 6592 ICLASS : VPGATHERDQ 6593 CPL : 3 6594 CATEGORY : AVX2GATHER 6595 EXTENSION : AVX2GATHER 6596 ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED 6597 EXCEPTIONS: avx-type-12 6598 6599 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 6600 PATTERN : VV1 0x90 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 6601 OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:q:u64 REG1=YMM_N():rw:qq:i64 6602 IFORM: VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 6603 6604 # VL = 128 - index, mask and dest are all XMMs 6605 PATTERN : VV1 0x90 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 6606 OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:q:u64 REG1=XMM_N():rw:dq:i64 6607 IFORM: VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 6608 6609 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 6610 } 6611 { 6612 ICLASS : VPGATHERDD 6613 CPL : 3 6614 CATEGORY : AVX2GATHER 6615 EXTENSION : AVX2GATHER 6616 ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED 6617 EXCEPTIONS: avx-type-12 6618 6619 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 6620 PATTERN : VV1 0x90 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 6621 OPERANDS : REG0=YMM_R():crw:qq:u32 MEM0:r:d:u32 REG1=YMM_N():rw:qq:i32 6622 IFORM: VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 6623 6624 # VL = 128 - index, mask and dest are all XMMs 6625 PATTERN : VV1 0x90 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 6626 OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:d:u32 REG1=XMM_N():rw:dq:i32 6627 IFORM: VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 6628 6629 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 6630 } 6631 { 6632 ICLASS : VPGATHERQQ 6633 CPL : 3 6634 CATEGORY : AVX2GATHER 6635 EXTENSION : AVX2GATHER 6636 ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED 6637 EXCEPTIONS: avx-type-12 6638 6639 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 6640 PATTERN : VV1 0x91 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 6641 OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:q:u64 REG1=YMM_N():rw:qq:i64 6642 IFORM: VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 6643 6644 # VL = 128 - index, mask and dest are all XMMs 6645 PATTERN : VV1 0x91 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 6646 OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:q:u64 REG1=XMM_N():rw:dq:i64 6647 IFORM: VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 6648 6649 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 6650 } 6651 { 6652 ICLASS : VPGATHERQD 6653 CPL : 3 6654 CATEGORY : AVX2GATHER 6655 EXTENSION : AVX2GATHER 6656 ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED 6657 EXCEPTIONS: avx-type-12 6658 6659 # VL = 256 - when data/mask differ from index size see asterisks in above chart. 6660 PATTERN : VV1 0x91 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 6661 OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:d:u32 REG1=XMM_N():rw:dq:i32 6662 IFORM: VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 6663 6664 # VL = 128 - index, mask and dest are all XMMs 6665 PATTERN : VV1 0x91 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 6666 OPERANDS : REG0=XMM_R():crw:q:u32 MEM0:r:d:u32 REG1=XMM_N():rw:q:i32 6667 IFORM: VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 6668 6669 COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz 6670 } 6671 6672 6673 6674 ###FILE: ./datafiles/avxhsw/hsw-int256-isa.txt 6675 6676 #BEGIN_LEGAL 6677 # 6678 #Copyright (c) 2017 Intel Corporation 6679 # 6680 # Licensed under the Apache License, Version 2.0 (the "License"); 6681 # you may not use this file except in compliance with the License. 6682 # You may obtain a copy of the License at 6683 # 6684 # http://www.apache.org/licenses/LICENSE-2.0 6685 # 6686 # Unless required by applicable law or agreed to in writing, software 6687 # distributed under the License is distributed on an "AS IS" BASIS, 6688 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 6689 # See the License for the specific language governing permissions and 6690 # limitations under the License. 6691 # 6692 #END_LEGAL 6693 AVX_INSTRUCTIONS():: 6694 6695 6696 { 6697 ICLASS : VPABSB 6698 CPL : 3 6699 CATEGORY : AVX2 6700 EXTENSION : AVX2 6701 EXCEPTIONS: avx-type-4 6702 PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6703 OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:qq:i8 6704 6705 PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6706 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_B():r:qq:i8 6707 } 6708 { 6709 ICLASS : VPABSW 6710 CPL : 3 6711 CATEGORY : AVX2 6712 EXTENSION : AVX2 6713 EXCEPTIONS: avx-type-4 6714 PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6715 OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:i16 6716 6717 PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6718 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:i16 6719 } 6720 { 6721 ICLASS : VPABSD 6722 CPL : 3 6723 CATEGORY : AVX2 6724 EXTENSION : AVX2 6725 EXCEPTIONS: avx-type-4 6726 PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6727 OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:i32 6728 6729 PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6730 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:i32 6731 } 6732 6733 6734 6735 6736 6737 6738 6739 6740 6741 { 6742 ICLASS : VPACKSSWB 6743 CPL : 3 6744 CATEGORY : AVX2 6745 EXTENSION : AVX2 6746 EXCEPTIONS: avx-type-4 6747 PATTERN : VV1 0x63 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6748 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 6749 6750 PATTERN : VV1 0x63 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6751 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 6752 } 6753 { 6754 ICLASS : VPACKSSDW 6755 CPL : 3 6756 CATEGORY : AVX2 6757 EXTENSION : AVX2 6758 EXCEPTIONS: avx-type-4 6759 PATTERN : VV1 0x6B VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6760 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 6761 6762 PATTERN : VV1 0x6B VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6763 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 6764 } 6765 { 6766 ICLASS : VPACKUSWB 6767 CPL : 3 6768 CATEGORY : AVX2 6769 EXTENSION : AVX2 6770 EXCEPTIONS: avx-type-4 6771 PATTERN : VV1 0x67 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6772 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 6773 6774 PATTERN : VV1 0x67 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6775 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 6776 } 6777 { 6778 ICLASS : VPACKUSDW 6779 CPL : 3 6780 CATEGORY : AVX2 6781 EXTENSION : AVX2 6782 EXCEPTIONS: avx-type-4 6783 PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6784 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 6785 6786 PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6787 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 6788 } 6789 6790 { 6791 ICLASS : VPSLLW 6792 CPL : 3 6793 CATEGORY : AVX2 6794 EXTENSION : AVX2 6795 EXCEPTIONS: avx-type-4 6796 PATTERN : VV1 0xF1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6797 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 6798 6799 PATTERN : VV1 0xF1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6800 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 6801 } 6802 { 6803 ICLASS : VPSLLD 6804 CPL : 3 6805 CATEGORY : AVX2 6806 EXTENSION : AVX2 6807 EXCEPTIONS: avx-type-4 6808 PATTERN : VV1 0xF2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6809 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 6810 6811 PATTERN : VV1 0xF2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6812 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 6813 } 6814 { 6815 ICLASS : VPSLLQ 6816 CPL : 3 6817 CATEGORY : AVX2 6818 EXTENSION : AVX2 6819 EXCEPTIONS: avx-type-4 6820 PATTERN : VV1 0xF3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6821 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 6822 6823 PATTERN : VV1 0xF3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6824 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 6825 } 6826 6827 { 6828 ICLASS : VPSRLW 6829 CPL : 3 6830 CATEGORY : AVX2 6831 EXTENSION : AVX2 6832 EXCEPTIONS: avx-type-4 6833 PATTERN : VV1 0xD1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6834 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 6835 6836 PATTERN : VV1 0xD1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6837 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 6838 } 6839 { 6840 ICLASS : VPSRLD 6841 CPL : 3 6842 CATEGORY : AVX2 6843 EXTENSION : AVX2 6844 EXCEPTIONS: avx-type-4 6845 PATTERN : VV1 0xD2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6846 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 6847 6848 PATTERN : VV1 0xD2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6849 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 6850 } 6851 { 6852 ICLASS : VPSRLQ 6853 CPL : 3 6854 CATEGORY : AVX2 6855 EXTENSION : AVX2 6856 EXCEPTIONS: avx-type-4 6857 PATTERN : VV1 0xD3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6858 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 6859 6860 PATTERN : VV1 0xD3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6861 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 6862 } 6863 6864 { 6865 ICLASS : VPSRAW 6866 CPL : 3 6867 CATEGORY : AVX2 6868 EXTENSION : AVX2 6869 EXCEPTIONS: avx-type-4 6870 PATTERN : VV1 0xE1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6871 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:dq:u64 6872 6873 PATTERN : VV1 0xE1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6874 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=XMM_B():r:q:u64 6875 } 6876 { 6877 ICLASS : VPSRAD 6878 CPL : 3 6879 CATEGORY : AVX2 6880 EXTENSION : AVX2 6881 EXCEPTIONS: avx-type-4 6882 PATTERN : VV1 0xE2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6883 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:dq:u64 6884 6885 PATTERN : VV1 0xE2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6886 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=XMM_B():r:q:u64 6887 } 6888 6889 6890 { 6891 ICLASS : VPADDB 6892 CPL : 3 6893 CATEGORY : AVX2 6894 EXTENSION : AVX2 6895 EXCEPTIONS: avx-type-4 6896 PATTERN : VV1 0xFC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6897 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 6898 6899 PATTERN : VV1 0xFC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6900 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 6901 } 6902 { 6903 ICLASS : VPADDW 6904 CPL : 3 6905 CATEGORY : AVX2 6906 EXTENSION : AVX2 6907 EXCEPTIONS: avx-type-4 6908 PATTERN : VV1 0xFD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6909 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 6910 6911 PATTERN : VV1 0xFD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6912 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 6913 } 6914 { 6915 ICLASS : VPADDD 6916 CPL : 3 6917 CATEGORY : AVX2 6918 EXTENSION : AVX2 6919 EXCEPTIONS: avx-type-4 6920 PATTERN : VV1 0xFE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6921 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 6922 6923 PATTERN : VV1 0xFE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6924 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 6925 } 6926 { 6927 ICLASS : VPADDQ 6928 CPL : 3 6929 CATEGORY : AVX2 6930 EXTENSION : AVX2 6931 EXCEPTIONS: avx-type-4 6932 PATTERN : VV1 0xD4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6933 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 6934 6935 PATTERN : VV1 0xD4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6936 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 6937 } 6938 6939 { 6940 ICLASS : VPADDSB 6941 CPL : 3 6942 CATEGORY : AVX2 6943 EXTENSION : AVX2 6944 EXCEPTIONS: avx-type-4 6945 PATTERN : VV1 0xEC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6946 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 6947 6948 PATTERN : VV1 0xEC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6949 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 6950 } 6951 { 6952 ICLASS : VPADDSW 6953 CPL : 3 6954 CATEGORY : AVX2 6955 EXTENSION : AVX2 6956 EXCEPTIONS: avx-type-4 6957 PATTERN : VV1 0xED VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6958 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 6959 6960 PATTERN : VV1 0xED VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6961 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 6962 } 6963 6964 { 6965 ICLASS : VPADDUSB 6966 CPL : 3 6967 CATEGORY : AVX2 6968 EXTENSION : AVX2 6969 EXCEPTIONS: avx-type-4 6970 PATTERN : VV1 0xDC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6971 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 6972 6973 PATTERN : VV1 0xDC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6974 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 6975 } 6976 { 6977 ICLASS : VPADDUSW 6978 CPL : 3 6979 CATEGORY : AVX2 6980 EXTENSION : AVX2 6981 EXCEPTIONS: avx-type-4 6982 PATTERN : VV1 0xDD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6983 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 6984 6985 PATTERN : VV1 0xDD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6986 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 6987 } 6988 6989 { 6990 ICLASS : VPAVGB 6991 CPL : 3 6992 CATEGORY : AVX2 6993 EXTENSION : AVX2 6994 EXCEPTIONS: avx-type-4 6995 PATTERN : VV1 0xE0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 6996 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 6997 6998 PATTERN : VV1 0xE0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 6999 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 7000 } 7001 { 7002 ICLASS : VPAVGW 7003 CPL : 3 7004 CATEGORY : AVX2 7005 EXTENSION : AVX2 7006 EXCEPTIONS: avx-type-4 7007 PATTERN : VV1 0xE3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7008 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 7009 7010 PATTERN : VV1 0xE3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7011 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 7012 } 7013 7014 7015 { 7016 ICLASS : VPCMPEQB 7017 CPL : 3 7018 CATEGORY : AVX2 7019 EXTENSION : AVX2 7020 EXCEPTIONS: avx-type-4 7021 PATTERN : VV1 0x74 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7022 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 7023 7024 PATTERN : VV1 0x74 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7025 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 7026 } 7027 { 7028 ICLASS : VPCMPEQW 7029 CPL : 3 7030 CATEGORY : AVX2 7031 EXTENSION : AVX2 7032 EXCEPTIONS: avx-type-4 7033 PATTERN : VV1 0x75 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7034 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 7035 7036 PATTERN : VV1 0x75 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7037 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 7038 } 7039 { 7040 ICLASS : VPCMPEQD 7041 CPL : 3 7042 CATEGORY : AVX2 7043 EXTENSION : AVX2 7044 EXCEPTIONS: avx-type-4 7045 PATTERN : VV1 0x76 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7046 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 7047 7048 PATTERN : VV1 0x76 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7049 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 7050 } 7051 { 7052 ICLASS : VPCMPEQQ 7053 CPL : 3 7054 CATEGORY : AVX2 7055 EXTENSION : AVX2 7056 EXCEPTIONS: avx-type-4 7057 PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7058 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 7059 7060 PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7061 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 7062 } 7063 7064 { 7065 ICLASS : VPCMPGTB 7066 CPL : 3 7067 CATEGORY : AVX2 7068 EXTENSION : AVX2 7069 EXCEPTIONS: avx-type-4 7070 PATTERN : VV1 0x64 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7071 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 7072 7073 PATTERN : VV1 0x64 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7074 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 7075 } 7076 { 7077 ICLASS : VPCMPGTW 7078 CPL : 3 7079 CATEGORY : AVX2 7080 EXTENSION : AVX2 7081 EXCEPTIONS: avx-type-4 7082 PATTERN : VV1 0x65 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7083 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7084 7085 PATTERN : VV1 0x65 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7086 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7087 } 7088 { 7089 ICLASS : VPCMPGTD 7090 CPL : 3 7091 CATEGORY : AVX2 7092 EXTENSION : AVX2 7093 EXCEPTIONS: avx-type-4 7094 PATTERN : VV1 0x66 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7095 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 7096 7097 PATTERN : VV1 0x66 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7098 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 7099 } 7100 { 7101 ICLASS : VPCMPGTQ 7102 CPL : 3 7103 CATEGORY : AVX2 7104 EXTENSION : AVX2 7105 EXCEPTIONS: avx-type-4 7106 PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7107 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 7108 7109 PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7110 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 7111 } 7112 7113 7114 { 7115 ICLASS : VPHADDW 7116 CPL : 3 7117 CATEGORY : AVX2 7118 EXTENSION : AVX2 7119 EXCEPTIONS: avx-type-4 7120 PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7121 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7122 7123 PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7124 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7125 } 7126 { 7127 ICLASS : VPHADDD 7128 CPL : 3 7129 CATEGORY : AVX2 7130 EXTENSION : AVX2 7131 EXCEPTIONS: avx-type-4 7132 PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7133 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 7134 7135 PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7136 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 7137 } 7138 { 7139 ICLASS : VPHADDSW 7140 CPL : 3 7141 CATEGORY : AVX2 7142 EXTENSION : AVX2 7143 EXCEPTIONS: avx-type-4 7144 PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7145 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7146 7147 PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7148 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7149 } 7150 { 7151 ICLASS : VPHSUBW 7152 CPL : 3 7153 CATEGORY : AVX2 7154 EXTENSION : AVX2 7155 EXCEPTIONS: avx-type-4 7156 PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7157 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7158 7159 PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7160 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7161 } 7162 { 7163 ICLASS : VPHSUBD 7164 CPL : 3 7165 CATEGORY : AVX2 7166 EXTENSION : AVX2 7167 EXCEPTIONS: avx-type-4 7168 PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7169 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 7170 7171 PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7172 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 7173 } 7174 { 7175 ICLASS : VPHSUBSW 7176 CPL : 3 7177 CATEGORY : AVX2 7178 EXTENSION : AVX2 7179 EXCEPTIONS: avx-type-4 7180 PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7181 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7182 7183 PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7184 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7185 } 7186 7187 { 7188 ICLASS : VPMADDWD 7189 CPL : 3 7190 CATEGORY : AVX2 7191 EXTENSION : AVX2 7192 EXCEPTIONS: avx-type-4 7193 PATTERN : VV1 0xF5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7194 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7195 7196 PATTERN : VV1 0xF5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7197 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7198 } 7199 { 7200 ICLASS : VPMADDUBSW 7201 CPL : 3 7202 CATEGORY : AVX2 7203 EXTENSION : AVX2 7204 EXCEPTIONS: avx-type-4 7205 PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7206 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:i8 7207 7208 PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7209 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:i8 7210 } 7211 7212 { 7213 ICLASS : VPMAXSB 7214 CPL : 3 7215 CATEGORY : AVX2 7216 EXTENSION : AVX2 7217 EXCEPTIONS: avx-type-4 7218 PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7219 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 7220 7221 PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7222 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 7223 } 7224 { 7225 ICLASS : VPMAXSW 7226 CPL : 3 7227 CATEGORY : AVX2 7228 EXTENSION : AVX2 7229 EXCEPTIONS: avx-type-4 7230 PATTERN : VV1 0xEE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7231 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7232 7233 PATTERN : VV1 0xEE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7234 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7235 } 7236 { 7237 ICLASS : VPMAXSD 7238 CPL : 3 7239 CATEGORY : AVX2 7240 EXTENSION : AVX2 7241 EXCEPTIONS: avx-type-4 7242 PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7243 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 7244 7245 PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7246 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 7247 } 7248 7249 { 7250 ICLASS : VPMAXUB 7251 CPL : 3 7252 CATEGORY : AVX2 7253 EXTENSION : AVX2 7254 EXCEPTIONS: avx-type-4 7255 PATTERN : VV1 0xDE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7256 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 7257 7258 PATTERN : VV1 0xDE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7259 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 7260 } 7261 { 7262 ICLASS : VPMAXUW 7263 CPL : 3 7264 CATEGORY : AVX2 7265 EXTENSION : AVX2 7266 EXCEPTIONS: avx-type-4 7267 PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7268 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 7269 7270 PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7271 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 7272 } 7273 { 7274 ICLASS : VPMAXUD 7275 CPL : 3 7276 CATEGORY : AVX2 7277 EXTENSION : AVX2 7278 EXCEPTIONS: avx-type-4 7279 PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7280 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 7281 7282 PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7283 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 7284 } 7285 7286 { 7287 ICLASS : VPMINSB 7288 CPL : 3 7289 CATEGORY : AVX2 7290 EXTENSION : AVX2 7291 EXCEPTIONS: avx-type-4 7292 PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7293 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 7294 7295 PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7296 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 7297 } 7298 { 7299 ICLASS : VPMINSW 7300 CPL : 3 7301 CATEGORY : AVX2 7302 EXTENSION : AVX2 7303 EXCEPTIONS: avx-type-4 7304 PATTERN : VV1 0xEA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7305 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7306 7307 PATTERN : VV1 0xEA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7308 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7309 } 7310 { 7311 ICLASS : VPMINSD 7312 CPL : 3 7313 CATEGORY : AVX2 7314 EXTENSION : AVX2 7315 EXCEPTIONS: avx-type-4 7316 PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7317 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 7318 7319 PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7320 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 7321 } 7322 7323 { 7324 ICLASS : VPMINUB 7325 CPL : 3 7326 CATEGORY : AVX2 7327 EXTENSION : AVX2 7328 EXCEPTIONS: avx-type-4 7329 PATTERN : VV1 0xDA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7330 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 7331 7332 PATTERN : VV1 0xDA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7333 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 7334 } 7335 { 7336 ICLASS : VPMINUW 7337 CPL : 3 7338 CATEGORY : AVX2 7339 EXTENSION : AVX2 7340 EXCEPTIONS: avx-type-4 7341 PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7342 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 7343 7344 PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7345 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 7346 } 7347 { 7348 ICLASS : VPMINUD 7349 CPL : 3 7350 CATEGORY : AVX2 7351 EXTENSION : AVX2 7352 EXCEPTIONS: avx-type-4 7353 PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7354 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 7355 7356 PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7357 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 7358 } 7359 7360 { 7361 ICLASS : VPMULHUW 7362 CPL : 3 7363 CATEGORY : AVX2 7364 EXTENSION : AVX2 7365 EXCEPTIONS: avx-type-4 7366 PATTERN : VV1 0xE4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7367 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 7368 7369 PATTERN : VV1 0xE4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7370 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 7371 } 7372 { 7373 ICLASS : VPMULHRSW 7374 CPL : 3 7375 CATEGORY : AVX2 7376 EXTENSION : AVX2 7377 EXCEPTIONS: avx-type-4 7378 PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7379 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7380 7381 PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7382 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7383 } 7384 7385 { 7386 ICLASS : VPMULHW 7387 CPL : 3 7388 CATEGORY : AVX2 7389 EXTENSION : AVX2 7390 EXCEPTIONS: avx-type-4 7391 PATTERN : VV1 0xE5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7392 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7393 7394 PATTERN : VV1 0xE5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7395 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7396 } 7397 { 7398 ICLASS : VPMULLW 7399 CPL : 3 7400 CATEGORY : AVX2 7401 EXTENSION : AVX2 7402 EXCEPTIONS: avx-type-4 7403 PATTERN : VV1 0xD5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7404 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7405 7406 PATTERN : VV1 0xD5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7407 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7408 } 7409 { 7410 ICLASS : VPMULLD 7411 CPL : 3 7412 CATEGORY : AVX2 7413 EXTENSION : AVX2 7414 EXCEPTIONS: avx-type-4 7415 PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7416 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 7417 7418 PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7419 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 7420 } 7421 7422 { 7423 ICLASS : VPMULUDQ 7424 CPL : 3 7425 CATEGORY : AVX2 7426 EXTENSION : AVX2 7427 EXCEPTIONS: avx-type-4 7428 PATTERN : VV1 0xF4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7429 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 7430 7431 PATTERN : VV1 0xF4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7432 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 7433 } 7434 { 7435 ICLASS : VPMULDQ 7436 CPL : 3 7437 CATEGORY : AVX2 7438 EXTENSION : AVX2 7439 EXCEPTIONS: avx-type-4 7440 PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7441 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 7442 7443 PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7444 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 7445 } 7446 7447 { 7448 ICLASS : VPSADBW 7449 CPL : 3 7450 CATEGORY : AVX2 7451 EXTENSION : AVX2 7452 EXCEPTIONS: avx-type-4 7453 PATTERN : VV1 0xF6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7454 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 7455 7456 PATTERN : VV1 0xF6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7457 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 7458 } 7459 { 7460 ICLASS : VPSHUFB 7461 CPL : 3 7462 CATEGORY : AVX2 7463 EXTENSION : AVX2 7464 EXCEPTIONS: avx-type-4 7465 PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7466 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 7467 7468 PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7469 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 7470 } 7471 7472 { 7473 ICLASS : VPSIGNB 7474 CPL : 3 7475 CATEGORY : AVX2 7476 EXTENSION : AVX2 7477 EXCEPTIONS: avx-type-4 7478 PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7479 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 7480 7481 PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7482 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 7483 } 7484 { 7485 ICLASS : VPSIGNW 7486 CPL : 3 7487 CATEGORY : AVX2 7488 EXTENSION : AVX2 7489 EXCEPTIONS: avx-type-4 7490 PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7491 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7492 7493 PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7494 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7495 } 7496 { 7497 ICLASS : VPSIGND 7498 CPL : 3 7499 CATEGORY : AVX2 7500 EXTENSION : AVX2 7501 EXCEPTIONS: avx-type-4 7502 PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7503 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 7504 7505 PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7506 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 7507 } 7508 7509 7510 { 7511 ICLASS : VPSUBSB 7512 CPL : 3 7513 CATEGORY : AVX2 7514 EXTENSION : AVX2 7515 EXCEPTIONS: avx-type-4 7516 PATTERN : VV1 0xE8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7517 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 7518 7519 PATTERN : VV1 0xE8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7520 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 7521 } 7522 { 7523 ICLASS : VPSUBSW 7524 CPL : 3 7525 CATEGORY : AVX2 7526 EXTENSION : AVX2 7527 EXCEPTIONS: avx-type-4 7528 PATTERN : VV1 0xE9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7529 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7530 7531 PATTERN : VV1 0xE9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7532 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7533 } 7534 7535 { 7536 ICLASS : VPSUBUSB 7537 CPL : 3 7538 CATEGORY : AVX2 7539 EXTENSION : AVX2 7540 EXCEPTIONS: avx-type-4 7541 PATTERN : VV1 0xD8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7542 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 7543 7544 PATTERN : VV1 0xD8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7545 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 7546 } 7547 { 7548 ICLASS : VPSUBUSW 7549 CPL : 3 7550 CATEGORY : AVX2 7551 EXTENSION : AVX2 7552 EXCEPTIONS: avx-type-4 7553 PATTERN : VV1 0xD9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7554 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 7555 7556 PATTERN : VV1 0xD9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7557 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 7558 } 7559 7560 { 7561 ICLASS : VPSUBB 7562 CPL : 3 7563 CATEGORY : AVX2 7564 EXTENSION : AVX2 7565 EXCEPTIONS: avx-type-4 7566 PATTERN : VV1 0xF8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7567 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 7568 7569 PATTERN : VV1 0xF8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7570 OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 7571 } 7572 { 7573 ICLASS : VPSUBW 7574 CPL : 3 7575 CATEGORY : AVX2 7576 EXTENSION : AVX2 7577 EXCEPTIONS: avx-type-4 7578 PATTERN : VV1 0xF9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7579 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 7580 7581 PATTERN : VV1 0xF9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7582 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 7583 } 7584 { 7585 ICLASS : VPSUBD 7586 CPL : 3 7587 CATEGORY : AVX2 7588 EXTENSION : AVX2 7589 EXCEPTIONS: avx-type-4 7590 PATTERN : VV1 0xFA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7591 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 7592 7593 PATTERN : VV1 0xFA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7594 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 7595 } 7596 { 7597 ICLASS : VPSUBQ 7598 CPL : 3 7599 CATEGORY : AVX2 7600 EXTENSION : AVX2 7601 EXCEPTIONS: avx-type-4 7602 PATTERN : VV1 0xFB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7603 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 7604 7605 PATTERN : VV1 0xFB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7606 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 7607 } 7608 7609 { 7610 ICLASS : VPUNPCKHBW 7611 CPL : 3 7612 CATEGORY : AVX2 7613 EXTENSION : AVX2 7614 EXCEPTIONS: avx-type-4 7615 PATTERN : VV1 0x68 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7616 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 7617 7618 PATTERN : VV1 0x68 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7619 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 7620 } 7621 { 7622 ICLASS : VPUNPCKHWD 7623 CPL : 3 7624 CATEGORY : AVX2 7625 EXTENSION : AVX2 7626 EXCEPTIONS: avx-type-4 7627 PATTERN : VV1 0x69 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7628 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 7629 7630 PATTERN : VV1 0x69 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7631 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 7632 } 7633 { 7634 ICLASS : VPUNPCKHDQ 7635 CPL : 3 7636 CATEGORY : AVX2 7637 EXTENSION : AVX2 7638 EXCEPTIONS: avx-type-4 7639 PATTERN : VV1 0x6A VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7640 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 7641 7642 PATTERN : VV1 0x6A VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7643 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 7644 } 7645 { 7646 ICLASS : VPUNPCKHQDQ 7647 CPL : 3 7648 CATEGORY : AVX2 7649 EXTENSION : AVX2 7650 EXCEPTIONS: avx-type-4 7651 PATTERN : VV1 0x6D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7652 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 7653 7654 PATTERN : VV1 0x6D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7655 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 7656 } 7657 7658 { 7659 ICLASS : VPUNPCKLBW 7660 CPL : 3 7661 CATEGORY : AVX2 7662 EXTENSION : AVX2 7663 EXCEPTIONS: avx-type-4 7664 PATTERN : VV1 0x60 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7665 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 7666 7667 PATTERN : VV1 0x60 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7668 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 7669 } 7670 { 7671 ICLASS : VPUNPCKLWD 7672 CPL : 3 7673 CATEGORY : AVX2 7674 EXTENSION : AVX2 7675 EXCEPTIONS: avx-type-4 7676 PATTERN : VV1 0x61 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7677 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 7678 7679 PATTERN : VV1 0x61 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7680 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 7681 } 7682 { 7683 ICLASS : VPUNPCKLDQ 7684 CPL : 3 7685 CATEGORY : AVX2 7686 EXTENSION : AVX2 7687 EXCEPTIONS: avx-type-4 7688 PATTERN : VV1 0x62 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7689 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 7690 7691 PATTERN : VV1 0x62 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7692 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 7693 } 7694 { 7695 ICLASS : VPUNPCKLQDQ 7696 CPL : 3 7697 CATEGORY : AVX2 7698 EXTENSION : AVX2 7699 EXCEPTIONS: avx-type-4 7700 PATTERN : VV1 0x6C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7701 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 7702 7703 PATTERN : VV1 0x6C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7704 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 7705 } 7706 7707 7708 { 7709 ICLASS : VPALIGNR 7710 CPL : 3 7711 CATEGORY : AVX2 7712 EXTENSION : AVX2 7713 EXCEPTIONS: avx-type-4 7714 PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 7715 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b 7716 7717 PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 7718 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b 7719 } 7720 { 7721 ICLASS : VPBLENDW 7722 CPL : 3 7723 CATEGORY : AVX2 7724 EXTENSION : AVX2 7725 EXCEPTIONS: avx-type-4 7726 PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 7727 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b 7728 7729 PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 7730 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 IMM0:r:b 7731 } 7732 { 7733 ICLASS : VMPSADBW 7734 CPL : 3 7735 CATEGORY : AVX2 7736 EXTENSION : AVX2 7737 EXCEPTIONS: avx-type-4 7738 PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 7739 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b 7740 7741 PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 7742 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b 7743 } 7744 7745 7746 7747 { 7748 ICLASS : VPOR 7749 CPL : 3 7750 CATEGORY : LOGICAL 7751 EXTENSION : AVX2 7752 EXCEPTIONS: avx-type-4 7753 PATTERN : VV1 0xEB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7754 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 7755 7756 PATTERN : VV1 0xEB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7757 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 7758 } 7759 { 7760 ICLASS : VPAND 7761 CPL : 3 7762 CATEGORY : LOGICAL 7763 EXTENSION : AVX2 7764 EXCEPTIONS: avx-type-4 7765 PATTERN : VV1 0xDB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7766 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 7767 7768 PATTERN : VV1 0xDB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7769 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 7770 } 7771 { 7772 ICLASS : VPANDN 7773 CPL : 3 7774 CATEGORY : LOGICAL 7775 EXTENSION : AVX2 7776 EXCEPTIONS: avx-type-4 7777 PATTERN : VV1 0xDF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7778 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 7779 7780 PATTERN : VV1 0xDF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7781 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 7782 } 7783 { 7784 ICLASS : VPXOR 7785 CPL : 3 7786 CATEGORY : LOGICAL 7787 EXTENSION : AVX2 7788 EXCEPTIONS: avx-type-4 7789 PATTERN : VV1 0xEF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7790 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 7791 7792 PATTERN : VV1 0xEF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7793 OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 7794 } 7795 7796 7797 7798 { 7799 ICLASS : VPBLENDVB 7800 CPL : 3 7801 CATEGORY : AVX2 7802 EXTENSION : AVX2 7803 EXCEPTIONS: avx-type-4 7804 PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() 7805 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 REG2=YMM_SE():r:qq:u8 7806 7807 PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() 7808 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 REG3=YMM_SE():r:qq:u8 7809 } 7810 7811 7812 7813 7814 { 7815 ICLASS : VPMOVMSKB 7816 CPL : 3 7817 CATEGORY : AVX2 7818 EXTENSION : AVX2 7819 EXCEPTIONS: avx-type-7 7820 PATTERN : VV1 0xD7 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7821 OPERANDS : REG0=GPR32_R():w:d:u32 REG1=YMM_B():r:qq:i8 7822 } 7823 7824 7825 7826 { 7827 ICLASS : VPSHUFD 7828 CPL : 3 7829 CATEGORY : AVX2 7830 EXTENSION : AVX2 7831 EXCEPTIONS: avx-type-4 7832 PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 7833 OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:u32 IMM0:r:b 7834 7835 PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 7836 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b 7837 } 7838 { 7839 ICLASS : VPSHUFHW 7840 CPL : 3 7841 CATEGORY : AVX2 7842 EXTENSION : AVX2 7843 EXCEPTIONS: avx-type-4 7844 PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 7845 OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b 7846 7847 PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 7848 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b 7849 } 7850 { 7851 ICLASS : VPSHUFLW 7852 CPL : 3 7853 CATEGORY : AVX2 7854 EXTENSION : AVX2 7855 EXCEPTIONS: avx-type-4 7856 PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 7857 OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b 7858 7859 PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 7860 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b 7861 } 7862 7863 7864 7865 { 7866 ICLASS : VPSRLDQ 7867 CPL : 3 7868 CATEGORY : AVX2 7869 EXTENSION : AVX2 7870 EXCEPTIONS: avx-type-7 7871 PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() 7872 OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD 7873 } 7874 { 7875 ICLASS : VPSLLDQ 7876 CPL : 3 7877 CATEGORY : AVX2 7878 EXTENSION : AVX2 7879 EXCEPTIONS: avx-type-7 7880 PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() 7881 OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD 7882 } 7883 7884 ############################################## 7885 7886 { 7887 ICLASS : VPSLLW 7888 CPL : 3 7889 CATEGORY : AVX2 7890 EXTENSION : AVX2 7891 EXCEPTIONS: avx-type-7 7892 PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 7893 OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD 7894 } 7895 { 7896 ICLASS : VPSLLD 7897 CPL : 3 7898 CATEGORY : AVX2 7899 EXTENSION : AVX2 7900 EXCEPTIONS: avx-type-7 7901 PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 7902 OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b #NDD 7903 } 7904 { 7905 ICLASS : VPSLLQ 7906 CPL : 3 7907 CATEGORY : AVX2 7908 EXTENSION : AVX2 7909 EXCEPTIONS: avx-type-7 7910 PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() 7911 OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD 7912 } 7913 7914 { 7915 ICLASS : VPSRAW 7916 CPL : 3 7917 CATEGORY : AVX2 7918 EXTENSION : AVX2 7919 EXCEPTIONS: avx-type-7 7920 PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 7921 OPERANDS : REG0=YMM_N():w:qq:i16 REG1=YMM_B():r:qq:i16 IMM0:r:b # NDD 7922 } 7923 { 7924 ICLASS : VPSRAD 7925 CPL : 3 7926 CATEGORY : AVX2 7927 EXTENSION : AVX2 7928 EXCEPTIONS: avx-type-7 7929 PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() 7930 OPERANDS : REG0=YMM_N():w:qq:i32 REG1=YMM_B():r:qq:i32 IMM0:r:b # NDD 7931 } 7932 { 7933 ICLASS : VPSRLW 7934 CPL : 3 7935 CATEGORY : AVX2 7936 EXTENSION : AVX2 7937 EXCEPTIONS: avx-type-7 7938 PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 7939 OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD 7940 } 7941 { 7942 ICLASS : VPSRLD 7943 CPL : 3 7944 CATEGORY : AVX2 7945 EXTENSION : AVX2 7946 EXCEPTIONS: avx-type-7 7947 7948 PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 7949 OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b # NDD 7950 } 7951 { 7952 ICLASS : VPSRLQ 7953 CPL : 3 7954 CATEGORY : AVX2 7955 EXTENSION : AVX2 7956 EXCEPTIONS: avx-type-7 7957 PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() 7958 OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD 7959 } 7960 7961 7962 7963 ############################################################################ 7964 # SX versions 7965 ############################################################################ 7966 7967 { 7968 ICLASS : VPMOVSXBW 7969 CPL : 3 7970 CATEGORY : AVX2 7971 EXTENSION : AVX2 7972 EXCEPTIONS: avx-type-5 7973 PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7974 OPERANDS : REG0=YMM_R():w:qq:i16 REG1=XMM_B():r:dq:i8 7975 PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7976 OPERANDS : REG0=YMM_R():w:qq:i16 MEM0:r:dq:i8 7977 } 7978 7979 ############################################################################ 7980 { 7981 ICLASS : VPMOVSXBD 7982 CPL : 3 7983 CATEGORY : AVX2 7984 EXTENSION : AVX2 7985 EXCEPTIONS: avx-type-5 7986 PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7987 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:q:i8 7988 PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 7989 OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:q:i8 7990 } 7991 ############################################################################ 7992 { 7993 ICLASS : VPMOVSXBQ 7994 CPL : 3 7995 CATEGORY : AVX2 7996 EXTENSION : AVX2 7997 EXCEPTIONS: avx-type-5 7998 PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 7999 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:d:i8 8000 PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8001 OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:d:i8 8002 } 8003 ############################################################################ 8004 { 8005 ICLASS : VPMOVSXWD 8006 CPL : 3 8007 CATEGORY : AVX2 8008 EXTENSION : AVX2 8009 EXCEPTIONS: avx-type-5 8010 PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8011 OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:dq:i16 8012 PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8013 OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:dq:i16 8014 } 8015 ############################################################################ 8016 { 8017 ICLASS : VPMOVSXWQ 8018 CPL : 3 8019 CATEGORY : AVX2 8020 EXTENSION : AVX2 8021 EXCEPTIONS: avx-type-5 8022 PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8023 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:q:i16 8024 PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8025 OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:q:i16 8026 } 8027 ############################################################################ 8028 { 8029 ICLASS : VPMOVSXDQ 8030 CPL : 3 8031 CATEGORY : AVX2 8032 EXTENSION : AVX2 8033 EXCEPTIONS: avx-type-5 8034 PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8035 OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:dq:i32 8036 PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8037 OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:dq:i32 8038 } 8039 8040 8041 8042 8043 8044 ############################################################################ 8045 # ZX versions 8046 ############################################################################ 8047 8048 { 8049 ICLASS : VPMOVZXBW 8050 CPL : 3 8051 CATEGORY : AVX2 8052 EXTENSION : AVX2 8053 EXCEPTIONS: avx-type-5 8054 PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8055 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:dq:u8 8056 PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8057 OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:dq:u8 8058 } 8059 8060 ############################################################################ 8061 { 8062 ICLASS : VPMOVZXBD 8063 CPL : 3 8064 CATEGORY : AVX2 8065 EXTENSION : AVX2 8066 EXCEPTIONS: avx-type-5 8067 PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8068 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:q:u8 8069 PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8070 OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:q:u8 8071 } 8072 ############################################################################ 8073 { 8074 ICLASS : VPMOVZXBQ 8075 CPL : 3 8076 CATEGORY : AVX2 8077 EXTENSION : AVX2 8078 EXCEPTIONS: avx-type-5 8079 PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8080 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:d:u8 8081 PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8082 OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:d:u8 8083 } 8084 ############################################################################ 8085 { 8086 ICLASS : VPMOVZXWD 8087 CPL : 3 8088 CATEGORY : AVX2 8089 EXTENSION : AVX2 8090 EXCEPTIONS: avx-type-5 8091 PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8092 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:dq:u16 8093 PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8094 OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:dq:u16 8095 } 8096 ############################################################################ 8097 { 8098 ICLASS : VPMOVZXWQ 8099 CPL : 3 8100 CATEGORY : AVX2 8101 EXTENSION : AVX2 8102 EXCEPTIONS: avx-type-5 8103 PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8104 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u16 8105 PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8106 OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u16 8107 } 8108 ############################################################################ 8109 { 8110 ICLASS : VPMOVZXDQ 8111 CPL : 3 8112 CATEGORY : AVX2 8113 EXTENSION : AVX2 8114 EXCEPTIONS: avx-type-5 8115 PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8116 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:dq:u32 8117 PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8118 OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:dq:u32 8119 } 8120 8121 8122 ################################## 8123 # newer stuff 2009-08-14 8124 8125 8126 { 8127 ICLASS : VINSERTI128 8128 CPL : 3 8129 CATEGORY : AVX2 8130 EXTENSION : AVX2 8131 EXCEPTIONS: avx-type-6 8132 PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 8133 OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:dq:u128 IMM0:r:b 8134 8135 PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 8136 OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=XMM_B():r:dq:u128 IMM0:r:b 8137 } 8138 8139 8140 8141 8142 8143 { 8144 ICLASS : VEXTRACTI128 8145 CPL : 3 8146 CATEGORY : AVX2 8147 EXTENSION : AVX2 8148 EXCEPTIONS: avx-type-6 8149 PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 8150 OPERANDS : MEM0:w:dq:u128 REG0=YMM_R():r:qq:u128 IMM0:r:b 8151 8152 PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 8153 OPERANDS : REG0=XMM_B():w:dq:u128 REG1=YMM_R():r:qq:u128 IMM0:r:b 8154 } 8155 8156 8157 ########################################################################### 8158 8159 ### # VPMASKMOVD masked load and store 8160 ### # VPMASKMOVQ masked load and store 8161 8162 8163 8164 8165 { 8166 ICLASS : VPMASKMOVD 8167 CPL : 3 8168 CATEGORY : AVX2 8169 EXTENSION : AVX2 8170 ATTRIBUTES: maskop 8171 EXCEPTIONS: avx-type-6 8172 PATTERN : VV1 0x8C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8173 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 8174 8175 8176 PATTERN : VV1 0x8C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8177 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 8178 } 8179 { 8180 ICLASS : VPMASKMOVQ 8181 CPL : 3 8182 CATEGORY : AVX2 8183 EXTENSION : AVX2 8184 ATTRIBUTES: maskop 8185 EXCEPTIONS: avx-type-6 8186 8187 PATTERN : VV1 0x8C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8188 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 8189 8190 8191 PATTERN : VV1 0x8C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8192 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 8193 } 8194 8195 { 8196 ICLASS : VPMASKMOVD 8197 CPL : 3 8198 CATEGORY : AVX2 8199 EXTENSION : AVX2 8200 ATTRIBUTES: maskop 8201 EXCEPTIONS: avx-type-6 8202 PATTERN : VV1 0x8E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8203 OPERANDS : MEM0:w:dq:u32 REG0=XMM_N():r:dq:u32 REG1=XMM_R():r:dq:u32 8204 8205 8206 PATTERN : VV1 0x8E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8207 OPERANDS : MEM0:w:qq:u32 REG0=YMM_N():r:qq:u32 REG1=YMM_R():r:qq:u32 8208 } 8209 { 8210 ICLASS : VPMASKMOVQ 8211 CPL : 3 8212 CATEGORY : AVX2 8213 EXTENSION : AVX2 8214 ATTRIBUTES: maskop 8215 EXCEPTIONS: avx-type-6 8216 PATTERN : VV1 0x8E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8217 OPERANDS : MEM0:w:dq:u64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:u64 8218 8219 8220 PATTERN : VV1 0x8E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8221 OPERANDS : MEM0:w:qq:u64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:u64 8222 } 8223 ########################################################################### 8224 8225 8226 ### # VPERM2I128 256b only 8227 8228 { 8229 ICLASS : VPERM2I128 8230 CPL : 3 8231 CATEGORY : AVX2 8232 EXTENSION : AVX2 8233 EXCEPTIONS: avx-type-6 # Note: vperm2f128 is type 4... 8234 8235 PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 8236 OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 IMM0:r:b 8237 8238 PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 8239 OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 IMM0:r:b 8240 } 8241 8242 8243 { 8244 ICLASS : VPERMQ 8245 CPL : 3 8246 CATEGORY : AVX2 8247 EXTENSION : AVX2 8248 EXCEPTIONS: avx-type-4 8249 8250 PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 8251 OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:qq:u64 IMM0:r:b 8252 8253 PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 8254 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b 8255 } 8256 8257 { 8258 ICLASS : VPERMPD 8259 CPL : 3 8260 CATEGORY : AVX2 8261 EXTENSION : AVX2 8262 EXCEPTIONS: avx-type-4 8263 8264 PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 8265 OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b 8266 8267 PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 8268 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b 8269 } 8270 8271 8272 8273 8274 8275 8276 8277 8278 { 8279 ICLASS : VPERMD 8280 CPL : 3 8281 CATEGORY : AVX2 8282 EXTENSION : AVX2 8283 EXCEPTIONS: avx-type-4 8284 8285 8286 PATTERN : VV1 0x36 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8287 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 8288 8289 PATTERN : VV1 0x36 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8290 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 8291 } 8292 { 8293 ICLASS : VPERMPS 8294 CPL : 3 8295 CATEGORY : AVX2 8296 EXTENSION : AVX2 8297 EXCEPTIONS: avx-type-4 8298 8299 PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8300 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 8301 8302 PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8303 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 8304 } 8305 8306 8307 ########################################################################### 8308 8309 8310 ### # VPBLENDD imm 128/256 8311 8312 8313 8314 { 8315 ICLASS : VPBLENDD 8316 CPL : 3 8317 CATEGORY : AVX2 8318 EXTENSION : AVX2 8319 EXCEPTIONS: avx-type-4 8320 8321 PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 8322 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b 8323 8324 PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 8325 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b 8326 8327 8328 PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 8329 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 IMM0:r:b 8330 8331 PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 8332 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 IMM0:r:b 8333 } 8334 8335 8336 8337 ########################################################################### 8338 8339 { 8340 ICLASS : VPBROADCASTB 8341 COMMENT : gpr 128/256 8342 CPL : 3 8343 CATEGORY : BROADCAST 8344 EXTENSION : AVX2 8345 EXCEPTIONS: avx-type-6 8346 8347 PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8348 OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 8349 8350 PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8351 OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO16_8 8352 8353 PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8354 OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 8355 8356 PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8357 OPERANDS : REG0=YMM_R():w:qq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO32_8 8358 8359 } 8360 8361 8362 8363 8364 { 8365 ICLASS : VPBROADCASTW 8366 COMMENT : gpr 128/256 8367 CPL : 3 8368 CATEGORY : BROADCAST 8369 EXTENSION : AVX2 8370 EXCEPTIONS: avx-type-6 8371 8372 PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8373 OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO8_16 8374 8375 PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8376 OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO8_16 8377 8378 PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8379 OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO16_16 8380 8381 PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8382 OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO16_16 8383 } 8384 8385 8386 8387 8388 ### # VPBROADCASTD gpr/mem 8389 8390 8391 { 8392 ICLASS : VPBROADCASTD 8393 COMMENT : gpr 128/256 8394 CPL : 3 8395 CATEGORY : BROADCAST 8396 EXTENSION : AVX2 8397 EXCEPTIONS: avx-type-6 8398 8399 PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8400 OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 8401 8402 PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8403 OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO4_32 8404 8405 8406 PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8407 OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 8408 8409 PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8410 OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO8_32 8411 } 8412 8413 8414 8415 ### # VPBROADCASTQ gpr/mem 8416 8417 { 8418 ICLASS : VPBROADCASTQ 8419 COMMENT : gpr 128/256 8420 CPL : 3 8421 CATEGORY : BROADCAST 8422 EXTENSION : AVX2 8423 EXCEPTIONS: avx-type-6 8424 8425 PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8426 OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 8427 8428 PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8429 OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO2_64 8430 8431 PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8432 OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 8433 8434 PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8435 OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO4_64 8436 } 8437 8438 8439 8440 8441 8442 8443 { 8444 ICLASS : VBROADCASTSS 8445 CPL : 3 8446 CATEGORY : BROADCAST 8447 EXTENSION : AVX2 8448 EXCEPTIONS: avx-type-6 8449 COMMENT : xmm,xmm and ymm,xmm 8450 PATTERN : VV1 0x18 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8451 OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO4_32 8452 8453 PATTERN : VV1 0x18 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8454 OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO8_32 8455 } 8456 8457 8458 { 8459 ICLASS : VBROADCASTSD 8460 CPL : 3 8461 CATEGORY : BROADCAST 8462 EXTENSION : AVX2 8463 EXCEPTIONS: avx-type-6 8464 COMMENT : ymm,xmm only 8465 PATTERN : VV1 0x19 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8466 OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f64 EMX_BROADCAST_1TO4_64 8467 } 8468 8469 8470 8471 { 8472 ICLASS : VBROADCASTI128 8473 CPL : 3 8474 CATEGORY : BROADCAST 8475 EXTENSION : AVX2 8476 EXCEPTIONS: avx-type-6 8477 COMMENT : memonly 256 -- FIXME: make types u64 like in AVX1? 8478 PATTERN : VV1 0x5A VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8479 OPERANDS : REG0=YMM_R():w:qq:u128 MEM0:r:dq:u128 EMX_BROADCAST_2TO4_64 8480 } 8481 8482 8483 ###FILE: ./datafiles/avxhsw/hsw-isa.txt 8484 8485 #BEGIN_LEGAL 8486 # 8487 #Copyright (c) 2016 Intel Corporation 8488 # 8489 # Licensed under the Apache License, Version 2.0 (the "License"); 8490 # you may not use this file except in compliance with the License. 8491 # You may obtain a copy of the License at 8492 # 8493 # http://www.apache.org/licenses/LICENSE-2.0 8494 # 8495 # Unless required by applicable law or agreed to in writing, software 8496 # distributed under the License is distributed on an "AS IS" BASIS, 8497 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 8498 # See the License for the specific language governing permissions and 8499 # limitations under the License. 8500 # 8501 #END_LEGAL 8502 INSTRUCTIONS():: 8503 8504 { 8505 ICLASS : TZCNT 8506 CPL : 3 8507 CATEGORY : BMI1 8508 EXTENSION : BMI1 8509 FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ] 8510 PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8511 OPERANDS : REG0=GPRv_R():w MEM0:r:v 8512 8513 PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8514 OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r 8515 } 8516 8517 { 8518 ICLASS : BSF 8519 VERSION : 1 8520 COMMENT : AMD reused 0FBC for TZCNT and made BSF not have a refining prefix. This version replaces the normal version of BSF 8521 CPL : 3 8522 CATEGORY : BITBYTE 8523 EXTENSION : BASE 8524 ISA_SET : I386 8525 FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] 8526 8527 PATTERN : 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8528 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 8529 8530 PATTERN : 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8531 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 8532 8533 PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8534 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 8535 8536 PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8537 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 8538 } 8539 8540 { 8541 ICLASS : INVPCID 8542 CPL : 0 8543 CATEGORY : MISC 8544 EXTENSION : INVPCID 8545 ISA_SET : INVPCID 8546 ATTRIBUTES : RING0 NOTSX 8547 PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() 8548 OPERANDS : REG0=GPR64_R():r MEM0:r:dq 8549 PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() 8550 OPERANDS : REG0=GPR32_R():r MEM0:r:dq 8551 COMMENT : 8552 } 8553 8554 8555 ###FILE: ./datafiles/avxhsw/hsw-lzcnt.txt 8556 8557 #BEGIN_LEGAL 8558 # 8559 #Copyright (c) 2016 Intel Corporation 8560 # 8561 # Licensed under the Apache License, Version 2.0 (the "License"); 8562 # you may not use this file except in compliance with the License. 8563 # You may obtain a copy of the License at 8564 # 8565 # http://www.apache.org/licenses/LICENSE-2.0 8566 # 8567 # Unless required by applicable law or agreed to in writing, software 8568 # distributed under the License is distributed on an "AS IS" BASIS, 8569 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 8570 # See the License for the specific language governing permissions and 8571 # limitations under the License. 8572 # 8573 #END_LEGAL 8574 INSTRUCTIONS():: 8575 8576 # LZCNT reg16, reg/mem16 F30FBD /r 8577 # LZCNT reg32, reg/mem32 F30FBD /r 8578 # LZCNT reg64, reg/mem64 F30FBD /r 8579 8580 { 8581 ICLASS : LZCNT 8582 # This replace the AMD version in LZCNT builds 8583 VERSION : 2 8584 CPL : 3 8585 CATEGORY : LZCNT 8586 EXTENSION : LZCNT 8587 COMMENT: : These next one WAS introduced first by AMD circa SSE4a. 8588 FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ] 8589 PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8590 OPERANDS : REG0=GPRv_R():w:v MEM0:r:v 8591 PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8592 OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v 8593 } 8594 8595 8596 { 8597 ICLASS : BSR 8598 VERSION : 2 8599 COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR 8600 CPL : 3 8601 CATEGORY : BITBYTE 8602 EXTENSION : BASE 8603 ISA_SET : I386 8604 FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] 8605 PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8606 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 8607 8608 PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8609 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 8610 8611 PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8612 OPERANDS : REG0=GPRv_R():cw MEM0:r:v 8613 8614 PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8615 OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r 8616 } 8617 8618 8619 ###FILE: ./datafiles/avxhsw/hsw-vex-gpr-isa.txt 8620 8621 #BEGIN_LEGAL 8622 # 8623 #Copyright (c) 2016 Intel Corporation 8624 # 8625 # Licensed under the Apache License, Version 2.0 (the "License"); 8626 # you may not use this file except in compliance with the License. 8627 # You may obtain a copy of the License at 8628 # 8629 # http://www.apache.org/licenses/LICENSE-2.0 8630 # 8631 # Unless required by applicable law or agreed to in writing, software 8632 # distributed under the License is distributed on an "AS IS" BASIS, 8633 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 8634 # See the License for the specific language governing permissions and 8635 # limitations under the License. 8636 # 8637 #END_LEGAL 8638 8639 AVX_INSTRUCTIONS():: 8640 8641 { 8642 ICLASS : PDEP 8643 CPL : 3 8644 CATEGORY : BMI2 8645 EXTENSION : BMI2 8646 8647 #32b 8648 PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8649 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d 8650 8651 PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8652 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d 8653 8654 PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8655 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d 8656 8657 PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8658 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d 8659 8660 # 64b 8661 PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8662 OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q 8663 8664 PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8665 OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q 8666 } 8667 8668 { 8669 ICLASS : PEXT 8670 CPL : 3 8671 CATEGORY : BMI2 8672 EXTENSION : BMI2 8673 8674 8675 #32b 8676 PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8677 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d 8678 8679 PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8680 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d 8681 8682 PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8683 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d 8684 8685 PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8686 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d 8687 8688 # 64b 8689 PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8690 OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q 8691 8692 PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8693 OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q 8694 } 8695 8696 8697 { 8698 ICLASS : ANDN 8699 CPL : 3 8700 CATEGORY : BMI1 8701 EXTENSION : BMI1 8702 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ] 8703 8704 # 32b 8705 PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8706 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d 8707 8708 PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8709 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d MEM0:r:d 8710 8711 PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8712 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d 8713 8714 PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8715 OPERANDS : REG0=VGPR32_R():rw:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d 8716 8717 # 64b 8718 PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8719 OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q MEM0:r:q 8720 8721 PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8722 OPERANDS : REG0=VGPR64_R():rw:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q 8723 } 8724 8725 { 8726 ICLASS : BLSR 8727 CPL : 3 8728 CATEGORY : BMI1 8729 EXTENSION : BMI1 8730 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ] 8731 8732 # 32b 8733 PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 8734 OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d 8735 8736 PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 8737 OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d 8738 8739 PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 8740 OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d 8741 8742 PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 8743 OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d 8744 8745 # 64b 8746 PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() 8747 OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q 8748 8749 PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b001] RM[nnn] 8750 OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q 8751 8752 } 8753 8754 { 8755 ICLASS : BLSMSK 8756 CPL : 3 8757 CATEGORY : BMI1 8758 EXTENSION : BMI1 8759 FLAGS : MUST [ of-0 sf-mod zf-0 af-u pf-u cf-mod ] 8760 8761 #32b 8762 PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 8763 OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d 8764 8765 PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 8766 OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d 8767 8768 PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 8769 OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d 8770 8771 PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 8772 OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d 8773 8774 #64b 8775 PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 8776 OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q 8777 8778 PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b010] RM[nnn] 8779 OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q 8780 } 8781 8782 { 8783 ICLASS : BLSI 8784 CPL : 3 8785 CATEGORY : BMI1 8786 EXTENSION : BMI1 8787 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ] 8788 8789 # 32b 8790 PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 8791 OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d 8792 8793 PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 8794 OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d 8795 8796 PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 8797 OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d 8798 8799 PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 8800 OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d 8801 8802 # 64b 8803 PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() 8804 OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q 8805 8806 PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b011] RM[nnn] 8807 OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q 8808 } 8809 8810 { 8811 ICLASS : BZHI 8812 CPL : 3 8813 CATEGORY : BMI2 8814 EXTENSION : BMI2 8815 FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ] 8816 8817 # 32b 8818 PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8819 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 8820 8821 PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8822 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 8823 8824 PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8825 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 8826 8827 PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8828 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 8829 8830 # 64b 8831 PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8832 OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q 8833 8834 PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8835 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q 8836 } 8837 8838 { 8839 ICLASS : BEXTR 8840 CPL : 3 8841 CATEGORY : BMI1 8842 EXTENSION : BMI1 8843 FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] 8844 8845 # 32b 8846 PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8847 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 8848 8849 PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8850 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 8851 8852 PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8853 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 8854 8855 PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8856 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 8857 8858 # 64b 8859 PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8860 OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q 8861 8862 PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8863 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q 8864 } 8865 8866 8867 8868 { 8869 ICLASS : SHLX 8870 CPL : 3 8871 CATEGORY : BMI2 8872 EXTENSION : BMI2 8873 8874 # 32b 8875 PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8876 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 8877 8878 PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8879 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 8880 8881 PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8882 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 8883 8884 PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8885 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 8886 8887 # 64b 8888 PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8889 OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q 8890 8891 PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8892 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q 8893 } 8894 { 8895 ICLASS : SARX 8896 CPL : 3 8897 CATEGORY : BMI2 8898 EXTENSION : BMI2 8899 8900 # 32b 8901 PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8902 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 8903 8904 PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8905 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 8906 8907 PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8908 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 8909 8910 PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8911 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 8912 8913 # 64b 8914 PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8915 OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q 8916 8917 PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8918 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q 8919 } 8920 { 8921 ICLASS : SHRX 8922 CPL : 3 8923 CATEGORY : BMI2 8924 EXTENSION : BMI2 8925 8926 # 32b 8927 PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8928 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 8929 8930 PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8931 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d 8932 8933 PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8934 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 8935 8936 PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8937 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d 8938 8939 # 64b 8940 PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8941 OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q 8942 8943 PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8944 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q 8945 } 8946 8947 8948 8949 { 8950 ICLASS : MULX 8951 CPL : 3 8952 CATEGORY : BMI2 8953 EXTENSION : BMI2 8954 8955 # reg:w vvvv:w rm:r rdx:r 8956 # 32b 8957 PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8958 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP 8959 8960 PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8961 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP 8962 PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8963 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP 8964 8965 PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8966 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP 8967 8968 # 64b 8969 PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 8970 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q REG2=VGPR64_B():r:q REG3=XED_REG_RDX:r:SUPP 8971 PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 8972 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q MEM0:r:q REG2=XED_REG_RDX:r:SUPP 8973 } 8974 8975 { 8976 ICLASS : RORX 8977 CPL : 3 8978 CATEGORY : BMI2 8979 EXTENSION : BMI2 8980 8981 # reg(w) rm(r) / vvvv must be 1111. / 2010-01-08 CART change 8982 8983 # 32b 8984 PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 8985 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b 8986 8987 PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 8988 OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b 8989 PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 8990 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b 8991 8992 PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 8993 OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b 8994 8995 # 64b 8996 PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() 8997 OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q IMM0:r:b 8998 PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 8999 OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q IMM0:r:b 9000 } 9001 9002 9003 ###FILE: ./datafiles/avxhsw/hsw-vshift-isa.txt 9004 9005 #BEGIN_LEGAL 9006 # 9007 #Copyright (c) 2016 Intel Corporation 9008 # 9009 # Licensed under the Apache License, Version 2.0 (the "License"); 9010 # you may not use this file except in compliance with the License. 9011 # You may obtain a copy of the License at 9012 # 9013 # http://www.apache.org/licenses/LICENSE-2.0 9014 # 9015 # Unless required by applicable law or agreed to in writing, software 9016 # distributed under the License is distributed on an "AS IS" BASIS, 9017 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 9018 # See the License for the specific language governing permissions and 9019 # limitations under the License. 9020 # 9021 #END_LEGAL 9022 AVX_INSTRUCTIONS():: 9023 9024 9025 9026 9027 { 9028 ICLASS : VPSLLVD 9029 CPL : 3 9030 CATEGORY : AVX2 9031 EXTENSION : AVX2 9032 EXCEPTIONS: avx-type-4 9033 PATTERN : VV1 0x47 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9034 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 9035 9036 PATTERN : VV1 0x47 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9037 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 9038 9039 PATTERN : VV1 0x47 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9040 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 9041 9042 PATTERN : VV1 0x47 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9043 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 9044 9045 } 9046 { 9047 ICLASS : VPSLLVQ 9048 CPL : 3 9049 CATEGORY : AVX2 9050 EXTENSION : AVX2 9051 EXCEPTIONS: avx-type-4 9052 PATTERN : VV1 0x47 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9053 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 9054 9055 PATTERN : VV1 0x47 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9056 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 9057 9058 PATTERN : VV1 0x47 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9059 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 9060 9061 PATTERN : VV1 0x47 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9062 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 9063 9064 } 9065 9066 { 9067 ICLASS : VPSRLVD 9068 CPL : 3 9069 CATEGORY : AVX2 9070 EXTENSION : AVX2 9071 EXCEPTIONS: avx-type-4 9072 PATTERN : VV1 0x45 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9073 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 9074 9075 PATTERN : VV1 0x45 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9076 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 9077 9078 PATTERN : VV1 0x45 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9079 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 9080 9081 PATTERN : VV1 0x45 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9082 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 9083 9084 } 9085 { 9086 ICLASS : VPSRLVQ 9087 CPL : 3 9088 CATEGORY : AVX2 9089 EXTENSION : AVX2 9090 EXCEPTIONS: avx-type-4 9091 PATTERN : VV1 0x45 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9092 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 9093 9094 PATTERN : VV1 0x45 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9095 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 9096 9097 PATTERN : VV1 0x45 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9098 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 9099 9100 PATTERN : VV1 0x45 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9101 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 9102 9103 } 9104 9105 { 9106 ICLASS : VPSRAVD 9107 CPL : 3 9108 CATEGORY : AVX2 9109 EXTENSION : AVX2 9110 EXCEPTIONS: avx-type-4 9111 PATTERN : VV1 0x46 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9112 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq 9113 9114 PATTERN : VV1 0x46 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9115 OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq 9116 9117 PATTERN : VV1 0x46 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9118 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq 9119 9120 PATTERN : VV1 0x46 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9121 OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq 9122 9123 } 9124 9125 9126 9127 9128 ###FILE: ./datafiles/avxhsw/movnt-load-isa.txt 9129 9130 #BEGIN_LEGAL 9131 # 9132 #Copyright (c) 2016 Intel Corporation 9133 # 9134 # Licensed under the Apache License, Version 2.0 (the "License"); 9135 # you may not use this file except in compliance with the License. 9136 # You may obtain a copy of the License at 9137 # 9138 # http://www.apache.org/licenses/LICENSE-2.0 9139 # 9140 # Unless required by applicable law or agreed to in writing, software 9141 # distributed under the License is distributed on an "AS IS" BASIS, 9142 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 9143 # See the License for the specific language governing permissions and 9144 # limitations under the License. 9145 # 9146 #END_LEGAL 9147 AVX_INSTRUCTIONS():: 9148 9149 9150 { 9151 ICLASS : VMOVNTDQA 9152 CPL : 3 9153 CATEGORY : DATAXFER 9154 EXTENSION : AVX2 9155 EXCEPTIONS: avx-type-1 9156 ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL 9157 9158 PATTERN : VV1 0x2A V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9159 OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq 9160 } 9161 9162 9163 9164 9165 9166 ###FILE: ./datafiles/avxhsw/vmfunc-isa.txt 9167 9168 #BEGIN_LEGAL 9169 # 9170 #Copyright (c) 2016 Intel Corporation 9171 # 9172 # Licensed under the Apache License, Version 2.0 (the "License"); 9173 # you may not use this file except in compliance with the License. 9174 # You may obtain a copy of the License at 9175 # 9176 # http://www.apache.org/licenses/LICENSE-2.0 9177 # 9178 # Unless required by applicable law or agreed to in writing, software 9179 # distributed under the License is distributed on an "AS IS" BASIS, 9180 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 9181 # See the License for the specific language governing permissions and 9182 # limitations under the License. 9183 # 9184 #END_LEGAL 9185 INSTRUCTIONS():: 9186 9187 { 9188 ICLASS : VMFUNC 9189 CPL : 3 9190 CATEGORY : VTX 9191 EXTENSION : VMFUNC 9192 ISA_SET : VMFUNC 9193 ATTRIBUTES : 9194 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix 9195 OPERANDS : REG0=XED_REG_EAX:r:SUPP 9196 } 9197 9198 9199 ###FILE: ./datafiles/avxhsw/rtm.xed 9200 9201 #BEGIN_LEGAL 9202 # 9203 #Copyright (c) 2017 Intel Corporation 9204 # 9205 # Licensed under the Apache License, Version 2.0 (the "License"); 9206 # you may not use this file except in compliance with the License. 9207 # You may obtain a copy of the License at 9208 # 9209 # http://www.apache.org/licenses/LICENSE-2.0 9210 # 9211 # Unless required by applicable law or agreed to in writing, software 9212 # distributed under the License is distributed on an "AS IS" BASIS, 9213 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 9214 # See the License for the specific language governing permissions and 9215 # limitations under the License. 9216 # 9217 #END_LEGAL 9218 INSTRUCTIONS():: 9219 9220 { 9221 ICLASS : XBEGIN 9222 CPL : 3 9223 CATEGORY : COND_BR 9224 EXTENSION : RTM 9225 COMMENT : Not always a branch. If aborts, then branches & eax is written 9226 9227 PATTERN : 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[0b000] BRDISPz() 9228 OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP REG1=XED_REG_EAX:cw:SUPP 9229 } 9230 9231 { 9232 ICLASS : XEND 9233 CPL : 3 9234 CATEGORY : COND_BR 9235 EXTENSION : RTM 9236 COMMENT : Transaction end. may branch 9237 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix 9238 OPERANDS : 9239 } 9240 9241 { 9242 ICLASS : XABORT 9243 CPL : 3 9244 CATEGORY : UNCOND_BR 9245 EXTENSION : RTM 9246 COMMENT : Transaction abort. Branches. NOP outside of transaction; Thus eax is rcw. 9247 PATTERN : 0xC6 MOD[0b11] MOD=3 REG[0b111] RM[0b000] UIMM8() 9248 OPERANDS : REG0=XED_REG_EAX:rcw:SUPP IMM0:r:b 9249 } 9250 9251 9252 { 9253 ICLASS : XTEST 9254 CPL : 3 9255 CATEGORY : LOGICAL 9256 EXTENSION : RTM 9257 COMMENT : test if in RTM transaction mode 9258 FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-0 cf-0 ] 9259 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix 9260 OPERANDS : 9261 } 9262 9263 9264 ###FILE: ./datafiles/avx/avx-fma-isa.txt 9265 9266 #BEGIN_LEGAL 9267 # 9268 #Copyright (c) 2016 Intel Corporation 9269 # 9270 # Licensed under the Apache License, Version 2.0 (the "License"); 9271 # you may not use this file except in compliance with the License. 9272 # You may obtain a copy of the License at 9273 # 9274 # http://www.apache.org/licenses/LICENSE-2.0 9275 # 9276 # Unless required by applicable law or agreed to in writing, software 9277 # distributed under the License is distributed on an "AS IS" BASIS, 9278 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 9279 # See the License for the specific language governing permissions and 9280 # limitations under the License. 9281 # 9282 #END_LEGAL 9283 AVX_INSTRUCTIONS():: 9284 9285 # Issues: encoder is at a loss for vmaddps xmm0,xmm0,xmm0,xmm0. 9286 # Encoder must enforce equality between two parameters. Never had to do this before. 9287 # Extra check? 9288 # Decoder must rip off suffixes _DDMR, _DDRM, _DRMD in disassembly (eventually) 9289 ############################################################################################# 9290 # Operand orders: 9291 # A = B * C + D 9292 #Type 1) reg0 reg0 mem/reg1 reg2 DDMR 312 or 132 9293 #Type 2) reg0 reg0 reg1 mem/reg2 DDRM 123 or 213 9294 #Type 3) reg0 reg1 mem/reg2 reg0 DRMD 321 or 231 9295 9296 # dst is in MODRM.REG 9297 # regsrc is in VEX.vvvv 9298 # memop is in MODRM.RM 9299 ############################################################################################ 9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 9310 9311 9312 ########################################################## 9313 9314 9315 9316 9317 9318 9319 9320 9321 9322 9323 9324 9325 ################################################################## 9326 9327 9328 9329 9330 9331 9332 9333 9334 9335 9336 9337 9338 9339 ################################################################## 9340 { 9341 ICLASS : VFMADD132PD 9342 EXCEPTIONS: avx-type-2 9343 CPL : 3 9344 CATEGORY : VFMA 9345 EXTENSION : FMA 9346 ATTRIBUTES: MXCSR 9347 # R/M 128 9348 PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9349 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 9350 # R/R 128 9351 PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9352 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 9353 9354 9355 # R/M 256 9356 PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9357 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 9358 # R/R 256 9359 PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9360 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 9361 } 9362 { 9363 ICLASS : VFMADD132PS 9364 EXCEPTIONS: avx-type-2 9365 CPL : 3 9366 CATEGORY : VFMA 9367 EXTENSION : FMA 9368 ATTRIBUTES: MXCSR 9369 # R/M 128 9370 PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9371 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 9372 # R/R 128 9373 PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9374 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 9375 9376 9377 # R/M 256 9378 PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9379 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 9380 # R/R 256 9381 PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9382 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 9383 } 9384 { 9385 ICLASS : VFMADD132SD 9386 EXCEPTIONS: avx-type-3 9387 CPL : 3 9388 CATEGORY : VFMA 9389 EXTENSION : FMA 9390 ATTRIBUTES: MXCSR simd_scalar 9391 # R/M 128 9392 PATTERN : VV1 0x99 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9393 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 9394 # R/R 128 9395 PATTERN : VV1 0x99 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9396 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 9397 } 9398 { 9399 ICLASS : VFMADD132SS 9400 EXCEPTIONS: avx-type-3 9401 CPL : 3 9402 CATEGORY : VFMA 9403 EXTENSION : FMA 9404 ATTRIBUTES: MXCSR simd_scalar 9405 # R/M 128 9406 PATTERN : VV1 0x99 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9407 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 9408 # R/R 128 9409 PATTERN : VV1 0x99 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9410 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 9411 9412 } 9413 9414 { 9415 ICLASS : VFMADD213PD 9416 EXCEPTIONS: avx-type-2 9417 CPL : 3 9418 CATEGORY : VFMA 9419 EXTENSION : FMA 9420 ATTRIBUTES: MXCSR 9421 # R/M 128 9422 PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9423 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 9424 # R/R 128 9425 PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9426 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 9427 9428 9429 # R/M 256 9430 PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9431 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 9432 # R/R 256 9433 PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9434 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 9435 } 9436 { 9437 ICLASS : VFMADD213PS 9438 EXCEPTIONS: avx-type-2 9439 CPL : 3 9440 CATEGORY : VFMA 9441 EXTENSION : FMA 9442 ATTRIBUTES: MXCSR 9443 # R/M 128 9444 PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9445 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 9446 # R/R 128 9447 PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9448 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 9449 9450 9451 # R/M 256 9452 PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9453 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 9454 # R/R 256 9455 PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9456 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 9457 } 9458 { 9459 ICLASS : VFMADD213SD 9460 EXCEPTIONS: avx-type-3 9461 CPL : 3 9462 CATEGORY : VFMA 9463 EXTENSION : FMA 9464 ATTRIBUTES: MXCSR simd_scalar 9465 # R/M 128 9466 PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9467 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 9468 # R/R 128 9469 PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9470 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 9471 9472 } 9473 { 9474 ICLASS : VFMADD213SS 9475 EXCEPTIONS: avx-type-3 9476 CPL : 3 9477 CATEGORY : VFMA 9478 EXTENSION : FMA 9479 ATTRIBUTES: MXCSR simd_scalar 9480 # R/M 128 9481 PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9482 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 9483 # R/R 128 9484 PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9485 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 9486 } 9487 9488 { 9489 ICLASS : VFMADD231PD 9490 EXCEPTIONS: avx-type-2 9491 CPL : 3 9492 CATEGORY : VFMA 9493 EXTENSION : FMA 9494 ATTRIBUTES: MXCSR 9495 # R/M 128 9496 PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9497 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 9498 # R/R 128 9499 PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9500 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 9501 9502 9503 # R/M 256 9504 PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9505 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 9506 # R/R 256 9507 PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9508 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 9509 9510 } 9511 { 9512 ICLASS : VFMADD231PS 9513 EXCEPTIONS: avx-type-2 9514 CPL : 3 9515 CATEGORY : VFMA 9516 EXTENSION : FMA 9517 ATTRIBUTES: MXCSR 9518 # R/M 128 9519 PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9520 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 9521 # R/R 128 9522 PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9523 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 9524 9525 # R/M 256 9526 PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9527 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 9528 # R/R 256 9529 PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9530 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 9531 9532 } 9533 { 9534 ICLASS : VFMADD231SD 9535 EXCEPTIONS: avx-type-3 9536 CPL : 3 9537 CATEGORY : VFMA 9538 EXTENSION : FMA 9539 ATTRIBUTES: MXCSR simd_scalar 9540 # R/M 128 9541 PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9542 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 9543 # R/R 128 9544 PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9545 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 9546 9547 } 9548 { 9549 ICLASS : VFMADD231SS 9550 EXCEPTIONS: avx-type-3 9551 CPL : 3 9552 CATEGORY : VFMA 9553 EXTENSION : FMA 9554 ATTRIBUTES: MXCSR simd_scalar 9555 # R/M 128 9556 PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9557 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 9558 # R/R 128 9559 PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9560 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 9561 9562 } 9563 9564 9565 ################################################### 9566 { 9567 ICLASS : VFMADDSUB132PD 9568 EXCEPTIONS: avx-type-2 9569 CPL : 3 9570 CATEGORY : VFMA 9571 EXTENSION : FMA 9572 ATTRIBUTES: MXCSR 9573 # R/M 128 9574 PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9575 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 9576 # R/R 128 9577 PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9578 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 9579 9580 9581 # R/M 256 9582 PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9583 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 9584 # R/R 256 9585 PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9586 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 9587 } 9588 { 9589 ICLASS : VFMADDSUB213PD 9590 EXCEPTIONS: avx-type-2 9591 CPL : 3 9592 CATEGORY : VFMA 9593 EXTENSION : FMA 9594 ATTRIBUTES: MXCSR 9595 # R/M 128 9596 PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9597 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 9598 # R/R 128 9599 PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9600 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 9601 9602 9603 # R/M 256 9604 PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9605 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 9606 # R/R 256 9607 PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9608 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 9609 } 9610 { 9611 ICLASS : VFMADDSUB231PD 9612 EXCEPTIONS: avx-type-2 9613 CPL : 3 9614 CATEGORY : VFMA 9615 EXTENSION : FMA 9616 ATTRIBUTES: MXCSR 9617 # R/M 128 9618 PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9619 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 9620 # R/R 128 9621 PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9622 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 9623 9624 9625 # R/M 256 9626 PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9627 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 9628 # R/R 256 9629 PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9630 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 9631 9632 } 9633 9634 { 9635 ICLASS : VFMADDSUB132PS 9636 EXCEPTIONS: avx-type-2 9637 CPL : 3 9638 CATEGORY : VFMA 9639 EXTENSION : FMA 9640 ATTRIBUTES: MXCSR 9641 # R/M 128 9642 PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9643 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 9644 # R/R 128 9645 PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9646 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 9647 9648 9649 # R/M 256 9650 PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9651 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 9652 # R/R 256 9653 PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9654 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 9655 } 9656 { 9657 ICLASS : VFMADDSUB213PS 9658 EXCEPTIONS: avx-type-2 9659 CPL : 3 9660 CATEGORY : VFMA 9661 EXTENSION : FMA 9662 ATTRIBUTES: MXCSR 9663 # R/M 128 9664 PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9665 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 9666 # R/R 128 9667 PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9668 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 9669 9670 9671 # R/M 256 9672 PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9673 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 9674 # R/R 256 9675 PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9676 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 9677 } 9678 { 9679 ICLASS : VFMADDSUB231PS 9680 EXCEPTIONS: avx-type-2 9681 CPL : 3 9682 CATEGORY : VFMA 9683 EXTENSION : FMA 9684 ATTRIBUTES: MXCSR 9685 # R/M 128 9686 PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9687 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 9688 # R/R 128 9689 PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9690 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 9691 9692 # R/M 256 9693 PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9694 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 9695 # R/R 256 9696 PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9697 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 9698 9699 } 9700 ################################################### 9701 9702 { 9703 ICLASS : VFMSUBADD132PD 9704 EXCEPTIONS: avx-type-2 9705 CPL : 3 9706 CATEGORY : VFMA 9707 EXTENSION : FMA 9708 ATTRIBUTES: MXCSR 9709 # R/M 128 9710 PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9711 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 9712 # R/R 128 9713 PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9714 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 9715 9716 9717 # R/M 256 9718 PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9719 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 9720 # R/R 256 9721 PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9722 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 9723 } 9724 { 9725 ICLASS : VFMSUBADD213PD 9726 EXCEPTIONS: avx-type-2 9727 CPL : 3 9728 CATEGORY : VFMA 9729 EXTENSION : FMA 9730 ATTRIBUTES: MXCSR 9731 # R/M 128 9732 PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9733 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 9734 # R/R 128 9735 PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9736 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 9737 9738 9739 # R/M 256 9740 PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9741 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 9742 # R/R 256 9743 PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9744 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 9745 } 9746 { 9747 ICLASS : VFMSUBADD231PD 9748 EXCEPTIONS: avx-type-2 9749 CPL : 3 9750 CATEGORY : VFMA 9751 EXTENSION : FMA 9752 ATTRIBUTES: MXCSR 9753 # R/M 128 9754 PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9755 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 9756 # R/R 128 9757 PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9758 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 9759 9760 9761 # R/M 256 9762 PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9763 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 9764 # R/R 256 9765 PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9766 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 9767 9768 } 9769 9770 { 9771 ICLASS : VFMSUBADD132PS 9772 EXCEPTIONS: avx-type-2 9773 CPL : 3 9774 CATEGORY : VFMA 9775 EXTENSION : FMA 9776 ATTRIBUTES: MXCSR 9777 # R/M 128 9778 PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9779 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 9780 # R/R 128 9781 PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9782 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 9783 9784 9785 # R/M 256 9786 PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9787 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 9788 # R/R 256 9789 PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9790 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 9791 } 9792 { 9793 ICLASS : VFMSUBADD213PS 9794 EXCEPTIONS: avx-type-2 9795 CPL : 3 9796 CATEGORY : VFMA 9797 EXTENSION : FMA 9798 ATTRIBUTES: MXCSR 9799 # R/M 128 9800 PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9801 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 9802 # R/R 128 9803 PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9804 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 9805 9806 9807 # R/M 256 9808 PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9809 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 9810 # R/R 256 9811 PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9812 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 9813 } 9814 { 9815 ICLASS : VFMSUBADD231PS 9816 EXCEPTIONS: avx-type-2 9817 CPL : 3 9818 CATEGORY : VFMA 9819 EXTENSION : FMA 9820 ATTRIBUTES: MXCSR 9821 # R/M 128 9822 PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9823 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 9824 # R/R 128 9825 PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9826 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 9827 9828 # R/M 256 9829 PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9830 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 9831 # R/R 256 9832 PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9833 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 9834 9835 } 9836 9837 9838 ################################################### 9839 9840 { 9841 ICLASS : VFMSUB132PD 9842 EXCEPTIONS: avx-type-2 9843 CPL : 3 9844 CATEGORY : VFMA 9845 EXTENSION : FMA 9846 ATTRIBUTES: MXCSR 9847 # R/M 128 9848 PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9849 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 9850 # R/R 128 9851 PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9852 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 9853 9854 9855 # R/M 256 9856 PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9857 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 9858 # R/R 256 9859 PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9860 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 9861 } 9862 { 9863 ICLASS : VFMSUB132PS 9864 EXCEPTIONS: avx-type-2 9865 CPL : 3 9866 CATEGORY : VFMA 9867 EXTENSION : FMA 9868 ATTRIBUTES: MXCSR 9869 # R/M 128 9870 PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9871 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 9872 # R/R 128 9873 PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9874 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 9875 9876 9877 # R/M 256 9878 PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9879 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 9880 # R/R 256 9881 PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9882 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 9883 } 9884 { 9885 ICLASS : VFMSUB132SD 9886 EXCEPTIONS: avx-type-3 9887 CPL : 3 9888 CATEGORY : VFMA 9889 EXTENSION : FMA 9890 ATTRIBUTES: MXCSR simd_scalar 9891 # R/M 128 9892 PATTERN : VV1 0x9B V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9893 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 9894 # R/R 128 9895 PATTERN : VV1 0x9B V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9896 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 9897 } 9898 { 9899 ICLASS : VFMSUB132SS 9900 EXCEPTIONS: avx-type-3 9901 CPL : 3 9902 CATEGORY : VFMA 9903 EXTENSION : FMA 9904 ATTRIBUTES: MXCSR simd_scalar 9905 # R/M 128 9906 PATTERN : VV1 0x9B V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9907 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 9908 # R/R 128 9909 PATTERN : VV1 0x9B V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9910 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 9911 9912 } 9913 9914 { 9915 ICLASS : VFMSUB213PD 9916 EXCEPTIONS: avx-type-2 9917 CPL : 3 9918 CATEGORY : VFMA 9919 EXTENSION : FMA 9920 ATTRIBUTES: MXCSR 9921 # R/M 128 9922 PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9923 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 9924 # R/R 128 9925 PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9926 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 9927 9928 9929 # R/M 256 9930 PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9931 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 9932 # R/R 256 9933 PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9934 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 9935 } 9936 { 9937 ICLASS : VFMSUB213PS 9938 EXCEPTIONS: avx-type-2 9939 CPL : 3 9940 CATEGORY : VFMA 9941 EXTENSION : FMA 9942 ATTRIBUTES: MXCSR 9943 # R/M 128 9944 PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9945 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 9946 # R/R 128 9947 PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9948 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 9949 9950 9951 # R/M 256 9952 PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9953 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 9954 # R/R 256 9955 PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9956 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 9957 } 9958 { 9959 ICLASS : VFMSUB213SD 9960 EXCEPTIONS: avx-type-3 9961 CPL : 3 9962 CATEGORY : VFMA 9963 EXTENSION : FMA 9964 ATTRIBUTES: MXCSR simd_scalar 9965 # R/M 128 9966 PATTERN : VV1 0xAB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9967 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 9968 # R/R 128 9969 PATTERN : VV1 0xAB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9970 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 9971 9972 } 9973 { 9974 ICLASS : VFMSUB213SS 9975 EXCEPTIONS: avx-type-3 9976 CPL : 3 9977 CATEGORY : VFMA 9978 EXTENSION : FMA 9979 ATTRIBUTES: MXCSR simd_scalar 9980 # R/M 128 9981 PATTERN : VV1 0xAB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9982 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 9983 # R/R 128 9984 PATTERN : VV1 0xAB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 9985 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 9986 } 9987 9988 { 9989 ICLASS : VFMSUB231PD 9990 EXCEPTIONS: avx-type-2 9991 CPL : 3 9992 CATEGORY : VFMA 9993 EXTENSION : FMA 9994 ATTRIBUTES: MXCSR 9995 # R/M 128 9996 PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 9997 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 9998 # R/R 128 9999 PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10000 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 10001 10002 10003 # R/M 256 10004 PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10005 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 10006 # R/R 256 10007 PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10008 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 10009 10010 } 10011 { 10012 ICLASS : VFMSUB231PS 10013 EXCEPTIONS: avx-type-2 10014 CPL : 3 10015 CATEGORY : VFMA 10016 EXTENSION : FMA 10017 ATTRIBUTES: MXCSR 10018 # R/M 128 10019 PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10020 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 10021 # R/R 128 10022 PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10023 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 10024 10025 # R/M 256 10026 PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10027 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 10028 # R/R 256 10029 PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10030 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 10031 10032 } 10033 { 10034 ICLASS : VFMSUB231SD 10035 EXCEPTIONS: avx-type-3 10036 CPL : 3 10037 CATEGORY : VFMA 10038 EXTENSION : FMA 10039 ATTRIBUTES: MXCSR simd_scalar 10040 # R/M 128 10041 PATTERN : VV1 0xBB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10042 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 10043 # R/R 128 10044 PATTERN : VV1 0xBB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10045 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 10046 10047 } 10048 { 10049 ICLASS : VFMSUB231SS 10050 EXCEPTIONS: avx-type-3 10051 CPL : 3 10052 CATEGORY : VFMA 10053 EXTENSION : FMA 10054 ATTRIBUTES: MXCSR simd_scalar 10055 # R/M 128 10056 PATTERN : VV1 0xBB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10057 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 10058 # R/R 128 10059 PATTERN : VV1 0xBB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10060 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 10061 10062 } 10063 10064 ################################################### 10065 10066 10067 { 10068 ICLASS : VFNMADD132PD 10069 EXCEPTIONS: avx-type-2 10070 CPL : 3 10071 CATEGORY : VFMA 10072 EXTENSION : FMA 10073 ATTRIBUTES: MXCSR 10074 # R/M 128 10075 PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10076 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 10077 # R/R 128 10078 PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10079 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 10080 10081 10082 # R/M 256 10083 PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10084 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 10085 # R/R 256 10086 PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10087 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 10088 } 10089 { 10090 ICLASS : VFNMADD132PS 10091 EXCEPTIONS: avx-type-2 10092 CPL : 3 10093 CATEGORY : VFMA 10094 EXTENSION : FMA 10095 ATTRIBUTES: MXCSR 10096 # R/M 128 10097 PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10098 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 10099 # R/R 128 10100 PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10101 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 10102 10103 10104 # R/M 256 10105 PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10106 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 10107 # R/R 256 10108 PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10109 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 10110 } 10111 { 10112 ICLASS : VFNMADD132SD 10113 EXCEPTIONS: avx-type-3 10114 CPL : 3 10115 CATEGORY : VFMA 10116 EXTENSION : FMA 10117 ATTRIBUTES: MXCSR simd_scalar 10118 # R/M 128 10119 PATTERN : VV1 0x9D V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10120 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 10121 # R/R 128 10122 PATTERN : VV1 0x9D V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10123 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 10124 } 10125 { 10126 ICLASS : VFNMADD132SS 10127 EXCEPTIONS: avx-type-3 10128 CPL : 3 10129 CATEGORY : VFMA 10130 EXTENSION : FMA 10131 ATTRIBUTES: MXCSR simd_scalar 10132 # R/M 128 10133 PATTERN : VV1 0x9D V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10134 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 10135 # R/R 128 10136 PATTERN : VV1 0x9D V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10137 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 10138 10139 } 10140 10141 { 10142 ICLASS : VFNMADD213PD 10143 EXCEPTIONS: avx-type-2 10144 CPL : 3 10145 CATEGORY : VFMA 10146 EXTENSION : FMA 10147 ATTRIBUTES: MXCSR 10148 # R/M 128 10149 PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10150 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 10151 # R/R 128 10152 PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10153 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 10154 10155 10156 # R/M 256 10157 PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10158 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 10159 # R/R 256 10160 PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10161 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 10162 } 10163 { 10164 ICLASS : VFNMADD213PS 10165 EXCEPTIONS: avx-type-2 10166 CPL : 3 10167 CATEGORY : VFMA 10168 EXTENSION : FMA 10169 ATTRIBUTES: MXCSR 10170 # R/M 128 10171 PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10172 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 10173 # R/R 128 10174 PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10175 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 10176 10177 10178 # R/M 256 10179 PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10180 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 10181 # R/R 256 10182 PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10183 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 10184 } 10185 { 10186 ICLASS : VFNMADD213SD 10187 EXCEPTIONS: avx-type-3 10188 CPL : 3 10189 CATEGORY : VFMA 10190 EXTENSION : FMA 10191 ATTRIBUTES: MXCSR simd_scalar 10192 # R/M 128 10193 PATTERN : VV1 0xAD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10194 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 10195 # R/R 128 10196 PATTERN : VV1 0xAD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10197 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 10198 10199 } 10200 { 10201 ICLASS : VFNMADD213SS 10202 EXCEPTIONS: avx-type-3 10203 CPL : 3 10204 CATEGORY : VFMA 10205 EXTENSION : FMA 10206 ATTRIBUTES: MXCSR simd_scalar 10207 # R/M 128 10208 PATTERN : VV1 0xAD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10209 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 10210 # R/R 128 10211 PATTERN : VV1 0xAD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10212 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 10213 } 10214 10215 { 10216 ICLASS : VFNMADD231PD 10217 EXCEPTIONS: avx-type-2 10218 CPL : 3 10219 CATEGORY : VFMA 10220 EXTENSION : FMA 10221 ATTRIBUTES: MXCSR 10222 # R/M 128 10223 PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10224 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 10225 # R/R 128 10226 PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10227 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 10228 10229 10230 # R/M 256 10231 PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10232 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 10233 # R/R 256 10234 PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10235 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 10236 10237 } 10238 { 10239 ICLASS : VFNMADD231PS 10240 EXCEPTIONS: avx-type-2 10241 CPL : 3 10242 CATEGORY : VFMA 10243 EXTENSION : FMA 10244 ATTRIBUTES: MXCSR 10245 # R/M 128 10246 PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10247 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 10248 # R/R 128 10249 PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10250 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 10251 10252 # R/M 256 10253 PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10254 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 10255 # R/R 256 10256 PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10257 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 10258 10259 } 10260 { 10261 ICLASS : VFNMADD231SD 10262 EXCEPTIONS: avx-type-3 10263 CPL : 3 10264 CATEGORY : VFMA 10265 EXTENSION : FMA 10266 ATTRIBUTES: MXCSR simd_scalar 10267 # R/M 128 10268 PATTERN : VV1 0xBD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10269 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 10270 # R/R 128 10271 PATTERN : VV1 0xBD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10272 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 10273 10274 } 10275 { 10276 ICLASS : VFNMADD231SS 10277 EXCEPTIONS: avx-type-3 10278 CPL : 3 10279 CATEGORY : VFMA 10280 EXTENSION : FMA 10281 ATTRIBUTES: MXCSR simd_scalar 10282 # R/M 128 10283 PATTERN : VV1 0xBD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10284 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 10285 # R/R 128 10286 PATTERN : VV1 0xBD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10287 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 10288 10289 } 10290 10291 ################################################### 10292 10293 10294 { 10295 ICLASS : VFNMSUB132PD 10296 EXCEPTIONS: avx-type-2 10297 CPL : 3 10298 CATEGORY : VFMA 10299 EXTENSION : FMA 10300 ATTRIBUTES: MXCSR 10301 # R/M 128 10302 PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10303 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 10304 # R/R 128 10305 PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10306 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 10307 10308 10309 # R/M 256 10310 PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10311 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 10312 # R/R 256 10313 PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10314 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 10315 } 10316 { 10317 ICLASS : VFNMSUB132PS 10318 EXCEPTIONS: avx-type-2 10319 CPL : 3 10320 CATEGORY : VFMA 10321 EXTENSION : FMA 10322 ATTRIBUTES: MXCSR 10323 # R/M 128 10324 PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10325 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 10326 # R/R 128 10327 PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10328 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 10329 10330 10331 # R/M 256 10332 PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10333 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 10334 # R/R 256 10335 PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10336 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 10337 } 10338 { 10339 ICLASS : VFNMSUB132SD 10340 EXCEPTIONS: avx-type-3 10341 CPL : 3 10342 CATEGORY : VFMA 10343 EXTENSION : FMA 10344 ATTRIBUTES: MXCSR simd_scalar 10345 # R/M 128 10346 PATTERN : VV1 0x9F V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10347 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 10348 # R/R 128 10349 PATTERN : VV1 0x9F V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10350 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 10351 } 10352 { 10353 ICLASS : VFNMSUB132SS 10354 EXCEPTIONS: avx-type-3 10355 CPL : 3 10356 CATEGORY : VFMA 10357 EXTENSION : FMA 10358 ATTRIBUTES: MXCSR simd_scalar 10359 # R/M 128 10360 PATTERN : VV1 0x9F V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10361 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 10362 # R/R 128 10363 PATTERN : VV1 0x9F V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10364 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 10365 10366 } 10367 10368 { 10369 ICLASS : VFNMSUB213PD 10370 EXCEPTIONS: avx-type-2 10371 CPL : 3 10372 CATEGORY : VFMA 10373 EXTENSION : FMA 10374 ATTRIBUTES: MXCSR 10375 # R/M 128 10376 PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10377 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 10378 # R/R 128 10379 PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10380 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 10381 10382 10383 # R/M 256 10384 PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10385 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 10386 # R/R 256 10387 PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10388 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 10389 } 10390 { 10391 ICLASS : VFNMSUB213PS 10392 EXCEPTIONS: avx-type-2 10393 CPL : 3 10394 CATEGORY : VFMA 10395 EXTENSION : FMA 10396 ATTRIBUTES: MXCSR 10397 # R/M 128 10398 PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10399 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 10400 # R/R 128 10401 PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10402 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 10403 10404 10405 # R/M 256 10406 PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10407 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 10408 # R/R 256 10409 PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10410 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 10411 } 10412 { 10413 ICLASS : VFNMSUB213SD 10414 EXCEPTIONS: avx-type-3 10415 CPL : 3 10416 CATEGORY : VFMA 10417 EXTENSION : FMA 10418 ATTRIBUTES: MXCSR simd_scalar 10419 # R/M 128 10420 PATTERN : VV1 0xAF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10421 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 10422 # R/R 128 10423 PATTERN : VV1 0xAF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10424 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 10425 10426 } 10427 { 10428 ICLASS : VFNMSUB213SS 10429 EXCEPTIONS: avx-type-3 10430 CPL : 3 10431 CATEGORY : VFMA 10432 EXTENSION : FMA 10433 ATTRIBUTES: MXCSR simd_scalar 10434 # R/M 128 10435 PATTERN : VV1 0xAF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10436 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 10437 # R/R 128 10438 PATTERN : VV1 0xAF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10439 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 10440 } 10441 10442 { 10443 ICLASS : VFNMSUB231PD 10444 EXCEPTIONS: avx-type-2 10445 CPL : 3 10446 CATEGORY : VFMA 10447 EXTENSION : FMA 10448 ATTRIBUTES: MXCSR 10449 # R/M 128 10450 PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10451 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 10452 # R/R 128 10453 PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10454 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 10455 10456 10457 # R/M 256 10458 PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10459 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 10460 # R/R 256 10461 PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10462 OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 10463 10464 } 10465 { 10466 ICLASS : VFNMSUB231PS 10467 EXCEPTIONS: avx-type-2 10468 CPL : 3 10469 CATEGORY : VFMA 10470 EXTENSION : FMA 10471 ATTRIBUTES: MXCSR 10472 # R/M 128 10473 PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10474 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 10475 # R/R 128 10476 PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10477 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 10478 10479 # R/M 256 10480 PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10481 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 10482 # R/R 256 10483 PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10484 OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 10485 10486 } 10487 { 10488 ICLASS : VFNMSUB231SD 10489 EXCEPTIONS: avx-type-3 10490 CPL : 3 10491 CATEGORY : VFMA 10492 EXTENSION : FMA 10493 ATTRIBUTES: MXCSR simd_scalar 10494 # R/M 128 10495 PATTERN : VV1 0xBF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10496 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 10497 # R/R 128 10498 PATTERN : VV1 0xBF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10499 OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 10500 10501 } 10502 { 10503 ICLASS : VFNMSUB231SS 10504 EXCEPTIONS: avx-type-3 10505 CPL : 3 10506 CATEGORY : VFMA 10507 EXTENSION : FMA 10508 ATTRIBUTES: MXCSR simd_scalar 10509 # R/M 128 10510 PATTERN : VV1 0xBF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 10511 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 10512 # R/R 128 10513 PATTERN : VV1 0xBF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] 10514 OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 10515 10516 } 10517 10518 ################################################### 10519 10520 10521 10522 10523 10524 10525 ###FILE: ./datafiles/bdw/adox-adcx.xed.txt 10526 10527 #BEGIN_LEGAL 10528 # 10529 #Copyright (c) 2016 Intel Corporation 10530 # 10531 # Licensed under the Apache License, Version 2.0 (the "License"); 10532 # you may not use this file except in compliance with the License. 10533 # You may obtain a copy of the License at 10534 # 10535 # http://www.apache.org/licenses/LICENSE-2.0 10536 # 10537 # Unless required by applicable law or agreed to in writing, software 10538 # distributed under the License is distributed on an "AS IS" BASIS, 10539 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 10540 # See the License for the specific language governing permissions and 10541 # limitations under the License. 10542 # 10543 #END_LEGAL 10544 INSTRUCTIONS():: 10545 10546 { 10547 ICLASS : ADCX 10548 CPL : 3 10549 CATEGORY : ADOX_ADCX 10550 EXTENSION : ADOX_ADCX 10551 ISA_SET : ADOX_ADCX 10552 10553 FLAGS : MUST [ cf-tst cf-mod ] 10554 10555 # reg:rw rm:r 10556 # 32b 10557 PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W0 IMMUNE66() 10558 OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d 10559 PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 IMMUNE66() 10560 OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d 10561 10562 # 64b 10563 PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W1 IMMUNE66() 10564 OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q 10565 PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 IMMUNE66() 10566 OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q 10567 } 10568 10569 10570 10571 { 10572 ICLASS : ADOX 10573 CPL : 3 10574 CATEGORY : ADOX_ADCX 10575 EXTENSION : ADOX_ADCX 10576 ISA_SET : ADOX_ADCX 10577 10578 FLAGS : MUST [ of-tst of-mod ] 10579 10580 # reg:rw rm:r 10581 # 32b 10582 PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66() 10583 OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d 10584 PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66() 10585 OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d 10586 10587 # 64b 10588 PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W1 IMMUNE66() 10589 OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q 10590 PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W1 IMMUNE66() 10591 OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q 10592 } 10593 10594 10595 10596 ###FILE: ./datafiles/bdw/rdseed.xed.txt 10597 10598 #BEGIN_LEGAL 10599 # 10600 #Copyright (c) 2016 Intel Corporation 10601 # 10602 # Licensed under the Apache License, Version 2.0 (the "License"); 10603 # you may not use this file except in compliance with the License. 10604 # You may obtain a copy of the License at 10605 # 10606 # http://www.apache.org/licenses/LICENSE-2.0 10607 # 10608 # Unless required by applicable law or agreed to in writing, software 10609 # distributed under the License is distributed on an "AS IS" BASIS, 10610 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 10611 # See the License for the specific language governing permissions and 10612 # limitations under the License. 10613 # 10614 #END_LEGAL 10615 INSTRUCTIONS():: 10616 10617 { 10618 ICLASS : RDSEED 10619 CPL : 3 10620 CATEGORY : RDSEED 10621 EXTENSION : RDSEED 10622 ISA_SET : RDSEED 10623 FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] 10624 PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining 10625 OPERANDS : REG0=GPRv_B():w 10626 } 10627 10628 10629 10630 ###FILE: ./datafiles/bdw/smap.xed.txt 10631 10632 #BEGIN_LEGAL 10633 # 10634 #Copyright (c) 2016 Intel Corporation 10635 # 10636 # Licensed under the Apache License, Version 2.0 (the "License"); 10637 # you may not use this file except in compliance with the License. 10638 # You may obtain a copy of the License at 10639 # 10640 # http://www.apache.org/licenses/LICENSE-2.0 10641 # 10642 # Unless required by applicable law or agreed to in writing, software 10643 # distributed under the License is distributed on an "AS IS" BASIS, 10644 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 10645 # See the License for the specific language governing permissions and 10646 # limitations under the License. 10647 # 10648 #END_LEGAL 10649 10650 INSTRUCTIONS():: 10651 10652 { 10653 ICLASS : CLAC 10654 CPL : 0 10655 CATEGORY : SMAP 10656 EXTENSION : SMAP 10657 FLAGS : MUST [ ac-0 ] 10658 # 0F 01 CA = 1100_1010 = 11_001_010 10659 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix 10660 OPERANDS : 10661 } 10662 10663 { 10664 ICLASS : STAC 10665 CPL : 0 10666 CATEGORY : SMAP 10667 EXTENSION : SMAP 10668 FLAGS : MUST [ ac-1 ] 10669 # 0F 01 CB = 1100_1011 = 11_001_011 10670 PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix 10671 OPERANDS : 10672 } 10673 10674 10675 10676 ###FILE: ./datafiles/sgx/sgx-isa.xed.txt 10677 10678 #BEGIN_LEGAL 10679 # 10680 #Copyright (c) 2016 Intel Corporation 10681 # 10682 # Licensed under the Apache License, Version 2.0 (the "License"); 10683 # you may not use this file except in compliance with the License. 10684 # You may obtain a copy of the License at 10685 # 10686 # http://www.apache.org/licenses/LICENSE-2.0 10687 # 10688 # Unless required by applicable law or agreed to in writing, software 10689 # distributed under the License is distributed on an "AS IS" BASIS, 10690 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 10691 # See the License for the specific language governing permissions and 10692 # limitations under the License. 10693 # 10694 #END_LEGAL 10695 10696 INSTRUCTIONS():: 10697 10698 # Both read EAX 10699 # Both may read or write or r/w RBX, RCX, RDX 10700 # ENCLU 0f 01 D7 10701 # D7 = 1101 0111 10702 10703 # ENCLS 0f 01 CF 10704 # CF = 1100_1111 10705 10706 10707 10708 { 10709 ICLASS: ENCLU 10710 CPL: 3 10711 CATEGORY: SGX 10712 EXTENSION: SGX 10713 ISA_SET: SGX 10714 COMMENT: May set flags 10715 PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix 10716 OPERANDS: REG0=XED_REG_EAX:r:SUPP \ 10717 REG1=XED_REG_RBX:crw:SUPP \ 10718 REG2=XED_REG_RCX:crw:SUPP \ 10719 REG3=XED_REG_RDX:crw:SUPP 10720 } 10721 10722 { 10723 10724 ICLASS: ENCLS 10725 CPL: 0 10726 CATEGORY: SGX 10727 EXTENSION: SGX 10728 ISA_SET: SGX 10729 COMMENT: May set flags 10730 PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix 10731 OPERANDS: REG0=XED_REG_EAX:r:SUPP \ 10732 REG1=XED_REG_RBX:crw:SUPP \ 10733 REG2=XED_REG_RCX:crw:SUPP \ 10734 REG3=XED_REG_RDX:crw:SUPP 10735 10736 } 10737 10738 10739 ###FILE: ./datafiles/clflushopt/clflushopt.xed.txt 10740 10741 #BEGIN_LEGAL 10742 # 10743 #Copyright (c) 2016 Intel Corporation 10744 # 10745 # Licensed under the Apache License, Version 2.0 (the "License"); 10746 # you may not use this file except in compliance with the License. 10747 # You may obtain a copy of the License at 10748 # 10749 # http://www.apache.org/licenses/LICENSE-2.0 10750 # 10751 # Unless required by applicable law or agreed to in writing, software 10752 # distributed under the License is distributed on an "AS IS" BASIS, 10753 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 10754 # See the License for the specific language governing permissions and 10755 # limitations under the License. 10756 # 10757 #END_LEGAL 10758 10759 INSTRUCTIONS():: 10760 10761 { 10762 ICLASS: CLFLUSHOPT 10763 CPL: 3 10764 CATEGORY: CLFLUSHOPT 10765 EXTENSION: CLFLUSHOPT 10766 ISA_SET: CLFLUSHOPT 10767 ATTRIBUTES: PREFETCH # check TSX-friendlyness 10768 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM() 10769 OPERANDS : MEM0:r:mprefetch 10770 } 10771 10772 10773 10774 10775 ###FILE: ./datafiles/pku/pku-isa.xed.txt 10776 10777 #BEGIN_LEGAL 10778 # 10779 #Copyright (c) 2016 Intel Corporation 10780 # 10781 # Licensed under the Apache License, Version 2.0 (the "License"); 10782 # you may not use this file except in compliance with the License. 10783 # You may obtain a copy of the License at 10784 # 10785 # http://www.apache.org/licenses/LICENSE-2.0 10786 # 10787 # Unless required by applicable law or agreed to in writing, software 10788 # distributed under the License is distributed on an "AS IS" BASIS, 10789 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 10790 # See the License for the specific language governing permissions and 10791 # limitations under the License. 10792 # 10793 #END_LEGAL 10794 10795 10796 INSTRUCTIONS():: 10797 10798 { 10799 ICLASS: RDPKRU 10800 CPL: 3 10801 CATEGORY: PKU 10802 EXTENSION: PKU 10803 ISA_SET: PKU 10804 ATTRIBUTES: 10805 PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix 10806 OPERANDS: REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:r:SUPP 10807 } 10808 10809 10810 { 10811 ICLASS: WRPKRU 10812 CPL: 3 10813 CATEGORY: PKU 10814 EXTENSION: PKU 10815 ISA_SET: PKU 10816 ATTRIBUTES: 10817 PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix 10818 OPERANDS: REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP 10819 } 10820 10821 10822 10823 ###FILE: ./datafiles/clwb/clwb.xed.txt 10824 10825 #BEGIN_LEGAL 10826 # 10827 #Copyright (c) 2016 Intel Corporation 10828 # 10829 # Licensed under the Apache License, Version 2.0 (the "License"); 10830 # you may not use this file except in compliance with the License. 10831 # You may obtain a copy of the License at 10832 # 10833 # http://www.apache.org/licenses/LICENSE-2.0 10834 # 10835 # Unless required by applicable law or agreed to in writing, software 10836 # distributed under the License is distributed on an "AS IS" BASIS, 10837 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 10838 # See the License for the specific language governing permissions and 10839 # limitations under the License. 10840 # 10841 #END_LEGAL 10842 10843 INSTRUCTIONS():: 10844 10845 { 10846 ICLASS: CLWB 10847 CPL: 3 10848 CATEGORY: CLWB 10849 EXTENSION: CLWB 10850 ISA_SET: CLWB 10851 ATTRIBUTES: PREFETCH # check TSX-friendlyness 10852 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() 10853 OPERANDS : MEM0:r:mprefetch 10854 } 10855 10856 10857 10858 10859 ###FILE: ./datafiles/knl/knl-fixup.txt 10860 10861 #BEGIN_LEGAL 10862 # 10863 #Copyright (c) 2016 Intel Corporation 10864 # 10865 # Licensed under the Apache License, Version 2.0 (the "License"); 10866 # you may not use this file except in compliance with the License. 10867 # You may obtain a copy of the License at 10868 # 10869 # http://www.apache.org/licenses/LICENSE-2.0 10870 # 10871 # Unless required by applicable law or agreed to in writing, software 10872 # distributed under the License is distributed on an "AS IS" BASIS, 10873 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 10874 # See the License for the specific language governing permissions and 10875 # limitations under the License. 10876 # 10877 #END_LEGAL 10878 10879 INSTRUCTIONS():: 10880 UDELETE : PREFETCH_RESERVED_0F0Dr2 10881 10882 10883 ###FILE: ./datafiles/knl/knl-isa.xed.txt 10884 10885 #BEGIN_LEGAL 10886 # 10887 #Copyright (c) 2016 Intel Corporation 10888 # 10889 # Licensed under the Apache License, Version 2.0 (the "License"); 10890 # you may not use this file except in compliance with the License. 10891 # You may obtain a copy of the License at 10892 # 10893 # http://www.apache.org/licenses/LICENSE-2.0 10894 # 10895 # Unless required by applicable law or agreed to in writing, software 10896 # distributed under the License is distributed on an "AS IS" BASIS, 10897 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 10898 # See the License for the specific language governing permissions and 10899 # limitations under the License. 10900 # 10901 #END_LEGAL 10902 # 10903 # 10904 # 10905 # ***** GENERATED FILE -- DO NOT EDIT! ***** 10906 # ***** GENERATED FILE -- DO NOT EDIT! ***** 10907 # ***** GENERATED FILE -- DO NOT EDIT! ***** 10908 # 10909 # 10910 # 10911 EVEX_INSTRUCTIONS():: 10912 # EMITTING VEXP2PD (VEXP2PD-512-1) 10913 { 10914 ICLASS: VEXP2PD 10915 CPL: 3 10916 CATEGORY: AVX512 10917 EXTENSION: AVX512EVEX 10918 ISA_SET: AVX512ER_512 10919 EXCEPTIONS: AVX512-E2 10920 REAL_OPCODE: Y 10921 ATTRIBUTES: MXCSR MASKOP_EVEX 10922 PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 10923 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 10924 IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 10925 } 10926 10927 { 10928 ICLASS: VEXP2PD 10929 CPL: 3 10930 CATEGORY: AVX512 10931 EXTENSION: AVX512EVEX 10932 ISA_SET: AVX512ER_512 10933 EXCEPTIONS: AVX512-E2 10934 REAL_OPCODE: Y 10935 ATTRIBUTES: MXCSR MASKOP_EVEX 10936 PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 10937 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 10938 IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 10939 } 10940 10941 { 10942 ICLASS: VEXP2PD 10943 CPL: 3 10944 CATEGORY: AVX512 10945 EXTENSION: AVX512EVEX 10946 ISA_SET: AVX512ER_512 10947 EXCEPTIONS: AVX512-E2 10948 REAL_OPCODE: Y 10949 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 10950 PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 10951 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 10952 IFORM: VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER 10953 } 10954 10955 10956 # EMITTING VEXP2PS (VEXP2PS-512-1) 10957 { 10958 ICLASS: VEXP2PS 10959 CPL: 3 10960 CATEGORY: AVX512 10961 EXTENSION: AVX512EVEX 10962 ISA_SET: AVX512ER_512 10963 EXCEPTIONS: AVX512-E2 10964 REAL_OPCODE: Y 10965 ATTRIBUTES: MXCSR MASKOP_EVEX 10966 PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 10967 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 10968 IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 10969 } 10970 10971 { 10972 ICLASS: VEXP2PS 10973 CPL: 3 10974 CATEGORY: AVX512 10975 EXTENSION: AVX512EVEX 10976 ISA_SET: AVX512ER_512 10977 EXCEPTIONS: AVX512-E2 10978 REAL_OPCODE: Y 10979 ATTRIBUTES: MXCSR MASKOP_EVEX 10980 PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 10981 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 10982 IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 10983 } 10984 10985 { 10986 ICLASS: VEXP2PS 10987 CPL: 3 10988 CATEGORY: AVX512 10989 EXTENSION: AVX512EVEX 10990 ISA_SET: AVX512ER_512 10991 EXCEPTIONS: AVX512-E2 10992 REAL_OPCODE: Y 10993 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 10994 PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 10995 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 10996 IFORM: VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER 10997 } 10998 10999 11000 # EMITTING VGATHERPF0DPD (VGATHERPF0DPD-512-1) 11001 { 11002 ICLASS: VGATHERPF0DPD 11003 CPL: 3 11004 CATEGORY: GATHER 11005 EXTENSION: AVX512EVEX 11006 ISA_SET: AVX512PF_512 11007 EXCEPTIONS: AVX512-E12NP 11008 REAL_OPCODE: Y 11009 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 11010 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 11011 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 11012 IFORM: VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 11013 } 11014 11015 11016 # EMITTING VGATHERPF0DPS (VGATHERPF0DPS-512-1) 11017 { 11018 ICLASS: VGATHERPF0DPS 11019 CPL: 3 11020 CATEGORY: GATHER 11021 EXTENSION: AVX512EVEX 11022 ISA_SET: AVX512PF_512 11023 EXCEPTIONS: AVX512-E12NP 11024 REAL_OPCODE: Y 11025 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 11026 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 11027 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 11028 IFORM: VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 11029 } 11030 11031 11032 # EMITTING VGATHERPF0QPD (VGATHERPF0QPD-512-1) 11033 { 11034 ICLASS: VGATHERPF0QPD 11035 CPL: 3 11036 CATEGORY: GATHER 11037 EXTENSION: AVX512EVEX 11038 ISA_SET: AVX512PF_512 11039 EXCEPTIONS: AVX512-E12NP 11040 REAL_OPCODE: Y 11041 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 11042 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 11043 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 11044 IFORM: VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 11045 } 11046 11047 11048 # EMITTING VGATHERPF0QPS (VGATHERPF0QPS-512-1) 11049 { 11050 ICLASS: VGATHERPF0QPS 11051 CPL: 3 11052 CATEGORY: GATHER 11053 EXTENSION: AVX512EVEX 11054 ISA_SET: AVX512PF_512 11055 EXCEPTIONS: AVX512-E12NP 11056 REAL_OPCODE: Y 11057 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 11058 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 11059 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 11060 IFORM: VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 11061 } 11062 11063 11064 # EMITTING VGATHERPF1DPD (VGATHERPF1DPD-512-1) 11065 { 11066 ICLASS: VGATHERPF1DPD 11067 CPL: 3 11068 CATEGORY: GATHER 11069 EXTENSION: AVX512EVEX 11070 ISA_SET: AVX512PF_512 11071 EXCEPTIONS: AVX512-E12NP 11072 REAL_OPCODE: Y 11073 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 11074 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 11075 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 11076 IFORM: VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 11077 } 11078 11079 11080 # EMITTING VGATHERPF1DPS (VGATHERPF1DPS-512-1) 11081 { 11082 ICLASS: VGATHERPF1DPS 11083 CPL: 3 11084 CATEGORY: GATHER 11085 EXTENSION: AVX512EVEX 11086 ISA_SET: AVX512PF_512 11087 EXCEPTIONS: AVX512-E12NP 11088 REAL_OPCODE: Y 11089 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 11090 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 11091 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 11092 IFORM: VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 11093 } 11094 11095 11096 # EMITTING VGATHERPF1QPD (VGATHERPF1QPD-512-1) 11097 { 11098 ICLASS: VGATHERPF1QPD 11099 CPL: 3 11100 CATEGORY: GATHER 11101 EXTENSION: AVX512EVEX 11102 ISA_SET: AVX512PF_512 11103 EXCEPTIONS: AVX512-E12NP 11104 REAL_OPCODE: Y 11105 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 11106 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 11107 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 11108 IFORM: VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 11109 } 11110 11111 11112 # EMITTING VGATHERPF1QPS (VGATHERPF1QPS-512-1) 11113 { 11114 ICLASS: VGATHERPF1QPS 11115 CPL: 3 11116 CATEGORY: GATHER 11117 EXTENSION: AVX512EVEX 11118 ISA_SET: AVX512PF_512 11119 EXCEPTIONS: AVX512-E12NP 11120 REAL_OPCODE: Y 11121 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT 11122 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 11123 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 11124 IFORM: VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 11125 } 11126 11127 11128 # EMITTING VRCP28PD (VRCP28PD-512-1) 11129 { 11130 ICLASS: VRCP28PD 11131 CPL: 3 11132 CATEGORY: AVX512 11133 EXTENSION: AVX512EVEX 11134 ISA_SET: AVX512ER_512 11135 EXCEPTIONS: AVX512-E2 11136 REAL_OPCODE: Y 11137 ATTRIBUTES: MXCSR MASKOP_EVEX 11138 PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 11139 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 11140 IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 11141 } 11142 11143 { 11144 ICLASS: VRCP28PD 11145 CPL: 3 11146 CATEGORY: AVX512 11147 EXTENSION: AVX512EVEX 11148 ISA_SET: AVX512ER_512 11149 EXCEPTIONS: AVX512-E2 11150 REAL_OPCODE: Y 11151 ATTRIBUTES: MXCSR MASKOP_EVEX 11152 PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 11153 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 11154 IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 11155 } 11156 11157 { 11158 ICLASS: VRCP28PD 11159 CPL: 3 11160 CATEGORY: AVX512 11161 EXTENSION: AVX512EVEX 11162 ISA_SET: AVX512ER_512 11163 EXCEPTIONS: AVX512-E2 11164 REAL_OPCODE: Y 11165 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 11166 PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 11167 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 11168 IFORM: VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER 11169 } 11170 11171 11172 # EMITTING VRCP28PS (VRCP28PS-512-1) 11173 { 11174 ICLASS: VRCP28PS 11175 CPL: 3 11176 CATEGORY: AVX512 11177 EXTENSION: AVX512EVEX 11178 ISA_SET: AVX512ER_512 11179 EXCEPTIONS: AVX512-E2 11180 REAL_OPCODE: Y 11181 ATTRIBUTES: MXCSR MASKOP_EVEX 11182 PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 11183 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 11184 IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 11185 } 11186 11187 { 11188 ICLASS: VRCP28PS 11189 CPL: 3 11190 CATEGORY: AVX512 11191 EXTENSION: AVX512EVEX 11192 ISA_SET: AVX512ER_512 11193 EXCEPTIONS: AVX512-E2 11194 REAL_OPCODE: Y 11195 ATTRIBUTES: MXCSR MASKOP_EVEX 11196 PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 11197 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 11198 IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 11199 } 11200 11201 { 11202 ICLASS: VRCP28PS 11203 CPL: 3 11204 CATEGORY: AVX512 11205 EXTENSION: AVX512EVEX 11206 ISA_SET: AVX512ER_512 11207 EXCEPTIONS: AVX512-E2 11208 REAL_OPCODE: Y 11209 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 11210 PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 11211 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 11212 IFORM: VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER 11213 } 11214 11215 11216 # EMITTING VRCP28SD (VRCP28SD-128-1) 11217 { 11218 ICLASS: VRCP28SD 11219 CPL: 3 11220 CATEGORY: AVX512 11221 EXTENSION: AVX512EVEX 11222 ISA_SET: AVX512ER_SCALAR 11223 EXCEPTIONS: AVX512-E3 11224 REAL_OPCODE: Y 11225 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 11226 PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 11227 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 11228 IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER 11229 } 11230 11231 { 11232 ICLASS: VRCP28SD 11233 CPL: 3 11234 CATEGORY: AVX512 11235 EXTENSION: AVX512EVEX 11236 ISA_SET: AVX512ER_SCALAR 11237 EXCEPTIONS: AVX512-E3 11238 REAL_OPCODE: Y 11239 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 11240 PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 11241 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 11242 IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER 11243 } 11244 11245 { 11246 ICLASS: VRCP28SD 11247 CPL: 3 11248 CATEGORY: AVX512 11249 EXTENSION: AVX512EVEX 11250 ISA_SET: AVX512ER_SCALAR 11251 EXCEPTIONS: AVX512-E3 11252 REAL_OPCODE: Y 11253 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 11254 PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 11255 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 11256 IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER 11257 } 11258 11259 11260 # EMITTING VRCP28SS (VRCP28SS-128-1) 11261 { 11262 ICLASS: VRCP28SS 11263 CPL: 3 11264 CATEGORY: AVX512 11265 EXTENSION: AVX512EVEX 11266 ISA_SET: AVX512ER_SCALAR 11267 EXCEPTIONS: AVX512-E3 11268 REAL_OPCODE: Y 11269 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 11270 PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 11271 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 11272 IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER 11273 } 11274 11275 { 11276 ICLASS: VRCP28SS 11277 CPL: 3 11278 CATEGORY: AVX512 11279 EXTENSION: AVX512EVEX 11280 ISA_SET: AVX512ER_SCALAR 11281 EXCEPTIONS: AVX512-E3 11282 REAL_OPCODE: Y 11283 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 11284 PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 11285 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 11286 IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER 11287 } 11288 11289 { 11290 ICLASS: VRCP28SS 11291 CPL: 3 11292 CATEGORY: AVX512 11293 EXTENSION: AVX512EVEX 11294 ISA_SET: AVX512ER_SCALAR 11295 EXCEPTIONS: AVX512-E3 11296 REAL_OPCODE: Y 11297 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 11298 PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 11299 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 11300 IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER 11301 } 11302 11303 11304 # EMITTING VRSQRT28PD (VRSQRT28PD-512-1) 11305 { 11306 ICLASS: VRSQRT28PD 11307 CPL: 3 11308 CATEGORY: AVX512 11309 EXTENSION: AVX512EVEX 11310 ISA_SET: AVX512ER_512 11311 EXCEPTIONS: AVX512-E2 11312 REAL_OPCODE: Y 11313 ATTRIBUTES: MXCSR MASKOP_EVEX 11314 PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 11315 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 11316 IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 11317 } 11318 11319 { 11320 ICLASS: VRSQRT28PD 11321 CPL: 3 11322 CATEGORY: AVX512 11323 EXTENSION: AVX512EVEX 11324 ISA_SET: AVX512ER_512 11325 EXCEPTIONS: AVX512-E2 11326 REAL_OPCODE: Y 11327 ATTRIBUTES: MXCSR MASKOP_EVEX 11328 PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 11329 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 11330 IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 11331 } 11332 11333 { 11334 ICLASS: VRSQRT28PD 11335 CPL: 3 11336 CATEGORY: AVX512 11337 EXTENSION: AVX512EVEX 11338 ISA_SET: AVX512ER_512 11339 EXCEPTIONS: AVX512-E2 11340 REAL_OPCODE: Y 11341 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 11342 PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 11343 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 11344 IFORM: VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER 11345 } 11346 11347 11348 # EMITTING VRSQRT28PS (VRSQRT28PS-512-1) 11349 { 11350 ICLASS: VRSQRT28PS 11351 CPL: 3 11352 CATEGORY: AVX512 11353 EXTENSION: AVX512EVEX 11354 ISA_SET: AVX512ER_512 11355 EXCEPTIONS: AVX512-E2 11356 REAL_OPCODE: Y 11357 ATTRIBUTES: MXCSR MASKOP_EVEX 11358 PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 11359 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 11360 IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 11361 } 11362 11363 { 11364 ICLASS: VRSQRT28PS 11365 CPL: 3 11366 CATEGORY: AVX512 11367 EXTENSION: AVX512EVEX 11368 ISA_SET: AVX512ER_512 11369 EXCEPTIONS: AVX512-E2 11370 REAL_OPCODE: Y 11371 ATTRIBUTES: MXCSR MASKOP_EVEX 11372 PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 11373 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 11374 IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 11375 } 11376 11377 { 11378 ICLASS: VRSQRT28PS 11379 CPL: 3 11380 CATEGORY: AVX512 11381 EXTENSION: AVX512EVEX 11382 ISA_SET: AVX512ER_512 11383 EXCEPTIONS: AVX512-E2 11384 REAL_OPCODE: Y 11385 ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 11386 PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 11387 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 11388 IFORM: VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER 11389 } 11390 11391 11392 # EMITTING VRSQRT28SD (VRSQRT28SD-128-1) 11393 { 11394 ICLASS: VRSQRT28SD 11395 CPL: 3 11396 CATEGORY: AVX512 11397 EXTENSION: AVX512EVEX 11398 ISA_SET: AVX512ER_SCALAR 11399 EXCEPTIONS: AVX512-E3 11400 REAL_OPCODE: Y 11401 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 11402 PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 11403 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 11404 IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER 11405 } 11406 11407 { 11408 ICLASS: VRSQRT28SD 11409 CPL: 3 11410 CATEGORY: AVX512 11411 EXTENSION: AVX512EVEX 11412 ISA_SET: AVX512ER_SCALAR 11413 EXCEPTIONS: AVX512-E3 11414 REAL_OPCODE: Y 11415 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 11416 PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 11417 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 11418 IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER 11419 } 11420 11421 { 11422 ICLASS: VRSQRT28SD 11423 CPL: 3 11424 CATEGORY: AVX512 11425 EXTENSION: AVX512EVEX 11426 ISA_SET: AVX512ER_SCALAR 11427 EXCEPTIONS: AVX512-E3 11428 REAL_OPCODE: Y 11429 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 11430 PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 11431 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 11432 IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER 11433 } 11434 11435 11436 # EMITTING VRSQRT28SS (VRSQRT28SS-128-1) 11437 { 11438 ICLASS: VRSQRT28SS 11439 CPL: 3 11440 CATEGORY: AVX512 11441 EXTENSION: AVX512EVEX 11442 ISA_SET: AVX512ER_SCALAR 11443 EXCEPTIONS: AVX512-E3 11444 REAL_OPCODE: Y 11445 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 11446 PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 11447 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 11448 IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER 11449 } 11450 11451 { 11452 ICLASS: VRSQRT28SS 11453 CPL: 3 11454 CATEGORY: AVX512 11455 EXTENSION: AVX512EVEX 11456 ISA_SET: AVX512ER_SCALAR 11457 EXCEPTIONS: AVX512-E3 11458 REAL_OPCODE: Y 11459 ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX 11460 PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 11461 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 11462 IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER 11463 } 11464 11465 { 11466 ICLASS: VRSQRT28SS 11467 CPL: 3 11468 CATEGORY: AVX512 11469 EXTENSION: AVX512EVEX 11470 ISA_SET: AVX512ER_SCALAR 11471 EXCEPTIONS: AVX512-E3 11472 REAL_OPCODE: Y 11473 ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR 11474 PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 11475 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 11476 IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER 11477 } 11478 11479 11480 # EMITTING VSCATTERPF0DPD (VSCATTERPF0DPD-512-1) 11481 { 11482 ICLASS: VSCATTERPF0DPD 11483 CPL: 3 11484 CATEGORY: SCATTER 11485 EXTENSION: AVX512EVEX 11486 ISA_SET: AVX512PF_512 11487 EXCEPTIONS: AVX512-E12NP 11488 REAL_OPCODE: Y 11489 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 11490 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 11491 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 11492 IFORM: VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 11493 } 11494 11495 11496 # EMITTING VSCATTERPF0DPS (VSCATTERPF0DPS-512-1) 11497 { 11498 ICLASS: VSCATTERPF0DPS 11499 CPL: 3 11500 CATEGORY: SCATTER 11501 EXTENSION: AVX512EVEX 11502 ISA_SET: AVX512PF_512 11503 EXCEPTIONS: AVX512-E12NP 11504 REAL_OPCODE: Y 11505 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 11506 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 11507 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 11508 IFORM: VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 11509 } 11510 11511 11512 # EMITTING VSCATTERPF0QPD (VSCATTERPF0QPD-512-1) 11513 { 11514 ICLASS: VSCATTERPF0QPD 11515 CPL: 3 11516 CATEGORY: SCATTER 11517 EXTENSION: AVX512EVEX 11518 ISA_SET: AVX512PF_512 11519 EXCEPTIONS: AVX512-E12NP 11520 REAL_OPCODE: Y 11521 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 11522 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 11523 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 11524 IFORM: VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 11525 } 11526 11527 11528 # EMITTING VSCATTERPF0QPS (VSCATTERPF0QPS-512-1) 11529 { 11530 ICLASS: VSCATTERPF0QPS 11531 CPL: 3 11532 CATEGORY: SCATTER 11533 EXTENSION: AVX512EVEX 11534 ISA_SET: AVX512PF_512 11535 EXCEPTIONS: AVX512-E12NP 11536 REAL_OPCODE: Y 11537 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 11538 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 11539 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 11540 IFORM: VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 11541 } 11542 11543 11544 # EMITTING VSCATTERPF1DPD (VSCATTERPF1DPD-512-1) 11545 { 11546 ICLASS: VSCATTERPF1DPD 11547 CPL: 3 11548 CATEGORY: SCATTER 11549 EXTENSION: AVX512EVEX 11550 ISA_SET: AVX512PF_512 11551 EXCEPTIONS: AVX512-E12NP 11552 REAL_OPCODE: Y 11553 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 11554 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 11555 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 11556 IFORM: VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 11557 } 11558 11559 11560 # EMITTING VSCATTERPF1DPS (VSCATTERPF1DPS-512-1) 11561 { 11562 ICLASS: VSCATTERPF1DPS 11563 CPL: 3 11564 CATEGORY: SCATTER 11565 EXTENSION: AVX512EVEX 11566 ISA_SET: AVX512PF_512 11567 EXCEPTIONS: AVX512-E12NP 11568 REAL_OPCODE: Y 11569 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 11570 PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 11571 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 11572 IFORM: VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 11573 } 11574 11575 11576 # EMITTING VSCATTERPF1QPD (VSCATTERPF1QPD-512-1) 11577 { 11578 ICLASS: VSCATTERPF1QPD 11579 CPL: 3 11580 CATEGORY: SCATTER 11581 EXTENSION: AVX512EVEX 11582 ISA_SET: AVX512PF_512 11583 EXCEPTIONS: AVX512-E12NP 11584 REAL_OPCODE: Y 11585 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 11586 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 11587 OPERANDS: MEM0:r:b:f64 REG0=MASKNOT0():rw:mskw 11588 IFORM: VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 11589 } 11590 11591 11592 # EMITTING VSCATTERPF1QPS (VSCATTERPF1QPS-512-1) 11593 { 11594 ICLASS: VSCATTERPF1QPS 11595 CPL: 3 11596 CATEGORY: SCATTER 11597 EXTENSION: AVX512EVEX 11598 ISA_SET: AVX512PF_512 11599 EXCEPTIONS: AVX512-E12NP 11600 REAL_OPCODE: Y 11601 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT 11602 PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 11603 OPERANDS: MEM0:r:b:f32 REG0=MASKNOT0():rw:mskw 11604 IFORM: VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 11605 } 11606 11607 11608 INSTRUCTIONS():: 11609 # EMITTING PREFETCHWT1 (PREFETCHWT1-N/A-1) 11610 { 11611 ICLASS: PREFETCHWT1 11612 CPL: 3 11613 CATEGORY: PREFETCHWT1 11614 EXTENSION: PREFETCHWT1 11615 ISA_SET: PREFETCHWT1 11616 REAL_OPCODE: Y 11617 ATTRIBUTES: PREFETCH 11618 PATTERN: 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() 11619 OPERANDS: MEM0:r:b:u8 11620 IFORM: PREFETCHWT1_MEMu8 11621 } 11622 11623 11624 11625 11626 ###FILE: ./datafiles/4fmaps-512/4fmaps-512-isa.xed.txt 11627 11628 #BEGIN_LEGAL 11629 # 11630 #Copyright (c) 2016 Intel Corporation 11631 # 11632 # Licensed under the Apache License, Version 2.0 (the "License"); 11633 # you may not use this file except in compliance with the License. 11634 # You may obtain a copy of the License at 11635 # 11636 # http://www.apache.org/licenses/LICENSE-2.0 11637 # 11638 # Unless required by applicable law or agreed to in writing, software 11639 # distributed under the License is distributed on an "AS IS" BASIS, 11640 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 11641 # See the License for the specific language governing permissions and 11642 # limitations under the License. 11643 # 11644 #END_LEGAL 11645 # 11646 # 11647 # 11648 # ***** GENERATED FILE -- DO NOT EDIT! ***** 11649 # ***** GENERATED FILE -- DO NOT EDIT! ***** 11650 # ***** GENERATED FILE -- DO NOT EDIT! ***** 11651 # 11652 # 11653 # 11654 EVEX_INSTRUCTIONS():: 11655 # EMITTING V4FMADDPS (V4FMADDPS-512-1) 11656 { 11657 ICLASS: V4FMADDPS 11658 CPL: 3 11659 CATEGORY: AVX512_4FMAPS 11660 EXTENSION: AVX512EVEX 11661 ISA_SET: AVX512_4FMAPS_512 11662 EXCEPTIONS: AVX512-E2 11663 REAL_OPCODE: Y 11664 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX 11665 PATTERN: EVV 0x9A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() 11666 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 11667 IFORM: V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 11668 } 11669 11670 11671 # EMITTING V4FMADDSS (V4FMADDSS-128-1) 11672 { 11673 ICLASS: V4FMADDSS 11674 CPL: 3 11675 CATEGORY: AVX512_4FMAPS 11676 EXTENSION: AVX512EVEX 11677 ISA_SET: AVX512_4FMAPS_SCALAR 11678 EXCEPTIONS: AVX512-E2 11679 REAL_OPCODE: Y 11680 ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR 11681 PATTERN: EVV 0x9B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() 11682 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 11683 IFORM: V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 11684 } 11685 11686 11687 # EMITTING V4FNMADDPS (V4FNMADDPS-512-1) 11688 { 11689 ICLASS: V4FNMADDPS 11690 CPL: 3 11691 CATEGORY: AVX512_4FMAPS 11692 EXTENSION: AVX512EVEX 11693 ISA_SET: AVX512_4FMAPS_512 11694 EXCEPTIONS: AVX512-E2 11695 REAL_OPCODE: Y 11696 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX 11697 PATTERN: EVV 0xAA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() 11698 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 11699 IFORM: V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 11700 } 11701 11702 11703 # EMITTING V4FNMADDSS (V4FNMADDSS-128-1) 11704 { 11705 ICLASS: V4FNMADDSS 11706 CPL: 3 11707 CATEGORY: AVX512_4FMAPS 11708 EXTENSION: AVX512EVEX 11709 ISA_SET: AVX512_4FMAPS_SCALAR 11710 EXCEPTIONS: AVX512-E2 11711 REAL_OPCODE: Y 11712 ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR 11713 PATTERN: EVV 0xAB VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() 11714 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 11715 IFORM: V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 11716 } 11717 11718 11719 11720 11721 ###FILE: ./datafiles/4vnniw-512/4vnniw-512-isa.xed.txt 11722 11723 #BEGIN_LEGAL 11724 # 11725 #Copyright (c) 2016 Intel Corporation 11726 # 11727 # Licensed under the Apache License, Version 2.0 (the "License"); 11728 # you may not use this file except in compliance with the License. 11729 # You may obtain a copy of the License at 11730 # 11731 # http://www.apache.org/licenses/LICENSE-2.0 11732 # 11733 # Unless required by applicable law or agreed to in writing, software 11734 # distributed under the License is distributed on an "AS IS" BASIS, 11735 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 11736 # See the License for the specific language governing permissions and 11737 # limitations under the License. 11738 # 11739 #END_LEGAL 11740 # 11741 # 11742 # 11743 # ***** GENERATED FILE -- DO NOT EDIT! ***** 11744 # ***** GENERATED FILE -- DO NOT EDIT! ***** 11745 # ***** GENERATED FILE -- DO NOT EDIT! ***** 11746 # 11747 # 11748 # 11749 EVEX_INSTRUCTIONS():: 11750 # EMITTING VP4DPWSSD (VP4DPWSSD-512-1) 11751 { 11752 ICLASS: VP4DPWSSD 11753 CPL: 3 11754 CATEGORY: AVX512_4VNNIW 11755 EXTENSION: AVX512EVEX 11756 ISA_SET: AVX512_4VNNIW_512 11757 EXCEPTIONS: AVX512-E4 11758 REAL_OPCODE: Y 11759 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX 11760 PATTERN: EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() 11761 OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 11762 IFORM: VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 11763 } 11764 11765 11766 # EMITTING VP4DPWSSDS (VP4DPWSSDS-512-1) 11767 { 11768 ICLASS: VP4DPWSSDS 11769 CPL: 3 11770 CATEGORY: AVX512_4VNNIW 11771 EXTENSION: AVX512EVEX 11772 ISA_SET: AVX512_4VNNIW_512 11773 EXCEPTIONS: AVX512-E4 11774 REAL_OPCODE: Y 11775 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX 11776 PATTERN: EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() 11777 OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 11778 IFORM: VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 11779 } 11780 11781 11782 11783 11784 ###FILE: ./datafiles/vpopcntdq-512/vpopcntdq-512-isa.xed.txt 11785 11786 #BEGIN_LEGAL 11787 # 11788 #Copyright (c) 2016 Intel Corporation 11789 # 11790 # Licensed under the Apache License, Version 2.0 (the "License"); 11791 # you may not use this file except in compliance with the License. 11792 # You may obtain a copy of the License at 11793 # 11794 # http://www.apache.org/licenses/LICENSE-2.0 11795 # 11796 # Unless required by applicable law or agreed to in writing, software 11797 # distributed under the License is distributed on an "AS IS" BASIS, 11798 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 11799 # See the License for the specific language governing permissions and 11800 # limitations under the License. 11801 # 11802 #END_LEGAL 11803 # 11804 # 11805 # 11806 # ***** GENERATED FILE -- DO NOT EDIT! ***** 11807 # ***** GENERATED FILE -- DO NOT EDIT! ***** 11808 # ***** GENERATED FILE -- DO NOT EDIT! ***** 11809 # 11810 # 11811 # 11812 EVEX_INSTRUCTIONS():: 11813 # EMITTING VPOPCNTD (VPOPCNTD-512-1) 11814 { 11815 ICLASS: VPOPCNTD 11816 CPL: 3 11817 CATEGORY: AVX512 11818 EXTENSION: AVX512EVEX 11819 ISA_SET: AVX512_VPOPCNTDQ_512 11820 EXCEPTIONS: AVX512-E4 11821 REAL_OPCODE: Y 11822 ATTRIBUTES: MASKOP_EVEX 11823 PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 11824 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 11825 IFORM: VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 11826 } 11827 11828 { 11829 ICLASS: VPOPCNTD 11830 CPL: 3 11831 CATEGORY: AVX512 11832 EXTENSION: AVX512EVEX 11833 ISA_SET: AVX512_VPOPCNTDQ_512 11834 EXCEPTIONS: AVX512-E4 11835 REAL_OPCODE: Y 11836 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 11837 PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 11838 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 11839 IFORM: VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 11840 } 11841 11842 11843 # EMITTING VPOPCNTQ (VPOPCNTQ-512-1) 11844 { 11845 ICLASS: VPOPCNTQ 11846 CPL: 3 11847 CATEGORY: AVX512 11848 EXTENSION: AVX512EVEX 11849 ISA_SET: AVX512_VPOPCNTDQ_512 11850 EXCEPTIONS: AVX512-E4 11851 REAL_OPCODE: Y 11852 ATTRIBUTES: MASKOP_EVEX 11853 PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 11854 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 11855 IFORM: VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 11856 } 11857 11858 { 11859 ICLASS: VPOPCNTQ 11860 CPL: 3 11861 CATEGORY: AVX512 11862 EXTENSION: AVX512EVEX 11863 ISA_SET: AVX512_VPOPCNTDQ_512 11864 EXCEPTIONS: AVX512-E4 11865 REAL_OPCODE: Y 11866 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 11867 PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 11868 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 11869 IFORM: VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 11870 } 11871 11872 11873 11874 11875 ###FILE: ./datafiles/avx512f/avx512-foundation-isa.xed.txt 11876 #BEGIN_LEGAL 11877 # 11878 #Copyright (c) 2019 Intel Corporation 11879 # 11880 # Licensed under the Apache License, Version 2.0 (the "License"); 11881 # you may not use this file except in compliance with the License. 11882 # You may obtain a copy of the License at 11883 # 11884 # http://www.apache.org/licenses/LICENSE-2.0 11885 # 11886 # Unless required by applicable law or agreed to in writing, software 11887 # distributed under the License is distributed on an "AS IS" BASIS, 11888 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 11889 # See the License for the specific language governing permissions and 11890 # limitations under the License. 11891 # 11892 #END_LEGAL 11893 # 11894 # 11895 # 11896 # ***** GENERATED FILE -- DO NOT EDIT! ***** 11897 # ***** GENERATED FILE -- DO NOT EDIT! ***** 11898 # ***** GENERATED FILE -- DO NOT EDIT! ***** 11899 # 11900 # 11901 # 11902 EVEX_INSTRUCTIONS():: 11903 # EMITTING VADDPD (VADDPD-512-1) 11904 { 11905 ICLASS: VADDPD 11906 CPL: 3 11907 CATEGORY: AVX512 11908 EXTENSION: AVX512EVEX 11909 ISA_SET: AVX512F_512 11910 EXCEPTIONS: AVX512-E2 11911 REAL_OPCODE: Y 11912 ATTRIBUTES: MASKOP_EVEX MXCSR 11913 PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 11914 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 11915 IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 11916 } 11917 11918 { 11919 ICLASS: VADDPD 11920 CPL: 3 11921 CATEGORY: AVX512 11922 EXTENSION: AVX512EVEX 11923 ISA_SET: AVX512F_512 11924 EXCEPTIONS: AVX512-E2 11925 REAL_OPCODE: Y 11926 ATTRIBUTES: MASKOP_EVEX MXCSR 11927 PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 11928 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 11929 IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 11930 } 11931 11932 { 11933 ICLASS: VADDPD 11934 CPL: 3 11935 CATEGORY: AVX512 11936 EXTENSION: AVX512EVEX 11937 ISA_SET: AVX512F_512 11938 EXCEPTIONS: AVX512-E2 11939 REAL_OPCODE: Y 11940 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 11941 PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 11942 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 11943 IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 11944 } 11945 11946 11947 # EMITTING VADDPS (VADDPS-512-1) 11948 { 11949 ICLASS: VADDPS 11950 CPL: 3 11951 CATEGORY: AVX512 11952 EXTENSION: AVX512EVEX 11953 ISA_SET: AVX512F_512 11954 EXCEPTIONS: AVX512-E2 11955 REAL_OPCODE: Y 11956 ATTRIBUTES: MASKOP_EVEX MXCSR 11957 PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 11958 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 11959 IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 11960 } 11961 11962 { 11963 ICLASS: VADDPS 11964 CPL: 3 11965 CATEGORY: AVX512 11966 EXTENSION: AVX512EVEX 11967 ISA_SET: AVX512F_512 11968 EXCEPTIONS: AVX512-E2 11969 REAL_OPCODE: Y 11970 ATTRIBUTES: MASKOP_EVEX MXCSR 11971 PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 11972 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 11973 IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 11974 } 11975 11976 { 11977 ICLASS: VADDPS 11978 CPL: 3 11979 CATEGORY: AVX512 11980 EXTENSION: AVX512EVEX 11981 ISA_SET: AVX512F_512 11982 EXCEPTIONS: AVX512-E2 11983 REAL_OPCODE: Y 11984 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 11985 PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 11986 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 11987 IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 11988 } 11989 11990 11991 # EMITTING VADDSD (VADDSD-128-1) 11992 { 11993 ICLASS: VADDSD 11994 CPL: 3 11995 CATEGORY: AVX512 11996 EXTENSION: AVX512EVEX 11997 ISA_SET: AVX512F_SCALAR 11998 EXCEPTIONS: AVX512-E3 11999 REAL_OPCODE: Y 12000 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 12001 PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 12002 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 12003 IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 12004 } 12005 12006 { 12007 ICLASS: VADDSD 12008 CPL: 3 12009 CATEGORY: AVX512 12010 EXTENSION: AVX512EVEX 12011 ISA_SET: AVX512F_SCALAR 12012 EXCEPTIONS: AVX512-E3 12013 REAL_OPCODE: Y 12014 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 12015 PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 12016 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 12017 IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 12018 } 12019 12020 { 12021 ICLASS: VADDSD 12022 CPL: 3 12023 CATEGORY: AVX512 12024 EXTENSION: AVX512EVEX 12025 ISA_SET: AVX512F_SCALAR 12026 EXCEPTIONS: AVX512-E3 12027 REAL_OPCODE: Y 12028 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 12029 PATTERN: EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 12030 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 12031 IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 12032 } 12033 12034 12035 # EMITTING VADDSS (VADDSS-128-1) 12036 { 12037 ICLASS: VADDSS 12038 CPL: 3 12039 CATEGORY: AVX512 12040 EXTENSION: AVX512EVEX 12041 ISA_SET: AVX512F_SCALAR 12042 EXCEPTIONS: AVX512-E3 12043 REAL_OPCODE: Y 12044 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 12045 PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 12046 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 12047 IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 12048 } 12049 12050 { 12051 ICLASS: VADDSS 12052 CPL: 3 12053 CATEGORY: AVX512 12054 EXTENSION: AVX512EVEX 12055 ISA_SET: AVX512F_SCALAR 12056 EXCEPTIONS: AVX512-E3 12057 REAL_OPCODE: Y 12058 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 12059 PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 12060 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 12061 IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 12062 } 12063 12064 { 12065 ICLASS: VADDSS 12066 CPL: 3 12067 CATEGORY: AVX512 12068 EXTENSION: AVX512EVEX 12069 ISA_SET: AVX512F_SCALAR 12070 EXCEPTIONS: AVX512-E3 12071 REAL_OPCODE: Y 12072 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 12073 PATTERN: EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 12074 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 12075 IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 12076 } 12077 12078 12079 # EMITTING VALIGND (VALIGND-512-1) 12080 { 12081 ICLASS: VALIGND 12082 CPL: 3 12083 CATEGORY: AVX512 12084 EXTENSION: AVX512EVEX 12085 ISA_SET: AVX512F_512 12086 EXCEPTIONS: AVX512-E4NF 12087 REAL_OPCODE: Y 12088 ATTRIBUTES: MASKOP_EVEX 12089 PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 12090 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b 12091 IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 12092 } 12093 12094 { 12095 ICLASS: VALIGND 12096 CPL: 3 12097 CATEGORY: AVX512 12098 EXTENSION: AVX512EVEX 12099 ISA_SET: AVX512F_512 12100 EXCEPTIONS: AVX512-E4NF 12101 REAL_OPCODE: Y 12102 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 12103 PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 12104 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 12105 IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 12106 } 12107 12108 12109 # EMITTING VALIGNQ (VALIGNQ-512-1) 12110 { 12111 ICLASS: VALIGNQ 12112 CPL: 3 12113 CATEGORY: AVX512 12114 EXTENSION: AVX512EVEX 12115 ISA_SET: AVX512F_512 12116 EXCEPTIONS: AVX512-E4NF 12117 REAL_OPCODE: Y 12118 ATTRIBUTES: MASKOP_EVEX 12119 PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 12120 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b 12121 IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 12122 } 12123 12124 { 12125 ICLASS: VALIGNQ 12126 CPL: 3 12127 CATEGORY: AVX512 12128 EXTENSION: AVX512EVEX 12129 ISA_SET: AVX512F_512 12130 EXCEPTIONS: AVX512-E4NF 12131 REAL_OPCODE: Y 12132 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 12133 PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 12134 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 12135 IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 12136 } 12137 12138 12139 # EMITTING VBLENDMPD (VBLENDMPD-512-1) 12140 { 12141 ICLASS: VBLENDMPD 12142 CPL: 3 12143 CATEGORY: BLEND 12144 EXTENSION: AVX512EVEX 12145 ISA_SET: AVX512F_512 12146 EXCEPTIONS: AVX512-E4 12147 REAL_OPCODE: Y 12148 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 12149 PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 12150 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 12151 IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 12152 } 12153 12154 { 12155 ICLASS: VBLENDMPD 12156 CPL: 3 12157 CATEGORY: BLEND 12158 EXTENSION: AVX512EVEX 12159 ISA_SET: AVX512F_512 12160 EXCEPTIONS: AVX512-E4 12161 REAL_OPCODE: Y 12162 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL 12163 PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 12164 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 12165 IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 12166 } 12167 12168 12169 # EMITTING VBLENDMPS (VBLENDMPS-512-1) 12170 { 12171 ICLASS: VBLENDMPS 12172 CPL: 3 12173 CATEGORY: BLEND 12174 EXTENSION: AVX512EVEX 12175 ISA_SET: AVX512F_512 12176 EXCEPTIONS: AVX512-E4 12177 REAL_OPCODE: Y 12178 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 12179 PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 12180 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 12181 IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 12182 } 12183 12184 { 12185 ICLASS: VBLENDMPS 12186 CPL: 3 12187 CATEGORY: BLEND 12188 EXTENSION: AVX512EVEX 12189 ISA_SET: AVX512F_512 12190 EXCEPTIONS: AVX512-E4 12191 REAL_OPCODE: Y 12192 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL 12193 PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 12194 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 12195 IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 12196 } 12197 12198 12199 # EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-512-1) 12200 { 12201 ICLASS: VBROADCASTF32X4 12202 CPL: 3 12203 CATEGORY: BROADCAST 12204 EXTENSION: AVX512EVEX 12205 ISA_SET: AVX512F_512 12206 EXCEPTIONS: AVX512-E6 12207 REAL_OPCODE: Y 12208 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 12209 PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() 12210 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO16_32 12211 IFORM: VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 12212 } 12213 12214 12215 # EMITTING VBROADCASTF64X4 (VBROADCASTF64X4-512-1) 12216 { 12217 ICLASS: VBROADCASTF64X4 12218 CPL: 3 12219 CATEGORY: BROADCAST 12220 EXTENSION: AVX512EVEX 12221 ISA_SET: AVX512F_512 12222 EXCEPTIONS: AVX512-E6 12223 REAL_OPCODE: Y 12224 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 12225 PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() 12226 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 EMX_BROADCAST_4TO8_64 12227 IFORM: VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 12228 } 12229 12230 12231 # EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-512-1) 12232 { 12233 ICLASS: VBROADCASTI32X4 12234 CPL: 3 12235 CATEGORY: BROADCAST 12236 EXTENSION: AVX512EVEX 12237 ISA_SET: AVX512F_512 12238 EXCEPTIONS: AVX512-E6 12239 REAL_OPCODE: Y 12240 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 12241 PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() 12242 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO16_32 12243 IFORM: VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 12244 } 12245 12246 12247 # EMITTING VBROADCASTI64X4 (VBROADCASTI64X4-512-1) 12248 { 12249 ICLASS: VBROADCASTI64X4 12250 CPL: 3 12251 CATEGORY: BROADCAST 12252 EXTENSION: AVX512EVEX 12253 ISA_SET: AVX512F_512 12254 EXCEPTIONS: AVX512-E6 12255 REAL_OPCODE: Y 12256 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 12257 PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() 12258 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 EMX_BROADCAST_4TO8_64 12259 IFORM: VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 12260 } 12261 12262 12263 # EMITTING VBROADCASTSD (VBROADCASTSD-512-1) 12264 { 12265 ICLASS: VBROADCASTSD 12266 CPL: 3 12267 CATEGORY: BROADCAST 12268 EXTENSION: AVX512EVEX 12269 ISA_SET: AVX512F_512 12270 EXCEPTIONS: AVX512-E6 12271 REAL_OPCODE: Y 12272 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 12273 PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() 12274 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO8_64 12275 IFORM: VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 12276 } 12277 12278 12279 # EMITTING VBROADCASTSD (VBROADCASTSD-512-2) 12280 { 12281 ICLASS: VBROADCASTSD 12282 CPL: 3 12283 CATEGORY: BROADCAST 12284 EXTENSION: AVX512EVEX 12285 ISA_SET: AVX512F_512 12286 EXCEPTIONS: AVX512-E6 12287 REAL_OPCODE: Y 12288 ATTRIBUTES: MASKOP_EVEX 12289 PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 12290 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO8_64 12291 IFORM: VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 12292 } 12293 12294 12295 # EMITTING VBROADCASTSS (VBROADCASTSS-512-1) 12296 { 12297 ICLASS: VBROADCASTSS 12298 CPL: 3 12299 CATEGORY: BROADCAST 12300 EXTENSION: AVX512EVEX 12301 ISA_SET: AVX512F_512 12302 EXCEPTIONS: AVX512-E6 12303 REAL_OPCODE: Y 12304 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 12305 PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() 12306 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO16_32 12307 IFORM: VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 12308 } 12309 12310 12311 # EMITTING VBROADCASTSS (VBROADCASTSS-512-2) 12312 { 12313 ICLASS: VBROADCASTSS 12314 CPL: 3 12315 CATEGORY: BROADCAST 12316 EXTENSION: AVX512EVEX 12317 ISA_SET: AVX512F_512 12318 EXCEPTIONS: AVX512-E6 12319 REAL_OPCODE: Y 12320 ATTRIBUTES: MASKOP_EVEX 12321 PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 12322 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO16_32 12323 IFORM: VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 12324 } 12325 12326 12327 # EMITTING VCMPPD (VCMPPD-512-1) 12328 { 12329 ICLASS: VCMPPD 12330 CPL: 3 12331 CATEGORY: AVX512 12332 EXTENSION: AVX512EVEX 12333 ISA_SET: AVX512F_512 12334 EXCEPTIONS: AVX512-E2 12335 REAL_OPCODE: Y 12336 ATTRIBUTES: MASKOP_EVEX MXCSR 12337 PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() 12338 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 12339 IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 12340 } 12341 12342 { 12343 ICLASS: VCMPPD 12344 CPL: 3 12345 CATEGORY: AVX512 12346 EXTENSION: AVX512EVEX 12347 ISA_SET: AVX512F_512 12348 EXCEPTIONS: AVX512-E2 12349 REAL_OPCODE: Y 12350 ATTRIBUTES: MASKOP_EVEX MXCSR 12351 PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 ZEROING=0 UIMM8() 12352 OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 12353 IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 12354 } 12355 12356 { 12357 ICLASS: VCMPPD 12358 CPL: 3 12359 CATEGORY: AVX512 12360 EXTENSION: AVX512EVEX 12361 ISA_SET: AVX512F_512 12362 EXCEPTIONS: AVX512-E2 12363 REAL_OPCODE: Y 12364 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 12365 PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 12366 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 12367 IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 12368 } 12369 12370 12371 # EMITTING VCMPPS (VCMPPS-512-1) 12372 { 12373 ICLASS: VCMPPS 12374 CPL: 3 12375 CATEGORY: AVX512 12376 EXTENSION: AVX512EVEX 12377 ISA_SET: AVX512F_512 12378 EXCEPTIONS: AVX512-E2 12379 REAL_OPCODE: Y 12380 ATTRIBUTES: MASKOP_EVEX MXCSR 12381 PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() 12382 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 12383 IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 12384 } 12385 12386 { 12387 ICLASS: VCMPPS 12388 CPL: 3 12389 CATEGORY: AVX512 12390 EXTENSION: AVX512EVEX 12391 ISA_SET: AVX512F_512 12392 EXCEPTIONS: AVX512-E2 12393 REAL_OPCODE: Y 12394 ATTRIBUTES: MASKOP_EVEX MXCSR 12395 PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8() 12396 OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 12397 IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 12398 } 12399 12400 { 12401 ICLASS: VCMPPS 12402 CPL: 3 12403 CATEGORY: AVX512 12404 EXTENSION: AVX512EVEX 12405 ISA_SET: AVX512F_512 12406 EXCEPTIONS: AVX512-E2 12407 REAL_OPCODE: Y 12408 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 12409 PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 12410 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 12411 IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 12412 } 12413 12414 12415 # EMITTING VCMPSD (VCMPSD-128-1) 12416 { 12417 ICLASS: VCMPSD 12418 CPL: 3 12419 CATEGORY: AVX512 12420 EXTENSION: AVX512EVEX 12421 ISA_SET: AVX512F_SCALAR 12422 EXCEPTIONS: AVX512-E3 12423 REAL_OPCODE: Y 12424 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 12425 PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 ZEROING=0 UIMM8() 12426 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 12427 IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 12428 } 12429 12430 { 12431 ICLASS: VCMPSD 12432 CPL: 3 12433 CATEGORY: AVX512 12434 EXTENSION: AVX512EVEX 12435 ISA_SET: AVX512F_SCALAR 12436 EXCEPTIONS: AVX512-E3 12437 REAL_OPCODE: Y 12438 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 12439 PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 ZEROING=0 UIMM8() 12440 OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 12441 IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 12442 } 12443 12444 { 12445 ICLASS: VCMPSD 12446 CPL: 3 12447 CATEGORY: AVX512 12448 EXTENSION: AVX512EVEX 12449 ISA_SET: AVX512F_SCALAR 12450 EXCEPTIONS: AVX512-E3 12451 REAL_OPCODE: Y 12452 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 12453 PATTERN: EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 12454 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 12455 IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 12456 } 12457 12458 12459 # EMITTING VCMPSS (VCMPSS-128-1) 12460 { 12461 ICLASS: VCMPSS 12462 CPL: 3 12463 CATEGORY: AVX512 12464 EXTENSION: AVX512EVEX 12465 ISA_SET: AVX512F_SCALAR 12466 EXCEPTIONS: AVX512-E3 12467 REAL_OPCODE: Y 12468 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 12469 PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 UIMM8() 12470 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 12471 IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 12472 } 12473 12474 { 12475 ICLASS: VCMPSS 12476 CPL: 3 12477 CATEGORY: AVX512 12478 EXTENSION: AVX512EVEX 12479 ISA_SET: AVX512F_SCALAR 12480 EXCEPTIONS: AVX512-E3 12481 REAL_OPCODE: Y 12482 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 12483 PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8() 12484 OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 12485 IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 12486 } 12487 12488 { 12489 ICLASS: VCMPSS 12490 CPL: 3 12491 CATEGORY: AVX512 12492 EXTENSION: AVX512EVEX 12493 ISA_SET: AVX512F_SCALAR 12494 EXCEPTIONS: AVX512-E3 12495 REAL_OPCODE: Y 12496 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 12497 PATTERN: EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 12498 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 12499 IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 12500 } 12501 12502 12503 # EMITTING VCOMISD (VCOMISD-128-1) 12504 { 12505 ICLASS: VCOMISD 12506 CPL: 3 12507 CATEGORY: AVX512 12508 EXTENSION: AVX512EVEX 12509 ISA_SET: AVX512F_SCALAR 12510 EXCEPTIONS: AVX512-E3NF 12511 REAL_OPCODE: Y 12512 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 12513 ATTRIBUTES: MXCSR SIMD_SCALAR 12514 PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 12515 OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 12516 IFORM: VCOMISD_XMMf64_XMMf64_AVX512 12517 } 12518 12519 { 12520 ICLASS: VCOMISD 12521 CPL: 3 12522 CATEGORY: AVX512 12523 EXTENSION: AVX512EVEX 12524 ISA_SET: AVX512F_SCALAR 12525 EXCEPTIONS: AVX512-E3NF 12526 REAL_OPCODE: Y 12527 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 12528 ATTRIBUTES: MXCSR SIMD_SCALAR 12529 PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 12530 OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 12531 IFORM: VCOMISD_XMMf64_XMMf64_AVX512 12532 } 12533 12534 { 12535 ICLASS: VCOMISD 12536 CPL: 3 12537 CATEGORY: AVX512 12538 EXTENSION: AVX512EVEX 12539 ISA_SET: AVX512F_SCALAR 12540 EXCEPTIONS: AVX512-E3NF 12541 REAL_OPCODE: Y 12542 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 12543 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR 12544 PATTERN: EVV 0x2F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 12545 OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 12546 IFORM: VCOMISD_XMMf64_MEMf64_AVX512 12547 } 12548 12549 12550 # EMITTING VCOMISS (VCOMISS-128-1) 12551 { 12552 ICLASS: VCOMISS 12553 CPL: 3 12554 CATEGORY: AVX512 12555 EXTENSION: AVX512EVEX 12556 ISA_SET: AVX512F_SCALAR 12557 EXCEPTIONS: AVX512-E3NF 12558 REAL_OPCODE: Y 12559 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 12560 ATTRIBUTES: MXCSR SIMD_SCALAR 12561 PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 12562 OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 12563 IFORM: VCOMISS_XMMf32_XMMf32_AVX512 12564 } 12565 12566 { 12567 ICLASS: VCOMISS 12568 CPL: 3 12569 CATEGORY: AVX512 12570 EXTENSION: AVX512EVEX 12571 ISA_SET: AVX512F_SCALAR 12572 EXCEPTIONS: AVX512-E3NF 12573 REAL_OPCODE: Y 12574 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 12575 ATTRIBUTES: MXCSR SIMD_SCALAR 12576 PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 12577 OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 12578 IFORM: VCOMISS_XMMf32_XMMf32_AVX512 12579 } 12580 12581 { 12582 ICLASS: VCOMISS 12583 CPL: 3 12584 CATEGORY: AVX512 12585 EXTENSION: AVX512EVEX 12586 ISA_SET: AVX512F_SCALAR 12587 EXCEPTIONS: AVX512-E3NF 12588 REAL_OPCODE: Y 12589 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 12590 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR 12591 PATTERN: EVV 0x2F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() 12592 OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 12593 IFORM: VCOMISS_XMMf32_MEMf32_AVX512 12594 } 12595 12596 12597 # EMITTING VCOMPRESSPD (VCOMPRESSPD-512-1) 12598 { 12599 ICLASS: VCOMPRESSPD 12600 CPL: 3 12601 CATEGORY: COMPRESS 12602 EXTENSION: AVX512EVEX 12603 ISA_SET: AVX512F_512 12604 EXCEPTIONS: AVX512-E4 12605 REAL_OPCODE: Y 12606 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 12607 PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 12608 OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 12609 IFORM: VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 12610 } 12611 12612 12613 # EMITTING VCOMPRESSPD (VCOMPRESSPD-512-2) 12614 { 12615 ICLASS: VCOMPRESSPD 12616 CPL: 3 12617 CATEGORY: COMPRESS 12618 EXTENSION: AVX512EVEX 12619 ISA_SET: AVX512F_512 12620 EXCEPTIONS: AVX512-E4 12621 REAL_OPCODE: Y 12622 ATTRIBUTES: MASKOP_EVEX 12623 PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 12624 OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 12625 IFORM: VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 12626 } 12627 12628 12629 # EMITTING VCOMPRESSPS (VCOMPRESSPS-512-1) 12630 { 12631 ICLASS: VCOMPRESSPS 12632 CPL: 3 12633 CATEGORY: COMPRESS 12634 EXTENSION: AVX512EVEX 12635 ISA_SET: AVX512F_512 12636 EXCEPTIONS: AVX512-E4 12637 REAL_OPCODE: Y 12638 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 12639 PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 12640 OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 12641 IFORM: VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 12642 } 12643 12644 12645 # EMITTING VCOMPRESSPS (VCOMPRESSPS-512-2) 12646 { 12647 ICLASS: VCOMPRESSPS 12648 CPL: 3 12649 CATEGORY: COMPRESS 12650 EXTENSION: AVX512EVEX 12651 ISA_SET: AVX512F_512 12652 EXCEPTIONS: AVX512-E4 12653 REAL_OPCODE: Y 12654 ATTRIBUTES: MASKOP_EVEX 12655 PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 12656 OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 12657 IFORM: VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 12658 } 12659 12660 12661 # EMITTING VCVTDQ2PD (VCVTDQ2PD-512-1) 12662 { 12663 ICLASS: VCVTDQ2PD 12664 CPL: 3 12665 CATEGORY: CONVERT 12666 EXTENSION: AVX512EVEX 12667 ISA_SET: AVX512F_512 12668 EXCEPTIONS: AVX512-E5 12669 REAL_OPCODE: Y 12670 ATTRIBUTES: MASKOP_EVEX 12671 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 12672 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 12673 IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 12674 } 12675 12676 { 12677 ICLASS: VCVTDQ2PD 12678 CPL: 3 12679 CATEGORY: CONVERT 12680 EXTENSION: AVX512EVEX 12681 ISA_SET: AVX512F_512 12682 EXCEPTIONS: AVX512-E5 12683 REAL_OPCODE: Y 12684 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 12685 PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 12686 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 12687 IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 12688 } 12689 12690 12691 # EMITTING VCVTDQ2PS (VCVTDQ2PS-512-1) 12692 { 12693 ICLASS: VCVTDQ2PS 12694 CPL: 3 12695 CATEGORY: CONVERT 12696 EXTENSION: AVX512EVEX 12697 ISA_SET: AVX512F_512 12698 EXCEPTIONS: AVX512-E2 12699 REAL_OPCODE: Y 12700 ATTRIBUTES: MASKOP_EVEX MXCSR 12701 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 12702 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 12703 IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 12704 } 12705 12706 { 12707 ICLASS: VCVTDQ2PS 12708 CPL: 3 12709 CATEGORY: CONVERT 12710 EXTENSION: AVX512EVEX 12711 ISA_SET: AVX512F_512 12712 EXCEPTIONS: AVX512-E2 12713 REAL_OPCODE: Y 12714 ATTRIBUTES: MASKOP_EVEX MXCSR 12715 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 12716 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 12717 IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 12718 } 12719 12720 { 12721 ICLASS: VCVTDQ2PS 12722 CPL: 3 12723 CATEGORY: CONVERT 12724 EXTENSION: AVX512EVEX 12725 ISA_SET: AVX512F_512 12726 EXCEPTIONS: AVX512-E2 12727 REAL_OPCODE: Y 12728 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 12729 PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 12730 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 12731 IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 12732 } 12733 12734 12735 # EMITTING VCVTPD2DQ (VCVTPD2DQ-512-1) 12736 { 12737 ICLASS: VCVTPD2DQ 12738 CPL: 3 12739 CATEGORY: CONVERT 12740 EXTENSION: AVX512EVEX 12741 ISA_SET: AVX512F_512 12742 EXCEPTIONS: AVX512-E2 12743 REAL_OPCODE: Y 12744 ATTRIBUTES: MASKOP_EVEX MXCSR 12745 PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 12746 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 12747 IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 12748 } 12749 12750 { 12751 ICLASS: VCVTPD2DQ 12752 CPL: 3 12753 CATEGORY: CONVERT 12754 EXTENSION: AVX512EVEX 12755 ISA_SET: AVX512F_512 12756 EXCEPTIONS: AVX512-E2 12757 REAL_OPCODE: Y 12758 ATTRIBUTES: MASKOP_EVEX MXCSR 12759 PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 12760 OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 12761 IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 12762 } 12763 12764 { 12765 ICLASS: VCVTPD2DQ 12766 CPL: 3 12767 CATEGORY: CONVERT 12768 EXTENSION: AVX512EVEX 12769 ISA_SET: AVX512F_512 12770 EXCEPTIONS: AVX512-E2 12771 REAL_OPCODE: Y 12772 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 12773 PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 12774 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 12775 IFORM: VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 12776 } 12777 12778 12779 # EMITTING VCVTPD2PS (VCVTPD2PS-512-1) 12780 { 12781 ICLASS: VCVTPD2PS 12782 CPL: 3 12783 CATEGORY: CONVERT 12784 EXTENSION: AVX512EVEX 12785 ISA_SET: AVX512F_512 12786 EXCEPTIONS: AVX512-E2 12787 REAL_OPCODE: Y 12788 ATTRIBUTES: MASKOP_EVEX MXCSR 12789 PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 12790 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 12791 IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 12792 } 12793 12794 { 12795 ICLASS: VCVTPD2PS 12796 CPL: 3 12797 CATEGORY: CONVERT 12798 EXTENSION: AVX512EVEX 12799 ISA_SET: AVX512F_512 12800 EXCEPTIONS: AVX512-E2 12801 REAL_OPCODE: Y 12802 ATTRIBUTES: MASKOP_EVEX MXCSR 12803 PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 12804 OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 12805 IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 12806 } 12807 12808 { 12809 ICLASS: VCVTPD2PS 12810 CPL: 3 12811 CATEGORY: CONVERT 12812 EXTENSION: AVX512EVEX 12813 ISA_SET: AVX512F_512 12814 EXCEPTIONS: AVX512-E2 12815 REAL_OPCODE: Y 12816 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 12817 PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 12818 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 12819 IFORM: VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 12820 } 12821 12822 12823 # EMITTING VCVTPD2UDQ (VCVTPD2UDQ-512-1) 12824 { 12825 ICLASS: VCVTPD2UDQ 12826 CPL: 3 12827 CATEGORY: CONVERT 12828 EXTENSION: AVX512EVEX 12829 ISA_SET: AVX512F_512 12830 EXCEPTIONS: AVX512-E2 12831 REAL_OPCODE: Y 12832 ATTRIBUTES: MASKOP_EVEX MXCSR 12833 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 12834 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 12835 IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 12836 } 12837 12838 { 12839 ICLASS: VCVTPD2UDQ 12840 CPL: 3 12841 CATEGORY: CONVERT 12842 EXTENSION: AVX512EVEX 12843 ISA_SET: AVX512F_512 12844 EXCEPTIONS: AVX512-E2 12845 REAL_OPCODE: Y 12846 ATTRIBUTES: MASKOP_EVEX MXCSR 12847 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 12848 OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 12849 IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 12850 } 12851 12852 { 12853 ICLASS: VCVTPD2UDQ 12854 CPL: 3 12855 CATEGORY: CONVERT 12856 EXTENSION: AVX512EVEX 12857 ISA_SET: AVX512F_512 12858 EXCEPTIONS: AVX512-E2 12859 REAL_OPCODE: Y 12860 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 12861 PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 12862 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 12863 IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 12864 } 12865 12866 12867 # EMITTING VCVTPH2PS (VCVTPH2PS-512-1) 12868 { 12869 ICLASS: VCVTPH2PS 12870 CPL: 3 12871 CATEGORY: CONVERT 12872 EXTENSION: AVX512EVEX 12873 ISA_SET: AVX512F_512 12874 EXCEPTIONS: AVX512-E11 12875 REAL_OPCODE: Y 12876 ATTRIBUTES: MASKOP_EVEX MXCSR 12877 PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 12878 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 12879 IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 12880 } 12881 12882 { 12883 ICLASS: VCVTPH2PS 12884 CPL: 3 12885 CATEGORY: CONVERT 12886 EXTENSION: AVX512EVEX 12887 ISA_SET: AVX512F_512 12888 EXCEPTIONS: AVX512-E11 12889 REAL_OPCODE: Y 12890 ATTRIBUTES: MASKOP_EVEX MXCSR 12891 PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 12892 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 12893 IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 12894 } 12895 12896 { 12897 ICLASS: VCVTPH2PS 12898 CPL: 3 12899 CATEGORY: CONVERT 12900 EXTENSION: AVX512EVEX 12901 ISA_SET: AVX512F_512 12902 EXCEPTIONS: AVX512-E11 12903 REAL_OPCODE: Y 12904 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM 12905 PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 12906 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f16 12907 IFORM: VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 12908 } 12909 12910 12911 # EMITTING VCVTPS2DQ (VCVTPS2DQ-512-1) 12912 { 12913 ICLASS: VCVTPS2DQ 12914 CPL: 3 12915 CATEGORY: CONVERT 12916 EXTENSION: AVX512EVEX 12917 ISA_SET: AVX512F_512 12918 EXCEPTIONS: AVX512-E2 12919 REAL_OPCODE: Y 12920 ATTRIBUTES: MASKOP_EVEX MXCSR 12921 PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 12922 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 12923 IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 12924 } 12925 12926 { 12927 ICLASS: VCVTPS2DQ 12928 CPL: 3 12929 CATEGORY: CONVERT 12930 EXTENSION: AVX512EVEX 12931 ISA_SET: AVX512F_512 12932 EXCEPTIONS: AVX512-E2 12933 REAL_OPCODE: Y 12934 ATTRIBUTES: MASKOP_EVEX MXCSR 12935 PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 12936 OPERANDS: REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 12937 IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 12938 } 12939 12940 { 12941 ICLASS: VCVTPS2DQ 12942 CPL: 3 12943 CATEGORY: CONVERT 12944 EXTENSION: AVX512EVEX 12945 ISA_SET: AVX512F_512 12946 EXCEPTIONS: AVX512-E2 12947 REAL_OPCODE: Y 12948 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 12949 PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 12950 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 12951 IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 12952 } 12953 12954 12955 # EMITTING VCVTPS2PD (VCVTPS2PD-512-1) 12956 { 12957 ICLASS: VCVTPS2PD 12958 CPL: 3 12959 CATEGORY: CONVERT 12960 EXTENSION: AVX512EVEX 12961 ISA_SET: AVX512F_512 12962 EXCEPTIONS: AVX512-E3 12963 REAL_OPCODE: Y 12964 ATTRIBUTES: MASKOP_EVEX MXCSR 12965 PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 12966 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 12967 IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 12968 } 12969 12970 { 12971 ICLASS: VCVTPS2PD 12972 CPL: 3 12973 CATEGORY: CONVERT 12974 EXTENSION: AVX512EVEX 12975 ISA_SET: AVX512F_512 12976 EXCEPTIONS: AVX512-E3 12977 REAL_OPCODE: Y 12978 ATTRIBUTES: MASKOP_EVEX MXCSR 12979 PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 12980 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 12981 IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 12982 } 12983 12984 { 12985 ICLASS: VCVTPS2PD 12986 CPL: 3 12987 CATEGORY: CONVERT 12988 EXTENSION: AVX512EVEX 12989 ISA_SET: AVX512F_512 12990 EXCEPTIONS: AVX512-E3 12991 REAL_OPCODE: Y 12992 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 12993 PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 12994 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 12995 IFORM: VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 12996 } 12997 12998 12999 # EMITTING VCVTPS2PH (VCVTPS2PH-512-1) 13000 { 13001 ICLASS: VCVTPS2PH 13002 CPL: 3 13003 CATEGORY: CONVERT 13004 EXTENSION: AVX512EVEX 13005 ISA_SET: AVX512F_512 13006 EXCEPTIONS: AVX512-E11NF 13007 REAL_OPCODE: Y 13008 ATTRIBUTES: MASKOP_EVEX MXCSR 13009 PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 13010 OPERANDS: REG0=YMM_B3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b 13011 IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 13012 } 13013 13014 { 13015 ICLASS: VCVTPS2PH 13016 CPL: 3 13017 CATEGORY: CONVERT 13018 EXTENSION: AVX512EVEX 13019 ISA_SET: AVX512F_512 13020 EXCEPTIONS: AVX512-E11NF 13021 REAL_OPCODE: Y 13022 ATTRIBUTES: MASKOP_EVEX MXCSR 13023 PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() 13024 OPERANDS: REG0=YMM_B3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b 13025 IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 13026 } 13027 13028 13029 # EMITTING VCVTPS2PH (VCVTPS2PH-512-2) 13030 { 13031 ICLASS: VCVTPS2PH 13032 CPL: 3 13033 CATEGORY: CONVERT 13034 EXTENSION: AVX512EVEX 13035 ISA_SET: AVX512F_512 13036 EXCEPTIONS: AVX512-E11 13037 REAL_OPCODE: Y 13038 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM 13039 PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() 13040 OPERANDS: MEM0:w:qq:f16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b 13041 IFORM: VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 13042 } 13043 13044 13045 # EMITTING VCVTPS2UDQ (VCVTPS2UDQ-512-1) 13046 { 13047 ICLASS: VCVTPS2UDQ 13048 CPL: 3 13049 CATEGORY: CONVERT 13050 EXTENSION: AVX512EVEX 13051 ISA_SET: AVX512F_512 13052 EXCEPTIONS: AVX512-E2 13053 REAL_OPCODE: Y 13054 ATTRIBUTES: MASKOP_EVEX MXCSR 13055 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 13056 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 13057 IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 13058 } 13059 13060 { 13061 ICLASS: VCVTPS2UDQ 13062 CPL: 3 13063 CATEGORY: CONVERT 13064 EXTENSION: AVX512EVEX 13065 ISA_SET: AVX512F_512 13066 EXCEPTIONS: AVX512-E2 13067 REAL_OPCODE: Y 13068 ATTRIBUTES: MASKOP_EVEX MXCSR 13069 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 13070 OPERANDS: REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 13071 IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 13072 } 13073 13074 { 13075 ICLASS: VCVTPS2UDQ 13076 CPL: 3 13077 CATEGORY: CONVERT 13078 EXTENSION: AVX512EVEX 13079 ISA_SET: AVX512F_512 13080 EXCEPTIONS: AVX512-E2 13081 REAL_OPCODE: Y 13082 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 13083 PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 13084 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 13085 IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 13086 } 13087 13088 13089 # EMITTING VCVTSD2SI (VCVTSD2SI-128-1) 13090 { 13091 ICLASS: VCVTSD2SI 13092 CPL: 3 13093 CATEGORY: CONVERT 13094 EXTENSION: AVX512EVEX 13095 ISA_SET: AVX512F_SCALAR 13096 EXCEPTIONS: AVX512-E3NF 13097 REAL_OPCODE: Y 13098 ATTRIBUTES: MXCSR SIMD_SCALAR 13099 PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 13100 OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 13101 IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 13102 PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13103 OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 13104 IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 13105 } 13106 13107 { 13108 ICLASS: VCVTSD2SI 13109 CPL: 3 13110 CATEGORY: CONVERT 13111 EXTENSION: AVX512EVEX 13112 ISA_SET: AVX512F_SCALAR 13113 EXCEPTIONS: AVX512-E3NF 13114 REAL_OPCODE: Y 13115 ATTRIBUTES: MXCSR SIMD_SCALAR 13116 PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 13117 OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 13118 IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 13119 PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13120 OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 13121 IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 13122 } 13123 13124 { 13125 ICLASS: VCVTSD2SI 13126 CPL: 3 13127 CATEGORY: CONVERT 13128 EXTENSION: AVX512EVEX 13129 ISA_SET: AVX512F_SCALAR 13130 EXCEPTIONS: AVX512-E3NF 13131 REAL_OPCODE: Y 13132 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 13133 PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() 13134 OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 13135 IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512 13136 PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE 13137 OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 13138 IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512 13139 } 13140 13141 13142 # EMITTING VCVTSD2SI (VCVTSD2SI-128-2) 13143 { 13144 ICLASS: VCVTSD2SI 13145 CPL: 3 13146 CATEGORY: CONVERT 13147 EXTENSION: AVX512EVEX 13148 ISA_SET: AVX512F_SCALAR 13149 EXCEPTIONS: AVX512-E3NF 13150 REAL_OPCODE: Y 13151 ATTRIBUTES: MXCSR SIMD_SCALAR 13152 PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13153 OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 13154 IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 13155 } 13156 13157 { 13158 ICLASS: VCVTSD2SI 13159 CPL: 3 13160 CATEGORY: CONVERT 13161 EXTENSION: AVX512EVEX 13162 ISA_SET: AVX512F_SCALAR 13163 EXCEPTIONS: AVX512-E3NF 13164 REAL_OPCODE: Y 13165 ATTRIBUTES: MXCSR SIMD_SCALAR 13166 PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13167 OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 13168 IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 13169 } 13170 13171 { 13172 ICLASS: VCVTSD2SI 13173 CPL: 3 13174 CATEGORY: CONVERT 13175 EXTENSION: AVX512EVEX 13176 ISA_SET: AVX512F_SCALAR 13177 EXCEPTIONS: AVX512-E3NF 13178 REAL_OPCODE: Y 13179 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 13180 PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE 13181 OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 13182 IFORM: VCVTSD2SI_GPR64i64_MEMf64_AVX512 13183 } 13184 13185 13186 # EMITTING VCVTSD2SS (VCVTSD2SS-128-1) 13187 { 13188 ICLASS: VCVTSD2SS 13189 CPL: 3 13190 CATEGORY: CONVERT 13191 EXTENSION: AVX512EVEX 13192 ISA_SET: AVX512F_SCALAR 13193 EXCEPTIONS: AVX512-E3 13194 REAL_OPCODE: Y 13195 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 13196 PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 13197 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 13198 IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 13199 } 13200 13201 { 13202 ICLASS: VCVTSD2SS 13203 CPL: 3 13204 CATEGORY: CONVERT 13205 EXTENSION: AVX512EVEX 13206 ISA_SET: AVX512F_SCALAR 13207 EXCEPTIONS: AVX512-E3 13208 REAL_OPCODE: Y 13209 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 13210 PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 13211 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 13212 IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 13213 } 13214 13215 { 13216 ICLASS: VCVTSD2SS 13217 CPL: 3 13218 CATEGORY: CONVERT 13219 EXTENSION: AVX512EVEX 13220 ISA_SET: AVX512F_SCALAR 13221 EXCEPTIONS: AVX512-E3 13222 REAL_OPCODE: Y 13223 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 13224 PATTERN: EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 13225 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 13226 IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 13227 } 13228 13229 13230 # EMITTING VCVTSD2USI (VCVTSD2USI-128-1) 13231 { 13232 ICLASS: VCVTSD2USI 13233 CPL: 3 13234 CATEGORY: CONVERT 13235 EXTENSION: AVX512EVEX 13236 ISA_SET: AVX512F_SCALAR 13237 EXCEPTIONS: AVX512-E3NF 13238 REAL_OPCODE: Y 13239 ATTRIBUTES: MXCSR SIMD_SCALAR 13240 PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 13241 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 13242 IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 13243 PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13244 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 13245 IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 13246 } 13247 13248 { 13249 ICLASS: VCVTSD2USI 13250 CPL: 3 13251 CATEGORY: CONVERT 13252 EXTENSION: AVX512EVEX 13253 ISA_SET: AVX512F_SCALAR 13254 EXCEPTIONS: AVX512-E3NF 13255 REAL_OPCODE: Y 13256 ATTRIBUTES: MXCSR SIMD_SCALAR 13257 PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 13258 OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 13259 IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 13260 PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13261 OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 13262 IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 13263 } 13264 13265 { 13266 ICLASS: VCVTSD2USI 13267 CPL: 3 13268 CATEGORY: CONVERT 13269 EXTENSION: AVX512EVEX 13270 ISA_SET: AVX512F_SCALAR 13271 EXCEPTIONS: AVX512-E3NF 13272 REAL_OPCODE: Y 13273 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 13274 PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() 13275 OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 13276 IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512 13277 PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE 13278 OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 13279 IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512 13280 } 13281 13282 13283 # EMITTING VCVTSD2USI (VCVTSD2USI-128-2) 13284 { 13285 ICLASS: VCVTSD2USI 13286 CPL: 3 13287 CATEGORY: CONVERT 13288 EXTENSION: AVX512EVEX 13289 ISA_SET: AVX512F_SCALAR 13290 EXCEPTIONS: AVX512-E3NF 13291 REAL_OPCODE: Y 13292 ATTRIBUTES: MXCSR SIMD_SCALAR 13293 PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13294 OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 13295 IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 13296 } 13297 13298 { 13299 ICLASS: VCVTSD2USI 13300 CPL: 3 13301 CATEGORY: CONVERT 13302 EXTENSION: AVX512EVEX 13303 ISA_SET: AVX512F_SCALAR 13304 EXCEPTIONS: AVX512-E3NF 13305 REAL_OPCODE: Y 13306 ATTRIBUTES: MXCSR SIMD_SCALAR 13307 PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13308 OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 13309 IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 13310 } 13311 13312 { 13313 ICLASS: VCVTSD2USI 13314 CPL: 3 13315 CATEGORY: CONVERT 13316 EXTENSION: AVX512EVEX 13317 ISA_SET: AVX512F_SCALAR 13318 EXCEPTIONS: AVX512-E3NF 13319 REAL_OPCODE: Y 13320 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 13321 PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE 13322 OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 13323 IFORM: VCVTSD2USI_GPR64u64_MEMf64_AVX512 13324 } 13325 13326 13327 # EMITTING VCVTSI2SD (VCVTSI2SD-128-1) 13328 { 13329 ICLASS: VCVTSI2SD 13330 CPL: 3 13331 CATEGORY: CONVERT 13332 EXTENSION: AVX512EVEX 13333 ISA_SET: AVX512F_SCALAR 13334 EXCEPTIONS: AVX512-E10NF 13335 REAL_OPCODE: Y 13336 ATTRIBUTES: SIMD_SCALAR 13337 COMMENT: Ignores rounding controls: 32b-INT-to-FP64 does not need rounding 13338 PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 13339 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32 13340 IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 13341 PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 13342 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32 13343 IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 13344 } 13345 13346 { 13347 ICLASS: VCVTSI2SD 13348 CPL: 3 13349 CATEGORY: CONVERT 13350 EXTENSION: AVX512EVEX 13351 ISA_SET: AVX512F_SCALAR 13352 EXCEPTIONS: AVX512-E10NF 13353 REAL_OPCODE: Y 13354 ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER 13355 PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() 13356 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32 13357 IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 13358 PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() 13359 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32 13360 IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 13361 } 13362 13363 13364 # EMITTING VCVTSI2SD (VCVTSI2SD-128-2) 13365 { 13366 ICLASS: VCVTSI2SD 13367 CPL: 3 13368 CATEGORY: CONVERT 13369 EXTENSION: AVX512EVEX 13370 ISA_SET: AVX512F_SCALAR 13371 EXCEPTIONS: AVX512-E3NF 13372 REAL_OPCODE: Y 13373 ATTRIBUTES: MXCSR SIMD_SCALAR 13374 PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 13375 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 13376 IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 13377 } 13378 13379 { 13380 ICLASS: VCVTSI2SD 13381 CPL: 3 13382 CATEGORY: CONVERT 13383 EXTENSION: AVX512EVEX 13384 ISA_SET: AVX512F_SCALAR 13385 EXCEPTIONS: AVX512-E3NF 13386 REAL_OPCODE: Y 13387 ATTRIBUTES: MXCSR SIMD_SCALAR 13388 PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND() 13389 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 13390 IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 13391 } 13392 13393 { 13394 ICLASS: VCVTSI2SD 13395 CPL: 3 13396 CATEGORY: CONVERT 13397 EXTENSION: AVX512EVEX 13398 ISA_SET: AVX512F_SCALAR 13399 EXCEPTIONS: AVX512-E3NF 13400 REAL_OPCODE: Y 13401 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER 13402 PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() 13403 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:i64 13404 IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 13405 } 13406 13407 13408 # EMITTING VCVTSI2SS (VCVTSI2SS-128-1) 13409 { 13410 ICLASS: VCVTSI2SS 13411 CPL: 3 13412 CATEGORY: CONVERT 13413 EXTENSION: AVX512EVEX 13414 ISA_SET: AVX512F_SCALAR 13415 EXCEPTIONS: AVX512-E3NF 13416 REAL_OPCODE: Y 13417 ATTRIBUTES: MXCSR SIMD_SCALAR 13418 PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 13419 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 13420 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 13421 PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 13422 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 13423 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 13424 } 13425 13426 { 13427 ICLASS: VCVTSI2SS 13428 CPL: 3 13429 CATEGORY: CONVERT 13430 EXTENSION: AVX512EVEX 13431 ISA_SET: AVX512F_SCALAR 13432 EXCEPTIONS: AVX512-E3NF 13433 REAL_OPCODE: Y 13434 ATTRIBUTES: MXCSR SIMD_SCALAR 13435 PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 13436 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 13437 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 13438 PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0 13439 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 13440 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 13441 } 13442 13443 { 13444 ICLASS: VCVTSI2SS 13445 CPL: 3 13446 CATEGORY: CONVERT 13447 EXTENSION: AVX512EVEX 13448 ISA_SET: AVX512F_SCALAR 13449 EXCEPTIONS: AVX512-E3NF 13450 REAL_OPCODE: Y 13451 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER 13452 PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() 13453 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 13454 IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 13455 PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() 13456 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 13457 IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 13458 } 13459 13460 13461 # EMITTING VCVTSI2SS (VCVTSI2SS-128-2) 13462 { 13463 ICLASS: VCVTSI2SS 13464 CPL: 3 13465 CATEGORY: CONVERT 13466 EXTENSION: AVX512EVEX 13467 ISA_SET: AVX512F_SCALAR 13468 EXCEPTIONS: AVX512-E3NF 13469 REAL_OPCODE: Y 13470 ATTRIBUTES: MXCSR SIMD_SCALAR 13471 PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 13472 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 13473 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 13474 } 13475 13476 { 13477 ICLASS: VCVTSI2SS 13478 CPL: 3 13479 CATEGORY: CONVERT 13480 EXTENSION: AVX512EVEX 13481 ISA_SET: AVX512F_SCALAR 13482 EXCEPTIONS: AVX512-E3NF 13483 REAL_OPCODE: Y 13484 ATTRIBUTES: MXCSR SIMD_SCALAR 13485 PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0 13486 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 13487 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 13488 } 13489 13490 { 13491 ICLASS: VCVTSI2SS 13492 CPL: 3 13493 CATEGORY: CONVERT 13494 EXTENSION: AVX512EVEX 13495 ISA_SET: AVX512F_SCALAR 13496 EXCEPTIONS: AVX512-E3NF 13497 REAL_OPCODE: Y 13498 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER 13499 PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() 13500 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:i64 13501 IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 13502 } 13503 # EMITTING VCVTSS2SD (VCVTSS2SD-128-1) 13504 { 13505 ICLASS: VCVTSS2SD 13506 CPL: 3 13507 CATEGORY: CONVERT 13508 EXTENSION: AVX512EVEX 13509 ISA_SET: AVX512F_SCALAR 13510 EXCEPTIONS: AVX512-E3 13511 REAL_OPCODE: Y 13512 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 13513 PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 13514 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 13515 IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 13516 } 13517 13518 { 13519 ICLASS: VCVTSS2SD 13520 CPL: 3 13521 CATEGORY: CONVERT 13522 EXTENSION: AVX512EVEX 13523 ISA_SET: AVX512F_SCALAR 13524 EXCEPTIONS: AVX512-E3 13525 REAL_OPCODE: Y 13526 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 13527 PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 13528 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 13529 IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 13530 } 13531 13532 { 13533 ICLASS: VCVTSS2SD 13534 CPL: 3 13535 CATEGORY: CONVERT 13536 EXTENSION: AVX512EVEX 13537 ISA_SET: AVX512F_SCALAR 13538 EXCEPTIONS: AVX512-E3 13539 REAL_OPCODE: Y 13540 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 13541 PATTERN: EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 13542 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 13543 IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 13544 } 13545 13546 13547 # EMITTING VCVTSS2SI (VCVTSS2SI-128-1) 13548 { 13549 ICLASS: VCVTSS2SI 13550 CPL: 3 13551 CATEGORY: CONVERT 13552 EXTENSION: AVX512EVEX 13553 ISA_SET: AVX512F_SCALAR 13554 EXCEPTIONS: AVX512-E3NF 13555 REAL_OPCODE: Y 13556 ATTRIBUTES: MXCSR SIMD_SCALAR 13557 PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 13558 OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 13559 IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 13560 PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13561 OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 13562 IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 13563 } 13564 13565 { 13566 ICLASS: VCVTSS2SI 13567 CPL: 3 13568 CATEGORY: CONVERT 13569 EXTENSION: AVX512EVEX 13570 ISA_SET: AVX512F_SCALAR 13571 EXCEPTIONS: AVX512-E3NF 13572 REAL_OPCODE: Y 13573 ATTRIBUTES: MXCSR SIMD_SCALAR 13574 PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 13575 OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 13576 IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 13577 PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13578 OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 13579 IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 13580 } 13581 13582 { 13583 ICLASS: VCVTSS2SI 13584 CPL: 3 13585 CATEGORY: CONVERT 13586 EXTENSION: AVX512EVEX 13587 ISA_SET: AVX512F_SCALAR 13588 EXCEPTIONS: AVX512-E3NF 13589 REAL_OPCODE: Y 13590 ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 13591 PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() 13592 OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 13593 IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512 13594 PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE 13595 OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 13596 IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512 13597 } 13598 13599 13600 # EMITTING VCVTSS2SI (VCVTSS2SI-128-2) 13601 { 13602 ICLASS: VCVTSS2SI 13603 CPL: 3 13604 CATEGORY: CONVERT 13605 EXTENSION: AVX512EVEX 13606 ISA_SET: AVX512F_SCALAR 13607 EXCEPTIONS: AVX512-E3NF 13608 REAL_OPCODE: Y 13609 ATTRIBUTES: MXCSR SIMD_SCALAR 13610 PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13611 OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 13612 IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 13613 } 13614 13615 { 13616 ICLASS: VCVTSS2SI 13617 CPL: 3 13618 CATEGORY: CONVERT 13619 EXTENSION: AVX512EVEX 13620 ISA_SET: AVX512F_SCALAR 13621 EXCEPTIONS: AVX512-E3NF 13622 REAL_OPCODE: Y 13623 ATTRIBUTES: MXCSR SIMD_SCALAR 13624 PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13625 OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 13626 IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 13627 } 13628 13629 { 13630 ICLASS: VCVTSS2SI 13631 CPL: 3 13632 CATEGORY: CONVERT 13633 EXTENSION: AVX512EVEX 13634 ISA_SET: AVX512F_SCALAR 13635 EXCEPTIONS: AVX512-E3NF 13636 REAL_OPCODE: Y 13637 ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 13638 PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE 13639 OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 13640 IFORM: VCVTSS2SI_GPR64i64_MEMf32_AVX512 13641 } 13642 13643 13644 # EMITTING VCVTSS2USI (VCVTSS2USI-128-1) 13645 { 13646 ICLASS: VCVTSS2USI 13647 CPL: 3 13648 CATEGORY: CONVERT 13649 EXTENSION: AVX512EVEX 13650 ISA_SET: AVX512F_SCALAR 13651 EXCEPTIONS: AVX512-E3NF 13652 REAL_OPCODE: Y 13653 ATTRIBUTES: MXCSR SIMD_SCALAR 13654 PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 13655 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 13656 IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 13657 PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13658 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 13659 IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 13660 } 13661 13662 { 13663 ICLASS: VCVTSS2USI 13664 CPL: 3 13665 CATEGORY: CONVERT 13666 EXTENSION: AVX512EVEX 13667 ISA_SET: AVX512F_SCALAR 13668 EXCEPTIONS: AVX512-E3NF 13669 REAL_OPCODE: Y 13670 ATTRIBUTES: MXCSR SIMD_SCALAR 13671 PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 13672 OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 13673 IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 13674 PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13675 OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 13676 IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 13677 } 13678 13679 { 13680 ICLASS: VCVTSS2USI 13681 CPL: 3 13682 CATEGORY: CONVERT 13683 EXTENSION: AVX512EVEX 13684 ISA_SET: AVX512F_SCALAR 13685 EXCEPTIONS: AVX512-E3NF 13686 REAL_OPCODE: Y 13687 ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 13688 PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() 13689 OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 13690 IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512 13691 PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE 13692 OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 13693 IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512 13694 } 13695 13696 13697 # EMITTING VCVTSS2USI (VCVTSS2USI-128-2) 13698 { 13699 ICLASS: VCVTSS2USI 13700 CPL: 3 13701 CATEGORY: CONVERT 13702 EXTENSION: AVX512EVEX 13703 ISA_SET: AVX512F_SCALAR 13704 EXCEPTIONS: AVX512-E3NF 13705 REAL_OPCODE: Y 13706 ATTRIBUTES: MXCSR SIMD_SCALAR 13707 PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13708 OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 13709 IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 13710 } 13711 13712 { 13713 ICLASS: VCVTSS2USI 13714 CPL: 3 13715 CATEGORY: CONVERT 13716 EXTENSION: AVX512EVEX 13717 ISA_SET: AVX512F_SCALAR 13718 EXCEPTIONS: AVX512-E3NF 13719 REAL_OPCODE: Y 13720 ATTRIBUTES: MXCSR SIMD_SCALAR 13721 PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13722 OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 13723 IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 13724 } 13725 13726 { 13727 ICLASS: VCVTSS2USI 13728 CPL: 3 13729 CATEGORY: CONVERT 13730 EXTENSION: AVX512EVEX 13731 ISA_SET: AVX512F_SCALAR 13732 EXCEPTIONS: AVX512-E3NF 13733 REAL_OPCODE: Y 13734 ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 13735 PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE 13736 OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 13737 IFORM: VCVTSS2USI_GPR64u64_MEMf32_AVX512 13738 } 13739 13740 13741 # EMITTING VCVTTPD2DQ (VCVTTPD2DQ-512-1) 13742 { 13743 ICLASS: VCVTTPD2DQ 13744 CPL: 3 13745 CATEGORY: CONVERT 13746 EXTENSION: AVX512EVEX 13747 ISA_SET: AVX512F_512 13748 EXCEPTIONS: AVX512-E2 13749 REAL_OPCODE: Y 13750 ATTRIBUTES: MASKOP_EVEX MXCSR 13751 PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 13752 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 13753 IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 13754 } 13755 13756 { 13757 ICLASS: VCVTTPD2DQ 13758 CPL: 3 13759 CATEGORY: CONVERT 13760 EXTENSION: AVX512EVEX 13761 ISA_SET: AVX512F_512 13762 EXCEPTIONS: AVX512-E2 13763 REAL_OPCODE: Y 13764 ATTRIBUTES: MASKOP_EVEX MXCSR 13765 PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 13766 OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 13767 IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 13768 } 13769 13770 { 13771 ICLASS: VCVTTPD2DQ 13772 CPL: 3 13773 CATEGORY: CONVERT 13774 EXTENSION: AVX512EVEX 13775 ISA_SET: AVX512F_512 13776 EXCEPTIONS: AVX512-E2 13777 REAL_OPCODE: Y 13778 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 13779 PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 13780 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 13781 IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 13782 } 13783 13784 13785 # EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-512-1) 13786 { 13787 ICLASS: VCVTTPD2UDQ 13788 CPL: 3 13789 CATEGORY: CONVERT 13790 EXTENSION: AVX512EVEX 13791 ISA_SET: AVX512F_512 13792 EXCEPTIONS: AVX512-E2 13793 REAL_OPCODE: Y 13794 ATTRIBUTES: MASKOP_EVEX MXCSR 13795 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 13796 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 13797 IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 13798 } 13799 13800 { 13801 ICLASS: VCVTTPD2UDQ 13802 CPL: 3 13803 CATEGORY: CONVERT 13804 EXTENSION: AVX512EVEX 13805 ISA_SET: AVX512F_512 13806 EXCEPTIONS: AVX512-E2 13807 REAL_OPCODE: Y 13808 ATTRIBUTES: MASKOP_EVEX MXCSR 13809 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 13810 OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 13811 IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 13812 } 13813 13814 { 13815 ICLASS: VCVTTPD2UDQ 13816 CPL: 3 13817 CATEGORY: CONVERT 13818 EXTENSION: AVX512EVEX 13819 ISA_SET: AVX512F_512 13820 EXCEPTIONS: AVX512-E2 13821 REAL_OPCODE: Y 13822 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 13823 PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 13824 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 13825 IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 13826 } 13827 13828 13829 # EMITTING VCVTTPS2DQ (VCVTTPS2DQ-512-1) 13830 { 13831 ICLASS: VCVTTPS2DQ 13832 CPL: 3 13833 CATEGORY: CONVERT 13834 EXTENSION: AVX512EVEX 13835 ISA_SET: AVX512F_512 13836 EXCEPTIONS: AVX512-E2 13837 REAL_OPCODE: Y 13838 ATTRIBUTES: MASKOP_EVEX MXCSR 13839 PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 13840 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 13841 IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 13842 } 13843 13844 { 13845 ICLASS: VCVTTPS2DQ 13846 CPL: 3 13847 CATEGORY: CONVERT 13848 EXTENSION: AVX512EVEX 13849 ISA_SET: AVX512F_512 13850 EXCEPTIONS: AVX512-E2 13851 REAL_OPCODE: Y 13852 ATTRIBUTES: MASKOP_EVEX MXCSR 13853 PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 13854 OPERANDS: REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 13855 IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 13856 } 13857 13858 { 13859 ICLASS: VCVTTPS2DQ 13860 CPL: 3 13861 CATEGORY: CONVERT 13862 EXTENSION: AVX512EVEX 13863 ISA_SET: AVX512F_512 13864 EXCEPTIONS: AVX512-E2 13865 REAL_OPCODE: Y 13866 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 13867 PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 13868 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 13869 IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 13870 } 13871 13872 13873 # EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-512-1) 13874 { 13875 ICLASS: VCVTTPS2UDQ 13876 CPL: 3 13877 CATEGORY: CONVERT 13878 EXTENSION: AVX512EVEX 13879 ISA_SET: AVX512F_512 13880 EXCEPTIONS: AVX512-E2 13881 REAL_OPCODE: Y 13882 ATTRIBUTES: MASKOP_EVEX MXCSR 13883 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 13884 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 13885 IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 13886 } 13887 13888 { 13889 ICLASS: VCVTTPS2UDQ 13890 CPL: 3 13891 CATEGORY: CONVERT 13892 EXTENSION: AVX512EVEX 13893 ISA_SET: AVX512F_512 13894 EXCEPTIONS: AVX512-E2 13895 REAL_OPCODE: Y 13896 ATTRIBUTES: MASKOP_EVEX MXCSR 13897 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 13898 OPERANDS: REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 13899 IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 13900 } 13901 13902 { 13903 ICLASS: VCVTTPS2UDQ 13904 CPL: 3 13905 CATEGORY: CONVERT 13906 EXTENSION: AVX512EVEX 13907 ISA_SET: AVX512F_512 13908 EXCEPTIONS: AVX512-E2 13909 REAL_OPCODE: Y 13910 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 13911 PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 13912 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 13913 IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 13914 } 13915 13916 13917 # EMITTING VCVTTSD2SI (VCVTTSD2SI-128-1) 13918 { 13919 ICLASS: VCVTTSD2SI 13920 CPL: 3 13921 CATEGORY: CONVERT 13922 EXTENSION: AVX512EVEX 13923 ISA_SET: AVX512F_SCALAR 13924 EXCEPTIONS: AVX512-E3NF 13925 REAL_OPCODE: Y 13926 ATTRIBUTES: MXCSR SIMD_SCALAR 13927 PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 13928 OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 13929 IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 13930 PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13931 OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 13932 IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 13933 } 13934 13935 { 13936 ICLASS: VCVTTSD2SI 13937 CPL: 3 13938 CATEGORY: CONVERT 13939 EXTENSION: AVX512EVEX 13940 ISA_SET: AVX512F_SCALAR 13941 EXCEPTIONS: AVX512-E3NF 13942 REAL_OPCODE: Y 13943 ATTRIBUTES: MXCSR SIMD_SCALAR 13944 PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 13945 OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 13946 IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 13947 PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13948 OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 13949 IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 13950 } 13951 13952 { 13953 ICLASS: VCVTTSD2SI 13954 CPL: 3 13955 CATEGORY: CONVERT 13956 EXTENSION: AVX512EVEX 13957 ISA_SET: AVX512F_SCALAR 13958 EXCEPTIONS: AVX512-E3NF 13959 REAL_OPCODE: Y 13960 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 13961 PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() 13962 OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 13963 IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512 13964 PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE 13965 OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 13966 IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512 13967 } 13968 13969 13970 # EMITTING VCVTTSD2SI (VCVTTSD2SI-128-2) 13971 { 13972 ICLASS: VCVTTSD2SI 13973 CPL: 3 13974 CATEGORY: CONVERT 13975 EXTENSION: AVX512EVEX 13976 ISA_SET: AVX512F_SCALAR 13977 EXCEPTIONS: AVX512-E3NF 13978 REAL_OPCODE: Y 13979 ATTRIBUTES: MXCSR SIMD_SCALAR 13980 PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13981 OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 13982 IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 13983 } 13984 13985 { 13986 ICLASS: VCVTTSD2SI 13987 CPL: 3 13988 CATEGORY: CONVERT 13989 EXTENSION: AVX512EVEX 13990 ISA_SET: AVX512F_SCALAR 13991 EXCEPTIONS: AVX512-E3NF 13992 REAL_OPCODE: Y 13993 ATTRIBUTES: MXCSR SIMD_SCALAR 13994 PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 13995 OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 13996 IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 13997 } 13998 13999 { 14000 ICLASS: VCVTTSD2SI 14001 CPL: 3 14002 CATEGORY: CONVERT 14003 EXTENSION: AVX512EVEX 14004 ISA_SET: AVX512F_SCALAR 14005 EXCEPTIONS: AVX512-E3NF 14006 REAL_OPCODE: Y 14007 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 14008 PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE 14009 OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 14010 IFORM: VCVTTSD2SI_GPR64i64_MEMf64_AVX512 14011 } 14012 14013 14014 # EMITTING VCVTTSD2USI (VCVTTSD2USI-128-1) 14015 { 14016 ICLASS: VCVTTSD2USI 14017 CPL: 3 14018 CATEGORY: CONVERT 14019 EXTENSION: AVX512EVEX 14020 ISA_SET: AVX512F_SCALAR 14021 EXCEPTIONS: AVX512-E3NF 14022 REAL_OPCODE: Y 14023 ATTRIBUTES: MXCSR SIMD_SCALAR 14024 PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 14025 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 14026 IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 14027 PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 14028 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 14029 IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 14030 } 14031 14032 { 14033 ICLASS: VCVTTSD2USI 14034 CPL: 3 14035 CATEGORY: CONVERT 14036 EXTENSION: AVX512EVEX 14037 ISA_SET: AVX512F_SCALAR 14038 EXCEPTIONS: AVX512-E3NF 14039 REAL_OPCODE: Y 14040 ATTRIBUTES: MXCSR SIMD_SCALAR 14041 PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 14042 OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 14043 IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 14044 PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 14045 OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 14046 IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 14047 } 14048 14049 { 14050 ICLASS: VCVTTSD2USI 14051 CPL: 3 14052 CATEGORY: CONVERT 14053 EXTENSION: AVX512EVEX 14054 ISA_SET: AVX512F_SCALAR 14055 EXCEPTIONS: AVX512-E3NF 14056 REAL_OPCODE: Y 14057 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 14058 PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() 14059 OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 14060 IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512 14061 PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE 14062 OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 14063 IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512 14064 } 14065 14066 14067 # EMITTING VCVTTSD2USI (VCVTTSD2USI-128-2) 14068 { 14069 ICLASS: VCVTTSD2USI 14070 CPL: 3 14071 CATEGORY: CONVERT 14072 EXTENSION: AVX512EVEX 14073 ISA_SET: AVX512F_SCALAR 14074 EXCEPTIONS: AVX512-E3NF 14075 REAL_OPCODE: Y 14076 ATTRIBUTES: MXCSR SIMD_SCALAR 14077 PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 14078 OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 14079 IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 14080 } 14081 14082 { 14083 ICLASS: VCVTTSD2USI 14084 CPL: 3 14085 CATEGORY: CONVERT 14086 EXTENSION: AVX512EVEX 14087 ISA_SET: AVX512F_SCALAR 14088 EXCEPTIONS: AVX512-E3NF 14089 REAL_OPCODE: Y 14090 ATTRIBUTES: MXCSR SIMD_SCALAR 14091 PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 14092 OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 14093 IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 14094 } 14095 14096 { 14097 ICLASS: VCVTTSD2USI 14098 CPL: 3 14099 CATEGORY: CONVERT 14100 EXTENSION: AVX512EVEX 14101 ISA_SET: AVX512F_SCALAR 14102 EXCEPTIONS: AVX512-E3NF 14103 REAL_OPCODE: Y 14104 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q 14105 PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE 14106 OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 14107 IFORM: VCVTTSD2USI_GPR64u64_MEMf64_AVX512 14108 } 14109 14110 14111 # EMITTING VCVTTSS2SI (VCVTTSS2SI-128-1) 14112 { 14113 ICLASS: VCVTTSS2SI 14114 CPL: 3 14115 CATEGORY: CONVERT 14116 EXTENSION: AVX512EVEX 14117 ISA_SET: AVX512F_SCALAR 14118 EXCEPTIONS: AVX512-E3NF 14119 REAL_OPCODE: Y 14120 ATTRIBUTES: MXCSR SIMD_SCALAR 14121 PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 14122 OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 14123 IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 14124 PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 14125 OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 14126 IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 14127 } 14128 14129 { 14130 ICLASS: VCVTTSS2SI 14131 CPL: 3 14132 CATEGORY: CONVERT 14133 EXTENSION: AVX512EVEX 14134 ISA_SET: AVX512F_SCALAR 14135 EXCEPTIONS: AVX512-E3NF 14136 REAL_OPCODE: Y 14137 ATTRIBUTES: MXCSR SIMD_SCALAR 14138 PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 14139 OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 14140 IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 14141 PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 14142 OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 14143 IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 14144 } 14145 14146 { 14147 ICLASS: VCVTTSS2SI 14148 CPL: 3 14149 CATEGORY: CONVERT 14150 EXTENSION: AVX512EVEX 14151 ISA_SET: AVX512F_SCALAR 14152 EXCEPTIONS: AVX512-E3NF 14153 REAL_OPCODE: Y 14154 ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 14155 PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() 14156 OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 14157 IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512 14158 PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE 14159 OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 14160 IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512 14161 } 14162 14163 14164 # EMITTING VCVTTSS2SI (VCVTTSS2SI-128-2) 14165 { 14166 ICLASS: VCVTTSS2SI 14167 CPL: 3 14168 CATEGORY: CONVERT 14169 EXTENSION: AVX512EVEX 14170 ISA_SET: AVX512F_SCALAR 14171 EXCEPTIONS: AVX512-E3NF 14172 REAL_OPCODE: Y 14173 ATTRIBUTES: MXCSR SIMD_SCALAR 14174 PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 14175 OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 14176 IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 14177 } 14178 14179 { 14180 ICLASS: VCVTTSS2SI 14181 CPL: 3 14182 CATEGORY: CONVERT 14183 EXTENSION: AVX512EVEX 14184 ISA_SET: AVX512F_SCALAR 14185 EXCEPTIONS: AVX512-E3NF 14186 REAL_OPCODE: Y 14187 ATTRIBUTES: MXCSR SIMD_SCALAR 14188 PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 14189 OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 14190 IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 14191 } 14192 14193 { 14194 ICLASS: VCVTTSS2SI 14195 CPL: 3 14196 CATEGORY: CONVERT 14197 EXTENSION: AVX512EVEX 14198 ISA_SET: AVX512F_SCALAR 14199 EXCEPTIONS: AVX512-E3NF 14200 REAL_OPCODE: Y 14201 ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 14202 PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE 14203 OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 14204 IFORM: VCVTTSS2SI_GPR64i64_MEMf32_AVX512 14205 } 14206 14207 14208 # EMITTING VCVTTSS2USI (VCVTTSS2USI-128-1) 14209 { 14210 ICLASS: VCVTTSS2USI 14211 CPL: 3 14212 CATEGORY: CONVERT 14213 EXTENSION: AVX512EVEX 14214 ISA_SET: AVX512F_SCALAR 14215 EXCEPTIONS: AVX512-E3NF 14216 REAL_OPCODE: Y 14217 ATTRIBUTES: MXCSR SIMD_SCALAR 14218 PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 14219 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 14220 IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 14221 PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 14222 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 14223 IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 14224 } 14225 14226 { 14227 ICLASS: VCVTTSS2USI 14228 CPL: 3 14229 CATEGORY: CONVERT 14230 EXTENSION: AVX512EVEX 14231 ISA_SET: AVX512F_SCALAR 14232 EXCEPTIONS: AVX512-E3NF 14233 REAL_OPCODE: Y 14234 ATTRIBUTES: MXCSR SIMD_SCALAR 14235 PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 14236 OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 14237 IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 14238 PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 14239 OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 14240 IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 14241 } 14242 14243 { 14244 ICLASS: VCVTTSS2USI 14245 CPL: 3 14246 CATEGORY: CONVERT 14247 EXTENSION: AVX512EVEX 14248 ISA_SET: AVX512F_SCALAR 14249 EXCEPTIONS: AVX512-E3NF 14250 REAL_OPCODE: Y 14251 ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 14252 PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() 14253 OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 14254 IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512 14255 PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE 14256 OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 14257 IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512 14258 } 14259 14260 14261 # EMITTING VCVTTSS2USI (VCVTTSS2USI-128-2) 14262 { 14263 ICLASS: VCVTTSS2USI 14264 CPL: 3 14265 CATEGORY: CONVERT 14266 EXTENSION: AVX512EVEX 14267 ISA_SET: AVX512F_SCALAR 14268 EXCEPTIONS: AVX512-E3NF 14269 REAL_OPCODE: Y 14270 ATTRIBUTES: MXCSR SIMD_SCALAR 14271 PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 14272 OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 14273 IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 14274 } 14275 14276 { 14277 ICLASS: VCVTTSS2USI 14278 CPL: 3 14279 CATEGORY: CONVERT 14280 EXTENSION: AVX512EVEX 14281 ISA_SET: AVX512F_SCALAR 14282 EXCEPTIONS: AVX512-E3NF 14283 REAL_OPCODE: Y 14284 ATTRIBUTES: MXCSR SIMD_SCALAR 14285 PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE 14286 OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 14287 IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 14288 } 14289 14290 { 14291 ICLASS: VCVTTSS2USI 14292 CPL: 3 14293 CATEGORY: CONVERT 14294 EXTENSION: AVX512EVEX 14295 ISA_SET: AVX512F_SCALAR 14296 EXCEPTIONS: AVX512-E3NF 14297 REAL_OPCODE: Y 14298 ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR 14299 PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE 14300 OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 14301 IFORM: VCVTTSS2USI_GPR64u64_MEMf32_AVX512 14302 } 14303 14304 14305 # EMITTING VCVTUDQ2PD (VCVTUDQ2PD-512-1) 14306 { 14307 ICLASS: VCVTUDQ2PD 14308 CPL: 3 14309 CATEGORY: CONVERT 14310 EXTENSION: AVX512EVEX 14311 ISA_SET: AVX512F_512 14312 EXCEPTIONS: AVX512-E5 14313 REAL_OPCODE: Y 14314 ATTRIBUTES: MASKOP_EVEX 14315 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 14316 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 14317 IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 14318 } 14319 14320 { 14321 ICLASS: VCVTUDQ2PD 14322 CPL: 3 14323 CATEGORY: CONVERT 14324 EXTENSION: AVX512EVEX 14325 ISA_SET: AVX512F_512 14326 EXCEPTIONS: AVX512-E5 14327 REAL_OPCODE: Y 14328 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 14329 PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 14330 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 14331 IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 14332 } 14333 14334 14335 # EMITTING VCVTUDQ2PS (VCVTUDQ2PS-512-1) 14336 { 14337 ICLASS: VCVTUDQ2PS 14338 CPL: 3 14339 CATEGORY: CONVERT 14340 EXTENSION: AVX512EVEX 14341 ISA_SET: AVX512F_512 14342 EXCEPTIONS: AVX512-E2 14343 REAL_OPCODE: Y 14344 ATTRIBUTES: MASKOP_EVEX MXCSR 14345 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 14346 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 14347 IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 14348 } 14349 14350 { 14351 ICLASS: VCVTUDQ2PS 14352 CPL: 3 14353 CATEGORY: CONVERT 14354 EXTENSION: AVX512EVEX 14355 ISA_SET: AVX512F_512 14356 EXCEPTIONS: AVX512-E2 14357 REAL_OPCODE: Y 14358 ATTRIBUTES: MASKOP_EVEX MXCSR 14359 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 14360 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 14361 IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 14362 } 14363 14364 { 14365 ICLASS: VCVTUDQ2PS 14366 CPL: 3 14367 CATEGORY: CONVERT 14368 EXTENSION: AVX512EVEX 14369 ISA_SET: AVX512F_512 14370 EXCEPTIONS: AVX512-E2 14371 REAL_OPCODE: Y 14372 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 14373 PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 14374 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 14375 IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 14376 } 14377 14378 14379 # EMITTING VCVTUSI2SD (VCVTUSI2SD-128-1) 14380 { 14381 ICLASS: VCVTUSI2SD 14382 CPL: 3 14383 CATEGORY: CONVERT 14384 EXTENSION: AVX512EVEX 14385 ISA_SET: AVX512F_SCALAR 14386 EXCEPTIONS: AVX512-E10NF 14387 REAL_OPCODE: Y 14388 ATTRIBUTES: SIMD_SCALAR 14389 PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 14390 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32 14391 IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 14392 PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 14393 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32 14394 IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 14395 } 14396 14397 { 14398 ICLASS: VCVTUSI2SD 14399 CPL: 3 14400 CATEGORY: CONVERT 14401 EXTENSION: AVX512EVEX 14402 ISA_SET: AVX512F_SCALAR 14403 EXCEPTIONS: AVX512-E10NF 14404 REAL_OPCODE: Y 14405 ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER 14406 PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() 14407 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32 14408 IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 14409 PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() 14410 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32 14411 IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 14412 } 14413 14414 14415 # EMITTING VCVTUSI2SD (VCVTUSI2SD-128-2) 14416 { 14417 ICLASS: VCVTUSI2SD 14418 CPL: 3 14419 CATEGORY: CONVERT 14420 EXTENSION: AVX512EVEX 14421 ISA_SET: AVX512F_SCALAR 14422 EXCEPTIONS: AVX512-E3NF 14423 REAL_OPCODE: Y 14424 ATTRIBUTES: MXCSR SIMD_SCALAR 14425 PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 14426 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 14427 IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 14428 } 14429 14430 { 14431 ICLASS: VCVTUSI2SD 14432 CPL: 3 14433 CATEGORY: CONVERT 14434 EXTENSION: AVX512EVEX 14435 ISA_SET: AVX512F_SCALAR 14436 EXCEPTIONS: AVX512-E3NF 14437 REAL_OPCODE: Y 14438 ATTRIBUTES: MXCSR SIMD_SCALAR 14439 PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND() 14440 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 14441 IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 14442 } 14443 14444 { 14445 ICLASS: VCVTUSI2SD 14446 CPL: 3 14447 CATEGORY: CONVERT 14448 EXTENSION: AVX512EVEX 14449 ISA_SET: AVX512F_SCALAR 14450 EXCEPTIONS: AVX512-E3NF 14451 REAL_OPCODE: Y 14452 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER 14453 PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() 14454 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:u64 14455 IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 14456 } 14457 14458 14459 # EMITTING VCVTUSI2SS (VCVTUSI2SS-128-1) 14460 { 14461 ICLASS: VCVTUSI2SS 14462 CPL: 3 14463 CATEGORY: CONVERT 14464 EXTENSION: AVX512EVEX 14465 ISA_SET: AVX512F_SCALAR 14466 EXCEPTIONS: AVX512-E3NF 14467 REAL_OPCODE: Y 14468 ATTRIBUTES: MXCSR SIMD_SCALAR 14469 PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 14470 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 14471 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 14472 PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 14473 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 14474 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 14475 } 14476 14477 { 14478 ICLASS: VCVTUSI2SS 14479 CPL: 3 14480 CATEGORY: CONVERT 14481 EXTENSION: AVX512EVEX 14482 ISA_SET: AVX512F_SCALAR 14483 EXCEPTIONS: AVX512-E3NF 14484 REAL_OPCODE: Y 14485 ATTRIBUTES: MXCSR SIMD_SCALAR 14486 PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 14487 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 14488 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 14489 PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0 14490 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 14491 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 14492 } 14493 14494 { 14495 ICLASS: VCVTUSI2SS 14496 CPL: 3 14497 CATEGORY: CONVERT 14498 EXTENSION: AVX512EVEX 14499 ISA_SET: AVX512F_SCALAR 14500 EXCEPTIONS: AVX512-E3NF 14501 REAL_OPCODE: Y 14502 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER 14503 PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() 14504 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 14505 IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 14506 PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() 14507 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 14508 IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 14509 } 14510 14511 14512 # EMITTING VCVTUSI2SS (VCVTUSI2SS-128-2) 14513 { 14514 ICLASS: VCVTUSI2SS 14515 CPL: 3 14516 CATEGORY: CONVERT 14517 EXTENSION: AVX512EVEX 14518 ISA_SET: AVX512F_SCALAR 14519 EXCEPTIONS: AVX512-E3NF 14520 REAL_OPCODE: Y 14521 ATTRIBUTES: MXCSR SIMD_SCALAR 14522 PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 14523 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 14524 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 14525 } 14526 14527 { 14528 ICLASS: VCVTUSI2SS 14529 CPL: 3 14530 CATEGORY: CONVERT 14531 EXTENSION: AVX512EVEX 14532 ISA_SET: AVX512F_SCALAR 14533 EXCEPTIONS: AVX512-E3NF 14534 REAL_OPCODE: Y 14535 ATTRIBUTES: MXCSR SIMD_SCALAR 14536 PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0 14537 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 14538 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 14539 } 14540 14541 { 14542 ICLASS: VCVTUSI2SS 14543 CPL: 3 14544 CATEGORY: CONVERT 14545 EXTENSION: AVX512EVEX 14546 ISA_SET: AVX512F_SCALAR 14547 EXCEPTIONS: AVX512-E3NF 14548 REAL_OPCODE: Y 14549 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER 14550 PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() 14551 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:u64 14552 IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 14553 } 14554 14555 14556 # EMITTING VDIVPD (VDIVPD-512-1) 14557 { 14558 ICLASS: VDIVPD 14559 CPL: 3 14560 CATEGORY: AVX512 14561 EXTENSION: AVX512EVEX 14562 ISA_SET: AVX512F_512 14563 EXCEPTIONS: AVX512-E2 14564 REAL_OPCODE: Y 14565 ATTRIBUTES: MASKOP_EVEX MXCSR 14566 PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 14567 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 14568 IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 14569 } 14570 14571 { 14572 ICLASS: VDIVPD 14573 CPL: 3 14574 CATEGORY: AVX512 14575 EXTENSION: AVX512EVEX 14576 ISA_SET: AVX512F_512 14577 EXCEPTIONS: AVX512-E2 14578 REAL_OPCODE: Y 14579 ATTRIBUTES: MASKOP_EVEX MXCSR 14580 PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 14581 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 14582 IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 14583 } 14584 14585 { 14586 ICLASS: VDIVPD 14587 CPL: 3 14588 CATEGORY: AVX512 14589 EXTENSION: AVX512EVEX 14590 ISA_SET: AVX512F_512 14591 EXCEPTIONS: AVX512-E2 14592 REAL_OPCODE: Y 14593 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 14594 PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 14595 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 14596 IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 14597 } 14598 14599 14600 # EMITTING VDIVPS (VDIVPS-512-1) 14601 { 14602 ICLASS: VDIVPS 14603 CPL: 3 14604 CATEGORY: AVX512 14605 EXTENSION: AVX512EVEX 14606 ISA_SET: AVX512F_512 14607 EXCEPTIONS: AVX512-E2 14608 REAL_OPCODE: Y 14609 ATTRIBUTES: MASKOP_EVEX MXCSR 14610 PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 14611 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 14612 IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 14613 } 14614 14615 { 14616 ICLASS: VDIVPS 14617 CPL: 3 14618 CATEGORY: AVX512 14619 EXTENSION: AVX512EVEX 14620 ISA_SET: AVX512F_512 14621 EXCEPTIONS: AVX512-E2 14622 REAL_OPCODE: Y 14623 ATTRIBUTES: MASKOP_EVEX MXCSR 14624 PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 14625 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 14626 IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 14627 } 14628 14629 { 14630 ICLASS: VDIVPS 14631 CPL: 3 14632 CATEGORY: AVX512 14633 EXTENSION: AVX512EVEX 14634 ISA_SET: AVX512F_512 14635 EXCEPTIONS: AVX512-E2 14636 REAL_OPCODE: Y 14637 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 14638 PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 14639 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 14640 IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 14641 } 14642 14643 14644 # EMITTING VDIVSD (VDIVSD-128-1) 14645 { 14646 ICLASS: VDIVSD 14647 CPL: 3 14648 CATEGORY: AVX512 14649 EXTENSION: AVX512EVEX 14650 ISA_SET: AVX512F_SCALAR 14651 EXCEPTIONS: AVX512-E3 14652 REAL_OPCODE: Y 14653 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 14654 PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 14655 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 14656 IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 14657 } 14658 14659 { 14660 ICLASS: VDIVSD 14661 CPL: 3 14662 CATEGORY: AVX512 14663 EXTENSION: AVX512EVEX 14664 ISA_SET: AVX512F_SCALAR 14665 EXCEPTIONS: AVX512-E3 14666 REAL_OPCODE: Y 14667 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 14668 PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 14669 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 14670 IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 14671 } 14672 14673 { 14674 ICLASS: VDIVSD 14675 CPL: 3 14676 CATEGORY: AVX512 14677 EXTENSION: AVX512EVEX 14678 ISA_SET: AVX512F_SCALAR 14679 EXCEPTIONS: AVX512-E3 14680 REAL_OPCODE: Y 14681 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 14682 PATTERN: EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 14683 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 14684 IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 14685 } 14686 14687 14688 # EMITTING VDIVSS (VDIVSS-128-1) 14689 { 14690 ICLASS: VDIVSS 14691 CPL: 3 14692 CATEGORY: AVX512 14693 EXTENSION: AVX512EVEX 14694 ISA_SET: AVX512F_SCALAR 14695 EXCEPTIONS: AVX512-E3 14696 REAL_OPCODE: Y 14697 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 14698 PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 14699 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 14700 IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 14701 } 14702 14703 { 14704 ICLASS: VDIVSS 14705 CPL: 3 14706 CATEGORY: AVX512 14707 EXTENSION: AVX512EVEX 14708 ISA_SET: AVX512F_SCALAR 14709 EXCEPTIONS: AVX512-E3 14710 REAL_OPCODE: Y 14711 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 14712 PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 14713 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 14714 IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 14715 } 14716 14717 { 14718 ICLASS: VDIVSS 14719 CPL: 3 14720 CATEGORY: AVX512 14721 EXTENSION: AVX512EVEX 14722 ISA_SET: AVX512F_SCALAR 14723 EXCEPTIONS: AVX512-E3 14724 REAL_OPCODE: Y 14725 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 14726 PATTERN: EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 14727 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 14728 IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 14729 } 14730 14731 14732 # EMITTING VEXPANDPD (VEXPANDPD-512-1) 14733 { 14734 ICLASS: VEXPANDPD 14735 CPL: 3 14736 CATEGORY: EXPAND 14737 EXTENSION: AVX512EVEX 14738 ISA_SET: AVX512F_512 14739 EXCEPTIONS: AVX512-E4 14740 REAL_OPCODE: Y 14741 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 14742 PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() 14743 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 14744 IFORM: VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 14745 } 14746 14747 14748 # EMITTING VEXPANDPD (VEXPANDPD-512-2) 14749 { 14750 ICLASS: VEXPANDPD 14751 CPL: 3 14752 CATEGORY: EXPAND 14753 EXTENSION: AVX512EVEX 14754 ISA_SET: AVX512F_512 14755 EXCEPTIONS: AVX512-E4 14756 REAL_OPCODE: Y 14757 ATTRIBUTES: MASKOP_EVEX 14758 PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 14759 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 14760 IFORM: VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 14761 } 14762 14763 14764 # EMITTING VEXPANDPS (VEXPANDPS-512-1) 14765 { 14766 ICLASS: VEXPANDPS 14767 CPL: 3 14768 CATEGORY: EXPAND 14769 EXTENSION: AVX512EVEX 14770 ISA_SET: AVX512F_512 14771 EXCEPTIONS: AVX512-E4 14772 REAL_OPCODE: Y 14773 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 14774 PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() 14775 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 14776 IFORM: VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 14777 } 14778 14779 14780 # EMITTING VEXPANDPS (VEXPANDPS-512-2) 14781 { 14782 ICLASS: VEXPANDPS 14783 CPL: 3 14784 CATEGORY: EXPAND 14785 EXTENSION: AVX512EVEX 14786 ISA_SET: AVX512F_512 14787 EXCEPTIONS: AVX512-E4 14788 REAL_OPCODE: Y 14789 ATTRIBUTES: MASKOP_EVEX 14790 PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 14791 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 14792 IFORM: VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 14793 } 14794 14795 14796 # EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-1) 14797 { 14798 ICLASS: VEXTRACTF32X4 14799 CPL: 3 14800 CATEGORY: AVX512 14801 EXTENSION: AVX512EVEX 14802 ISA_SET: AVX512F_512 14803 EXCEPTIONS: AVX512-E6NF 14804 REAL_OPCODE: Y 14805 ATTRIBUTES: MASKOP_EVEX 14806 PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 14807 OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b 14808 IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 14809 } 14810 14811 14812 # EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-2) 14813 { 14814 ICLASS: VEXTRACTF32X4 14815 CPL: 3 14816 CATEGORY: AVX512 14817 EXTENSION: AVX512EVEX 14818 ISA_SET: AVX512F_512 14819 EXCEPTIONS: AVX512-E6NF 14820 REAL_OPCODE: Y 14821 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 14822 PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 14823 OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b 14824 IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 14825 } 14826 14827 14828 # EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-1) 14829 { 14830 ICLASS: VEXTRACTF64X4 14831 CPL: 3 14832 CATEGORY: AVX512 14833 EXTENSION: AVX512EVEX 14834 ISA_SET: AVX512F_512 14835 EXCEPTIONS: AVX512-E6NF 14836 REAL_OPCODE: Y 14837 ATTRIBUTES: MASKOP_EVEX 14838 PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 14839 OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b 14840 IFORM: VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 14841 } 14842 14843 14844 # EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-2) 14845 { 14846 ICLASS: VEXTRACTF64X4 14847 CPL: 3 14848 CATEGORY: AVX512 14849 EXTENSION: AVX512EVEX 14850 ISA_SET: AVX512F_512 14851 EXCEPTIONS: AVX512-E6NF 14852 REAL_OPCODE: Y 14853 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 14854 PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() 14855 OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b 14856 IFORM: VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 14857 } 14858 14859 14860 # EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-1) 14861 { 14862 ICLASS: VEXTRACTI32X4 14863 CPL: 3 14864 CATEGORY: AVX512 14865 EXTENSION: AVX512EVEX 14866 ISA_SET: AVX512F_512 14867 EXCEPTIONS: AVX512-E6NF 14868 REAL_OPCODE: Y 14869 ATTRIBUTES: MASKOP_EVEX 14870 PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 14871 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b 14872 IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 14873 } 14874 14875 14876 # EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-2) 14877 { 14878 ICLASS: VEXTRACTI32X4 14879 CPL: 3 14880 CATEGORY: AVX512 14881 EXTENSION: AVX512EVEX 14882 ISA_SET: AVX512F_512 14883 EXCEPTIONS: AVX512-E6NF 14884 REAL_OPCODE: Y 14885 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 14886 PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 14887 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b 14888 IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 14889 } 14890 14891 14892 # EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-1) 14893 { 14894 ICLASS: VEXTRACTI64X4 14895 CPL: 3 14896 CATEGORY: AVX512 14897 EXTENSION: AVX512EVEX 14898 ISA_SET: AVX512F_512 14899 EXCEPTIONS: AVX512-E6NF 14900 REAL_OPCODE: Y 14901 ATTRIBUTES: MASKOP_EVEX 14902 PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 14903 OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b 14904 IFORM: VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 14905 } 14906 14907 14908 # EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-2) 14909 { 14910 ICLASS: VEXTRACTI64X4 14911 CPL: 3 14912 CATEGORY: AVX512 14913 EXTENSION: AVX512EVEX 14914 ISA_SET: AVX512F_512 14915 EXCEPTIONS: AVX512-E6NF 14916 REAL_OPCODE: Y 14917 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 14918 PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() 14919 OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b 14920 IFORM: VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 14921 } 14922 14923 14924 # EMITTING VEXTRACTPS (VEXTRACTPS-128-1) 14925 { 14926 ICLASS: VEXTRACTPS 14927 CPL: 3 14928 CATEGORY: AVX512 14929 EXTENSION: AVX512EVEX 14930 ISA_SET: AVX512F_128N 14931 EXCEPTIONS: AVX512-E9NF 14932 REAL_OPCODE: Y 14933 PATTERN: EVV 0x17 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() 14934 OPERANDS: REG0=GPR32_B():w:d:f32 REG1=XMM_R3():r:dq:f32 IMM0:r:b 14935 IFORM: VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 14936 } 14937 14938 { 14939 ICLASS: VEXTRACTPS 14940 CPL: 3 14941 CATEGORY: AVX512 14942 EXTENSION: AVX512EVEX 14943 ISA_SET: AVX512F_128N 14944 EXCEPTIONS: AVX512-E9NF 14945 REAL_OPCODE: Y 14946 ATTRIBUTES: DISP8_GPR_WRITER_STORE 14947 PATTERN: EVV 0x17 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() 14948 OPERANDS: MEM0:w:d:f32 REG0=XMM_R3():r:dq:f32 IMM0:r:b 14949 IFORM: VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 14950 } 14951 14952 14953 # EMITTING VFIXUPIMMPD (VFIXUPIMMPD-512-1) 14954 { 14955 ICLASS: VFIXUPIMMPD 14956 CPL: 3 14957 CATEGORY: AVX512 14958 EXTENSION: AVX512EVEX 14959 ISA_SET: AVX512F_512 14960 EXCEPTIONS: AVX512-E2 14961 REAL_OPCODE: Y 14962 ATTRIBUTES: MASKOP_EVEX MXCSR 14963 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 14964 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 14965 IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 14966 } 14967 14968 { 14969 ICLASS: VFIXUPIMMPD 14970 CPL: 3 14971 CATEGORY: AVX512 14972 EXTENSION: AVX512EVEX 14973 ISA_SET: AVX512F_512 14974 EXCEPTIONS: AVX512-E2 14975 REAL_OPCODE: Y 14976 ATTRIBUTES: MASKOP_EVEX MXCSR 14977 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() 14978 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 14979 IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 14980 } 14981 14982 { 14983 ICLASS: VFIXUPIMMPD 14984 CPL: 3 14985 CATEGORY: AVX512 14986 EXTENSION: AVX512EVEX 14987 ISA_SET: AVX512F_512 14988 EXCEPTIONS: AVX512-E2 14989 REAL_OPCODE: Y 14990 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 14991 PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 14992 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 14993 IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 14994 } 14995 14996 14997 # EMITTING VFIXUPIMMPS (VFIXUPIMMPS-512-1) 14998 { 14999 ICLASS: VFIXUPIMMPS 15000 CPL: 3 15001 CATEGORY: AVX512 15002 EXTENSION: AVX512EVEX 15003 ISA_SET: AVX512F_512 15004 EXCEPTIONS: AVX512-E2 15005 REAL_OPCODE: Y 15006 ATTRIBUTES: MASKOP_EVEX MXCSR 15007 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 15008 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 15009 IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 15010 } 15011 15012 { 15013 ICLASS: VFIXUPIMMPS 15014 CPL: 3 15015 CATEGORY: AVX512 15016 EXTENSION: AVX512EVEX 15017 ISA_SET: AVX512F_512 15018 EXCEPTIONS: AVX512-E2 15019 REAL_OPCODE: Y 15020 ATTRIBUTES: MASKOP_EVEX MXCSR 15021 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() 15022 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 15023 IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 15024 } 15025 15026 { 15027 ICLASS: VFIXUPIMMPS 15028 CPL: 3 15029 CATEGORY: AVX512 15030 EXTENSION: AVX512EVEX 15031 ISA_SET: AVX512F_512 15032 EXCEPTIONS: AVX512-E2 15033 REAL_OPCODE: Y 15034 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15035 PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 15036 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 15037 IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 15038 } 15039 15040 15041 # EMITTING VFIXUPIMMSD (VFIXUPIMMSD-128-1) 15042 { 15043 ICLASS: VFIXUPIMMSD 15044 CPL: 3 15045 CATEGORY: AVX512 15046 EXTENSION: AVX512EVEX 15047 ISA_SET: AVX512F_SCALAR 15048 EXCEPTIONS: AVX512-E3 15049 REAL_OPCODE: Y 15050 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15051 PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() 15052 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 15053 IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 15054 } 15055 15056 { 15057 ICLASS: VFIXUPIMMSD 15058 CPL: 3 15059 CATEGORY: AVX512 15060 EXTENSION: AVX512EVEX 15061 ISA_SET: AVX512F_SCALAR 15062 EXCEPTIONS: AVX512-E3 15063 REAL_OPCODE: Y 15064 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15065 PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() 15066 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 15067 IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 15068 } 15069 15070 { 15071 ICLASS: VFIXUPIMMSD 15072 CPL: 3 15073 CATEGORY: AVX512 15074 EXTENSION: AVX512EVEX 15075 ISA_SET: AVX512F_SCALAR 15076 EXCEPTIONS: AVX512-E3 15077 REAL_OPCODE: Y 15078 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 15079 PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 15080 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 15081 IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 15082 } 15083 15084 15085 # EMITTING VFIXUPIMMSS (VFIXUPIMMSS-128-1) 15086 { 15087 ICLASS: VFIXUPIMMSS 15088 CPL: 3 15089 CATEGORY: AVX512 15090 EXTENSION: AVX512EVEX 15091 ISA_SET: AVX512F_SCALAR 15092 EXCEPTIONS: AVX512-E3 15093 REAL_OPCODE: Y 15094 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15095 PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() 15096 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 15097 IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 15098 } 15099 15100 { 15101 ICLASS: VFIXUPIMMSS 15102 CPL: 3 15103 CATEGORY: AVX512 15104 EXTENSION: AVX512EVEX 15105 ISA_SET: AVX512F_SCALAR 15106 EXCEPTIONS: AVX512-E3 15107 REAL_OPCODE: Y 15108 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15109 PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() 15110 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 15111 IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 15112 } 15113 15114 { 15115 ICLASS: VFIXUPIMMSS 15116 CPL: 3 15117 CATEGORY: AVX512 15118 EXTENSION: AVX512EVEX 15119 ISA_SET: AVX512F_SCALAR 15120 EXCEPTIONS: AVX512-E3 15121 REAL_OPCODE: Y 15122 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 15123 PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 15124 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 15125 IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 15126 } 15127 15128 15129 # EMITTING VFMADD132PD (VFMADD132PD-512-1) 15130 { 15131 ICLASS: VFMADD132PD 15132 CPL: 3 15133 CATEGORY: VFMA 15134 EXTENSION: AVX512EVEX 15135 ISA_SET: AVX512F_512 15136 EXCEPTIONS: AVX512-E2 15137 REAL_OPCODE: Y 15138 ATTRIBUTES: MASKOP_EVEX MXCSR 15139 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 15140 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15141 IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15142 } 15143 15144 { 15145 ICLASS: VFMADD132PD 15146 CPL: 3 15147 CATEGORY: VFMA 15148 EXTENSION: AVX512EVEX 15149 ISA_SET: AVX512F_512 15150 EXCEPTIONS: AVX512-E2 15151 REAL_OPCODE: Y 15152 ATTRIBUTES: MASKOP_EVEX MXCSR 15153 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 15154 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15155 IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15156 } 15157 15158 { 15159 ICLASS: VFMADD132PD 15160 CPL: 3 15161 CATEGORY: VFMA 15162 EXTENSION: AVX512EVEX 15163 ISA_SET: AVX512F_512 15164 EXCEPTIONS: AVX512-E2 15165 REAL_OPCODE: Y 15166 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15167 PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 15168 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 15169 IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 15170 } 15171 15172 15173 # EMITTING VFMADD132PS (VFMADD132PS-512-1) 15174 { 15175 ICLASS: VFMADD132PS 15176 CPL: 3 15177 CATEGORY: VFMA 15178 EXTENSION: AVX512EVEX 15179 ISA_SET: AVX512F_512 15180 EXCEPTIONS: AVX512-E2 15181 REAL_OPCODE: Y 15182 ATTRIBUTES: MASKOP_EVEX MXCSR 15183 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 15184 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15185 IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15186 } 15187 15188 { 15189 ICLASS: VFMADD132PS 15190 CPL: 3 15191 CATEGORY: VFMA 15192 EXTENSION: AVX512EVEX 15193 ISA_SET: AVX512F_512 15194 EXCEPTIONS: AVX512-E2 15195 REAL_OPCODE: Y 15196 ATTRIBUTES: MASKOP_EVEX MXCSR 15197 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 15198 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15199 IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15200 } 15201 15202 { 15203 ICLASS: VFMADD132PS 15204 CPL: 3 15205 CATEGORY: VFMA 15206 EXTENSION: AVX512EVEX 15207 ISA_SET: AVX512F_512 15208 EXCEPTIONS: AVX512-E2 15209 REAL_OPCODE: Y 15210 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15211 PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 15212 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 15213 IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 15214 } 15215 15216 15217 # EMITTING VFMADD132SD (VFMADD132SD-128-1) 15218 { 15219 ICLASS: VFMADD132SD 15220 CPL: 3 15221 CATEGORY: VFMA 15222 EXTENSION: AVX512EVEX 15223 ISA_SET: AVX512F_SCALAR 15224 EXCEPTIONS: AVX512-E3 15225 REAL_OPCODE: Y 15226 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15227 PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 15228 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 15229 IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 15230 } 15231 15232 { 15233 ICLASS: VFMADD132SD 15234 CPL: 3 15235 CATEGORY: VFMA 15236 EXTENSION: AVX512EVEX 15237 ISA_SET: AVX512F_SCALAR 15238 EXCEPTIONS: AVX512-E3 15239 REAL_OPCODE: Y 15240 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15241 PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 15242 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 15243 IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 15244 } 15245 15246 { 15247 ICLASS: VFMADD132SD 15248 CPL: 3 15249 CATEGORY: VFMA 15250 EXTENSION: AVX512EVEX 15251 ISA_SET: AVX512F_SCALAR 15252 EXCEPTIONS: AVX512-E3 15253 REAL_OPCODE: Y 15254 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 15255 PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 15256 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 15257 IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 15258 } 15259 15260 15261 # EMITTING VFMADD132SS (VFMADD132SS-128-1) 15262 { 15263 ICLASS: VFMADD132SS 15264 CPL: 3 15265 CATEGORY: VFMA 15266 EXTENSION: AVX512EVEX 15267 ISA_SET: AVX512F_SCALAR 15268 EXCEPTIONS: AVX512-E3 15269 REAL_OPCODE: Y 15270 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15271 PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 15272 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 15273 IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 15274 } 15275 15276 { 15277 ICLASS: VFMADD132SS 15278 CPL: 3 15279 CATEGORY: VFMA 15280 EXTENSION: AVX512EVEX 15281 ISA_SET: AVX512F_SCALAR 15282 EXCEPTIONS: AVX512-E3 15283 REAL_OPCODE: Y 15284 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15285 PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 15286 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 15287 IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 15288 } 15289 15290 { 15291 ICLASS: VFMADD132SS 15292 CPL: 3 15293 CATEGORY: VFMA 15294 EXTENSION: AVX512EVEX 15295 ISA_SET: AVX512F_SCALAR 15296 EXCEPTIONS: AVX512-E3 15297 REAL_OPCODE: Y 15298 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 15299 PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 15300 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 15301 IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 15302 } 15303 15304 15305 # EMITTING VFMADD213PD (VFMADD213PD-512-1) 15306 { 15307 ICLASS: VFMADD213PD 15308 CPL: 3 15309 CATEGORY: VFMA 15310 EXTENSION: AVX512EVEX 15311 ISA_SET: AVX512F_512 15312 EXCEPTIONS: AVX512-E2 15313 REAL_OPCODE: Y 15314 ATTRIBUTES: MASKOP_EVEX MXCSR 15315 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 15316 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15317 IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15318 } 15319 15320 { 15321 ICLASS: VFMADD213PD 15322 CPL: 3 15323 CATEGORY: VFMA 15324 EXTENSION: AVX512EVEX 15325 ISA_SET: AVX512F_512 15326 EXCEPTIONS: AVX512-E2 15327 REAL_OPCODE: Y 15328 ATTRIBUTES: MASKOP_EVEX MXCSR 15329 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 15330 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15331 IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15332 } 15333 15334 { 15335 ICLASS: VFMADD213PD 15336 CPL: 3 15337 CATEGORY: VFMA 15338 EXTENSION: AVX512EVEX 15339 ISA_SET: AVX512F_512 15340 EXCEPTIONS: AVX512-E2 15341 REAL_OPCODE: Y 15342 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15343 PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 15344 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 15345 IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 15346 } 15347 15348 15349 # EMITTING VFMADD213PS (VFMADD213PS-512-1) 15350 { 15351 ICLASS: VFMADD213PS 15352 CPL: 3 15353 CATEGORY: VFMA 15354 EXTENSION: AVX512EVEX 15355 ISA_SET: AVX512F_512 15356 EXCEPTIONS: AVX512-E2 15357 REAL_OPCODE: Y 15358 ATTRIBUTES: MASKOP_EVEX MXCSR 15359 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 15360 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15361 IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15362 } 15363 15364 { 15365 ICLASS: VFMADD213PS 15366 CPL: 3 15367 CATEGORY: VFMA 15368 EXTENSION: AVX512EVEX 15369 ISA_SET: AVX512F_512 15370 EXCEPTIONS: AVX512-E2 15371 REAL_OPCODE: Y 15372 ATTRIBUTES: MASKOP_EVEX MXCSR 15373 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 15374 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15375 IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15376 } 15377 15378 { 15379 ICLASS: VFMADD213PS 15380 CPL: 3 15381 CATEGORY: VFMA 15382 EXTENSION: AVX512EVEX 15383 ISA_SET: AVX512F_512 15384 EXCEPTIONS: AVX512-E2 15385 REAL_OPCODE: Y 15386 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15387 PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 15388 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 15389 IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 15390 } 15391 15392 15393 # EMITTING VFMADD213SD (VFMADD213SD-128-1) 15394 { 15395 ICLASS: VFMADD213SD 15396 CPL: 3 15397 CATEGORY: VFMA 15398 EXTENSION: AVX512EVEX 15399 ISA_SET: AVX512F_SCALAR 15400 EXCEPTIONS: AVX512-E3 15401 REAL_OPCODE: Y 15402 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15403 PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 15404 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 15405 IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 15406 } 15407 15408 { 15409 ICLASS: VFMADD213SD 15410 CPL: 3 15411 CATEGORY: VFMA 15412 EXTENSION: AVX512EVEX 15413 ISA_SET: AVX512F_SCALAR 15414 EXCEPTIONS: AVX512-E3 15415 REAL_OPCODE: Y 15416 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15417 PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 15418 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 15419 IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 15420 } 15421 15422 { 15423 ICLASS: VFMADD213SD 15424 CPL: 3 15425 CATEGORY: VFMA 15426 EXTENSION: AVX512EVEX 15427 ISA_SET: AVX512F_SCALAR 15428 EXCEPTIONS: AVX512-E3 15429 REAL_OPCODE: Y 15430 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 15431 PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 15432 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 15433 IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 15434 } 15435 15436 15437 # EMITTING VFMADD213SS (VFMADD213SS-128-1) 15438 { 15439 ICLASS: VFMADD213SS 15440 CPL: 3 15441 CATEGORY: VFMA 15442 EXTENSION: AVX512EVEX 15443 ISA_SET: AVX512F_SCALAR 15444 EXCEPTIONS: AVX512-E3 15445 REAL_OPCODE: Y 15446 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15447 PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 15448 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 15449 IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 15450 } 15451 15452 { 15453 ICLASS: VFMADD213SS 15454 CPL: 3 15455 CATEGORY: VFMA 15456 EXTENSION: AVX512EVEX 15457 ISA_SET: AVX512F_SCALAR 15458 EXCEPTIONS: AVX512-E3 15459 REAL_OPCODE: Y 15460 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15461 PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 15462 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 15463 IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 15464 } 15465 15466 { 15467 ICLASS: VFMADD213SS 15468 CPL: 3 15469 CATEGORY: VFMA 15470 EXTENSION: AVX512EVEX 15471 ISA_SET: AVX512F_SCALAR 15472 EXCEPTIONS: AVX512-E3 15473 REAL_OPCODE: Y 15474 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 15475 PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 15476 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 15477 IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 15478 } 15479 15480 15481 # EMITTING VFMADD231PD (VFMADD231PD-512-1) 15482 { 15483 ICLASS: VFMADD231PD 15484 CPL: 3 15485 CATEGORY: VFMA 15486 EXTENSION: AVX512EVEX 15487 ISA_SET: AVX512F_512 15488 EXCEPTIONS: AVX512-E2 15489 REAL_OPCODE: Y 15490 ATTRIBUTES: MASKOP_EVEX MXCSR 15491 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 15492 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15493 IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15494 } 15495 15496 { 15497 ICLASS: VFMADD231PD 15498 CPL: 3 15499 CATEGORY: VFMA 15500 EXTENSION: AVX512EVEX 15501 ISA_SET: AVX512F_512 15502 EXCEPTIONS: AVX512-E2 15503 REAL_OPCODE: Y 15504 ATTRIBUTES: MASKOP_EVEX MXCSR 15505 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 15506 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15507 IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15508 } 15509 15510 { 15511 ICLASS: VFMADD231PD 15512 CPL: 3 15513 CATEGORY: VFMA 15514 EXTENSION: AVX512EVEX 15515 ISA_SET: AVX512F_512 15516 EXCEPTIONS: AVX512-E2 15517 REAL_OPCODE: Y 15518 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15519 PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 15520 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 15521 IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 15522 } 15523 15524 15525 # EMITTING VFMADD231PS (VFMADD231PS-512-1) 15526 { 15527 ICLASS: VFMADD231PS 15528 CPL: 3 15529 CATEGORY: VFMA 15530 EXTENSION: AVX512EVEX 15531 ISA_SET: AVX512F_512 15532 EXCEPTIONS: AVX512-E2 15533 REAL_OPCODE: Y 15534 ATTRIBUTES: MASKOP_EVEX MXCSR 15535 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 15536 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15537 IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15538 } 15539 15540 { 15541 ICLASS: VFMADD231PS 15542 CPL: 3 15543 CATEGORY: VFMA 15544 EXTENSION: AVX512EVEX 15545 ISA_SET: AVX512F_512 15546 EXCEPTIONS: AVX512-E2 15547 REAL_OPCODE: Y 15548 ATTRIBUTES: MASKOP_EVEX MXCSR 15549 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 15550 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15551 IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15552 } 15553 15554 { 15555 ICLASS: VFMADD231PS 15556 CPL: 3 15557 CATEGORY: VFMA 15558 EXTENSION: AVX512EVEX 15559 ISA_SET: AVX512F_512 15560 EXCEPTIONS: AVX512-E2 15561 REAL_OPCODE: Y 15562 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15563 PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 15564 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 15565 IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 15566 } 15567 15568 15569 # EMITTING VFMADD231SD (VFMADD231SD-128-1) 15570 { 15571 ICLASS: VFMADD231SD 15572 CPL: 3 15573 CATEGORY: VFMA 15574 EXTENSION: AVX512EVEX 15575 ISA_SET: AVX512F_SCALAR 15576 EXCEPTIONS: AVX512-E3 15577 REAL_OPCODE: Y 15578 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15579 PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 15580 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 15581 IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 15582 } 15583 15584 { 15585 ICLASS: VFMADD231SD 15586 CPL: 3 15587 CATEGORY: VFMA 15588 EXTENSION: AVX512EVEX 15589 ISA_SET: AVX512F_SCALAR 15590 EXCEPTIONS: AVX512-E3 15591 REAL_OPCODE: Y 15592 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15593 PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 15594 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 15595 IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 15596 } 15597 15598 { 15599 ICLASS: VFMADD231SD 15600 CPL: 3 15601 CATEGORY: VFMA 15602 EXTENSION: AVX512EVEX 15603 ISA_SET: AVX512F_SCALAR 15604 EXCEPTIONS: AVX512-E3 15605 REAL_OPCODE: Y 15606 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 15607 PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 15608 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 15609 IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 15610 } 15611 15612 15613 # EMITTING VFMADD231SS (VFMADD231SS-128-1) 15614 { 15615 ICLASS: VFMADD231SS 15616 CPL: 3 15617 CATEGORY: VFMA 15618 EXTENSION: AVX512EVEX 15619 ISA_SET: AVX512F_SCALAR 15620 EXCEPTIONS: AVX512-E3 15621 REAL_OPCODE: Y 15622 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15623 PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 15624 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 15625 IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 15626 } 15627 15628 { 15629 ICLASS: VFMADD231SS 15630 CPL: 3 15631 CATEGORY: VFMA 15632 EXTENSION: AVX512EVEX 15633 ISA_SET: AVX512F_SCALAR 15634 EXCEPTIONS: AVX512-E3 15635 REAL_OPCODE: Y 15636 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 15637 PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 15638 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 15639 IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 15640 } 15641 15642 { 15643 ICLASS: VFMADD231SS 15644 CPL: 3 15645 CATEGORY: VFMA 15646 EXTENSION: AVX512EVEX 15647 ISA_SET: AVX512F_SCALAR 15648 EXCEPTIONS: AVX512-E3 15649 REAL_OPCODE: Y 15650 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 15651 PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 15652 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 15653 IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 15654 } 15655 15656 15657 # EMITTING VFMADDSUB132PD (VFMADDSUB132PD-512-1) 15658 { 15659 ICLASS: VFMADDSUB132PD 15660 CPL: 3 15661 CATEGORY: VFMA 15662 EXTENSION: AVX512EVEX 15663 ISA_SET: AVX512F_512 15664 EXCEPTIONS: AVX512-E2 15665 REAL_OPCODE: Y 15666 ATTRIBUTES: MASKOP_EVEX MXCSR 15667 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 15668 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15669 IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15670 } 15671 15672 { 15673 ICLASS: VFMADDSUB132PD 15674 CPL: 3 15675 CATEGORY: VFMA 15676 EXTENSION: AVX512EVEX 15677 ISA_SET: AVX512F_512 15678 EXCEPTIONS: AVX512-E2 15679 REAL_OPCODE: Y 15680 ATTRIBUTES: MASKOP_EVEX MXCSR 15681 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 15682 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15683 IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15684 } 15685 15686 { 15687 ICLASS: VFMADDSUB132PD 15688 CPL: 3 15689 CATEGORY: VFMA 15690 EXTENSION: AVX512EVEX 15691 ISA_SET: AVX512F_512 15692 EXCEPTIONS: AVX512-E2 15693 REAL_OPCODE: Y 15694 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15695 PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 15696 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 15697 IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 15698 } 15699 15700 15701 # EMITTING VFMADDSUB132PS (VFMADDSUB132PS-512-1) 15702 { 15703 ICLASS: VFMADDSUB132PS 15704 CPL: 3 15705 CATEGORY: VFMA 15706 EXTENSION: AVX512EVEX 15707 ISA_SET: AVX512F_512 15708 EXCEPTIONS: AVX512-E2 15709 REAL_OPCODE: Y 15710 ATTRIBUTES: MASKOP_EVEX MXCSR 15711 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 15712 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15713 IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15714 } 15715 15716 { 15717 ICLASS: VFMADDSUB132PS 15718 CPL: 3 15719 CATEGORY: VFMA 15720 EXTENSION: AVX512EVEX 15721 ISA_SET: AVX512F_512 15722 EXCEPTIONS: AVX512-E2 15723 REAL_OPCODE: Y 15724 ATTRIBUTES: MASKOP_EVEX MXCSR 15725 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 15726 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15727 IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15728 } 15729 15730 { 15731 ICLASS: VFMADDSUB132PS 15732 CPL: 3 15733 CATEGORY: VFMA 15734 EXTENSION: AVX512EVEX 15735 ISA_SET: AVX512F_512 15736 EXCEPTIONS: AVX512-E2 15737 REAL_OPCODE: Y 15738 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15739 PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 15740 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 15741 IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 15742 } 15743 15744 15745 # EMITTING VFMADDSUB213PD (VFMADDSUB213PD-512-1) 15746 { 15747 ICLASS: VFMADDSUB213PD 15748 CPL: 3 15749 CATEGORY: VFMA 15750 EXTENSION: AVX512EVEX 15751 ISA_SET: AVX512F_512 15752 EXCEPTIONS: AVX512-E2 15753 REAL_OPCODE: Y 15754 ATTRIBUTES: MASKOP_EVEX MXCSR 15755 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 15756 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15757 IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15758 } 15759 15760 { 15761 ICLASS: VFMADDSUB213PD 15762 CPL: 3 15763 CATEGORY: VFMA 15764 EXTENSION: AVX512EVEX 15765 ISA_SET: AVX512F_512 15766 EXCEPTIONS: AVX512-E2 15767 REAL_OPCODE: Y 15768 ATTRIBUTES: MASKOP_EVEX MXCSR 15769 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 15770 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15771 IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15772 } 15773 15774 { 15775 ICLASS: VFMADDSUB213PD 15776 CPL: 3 15777 CATEGORY: VFMA 15778 EXTENSION: AVX512EVEX 15779 ISA_SET: AVX512F_512 15780 EXCEPTIONS: AVX512-E2 15781 REAL_OPCODE: Y 15782 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15783 PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 15784 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 15785 IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 15786 } 15787 15788 15789 # EMITTING VFMADDSUB213PS (VFMADDSUB213PS-512-1) 15790 { 15791 ICLASS: VFMADDSUB213PS 15792 CPL: 3 15793 CATEGORY: VFMA 15794 EXTENSION: AVX512EVEX 15795 ISA_SET: AVX512F_512 15796 EXCEPTIONS: AVX512-E2 15797 REAL_OPCODE: Y 15798 ATTRIBUTES: MASKOP_EVEX MXCSR 15799 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 15800 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15801 IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15802 } 15803 15804 { 15805 ICLASS: VFMADDSUB213PS 15806 CPL: 3 15807 CATEGORY: VFMA 15808 EXTENSION: AVX512EVEX 15809 ISA_SET: AVX512F_512 15810 EXCEPTIONS: AVX512-E2 15811 REAL_OPCODE: Y 15812 ATTRIBUTES: MASKOP_EVEX MXCSR 15813 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 15814 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15815 IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15816 } 15817 15818 { 15819 ICLASS: VFMADDSUB213PS 15820 CPL: 3 15821 CATEGORY: VFMA 15822 EXTENSION: AVX512EVEX 15823 ISA_SET: AVX512F_512 15824 EXCEPTIONS: AVX512-E2 15825 REAL_OPCODE: Y 15826 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15827 PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 15828 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 15829 IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 15830 } 15831 15832 15833 # EMITTING VFMADDSUB231PD (VFMADDSUB231PD-512-1) 15834 { 15835 ICLASS: VFMADDSUB231PD 15836 CPL: 3 15837 CATEGORY: VFMA 15838 EXTENSION: AVX512EVEX 15839 ISA_SET: AVX512F_512 15840 EXCEPTIONS: AVX512-E2 15841 REAL_OPCODE: Y 15842 ATTRIBUTES: MASKOP_EVEX MXCSR 15843 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 15844 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15845 IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15846 } 15847 15848 { 15849 ICLASS: VFMADDSUB231PD 15850 CPL: 3 15851 CATEGORY: VFMA 15852 EXTENSION: AVX512EVEX 15853 ISA_SET: AVX512F_512 15854 EXCEPTIONS: AVX512-E2 15855 REAL_OPCODE: Y 15856 ATTRIBUTES: MASKOP_EVEX MXCSR 15857 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 15858 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15859 IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15860 } 15861 15862 { 15863 ICLASS: VFMADDSUB231PD 15864 CPL: 3 15865 CATEGORY: VFMA 15866 EXTENSION: AVX512EVEX 15867 ISA_SET: AVX512F_512 15868 EXCEPTIONS: AVX512-E2 15869 REAL_OPCODE: Y 15870 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15871 PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 15872 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 15873 IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 15874 } 15875 15876 15877 # EMITTING VFMADDSUB231PS (VFMADDSUB231PS-512-1) 15878 { 15879 ICLASS: VFMADDSUB231PS 15880 CPL: 3 15881 CATEGORY: VFMA 15882 EXTENSION: AVX512EVEX 15883 ISA_SET: AVX512F_512 15884 EXCEPTIONS: AVX512-E2 15885 REAL_OPCODE: Y 15886 ATTRIBUTES: MASKOP_EVEX MXCSR 15887 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 15888 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15889 IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15890 } 15891 15892 { 15893 ICLASS: VFMADDSUB231PS 15894 CPL: 3 15895 CATEGORY: VFMA 15896 EXTENSION: AVX512EVEX 15897 ISA_SET: AVX512F_512 15898 EXCEPTIONS: AVX512-E2 15899 REAL_OPCODE: Y 15900 ATTRIBUTES: MASKOP_EVEX MXCSR 15901 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 15902 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15903 IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15904 } 15905 15906 { 15907 ICLASS: VFMADDSUB231PS 15908 CPL: 3 15909 CATEGORY: VFMA 15910 EXTENSION: AVX512EVEX 15911 ISA_SET: AVX512F_512 15912 EXCEPTIONS: AVX512-E2 15913 REAL_OPCODE: Y 15914 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15915 PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 15916 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 15917 IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 15918 } 15919 15920 15921 # EMITTING VFMSUB132PD (VFMSUB132PD-512-1) 15922 { 15923 ICLASS: VFMSUB132PD 15924 CPL: 3 15925 CATEGORY: VFMA 15926 EXTENSION: AVX512EVEX 15927 ISA_SET: AVX512F_512 15928 EXCEPTIONS: AVX512-E2 15929 REAL_OPCODE: Y 15930 ATTRIBUTES: MASKOP_EVEX MXCSR 15931 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 15932 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15933 IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15934 } 15935 15936 { 15937 ICLASS: VFMSUB132PD 15938 CPL: 3 15939 CATEGORY: VFMA 15940 EXTENSION: AVX512EVEX 15941 ISA_SET: AVX512F_512 15942 EXCEPTIONS: AVX512-E2 15943 REAL_OPCODE: Y 15944 ATTRIBUTES: MASKOP_EVEX MXCSR 15945 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 15946 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 15947 IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 15948 } 15949 15950 { 15951 ICLASS: VFMSUB132PD 15952 CPL: 3 15953 CATEGORY: VFMA 15954 EXTENSION: AVX512EVEX 15955 ISA_SET: AVX512F_512 15956 EXCEPTIONS: AVX512-E2 15957 REAL_OPCODE: Y 15958 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 15959 PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 15960 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 15961 IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 15962 } 15963 15964 15965 # EMITTING VFMSUB132PS (VFMSUB132PS-512-1) 15966 { 15967 ICLASS: VFMSUB132PS 15968 CPL: 3 15969 CATEGORY: VFMA 15970 EXTENSION: AVX512EVEX 15971 ISA_SET: AVX512F_512 15972 EXCEPTIONS: AVX512-E2 15973 REAL_OPCODE: Y 15974 ATTRIBUTES: MASKOP_EVEX MXCSR 15975 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 15976 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15977 IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15978 } 15979 15980 { 15981 ICLASS: VFMSUB132PS 15982 CPL: 3 15983 CATEGORY: VFMA 15984 EXTENSION: AVX512EVEX 15985 ISA_SET: AVX512F_512 15986 EXCEPTIONS: AVX512-E2 15987 REAL_OPCODE: Y 15988 ATTRIBUTES: MASKOP_EVEX MXCSR 15989 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 15990 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 15991 IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 15992 } 15993 15994 { 15995 ICLASS: VFMSUB132PS 15996 CPL: 3 15997 CATEGORY: VFMA 15998 EXTENSION: AVX512EVEX 15999 ISA_SET: AVX512F_512 16000 EXCEPTIONS: AVX512-E2 16001 REAL_OPCODE: Y 16002 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16003 PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 16004 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 16005 IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 16006 } 16007 16008 16009 # EMITTING VFMSUB132SD (VFMSUB132SD-128-1) 16010 { 16011 ICLASS: VFMSUB132SD 16012 CPL: 3 16013 CATEGORY: VFMA 16014 EXTENSION: AVX512EVEX 16015 ISA_SET: AVX512F_SCALAR 16016 EXCEPTIONS: AVX512-E3 16017 REAL_OPCODE: Y 16018 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16019 PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 16020 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 16021 IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 16022 } 16023 16024 { 16025 ICLASS: VFMSUB132SD 16026 CPL: 3 16027 CATEGORY: VFMA 16028 EXTENSION: AVX512EVEX 16029 ISA_SET: AVX512F_SCALAR 16030 EXCEPTIONS: AVX512-E3 16031 REAL_OPCODE: Y 16032 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16033 PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 16034 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 16035 IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 16036 } 16037 16038 { 16039 ICLASS: VFMSUB132SD 16040 CPL: 3 16041 CATEGORY: VFMA 16042 EXTENSION: AVX512EVEX 16043 ISA_SET: AVX512F_SCALAR 16044 EXCEPTIONS: AVX512-E3 16045 REAL_OPCODE: Y 16046 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 16047 PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 16048 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 16049 IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 16050 } 16051 16052 16053 # EMITTING VFMSUB132SS (VFMSUB132SS-128-1) 16054 { 16055 ICLASS: VFMSUB132SS 16056 CPL: 3 16057 CATEGORY: VFMA 16058 EXTENSION: AVX512EVEX 16059 ISA_SET: AVX512F_SCALAR 16060 EXCEPTIONS: AVX512-E3 16061 REAL_OPCODE: Y 16062 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16063 PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 16064 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 16065 IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 16066 } 16067 16068 { 16069 ICLASS: VFMSUB132SS 16070 CPL: 3 16071 CATEGORY: VFMA 16072 EXTENSION: AVX512EVEX 16073 ISA_SET: AVX512F_SCALAR 16074 EXCEPTIONS: AVX512-E3 16075 REAL_OPCODE: Y 16076 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16077 PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 16078 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 16079 IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 16080 } 16081 16082 { 16083 ICLASS: VFMSUB132SS 16084 CPL: 3 16085 CATEGORY: VFMA 16086 EXTENSION: AVX512EVEX 16087 ISA_SET: AVX512F_SCALAR 16088 EXCEPTIONS: AVX512-E3 16089 REAL_OPCODE: Y 16090 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 16091 PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 16092 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 16093 IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 16094 } 16095 16096 16097 # EMITTING VFMSUB213PD (VFMSUB213PD-512-1) 16098 { 16099 ICLASS: VFMSUB213PD 16100 CPL: 3 16101 CATEGORY: VFMA 16102 EXTENSION: AVX512EVEX 16103 ISA_SET: AVX512F_512 16104 EXCEPTIONS: AVX512-E2 16105 REAL_OPCODE: Y 16106 ATTRIBUTES: MASKOP_EVEX MXCSR 16107 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 16108 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16109 IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16110 } 16111 16112 { 16113 ICLASS: VFMSUB213PD 16114 CPL: 3 16115 CATEGORY: VFMA 16116 EXTENSION: AVX512EVEX 16117 ISA_SET: AVX512F_512 16118 EXCEPTIONS: AVX512-E2 16119 REAL_OPCODE: Y 16120 ATTRIBUTES: MASKOP_EVEX MXCSR 16121 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 16122 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16123 IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16124 } 16125 16126 { 16127 ICLASS: VFMSUB213PD 16128 CPL: 3 16129 CATEGORY: VFMA 16130 EXTENSION: AVX512EVEX 16131 ISA_SET: AVX512F_512 16132 EXCEPTIONS: AVX512-E2 16133 REAL_OPCODE: Y 16134 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16135 PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 16136 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 16137 IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 16138 } 16139 16140 16141 # EMITTING VFMSUB213PS (VFMSUB213PS-512-1) 16142 { 16143 ICLASS: VFMSUB213PS 16144 CPL: 3 16145 CATEGORY: VFMA 16146 EXTENSION: AVX512EVEX 16147 ISA_SET: AVX512F_512 16148 EXCEPTIONS: AVX512-E2 16149 REAL_OPCODE: Y 16150 ATTRIBUTES: MASKOP_EVEX MXCSR 16151 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 16152 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16153 IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16154 } 16155 16156 { 16157 ICLASS: VFMSUB213PS 16158 CPL: 3 16159 CATEGORY: VFMA 16160 EXTENSION: AVX512EVEX 16161 ISA_SET: AVX512F_512 16162 EXCEPTIONS: AVX512-E2 16163 REAL_OPCODE: Y 16164 ATTRIBUTES: MASKOP_EVEX MXCSR 16165 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 16166 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16167 IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16168 } 16169 16170 { 16171 ICLASS: VFMSUB213PS 16172 CPL: 3 16173 CATEGORY: VFMA 16174 EXTENSION: AVX512EVEX 16175 ISA_SET: AVX512F_512 16176 EXCEPTIONS: AVX512-E2 16177 REAL_OPCODE: Y 16178 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16179 PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 16180 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 16181 IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 16182 } 16183 16184 16185 # EMITTING VFMSUB213SD (VFMSUB213SD-128-1) 16186 { 16187 ICLASS: VFMSUB213SD 16188 CPL: 3 16189 CATEGORY: VFMA 16190 EXTENSION: AVX512EVEX 16191 ISA_SET: AVX512F_SCALAR 16192 EXCEPTIONS: AVX512-E3 16193 REAL_OPCODE: Y 16194 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16195 PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 16196 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 16197 IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 16198 } 16199 16200 { 16201 ICLASS: VFMSUB213SD 16202 CPL: 3 16203 CATEGORY: VFMA 16204 EXTENSION: AVX512EVEX 16205 ISA_SET: AVX512F_SCALAR 16206 EXCEPTIONS: AVX512-E3 16207 REAL_OPCODE: Y 16208 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16209 PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 16210 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 16211 IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 16212 } 16213 16214 { 16215 ICLASS: VFMSUB213SD 16216 CPL: 3 16217 CATEGORY: VFMA 16218 EXTENSION: AVX512EVEX 16219 ISA_SET: AVX512F_SCALAR 16220 EXCEPTIONS: AVX512-E3 16221 REAL_OPCODE: Y 16222 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 16223 PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 16224 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 16225 IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 16226 } 16227 16228 16229 # EMITTING VFMSUB213SS (VFMSUB213SS-128-1) 16230 { 16231 ICLASS: VFMSUB213SS 16232 CPL: 3 16233 CATEGORY: VFMA 16234 EXTENSION: AVX512EVEX 16235 ISA_SET: AVX512F_SCALAR 16236 EXCEPTIONS: AVX512-E3 16237 REAL_OPCODE: Y 16238 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16239 PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 16240 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 16241 IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 16242 } 16243 16244 { 16245 ICLASS: VFMSUB213SS 16246 CPL: 3 16247 CATEGORY: VFMA 16248 EXTENSION: AVX512EVEX 16249 ISA_SET: AVX512F_SCALAR 16250 EXCEPTIONS: AVX512-E3 16251 REAL_OPCODE: Y 16252 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16253 PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 16254 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 16255 IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 16256 } 16257 16258 { 16259 ICLASS: VFMSUB213SS 16260 CPL: 3 16261 CATEGORY: VFMA 16262 EXTENSION: AVX512EVEX 16263 ISA_SET: AVX512F_SCALAR 16264 EXCEPTIONS: AVX512-E3 16265 REAL_OPCODE: Y 16266 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 16267 PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 16268 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 16269 IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 16270 } 16271 16272 16273 # EMITTING VFMSUB231PD (VFMSUB231PD-512-1) 16274 { 16275 ICLASS: VFMSUB231PD 16276 CPL: 3 16277 CATEGORY: VFMA 16278 EXTENSION: AVX512EVEX 16279 ISA_SET: AVX512F_512 16280 EXCEPTIONS: AVX512-E2 16281 REAL_OPCODE: Y 16282 ATTRIBUTES: MASKOP_EVEX MXCSR 16283 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 16284 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16285 IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16286 } 16287 16288 { 16289 ICLASS: VFMSUB231PD 16290 CPL: 3 16291 CATEGORY: VFMA 16292 EXTENSION: AVX512EVEX 16293 ISA_SET: AVX512F_512 16294 EXCEPTIONS: AVX512-E2 16295 REAL_OPCODE: Y 16296 ATTRIBUTES: MASKOP_EVEX MXCSR 16297 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 16298 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16299 IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16300 } 16301 16302 { 16303 ICLASS: VFMSUB231PD 16304 CPL: 3 16305 CATEGORY: VFMA 16306 EXTENSION: AVX512EVEX 16307 ISA_SET: AVX512F_512 16308 EXCEPTIONS: AVX512-E2 16309 REAL_OPCODE: Y 16310 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16311 PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 16312 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 16313 IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 16314 } 16315 16316 16317 # EMITTING VFMSUB231PS (VFMSUB231PS-512-1) 16318 { 16319 ICLASS: VFMSUB231PS 16320 CPL: 3 16321 CATEGORY: VFMA 16322 EXTENSION: AVX512EVEX 16323 ISA_SET: AVX512F_512 16324 EXCEPTIONS: AVX512-E2 16325 REAL_OPCODE: Y 16326 ATTRIBUTES: MASKOP_EVEX MXCSR 16327 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 16328 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16329 IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16330 } 16331 16332 { 16333 ICLASS: VFMSUB231PS 16334 CPL: 3 16335 CATEGORY: VFMA 16336 EXTENSION: AVX512EVEX 16337 ISA_SET: AVX512F_512 16338 EXCEPTIONS: AVX512-E2 16339 REAL_OPCODE: Y 16340 ATTRIBUTES: MASKOP_EVEX MXCSR 16341 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 16342 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16343 IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16344 } 16345 16346 { 16347 ICLASS: VFMSUB231PS 16348 CPL: 3 16349 CATEGORY: VFMA 16350 EXTENSION: AVX512EVEX 16351 ISA_SET: AVX512F_512 16352 EXCEPTIONS: AVX512-E2 16353 REAL_OPCODE: Y 16354 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16355 PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 16356 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 16357 IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 16358 } 16359 16360 16361 # EMITTING VFMSUB231SD (VFMSUB231SD-128-1) 16362 { 16363 ICLASS: VFMSUB231SD 16364 CPL: 3 16365 CATEGORY: VFMA 16366 EXTENSION: AVX512EVEX 16367 ISA_SET: AVX512F_SCALAR 16368 EXCEPTIONS: AVX512-E3 16369 REAL_OPCODE: Y 16370 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16371 PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 16372 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 16373 IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 16374 } 16375 16376 { 16377 ICLASS: VFMSUB231SD 16378 CPL: 3 16379 CATEGORY: VFMA 16380 EXTENSION: AVX512EVEX 16381 ISA_SET: AVX512F_SCALAR 16382 EXCEPTIONS: AVX512-E3 16383 REAL_OPCODE: Y 16384 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16385 PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 16386 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 16387 IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 16388 } 16389 16390 { 16391 ICLASS: VFMSUB231SD 16392 CPL: 3 16393 CATEGORY: VFMA 16394 EXTENSION: AVX512EVEX 16395 ISA_SET: AVX512F_SCALAR 16396 EXCEPTIONS: AVX512-E3 16397 REAL_OPCODE: Y 16398 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 16399 PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 16400 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 16401 IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 16402 } 16403 16404 16405 # EMITTING VFMSUB231SS (VFMSUB231SS-128-1) 16406 { 16407 ICLASS: VFMSUB231SS 16408 CPL: 3 16409 CATEGORY: VFMA 16410 EXTENSION: AVX512EVEX 16411 ISA_SET: AVX512F_SCALAR 16412 EXCEPTIONS: AVX512-E3 16413 REAL_OPCODE: Y 16414 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16415 PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 16416 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 16417 IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 16418 } 16419 16420 { 16421 ICLASS: VFMSUB231SS 16422 CPL: 3 16423 CATEGORY: VFMA 16424 EXTENSION: AVX512EVEX 16425 ISA_SET: AVX512F_SCALAR 16426 EXCEPTIONS: AVX512-E3 16427 REAL_OPCODE: Y 16428 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16429 PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 16430 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 16431 IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 16432 } 16433 16434 { 16435 ICLASS: VFMSUB231SS 16436 CPL: 3 16437 CATEGORY: VFMA 16438 EXTENSION: AVX512EVEX 16439 ISA_SET: AVX512F_SCALAR 16440 EXCEPTIONS: AVX512-E3 16441 REAL_OPCODE: Y 16442 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 16443 PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 16444 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 16445 IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 16446 } 16447 16448 16449 # EMITTING VFMSUBADD132PD (VFMSUBADD132PD-512-1) 16450 { 16451 ICLASS: VFMSUBADD132PD 16452 CPL: 3 16453 CATEGORY: VFMA 16454 EXTENSION: AVX512EVEX 16455 ISA_SET: AVX512F_512 16456 EXCEPTIONS: AVX512-E2 16457 REAL_OPCODE: Y 16458 ATTRIBUTES: MASKOP_EVEX MXCSR 16459 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 16460 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16461 IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16462 } 16463 16464 { 16465 ICLASS: VFMSUBADD132PD 16466 CPL: 3 16467 CATEGORY: VFMA 16468 EXTENSION: AVX512EVEX 16469 ISA_SET: AVX512F_512 16470 EXCEPTIONS: AVX512-E2 16471 REAL_OPCODE: Y 16472 ATTRIBUTES: MASKOP_EVEX MXCSR 16473 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 16474 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16475 IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16476 } 16477 16478 { 16479 ICLASS: VFMSUBADD132PD 16480 CPL: 3 16481 CATEGORY: VFMA 16482 EXTENSION: AVX512EVEX 16483 ISA_SET: AVX512F_512 16484 EXCEPTIONS: AVX512-E2 16485 REAL_OPCODE: Y 16486 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16487 PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 16488 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 16489 IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 16490 } 16491 16492 16493 # EMITTING VFMSUBADD132PS (VFMSUBADD132PS-512-1) 16494 { 16495 ICLASS: VFMSUBADD132PS 16496 CPL: 3 16497 CATEGORY: VFMA 16498 EXTENSION: AVX512EVEX 16499 ISA_SET: AVX512F_512 16500 EXCEPTIONS: AVX512-E2 16501 REAL_OPCODE: Y 16502 ATTRIBUTES: MASKOP_EVEX MXCSR 16503 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 16504 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16505 IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16506 } 16507 16508 { 16509 ICLASS: VFMSUBADD132PS 16510 CPL: 3 16511 CATEGORY: VFMA 16512 EXTENSION: AVX512EVEX 16513 ISA_SET: AVX512F_512 16514 EXCEPTIONS: AVX512-E2 16515 REAL_OPCODE: Y 16516 ATTRIBUTES: MASKOP_EVEX MXCSR 16517 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 16518 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16519 IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16520 } 16521 16522 { 16523 ICLASS: VFMSUBADD132PS 16524 CPL: 3 16525 CATEGORY: VFMA 16526 EXTENSION: AVX512EVEX 16527 ISA_SET: AVX512F_512 16528 EXCEPTIONS: AVX512-E2 16529 REAL_OPCODE: Y 16530 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16531 PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 16532 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 16533 IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 16534 } 16535 16536 16537 # EMITTING VFMSUBADD213PD (VFMSUBADD213PD-512-1) 16538 { 16539 ICLASS: VFMSUBADD213PD 16540 CPL: 3 16541 CATEGORY: VFMA 16542 EXTENSION: AVX512EVEX 16543 ISA_SET: AVX512F_512 16544 EXCEPTIONS: AVX512-E2 16545 REAL_OPCODE: Y 16546 ATTRIBUTES: MASKOP_EVEX MXCSR 16547 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 16548 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16549 IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16550 } 16551 16552 { 16553 ICLASS: VFMSUBADD213PD 16554 CPL: 3 16555 CATEGORY: VFMA 16556 EXTENSION: AVX512EVEX 16557 ISA_SET: AVX512F_512 16558 EXCEPTIONS: AVX512-E2 16559 REAL_OPCODE: Y 16560 ATTRIBUTES: MASKOP_EVEX MXCSR 16561 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 16562 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16563 IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16564 } 16565 16566 { 16567 ICLASS: VFMSUBADD213PD 16568 CPL: 3 16569 CATEGORY: VFMA 16570 EXTENSION: AVX512EVEX 16571 ISA_SET: AVX512F_512 16572 EXCEPTIONS: AVX512-E2 16573 REAL_OPCODE: Y 16574 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16575 PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 16576 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 16577 IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 16578 } 16579 16580 16581 # EMITTING VFMSUBADD213PS (VFMSUBADD213PS-512-1) 16582 { 16583 ICLASS: VFMSUBADD213PS 16584 CPL: 3 16585 CATEGORY: VFMA 16586 EXTENSION: AVX512EVEX 16587 ISA_SET: AVX512F_512 16588 EXCEPTIONS: AVX512-E2 16589 REAL_OPCODE: Y 16590 ATTRIBUTES: MASKOP_EVEX MXCSR 16591 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 16592 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16593 IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16594 } 16595 16596 { 16597 ICLASS: VFMSUBADD213PS 16598 CPL: 3 16599 CATEGORY: VFMA 16600 EXTENSION: AVX512EVEX 16601 ISA_SET: AVX512F_512 16602 EXCEPTIONS: AVX512-E2 16603 REAL_OPCODE: Y 16604 ATTRIBUTES: MASKOP_EVEX MXCSR 16605 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 16606 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16607 IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16608 } 16609 16610 { 16611 ICLASS: VFMSUBADD213PS 16612 CPL: 3 16613 CATEGORY: VFMA 16614 EXTENSION: AVX512EVEX 16615 ISA_SET: AVX512F_512 16616 EXCEPTIONS: AVX512-E2 16617 REAL_OPCODE: Y 16618 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16619 PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 16620 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 16621 IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 16622 } 16623 16624 16625 # EMITTING VFMSUBADD231PD (VFMSUBADD231PD-512-1) 16626 { 16627 ICLASS: VFMSUBADD231PD 16628 CPL: 3 16629 CATEGORY: VFMA 16630 EXTENSION: AVX512EVEX 16631 ISA_SET: AVX512F_512 16632 EXCEPTIONS: AVX512-E2 16633 REAL_OPCODE: Y 16634 ATTRIBUTES: MASKOP_EVEX MXCSR 16635 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 16636 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16637 IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16638 } 16639 16640 { 16641 ICLASS: VFMSUBADD231PD 16642 CPL: 3 16643 CATEGORY: VFMA 16644 EXTENSION: AVX512EVEX 16645 ISA_SET: AVX512F_512 16646 EXCEPTIONS: AVX512-E2 16647 REAL_OPCODE: Y 16648 ATTRIBUTES: MASKOP_EVEX MXCSR 16649 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 16650 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16651 IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16652 } 16653 16654 { 16655 ICLASS: VFMSUBADD231PD 16656 CPL: 3 16657 CATEGORY: VFMA 16658 EXTENSION: AVX512EVEX 16659 ISA_SET: AVX512F_512 16660 EXCEPTIONS: AVX512-E2 16661 REAL_OPCODE: Y 16662 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16663 PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 16664 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 16665 IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 16666 } 16667 16668 16669 # EMITTING VFMSUBADD231PS (VFMSUBADD231PS-512-1) 16670 { 16671 ICLASS: VFMSUBADD231PS 16672 CPL: 3 16673 CATEGORY: VFMA 16674 EXTENSION: AVX512EVEX 16675 ISA_SET: AVX512F_512 16676 EXCEPTIONS: AVX512-E2 16677 REAL_OPCODE: Y 16678 ATTRIBUTES: MASKOP_EVEX MXCSR 16679 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 16680 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16681 IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16682 } 16683 16684 { 16685 ICLASS: VFMSUBADD231PS 16686 CPL: 3 16687 CATEGORY: VFMA 16688 EXTENSION: AVX512EVEX 16689 ISA_SET: AVX512F_512 16690 EXCEPTIONS: AVX512-E2 16691 REAL_OPCODE: Y 16692 ATTRIBUTES: MASKOP_EVEX MXCSR 16693 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 16694 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16695 IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16696 } 16697 16698 { 16699 ICLASS: VFMSUBADD231PS 16700 CPL: 3 16701 CATEGORY: VFMA 16702 EXTENSION: AVX512EVEX 16703 ISA_SET: AVX512F_512 16704 EXCEPTIONS: AVX512-E2 16705 REAL_OPCODE: Y 16706 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16707 PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 16708 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 16709 IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 16710 } 16711 16712 16713 # EMITTING VFNMADD132PD (VFNMADD132PD-512-1) 16714 { 16715 ICLASS: VFNMADD132PD 16716 CPL: 3 16717 CATEGORY: VFMA 16718 EXTENSION: AVX512EVEX 16719 ISA_SET: AVX512F_512 16720 EXCEPTIONS: AVX512-E2 16721 REAL_OPCODE: Y 16722 ATTRIBUTES: MASKOP_EVEX MXCSR 16723 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 16724 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16725 IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16726 } 16727 16728 { 16729 ICLASS: VFNMADD132PD 16730 CPL: 3 16731 CATEGORY: VFMA 16732 EXTENSION: AVX512EVEX 16733 ISA_SET: AVX512F_512 16734 EXCEPTIONS: AVX512-E2 16735 REAL_OPCODE: Y 16736 ATTRIBUTES: MASKOP_EVEX MXCSR 16737 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 16738 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16739 IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16740 } 16741 16742 { 16743 ICLASS: VFNMADD132PD 16744 CPL: 3 16745 CATEGORY: VFMA 16746 EXTENSION: AVX512EVEX 16747 ISA_SET: AVX512F_512 16748 EXCEPTIONS: AVX512-E2 16749 REAL_OPCODE: Y 16750 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16751 PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 16752 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 16753 IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 16754 } 16755 16756 16757 # EMITTING VFNMADD132PS (VFNMADD132PS-512-1) 16758 { 16759 ICLASS: VFNMADD132PS 16760 CPL: 3 16761 CATEGORY: VFMA 16762 EXTENSION: AVX512EVEX 16763 ISA_SET: AVX512F_512 16764 EXCEPTIONS: AVX512-E2 16765 REAL_OPCODE: Y 16766 ATTRIBUTES: MASKOP_EVEX MXCSR 16767 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 16768 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16769 IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16770 } 16771 16772 { 16773 ICLASS: VFNMADD132PS 16774 CPL: 3 16775 CATEGORY: VFMA 16776 EXTENSION: AVX512EVEX 16777 ISA_SET: AVX512F_512 16778 EXCEPTIONS: AVX512-E2 16779 REAL_OPCODE: Y 16780 ATTRIBUTES: MASKOP_EVEX MXCSR 16781 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 16782 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16783 IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16784 } 16785 16786 { 16787 ICLASS: VFNMADD132PS 16788 CPL: 3 16789 CATEGORY: VFMA 16790 EXTENSION: AVX512EVEX 16791 ISA_SET: AVX512F_512 16792 EXCEPTIONS: AVX512-E2 16793 REAL_OPCODE: Y 16794 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16795 PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 16796 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 16797 IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 16798 } 16799 16800 16801 # EMITTING VFNMADD132SD (VFNMADD132SD-128-1) 16802 { 16803 ICLASS: VFNMADD132SD 16804 CPL: 3 16805 CATEGORY: VFMA 16806 EXTENSION: AVX512EVEX 16807 ISA_SET: AVX512F_SCALAR 16808 EXCEPTIONS: AVX512-E3 16809 REAL_OPCODE: Y 16810 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16811 PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 16812 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 16813 IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 16814 } 16815 16816 { 16817 ICLASS: VFNMADD132SD 16818 CPL: 3 16819 CATEGORY: VFMA 16820 EXTENSION: AVX512EVEX 16821 ISA_SET: AVX512F_SCALAR 16822 EXCEPTIONS: AVX512-E3 16823 REAL_OPCODE: Y 16824 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16825 PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 16826 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 16827 IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 16828 } 16829 16830 { 16831 ICLASS: VFNMADD132SD 16832 CPL: 3 16833 CATEGORY: VFMA 16834 EXTENSION: AVX512EVEX 16835 ISA_SET: AVX512F_SCALAR 16836 EXCEPTIONS: AVX512-E3 16837 REAL_OPCODE: Y 16838 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 16839 PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 16840 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 16841 IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 16842 } 16843 16844 16845 # EMITTING VFNMADD132SS (VFNMADD132SS-128-1) 16846 { 16847 ICLASS: VFNMADD132SS 16848 CPL: 3 16849 CATEGORY: VFMA 16850 EXTENSION: AVX512EVEX 16851 ISA_SET: AVX512F_SCALAR 16852 EXCEPTIONS: AVX512-E3 16853 REAL_OPCODE: Y 16854 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16855 PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 16856 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 16857 IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 16858 } 16859 16860 { 16861 ICLASS: VFNMADD132SS 16862 CPL: 3 16863 CATEGORY: VFMA 16864 EXTENSION: AVX512EVEX 16865 ISA_SET: AVX512F_SCALAR 16866 EXCEPTIONS: AVX512-E3 16867 REAL_OPCODE: Y 16868 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16869 PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 16870 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 16871 IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 16872 } 16873 16874 { 16875 ICLASS: VFNMADD132SS 16876 CPL: 3 16877 CATEGORY: VFMA 16878 EXTENSION: AVX512EVEX 16879 ISA_SET: AVX512F_SCALAR 16880 EXCEPTIONS: AVX512-E3 16881 REAL_OPCODE: Y 16882 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 16883 PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 16884 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 16885 IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 16886 } 16887 16888 16889 # EMITTING VFNMADD213PD (VFNMADD213PD-512-1) 16890 { 16891 ICLASS: VFNMADD213PD 16892 CPL: 3 16893 CATEGORY: VFMA 16894 EXTENSION: AVX512EVEX 16895 ISA_SET: AVX512F_512 16896 EXCEPTIONS: AVX512-E2 16897 REAL_OPCODE: Y 16898 ATTRIBUTES: MASKOP_EVEX MXCSR 16899 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 16900 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16901 IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16902 } 16903 16904 { 16905 ICLASS: VFNMADD213PD 16906 CPL: 3 16907 CATEGORY: VFMA 16908 EXTENSION: AVX512EVEX 16909 ISA_SET: AVX512F_512 16910 EXCEPTIONS: AVX512-E2 16911 REAL_OPCODE: Y 16912 ATTRIBUTES: MASKOP_EVEX MXCSR 16913 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 16914 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 16915 IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 16916 } 16917 16918 { 16919 ICLASS: VFNMADD213PD 16920 CPL: 3 16921 CATEGORY: VFMA 16922 EXTENSION: AVX512EVEX 16923 ISA_SET: AVX512F_512 16924 EXCEPTIONS: AVX512-E2 16925 REAL_OPCODE: Y 16926 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16927 PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 16928 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 16929 IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 16930 } 16931 16932 16933 # EMITTING VFNMADD213PS (VFNMADD213PS-512-1) 16934 { 16935 ICLASS: VFNMADD213PS 16936 CPL: 3 16937 CATEGORY: VFMA 16938 EXTENSION: AVX512EVEX 16939 ISA_SET: AVX512F_512 16940 EXCEPTIONS: AVX512-E2 16941 REAL_OPCODE: Y 16942 ATTRIBUTES: MASKOP_EVEX MXCSR 16943 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 16944 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16945 IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16946 } 16947 16948 { 16949 ICLASS: VFNMADD213PS 16950 CPL: 3 16951 CATEGORY: VFMA 16952 EXTENSION: AVX512EVEX 16953 ISA_SET: AVX512F_512 16954 EXCEPTIONS: AVX512-E2 16955 REAL_OPCODE: Y 16956 ATTRIBUTES: MASKOP_EVEX MXCSR 16957 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 16958 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 16959 IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 16960 } 16961 16962 { 16963 ICLASS: VFNMADD213PS 16964 CPL: 3 16965 CATEGORY: VFMA 16966 EXTENSION: AVX512EVEX 16967 ISA_SET: AVX512F_512 16968 EXCEPTIONS: AVX512-E2 16969 REAL_OPCODE: Y 16970 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 16971 PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 16972 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 16973 IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 16974 } 16975 16976 16977 # EMITTING VFNMADD213SD (VFNMADD213SD-128-1) 16978 { 16979 ICLASS: VFNMADD213SD 16980 CPL: 3 16981 CATEGORY: VFMA 16982 EXTENSION: AVX512EVEX 16983 ISA_SET: AVX512F_SCALAR 16984 EXCEPTIONS: AVX512-E3 16985 REAL_OPCODE: Y 16986 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 16987 PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 16988 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 16989 IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 16990 } 16991 16992 { 16993 ICLASS: VFNMADD213SD 16994 CPL: 3 16995 CATEGORY: VFMA 16996 EXTENSION: AVX512EVEX 16997 ISA_SET: AVX512F_SCALAR 16998 EXCEPTIONS: AVX512-E3 16999 REAL_OPCODE: Y 17000 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17001 PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 17002 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 17003 IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 17004 } 17005 17006 { 17007 ICLASS: VFNMADD213SD 17008 CPL: 3 17009 CATEGORY: VFMA 17010 EXTENSION: AVX512EVEX 17011 ISA_SET: AVX512F_SCALAR 17012 EXCEPTIONS: AVX512-E3 17013 REAL_OPCODE: Y 17014 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 17015 PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 17016 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 17017 IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 17018 } 17019 17020 17021 # EMITTING VFNMADD213SS (VFNMADD213SS-128-1) 17022 { 17023 ICLASS: VFNMADD213SS 17024 CPL: 3 17025 CATEGORY: VFMA 17026 EXTENSION: AVX512EVEX 17027 ISA_SET: AVX512F_SCALAR 17028 EXCEPTIONS: AVX512-E3 17029 REAL_OPCODE: Y 17030 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17031 PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 17032 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 17033 IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 17034 } 17035 17036 { 17037 ICLASS: VFNMADD213SS 17038 CPL: 3 17039 CATEGORY: VFMA 17040 EXTENSION: AVX512EVEX 17041 ISA_SET: AVX512F_SCALAR 17042 EXCEPTIONS: AVX512-E3 17043 REAL_OPCODE: Y 17044 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17045 PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 17046 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 17047 IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 17048 } 17049 17050 { 17051 ICLASS: VFNMADD213SS 17052 CPL: 3 17053 CATEGORY: VFMA 17054 EXTENSION: AVX512EVEX 17055 ISA_SET: AVX512F_SCALAR 17056 EXCEPTIONS: AVX512-E3 17057 REAL_OPCODE: Y 17058 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 17059 PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 17060 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 17061 IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 17062 } 17063 17064 17065 # EMITTING VFNMADD231PD (VFNMADD231PD-512-1) 17066 { 17067 ICLASS: VFNMADD231PD 17068 CPL: 3 17069 CATEGORY: VFMA 17070 EXTENSION: AVX512EVEX 17071 ISA_SET: AVX512F_512 17072 EXCEPTIONS: AVX512-E2 17073 REAL_OPCODE: Y 17074 ATTRIBUTES: MASKOP_EVEX MXCSR 17075 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 17076 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 17077 IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 17078 } 17079 17080 { 17081 ICLASS: VFNMADD231PD 17082 CPL: 3 17083 CATEGORY: VFMA 17084 EXTENSION: AVX512EVEX 17085 ISA_SET: AVX512F_512 17086 EXCEPTIONS: AVX512-E2 17087 REAL_OPCODE: Y 17088 ATTRIBUTES: MASKOP_EVEX MXCSR 17089 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 17090 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 17091 IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 17092 } 17093 17094 { 17095 ICLASS: VFNMADD231PD 17096 CPL: 3 17097 CATEGORY: VFMA 17098 EXTENSION: AVX512EVEX 17099 ISA_SET: AVX512F_512 17100 EXCEPTIONS: AVX512-E2 17101 REAL_OPCODE: Y 17102 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 17103 PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 17104 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 17105 IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 17106 } 17107 17108 17109 # EMITTING VFNMADD231PS (VFNMADD231PS-512-1) 17110 { 17111 ICLASS: VFNMADD231PS 17112 CPL: 3 17113 CATEGORY: VFMA 17114 EXTENSION: AVX512EVEX 17115 ISA_SET: AVX512F_512 17116 EXCEPTIONS: AVX512-E2 17117 REAL_OPCODE: Y 17118 ATTRIBUTES: MASKOP_EVEX MXCSR 17119 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 17120 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 17121 IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 17122 } 17123 17124 { 17125 ICLASS: VFNMADD231PS 17126 CPL: 3 17127 CATEGORY: VFMA 17128 EXTENSION: AVX512EVEX 17129 ISA_SET: AVX512F_512 17130 EXCEPTIONS: AVX512-E2 17131 REAL_OPCODE: Y 17132 ATTRIBUTES: MASKOP_EVEX MXCSR 17133 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 17134 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 17135 IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 17136 } 17137 17138 { 17139 ICLASS: VFNMADD231PS 17140 CPL: 3 17141 CATEGORY: VFMA 17142 EXTENSION: AVX512EVEX 17143 ISA_SET: AVX512F_512 17144 EXCEPTIONS: AVX512-E2 17145 REAL_OPCODE: Y 17146 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 17147 PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 17148 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 17149 IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 17150 } 17151 17152 17153 # EMITTING VFNMADD231SD (VFNMADD231SD-128-1) 17154 { 17155 ICLASS: VFNMADD231SD 17156 CPL: 3 17157 CATEGORY: VFMA 17158 EXTENSION: AVX512EVEX 17159 ISA_SET: AVX512F_SCALAR 17160 EXCEPTIONS: AVX512-E3 17161 REAL_OPCODE: Y 17162 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17163 PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 17164 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 17165 IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 17166 } 17167 17168 { 17169 ICLASS: VFNMADD231SD 17170 CPL: 3 17171 CATEGORY: VFMA 17172 EXTENSION: AVX512EVEX 17173 ISA_SET: AVX512F_SCALAR 17174 EXCEPTIONS: AVX512-E3 17175 REAL_OPCODE: Y 17176 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17177 PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 17178 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 17179 IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 17180 } 17181 17182 { 17183 ICLASS: VFNMADD231SD 17184 CPL: 3 17185 CATEGORY: VFMA 17186 EXTENSION: AVX512EVEX 17187 ISA_SET: AVX512F_SCALAR 17188 EXCEPTIONS: AVX512-E3 17189 REAL_OPCODE: Y 17190 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 17191 PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 17192 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 17193 IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 17194 } 17195 17196 17197 # EMITTING VFNMADD231SS (VFNMADD231SS-128-1) 17198 { 17199 ICLASS: VFNMADD231SS 17200 CPL: 3 17201 CATEGORY: VFMA 17202 EXTENSION: AVX512EVEX 17203 ISA_SET: AVX512F_SCALAR 17204 EXCEPTIONS: AVX512-E3 17205 REAL_OPCODE: Y 17206 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17207 PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 17208 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 17209 IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 17210 } 17211 17212 { 17213 ICLASS: VFNMADD231SS 17214 CPL: 3 17215 CATEGORY: VFMA 17216 EXTENSION: AVX512EVEX 17217 ISA_SET: AVX512F_SCALAR 17218 EXCEPTIONS: AVX512-E3 17219 REAL_OPCODE: Y 17220 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17221 PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 17222 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 17223 IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 17224 } 17225 17226 { 17227 ICLASS: VFNMADD231SS 17228 CPL: 3 17229 CATEGORY: VFMA 17230 EXTENSION: AVX512EVEX 17231 ISA_SET: AVX512F_SCALAR 17232 EXCEPTIONS: AVX512-E3 17233 REAL_OPCODE: Y 17234 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 17235 PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 17236 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 17237 IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 17238 } 17239 17240 17241 # EMITTING VFNMSUB132PD (VFNMSUB132PD-512-1) 17242 { 17243 ICLASS: VFNMSUB132PD 17244 CPL: 3 17245 CATEGORY: VFMA 17246 EXTENSION: AVX512EVEX 17247 ISA_SET: AVX512F_512 17248 EXCEPTIONS: AVX512-E2 17249 REAL_OPCODE: Y 17250 ATTRIBUTES: MASKOP_EVEX MXCSR 17251 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 17252 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 17253 IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 17254 } 17255 17256 { 17257 ICLASS: VFNMSUB132PD 17258 CPL: 3 17259 CATEGORY: VFMA 17260 EXTENSION: AVX512EVEX 17261 ISA_SET: AVX512F_512 17262 EXCEPTIONS: AVX512-E2 17263 REAL_OPCODE: Y 17264 ATTRIBUTES: MASKOP_EVEX MXCSR 17265 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 17266 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 17267 IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 17268 } 17269 17270 { 17271 ICLASS: VFNMSUB132PD 17272 CPL: 3 17273 CATEGORY: VFMA 17274 EXTENSION: AVX512EVEX 17275 ISA_SET: AVX512F_512 17276 EXCEPTIONS: AVX512-E2 17277 REAL_OPCODE: Y 17278 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 17279 PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 17280 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 17281 IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 17282 } 17283 17284 17285 # EMITTING VFNMSUB132PS (VFNMSUB132PS-512-1) 17286 { 17287 ICLASS: VFNMSUB132PS 17288 CPL: 3 17289 CATEGORY: VFMA 17290 EXTENSION: AVX512EVEX 17291 ISA_SET: AVX512F_512 17292 EXCEPTIONS: AVX512-E2 17293 REAL_OPCODE: Y 17294 ATTRIBUTES: MASKOP_EVEX MXCSR 17295 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 17296 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 17297 IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 17298 } 17299 17300 { 17301 ICLASS: VFNMSUB132PS 17302 CPL: 3 17303 CATEGORY: VFMA 17304 EXTENSION: AVX512EVEX 17305 ISA_SET: AVX512F_512 17306 EXCEPTIONS: AVX512-E2 17307 REAL_OPCODE: Y 17308 ATTRIBUTES: MASKOP_EVEX MXCSR 17309 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 17310 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 17311 IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 17312 } 17313 17314 { 17315 ICLASS: VFNMSUB132PS 17316 CPL: 3 17317 CATEGORY: VFMA 17318 EXTENSION: AVX512EVEX 17319 ISA_SET: AVX512F_512 17320 EXCEPTIONS: AVX512-E2 17321 REAL_OPCODE: Y 17322 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 17323 PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 17324 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 17325 IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 17326 } 17327 17328 17329 # EMITTING VFNMSUB132SD (VFNMSUB132SD-128-1) 17330 { 17331 ICLASS: VFNMSUB132SD 17332 CPL: 3 17333 CATEGORY: VFMA 17334 EXTENSION: AVX512EVEX 17335 ISA_SET: AVX512F_SCALAR 17336 EXCEPTIONS: AVX512-E3 17337 REAL_OPCODE: Y 17338 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17339 PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 17340 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 17341 IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 17342 } 17343 17344 { 17345 ICLASS: VFNMSUB132SD 17346 CPL: 3 17347 CATEGORY: VFMA 17348 EXTENSION: AVX512EVEX 17349 ISA_SET: AVX512F_SCALAR 17350 EXCEPTIONS: AVX512-E3 17351 REAL_OPCODE: Y 17352 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17353 PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 17354 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 17355 IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 17356 } 17357 17358 { 17359 ICLASS: VFNMSUB132SD 17360 CPL: 3 17361 CATEGORY: VFMA 17362 EXTENSION: AVX512EVEX 17363 ISA_SET: AVX512F_SCALAR 17364 EXCEPTIONS: AVX512-E3 17365 REAL_OPCODE: Y 17366 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 17367 PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 17368 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 17369 IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 17370 } 17371 17372 17373 # EMITTING VFNMSUB132SS (VFNMSUB132SS-128-1) 17374 { 17375 ICLASS: VFNMSUB132SS 17376 CPL: 3 17377 CATEGORY: VFMA 17378 EXTENSION: AVX512EVEX 17379 ISA_SET: AVX512F_SCALAR 17380 EXCEPTIONS: AVX512-E3 17381 REAL_OPCODE: Y 17382 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17383 PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 17384 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 17385 IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 17386 } 17387 17388 { 17389 ICLASS: VFNMSUB132SS 17390 CPL: 3 17391 CATEGORY: VFMA 17392 EXTENSION: AVX512EVEX 17393 ISA_SET: AVX512F_SCALAR 17394 EXCEPTIONS: AVX512-E3 17395 REAL_OPCODE: Y 17396 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17397 PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 17398 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 17399 IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 17400 } 17401 17402 { 17403 ICLASS: VFNMSUB132SS 17404 CPL: 3 17405 CATEGORY: VFMA 17406 EXTENSION: AVX512EVEX 17407 ISA_SET: AVX512F_SCALAR 17408 EXCEPTIONS: AVX512-E3 17409 REAL_OPCODE: Y 17410 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 17411 PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 17412 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 17413 IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 17414 } 17415 17416 17417 # EMITTING VFNMSUB213PD (VFNMSUB213PD-512-1) 17418 { 17419 ICLASS: VFNMSUB213PD 17420 CPL: 3 17421 CATEGORY: VFMA 17422 EXTENSION: AVX512EVEX 17423 ISA_SET: AVX512F_512 17424 EXCEPTIONS: AVX512-E2 17425 REAL_OPCODE: Y 17426 ATTRIBUTES: MASKOP_EVEX MXCSR 17427 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 17428 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 17429 IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 17430 } 17431 17432 { 17433 ICLASS: VFNMSUB213PD 17434 CPL: 3 17435 CATEGORY: VFMA 17436 EXTENSION: AVX512EVEX 17437 ISA_SET: AVX512F_512 17438 EXCEPTIONS: AVX512-E2 17439 REAL_OPCODE: Y 17440 ATTRIBUTES: MASKOP_EVEX MXCSR 17441 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 17442 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 17443 IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 17444 } 17445 17446 { 17447 ICLASS: VFNMSUB213PD 17448 CPL: 3 17449 CATEGORY: VFMA 17450 EXTENSION: AVX512EVEX 17451 ISA_SET: AVX512F_512 17452 EXCEPTIONS: AVX512-E2 17453 REAL_OPCODE: Y 17454 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 17455 PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 17456 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 17457 IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 17458 } 17459 17460 17461 # EMITTING VFNMSUB213PS (VFNMSUB213PS-512-1) 17462 { 17463 ICLASS: VFNMSUB213PS 17464 CPL: 3 17465 CATEGORY: VFMA 17466 EXTENSION: AVX512EVEX 17467 ISA_SET: AVX512F_512 17468 EXCEPTIONS: AVX512-E2 17469 REAL_OPCODE: Y 17470 ATTRIBUTES: MASKOP_EVEX MXCSR 17471 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 17472 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 17473 IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 17474 } 17475 17476 { 17477 ICLASS: VFNMSUB213PS 17478 CPL: 3 17479 CATEGORY: VFMA 17480 EXTENSION: AVX512EVEX 17481 ISA_SET: AVX512F_512 17482 EXCEPTIONS: AVX512-E2 17483 REAL_OPCODE: Y 17484 ATTRIBUTES: MASKOP_EVEX MXCSR 17485 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 17486 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 17487 IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 17488 } 17489 17490 { 17491 ICLASS: VFNMSUB213PS 17492 CPL: 3 17493 CATEGORY: VFMA 17494 EXTENSION: AVX512EVEX 17495 ISA_SET: AVX512F_512 17496 EXCEPTIONS: AVX512-E2 17497 REAL_OPCODE: Y 17498 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 17499 PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 17500 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 17501 IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 17502 } 17503 17504 17505 # EMITTING VFNMSUB213SD (VFNMSUB213SD-128-1) 17506 { 17507 ICLASS: VFNMSUB213SD 17508 CPL: 3 17509 CATEGORY: VFMA 17510 EXTENSION: AVX512EVEX 17511 ISA_SET: AVX512F_SCALAR 17512 EXCEPTIONS: AVX512-E3 17513 REAL_OPCODE: Y 17514 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17515 PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 17516 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 17517 IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 17518 } 17519 17520 { 17521 ICLASS: VFNMSUB213SD 17522 CPL: 3 17523 CATEGORY: VFMA 17524 EXTENSION: AVX512EVEX 17525 ISA_SET: AVX512F_SCALAR 17526 EXCEPTIONS: AVX512-E3 17527 REAL_OPCODE: Y 17528 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17529 PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 17530 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 17531 IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 17532 } 17533 17534 { 17535 ICLASS: VFNMSUB213SD 17536 CPL: 3 17537 CATEGORY: VFMA 17538 EXTENSION: AVX512EVEX 17539 ISA_SET: AVX512F_SCALAR 17540 EXCEPTIONS: AVX512-E3 17541 REAL_OPCODE: Y 17542 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 17543 PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 17544 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 17545 IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 17546 } 17547 17548 17549 # EMITTING VFNMSUB213SS (VFNMSUB213SS-128-1) 17550 { 17551 ICLASS: VFNMSUB213SS 17552 CPL: 3 17553 CATEGORY: VFMA 17554 EXTENSION: AVX512EVEX 17555 ISA_SET: AVX512F_SCALAR 17556 EXCEPTIONS: AVX512-E3 17557 REAL_OPCODE: Y 17558 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17559 PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 17560 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 17561 IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 17562 } 17563 17564 { 17565 ICLASS: VFNMSUB213SS 17566 CPL: 3 17567 CATEGORY: VFMA 17568 EXTENSION: AVX512EVEX 17569 ISA_SET: AVX512F_SCALAR 17570 EXCEPTIONS: AVX512-E3 17571 REAL_OPCODE: Y 17572 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17573 PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 17574 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 17575 IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 17576 } 17577 17578 { 17579 ICLASS: VFNMSUB213SS 17580 CPL: 3 17581 CATEGORY: VFMA 17582 EXTENSION: AVX512EVEX 17583 ISA_SET: AVX512F_SCALAR 17584 EXCEPTIONS: AVX512-E3 17585 REAL_OPCODE: Y 17586 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 17587 PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 17588 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 17589 IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 17590 } 17591 17592 17593 # EMITTING VFNMSUB231PD (VFNMSUB231PD-512-1) 17594 { 17595 ICLASS: VFNMSUB231PD 17596 CPL: 3 17597 CATEGORY: VFMA 17598 EXTENSION: AVX512EVEX 17599 ISA_SET: AVX512F_512 17600 EXCEPTIONS: AVX512-E2 17601 REAL_OPCODE: Y 17602 ATTRIBUTES: MASKOP_EVEX MXCSR 17603 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 17604 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 17605 IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 17606 } 17607 17608 { 17609 ICLASS: VFNMSUB231PD 17610 CPL: 3 17611 CATEGORY: VFMA 17612 EXTENSION: AVX512EVEX 17613 ISA_SET: AVX512F_512 17614 EXCEPTIONS: AVX512-E2 17615 REAL_OPCODE: Y 17616 ATTRIBUTES: MASKOP_EVEX MXCSR 17617 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 17618 OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 17619 IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 17620 } 17621 17622 { 17623 ICLASS: VFNMSUB231PD 17624 CPL: 3 17625 CATEGORY: VFMA 17626 EXTENSION: AVX512EVEX 17627 ISA_SET: AVX512F_512 17628 EXCEPTIONS: AVX512-E2 17629 REAL_OPCODE: Y 17630 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 17631 PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 17632 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 17633 IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 17634 } 17635 17636 17637 # EMITTING VFNMSUB231PS (VFNMSUB231PS-512-1) 17638 { 17639 ICLASS: VFNMSUB231PS 17640 CPL: 3 17641 CATEGORY: VFMA 17642 EXTENSION: AVX512EVEX 17643 ISA_SET: AVX512F_512 17644 EXCEPTIONS: AVX512-E2 17645 REAL_OPCODE: Y 17646 ATTRIBUTES: MASKOP_EVEX MXCSR 17647 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 17648 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 17649 IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 17650 } 17651 17652 { 17653 ICLASS: VFNMSUB231PS 17654 CPL: 3 17655 CATEGORY: VFMA 17656 EXTENSION: AVX512EVEX 17657 ISA_SET: AVX512F_512 17658 EXCEPTIONS: AVX512-E2 17659 REAL_OPCODE: Y 17660 ATTRIBUTES: MASKOP_EVEX MXCSR 17661 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 17662 OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 17663 IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 17664 } 17665 17666 { 17667 ICLASS: VFNMSUB231PS 17668 CPL: 3 17669 CATEGORY: VFMA 17670 EXTENSION: AVX512EVEX 17671 ISA_SET: AVX512F_512 17672 EXCEPTIONS: AVX512-E2 17673 REAL_OPCODE: Y 17674 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 17675 PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 17676 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 17677 IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 17678 } 17679 17680 17681 # EMITTING VFNMSUB231SD (VFNMSUB231SD-128-1) 17682 { 17683 ICLASS: VFNMSUB231SD 17684 CPL: 3 17685 CATEGORY: VFMA 17686 EXTENSION: AVX512EVEX 17687 ISA_SET: AVX512F_SCALAR 17688 EXCEPTIONS: AVX512-E3 17689 REAL_OPCODE: Y 17690 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17691 PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 17692 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 17693 IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 17694 } 17695 17696 { 17697 ICLASS: VFNMSUB231SD 17698 CPL: 3 17699 CATEGORY: VFMA 17700 EXTENSION: AVX512EVEX 17701 ISA_SET: AVX512F_SCALAR 17702 EXCEPTIONS: AVX512-E3 17703 REAL_OPCODE: Y 17704 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17705 PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 17706 OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 17707 IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 17708 } 17709 17710 { 17711 ICLASS: VFNMSUB231SD 17712 CPL: 3 17713 CATEGORY: VFMA 17714 EXTENSION: AVX512EVEX 17715 ISA_SET: AVX512F_SCALAR 17716 EXCEPTIONS: AVX512-E3 17717 REAL_OPCODE: Y 17718 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 17719 PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 17720 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 17721 IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 17722 } 17723 17724 17725 # EMITTING VFNMSUB231SS (VFNMSUB231SS-128-1) 17726 { 17727 ICLASS: VFNMSUB231SS 17728 CPL: 3 17729 CATEGORY: VFMA 17730 EXTENSION: AVX512EVEX 17731 ISA_SET: AVX512F_SCALAR 17732 EXCEPTIONS: AVX512-E3 17733 REAL_OPCODE: Y 17734 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17735 PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 17736 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 17737 IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 17738 } 17739 17740 { 17741 ICLASS: VFNMSUB231SS 17742 CPL: 3 17743 CATEGORY: VFMA 17744 EXTENSION: AVX512EVEX 17745 ISA_SET: AVX512F_SCALAR 17746 EXCEPTIONS: AVX512-E3 17747 REAL_OPCODE: Y 17748 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17749 PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 17750 OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 17751 IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 17752 } 17753 17754 { 17755 ICLASS: VFNMSUB231SS 17756 CPL: 3 17757 CATEGORY: VFMA 17758 EXTENSION: AVX512EVEX 17759 ISA_SET: AVX512F_SCALAR 17760 EXCEPTIONS: AVX512-E3 17761 REAL_OPCODE: Y 17762 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 17763 PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 17764 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 17765 IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 17766 } 17767 17768 17769 # EMITTING VGATHERDPD (VGATHERDPD-512-1) 17770 { 17771 ICLASS: VGATHERDPD 17772 CPL: 3 17773 CATEGORY: GATHER 17774 EXTENSION: AVX512EVEX 17775 ISA_SET: AVX512F_512 17776 EXCEPTIONS: AVX512-E12 17777 REAL_OPCODE: Y 17778 ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 17779 PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 17780 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 17781 IFORM: VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 17782 } 17783 17784 17785 # EMITTING VGATHERDPS (VGATHERDPS-512-1) 17786 { 17787 ICLASS: VGATHERDPS 17788 CPL: 3 17789 CATEGORY: GATHER 17790 EXTENSION: AVX512EVEX 17791 ISA_SET: AVX512F_512 17792 EXCEPTIONS: AVX512-E12 17793 REAL_OPCODE: Y 17794 ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 17795 PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 17796 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 17797 IFORM: VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 17798 } 17799 17800 17801 # EMITTING VGATHERQPD (VGATHERQPD-512-1) 17802 { 17803 ICLASS: VGATHERQPD 17804 CPL: 3 17805 CATEGORY: GATHER 17806 EXTENSION: AVX512EVEX 17807 ISA_SET: AVX512F_512 17808 EXCEPTIONS: AVX512-E12 17809 REAL_OPCODE: Y 17810 ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 17811 PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 17812 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 17813 IFORM: VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 17814 } 17815 17816 17817 # EMITTING VGATHERQPS (VGATHERQPS-512-1) 17818 { 17819 ICLASS: VGATHERQPS 17820 CPL: 3 17821 CATEGORY: GATHER 17822 EXTENSION: AVX512EVEX 17823 ISA_SET: AVX512F_512 17824 EXCEPTIONS: AVX512-E12 17825 REAL_OPCODE: Y 17826 ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 17827 PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 17828 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 17829 IFORM: VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 17830 } 17831 17832 17833 # EMITTING VGETEXPPD (VGETEXPPD-512-1) 17834 { 17835 ICLASS: VGETEXPPD 17836 CPL: 3 17837 CATEGORY: AVX512 17838 EXTENSION: AVX512EVEX 17839 ISA_SET: AVX512F_512 17840 EXCEPTIONS: AVX512-E2 17841 REAL_OPCODE: Y 17842 ATTRIBUTES: MASKOP_EVEX MXCSR 17843 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 17844 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 17845 IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 17846 } 17847 17848 { 17849 ICLASS: VGETEXPPD 17850 CPL: 3 17851 CATEGORY: AVX512 17852 EXTENSION: AVX512EVEX 17853 ISA_SET: AVX512F_512 17854 EXCEPTIONS: AVX512-E2 17855 REAL_OPCODE: Y 17856 ATTRIBUTES: MASKOP_EVEX MXCSR 17857 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 17858 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 17859 IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 17860 } 17861 17862 { 17863 ICLASS: VGETEXPPD 17864 CPL: 3 17865 CATEGORY: AVX512 17866 EXTENSION: AVX512EVEX 17867 ISA_SET: AVX512F_512 17868 EXCEPTIONS: AVX512-E2 17869 REAL_OPCODE: Y 17870 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 17871 PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 17872 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 17873 IFORM: VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 17874 } 17875 17876 17877 # EMITTING VGETEXPPS (VGETEXPPS-512-1) 17878 { 17879 ICLASS: VGETEXPPS 17880 CPL: 3 17881 CATEGORY: AVX512 17882 EXTENSION: AVX512EVEX 17883 ISA_SET: AVX512F_512 17884 EXCEPTIONS: AVX512-E2 17885 REAL_OPCODE: Y 17886 ATTRIBUTES: MASKOP_EVEX MXCSR 17887 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 17888 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 17889 IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 17890 } 17891 17892 { 17893 ICLASS: VGETEXPPS 17894 CPL: 3 17895 CATEGORY: AVX512 17896 EXTENSION: AVX512EVEX 17897 ISA_SET: AVX512F_512 17898 EXCEPTIONS: AVX512-E2 17899 REAL_OPCODE: Y 17900 ATTRIBUTES: MASKOP_EVEX MXCSR 17901 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 17902 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 17903 IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 17904 } 17905 17906 { 17907 ICLASS: VGETEXPPS 17908 CPL: 3 17909 CATEGORY: AVX512 17910 EXTENSION: AVX512EVEX 17911 ISA_SET: AVX512F_512 17912 EXCEPTIONS: AVX512-E2 17913 REAL_OPCODE: Y 17914 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 17915 PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 17916 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 17917 IFORM: VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 17918 } 17919 17920 17921 # EMITTING VGETEXPSD (VGETEXPSD-128-1) 17922 { 17923 ICLASS: VGETEXPSD 17924 CPL: 3 17925 CATEGORY: AVX512 17926 EXTENSION: AVX512EVEX 17927 ISA_SET: AVX512F_SCALAR 17928 EXCEPTIONS: AVX512-E3 17929 REAL_OPCODE: Y 17930 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17931 PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 17932 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 17933 IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 17934 } 17935 17936 { 17937 ICLASS: VGETEXPSD 17938 CPL: 3 17939 CATEGORY: AVX512 17940 EXTENSION: AVX512EVEX 17941 ISA_SET: AVX512F_SCALAR 17942 EXCEPTIONS: AVX512-E3 17943 REAL_OPCODE: Y 17944 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17945 PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 17946 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 17947 IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 17948 } 17949 17950 { 17951 ICLASS: VGETEXPSD 17952 CPL: 3 17953 CATEGORY: AVX512 17954 EXTENSION: AVX512EVEX 17955 ISA_SET: AVX512F_SCALAR 17956 EXCEPTIONS: AVX512-E3 17957 REAL_OPCODE: Y 17958 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 17959 PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 17960 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 17961 IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 17962 } 17963 17964 17965 # EMITTING VGETEXPSS (VGETEXPSS-128-1) 17966 { 17967 ICLASS: VGETEXPSS 17968 CPL: 3 17969 CATEGORY: AVX512 17970 EXTENSION: AVX512EVEX 17971 ISA_SET: AVX512F_SCALAR 17972 EXCEPTIONS: AVX512-E3 17973 REAL_OPCODE: Y 17974 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17975 PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 17976 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 17977 IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 17978 } 17979 17980 { 17981 ICLASS: VGETEXPSS 17982 CPL: 3 17983 CATEGORY: AVX512 17984 EXTENSION: AVX512EVEX 17985 ISA_SET: AVX512F_SCALAR 17986 EXCEPTIONS: AVX512-E3 17987 REAL_OPCODE: Y 17988 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 17989 PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 17990 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 17991 IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 17992 } 17993 17994 { 17995 ICLASS: VGETEXPSS 17996 CPL: 3 17997 CATEGORY: AVX512 17998 EXTENSION: AVX512EVEX 17999 ISA_SET: AVX512F_SCALAR 18000 EXCEPTIONS: AVX512-E3 18001 REAL_OPCODE: Y 18002 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 18003 PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 18004 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 18005 IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 18006 } 18007 18008 18009 # EMITTING VGETMANTPD (VGETMANTPD-512-1) 18010 { 18011 ICLASS: VGETMANTPD 18012 CPL: 3 18013 CATEGORY: AVX512 18014 EXTENSION: AVX512EVEX 18015 ISA_SET: AVX512F_512 18016 EXCEPTIONS: AVX512-E2 18017 REAL_OPCODE: Y 18018 ATTRIBUTES: MASKOP_EVEX MXCSR 18019 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 18020 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 18021 IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 18022 } 18023 18024 { 18025 ICLASS: VGETMANTPD 18026 CPL: 3 18027 CATEGORY: AVX512 18028 EXTENSION: AVX512EVEX 18029 ISA_SET: AVX512F_512 18030 EXCEPTIONS: AVX512-E2 18031 REAL_OPCODE: Y 18032 ATTRIBUTES: MASKOP_EVEX MXCSR 18033 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() 18034 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 18035 IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 18036 } 18037 18038 { 18039 ICLASS: VGETMANTPD 18040 CPL: 3 18041 CATEGORY: AVX512 18042 EXTENSION: AVX512EVEX 18043 ISA_SET: AVX512F_512 18044 EXCEPTIONS: AVX512-E2 18045 REAL_OPCODE: Y 18046 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 18047 PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 18048 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 18049 IFORM: VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 18050 } 18051 18052 18053 # EMITTING VGETMANTPS (VGETMANTPS-512-1) 18054 { 18055 ICLASS: VGETMANTPS 18056 CPL: 3 18057 CATEGORY: AVX512 18058 EXTENSION: AVX512EVEX 18059 ISA_SET: AVX512F_512 18060 EXCEPTIONS: AVX512-E2 18061 REAL_OPCODE: Y 18062 ATTRIBUTES: MASKOP_EVEX MXCSR 18063 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 18064 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 18065 IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 18066 } 18067 18068 { 18069 ICLASS: VGETMANTPS 18070 CPL: 3 18071 CATEGORY: AVX512 18072 EXTENSION: AVX512EVEX 18073 ISA_SET: AVX512F_512 18074 EXCEPTIONS: AVX512-E2 18075 REAL_OPCODE: Y 18076 ATTRIBUTES: MASKOP_EVEX MXCSR 18077 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() 18078 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 18079 IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 18080 } 18081 18082 { 18083 ICLASS: VGETMANTPS 18084 CPL: 3 18085 CATEGORY: AVX512 18086 EXTENSION: AVX512EVEX 18087 ISA_SET: AVX512F_512 18088 EXCEPTIONS: AVX512-E2 18089 REAL_OPCODE: Y 18090 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 18091 PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 18092 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 18093 IFORM: VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 18094 } 18095 18096 18097 # EMITTING VGETMANTSD (VGETMANTSD-128-1) 18098 { 18099 ICLASS: VGETMANTSD 18100 CPL: 3 18101 CATEGORY: AVX512 18102 EXTENSION: AVX512EVEX 18103 ISA_SET: AVX512F_SCALAR 18104 EXCEPTIONS: AVX512-E3 18105 REAL_OPCODE: Y 18106 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 18107 PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() 18108 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 18109 IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 18110 } 18111 18112 { 18113 ICLASS: VGETMANTSD 18114 CPL: 3 18115 CATEGORY: AVX512 18116 EXTENSION: AVX512EVEX 18117 ISA_SET: AVX512F_SCALAR 18118 EXCEPTIONS: AVX512-E3 18119 REAL_OPCODE: Y 18120 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 18121 PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() 18122 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 18123 IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 18124 } 18125 18126 { 18127 ICLASS: VGETMANTSD 18128 CPL: 3 18129 CATEGORY: AVX512 18130 EXTENSION: AVX512EVEX 18131 ISA_SET: AVX512F_SCALAR 18132 EXCEPTIONS: AVX512-E3 18133 REAL_OPCODE: Y 18134 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 18135 PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 18136 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 18137 IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 18138 } 18139 18140 18141 # EMITTING VGETMANTSS (VGETMANTSS-128-1) 18142 { 18143 ICLASS: VGETMANTSS 18144 CPL: 3 18145 CATEGORY: AVX512 18146 EXTENSION: AVX512EVEX 18147 ISA_SET: AVX512F_SCALAR 18148 EXCEPTIONS: AVX512-E3 18149 REAL_OPCODE: Y 18150 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 18151 PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() 18152 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 18153 IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 18154 } 18155 18156 { 18157 ICLASS: VGETMANTSS 18158 CPL: 3 18159 CATEGORY: AVX512 18160 EXTENSION: AVX512EVEX 18161 ISA_SET: AVX512F_SCALAR 18162 EXCEPTIONS: AVX512-E3 18163 REAL_OPCODE: Y 18164 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 18165 PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() 18166 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 18167 IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 18168 } 18169 18170 { 18171 ICLASS: VGETMANTSS 18172 CPL: 3 18173 CATEGORY: AVX512 18174 EXTENSION: AVX512EVEX 18175 ISA_SET: AVX512F_SCALAR 18176 EXCEPTIONS: AVX512-E3 18177 REAL_OPCODE: Y 18178 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 18179 PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 18180 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 18181 IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 18182 } 18183 18184 18185 # EMITTING VINSERTF32X4 (VINSERTF32X4-512-1) 18186 { 18187 ICLASS: VINSERTF32X4 18188 CPL: 3 18189 CATEGORY: AVX512 18190 EXTENSION: AVX512EVEX 18191 ISA_SET: AVX512F_512 18192 EXCEPTIONS: AVX512-E6NF 18193 REAL_OPCODE: Y 18194 ATTRIBUTES: MASKOP_EVEX 18195 PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 18196 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 18197 IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 18198 } 18199 18200 { 18201 ICLASS: VINSERTF32X4 18202 CPL: 3 18203 CATEGORY: AVX512 18204 EXTENSION: AVX512EVEX 18205 ISA_SET: AVX512F_512 18206 EXCEPTIONS: AVX512-E6NF 18207 REAL_OPCODE: Y 18208 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 18209 PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 18210 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:dq:f32 IMM0:r:b 18211 IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 18212 } 18213 18214 18215 # EMITTING VINSERTF64X4 (VINSERTF64X4-512-1) 18216 { 18217 ICLASS: VINSERTF64X4 18218 CPL: 3 18219 CATEGORY: AVX512 18220 EXTENSION: AVX512EVEX 18221 ISA_SET: AVX512F_512 18222 EXCEPTIONS: AVX512-E6NF 18223 REAL_OPCODE: Y 18224 ATTRIBUTES: MASKOP_EVEX 18225 PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 18226 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=YMM_B3():r:qq:f64 IMM0:r:b 18227 IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 18228 } 18229 18230 { 18231 ICLASS: VINSERTF64X4 18232 CPL: 3 18233 CATEGORY: AVX512 18234 EXTENSION: AVX512EVEX 18235 ISA_SET: AVX512F_512 18236 EXCEPTIONS: AVX512-E6NF 18237 REAL_OPCODE: Y 18238 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 18239 PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() 18240 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:qq:f64 IMM0:r:b 18241 IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 18242 } 18243 18244 18245 # EMITTING VINSERTI32X4 (VINSERTI32X4-512-1) 18246 { 18247 ICLASS: VINSERTI32X4 18248 CPL: 3 18249 CATEGORY: AVX512 18250 EXTENSION: AVX512EVEX 18251 ISA_SET: AVX512F_512 18252 EXCEPTIONS: AVX512-E6NF 18253 REAL_OPCODE: Y 18254 ATTRIBUTES: MASKOP_EVEX 18255 PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 18256 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 IMM0:r:b 18257 IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 18258 } 18259 18260 { 18261 ICLASS: VINSERTI32X4 18262 CPL: 3 18263 CATEGORY: AVX512 18264 EXTENSION: AVX512EVEX 18265 ISA_SET: AVX512F_512 18266 EXCEPTIONS: AVX512-E6NF 18267 REAL_OPCODE: Y 18268 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 18269 PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 18270 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 IMM0:r:b 18271 IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 18272 } 18273 18274 18275 # EMITTING VINSERTI64X4 (VINSERTI64X4-512-1) 18276 { 18277 ICLASS: VINSERTI64X4 18278 CPL: 3 18279 CATEGORY: AVX512 18280 EXTENSION: AVX512EVEX 18281 ISA_SET: AVX512F_512 18282 EXCEPTIONS: AVX512-E6NF 18283 REAL_OPCODE: Y 18284 ATTRIBUTES: MASKOP_EVEX 18285 PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 18286 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=YMM_B3():r:qq:u64 IMM0:r:b 18287 IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 18288 } 18289 18290 { 18291 ICLASS: VINSERTI64X4 18292 CPL: 3 18293 CATEGORY: AVX512 18294 EXTENSION: AVX512EVEX 18295 ISA_SET: AVX512F_512 18296 EXCEPTIONS: AVX512-E6NF 18297 REAL_OPCODE: Y 18298 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 18299 PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() 18300 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:qq:u64 IMM0:r:b 18301 IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 18302 } 18303 18304 18305 # EMITTING VINSERTPS (VINSERTPS-128-1) 18306 { 18307 ICLASS: VINSERTPS 18308 CPL: 3 18309 CATEGORY: AVX512 18310 EXTENSION: AVX512EVEX 18311 ISA_SET: AVX512F_128N 18312 EXCEPTIONS: AVX512-E9NF 18313 REAL_OPCODE: Y 18314 PATTERN: EVV 0x21 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8() 18315 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 IMM0:r:b 18316 IFORM: VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 18317 } 18318 18319 { 18320 ICLASS: VINSERTPS 18321 CPL: 3 18322 CATEGORY: AVX512 18323 EXTENSION: AVX512EVEX 18324 ISA_SET: AVX512F_128N 18325 EXCEPTIONS: AVX512-E9NF 18326 REAL_OPCODE: Y 18327 ATTRIBUTES: DISP8_TUPLE1 18328 PATTERN: EVV 0x21 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE1() 18329 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 18330 IFORM: VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 18331 } 18332 18333 18334 # EMITTING VMAXPD (VMAXPD-512-1) 18335 { 18336 ICLASS: VMAXPD 18337 CPL: 3 18338 CATEGORY: AVX512 18339 EXTENSION: AVX512EVEX 18340 ISA_SET: AVX512F_512 18341 EXCEPTIONS: AVX512-E2 18342 REAL_OPCODE: Y 18343 ATTRIBUTES: MASKOP_EVEX MXCSR 18344 PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 18345 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 18346 IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 18347 } 18348 18349 { 18350 ICLASS: VMAXPD 18351 CPL: 3 18352 CATEGORY: AVX512 18353 EXTENSION: AVX512EVEX 18354 ISA_SET: AVX512F_512 18355 EXCEPTIONS: AVX512-E2 18356 REAL_OPCODE: Y 18357 ATTRIBUTES: MASKOP_EVEX MXCSR 18358 PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 18359 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 18360 IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 18361 } 18362 18363 { 18364 ICLASS: VMAXPD 18365 CPL: 3 18366 CATEGORY: AVX512 18367 EXTENSION: AVX512EVEX 18368 ISA_SET: AVX512F_512 18369 EXCEPTIONS: AVX512-E2 18370 REAL_OPCODE: Y 18371 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 18372 PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 18373 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 18374 IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 18375 } 18376 18377 18378 # EMITTING VMAXPS (VMAXPS-512-1) 18379 { 18380 ICLASS: VMAXPS 18381 CPL: 3 18382 CATEGORY: AVX512 18383 EXTENSION: AVX512EVEX 18384 ISA_SET: AVX512F_512 18385 EXCEPTIONS: AVX512-E2 18386 REAL_OPCODE: Y 18387 ATTRIBUTES: MASKOP_EVEX MXCSR 18388 PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 18389 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 18390 IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 18391 } 18392 18393 { 18394 ICLASS: VMAXPS 18395 CPL: 3 18396 CATEGORY: AVX512 18397 EXTENSION: AVX512EVEX 18398 ISA_SET: AVX512F_512 18399 EXCEPTIONS: AVX512-E2 18400 REAL_OPCODE: Y 18401 ATTRIBUTES: MASKOP_EVEX MXCSR 18402 PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 18403 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 18404 IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 18405 } 18406 18407 { 18408 ICLASS: VMAXPS 18409 CPL: 3 18410 CATEGORY: AVX512 18411 EXTENSION: AVX512EVEX 18412 ISA_SET: AVX512F_512 18413 EXCEPTIONS: AVX512-E2 18414 REAL_OPCODE: Y 18415 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 18416 PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 18417 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 18418 IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 18419 } 18420 18421 18422 # EMITTING VMAXSD (VMAXSD-128-1) 18423 { 18424 ICLASS: VMAXSD 18425 CPL: 3 18426 CATEGORY: AVX512 18427 EXTENSION: AVX512EVEX 18428 ISA_SET: AVX512F_SCALAR 18429 EXCEPTIONS: AVX512-E3 18430 REAL_OPCODE: Y 18431 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 18432 PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 18433 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 18434 IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 18435 } 18436 18437 { 18438 ICLASS: VMAXSD 18439 CPL: 3 18440 CATEGORY: AVX512 18441 EXTENSION: AVX512EVEX 18442 ISA_SET: AVX512F_SCALAR 18443 EXCEPTIONS: AVX512-E3 18444 REAL_OPCODE: Y 18445 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 18446 PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 18447 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 18448 IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 18449 } 18450 18451 { 18452 ICLASS: VMAXSD 18453 CPL: 3 18454 CATEGORY: AVX512 18455 EXTENSION: AVX512EVEX 18456 ISA_SET: AVX512F_SCALAR 18457 EXCEPTIONS: AVX512-E3 18458 REAL_OPCODE: Y 18459 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 18460 PATTERN: EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 18461 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 18462 IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 18463 } 18464 18465 18466 # EMITTING VMAXSS (VMAXSS-128-1) 18467 { 18468 ICLASS: VMAXSS 18469 CPL: 3 18470 CATEGORY: AVX512 18471 EXTENSION: AVX512EVEX 18472 ISA_SET: AVX512F_SCALAR 18473 EXCEPTIONS: AVX512-E3 18474 REAL_OPCODE: Y 18475 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 18476 PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 18477 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 18478 IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 18479 } 18480 18481 { 18482 ICLASS: VMAXSS 18483 CPL: 3 18484 CATEGORY: AVX512 18485 EXTENSION: AVX512EVEX 18486 ISA_SET: AVX512F_SCALAR 18487 EXCEPTIONS: AVX512-E3 18488 REAL_OPCODE: Y 18489 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 18490 PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 18491 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 18492 IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 18493 } 18494 18495 { 18496 ICLASS: VMAXSS 18497 CPL: 3 18498 CATEGORY: AVX512 18499 EXTENSION: AVX512EVEX 18500 ISA_SET: AVX512F_SCALAR 18501 EXCEPTIONS: AVX512-E3 18502 REAL_OPCODE: Y 18503 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 18504 PATTERN: EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 18505 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 18506 IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 18507 } 18508 18509 18510 # EMITTING VMINPD (VMINPD-512-1) 18511 { 18512 ICLASS: VMINPD 18513 CPL: 3 18514 CATEGORY: AVX512 18515 EXTENSION: AVX512EVEX 18516 ISA_SET: AVX512F_512 18517 EXCEPTIONS: AVX512-E2 18518 REAL_OPCODE: Y 18519 ATTRIBUTES: MASKOP_EVEX MXCSR 18520 PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 18521 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 18522 IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 18523 } 18524 18525 { 18526 ICLASS: VMINPD 18527 CPL: 3 18528 CATEGORY: AVX512 18529 EXTENSION: AVX512EVEX 18530 ISA_SET: AVX512F_512 18531 EXCEPTIONS: AVX512-E2 18532 REAL_OPCODE: Y 18533 ATTRIBUTES: MASKOP_EVEX MXCSR 18534 PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 18535 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 18536 IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 18537 } 18538 18539 { 18540 ICLASS: VMINPD 18541 CPL: 3 18542 CATEGORY: AVX512 18543 EXTENSION: AVX512EVEX 18544 ISA_SET: AVX512F_512 18545 EXCEPTIONS: AVX512-E2 18546 REAL_OPCODE: Y 18547 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 18548 PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 18549 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 18550 IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 18551 } 18552 18553 18554 # EMITTING VMINPS (VMINPS-512-1) 18555 { 18556 ICLASS: VMINPS 18557 CPL: 3 18558 CATEGORY: AVX512 18559 EXTENSION: AVX512EVEX 18560 ISA_SET: AVX512F_512 18561 EXCEPTIONS: AVX512-E2 18562 REAL_OPCODE: Y 18563 ATTRIBUTES: MASKOP_EVEX MXCSR 18564 PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 18565 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 18566 IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 18567 } 18568 18569 { 18570 ICLASS: VMINPS 18571 CPL: 3 18572 CATEGORY: AVX512 18573 EXTENSION: AVX512EVEX 18574 ISA_SET: AVX512F_512 18575 EXCEPTIONS: AVX512-E2 18576 REAL_OPCODE: Y 18577 ATTRIBUTES: MASKOP_EVEX MXCSR 18578 PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 18579 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 18580 IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 18581 } 18582 18583 { 18584 ICLASS: VMINPS 18585 CPL: 3 18586 CATEGORY: AVX512 18587 EXTENSION: AVX512EVEX 18588 ISA_SET: AVX512F_512 18589 EXCEPTIONS: AVX512-E2 18590 REAL_OPCODE: Y 18591 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 18592 PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 18593 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 18594 IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 18595 } 18596 18597 18598 # EMITTING VMINSD (VMINSD-128-1) 18599 { 18600 ICLASS: VMINSD 18601 CPL: 3 18602 CATEGORY: AVX512 18603 EXTENSION: AVX512EVEX 18604 ISA_SET: AVX512F_SCALAR 18605 EXCEPTIONS: AVX512-E3 18606 REAL_OPCODE: Y 18607 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 18608 PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 18609 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 18610 IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 18611 } 18612 18613 { 18614 ICLASS: VMINSD 18615 CPL: 3 18616 CATEGORY: AVX512 18617 EXTENSION: AVX512EVEX 18618 ISA_SET: AVX512F_SCALAR 18619 EXCEPTIONS: AVX512-E3 18620 REAL_OPCODE: Y 18621 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 18622 PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 18623 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 18624 IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 18625 } 18626 18627 { 18628 ICLASS: VMINSD 18629 CPL: 3 18630 CATEGORY: AVX512 18631 EXTENSION: AVX512EVEX 18632 ISA_SET: AVX512F_SCALAR 18633 EXCEPTIONS: AVX512-E3 18634 REAL_OPCODE: Y 18635 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 18636 PATTERN: EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 18637 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 18638 IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 18639 } 18640 18641 18642 # EMITTING VMINSS (VMINSS-128-1) 18643 { 18644 ICLASS: VMINSS 18645 CPL: 3 18646 CATEGORY: AVX512 18647 EXTENSION: AVX512EVEX 18648 ISA_SET: AVX512F_SCALAR 18649 EXCEPTIONS: AVX512-E3 18650 REAL_OPCODE: Y 18651 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 18652 PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 18653 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 18654 IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 18655 } 18656 18657 { 18658 ICLASS: VMINSS 18659 CPL: 3 18660 CATEGORY: AVX512 18661 EXTENSION: AVX512EVEX 18662 ISA_SET: AVX512F_SCALAR 18663 EXCEPTIONS: AVX512-E3 18664 REAL_OPCODE: Y 18665 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 18666 PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 18667 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 18668 IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 18669 } 18670 18671 { 18672 ICLASS: VMINSS 18673 CPL: 3 18674 CATEGORY: AVX512 18675 EXTENSION: AVX512EVEX 18676 ISA_SET: AVX512F_SCALAR 18677 EXCEPTIONS: AVX512-E3 18678 REAL_OPCODE: Y 18679 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 18680 PATTERN: EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 18681 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 18682 IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 18683 } 18684 18685 18686 # EMITTING VMOVAPD (VMOVAPD-512-1) 18687 { 18688 ICLASS: VMOVAPD 18689 CPL: 3 18690 CATEGORY: DATAXFER 18691 EXTENSION: AVX512EVEX 18692 ISA_SET: AVX512F_512 18693 EXCEPTIONS: AVX512-E1 18694 REAL_OPCODE: Y 18695 ATTRIBUTES: MASKOP_EVEX 18696 PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 18697 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 18698 IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 18699 } 18700 18701 { 18702 ICLASS: VMOVAPD 18703 CPL: 3 18704 CATEGORY: DATAXFER 18705 EXTENSION: AVX512EVEX 18706 ISA_SET: AVX512F_512 18707 EXCEPTIONS: AVX512-E1 18708 REAL_OPCODE: Y 18709 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 18710 PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 18711 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 18712 IFORM: VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 18713 } 18714 18715 18716 # EMITTING VMOVAPD (VMOVAPD-512-2) 18717 { 18718 ICLASS: VMOVAPD 18719 CPL: 3 18720 CATEGORY: DATAXFER 18721 EXTENSION: AVX512EVEX 18722 ISA_SET: AVX512F_512 18723 EXCEPTIONS: AVX512-E1 18724 REAL_OPCODE: Y 18725 ATTRIBUTES: MASKOP_EVEX 18726 PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 18727 OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 18728 IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 18729 } 18730 18731 18732 # EMITTING VMOVAPD (VMOVAPD-512-3) 18733 { 18734 ICLASS: VMOVAPD 18735 CPL: 3 18736 CATEGORY: DATAXFER 18737 EXTENSION: AVX512EVEX 18738 ISA_SET: AVX512F_512 18739 EXCEPTIONS: AVX512-E1 18740 REAL_OPCODE: Y 18741 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 18742 PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 18743 OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 18744 IFORM: VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 18745 } 18746 18747 18748 # EMITTING VMOVAPS (VMOVAPS-512-1) 18749 { 18750 ICLASS: VMOVAPS 18751 CPL: 3 18752 CATEGORY: DATAXFER 18753 EXTENSION: AVX512EVEX 18754 ISA_SET: AVX512F_512 18755 EXCEPTIONS: AVX512-E1 18756 REAL_OPCODE: Y 18757 ATTRIBUTES: MASKOP_EVEX 18758 PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 18759 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 18760 IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 18761 } 18762 18763 { 18764 ICLASS: VMOVAPS 18765 CPL: 3 18766 CATEGORY: DATAXFER 18767 EXTENSION: AVX512EVEX 18768 ISA_SET: AVX512F_512 18769 EXCEPTIONS: AVX512-E1 18770 REAL_OPCODE: Y 18771 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 18772 PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 18773 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 18774 IFORM: VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 18775 } 18776 18777 18778 # EMITTING VMOVAPS (VMOVAPS-512-2) 18779 { 18780 ICLASS: VMOVAPS 18781 CPL: 3 18782 CATEGORY: DATAXFER 18783 EXTENSION: AVX512EVEX 18784 ISA_SET: AVX512F_512 18785 EXCEPTIONS: AVX512-E1 18786 REAL_OPCODE: Y 18787 ATTRIBUTES: MASKOP_EVEX 18788 PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 18789 OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 18790 IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 18791 } 18792 18793 18794 # EMITTING VMOVAPS (VMOVAPS-512-3) 18795 { 18796 ICLASS: VMOVAPS 18797 CPL: 3 18798 CATEGORY: DATAXFER 18799 EXTENSION: AVX512EVEX 18800 ISA_SET: AVX512F_512 18801 EXCEPTIONS: AVX512-E1 18802 REAL_OPCODE: Y 18803 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 18804 PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 18805 OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 18806 IFORM: VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 18807 } 18808 18809 18810 # EMITTING VMOVD (VMOVD-128-1) 18811 { 18812 ICLASS: VMOVD 18813 CPL: 3 18814 CATEGORY: DATAXFER 18815 EXTENSION: AVX512EVEX 18816 ISA_SET: AVX512F_128N 18817 EXCEPTIONS: AVX512-E9NF 18818 REAL_OPCODE: Y 18819 PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 18820 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32 18821 IFORM: VMOVD_XMMu32_GPR32u32_AVX512 18822 PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 18823 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32 18824 IFORM: VMOVD_XMMu32_GPR32u32_AVX512 18825 } 18826 18827 { 18828 ICLASS: VMOVD 18829 CPL: 3 18830 CATEGORY: DATAXFER 18831 EXTENSION: AVX512EVEX 18832 ISA_SET: AVX512F_128N 18833 EXCEPTIONS: AVX512-E9NF 18834 REAL_OPCODE: Y 18835 ATTRIBUTES: DISP8_GPR_READER 18836 PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() 18837 OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32 18838 IFORM: VMOVD_XMMu32_MEMu32_AVX512 18839 PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() 18840 OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32 18841 IFORM: VMOVD_XMMu32_MEMu32_AVX512 18842 } 18843 18844 18845 # EMITTING VMOVD (VMOVD-128-2) 18846 { 18847 ICLASS: VMOVD 18848 CPL: 3 18849 CATEGORY: DATAXFER 18850 EXTENSION: AVX512EVEX 18851 ISA_SET: AVX512F_128N 18852 EXCEPTIONS: AVX512-E9NF 18853 REAL_OPCODE: Y 18854 PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 18855 OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 18856 IFORM: VMOVD_GPR32u32_XMMu32_AVX512 18857 PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 18858 OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 18859 IFORM: VMOVD_GPR32u32_XMMu32_AVX512 18860 } 18861 18862 { 18863 ICLASS: VMOVD 18864 CPL: 3 18865 CATEGORY: DATAXFER 18866 EXTENSION: AVX512EVEX 18867 ISA_SET: AVX512F_128N 18868 EXCEPTIONS: AVX512-E9NF 18869 REAL_OPCODE: Y 18870 ATTRIBUTES: DISP8_GPR_WRITER_STORE 18871 PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() 18872 OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 18873 IFORM: VMOVD_MEMu32_XMMu32_AVX512 18874 PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() 18875 OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 18876 IFORM: VMOVD_MEMu32_XMMu32_AVX512 18877 } 18878 18879 18880 # EMITTING VMOVDDUP (VMOVDDUP-512-1) 18881 { 18882 ICLASS: VMOVDDUP 18883 CPL: 3 18884 CATEGORY: DATAXFER 18885 EXTENSION: AVX512EVEX 18886 ISA_SET: AVX512F_512 18887 EXCEPTIONS: AVX512-E5NF 18888 REAL_OPCODE: Y 18889 ATTRIBUTES: MASKOP_EVEX 18890 PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 18891 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 18892 IFORM: VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 18893 } 18894 18895 { 18896 ICLASS: VMOVDDUP 18897 CPL: 3 18898 CATEGORY: DATAXFER 18899 EXTENSION: AVX512EVEX 18900 ISA_SET: AVX512F_512 18901 EXCEPTIONS: AVX512-E5NF 18902 REAL_OPCODE: Y 18903 ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP 18904 PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() 18905 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 18906 IFORM: VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 18907 } 18908 18909 18910 # EMITTING VMOVDQA32 (VMOVDQA32-512-1) 18911 { 18912 ICLASS: VMOVDQA32 18913 CPL: 3 18914 CATEGORY: DATAXFER 18915 EXTENSION: AVX512EVEX 18916 ISA_SET: AVX512F_512 18917 EXCEPTIONS: AVX512-E1 18918 REAL_OPCODE: Y 18919 ATTRIBUTES: MASKOP_EVEX 18920 PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 18921 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 18922 IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 18923 } 18924 18925 { 18926 ICLASS: VMOVDQA32 18927 CPL: 3 18928 CATEGORY: DATAXFER 18929 EXTENSION: AVX512EVEX 18930 ISA_SET: AVX512F_512 18931 EXCEPTIONS: AVX512-E1 18932 REAL_OPCODE: Y 18933 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 18934 PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 18935 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 18936 IFORM: VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 18937 } 18938 18939 18940 # EMITTING VMOVDQA32 (VMOVDQA32-512-2) 18941 { 18942 ICLASS: VMOVDQA32 18943 CPL: 3 18944 CATEGORY: DATAXFER 18945 EXTENSION: AVX512EVEX 18946 ISA_SET: AVX512F_512 18947 EXCEPTIONS: AVX512-E1 18948 REAL_OPCODE: Y 18949 ATTRIBUTES: MASKOP_EVEX 18950 PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 18951 OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 18952 IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 18953 } 18954 18955 18956 # EMITTING VMOVDQA32 (VMOVDQA32-512-3) 18957 { 18958 ICLASS: VMOVDQA32 18959 CPL: 3 18960 CATEGORY: DATAXFER 18961 EXTENSION: AVX512EVEX 18962 ISA_SET: AVX512F_512 18963 EXCEPTIONS: AVX512-E1 18964 REAL_OPCODE: Y 18965 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 18966 PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 18967 OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 18968 IFORM: VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 18969 } 18970 18971 18972 # EMITTING VMOVDQA64 (VMOVDQA64-512-1) 18973 { 18974 ICLASS: VMOVDQA64 18975 CPL: 3 18976 CATEGORY: DATAXFER 18977 EXTENSION: AVX512EVEX 18978 ISA_SET: AVX512F_512 18979 EXCEPTIONS: AVX512-E1 18980 REAL_OPCODE: Y 18981 ATTRIBUTES: MASKOP_EVEX 18982 PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 18983 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 18984 IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 18985 } 18986 18987 { 18988 ICLASS: VMOVDQA64 18989 CPL: 3 18990 CATEGORY: DATAXFER 18991 EXTENSION: AVX512EVEX 18992 ISA_SET: AVX512F_512 18993 EXCEPTIONS: AVX512-E1 18994 REAL_OPCODE: Y 18995 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 18996 PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 18997 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 18998 IFORM: VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 18999 } 19000 19001 19002 # EMITTING VMOVDQA64 (VMOVDQA64-512-2) 19003 { 19004 ICLASS: VMOVDQA64 19005 CPL: 3 19006 CATEGORY: DATAXFER 19007 EXTENSION: AVX512EVEX 19008 ISA_SET: AVX512F_512 19009 EXCEPTIONS: AVX512-E1 19010 REAL_OPCODE: Y 19011 ATTRIBUTES: MASKOP_EVEX 19012 PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 19013 OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 19014 IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 19015 } 19016 19017 19018 # EMITTING VMOVDQA64 (VMOVDQA64-512-3) 19019 { 19020 ICLASS: VMOVDQA64 19021 CPL: 3 19022 CATEGORY: DATAXFER 19023 EXTENSION: AVX512EVEX 19024 ISA_SET: AVX512F_512 19025 EXCEPTIONS: AVX512-E1 19026 REAL_OPCODE: Y 19027 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 19028 PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 19029 OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 19030 IFORM: VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 19031 } 19032 19033 19034 # EMITTING VMOVDQU32 (VMOVDQU32-512-1) 19035 { 19036 ICLASS: VMOVDQU32 19037 CPL: 3 19038 CATEGORY: DATAXFER 19039 EXTENSION: AVX512EVEX 19040 ISA_SET: AVX512F_512 19041 EXCEPTIONS: AVX512-E4 19042 REAL_OPCODE: Y 19043 ATTRIBUTES: MASKOP_EVEX 19044 PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 19045 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 19046 IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 19047 } 19048 19049 { 19050 ICLASS: VMOVDQU32 19051 CPL: 3 19052 CATEGORY: DATAXFER 19053 EXTENSION: AVX512EVEX 19054 ISA_SET: AVX512F_512 19055 EXCEPTIONS: AVX512-E4 19056 REAL_OPCODE: Y 19057 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 19058 PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 19059 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 19060 IFORM: VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 19061 } 19062 19063 19064 # EMITTING VMOVDQU32 (VMOVDQU32-512-2) 19065 { 19066 ICLASS: VMOVDQU32 19067 CPL: 3 19068 CATEGORY: DATAXFER 19069 EXTENSION: AVX512EVEX 19070 ISA_SET: AVX512F_512 19071 EXCEPTIONS: AVX512-E4 19072 REAL_OPCODE: Y 19073 ATTRIBUTES: MASKOP_EVEX 19074 PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 19075 OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 19076 IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 19077 } 19078 19079 19080 # EMITTING VMOVDQU32 (VMOVDQU32-512-3) 19081 { 19082 ICLASS: VMOVDQU32 19083 CPL: 3 19084 CATEGORY: DATAXFER 19085 EXTENSION: AVX512EVEX 19086 ISA_SET: AVX512F_512 19087 EXCEPTIONS: AVX512-E4 19088 REAL_OPCODE: Y 19089 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 19090 PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 19091 OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 19092 IFORM: VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 19093 } 19094 19095 19096 # EMITTING VMOVDQU64 (VMOVDQU64-512-1) 19097 { 19098 ICLASS: VMOVDQU64 19099 CPL: 3 19100 CATEGORY: DATAXFER 19101 EXTENSION: AVX512EVEX 19102 ISA_SET: AVX512F_512 19103 EXCEPTIONS: AVX512-E4 19104 REAL_OPCODE: Y 19105 ATTRIBUTES: MASKOP_EVEX 19106 PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 19107 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 19108 IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 19109 } 19110 19111 { 19112 ICLASS: VMOVDQU64 19113 CPL: 3 19114 CATEGORY: DATAXFER 19115 EXTENSION: AVX512EVEX 19116 ISA_SET: AVX512F_512 19117 EXCEPTIONS: AVX512-E4 19118 REAL_OPCODE: Y 19119 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 19120 PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 19121 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 19122 IFORM: VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 19123 } 19124 19125 19126 # EMITTING VMOVDQU64 (VMOVDQU64-512-2) 19127 { 19128 ICLASS: VMOVDQU64 19129 CPL: 3 19130 CATEGORY: DATAXFER 19131 EXTENSION: AVX512EVEX 19132 ISA_SET: AVX512F_512 19133 EXCEPTIONS: AVX512-E4 19134 REAL_OPCODE: Y 19135 ATTRIBUTES: MASKOP_EVEX 19136 PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 19137 OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 19138 IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 19139 } 19140 19141 19142 # EMITTING VMOVDQU64 (VMOVDQU64-512-3) 19143 { 19144 ICLASS: VMOVDQU64 19145 CPL: 3 19146 CATEGORY: DATAXFER 19147 EXTENSION: AVX512EVEX 19148 ISA_SET: AVX512F_512 19149 EXCEPTIONS: AVX512-E4 19150 REAL_OPCODE: Y 19151 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 19152 PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 19153 OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 19154 IFORM: VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 19155 } 19156 19157 19158 # EMITTING VMOVHLPS (VMOVHLPS-128-1) 19159 { 19160 ICLASS: VMOVHLPS 19161 CPL: 3 19162 CATEGORY: DATAXFER 19163 EXTENSION: AVX512EVEX 19164 ISA_SET: AVX512F_128N 19165 EXCEPTIONS: AVX512-E7NM128 19166 REAL_OPCODE: Y 19167 PATTERN: EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 19168 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 19169 IFORM: VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 19170 } 19171 19172 19173 # EMITTING VMOVHPD (VMOVHPD-128-1) 19174 { 19175 ICLASS: VMOVHPD 19176 CPL: 3 19177 CATEGORY: DATAXFER 19178 EXTENSION: AVX512EVEX 19179 ISA_SET: AVX512F_128N 19180 EXCEPTIONS: AVX512-E9NF 19181 REAL_OPCODE: Y 19182 ATTRIBUTES: DISP8_SCALAR 19183 PATTERN: EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 19184 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:q:f64 MEM0:r:q:f64 19185 IFORM: VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 19186 } 19187 19188 19189 # EMITTING VMOVHPD (VMOVHPD-128-2) 19190 { 19191 ICLASS: VMOVHPD 19192 CPL: 3 19193 CATEGORY: DATAXFER 19194 EXTENSION: AVX512EVEX 19195 ISA_SET: AVX512F_128N 19196 EXCEPTIONS: AVX512-E9NF 19197 REAL_OPCODE: Y 19198 ATTRIBUTES: DISP8_SCALAR 19199 PATTERN: EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 19200 OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:dq:f64 19201 IFORM: VMOVHPD_MEMf64_XMMf64_AVX512 19202 } 19203 19204 19205 # EMITTING VMOVHPS (VMOVHPS-128-1) 19206 { 19207 ICLASS: VMOVHPS 19208 CPL: 3 19209 CATEGORY: DATAXFER 19210 EXTENSION: AVX512EVEX 19211 ISA_SET: AVX512F_128N 19212 EXCEPTIONS: AVX512-E9NF 19213 REAL_OPCODE: Y 19214 ATTRIBUTES: DISP8_TUPLE2 19215 PATTERN: EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() 19216 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 MEM0:r:q:f32 19217 IFORM: VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 19218 } 19219 19220 19221 # EMITTING VMOVHPS (VMOVHPS-128-2) 19222 { 19223 ICLASS: VMOVHPS 19224 CPL: 3 19225 CATEGORY: DATAXFER 19226 EXTENSION: AVX512EVEX 19227 ISA_SET: AVX512F_128N 19228 EXCEPTIONS: AVX512-E9NF 19229 REAL_OPCODE: Y 19230 ATTRIBUTES: DISP8_TUPLE2 19231 PATTERN: EVV 0x17 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() 19232 OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:dq:f32 19233 IFORM: VMOVHPS_MEMf32_XMMf32_AVX512 19234 } 19235 19236 19237 # EMITTING VMOVLHPS (VMOVLHPS-128-1) 19238 { 19239 ICLASS: VMOVLHPS 19240 CPL: 3 19241 CATEGORY: DATAXFER 19242 EXTENSION: AVX512EVEX 19243 ISA_SET: AVX512F_128N 19244 EXCEPTIONS: AVX512-E7NM128 19245 REAL_OPCODE: Y 19246 PATTERN: EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 19247 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 REG2=XMM_B3():r:q:f32 19248 IFORM: VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 19249 } 19250 19251 19252 # EMITTING VMOVLPD (VMOVLPD-128-1) 19253 { 19254 ICLASS: VMOVLPD 19255 CPL: 3 19256 CATEGORY: DATAXFER 19257 EXTENSION: AVX512EVEX 19258 ISA_SET: AVX512F_128N 19259 EXCEPTIONS: AVX512-E9NF 19260 REAL_OPCODE: Y 19261 ATTRIBUTES: DISP8_SCALAR 19262 PATTERN: EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 19263 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:f64 19264 IFORM: VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 19265 } 19266 19267 19268 # EMITTING VMOVLPD (VMOVLPD-128-2) 19269 { 19270 ICLASS: VMOVLPD 19271 CPL: 3 19272 CATEGORY: DATAXFER 19273 EXTENSION: AVX512EVEX 19274 ISA_SET: AVX512F_128N 19275 EXCEPTIONS: AVX512-E9NF 19276 REAL_OPCODE: Y 19277 ATTRIBUTES: DISP8_SCALAR 19278 PATTERN: EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 19279 OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:q:f64 19280 IFORM: VMOVLPD_MEMf64_XMMf64_AVX512 19281 } 19282 19283 19284 # EMITTING VMOVLPS (VMOVLPS-128-1) 19285 { 19286 ICLASS: VMOVLPS 19287 CPL: 3 19288 CATEGORY: DATAXFER 19289 EXTENSION: AVX512EVEX 19290 ISA_SET: AVX512F_128N 19291 EXCEPTIONS: AVX512-E9NF 19292 REAL_OPCODE: Y 19293 ATTRIBUTES: DISP8_TUPLE2 19294 PATTERN: EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() 19295 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:f32 19296 IFORM: VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 19297 } 19298 19299 19300 # EMITTING VMOVLPS (VMOVLPS-128-2) 19301 { 19302 ICLASS: VMOVLPS 19303 CPL: 3 19304 CATEGORY: DATAXFER 19305 EXTENSION: AVX512EVEX 19306 ISA_SET: AVX512F_128N 19307 EXCEPTIONS: AVX512-E9NF 19308 REAL_OPCODE: Y 19309 ATTRIBUTES: DISP8_TUPLE2 19310 PATTERN: EVV 0x13 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() 19311 OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:q:f32 19312 IFORM: VMOVLPS_MEMf32_XMMf32_AVX512 19313 } 19314 19315 19316 # EMITTING VMOVNTDQ (VMOVNTDQ-512-1) 19317 { 19318 ICLASS: VMOVNTDQ 19319 CPL: 3 19320 CATEGORY: DATAXFER 19321 EXTENSION: AVX512EVEX 19322 ISA_SET: AVX512F_512 19323 EXCEPTIONS: AVX512-E1NF 19324 REAL_OPCODE: Y 19325 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 19326 PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 19327 OPERANDS: MEM0:w:zd:u32 REG0=ZMM_R3():r:zu32 19328 IFORM: VMOVNTDQ_MEMu32_ZMMu32_AVX512 19329 } 19330 19331 19332 # EMITTING VMOVNTDQA (VMOVNTDQA-512-1) 19333 { 19334 ICLASS: VMOVNTDQA 19335 CPL: 3 19336 CATEGORY: DATAXFER 19337 EXTENSION: AVX512EVEX 19338 ISA_SET: AVX512F_512 19339 EXCEPTIONS: AVX512-E1NF 19340 REAL_OPCODE: Y 19341 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 19342 PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 19343 OPERANDS: REG0=ZMM_R3():w:zu32 MEM0:r:zd:u32 19344 IFORM: VMOVNTDQA_ZMMu32_MEMu32_AVX512 19345 } 19346 19347 19348 # EMITTING VMOVNTPD (VMOVNTPD-512-1) 19349 { 19350 ICLASS: VMOVNTPD 19351 CPL: 3 19352 CATEGORY: DATAXFER 19353 EXTENSION: AVX512EVEX 19354 ISA_SET: AVX512F_512 19355 EXCEPTIONS: AVX512-E1NF 19356 REAL_OPCODE: Y 19357 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 19358 PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() 19359 OPERANDS: MEM0:w:zd:f64 REG0=ZMM_R3():r:zf64 19360 IFORM: VMOVNTPD_MEMf64_ZMMf64_AVX512 19361 } 19362 19363 19364 # EMITTING VMOVNTPS (VMOVNTPS-512-1) 19365 { 19366 ICLASS: VMOVNTPS 19367 CPL: 3 19368 CATEGORY: DATAXFER 19369 EXTENSION: AVX512EVEX 19370 ISA_SET: AVX512F_512 19371 EXCEPTIONS: AVX512-E1NF 19372 REAL_OPCODE: Y 19373 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 19374 PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 19375 OPERANDS: MEM0:w:zd:f32 REG0=ZMM_R3():r:zf32 19376 IFORM: VMOVNTPS_MEMf32_ZMMf32_AVX512 19377 } 19378 19379 19380 # EMITTING VMOVQ (VMOVQ-128-1) 19381 { 19382 ICLASS: VMOVQ 19383 CPL: 3 19384 CATEGORY: DATAXFER 19385 EXTENSION: AVX512EVEX 19386 ISA_SET: AVX512F_128N 19387 EXCEPTIONS: AVX512-E9NF 19388 REAL_OPCODE: Y 19389 PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 19390 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=GPR64_B():r:q:u64 19391 IFORM: VMOVQ_XMMu64_GPR64u64_AVX512 19392 } 19393 19394 { 19395 ICLASS: VMOVQ 19396 CPL: 3 19397 CATEGORY: DATAXFER 19398 EXTENSION: AVX512EVEX 19399 ISA_SET: AVX512F_128N 19400 EXCEPTIONS: AVX512-E9NF 19401 REAL_OPCODE: Y 19402 ATTRIBUTES: DISP8_GPR_READER 19403 PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() 19404 OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 19405 IFORM: VMOVQ_XMMu64_MEMu64_AVX512 19406 } 19407 19408 19409 # EMITTING VMOVQ (VMOVQ-128-2) 19410 { 19411 ICLASS: VMOVQ 19412 CPL: 3 19413 CATEGORY: DATAXFER 19414 EXTENSION: AVX512EVEX 19415 ISA_SET: AVX512F_128N 19416 EXCEPTIONS: AVX512-E9NF 19417 REAL_OPCODE: Y 19418 PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 19419 OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 19420 IFORM: VMOVQ_GPR64u64_XMMu64_AVX512 19421 } 19422 19423 { 19424 ICLASS: VMOVQ 19425 CPL: 3 19426 CATEGORY: DATAXFER 19427 EXTENSION: AVX512EVEX 19428 ISA_SET: AVX512F_128N 19429 EXCEPTIONS: AVX512-E9NF 19430 REAL_OPCODE: Y 19431 ATTRIBUTES: DISP8_GPR_WRITER_STORE 19432 PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() 19433 OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 19434 IFORM: VMOVQ_MEMu64_XMMu64_AVX512 19435 } 19436 19437 19438 # EMITTING VMOVQ (VMOVQ-128-3) 19439 { 19440 ICLASS: VMOVQ 19441 CPL: 3 19442 CATEGORY: DATAXFER 19443 EXTENSION: AVX512EVEX 19444 ISA_SET: AVX512F_128N 19445 EXCEPTIONS: AVX512-E9NF 19446 REAL_OPCODE: Y 19447 PATTERN: EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 19448 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_B3():r:dq:u64 19449 IFORM: VMOVQ_XMMu64_XMMu64_AVX512 19450 } 19451 19452 { 19453 ICLASS: VMOVQ 19454 CPL: 3 19455 CATEGORY: DATAXFER 19456 EXTENSION: AVX512EVEX 19457 ISA_SET: AVX512F_128N 19458 EXCEPTIONS: AVX512-E9NF 19459 REAL_OPCODE: Y 19460 ATTRIBUTES: DISP8_SCALAR 19461 PATTERN: EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 19462 OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 19463 IFORM: VMOVQ_XMMu64_MEMu64_AVX512 19464 } 19465 19466 19467 # EMITTING VMOVQ (VMOVQ-128-4) 19468 { 19469 ICLASS: VMOVQ 19470 CPL: 3 19471 CATEGORY: DATAXFER 19472 EXTENSION: AVX512EVEX 19473 ISA_SET: AVX512F_128N 19474 EXCEPTIONS: AVX512-E9NF 19475 REAL_OPCODE: Y 19476 PATTERN: EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 19477 OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=XMM_R3():r:dq:u64 19478 IFORM: VMOVQ_XMMu64_XMMu64_AVX512 19479 } 19480 19481 { 19482 ICLASS: VMOVQ 19483 CPL: 3 19484 CATEGORY: DATAXFER 19485 EXTENSION: AVX512EVEX 19486 ISA_SET: AVX512F_128N 19487 EXCEPTIONS: AVX512-E9NF 19488 REAL_OPCODE: Y 19489 ATTRIBUTES: DISP8_SCALAR 19490 PATTERN: EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 19491 OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 19492 IFORM: VMOVQ_MEMu64_XMMu64_AVX512 19493 } 19494 19495 19496 # EMITTING VMOVSD (VMOVSD-128-1) 19497 { 19498 ICLASS: VMOVSD 19499 CPL: 3 19500 CATEGORY: DATAXFER 19501 EXTENSION: AVX512EVEX 19502 ISA_SET: AVX512F_SCALAR 19503 EXCEPTIONS: AVX512-E5 19504 REAL_OPCODE: Y 19505 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR 19506 PATTERN: EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ESIZE_64_BITS() NELEM_SCALAR() 19507 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 19508 IFORM: VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 19509 } 19510 19511 19512 # EMITTING VMOVSD (VMOVSD-128-2) 19513 { 19514 ICLASS: VMOVSD 19515 CPL: 3 19516 CATEGORY: DATAXFER 19517 EXTENSION: AVX512EVEX 19518 ISA_SET: AVX512F_SCALAR 19519 EXCEPTIONS: AVX512-E5 19520 REAL_OPCODE: Y 19521 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR 19522 PATTERN: EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_SCALAR() 19523 OPERANDS: MEM0:w:q:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 19524 IFORM: VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 19525 } 19526 19527 19528 # EMITTING VMOVSD (VMOVSD-128-3) 19529 { 19530 ICLASS: VMOVSD 19531 CPL: 3 19532 CATEGORY: DATAXFER 19533 EXTENSION: AVX512EVEX 19534 ISA_SET: AVX512F_SCALAR 19535 EXCEPTIONS: AVX512-E5 19536 REAL_OPCODE: Y 19537 ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR 19538 PATTERN: EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 19539 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 19540 IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 19541 } 19542 19543 19544 # EMITTING VMOVSD (VMOVSD-128-4) 19545 { 19546 ICLASS: VMOVSD 19547 CPL: 3 19548 CATEGORY: DATAXFER 19549 EXTENSION: AVX512EVEX 19550 ISA_SET: AVX512F_SCALAR 19551 EXCEPTIONS: AVX512-E5 19552 REAL_OPCODE: Y 19553 ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR 19554 PATTERN: EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 19555 OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_R3():r:dq:f64 19556 IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 19557 } 19558 19559 19560 # EMITTING VMOVSHDUP (VMOVSHDUP-512-1) 19561 { 19562 ICLASS: VMOVSHDUP 19563 CPL: 3 19564 CATEGORY: DATAXFER 19565 EXTENSION: AVX512EVEX 19566 ISA_SET: AVX512F_512 19567 EXCEPTIONS: AVX512-E4NF 19568 REAL_OPCODE: Y 19569 ATTRIBUTES: MASKOP_EVEX 19570 PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 19571 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 19572 IFORM: VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 19573 } 19574 19575 { 19576 ICLASS: VMOVSHDUP 19577 CPL: 3 19578 CATEGORY: DATAXFER 19579 EXTENSION: AVX512EVEX 19580 ISA_SET: AVX512F_512 19581 EXCEPTIONS: AVX512-E4NF 19582 REAL_OPCODE: Y 19583 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 19584 PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 19585 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 19586 IFORM: VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 19587 } 19588 19589 19590 # EMITTING VMOVSLDUP (VMOVSLDUP-512-1) 19591 { 19592 ICLASS: VMOVSLDUP 19593 CPL: 3 19594 CATEGORY: DATAXFER 19595 EXTENSION: AVX512EVEX 19596 ISA_SET: AVX512F_512 19597 EXCEPTIONS: AVX512-E4NF 19598 REAL_OPCODE: Y 19599 ATTRIBUTES: MASKOP_EVEX 19600 PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 19601 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 19602 IFORM: VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 19603 } 19604 19605 { 19606 ICLASS: VMOVSLDUP 19607 CPL: 3 19608 CATEGORY: DATAXFER 19609 EXTENSION: AVX512EVEX 19610 ISA_SET: AVX512F_512 19611 EXCEPTIONS: AVX512-E4NF 19612 REAL_OPCODE: Y 19613 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 19614 PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 19615 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 19616 IFORM: VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 19617 } 19618 19619 19620 # EMITTING VMOVSS (VMOVSS-128-1) 19621 { 19622 ICLASS: VMOVSS 19623 CPL: 3 19624 CATEGORY: DATAXFER 19625 EXTENSION: AVX512EVEX 19626 ISA_SET: AVX512F_SCALAR 19627 EXCEPTIONS: AVX512-E5 19628 REAL_OPCODE: Y 19629 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR 19630 PATTERN: EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ESIZE_32_BITS() NELEM_SCALAR() 19631 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 19632 IFORM: VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 19633 } 19634 19635 19636 # EMITTING VMOVSS (VMOVSS-128-2) 19637 { 19638 ICLASS: VMOVSS 19639 CPL: 3 19640 CATEGORY: DATAXFER 19641 EXTENSION: AVX512EVEX 19642 ISA_SET: AVX512F_SCALAR 19643 EXCEPTIONS: AVX512-E5 19644 REAL_OPCODE: Y 19645 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR 19646 PATTERN: EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_SCALAR() 19647 OPERANDS: MEM0:w:d:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 19648 IFORM: VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 19649 } 19650 19651 19652 # EMITTING VMOVSS (VMOVSS-128-3) 19653 { 19654 ICLASS: VMOVSS 19655 CPL: 3 19656 CATEGORY: DATAXFER 19657 EXTENSION: AVX512EVEX 19658 ISA_SET: AVX512F_SCALAR 19659 EXCEPTIONS: AVX512-E5 19660 REAL_OPCODE: Y 19661 ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR 19662 PATTERN: EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 19663 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 19664 IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 19665 } 19666 19667 19668 # EMITTING VMOVSS (VMOVSS-128-4) 19669 { 19670 ICLASS: VMOVSS 19671 CPL: 3 19672 CATEGORY: DATAXFER 19673 EXTENSION: AVX512EVEX 19674 ISA_SET: AVX512F_SCALAR 19675 EXCEPTIONS: AVX512-E5 19676 REAL_OPCODE: Y 19677 ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR 19678 PATTERN: EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 19679 OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_R3():r:dq:f32 19680 IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 19681 } 19682 19683 19684 # EMITTING VMOVUPD (VMOVUPD-512-1) 19685 { 19686 ICLASS: VMOVUPD 19687 CPL: 3 19688 CATEGORY: DATAXFER 19689 EXTENSION: AVX512EVEX 19690 ISA_SET: AVX512F_512 19691 EXCEPTIONS: AVX512-E4 19692 REAL_OPCODE: Y 19693 ATTRIBUTES: MASKOP_EVEX 19694 PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 19695 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 19696 IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 19697 } 19698 19699 { 19700 ICLASS: VMOVUPD 19701 CPL: 3 19702 CATEGORY: DATAXFER 19703 EXTENSION: AVX512EVEX 19704 ISA_SET: AVX512F_512 19705 EXCEPTIONS: AVX512-E4 19706 REAL_OPCODE: Y 19707 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 19708 PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 19709 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 19710 IFORM: VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 19711 } 19712 19713 19714 # EMITTING VMOVUPD (VMOVUPD-512-2) 19715 { 19716 ICLASS: VMOVUPD 19717 CPL: 3 19718 CATEGORY: DATAXFER 19719 EXTENSION: AVX512EVEX 19720 ISA_SET: AVX512F_512 19721 EXCEPTIONS: AVX512-E4 19722 REAL_OPCODE: Y 19723 ATTRIBUTES: MASKOP_EVEX 19724 PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 19725 OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 19726 IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 19727 } 19728 19729 19730 # EMITTING VMOVUPD (VMOVUPD-512-3) 19731 { 19732 ICLASS: VMOVUPD 19733 CPL: 3 19734 CATEGORY: DATAXFER 19735 EXTENSION: AVX512EVEX 19736 ISA_SET: AVX512F_512 19737 EXCEPTIONS: AVX512-E4 19738 REAL_OPCODE: Y 19739 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 19740 PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 19741 OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 19742 IFORM: VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 19743 } 19744 19745 19746 # EMITTING VMOVUPS (VMOVUPS-512-1) 19747 { 19748 ICLASS: VMOVUPS 19749 CPL: 3 19750 CATEGORY: DATAXFER 19751 EXTENSION: AVX512EVEX 19752 ISA_SET: AVX512F_512 19753 EXCEPTIONS: AVX512-E4 19754 REAL_OPCODE: Y 19755 ATTRIBUTES: MASKOP_EVEX 19756 PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 19757 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 19758 IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 19759 } 19760 19761 { 19762 ICLASS: VMOVUPS 19763 CPL: 3 19764 CATEGORY: DATAXFER 19765 EXTENSION: AVX512EVEX 19766 ISA_SET: AVX512F_512 19767 EXCEPTIONS: AVX512-E4 19768 REAL_OPCODE: Y 19769 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 19770 PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 19771 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 19772 IFORM: VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 19773 } 19774 19775 19776 # EMITTING VMOVUPS (VMOVUPS-512-2) 19777 { 19778 ICLASS: VMOVUPS 19779 CPL: 3 19780 CATEGORY: DATAXFER 19781 EXTENSION: AVX512EVEX 19782 ISA_SET: AVX512F_512 19783 EXCEPTIONS: AVX512-E4 19784 REAL_OPCODE: Y 19785 ATTRIBUTES: MASKOP_EVEX 19786 PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 19787 OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 19788 IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 19789 } 19790 19791 19792 # EMITTING VMOVUPS (VMOVUPS-512-3) 19793 { 19794 ICLASS: VMOVUPS 19795 CPL: 3 19796 CATEGORY: DATAXFER 19797 EXTENSION: AVX512EVEX 19798 ISA_SET: AVX512F_512 19799 EXCEPTIONS: AVX512-E4 19800 REAL_OPCODE: Y 19801 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 19802 PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 19803 OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 19804 IFORM: VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 19805 } 19806 19807 19808 # EMITTING VMULPD (VMULPD-512-1) 19809 { 19810 ICLASS: VMULPD 19811 CPL: 3 19812 CATEGORY: AVX512 19813 EXTENSION: AVX512EVEX 19814 ISA_SET: AVX512F_512 19815 EXCEPTIONS: AVX512-E2 19816 REAL_OPCODE: Y 19817 ATTRIBUTES: MASKOP_EVEX MXCSR 19818 PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 19819 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 19820 IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 19821 } 19822 19823 { 19824 ICLASS: VMULPD 19825 CPL: 3 19826 CATEGORY: AVX512 19827 EXTENSION: AVX512EVEX 19828 ISA_SET: AVX512F_512 19829 EXCEPTIONS: AVX512-E2 19830 REAL_OPCODE: Y 19831 ATTRIBUTES: MASKOP_EVEX MXCSR 19832 PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 19833 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 19834 IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 19835 } 19836 19837 { 19838 ICLASS: VMULPD 19839 CPL: 3 19840 CATEGORY: AVX512 19841 EXTENSION: AVX512EVEX 19842 ISA_SET: AVX512F_512 19843 EXCEPTIONS: AVX512-E2 19844 REAL_OPCODE: Y 19845 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 19846 PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 19847 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 19848 IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 19849 } 19850 19851 19852 # EMITTING VMULPS (VMULPS-512-1) 19853 { 19854 ICLASS: VMULPS 19855 CPL: 3 19856 CATEGORY: AVX512 19857 EXTENSION: AVX512EVEX 19858 ISA_SET: AVX512F_512 19859 EXCEPTIONS: AVX512-E2 19860 REAL_OPCODE: Y 19861 ATTRIBUTES: MASKOP_EVEX MXCSR 19862 PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 19863 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 19864 IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 19865 } 19866 19867 { 19868 ICLASS: VMULPS 19869 CPL: 3 19870 CATEGORY: AVX512 19871 EXTENSION: AVX512EVEX 19872 ISA_SET: AVX512F_512 19873 EXCEPTIONS: AVX512-E2 19874 REAL_OPCODE: Y 19875 ATTRIBUTES: MASKOP_EVEX MXCSR 19876 PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 19877 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 19878 IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 19879 } 19880 19881 { 19882 ICLASS: VMULPS 19883 CPL: 3 19884 CATEGORY: AVX512 19885 EXTENSION: AVX512EVEX 19886 ISA_SET: AVX512F_512 19887 EXCEPTIONS: AVX512-E2 19888 REAL_OPCODE: Y 19889 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 19890 PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 19891 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 19892 IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 19893 } 19894 19895 19896 # EMITTING VMULSD (VMULSD-128-1) 19897 { 19898 ICLASS: VMULSD 19899 CPL: 3 19900 CATEGORY: AVX512 19901 EXTENSION: AVX512EVEX 19902 ISA_SET: AVX512F_SCALAR 19903 EXCEPTIONS: AVX512-E3 19904 REAL_OPCODE: Y 19905 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 19906 PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 19907 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 19908 IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 19909 } 19910 19911 { 19912 ICLASS: VMULSD 19913 CPL: 3 19914 CATEGORY: AVX512 19915 EXTENSION: AVX512EVEX 19916 ISA_SET: AVX512F_SCALAR 19917 EXCEPTIONS: AVX512-E3 19918 REAL_OPCODE: Y 19919 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 19920 PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 19921 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 19922 IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 19923 } 19924 19925 { 19926 ICLASS: VMULSD 19927 CPL: 3 19928 CATEGORY: AVX512 19929 EXTENSION: AVX512EVEX 19930 ISA_SET: AVX512F_SCALAR 19931 EXCEPTIONS: AVX512-E3 19932 REAL_OPCODE: Y 19933 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 19934 PATTERN: EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 19935 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 19936 IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 19937 } 19938 19939 19940 # EMITTING VMULSS (VMULSS-128-1) 19941 { 19942 ICLASS: VMULSS 19943 CPL: 3 19944 CATEGORY: AVX512 19945 EXTENSION: AVX512EVEX 19946 ISA_SET: AVX512F_SCALAR 19947 EXCEPTIONS: AVX512-E3 19948 REAL_OPCODE: Y 19949 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 19950 PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 19951 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 19952 IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 19953 } 19954 19955 { 19956 ICLASS: VMULSS 19957 CPL: 3 19958 CATEGORY: AVX512 19959 EXTENSION: AVX512EVEX 19960 ISA_SET: AVX512F_SCALAR 19961 EXCEPTIONS: AVX512-E3 19962 REAL_OPCODE: Y 19963 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 19964 PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 19965 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 19966 IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 19967 } 19968 19969 { 19970 ICLASS: VMULSS 19971 CPL: 3 19972 CATEGORY: AVX512 19973 EXTENSION: AVX512EVEX 19974 ISA_SET: AVX512F_SCALAR 19975 EXCEPTIONS: AVX512-E3 19976 REAL_OPCODE: Y 19977 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 19978 PATTERN: EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 19979 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 19980 IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 19981 } 19982 19983 19984 # EMITTING VPABSD (VPABSD-512-1) 19985 { 19986 ICLASS: VPABSD 19987 CPL: 3 19988 CATEGORY: AVX512 19989 EXTENSION: AVX512EVEX 19990 ISA_SET: AVX512F_512 19991 EXCEPTIONS: AVX512-E4 19992 REAL_OPCODE: Y 19993 ATTRIBUTES: MASKOP_EVEX 19994 PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 19995 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 19996 IFORM: VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 19997 } 19998 19999 { 20000 ICLASS: VPABSD 20001 CPL: 3 20002 CATEGORY: AVX512 20003 EXTENSION: AVX512EVEX 20004 ISA_SET: AVX512F_512 20005 EXCEPTIONS: AVX512-E4 20006 REAL_OPCODE: Y 20007 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20008 PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 20009 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 20010 IFORM: VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 20011 } 20012 20013 20014 # EMITTING VPABSQ (VPABSQ-512-1) 20015 { 20016 ICLASS: VPABSQ 20017 CPL: 3 20018 CATEGORY: AVX512 20019 EXTENSION: AVX512EVEX 20020 ISA_SET: AVX512F_512 20021 EXCEPTIONS: AVX512-E4 20022 REAL_OPCODE: Y 20023 ATTRIBUTES: MASKOP_EVEX 20024 PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 20025 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi64 20026 IFORM: VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 20027 } 20028 20029 { 20030 ICLASS: VPABSQ 20031 CPL: 3 20032 CATEGORY: AVX512 20033 EXTENSION: AVX512EVEX 20034 ISA_SET: AVX512F_512 20035 EXCEPTIONS: AVX512-E4 20036 REAL_OPCODE: Y 20037 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20038 PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 20039 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR 20040 IFORM: VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 20041 } 20042 20043 20044 # EMITTING VPADDD (VPADDD-512-1) 20045 { 20046 ICLASS: VPADDD 20047 CPL: 3 20048 CATEGORY: AVX512 20049 EXTENSION: AVX512EVEX 20050 ISA_SET: AVX512F_512 20051 EXCEPTIONS: AVX512-E4 20052 REAL_OPCODE: Y 20053 ATTRIBUTES: MASKOP_EVEX 20054 PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 20055 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 20056 IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 20057 } 20058 20059 { 20060 ICLASS: VPADDD 20061 CPL: 3 20062 CATEGORY: AVX512 20063 EXTENSION: AVX512EVEX 20064 ISA_SET: AVX512F_512 20065 EXCEPTIONS: AVX512-E4 20066 REAL_OPCODE: Y 20067 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20068 PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 20069 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 20070 IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 20071 } 20072 20073 20074 # EMITTING VPADDQ (VPADDQ-512-1) 20075 { 20076 ICLASS: VPADDQ 20077 CPL: 3 20078 CATEGORY: AVX512 20079 EXTENSION: AVX512EVEX 20080 ISA_SET: AVX512F_512 20081 EXCEPTIONS: AVX512-E4 20082 REAL_OPCODE: Y 20083 ATTRIBUTES: MASKOP_EVEX 20084 PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 20085 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 20086 IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 20087 } 20088 20089 { 20090 ICLASS: VPADDQ 20091 CPL: 3 20092 CATEGORY: AVX512 20093 EXTENSION: AVX512EVEX 20094 ISA_SET: AVX512F_512 20095 EXCEPTIONS: AVX512-E4 20096 REAL_OPCODE: Y 20097 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20098 PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 20099 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 20100 IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 20101 } 20102 20103 20104 # EMITTING VPANDD (VPANDD-512-1) 20105 { 20106 ICLASS: VPANDD 20107 CPL: 3 20108 CATEGORY: LOGICAL 20109 EXTENSION: AVX512EVEX 20110 ISA_SET: AVX512F_512 20111 EXCEPTIONS: AVX512-E4 20112 REAL_OPCODE: Y 20113 ATTRIBUTES: MASKOP_EVEX 20114 PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 20115 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 20116 IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 20117 } 20118 20119 { 20120 ICLASS: VPANDD 20121 CPL: 3 20122 CATEGORY: LOGICAL 20123 EXTENSION: AVX512EVEX 20124 ISA_SET: AVX512F_512 20125 EXCEPTIONS: AVX512-E4 20126 REAL_OPCODE: Y 20127 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20128 PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 20129 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 20130 IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 20131 } 20132 20133 20134 # EMITTING VPANDND (VPANDND-512-1) 20135 { 20136 ICLASS: VPANDND 20137 CPL: 3 20138 CATEGORY: LOGICAL 20139 EXTENSION: AVX512EVEX 20140 ISA_SET: AVX512F_512 20141 EXCEPTIONS: AVX512-E4 20142 REAL_OPCODE: Y 20143 ATTRIBUTES: MASKOP_EVEX 20144 PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 20145 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 20146 IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 20147 } 20148 20149 { 20150 ICLASS: VPANDND 20151 CPL: 3 20152 CATEGORY: LOGICAL 20153 EXTENSION: AVX512EVEX 20154 ISA_SET: AVX512F_512 20155 EXCEPTIONS: AVX512-E4 20156 REAL_OPCODE: Y 20157 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20158 PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 20159 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 20160 IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 20161 } 20162 20163 20164 # EMITTING VPANDNQ (VPANDNQ-512-1) 20165 { 20166 ICLASS: VPANDNQ 20167 CPL: 3 20168 CATEGORY: LOGICAL 20169 EXTENSION: AVX512EVEX 20170 ISA_SET: AVX512F_512 20171 EXCEPTIONS: AVX512-E4 20172 REAL_OPCODE: Y 20173 ATTRIBUTES: MASKOP_EVEX 20174 PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 20175 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 20176 IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 20177 } 20178 20179 { 20180 ICLASS: VPANDNQ 20181 CPL: 3 20182 CATEGORY: LOGICAL 20183 EXTENSION: AVX512EVEX 20184 ISA_SET: AVX512F_512 20185 EXCEPTIONS: AVX512-E4 20186 REAL_OPCODE: Y 20187 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20188 PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 20189 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 20190 IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 20191 } 20192 20193 20194 # EMITTING VPANDQ (VPANDQ-512-1) 20195 { 20196 ICLASS: VPANDQ 20197 CPL: 3 20198 CATEGORY: LOGICAL 20199 EXTENSION: AVX512EVEX 20200 ISA_SET: AVX512F_512 20201 EXCEPTIONS: AVX512-E4 20202 REAL_OPCODE: Y 20203 ATTRIBUTES: MASKOP_EVEX 20204 PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 20205 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 20206 IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 20207 } 20208 20209 { 20210 ICLASS: VPANDQ 20211 CPL: 3 20212 CATEGORY: LOGICAL 20213 EXTENSION: AVX512EVEX 20214 ISA_SET: AVX512F_512 20215 EXCEPTIONS: AVX512-E4 20216 REAL_OPCODE: Y 20217 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20218 PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 20219 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 20220 IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 20221 } 20222 20223 20224 # EMITTING VPBLENDMD (VPBLENDMD-512-1) 20225 { 20226 ICLASS: VPBLENDMD 20227 CPL: 3 20228 CATEGORY: BLEND 20229 EXTENSION: AVX512EVEX 20230 ISA_SET: AVX512F_512 20231 EXCEPTIONS: AVX512-E4 20232 REAL_OPCODE: Y 20233 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 20234 PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 20235 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 20236 IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 20237 } 20238 20239 { 20240 ICLASS: VPBLENDMD 20241 CPL: 3 20242 CATEGORY: BLEND 20243 EXTENSION: AVX512EVEX 20244 ISA_SET: AVX512F_512 20245 EXCEPTIONS: AVX512-E4 20246 REAL_OPCODE: Y 20247 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL 20248 PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 20249 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 20250 IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 20251 } 20252 20253 20254 # EMITTING VPBLENDMQ (VPBLENDMQ-512-1) 20255 { 20256 ICLASS: VPBLENDMQ 20257 CPL: 3 20258 CATEGORY: BLEND 20259 EXTENSION: AVX512EVEX 20260 ISA_SET: AVX512F_512 20261 EXCEPTIONS: AVX512-E4 20262 REAL_OPCODE: Y 20263 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 20264 PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 20265 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 20266 IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 20267 } 20268 20269 { 20270 ICLASS: VPBLENDMQ 20271 CPL: 3 20272 CATEGORY: BLEND 20273 EXTENSION: AVX512EVEX 20274 ISA_SET: AVX512F_512 20275 EXCEPTIONS: AVX512-E4 20276 REAL_OPCODE: Y 20277 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL 20278 PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 20279 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 20280 IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 20281 } 20282 20283 20284 # EMITTING VPBROADCASTD (VPBROADCASTD-512-1) 20285 { 20286 ICLASS: VPBROADCASTD 20287 CPL: 3 20288 CATEGORY: BROADCAST 20289 EXTENSION: AVX512EVEX 20290 ISA_SET: AVX512F_512 20291 EXCEPTIONS: AVX512-E6 20292 REAL_OPCODE: Y 20293 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 20294 PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() 20295 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO16_32 20296 IFORM: VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 20297 } 20298 20299 20300 # EMITTING VPBROADCASTD (VPBROADCASTD-512-2) 20301 { 20302 ICLASS: VPBROADCASTD 20303 CPL: 3 20304 CATEGORY: BROADCAST 20305 EXTENSION: AVX512EVEX 20306 ISA_SET: AVX512F_512 20307 EXCEPTIONS: AVX512-E6 20308 REAL_OPCODE: Y 20309 ATTRIBUTES: MASKOP_EVEX 20310 PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 20311 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO16_32 20312 IFORM: VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 20313 } 20314 20315 20316 # EMITTING VPBROADCASTD (VPBROADCASTD-512-3) 20317 { 20318 ICLASS: VPBROADCASTD 20319 CPL: 3 20320 CATEGORY: BROADCAST 20321 EXTENSION: AVX512EVEX 20322 ISA_SET: AVX512F_512 20323 EXCEPTIONS: AVX512-E7NM 20324 REAL_OPCODE: Y 20325 ATTRIBUTES: MASKOP_EVEX 20326 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 not64 NOEVSR 20327 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 20328 IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 20329 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W0 NOEVSR 20330 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 20331 IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 20332 } 20333 20334 20335 # EMITTING VPBROADCASTQ (VPBROADCASTQ-512-1) 20336 { 20337 ICLASS: VPBROADCASTQ 20338 CPL: 3 20339 CATEGORY: BROADCAST 20340 EXTENSION: AVX512EVEX 20341 ISA_SET: AVX512F_512 20342 EXCEPTIONS: AVX512-E6 20343 REAL_OPCODE: Y 20344 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 20345 PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() 20346 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO8_64 20347 IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 20348 } 20349 20350 20351 # EMITTING VPBROADCASTQ (VPBROADCASTQ-512-2) 20352 { 20353 ICLASS: VPBROADCASTQ 20354 CPL: 3 20355 CATEGORY: BROADCAST 20356 EXTENSION: AVX512EVEX 20357 ISA_SET: AVX512F_512 20358 EXCEPTIONS: AVX512-E6 20359 REAL_OPCODE: Y 20360 ATTRIBUTES: MASKOP_EVEX 20361 PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 20362 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO8_64 20363 IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 20364 } 20365 20366 20367 # EMITTING VPBROADCASTQ (VPBROADCASTQ-512-3) 20368 { 20369 ICLASS: VPBROADCASTQ 20370 CPL: 3 20371 CATEGORY: BROADCAST 20372 EXTENSION: AVX512EVEX 20373 ISA_SET: AVX512F_512 20374 EXCEPTIONS: AVX512-E7NM 20375 REAL_OPCODE: Y 20376 ATTRIBUTES: MASKOP_EVEX 20377 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W1 NOEVSR 20378 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO8_64 20379 IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 20380 } 20381 20382 20383 # EMITTING VPCMPD (VPCMPD-512-1) 20384 { 20385 ICLASS: VPCMPD 20386 CPL: 3 20387 CATEGORY: AVX512 20388 EXTENSION: AVX512EVEX 20389 ISA_SET: AVX512F_512 20390 EXCEPTIONS: AVX512-E4 20391 REAL_OPCODE: Y 20392 ATTRIBUTES: MASKOP_EVEX 20393 PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() 20394 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 IMM0:r:b 20395 IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 20396 } 20397 20398 { 20399 ICLASS: VPCMPD 20400 CPL: 3 20401 CATEGORY: AVX512 20402 EXTENSION: AVX512EVEX 20403 ISA_SET: AVX512F_512 20404 EXCEPTIONS: AVX512-E4 20405 REAL_OPCODE: Y 20406 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20407 PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 20408 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b 20409 IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 20410 } 20411 20412 20413 # EMITTING VPCMPEQD (VPCMPEQD-512-1) 20414 { 20415 ICLASS: VPCMPEQD 20416 CPL: 3 20417 CATEGORY: AVX512 20418 EXTENSION: AVX512EVEX 20419 ISA_SET: AVX512F_512 20420 EXCEPTIONS: AVX512-E4 20421 REAL_OPCODE: Y 20422 ATTRIBUTES: MASKOP_EVEX 20423 PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 20424 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 20425 IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 20426 } 20427 20428 { 20429 ICLASS: VPCMPEQD 20430 CPL: 3 20431 CATEGORY: AVX512 20432 EXTENSION: AVX512EVEX 20433 ISA_SET: AVX512F_512 20434 EXCEPTIONS: AVX512-E4 20435 REAL_OPCODE: Y 20436 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20437 PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 20438 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 20439 IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 20440 } 20441 20442 20443 # EMITTING VPCMPEQQ (VPCMPEQQ-512-1) 20444 { 20445 ICLASS: VPCMPEQQ 20446 CPL: 3 20447 CATEGORY: AVX512 20448 EXTENSION: AVX512EVEX 20449 ISA_SET: AVX512F_512 20450 EXCEPTIONS: AVX512-E4 20451 REAL_OPCODE: Y 20452 ATTRIBUTES: MASKOP_EVEX 20453 PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 20454 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 20455 IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 20456 } 20457 20458 { 20459 ICLASS: VPCMPEQQ 20460 CPL: 3 20461 CATEGORY: AVX512 20462 EXTENSION: AVX512EVEX 20463 ISA_SET: AVX512F_512 20464 EXCEPTIONS: AVX512-E4 20465 REAL_OPCODE: Y 20466 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20467 PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 20468 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 20469 IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 20470 } 20471 20472 20473 # EMITTING VPCMPGTD (VPCMPGTD-512-1) 20474 { 20475 ICLASS: VPCMPGTD 20476 CPL: 3 20477 CATEGORY: AVX512 20478 EXTENSION: AVX512EVEX 20479 ISA_SET: AVX512F_512 20480 EXCEPTIONS: AVX512-E4 20481 REAL_OPCODE: Y 20482 ATTRIBUTES: MASKOP_EVEX 20483 PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 20484 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 20485 IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 20486 } 20487 20488 { 20489 ICLASS: VPCMPGTD 20490 CPL: 3 20491 CATEGORY: AVX512 20492 EXTENSION: AVX512EVEX 20493 ISA_SET: AVX512F_512 20494 EXCEPTIONS: AVX512-E4 20495 REAL_OPCODE: Y 20496 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20497 PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 20498 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR 20499 IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 20500 } 20501 20502 20503 # EMITTING VPCMPGTQ (VPCMPGTQ-512-1) 20504 { 20505 ICLASS: VPCMPGTQ 20506 CPL: 3 20507 CATEGORY: AVX512 20508 EXTENSION: AVX512EVEX 20509 ISA_SET: AVX512F_512 20510 EXCEPTIONS: AVX512-E4 20511 REAL_OPCODE: Y 20512 ATTRIBUTES: MASKOP_EVEX 20513 PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 20514 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 20515 IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 20516 } 20517 20518 { 20519 ICLASS: VPCMPGTQ 20520 CPL: 3 20521 CATEGORY: AVX512 20522 EXTENSION: AVX512EVEX 20523 ISA_SET: AVX512F_512 20524 EXCEPTIONS: AVX512-E4 20525 REAL_OPCODE: Y 20526 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20527 PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 20528 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR 20529 IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 20530 } 20531 20532 20533 # EMITTING VPCMPQ (VPCMPQ-512-1) 20534 { 20535 ICLASS: VPCMPQ 20536 CPL: 3 20537 CATEGORY: AVX512 20538 EXTENSION: AVX512EVEX 20539 ISA_SET: AVX512F_512 20540 EXCEPTIONS: AVX512-E4 20541 REAL_OPCODE: Y 20542 ATTRIBUTES: MASKOP_EVEX 20543 PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() 20544 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 IMM0:r:b 20545 IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 20546 } 20547 20548 { 20549 ICLASS: VPCMPQ 20550 CPL: 3 20551 CATEGORY: AVX512 20552 EXTENSION: AVX512EVEX 20553 ISA_SET: AVX512F_512 20554 EXCEPTIONS: AVX512-E4 20555 REAL_OPCODE: Y 20556 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20557 PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 20558 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b 20559 IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 20560 } 20561 20562 20563 # EMITTING VPCMPUD (VPCMPUD-512-1) 20564 { 20565 ICLASS: VPCMPUD 20566 CPL: 3 20567 CATEGORY: AVX512 20568 EXTENSION: AVX512EVEX 20569 ISA_SET: AVX512F_512 20570 EXCEPTIONS: AVX512-E4 20571 REAL_OPCODE: Y 20572 ATTRIBUTES: MASKOP_EVEX 20573 PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() 20574 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b 20575 IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 20576 } 20577 20578 { 20579 ICLASS: VPCMPUD 20580 CPL: 3 20581 CATEGORY: AVX512 20582 EXTENSION: AVX512EVEX 20583 ISA_SET: AVX512F_512 20584 EXCEPTIONS: AVX512-E4 20585 REAL_OPCODE: Y 20586 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20587 PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 20588 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 20589 IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 20590 } 20591 20592 20593 # EMITTING VPCMPUQ (VPCMPUQ-512-1) 20594 { 20595 ICLASS: VPCMPUQ 20596 CPL: 3 20597 CATEGORY: AVX512 20598 EXTENSION: AVX512EVEX 20599 ISA_SET: AVX512F_512 20600 EXCEPTIONS: AVX512-E4 20601 REAL_OPCODE: Y 20602 ATTRIBUTES: MASKOP_EVEX 20603 PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() 20604 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b 20605 IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 20606 } 20607 20608 { 20609 ICLASS: VPCMPUQ 20610 CPL: 3 20611 CATEGORY: AVX512 20612 EXTENSION: AVX512EVEX 20613 ISA_SET: AVX512F_512 20614 EXCEPTIONS: AVX512-E4 20615 REAL_OPCODE: Y 20616 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20617 PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 20618 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 20619 IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 20620 } 20621 20622 20623 # EMITTING VPCOMPRESSD (VPCOMPRESSD-512-1) 20624 { 20625 ICLASS: VPCOMPRESSD 20626 CPL: 3 20627 CATEGORY: COMPRESS 20628 EXTENSION: AVX512EVEX 20629 ISA_SET: AVX512F_512 20630 EXCEPTIONS: AVX512-E4 20631 REAL_OPCODE: Y 20632 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 20633 PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 20634 OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 20635 IFORM: VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 20636 } 20637 20638 20639 # EMITTING VPCOMPRESSD (VPCOMPRESSD-512-2) 20640 { 20641 ICLASS: VPCOMPRESSD 20642 CPL: 3 20643 CATEGORY: COMPRESS 20644 EXTENSION: AVX512EVEX 20645 ISA_SET: AVX512F_512 20646 EXCEPTIONS: AVX512-E4 20647 REAL_OPCODE: Y 20648 ATTRIBUTES: MASKOP_EVEX 20649 PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 20650 OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 20651 IFORM: VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 20652 } 20653 20654 20655 # EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-1) 20656 { 20657 ICLASS: VPCOMPRESSQ 20658 CPL: 3 20659 CATEGORY: COMPRESS 20660 EXTENSION: AVX512EVEX 20661 ISA_SET: AVX512F_512 20662 EXCEPTIONS: AVX512-E4 20663 REAL_OPCODE: Y 20664 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 20665 PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 20666 OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 20667 IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 20668 } 20669 20670 20671 # EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-2) 20672 { 20673 ICLASS: VPCOMPRESSQ 20674 CPL: 3 20675 CATEGORY: COMPRESS 20676 EXTENSION: AVX512EVEX 20677 ISA_SET: AVX512F_512 20678 EXCEPTIONS: AVX512-E4 20679 REAL_OPCODE: Y 20680 ATTRIBUTES: MASKOP_EVEX 20681 PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 20682 OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 20683 IFORM: VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 20684 } 20685 20686 20687 # EMITTING VPERMD (VPERMD-512-1) 20688 { 20689 ICLASS: VPERMD 20690 CPL: 3 20691 CATEGORY: AVX512 20692 EXTENSION: AVX512EVEX 20693 ISA_SET: AVX512F_512 20694 EXCEPTIONS: AVX512-E4NF 20695 REAL_OPCODE: Y 20696 ATTRIBUTES: MASKOP_EVEX 20697 PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 20698 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 20699 IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 20700 } 20701 20702 { 20703 ICLASS: VPERMD 20704 CPL: 3 20705 CATEGORY: AVX512 20706 EXTENSION: AVX512EVEX 20707 ISA_SET: AVX512F_512 20708 EXCEPTIONS: AVX512-E4NF 20709 REAL_OPCODE: Y 20710 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20711 PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 20712 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 20713 IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 20714 } 20715 20716 20717 # EMITTING VPERMI2D (VPERMI2D-512-1) 20718 { 20719 ICLASS: VPERMI2D 20720 CPL: 3 20721 CATEGORY: AVX512 20722 EXTENSION: AVX512EVEX 20723 ISA_SET: AVX512F_512 20724 EXCEPTIONS: AVX512-E4NF 20725 REAL_OPCODE: Y 20726 ATTRIBUTES: MASKOP_EVEX 20727 PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 20728 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 20729 IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 20730 } 20731 20732 { 20733 ICLASS: VPERMI2D 20734 CPL: 3 20735 CATEGORY: AVX512 20736 EXTENSION: AVX512EVEX 20737 ISA_SET: AVX512F_512 20738 EXCEPTIONS: AVX512-E4NF 20739 REAL_OPCODE: Y 20740 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20741 PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 20742 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 20743 IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 20744 } 20745 20746 20747 # EMITTING VPERMI2PD (VPERMI2PD-512-1) 20748 { 20749 ICLASS: VPERMI2PD 20750 CPL: 3 20751 CATEGORY: AVX512 20752 EXTENSION: AVX512EVEX 20753 ISA_SET: AVX512F_512 20754 EXCEPTIONS: AVX512-E4NF 20755 REAL_OPCODE: Y 20756 ATTRIBUTES: MASKOP_EVEX 20757 PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 20758 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 20759 IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 20760 } 20761 20762 { 20763 ICLASS: VPERMI2PD 20764 CPL: 3 20765 CATEGORY: AVX512 20766 EXTENSION: AVX512EVEX 20767 ISA_SET: AVX512F_512 20768 EXCEPTIONS: AVX512-E4NF 20769 REAL_OPCODE: Y 20770 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20771 PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 20772 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 20773 IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 20774 } 20775 20776 20777 # EMITTING VPERMI2PS (VPERMI2PS-512-1) 20778 { 20779 ICLASS: VPERMI2PS 20780 CPL: 3 20781 CATEGORY: AVX512 20782 EXTENSION: AVX512EVEX 20783 ISA_SET: AVX512F_512 20784 EXCEPTIONS: AVX512-E4NF 20785 REAL_OPCODE: Y 20786 ATTRIBUTES: MASKOP_EVEX 20787 PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 20788 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 20789 IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 20790 } 20791 20792 { 20793 ICLASS: VPERMI2PS 20794 CPL: 3 20795 CATEGORY: AVX512 20796 EXTENSION: AVX512EVEX 20797 ISA_SET: AVX512F_512 20798 EXCEPTIONS: AVX512-E4NF 20799 REAL_OPCODE: Y 20800 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20801 PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 20802 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 20803 IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 20804 } 20805 20806 20807 # EMITTING VPERMI2Q (VPERMI2Q-512-1) 20808 { 20809 ICLASS: VPERMI2Q 20810 CPL: 3 20811 CATEGORY: AVX512 20812 EXTENSION: AVX512EVEX 20813 ISA_SET: AVX512F_512 20814 EXCEPTIONS: AVX512-E4NF 20815 REAL_OPCODE: Y 20816 ATTRIBUTES: MASKOP_EVEX 20817 PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 20818 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 20819 IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 20820 } 20821 20822 { 20823 ICLASS: VPERMI2Q 20824 CPL: 3 20825 CATEGORY: AVX512 20826 EXTENSION: AVX512EVEX 20827 ISA_SET: AVX512F_512 20828 EXCEPTIONS: AVX512-E4NF 20829 REAL_OPCODE: Y 20830 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20831 PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 20832 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 20833 IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 20834 } 20835 20836 20837 # EMITTING VPERMILPD (VPERMILPD-512-1) 20838 { 20839 ICLASS: VPERMILPD 20840 CPL: 3 20841 CATEGORY: AVX512 20842 EXTENSION: AVX512EVEX 20843 ISA_SET: AVX512F_512 20844 EXCEPTIONS: AVX512-E4NF 20845 REAL_OPCODE: Y 20846 ATTRIBUTES: MASKOP_EVEX 20847 PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 20848 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 20849 IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 20850 } 20851 20852 { 20853 ICLASS: VPERMILPD 20854 CPL: 3 20855 CATEGORY: AVX512 20856 EXTENSION: AVX512EVEX 20857 ISA_SET: AVX512F_512 20858 EXCEPTIONS: AVX512-E4NF 20859 REAL_OPCODE: Y 20860 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20861 PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 20862 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 20863 IFORM: VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 20864 } 20865 20866 20867 # EMITTING VPERMILPD (VPERMILPD-512-2) 20868 { 20869 ICLASS: VPERMILPD 20870 CPL: 3 20871 CATEGORY: AVX512 20872 EXTENSION: AVX512EVEX 20873 ISA_SET: AVX512F_512 20874 EXCEPTIONS: AVX512-E4NF 20875 REAL_OPCODE: Y 20876 ATTRIBUTES: MASKOP_EVEX 20877 PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 20878 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 20879 IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 20880 } 20881 20882 { 20883 ICLASS: VPERMILPD 20884 CPL: 3 20885 CATEGORY: AVX512 20886 EXTENSION: AVX512EVEX 20887 ISA_SET: AVX512F_512 20888 EXCEPTIONS: AVX512-E4NF 20889 REAL_OPCODE: Y 20890 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20891 PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 20892 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 20893 IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 20894 } 20895 20896 20897 # EMITTING VPERMILPS (VPERMILPS-512-1) 20898 { 20899 ICLASS: VPERMILPS 20900 CPL: 3 20901 CATEGORY: AVX512 20902 EXTENSION: AVX512EVEX 20903 ISA_SET: AVX512F_512 20904 EXCEPTIONS: AVX512-E4NF 20905 REAL_OPCODE: Y 20906 ATTRIBUTES: MASKOP_EVEX 20907 PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 20908 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 20909 IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 20910 } 20911 20912 { 20913 ICLASS: VPERMILPS 20914 CPL: 3 20915 CATEGORY: AVX512 20916 EXTENSION: AVX512EVEX 20917 ISA_SET: AVX512F_512 20918 EXCEPTIONS: AVX512-E4NF 20919 REAL_OPCODE: Y 20920 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20921 PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 20922 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 20923 IFORM: VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 20924 } 20925 20926 20927 # EMITTING VPERMILPS (VPERMILPS-512-2) 20928 { 20929 ICLASS: VPERMILPS 20930 CPL: 3 20931 CATEGORY: AVX512 20932 EXTENSION: AVX512EVEX 20933 ISA_SET: AVX512F_512 20934 EXCEPTIONS: AVX512-E4NF 20935 REAL_OPCODE: Y 20936 ATTRIBUTES: MASKOP_EVEX 20937 PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 20938 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 20939 IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 20940 } 20941 20942 { 20943 ICLASS: VPERMILPS 20944 CPL: 3 20945 CATEGORY: AVX512 20946 EXTENSION: AVX512EVEX 20947 ISA_SET: AVX512F_512 20948 EXCEPTIONS: AVX512-E4NF 20949 REAL_OPCODE: Y 20950 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20951 PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 20952 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 20953 IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 20954 } 20955 20956 20957 # EMITTING VPERMPD (VPERMPD-512-1) 20958 { 20959 ICLASS: VPERMPD 20960 CPL: 3 20961 CATEGORY: AVX512 20962 EXTENSION: AVX512EVEX 20963 ISA_SET: AVX512F_512 20964 EXCEPTIONS: AVX512-E4NF 20965 REAL_OPCODE: Y 20966 ATTRIBUTES: MASKOP_EVEX 20967 PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 20968 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 20969 IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 20970 } 20971 20972 { 20973 ICLASS: VPERMPD 20974 CPL: 3 20975 CATEGORY: AVX512 20976 EXTENSION: AVX512EVEX 20977 ISA_SET: AVX512F_512 20978 EXCEPTIONS: AVX512-E4NF 20979 REAL_OPCODE: Y 20980 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 20981 PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 20982 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 20983 IFORM: VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 20984 } 20985 20986 20987 # EMITTING VPERMPD (VPERMPD-512-2) 20988 { 20989 ICLASS: VPERMPD 20990 CPL: 3 20991 CATEGORY: AVX512 20992 EXTENSION: AVX512EVEX 20993 ISA_SET: AVX512F_512 20994 EXCEPTIONS: AVX512-E4NF 20995 REAL_OPCODE: Y 20996 ATTRIBUTES: MASKOP_EVEX 20997 PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 20998 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 20999 IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 21000 } 21001 21002 { 21003 ICLASS: VPERMPD 21004 CPL: 3 21005 CATEGORY: AVX512 21006 EXTENSION: AVX512EVEX 21007 ISA_SET: AVX512F_512 21008 EXCEPTIONS: AVX512-E4NF 21009 REAL_OPCODE: Y 21010 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21011 PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 21012 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 21013 IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 21014 } 21015 21016 21017 # EMITTING VPERMPS (VPERMPS-512-1) 21018 { 21019 ICLASS: VPERMPS 21020 CPL: 3 21021 CATEGORY: AVX512 21022 EXTENSION: AVX512EVEX 21023 ISA_SET: AVX512F_512 21024 EXCEPTIONS: AVX512-E4NF 21025 REAL_OPCODE: Y 21026 ATTRIBUTES: MASKOP_EVEX 21027 PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 21028 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 21029 IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 21030 } 21031 21032 { 21033 ICLASS: VPERMPS 21034 CPL: 3 21035 CATEGORY: AVX512 21036 EXTENSION: AVX512EVEX 21037 ISA_SET: AVX512F_512 21038 EXCEPTIONS: AVX512-E4NF 21039 REAL_OPCODE: Y 21040 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21041 PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 21042 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 21043 IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 21044 } 21045 21046 21047 # EMITTING VPERMQ (VPERMQ-512-1) 21048 { 21049 ICLASS: VPERMQ 21050 CPL: 3 21051 CATEGORY: AVX512 21052 EXTENSION: AVX512EVEX 21053 ISA_SET: AVX512F_512 21054 EXCEPTIONS: AVX512-E4NF 21055 REAL_OPCODE: Y 21056 ATTRIBUTES: MASKOP_EVEX 21057 PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 21058 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b 21059 IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 21060 } 21061 21062 { 21063 ICLASS: VPERMQ 21064 CPL: 3 21065 CATEGORY: AVX512 21066 EXTENSION: AVX512EVEX 21067 ISA_SET: AVX512F_512 21068 EXCEPTIONS: AVX512-E4NF 21069 REAL_OPCODE: Y 21070 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21071 PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 21072 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 21073 IFORM: VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 21074 } 21075 21076 21077 # EMITTING VPERMQ (VPERMQ-512-2) 21078 { 21079 ICLASS: VPERMQ 21080 CPL: 3 21081 CATEGORY: AVX512 21082 EXTENSION: AVX512EVEX 21083 ISA_SET: AVX512F_512 21084 EXCEPTIONS: AVX512-E4NF 21085 REAL_OPCODE: Y 21086 ATTRIBUTES: MASKOP_EVEX 21087 PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 21088 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 21089 IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 21090 } 21091 21092 { 21093 ICLASS: VPERMQ 21094 CPL: 3 21095 CATEGORY: AVX512 21096 EXTENSION: AVX512EVEX 21097 ISA_SET: AVX512F_512 21098 EXCEPTIONS: AVX512-E4NF 21099 REAL_OPCODE: Y 21100 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21101 PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 21102 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 21103 IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 21104 } 21105 21106 21107 # EMITTING VPERMT2D (VPERMT2D-512-1) 21108 { 21109 ICLASS: VPERMT2D 21110 CPL: 3 21111 CATEGORY: AVX512 21112 EXTENSION: AVX512EVEX 21113 ISA_SET: AVX512F_512 21114 EXCEPTIONS: AVX512-E4NF 21115 REAL_OPCODE: Y 21116 ATTRIBUTES: MASKOP_EVEX 21117 PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 21118 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 21119 IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 21120 } 21121 21122 { 21123 ICLASS: VPERMT2D 21124 CPL: 3 21125 CATEGORY: AVX512 21126 EXTENSION: AVX512EVEX 21127 ISA_SET: AVX512F_512 21128 EXCEPTIONS: AVX512-E4NF 21129 REAL_OPCODE: Y 21130 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21131 PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 21132 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 21133 IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 21134 } 21135 21136 21137 # EMITTING VPERMT2PD (VPERMT2PD-512-1) 21138 { 21139 ICLASS: VPERMT2PD 21140 CPL: 3 21141 CATEGORY: AVX512 21142 EXTENSION: AVX512EVEX 21143 ISA_SET: AVX512F_512 21144 EXCEPTIONS: AVX512-E4NF 21145 REAL_OPCODE: Y 21146 ATTRIBUTES: MASKOP_EVEX 21147 PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 21148 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 21149 IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 21150 } 21151 21152 { 21153 ICLASS: VPERMT2PD 21154 CPL: 3 21155 CATEGORY: AVX512 21156 EXTENSION: AVX512EVEX 21157 ISA_SET: AVX512F_512 21158 EXCEPTIONS: AVX512-E4NF 21159 REAL_OPCODE: Y 21160 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21161 PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 21162 OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 21163 IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 21164 } 21165 21166 21167 # EMITTING VPERMT2PS (VPERMT2PS-512-1) 21168 { 21169 ICLASS: VPERMT2PS 21170 CPL: 3 21171 CATEGORY: AVX512 21172 EXTENSION: AVX512EVEX 21173 ISA_SET: AVX512F_512 21174 EXCEPTIONS: AVX512-E4NF 21175 REAL_OPCODE: Y 21176 ATTRIBUTES: MASKOP_EVEX 21177 PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 21178 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 21179 IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 21180 } 21181 21182 { 21183 ICLASS: VPERMT2PS 21184 CPL: 3 21185 CATEGORY: AVX512 21186 EXTENSION: AVX512EVEX 21187 ISA_SET: AVX512F_512 21188 EXCEPTIONS: AVX512-E4NF 21189 REAL_OPCODE: Y 21190 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21191 PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 21192 OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 21193 IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 21194 } 21195 21196 21197 # EMITTING VPERMT2Q (VPERMT2Q-512-1) 21198 { 21199 ICLASS: VPERMT2Q 21200 CPL: 3 21201 CATEGORY: AVX512 21202 EXTENSION: AVX512EVEX 21203 ISA_SET: AVX512F_512 21204 EXCEPTIONS: AVX512-E4NF 21205 REAL_OPCODE: Y 21206 ATTRIBUTES: MASKOP_EVEX 21207 PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 21208 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 21209 IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 21210 } 21211 21212 { 21213 ICLASS: VPERMT2Q 21214 CPL: 3 21215 CATEGORY: AVX512 21216 EXTENSION: AVX512EVEX 21217 ISA_SET: AVX512F_512 21218 EXCEPTIONS: AVX512-E4NF 21219 REAL_OPCODE: Y 21220 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21221 PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 21222 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 21223 IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 21224 } 21225 21226 21227 # EMITTING VPEXPANDD (VPEXPANDD-512-1) 21228 { 21229 ICLASS: VPEXPANDD 21230 CPL: 3 21231 CATEGORY: EXPAND 21232 EXTENSION: AVX512EVEX 21233 ISA_SET: AVX512F_512 21234 EXCEPTIONS: AVX512-E4 21235 REAL_OPCODE: Y 21236 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 21237 PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() 21238 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 21239 IFORM: VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 21240 } 21241 21242 21243 # EMITTING VPEXPANDD (VPEXPANDD-512-2) 21244 { 21245 ICLASS: VPEXPANDD 21246 CPL: 3 21247 CATEGORY: EXPAND 21248 EXTENSION: AVX512EVEX 21249 ISA_SET: AVX512F_512 21250 EXCEPTIONS: AVX512-E4 21251 REAL_OPCODE: Y 21252 ATTRIBUTES: MASKOP_EVEX 21253 PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 21254 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 21255 IFORM: VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 21256 } 21257 21258 21259 # EMITTING VPEXPANDQ (VPEXPANDQ-512-1) 21260 { 21261 ICLASS: VPEXPANDQ 21262 CPL: 3 21263 CATEGORY: EXPAND 21264 EXTENSION: AVX512EVEX 21265 ISA_SET: AVX512F_512 21266 EXCEPTIONS: AVX512-E4 21267 REAL_OPCODE: Y 21268 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 21269 PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() 21270 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 21271 IFORM: VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 21272 } 21273 21274 21275 # EMITTING VPEXPANDQ (VPEXPANDQ-512-2) 21276 { 21277 ICLASS: VPEXPANDQ 21278 CPL: 3 21279 CATEGORY: EXPAND 21280 EXTENSION: AVX512EVEX 21281 ISA_SET: AVX512F_512 21282 EXCEPTIONS: AVX512-E4 21283 REAL_OPCODE: Y 21284 ATTRIBUTES: MASKOP_EVEX 21285 PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 21286 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 21287 IFORM: VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 21288 } 21289 21290 21291 # EMITTING VPGATHERDD (VPGATHERDD-512-1) 21292 { 21293 ICLASS: VPGATHERDD 21294 CPL: 3 21295 CATEGORY: GATHER 21296 EXTENSION: AVX512EVEX 21297 ISA_SET: AVX512F_512 21298 EXCEPTIONS: AVX512-E12 21299 REAL_OPCODE: Y 21300 ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 21301 PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 21302 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 21303 IFORM: VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 21304 } 21305 21306 21307 # EMITTING VPGATHERDQ (VPGATHERDQ-512-1) 21308 { 21309 ICLASS: VPGATHERDQ 21310 CPL: 3 21311 CATEGORY: GATHER 21312 EXTENSION: AVX512EVEX 21313 ISA_SET: AVX512F_512 21314 EXCEPTIONS: AVX512-E12 21315 REAL_OPCODE: Y 21316 ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 21317 PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 21318 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 21319 IFORM: VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 21320 } 21321 21322 21323 # EMITTING VPGATHERQD (VPGATHERQD-512-1) 21324 { 21325 ICLASS: VPGATHERQD 21326 CPL: 3 21327 CATEGORY: GATHER 21328 EXTENSION: AVX512EVEX 21329 ISA_SET: AVX512F_512 21330 EXCEPTIONS: AVX512-E12 21331 REAL_OPCODE: Y 21332 ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 21333 PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 21334 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 21335 IFORM: VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 21336 } 21337 21338 21339 # EMITTING VPGATHERQQ (VPGATHERQQ-512-1) 21340 { 21341 ICLASS: VPGATHERQQ 21342 CPL: 3 21343 CATEGORY: GATHER 21344 EXTENSION: AVX512EVEX 21345 ISA_SET: AVX512F_512 21346 EXCEPTIONS: AVX512-E12 21347 REAL_OPCODE: Y 21348 ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 21349 PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 21350 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 21351 IFORM: VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 21352 } 21353 21354 21355 # EMITTING VPMAXSD (VPMAXSD-512-1) 21356 { 21357 ICLASS: VPMAXSD 21358 CPL: 3 21359 CATEGORY: AVX512 21360 EXTENSION: AVX512EVEX 21361 ISA_SET: AVX512F_512 21362 EXCEPTIONS: AVX512-E4 21363 REAL_OPCODE: Y 21364 ATTRIBUTES: MASKOP_EVEX 21365 PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 21366 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 21367 IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 21368 } 21369 21370 { 21371 ICLASS: VPMAXSD 21372 CPL: 3 21373 CATEGORY: AVX512 21374 EXTENSION: AVX512EVEX 21375 ISA_SET: AVX512F_512 21376 EXCEPTIONS: AVX512-E4 21377 REAL_OPCODE: Y 21378 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21379 PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 21380 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR 21381 IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 21382 } 21383 21384 21385 # EMITTING VPMAXSQ (VPMAXSQ-512-1) 21386 { 21387 ICLASS: VPMAXSQ 21388 CPL: 3 21389 CATEGORY: AVX512 21390 EXTENSION: AVX512EVEX 21391 ISA_SET: AVX512F_512 21392 EXCEPTIONS: AVX512-E4 21393 REAL_OPCODE: Y 21394 ATTRIBUTES: MASKOP_EVEX 21395 PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 21396 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 21397 IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 21398 } 21399 21400 { 21401 ICLASS: VPMAXSQ 21402 CPL: 3 21403 CATEGORY: AVX512 21404 EXTENSION: AVX512EVEX 21405 ISA_SET: AVX512F_512 21406 EXCEPTIONS: AVX512-E4 21407 REAL_OPCODE: Y 21408 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21409 PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 21410 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR 21411 IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 21412 } 21413 21414 21415 # EMITTING VPMAXUD (VPMAXUD-512-1) 21416 { 21417 ICLASS: VPMAXUD 21418 CPL: 3 21419 CATEGORY: AVX512 21420 EXTENSION: AVX512EVEX 21421 ISA_SET: AVX512F_512 21422 EXCEPTIONS: AVX512-E4 21423 REAL_OPCODE: Y 21424 ATTRIBUTES: MASKOP_EVEX 21425 PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 21426 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 21427 IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 21428 } 21429 21430 { 21431 ICLASS: VPMAXUD 21432 CPL: 3 21433 CATEGORY: AVX512 21434 EXTENSION: AVX512EVEX 21435 ISA_SET: AVX512F_512 21436 EXCEPTIONS: AVX512-E4 21437 REAL_OPCODE: Y 21438 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21439 PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 21440 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 21441 IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 21442 } 21443 21444 21445 # EMITTING VPMAXUQ (VPMAXUQ-512-1) 21446 { 21447 ICLASS: VPMAXUQ 21448 CPL: 3 21449 CATEGORY: AVX512 21450 EXTENSION: AVX512EVEX 21451 ISA_SET: AVX512F_512 21452 EXCEPTIONS: AVX512-E4 21453 REAL_OPCODE: Y 21454 ATTRIBUTES: MASKOP_EVEX 21455 PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 21456 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 21457 IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 21458 } 21459 21460 { 21461 ICLASS: VPMAXUQ 21462 CPL: 3 21463 CATEGORY: AVX512 21464 EXTENSION: AVX512EVEX 21465 ISA_SET: AVX512F_512 21466 EXCEPTIONS: AVX512-E4 21467 REAL_OPCODE: Y 21468 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21469 PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 21470 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 21471 IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 21472 } 21473 21474 21475 # EMITTING VPMINSD (VPMINSD-512-1) 21476 { 21477 ICLASS: VPMINSD 21478 CPL: 3 21479 CATEGORY: AVX512 21480 EXTENSION: AVX512EVEX 21481 ISA_SET: AVX512F_512 21482 EXCEPTIONS: AVX512-E4 21483 REAL_OPCODE: Y 21484 ATTRIBUTES: MASKOP_EVEX 21485 PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 21486 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 21487 IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 21488 } 21489 21490 { 21491 ICLASS: VPMINSD 21492 CPL: 3 21493 CATEGORY: AVX512 21494 EXTENSION: AVX512EVEX 21495 ISA_SET: AVX512F_512 21496 EXCEPTIONS: AVX512-E4 21497 REAL_OPCODE: Y 21498 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21499 PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 21500 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR 21501 IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 21502 } 21503 21504 21505 # EMITTING VPMINSQ (VPMINSQ-512-1) 21506 { 21507 ICLASS: VPMINSQ 21508 CPL: 3 21509 CATEGORY: AVX512 21510 EXTENSION: AVX512EVEX 21511 ISA_SET: AVX512F_512 21512 EXCEPTIONS: AVX512-E4 21513 REAL_OPCODE: Y 21514 ATTRIBUTES: MASKOP_EVEX 21515 PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 21516 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 21517 IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 21518 } 21519 21520 { 21521 ICLASS: VPMINSQ 21522 CPL: 3 21523 CATEGORY: AVX512 21524 EXTENSION: AVX512EVEX 21525 ISA_SET: AVX512F_512 21526 EXCEPTIONS: AVX512-E4 21527 REAL_OPCODE: Y 21528 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21529 PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 21530 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR 21531 IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 21532 } 21533 21534 21535 # EMITTING VPMINUD (VPMINUD-512-1) 21536 { 21537 ICLASS: VPMINUD 21538 CPL: 3 21539 CATEGORY: AVX512 21540 EXTENSION: AVX512EVEX 21541 ISA_SET: AVX512F_512 21542 EXCEPTIONS: AVX512-E4 21543 REAL_OPCODE: Y 21544 ATTRIBUTES: MASKOP_EVEX 21545 PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 21546 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 21547 IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 21548 } 21549 21550 { 21551 ICLASS: VPMINUD 21552 CPL: 3 21553 CATEGORY: AVX512 21554 EXTENSION: AVX512EVEX 21555 ISA_SET: AVX512F_512 21556 EXCEPTIONS: AVX512-E4 21557 REAL_OPCODE: Y 21558 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21559 PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 21560 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 21561 IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 21562 } 21563 21564 21565 # EMITTING VPMINUQ (VPMINUQ-512-1) 21566 { 21567 ICLASS: VPMINUQ 21568 CPL: 3 21569 CATEGORY: AVX512 21570 EXTENSION: AVX512EVEX 21571 ISA_SET: AVX512F_512 21572 EXCEPTIONS: AVX512-E4 21573 REAL_OPCODE: Y 21574 ATTRIBUTES: MASKOP_EVEX 21575 PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 21576 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 21577 IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 21578 } 21579 21580 { 21581 ICLASS: VPMINUQ 21582 CPL: 3 21583 CATEGORY: AVX512 21584 EXTENSION: AVX512EVEX 21585 ISA_SET: AVX512F_512 21586 EXCEPTIONS: AVX512-E4 21587 REAL_OPCODE: Y 21588 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 21589 PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 21590 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 21591 IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 21592 } 21593 21594 21595 # EMITTING VPMOVDB (VPMOVDB-512-1) 21596 { 21597 ICLASS: VPMOVDB 21598 CPL: 3 21599 CATEGORY: DATAXFER 21600 EXTENSION: AVX512EVEX 21601 ISA_SET: AVX512F_512 21602 EXCEPTIONS: AVX512-E6NF 21603 REAL_OPCODE: Y 21604 ATTRIBUTES: MASKOP_EVEX 21605 PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 21606 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 21607 IFORM: VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 21608 } 21609 21610 21611 # EMITTING VPMOVDB (VPMOVDB-512-2) 21612 { 21613 ICLASS: VPMOVDB 21614 CPL: 3 21615 CATEGORY: DATAXFER 21616 EXTENSION: AVX512EVEX 21617 ISA_SET: AVX512F_512 21618 EXCEPTIONS: AVX512-E6 21619 REAL_OPCODE: Y 21620 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 21621 PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 21622 OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 21623 IFORM: VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 21624 } 21625 21626 21627 # EMITTING VPMOVDW (VPMOVDW-512-1) 21628 { 21629 ICLASS: VPMOVDW 21630 CPL: 3 21631 CATEGORY: DATAXFER 21632 EXTENSION: AVX512EVEX 21633 ISA_SET: AVX512F_512 21634 EXCEPTIONS: AVX512-E6NF 21635 REAL_OPCODE: Y 21636 ATTRIBUTES: MASKOP_EVEX 21637 PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 21638 OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 21639 IFORM: VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 21640 } 21641 21642 21643 # EMITTING VPMOVDW (VPMOVDW-512-2) 21644 { 21645 ICLASS: VPMOVDW 21646 CPL: 3 21647 CATEGORY: DATAXFER 21648 EXTENSION: AVX512EVEX 21649 ISA_SET: AVX512F_512 21650 EXCEPTIONS: AVX512-E6 21651 REAL_OPCODE: Y 21652 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 21653 PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 21654 OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 21655 IFORM: VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 21656 } 21657 21658 21659 # EMITTING VPMOVQB (VPMOVQB-512-1) 21660 { 21661 ICLASS: VPMOVQB 21662 CPL: 3 21663 CATEGORY: DATAXFER 21664 EXTENSION: AVX512EVEX 21665 ISA_SET: AVX512F_512 21666 EXCEPTIONS: AVX512-E6NF 21667 REAL_OPCODE: Y 21668 ATTRIBUTES: MASKOP_EVEX 21669 PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 21670 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 21671 IFORM: VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 21672 } 21673 21674 21675 # EMITTING VPMOVQB (VPMOVQB-512-2) 21676 { 21677 ICLASS: VPMOVQB 21678 CPL: 3 21679 CATEGORY: DATAXFER 21680 EXTENSION: AVX512EVEX 21681 ISA_SET: AVX512F_512 21682 EXCEPTIONS: AVX512-E6 21683 REAL_OPCODE: Y 21684 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 21685 PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 21686 OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 21687 IFORM: VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 21688 } 21689 21690 21691 # EMITTING VPMOVQD (VPMOVQD-512-1) 21692 { 21693 ICLASS: VPMOVQD 21694 CPL: 3 21695 CATEGORY: DATAXFER 21696 EXTENSION: AVX512EVEX 21697 ISA_SET: AVX512F_512 21698 EXCEPTIONS: AVX512-E6NF 21699 REAL_OPCODE: Y 21700 ATTRIBUTES: MASKOP_EVEX 21701 PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 21702 OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 21703 IFORM: VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 21704 } 21705 21706 21707 # EMITTING VPMOVQD (VPMOVQD-512-2) 21708 { 21709 ICLASS: VPMOVQD 21710 CPL: 3 21711 CATEGORY: DATAXFER 21712 EXTENSION: AVX512EVEX 21713 ISA_SET: AVX512F_512 21714 EXCEPTIONS: AVX512-E6 21715 REAL_OPCODE: Y 21716 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 21717 PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 21718 OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 21719 IFORM: VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 21720 } 21721 21722 21723 # EMITTING VPMOVQW (VPMOVQW-512-1) 21724 { 21725 ICLASS: VPMOVQW 21726 CPL: 3 21727 CATEGORY: DATAXFER 21728 EXTENSION: AVX512EVEX 21729 ISA_SET: AVX512F_512 21730 EXCEPTIONS: AVX512-E6NF 21731 REAL_OPCODE: Y 21732 ATTRIBUTES: MASKOP_EVEX 21733 PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 21734 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 21735 IFORM: VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 21736 } 21737 21738 21739 # EMITTING VPMOVQW (VPMOVQW-512-2) 21740 { 21741 ICLASS: VPMOVQW 21742 CPL: 3 21743 CATEGORY: DATAXFER 21744 EXTENSION: AVX512EVEX 21745 ISA_SET: AVX512F_512 21746 EXCEPTIONS: AVX512-E6 21747 REAL_OPCODE: Y 21748 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 21749 PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 21750 OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 21751 IFORM: VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 21752 } 21753 21754 21755 # EMITTING VPMOVSDB (VPMOVSDB-512-1) 21756 { 21757 ICLASS: VPMOVSDB 21758 CPL: 3 21759 CATEGORY: DATAXFER 21760 EXTENSION: AVX512EVEX 21761 ISA_SET: AVX512F_512 21762 EXCEPTIONS: AVX512-E6NF 21763 REAL_OPCODE: Y 21764 ATTRIBUTES: MASKOP_EVEX 21765 PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 21766 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 21767 IFORM: VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 21768 } 21769 21770 21771 # EMITTING VPMOVSDB (VPMOVSDB-512-2) 21772 { 21773 ICLASS: VPMOVSDB 21774 CPL: 3 21775 CATEGORY: DATAXFER 21776 EXTENSION: AVX512EVEX 21777 ISA_SET: AVX512F_512 21778 EXCEPTIONS: AVX512-E6 21779 REAL_OPCODE: Y 21780 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 21781 PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 21782 OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 21783 IFORM: VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 21784 } 21785 21786 21787 # EMITTING VPMOVSDW (VPMOVSDW-512-1) 21788 { 21789 ICLASS: VPMOVSDW 21790 CPL: 3 21791 CATEGORY: DATAXFER 21792 EXTENSION: AVX512EVEX 21793 ISA_SET: AVX512F_512 21794 EXCEPTIONS: AVX512-E6NF 21795 REAL_OPCODE: Y 21796 ATTRIBUTES: MASKOP_EVEX 21797 PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 21798 OPERANDS: REG0=YMM_B3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 21799 IFORM: VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 21800 } 21801 21802 21803 # EMITTING VPMOVSDW (VPMOVSDW-512-2) 21804 { 21805 ICLASS: VPMOVSDW 21806 CPL: 3 21807 CATEGORY: DATAXFER 21808 EXTENSION: AVX512EVEX 21809 ISA_SET: AVX512F_512 21810 EXCEPTIONS: AVX512-E6 21811 REAL_OPCODE: Y 21812 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 21813 PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 21814 OPERANDS: MEM0:w:qq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 21815 IFORM: VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 21816 } 21817 21818 21819 # EMITTING VPMOVSQB (VPMOVSQB-512-1) 21820 { 21821 ICLASS: VPMOVSQB 21822 CPL: 3 21823 CATEGORY: DATAXFER 21824 EXTENSION: AVX512EVEX 21825 ISA_SET: AVX512F_512 21826 EXCEPTIONS: AVX512-E6NF 21827 REAL_OPCODE: Y 21828 ATTRIBUTES: MASKOP_EVEX 21829 PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 21830 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 21831 IFORM: VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 21832 } 21833 21834 21835 # EMITTING VPMOVSQB (VPMOVSQB-512-2) 21836 { 21837 ICLASS: VPMOVSQB 21838 CPL: 3 21839 CATEGORY: DATAXFER 21840 EXTENSION: AVX512EVEX 21841 ISA_SET: AVX512F_512 21842 EXCEPTIONS: AVX512-E6 21843 REAL_OPCODE: Y 21844 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 21845 PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 21846 OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 21847 IFORM: VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 21848 } 21849 21850 21851 # EMITTING VPMOVSQD (VPMOVSQD-512-1) 21852 { 21853 ICLASS: VPMOVSQD 21854 CPL: 3 21855 CATEGORY: DATAXFER 21856 EXTENSION: AVX512EVEX 21857 ISA_SET: AVX512F_512 21858 EXCEPTIONS: AVX512-E6NF 21859 REAL_OPCODE: Y 21860 ATTRIBUTES: MASKOP_EVEX 21861 PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 21862 OPERANDS: REG0=YMM_B3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 21863 IFORM: VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 21864 } 21865 21866 21867 # EMITTING VPMOVSQD (VPMOVSQD-512-2) 21868 { 21869 ICLASS: VPMOVSQD 21870 CPL: 3 21871 CATEGORY: DATAXFER 21872 EXTENSION: AVX512EVEX 21873 ISA_SET: AVX512F_512 21874 EXCEPTIONS: AVX512-E6 21875 REAL_OPCODE: Y 21876 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 21877 PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 21878 OPERANDS: MEM0:w:qq:i32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 21879 IFORM: VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 21880 } 21881 21882 21883 # EMITTING VPMOVSQW (VPMOVSQW-512-1) 21884 { 21885 ICLASS: VPMOVSQW 21886 CPL: 3 21887 CATEGORY: DATAXFER 21888 EXTENSION: AVX512EVEX 21889 ISA_SET: AVX512F_512 21890 EXCEPTIONS: AVX512-E6NF 21891 REAL_OPCODE: Y 21892 ATTRIBUTES: MASKOP_EVEX 21893 PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 21894 OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 21895 IFORM: VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 21896 } 21897 21898 21899 # EMITTING VPMOVSQW (VPMOVSQW-512-2) 21900 { 21901 ICLASS: VPMOVSQW 21902 CPL: 3 21903 CATEGORY: DATAXFER 21904 EXTENSION: AVX512EVEX 21905 ISA_SET: AVX512F_512 21906 EXCEPTIONS: AVX512-E6 21907 REAL_OPCODE: Y 21908 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 21909 PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 21910 OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 21911 IFORM: VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 21912 } 21913 21914 21915 # EMITTING VPMOVSXBD (VPMOVSXBD-512-1) 21916 { 21917 ICLASS: VPMOVSXBD 21918 CPL: 3 21919 CATEGORY: DATAXFER 21920 EXTENSION: AVX512EVEX 21921 ISA_SET: AVX512F_512 21922 EXCEPTIONS: AVX512-E5 21923 REAL_OPCODE: Y 21924 ATTRIBUTES: MASKOP_EVEX 21925 PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 21926 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 21927 IFORM: VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 21928 } 21929 21930 { 21931 ICLASS: VPMOVSXBD 21932 CPL: 3 21933 CATEGORY: DATAXFER 21934 EXTENSION: AVX512EVEX 21935 ISA_SET: AVX512F_512 21936 EXCEPTIONS: AVX512-E5 21937 REAL_OPCODE: Y 21938 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 21939 PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() 21940 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 21941 IFORM: VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 21942 } 21943 21944 21945 # EMITTING VPMOVSXBQ (VPMOVSXBQ-512-1) 21946 { 21947 ICLASS: VPMOVSXBQ 21948 CPL: 3 21949 CATEGORY: DATAXFER 21950 EXTENSION: AVX512EVEX 21951 ISA_SET: AVX512F_512 21952 EXCEPTIONS: AVX512-E5 21953 REAL_OPCODE: Y 21954 ATTRIBUTES: MASKOP_EVEX 21955 PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 21956 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 21957 IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 21958 } 21959 21960 { 21961 ICLASS: VPMOVSXBQ 21962 CPL: 3 21963 CATEGORY: DATAXFER 21964 EXTENSION: AVX512EVEX 21965 ISA_SET: AVX512F_512 21966 EXCEPTIONS: AVX512-E5 21967 REAL_OPCODE: Y 21968 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 21969 PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() 21970 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 21971 IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 21972 } 21973 21974 21975 # EMITTING VPMOVSXDQ (VPMOVSXDQ-512-1) 21976 { 21977 ICLASS: VPMOVSXDQ 21978 CPL: 3 21979 CATEGORY: DATAXFER 21980 EXTENSION: AVX512EVEX 21981 ISA_SET: AVX512F_512 21982 EXCEPTIONS: AVX512-E5 21983 REAL_OPCODE: Y 21984 ATTRIBUTES: MASKOP_EVEX 21985 PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 21986 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 21987 IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 21988 } 21989 21990 { 21991 ICLASS: VPMOVSXDQ 21992 CPL: 3 21993 CATEGORY: DATAXFER 21994 EXTENSION: AVX512EVEX 21995 ISA_SET: AVX512F_512 21996 EXCEPTIONS: AVX512-E5 21997 REAL_OPCODE: Y 21998 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 21999 PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() 22000 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 22001 IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 22002 } 22003 22004 22005 # EMITTING VPMOVSXWD (VPMOVSXWD-512-1) 22006 { 22007 ICLASS: VPMOVSXWD 22008 CPL: 3 22009 CATEGORY: DATAXFER 22010 EXTENSION: AVX512EVEX 22011 ISA_SET: AVX512F_512 22012 EXCEPTIONS: AVX512-E5 22013 REAL_OPCODE: Y 22014 ATTRIBUTES: MASKOP_EVEX 22015 PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 22016 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 22017 IFORM: VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 22018 } 22019 22020 { 22021 ICLASS: VPMOVSXWD 22022 CPL: 3 22023 CATEGORY: DATAXFER 22024 EXTENSION: AVX512EVEX 22025 ISA_SET: AVX512F_512 22026 EXCEPTIONS: AVX512-E5 22027 REAL_OPCODE: Y 22028 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 22029 PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 22030 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 22031 IFORM: VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 22032 } 22033 22034 22035 # EMITTING VPMOVSXWQ (VPMOVSXWQ-512-1) 22036 { 22037 ICLASS: VPMOVSXWQ 22038 CPL: 3 22039 CATEGORY: DATAXFER 22040 EXTENSION: AVX512EVEX 22041 ISA_SET: AVX512F_512 22042 EXCEPTIONS: AVX512-E5 22043 REAL_OPCODE: Y 22044 ATTRIBUTES: MASKOP_EVEX 22045 PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 22046 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 22047 IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 22048 } 22049 22050 { 22051 ICLASS: VPMOVSXWQ 22052 CPL: 3 22053 CATEGORY: DATAXFER 22054 EXTENSION: AVX512EVEX 22055 ISA_SET: AVX512F_512 22056 EXCEPTIONS: AVX512-E5 22057 REAL_OPCODE: Y 22058 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 22059 PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() 22060 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 22061 IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 22062 } 22063 22064 22065 # EMITTING VPMOVUSDB (VPMOVUSDB-512-1) 22066 { 22067 ICLASS: VPMOVUSDB 22068 CPL: 3 22069 CATEGORY: DATAXFER 22070 EXTENSION: AVX512EVEX 22071 ISA_SET: AVX512F_512 22072 EXCEPTIONS: AVX512-E6NF 22073 REAL_OPCODE: Y 22074 ATTRIBUTES: MASKOP_EVEX 22075 PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 22076 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 22077 IFORM: VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 22078 } 22079 22080 22081 # EMITTING VPMOVUSDB (VPMOVUSDB-512-2) 22082 { 22083 ICLASS: VPMOVUSDB 22084 CPL: 3 22085 CATEGORY: DATAXFER 22086 EXTENSION: AVX512EVEX 22087 ISA_SET: AVX512F_512 22088 EXCEPTIONS: AVX512-E6 22089 REAL_OPCODE: Y 22090 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 22091 PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 22092 OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 22093 IFORM: VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 22094 } 22095 22096 22097 # EMITTING VPMOVUSDW (VPMOVUSDW-512-1) 22098 { 22099 ICLASS: VPMOVUSDW 22100 CPL: 3 22101 CATEGORY: DATAXFER 22102 EXTENSION: AVX512EVEX 22103 ISA_SET: AVX512F_512 22104 EXCEPTIONS: AVX512-E6NF 22105 REAL_OPCODE: Y 22106 ATTRIBUTES: MASKOP_EVEX 22107 PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 22108 OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 22109 IFORM: VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 22110 } 22111 22112 22113 # EMITTING VPMOVUSDW (VPMOVUSDW-512-2) 22114 { 22115 ICLASS: VPMOVUSDW 22116 CPL: 3 22117 CATEGORY: DATAXFER 22118 EXTENSION: AVX512EVEX 22119 ISA_SET: AVX512F_512 22120 EXCEPTIONS: AVX512-E6 22121 REAL_OPCODE: Y 22122 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 22123 PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 22124 OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 22125 IFORM: VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 22126 } 22127 22128 22129 # EMITTING VPMOVUSQB (VPMOVUSQB-512-1) 22130 { 22131 ICLASS: VPMOVUSQB 22132 CPL: 3 22133 CATEGORY: DATAXFER 22134 EXTENSION: AVX512EVEX 22135 ISA_SET: AVX512F_512 22136 EXCEPTIONS: AVX512-E6NF 22137 REAL_OPCODE: Y 22138 ATTRIBUTES: MASKOP_EVEX 22139 PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 22140 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 22141 IFORM: VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 22142 } 22143 22144 22145 # EMITTING VPMOVUSQB (VPMOVUSQB-512-2) 22146 { 22147 ICLASS: VPMOVUSQB 22148 CPL: 3 22149 CATEGORY: DATAXFER 22150 EXTENSION: AVX512EVEX 22151 ISA_SET: AVX512F_512 22152 EXCEPTIONS: AVX512-E6 22153 REAL_OPCODE: Y 22154 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 22155 PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 22156 OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 22157 IFORM: VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 22158 } 22159 22160 22161 # EMITTING VPMOVUSQD (VPMOVUSQD-512-1) 22162 { 22163 ICLASS: VPMOVUSQD 22164 CPL: 3 22165 CATEGORY: DATAXFER 22166 EXTENSION: AVX512EVEX 22167 ISA_SET: AVX512F_512 22168 EXCEPTIONS: AVX512-E6NF 22169 REAL_OPCODE: Y 22170 ATTRIBUTES: MASKOP_EVEX 22171 PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 22172 OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 22173 IFORM: VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 22174 } 22175 22176 22177 # EMITTING VPMOVUSQD (VPMOVUSQD-512-2) 22178 { 22179 ICLASS: VPMOVUSQD 22180 CPL: 3 22181 CATEGORY: DATAXFER 22182 EXTENSION: AVX512EVEX 22183 ISA_SET: AVX512F_512 22184 EXCEPTIONS: AVX512-E6 22185 REAL_OPCODE: Y 22186 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 22187 PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 22188 OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 22189 IFORM: VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 22190 } 22191 22192 22193 # EMITTING VPMOVUSQW (VPMOVUSQW-512-1) 22194 { 22195 ICLASS: VPMOVUSQW 22196 CPL: 3 22197 CATEGORY: DATAXFER 22198 EXTENSION: AVX512EVEX 22199 ISA_SET: AVX512F_512 22200 EXCEPTIONS: AVX512-E6NF 22201 REAL_OPCODE: Y 22202 ATTRIBUTES: MASKOP_EVEX 22203 PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 22204 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 22205 IFORM: VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 22206 } 22207 22208 22209 # EMITTING VPMOVUSQW (VPMOVUSQW-512-2) 22210 { 22211 ICLASS: VPMOVUSQW 22212 CPL: 3 22213 CATEGORY: DATAXFER 22214 EXTENSION: AVX512EVEX 22215 ISA_SET: AVX512F_512 22216 EXCEPTIONS: AVX512-E6 22217 REAL_OPCODE: Y 22218 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 22219 PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 22220 OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 22221 IFORM: VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 22222 } 22223 22224 22225 # EMITTING VPMOVZXBD (VPMOVZXBD-512-1) 22226 { 22227 ICLASS: VPMOVZXBD 22228 CPL: 3 22229 CATEGORY: DATAXFER 22230 EXTENSION: AVX512EVEX 22231 ISA_SET: AVX512F_512 22232 EXCEPTIONS: AVX512-E5 22233 REAL_OPCODE: Y 22234 ATTRIBUTES: MASKOP_EVEX 22235 PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 22236 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 22237 IFORM: VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 22238 } 22239 22240 { 22241 ICLASS: VPMOVZXBD 22242 CPL: 3 22243 CATEGORY: DATAXFER 22244 EXTENSION: AVX512EVEX 22245 ISA_SET: AVX512F_512 22246 EXCEPTIONS: AVX512-E5 22247 REAL_OPCODE: Y 22248 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 22249 PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() 22250 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 22251 IFORM: VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 22252 } 22253 22254 22255 # EMITTING VPMOVZXBQ (VPMOVZXBQ-512-1) 22256 { 22257 ICLASS: VPMOVZXBQ 22258 CPL: 3 22259 CATEGORY: DATAXFER 22260 EXTENSION: AVX512EVEX 22261 ISA_SET: AVX512F_512 22262 EXCEPTIONS: AVX512-E5 22263 REAL_OPCODE: Y 22264 ATTRIBUTES: MASKOP_EVEX 22265 PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 22266 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 22267 IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 22268 } 22269 22270 { 22271 ICLASS: VPMOVZXBQ 22272 CPL: 3 22273 CATEGORY: DATAXFER 22274 EXTENSION: AVX512EVEX 22275 ISA_SET: AVX512F_512 22276 EXCEPTIONS: AVX512-E5 22277 REAL_OPCODE: Y 22278 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 22279 PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() 22280 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 22281 IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 22282 } 22283 22284 22285 # EMITTING VPMOVZXDQ (VPMOVZXDQ-512-1) 22286 { 22287 ICLASS: VPMOVZXDQ 22288 CPL: 3 22289 CATEGORY: DATAXFER 22290 EXTENSION: AVX512EVEX 22291 ISA_SET: AVX512F_512 22292 EXCEPTIONS: AVX512-E5 22293 REAL_OPCODE: Y 22294 ATTRIBUTES: MASKOP_EVEX 22295 PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 22296 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 22297 IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 22298 } 22299 22300 { 22301 ICLASS: VPMOVZXDQ 22302 CPL: 3 22303 CATEGORY: DATAXFER 22304 EXTENSION: AVX512EVEX 22305 ISA_SET: AVX512F_512 22306 EXCEPTIONS: AVX512-E5 22307 REAL_OPCODE: Y 22308 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 22309 PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() 22310 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 22311 IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 22312 } 22313 22314 22315 # EMITTING VPMOVZXWD (VPMOVZXWD-512-1) 22316 { 22317 ICLASS: VPMOVZXWD 22318 CPL: 3 22319 CATEGORY: DATAXFER 22320 EXTENSION: AVX512EVEX 22321 ISA_SET: AVX512F_512 22322 EXCEPTIONS: AVX512-E5 22323 REAL_OPCODE: Y 22324 ATTRIBUTES: MASKOP_EVEX 22325 PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 22326 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 22327 IFORM: VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 22328 } 22329 22330 { 22331 ICLASS: VPMOVZXWD 22332 CPL: 3 22333 CATEGORY: DATAXFER 22334 EXTENSION: AVX512EVEX 22335 ISA_SET: AVX512F_512 22336 EXCEPTIONS: AVX512-E5 22337 REAL_OPCODE: Y 22338 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 22339 PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 22340 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 22341 IFORM: VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 22342 } 22343 22344 22345 # EMITTING VPMOVZXWQ (VPMOVZXWQ-512-1) 22346 { 22347 ICLASS: VPMOVZXWQ 22348 CPL: 3 22349 CATEGORY: DATAXFER 22350 EXTENSION: AVX512EVEX 22351 ISA_SET: AVX512F_512 22352 EXCEPTIONS: AVX512-E5 22353 REAL_OPCODE: Y 22354 ATTRIBUTES: MASKOP_EVEX 22355 PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 22356 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 22357 IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 22358 } 22359 22360 { 22361 ICLASS: VPMOVZXWQ 22362 CPL: 3 22363 CATEGORY: DATAXFER 22364 EXTENSION: AVX512EVEX 22365 ISA_SET: AVX512F_512 22366 EXCEPTIONS: AVX512-E5 22367 REAL_OPCODE: Y 22368 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 22369 PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() 22370 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 22371 IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 22372 } 22373 22374 22375 # EMITTING VPMULDQ (VPMULDQ-512-1) 22376 { 22377 ICLASS: VPMULDQ 22378 CPL: 3 22379 CATEGORY: AVX512 22380 EXTENSION: AVX512EVEX 22381 ISA_SET: AVX512F_512 22382 EXCEPTIONS: AVX512-E4 22383 REAL_OPCODE: Y 22384 COMMENT: Strange instruction that uses 32b of each 64b input element 22385 ATTRIBUTES: MASKOP_EVEX 22386 PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 22387 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 22388 IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 22389 } 22390 22391 { 22392 ICLASS: VPMULDQ 22393 CPL: 3 22394 CATEGORY: AVX512 22395 EXTENSION: AVX512EVEX 22396 ISA_SET: AVX512F_512 22397 EXCEPTIONS: AVX512-E4 22398 REAL_OPCODE: Y 22399 COMMENT: Strange instruction that uses 32b of each 64b input element 22400 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX 22401 PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 22402 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR 22403 IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 22404 } 22405 22406 22407 # EMITTING VPMULLD (VPMULLD-512-1) 22408 { 22409 ICLASS: VPMULLD 22410 CPL: 3 22411 CATEGORY: AVX512 22412 EXTENSION: AVX512EVEX 22413 ISA_SET: AVX512F_512 22414 EXCEPTIONS: AVX512-E4 22415 REAL_OPCODE: Y 22416 ATTRIBUTES: MASKOP_EVEX 22417 PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 22418 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 22419 IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 22420 } 22421 22422 { 22423 ICLASS: VPMULLD 22424 CPL: 3 22425 CATEGORY: AVX512 22426 EXTENSION: AVX512EVEX 22427 ISA_SET: AVX512F_512 22428 EXCEPTIONS: AVX512-E4 22429 REAL_OPCODE: Y 22430 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22431 PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 22432 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 22433 IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 22434 } 22435 22436 22437 # EMITTING VPMULUDQ (VPMULUDQ-512-1) 22438 { 22439 ICLASS: VPMULUDQ 22440 CPL: 3 22441 CATEGORY: AVX512 22442 EXTENSION: AVX512EVEX 22443 ISA_SET: AVX512F_512 22444 EXCEPTIONS: AVX512-E4 22445 REAL_OPCODE: Y 22446 COMMENT: Strange instruction that uses 32b of each 64b input element 22447 ATTRIBUTES: MASKOP_EVEX 22448 PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 22449 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 22450 IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 22451 } 22452 22453 { 22454 ICLASS: VPMULUDQ 22455 CPL: 3 22456 CATEGORY: AVX512 22457 EXTENSION: AVX512EVEX 22458 ISA_SET: AVX512F_512 22459 EXCEPTIONS: AVX512-E4 22460 REAL_OPCODE: Y 22461 COMMENT: Strange instruction that uses 32b of each 64b input element 22462 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX 22463 PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 22464 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 22465 IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 22466 } 22467 22468 22469 # EMITTING VPORD (VPORD-512-1) 22470 { 22471 ICLASS: VPORD 22472 CPL: 3 22473 CATEGORY: LOGICAL 22474 EXTENSION: AVX512EVEX 22475 ISA_SET: AVX512F_512 22476 EXCEPTIONS: AVX512-E4 22477 REAL_OPCODE: Y 22478 ATTRIBUTES: MASKOP_EVEX 22479 PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 22480 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 22481 IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 22482 } 22483 22484 { 22485 ICLASS: VPORD 22486 CPL: 3 22487 CATEGORY: LOGICAL 22488 EXTENSION: AVX512EVEX 22489 ISA_SET: AVX512F_512 22490 EXCEPTIONS: AVX512-E4 22491 REAL_OPCODE: Y 22492 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22493 PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 22494 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 22495 IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 22496 } 22497 22498 22499 # EMITTING VPORQ (VPORQ-512-1) 22500 { 22501 ICLASS: VPORQ 22502 CPL: 3 22503 CATEGORY: LOGICAL 22504 EXTENSION: AVX512EVEX 22505 ISA_SET: AVX512F_512 22506 EXCEPTIONS: AVX512-E4 22507 REAL_OPCODE: Y 22508 ATTRIBUTES: MASKOP_EVEX 22509 PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 22510 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 22511 IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 22512 } 22513 22514 { 22515 ICLASS: VPORQ 22516 CPL: 3 22517 CATEGORY: LOGICAL 22518 EXTENSION: AVX512EVEX 22519 ISA_SET: AVX512F_512 22520 EXCEPTIONS: AVX512-E4 22521 REAL_OPCODE: Y 22522 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22523 PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 22524 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 22525 IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 22526 } 22527 22528 22529 # EMITTING VPROLD (VPROLD-512-1) 22530 { 22531 ICLASS: VPROLD 22532 CPL: 3 22533 CATEGORY: AVX512 22534 EXTENSION: AVX512EVEX 22535 ISA_SET: AVX512F_512 22536 EXCEPTIONS: AVX512-E4 22537 REAL_OPCODE: Y 22538 ATTRIBUTES: MASKOP_EVEX 22539 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W0 UIMM8() 22540 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b 22541 IFORM: VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 22542 } 22543 22544 { 22545 ICLASS: VPROLD 22546 CPL: 3 22547 CATEGORY: AVX512 22548 EXTENSION: AVX512EVEX 22549 ISA_SET: AVX512F_512 22550 EXCEPTIONS: AVX512-E4 22551 REAL_OPCODE: Y 22552 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22553 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 22554 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 22555 IFORM: VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 22556 } 22557 22558 22559 # EMITTING VPROLQ (VPROLQ-512-1) 22560 { 22561 ICLASS: VPROLQ 22562 CPL: 3 22563 CATEGORY: AVX512 22564 EXTENSION: AVX512EVEX 22565 ISA_SET: AVX512F_512 22566 EXCEPTIONS: AVX512-E4 22567 REAL_OPCODE: Y 22568 ATTRIBUTES: MASKOP_EVEX 22569 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W1 UIMM8() 22570 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b 22571 IFORM: VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 22572 } 22573 22574 { 22575 ICLASS: VPROLQ 22576 CPL: 3 22577 CATEGORY: AVX512 22578 EXTENSION: AVX512EVEX 22579 ISA_SET: AVX512F_512 22580 EXCEPTIONS: AVX512-E4 22581 REAL_OPCODE: Y 22582 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22583 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 22584 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 22585 IFORM: VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 22586 } 22587 22588 22589 # EMITTING VPROLVD (VPROLVD-512-1) 22590 { 22591 ICLASS: VPROLVD 22592 CPL: 3 22593 CATEGORY: AVX512 22594 EXTENSION: AVX512EVEX 22595 ISA_SET: AVX512F_512 22596 EXCEPTIONS: AVX512-E4 22597 REAL_OPCODE: Y 22598 ATTRIBUTES: MASKOP_EVEX 22599 PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 22600 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 22601 IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 22602 } 22603 22604 { 22605 ICLASS: VPROLVD 22606 CPL: 3 22607 CATEGORY: AVX512 22608 EXTENSION: AVX512EVEX 22609 ISA_SET: AVX512F_512 22610 EXCEPTIONS: AVX512-E4 22611 REAL_OPCODE: Y 22612 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22613 PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 22614 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 22615 IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 22616 } 22617 22618 22619 # EMITTING VPROLVQ (VPROLVQ-512-1) 22620 { 22621 ICLASS: VPROLVQ 22622 CPL: 3 22623 CATEGORY: AVX512 22624 EXTENSION: AVX512EVEX 22625 ISA_SET: AVX512F_512 22626 EXCEPTIONS: AVX512-E4 22627 REAL_OPCODE: Y 22628 ATTRIBUTES: MASKOP_EVEX 22629 PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 22630 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 22631 IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 22632 } 22633 22634 { 22635 ICLASS: VPROLVQ 22636 CPL: 3 22637 CATEGORY: AVX512 22638 EXTENSION: AVX512EVEX 22639 ISA_SET: AVX512F_512 22640 EXCEPTIONS: AVX512-E4 22641 REAL_OPCODE: Y 22642 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22643 PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 22644 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 22645 IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 22646 } 22647 22648 22649 # EMITTING VPRORD (VPRORD-512-1) 22650 { 22651 ICLASS: VPRORD 22652 CPL: 3 22653 CATEGORY: AVX512 22654 EXTENSION: AVX512EVEX 22655 ISA_SET: AVX512F_512 22656 EXCEPTIONS: AVX512-E4 22657 REAL_OPCODE: Y 22658 ATTRIBUTES: MASKOP_EVEX 22659 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W0 UIMM8() 22660 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b 22661 IFORM: VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 22662 } 22663 22664 { 22665 ICLASS: VPRORD 22666 CPL: 3 22667 CATEGORY: AVX512 22668 EXTENSION: AVX512EVEX 22669 ISA_SET: AVX512F_512 22670 EXCEPTIONS: AVX512-E4 22671 REAL_OPCODE: Y 22672 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22673 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 22674 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 22675 IFORM: VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 22676 } 22677 22678 22679 # EMITTING VPRORQ (VPRORQ-512-1) 22680 { 22681 ICLASS: VPRORQ 22682 CPL: 3 22683 CATEGORY: AVX512 22684 EXTENSION: AVX512EVEX 22685 ISA_SET: AVX512F_512 22686 EXCEPTIONS: AVX512-E4 22687 REAL_OPCODE: Y 22688 ATTRIBUTES: MASKOP_EVEX 22689 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W1 UIMM8() 22690 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b 22691 IFORM: VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 22692 } 22693 22694 { 22695 ICLASS: VPRORQ 22696 CPL: 3 22697 CATEGORY: AVX512 22698 EXTENSION: AVX512EVEX 22699 ISA_SET: AVX512F_512 22700 EXCEPTIONS: AVX512-E4 22701 REAL_OPCODE: Y 22702 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22703 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 22704 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 22705 IFORM: VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 22706 } 22707 22708 22709 # EMITTING VPRORVD (VPRORVD-512-1) 22710 { 22711 ICLASS: VPRORVD 22712 CPL: 3 22713 CATEGORY: AVX512 22714 EXTENSION: AVX512EVEX 22715 ISA_SET: AVX512F_512 22716 EXCEPTIONS: AVX512-E4 22717 REAL_OPCODE: Y 22718 ATTRIBUTES: MASKOP_EVEX 22719 PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 22720 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 22721 IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 22722 } 22723 22724 { 22725 ICLASS: VPRORVD 22726 CPL: 3 22727 CATEGORY: AVX512 22728 EXTENSION: AVX512EVEX 22729 ISA_SET: AVX512F_512 22730 EXCEPTIONS: AVX512-E4 22731 REAL_OPCODE: Y 22732 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22733 PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 22734 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 22735 IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 22736 } 22737 22738 22739 # EMITTING VPRORVQ (VPRORVQ-512-1) 22740 { 22741 ICLASS: VPRORVQ 22742 CPL: 3 22743 CATEGORY: AVX512 22744 EXTENSION: AVX512EVEX 22745 ISA_SET: AVX512F_512 22746 EXCEPTIONS: AVX512-E4 22747 REAL_OPCODE: Y 22748 ATTRIBUTES: MASKOP_EVEX 22749 PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 22750 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 22751 IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 22752 } 22753 22754 { 22755 ICLASS: VPRORVQ 22756 CPL: 3 22757 CATEGORY: AVX512 22758 EXTENSION: AVX512EVEX 22759 ISA_SET: AVX512F_512 22760 EXCEPTIONS: AVX512-E4 22761 REAL_OPCODE: Y 22762 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22763 PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 22764 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 22765 IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 22766 } 22767 22768 22769 # EMITTING VPSCATTERDD (VPSCATTERDD-512-1) 22770 { 22771 ICLASS: VPSCATTERDD 22772 CPL: 3 22773 CATEGORY: SCATTER 22774 EXTENSION: AVX512EVEX 22775 ISA_SET: AVX512F_512 22776 EXCEPTIONS: AVX512-E12 22777 REAL_OPCODE: Y 22778 ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 22779 PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 22780 OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu32 22781 IFORM: VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 22782 } 22783 22784 22785 # EMITTING VPSCATTERDQ (VPSCATTERDQ-512-1) 22786 { 22787 ICLASS: VPSCATTERDQ 22788 CPL: 3 22789 CATEGORY: SCATTER 22790 EXTENSION: AVX512EVEX 22791 ISA_SET: AVX512F_512 22792 EXCEPTIONS: AVX512-E12 22793 REAL_OPCODE: Y 22794 ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 22795 PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 22796 OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 22797 IFORM: VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 22798 } 22799 22800 22801 # EMITTING VPSCATTERQD (VPSCATTERQD-512-1) 22802 { 22803 ICLASS: VPSCATTERQD 22804 CPL: 3 22805 CATEGORY: SCATTER 22806 EXTENSION: AVX512EVEX 22807 ISA_SET: AVX512F_512 22808 EXCEPTIONS: AVX512-E12 22809 REAL_OPCODE: Y 22810 ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 22811 PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 22812 OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 22813 IFORM: VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 22814 } 22815 22816 22817 # EMITTING VPSCATTERQQ (VPSCATTERQQ-512-1) 22818 { 22819 ICLASS: VPSCATTERQQ 22820 CPL: 3 22821 CATEGORY: SCATTER 22822 EXTENSION: AVX512EVEX 22823 ISA_SET: AVX512F_512 22824 EXCEPTIONS: AVX512-E12 22825 REAL_OPCODE: Y 22826 ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 22827 PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 22828 OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 22829 IFORM: VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 22830 } 22831 22832 22833 # EMITTING VPSHUFD (VPSHUFD-512-1) 22834 { 22835 ICLASS: VPSHUFD 22836 CPL: 3 22837 CATEGORY: AVX512 22838 EXTENSION: AVX512EVEX 22839 ISA_SET: AVX512F_512 22840 EXCEPTIONS: AVX512-E4NF 22841 REAL_OPCODE: Y 22842 ATTRIBUTES: MASKOP_EVEX 22843 PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 22844 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b 22845 IFORM: VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 22846 } 22847 22848 { 22849 ICLASS: VPSHUFD 22850 CPL: 3 22851 CATEGORY: AVX512 22852 EXTENSION: AVX512EVEX 22853 ISA_SET: AVX512F_512 22854 EXCEPTIONS: AVX512-E4NF 22855 REAL_OPCODE: Y 22856 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22857 PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 22858 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 22859 IFORM: VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 22860 } 22861 22862 22863 # EMITTING VPSLLD (VPSLLD-512-1) 22864 { 22865 ICLASS: VPSLLD 22866 CPL: 3 22867 CATEGORY: AVX512 22868 EXTENSION: AVX512EVEX 22869 ISA_SET: AVX512F_512 22870 EXCEPTIONS: AVX512-E4NF 22871 REAL_OPCODE: Y 22872 ATTRIBUTES: MASKOP_EVEX 22873 PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 22874 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 22875 IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 22876 } 22877 22878 { 22879 ICLASS: VPSLLD 22880 CPL: 3 22881 CATEGORY: AVX512 22882 EXTENSION: AVX512EVEX 22883 ISA_SET: AVX512F_512 22884 EXCEPTIONS: AVX512-E4NF 22885 REAL_OPCODE: Y 22886 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 22887 PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() 22888 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 22889 IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 22890 } 22891 22892 22893 # EMITTING VPSLLD (VPSLLD-512-2) 22894 { 22895 ICLASS: VPSLLD 22896 CPL: 3 22897 CATEGORY: AVX512 22898 EXTENSION: AVX512EVEX 22899 ISA_SET: AVX512F_512 22900 EXCEPTIONS: AVX512-E4 22901 REAL_OPCODE: Y 22902 ATTRIBUTES: MASKOP_EVEX 22903 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W0 UIMM8() 22904 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b 22905 IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 22906 } 22907 22908 { 22909 ICLASS: VPSLLD 22910 CPL: 3 22911 CATEGORY: AVX512 22912 EXTENSION: AVX512EVEX 22913 ISA_SET: AVX512F_512 22914 EXCEPTIONS: AVX512-E4 22915 REAL_OPCODE: Y 22916 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22917 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 22918 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 22919 IFORM: VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 22920 } 22921 22922 22923 # EMITTING VPSLLQ (VPSLLQ-512-1) 22924 { 22925 ICLASS: VPSLLQ 22926 CPL: 3 22927 CATEGORY: AVX512 22928 EXTENSION: AVX512EVEX 22929 ISA_SET: AVX512F_512 22930 EXCEPTIONS: AVX512-E4NF 22931 REAL_OPCODE: Y 22932 ATTRIBUTES: MASKOP_EVEX 22933 PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 22934 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 22935 IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 22936 } 22937 22938 { 22939 ICLASS: VPSLLQ 22940 CPL: 3 22941 CATEGORY: AVX512 22942 EXTENSION: AVX512EVEX 22943 ISA_SET: AVX512F_512 22944 EXCEPTIONS: AVX512-E4NF 22945 REAL_OPCODE: Y 22946 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 22947 PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() 22948 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 22949 IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 22950 } 22951 22952 22953 # EMITTING VPSLLQ (VPSLLQ-512-2) 22954 { 22955 ICLASS: VPSLLQ 22956 CPL: 3 22957 CATEGORY: AVX512 22958 EXTENSION: AVX512EVEX 22959 ISA_SET: AVX512F_512 22960 EXCEPTIONS: AVX512-E4 22961 REAL_OPCODE: Y 22962 ATTRIBUTES: MASKOP_EVEX 22963 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W1 UIMM8() 22964 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b 22965 IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 22966 } 22967 22968 { 22969 ICLASS: VPSLLQ 22970 CPL: 3 22971 CATEGORY: AVX512 22972 EXTENSION: AVX512EVEX 22973 ISA_SET: AVX512F_512 22974 EXCEPTIONS: AVX512-E4 22975 REAL_OPCODE: Y 22976 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 22977 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 22978 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 22979 IFORM: VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 22980 } 22981 22982 22983 # EMITTING VPSLLVD (VPSLLVD-512-1) 22984 { 22985 ICLASS: VPSLLVD 22986 CPL: 3 22987 CATEGORY: AVX512 22988 EXTENSION: AVX512EVEX 22989 ISA_SET: AVX512F_512 22990 EXCEPTIONS: AVX512-E4 22991 REAL_OPCODE: Y 22992 ATTRIBUTES: MASKOP_EVEX 22993 PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 22994 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 22995 IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 22996 } 22997 22998 { 22999 ICLASS: VPSLLVD 23000 CPL: 3 23001 CATEGORY: AVX512 23002 EXTENSION: AVX512EVEX 23003 ISA_SET: AVX512F_512 23004 EXCEPTIONS: AVX512-E4 23005 REAL_OPCODE: Y 23006 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23007 PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 23008 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 23009 IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 23010 } 23011 23012 23013 # EMITTING VPSLLVQ (VPSLLVQ-512-1) 23014 { 23015 ICLASS: VPSLLVQ 23016 CPL: 3 23017 CATEGORY: AVX512 23018 EXTENSION: AVX512EVEX 23019 ISA_SET: AVX512F_512 23020 EXCEPTIONS: AVX512-E4 23021 REAL_OPCODE: Y 23022 ATTRIBUTES: MASKOP_EVEX 23023 PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 23024 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 23025 IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 23026 } 23027 23028 { 23029 ICLASS: VPSLLVQ 23030 CPL: 3 23031 CATEGORY: AVX512 23032 EXTENSION: AVX512EVEX 23033 ISA_SET: AVX512F_512 23034 EXCEPTIONS: AVX512-E4 23035 REAL_OPCODE: Y 23036 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23037 PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 23038 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 23039 IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 23040 } 23041 23042 23043 # EMITTING VPSRAD (VPSRAD-512-1) 23044 { 23045 ICLASS: VPSRAD 23046 CPL: 3 23047 CATEGORY: AVX512 23048 EXTENSION: AVX512EVEX 23049 ISA_SET: AVX512F_512 23050 EXCEPTIONS: AVX512-E4NF 23051 REAL_OPCODE: Y 23052 ATTRIBUTES: MASKOP_EVEX 23053 PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 23054 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 23055 IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 23056 } 23057 23058 { 23059 ICLASS: VPSRAD 23060 CPL: 3 23061 CATEGORY: AVX512 23062 EXTENSION: AVX512EVEX 23063 ISA_SET: AVX512F_512 23064 EXCEPTIONS: AVX512-E4NF 23065 REAL_OPCODE: Y 23066 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 23067 PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() 23068 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 23069 IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 23070 } 23071 23072 23073 # EMITTING VPSRAD (VPSRAD-512-2) 23074 { 23075 ICLASS: VPSRAD 23076 CPL: 3 23077 CATEGORY: AVX512 23078 EXTENSION: AVX512EVEX 23079 ISA_SET: AVX512F_512 23080 EXCEPTIONS: AVX512-E4 23081 REAL_OPCODE: Y 23082 ATTRIBUTES: MASKOP_EVEX 23083 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W0 UIMM8() 23084 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b 23085 IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 23086 } 23087 23088 { 23089 ICLASS: VPSRAD 23090 CPL: 3 23091 CATEGORY: AVX512 23092 EXTENSION: AVX512EVEX 23093 ISA_SET: AVX512F_512 23094 EXCEPTIONS: AVX512-E4 23095 REAL_OPCODE: Y 23096 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23097 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 23098 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 23099 IFORM: VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 23100 } 23101 23102 23103 # EMITTING VPSRAQ (VPSRAQ-512-1) 23104 { 23105 ICLASS: VPSRAQ 23106 CPL: 3 23107 CATEGORY: AVX512 23108 EXTENSION: AVX512EVEX 23109 ISA_SET: AVX512F_512 23110 EXCEPTIONS: AVX512-E4NF 23111 REAL_OPCODE: Y 23112 ATTRIBUTES: MASKOP_EVEX 23113 PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 23114 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 23115 IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 23116 } 23117 23118 { 23119 ICLASS: VPSRAQ 23120 CPL: 3 23121 CATEGORY: AVX512 23122 EXTENSION: AVX512EVEX 23123 ISA_SET: AVX512F_512 23124 EXCEPTIONS: AVX512-E4NF 23125 REAL_OPCODE: Y 23126 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 23127 PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() 23128 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 23129 IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 23130 } 23131 23132 23133 # EMITTING VPSRAQ (VPSRAQ-512-2) 23134 { 23135 ICLASS: VPSRAQ 23136 CPL: 3 23137 CATEGORY: AVX512 23138 EXTENSION: AVX512EVEX 23139 ISA_SET: AVX512F_512 23140 EXCEPTIONS: AVX512-E4 23141 REAL_OPCODE: Y 23142 ATTRIBUTES: MASKOP_EVEX 23143 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W1 UIMM8() 23144 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b 23145 IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 23146 } 23147 23148 { 23149 ICLASS: VPSRAQ 23150 CPL: 3 23151 CATEGORY: AVX512 23152 EXTENSION: AVX512EVEX 23153 ISA_SET: AVX512F_512 23154 EXCEPTIONS: AVX512-E4 23155 REAL_OPCODE: Y 23156 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23157 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 23158 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 23159 IFORM: VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 23160 } 23161 23162 23163 # EMITTING VPSRAVD (VPSRAVD-512-1) 23164 { 23165 ICLASS: VPSRAVD 23166 CPL: 3 23167 CATEGORY: AVX512 23168 EXTENSION: AVX512EVEX 23169 ISA_SET: AVX512F_512 23170 EXCEPTIONS: AVX512-E4 23171 REAL_OPCODE: Y 23172 ATTRIBUTES: MASKOP_EVEX 23173 PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 23174 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 23175 IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 23176 } 23177 23178 { 23179 ICLASS: VPSRAVD 23180 CPL: 3 23181 CATEGORY: AVX512 23182 EXTENSION: AVX512EVEX 23183 ISA_SET: AVX512F_512 23184 EXCEPTIONS: AVX512-E4 23185 REAL_OPCODE: Y 23186 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23187 PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 23188 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 23189 IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 23190 } 23191 23192 23193 # EMITTING VPSRAVQ (VPSRAVQ-512-1) 23194 { 23195 ICLASS: VPSRAVQ 23196 CPL: 3 23197 CATEGORY: AVX512 23198 EXTENSION: AVX512EVEX 23199 ISA_SET: AVX512F_512 23200 EXCEPTIONS: AVX512-E4 23201 REAL_OPCODE: Y 23202 ATTRIBUTES: MASKOP_EVEX 23203 PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 23204 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 23205 IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 23206 } 23207 23208 { 23209 ICLASS: VPSRAVQ 23210 CPL: 3 23211 CATEGORY: AVX512 23212 EXTENSION: AVX512EVEX 23213 ISA_SET: AVX512F_512 23214 EXCEPTIONS: AVX512-E4 23215 REAL_OPCODE: Y 23216 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23217 PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 23218 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 23219 IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 23220 } 23221 23222 23223 # EMITTING VPSRLD (VPSRLD-512-1) 23224 { 23225 ICLASS: VPSRLD 23226 CPL: 3 23227 CATEGORY: AVX512 23228 EXTENSION: AVX512EVEX 23229 ISA_SET: AVX512F_512 23230 EXCEPTIONS: AVX512-E4NF 23231 REAL_OPCODE: Y 23232 ATTRIBUTES: MASKOP_EVEX 23233 PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 23234 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 23235 IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 23236 } 23237 23238 { 23239 ICLASS: VPSRLD 23240 CPL: 3 23241 CATEGORY: AVX512 23242 EXTENSION: AVX512EVEX 23243 ISA_SET: AVX512F_512 23244 EXCEPTIONS: AVX512-E4NF 23245 REAL_OPCODE: Y 23246 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 23247 PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() 23248 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 23249 IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 23250 } 23251 23252 23253 # EMITTING VPSRLD (VPSRLD-512-2) 23254 { 23255 ICLASS: VPSRLD 23256 CPL: 3 23257 CATEGORY: AVX512 23258 EXTENSION: AVX512EVEX 23259 ISA_SET: AVX512F_512 23260 EXCEPTIONS: AVX512-E4 23261 REAL_OPCODE: Y 23262 ATTRIBUTES: MASKOP_EVEX 23263 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W0 UIMM8() 23264 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b 23265 IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 23266 } 23267 23268 { 23269 ICLASS: VPSRLD 23270 CPL: 3 23271 CATEGORY: AVX512 23272 EXTENSION: AVX512EVEX 23273 ISA_SET: AVX512F_512 23274 EXCEPTIONS: AVX512-E4 23275 REAL_OPCODE: Y 23276 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23277 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 23278 OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 23279 IFORM: VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 23280 } 23281 23282 23283 # EMITTING VPSRLQ (VPSRLQ-512-1) 23284 { 23285 ICLASS: VPSRLQ 23286 CPL: 3 23287 CATEGORY: AVX512 23288 EXTENSION: AVX512EVEX 23289 ISA_SET: AVX512F_512 23290 EXCEPTIONS: AVX512-E4NF 23291 REAL_OPCODE: Y 23292 ATTRIBUTES: MASKOP_EVEX 23293 PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 23294 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 23295 IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 23296 } 23297 23298 { 23299 ICLASS: VPSRLQ 23300 CPL: 3 23301 CATEGORY: AVX512 23302 EXTENSION: AVX512EVEX 23303 ISA_SET: AVX512F_512 23304 EXCEPTIONS: AVX512-E4NF 23305 REAL_OPCODE: Y 23306 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 23307 PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() 23308 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 23309 IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 23310 } 23311 23312 23313 # EMITTING VPSRLQ (VPSRLQ-512-2) 23314 { 23315 ICLASS: VPSRLQ 23316 CPL: 3 23317 CATEGORY: AVX512 23318 EXTENSION: AVX512EVEX 23319 ISA_SET: AVX512F_512 23320 EXCEPTIONS: AVX512-E4 23321 REAL_OPCODE: Y 23322 ATTRIBUTES: MASKOP_EVEX 23323 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W1 UIMM8() 23324 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b 23325 IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 23326 } 23327 23328 { 23329 ICLASS: VPSRLQ 23330 CPL: 3 23331 CATEGORY: AVX512 23332 EXTENSION: AVX512EVEX 23333 ISA_SET: AVX512F_512 23334 EXCEPTIONS: AVX512-E4 23335 REAL_OPCODE: Y 23336 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23337 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 23338 OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 23339 IFORM: VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 23340 } 23341 23342 23343 # EMITTING VPSRLVD (VPSRLVD-512-1) 23344 { 23345 ICLASS: VPSRLVD 23346 CPL: 3 23347 CATEGORY: AVX512 23348 EXTENSION: AVX512EVEX 23349 ISA_SET: AVX512F_512 23350 EXCEPTIONS: AVX512-E4 23351 REAL_OPCODE: Y 23352 ATTRIBUTES: MASKOP_EVEX 23353 PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 23354 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 23355 IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 23356 } 23357 23358 { 23359 ICLASS: VPSRLVD 23360 CPL: 3 23361 CATEGORY: AVX512 23362 EXTENSION: AVX512EVEX 23363 ISA_SET: AVX512F_512 23364 EXCEPTIONS: AVX512-E4 23365 REAL_OPCODE: Y 23366 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23367 PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 23368 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 23369 IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 23370 } 23371 23372 23373 # EMITTING VPSRLVQ (VPSRLVQ-512-1) 23374 { 23375 ICLASS: VPSRLVQ 23376 CPL: 3 23377 CATEGORY: AVX512 23378 EXTENSION: AVX512EVEX 23379 ISA_SET: AVX512F_512 23380 EXCEPTIONS: AVX512-E4 23381 REAL_OPCODE: Y 23382 ATTRIBUTES: MASKOP_EVEX 23383 PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 23384 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 23385 IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 23386 } 23387 23388 { 23389 ICLASS: VPSRLVQ 23390 CPL: 3 23391 CATEGORY: AVX512 23392 EXTENSION: AVX512EVEX 23393 ISA_SET: AVX512F_512 23394 EXCEPTIONS: AVX512-E4 23395 REAL_OPCODE: Y 23396 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23397 PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 23398 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 23399 IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 23400 } 23401 23402 23403 # EMITTING VPSUBD (VPSUBD-512-1) 23404 { 23405 ICLASS: VPSUBD 23406 CPL: 3 23407 CATEGORY: AVX512 23408 EXTENSION: AVX512EVEX 23409 ISA_SET: AVX512F_512 23410 EXCEPTIONS: AVX512-E4 23411 REAL_OPCODE: Y 23412 ATTRIBUTES: MASKOP_EVEX 23413 PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 23414 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 23415 IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 23416 } 23417 23418 { 23419 ICLASS: VPSUBD 23420 CPL: 3 23421 CATEGORY: AVX512 23422 EXTENSION: AVX512EVEX 23423 ISA_SET: AVX512F_512 23424 EXCEPTIONS: AVX512-E4 23425 REAL_OPCODE: Y 23426 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23427 PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 23428 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 23429 IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 23430 } 23431 23432 23433 # EMITTING VPSUBQ (VPSUBQ-512-1) 23434 { 23435 ICLASS: VPSUBQ 23436 CPL: 3 23437 CATEGORY: AVX512 23438 EXTENSION: AVX512EVEX 23439 ISA_SET: AVX512F_512 23440 EXCEPTIONS: AVX512-E4 23441 REAL_OPCODE: Y 23442 ATTRIBUTES: MASKOP_EVEX 23443 PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 23444 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 23445 IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 23446 } 23447 23448 { 23449 ICLASS: VPSUBQ 23450 CPL: 3 23451 CATEGORY: AVX512 23452 EXTENSION: AVX512EVEX 23453 ISA_SET: AVX512F_512 23454 EXCEPTIONS: AVX512-E4 23455 REAL_OPCODE: Y 23456 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23457 PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 23458 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 23459 IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 23460 } 23461 23462 23463 # EMITTING VPTERNLOGD (VPTERNLOGD-512-1) 23464 { 23465 ICLASS: VPTERNLOGD 23466 CPL: 3 23467 CATEGORY: LOGICAL 23468 EXTENSION: AVX512EVEX 23469 ISA_SET: AVX512F_512 23470 EXCEPTIONS: AVX512-E4 23471 REAL_OPCODE: Y 23472 ATTRIBUTES: MASKOP_EVEX 23473 PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 23474 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b 23475 IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 23476 } 23477 23478 { 23479 ICLASS: VPTERNLOGD 23480 CPL: 3 23481 CATEGORY: LOGICAL 23482 EXTENSION: AVX512EVEX 23483 ISA_SET: AVX512F_512 23484 EXCEPTIONS: AVX512-E4 23485 REAL_OPCODE: Y 23486 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23487 PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 23488 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 23489 IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 23490 } 23491 23492 23493 # EMITTING VPTERNLOGQ (VPTERNLOGQ-512-1) 23494 { 23495 ICLASS: VPTERNLOGQ 23496 CPL: 3 23497 CATEGORY: LOGICAL 23498 EXTENSION: AVX512EVEX 23499 ISA_SET: AVX512F_512 23500 EXCEPTIONS: AVX512-E4 23501 REAL_OPCODE: Y 23502 ATTRIBUTES: MASKOP_EVEX 23503 PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 23504 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b 23505 IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 23506 } 23507 23508 { 23509 ICLASS: VPTERNLOGQ 23510 CPL: 3 23511 CATEGORY: LOGICAL 23512 EXTENSION: AVX512EVEX 23513 ISA_SET: AVX512F_512 23514 EXCEPTIONS: AVX512-E4 23515 REAL_OPCODE: Y 23516 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23517 PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 23518 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 23519 IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 23520 } 23521 23522 23523 # EMITTING VPTESTMD (VPTESTMD-512-1) 23524 { 23525 ICLASS: VPTESTMD 23526 CPL: 3 23527 CATEGORY: LOGICAL 23528 EXTENSION: AVX512EVEX 23529 ISA_SET: AVX512F_512 23530 EXCEPTIONS: AVX512-E4 23531 REAL_OPCODE: Y 23532 ATTRIBUTES: MASKOP_EVEX 23533 PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 23534 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 23535 IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 23536 } 23537 23538 { 23539 ICLASS: VPTESTMD 23540 CPL: 3 23541 CATEGORY: LOGICAL 23542 EXTENSION: AVX512EVEX 23543 ISA_SET: AVX512F_512 23544 EXCEPTIONS: AVX512-E4 23545 REAL_OPCODE: Y 23546 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23547 PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 23548 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 23549 IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 23550 } 23551 23552 23553 # EMITTING VPTESTMQ (VPTESTMQ-512-1) 23554 { 23555 ICLASS: VPTESTMQ 23556 CPL: 3 23557 CATEGORY: LOGICAL 23558 EXTENSION: AVX512EVEX 23559 ISA_SET: AVX512F_512 23560 EXCEPTIONS: AVX512-E4 23561 REAL_OPCODE: Y 23562 ATTRIBUTES: MASKOP_EVEX 23563 PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 23564 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 23565 IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 23566 } 23567 23568 { 23569 ICLASS: VPTESTMQ 23570 CPL: 3 23571 CATEGORY: LOGICAL 23572 EXTENSION: AVX512EVEX 23573 ISA_SET: AVX512F_512 23574 EXCEPTIONS: AVX512-E4 23575 REAL_OPCODE: Y 23576 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23577 PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 23578 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 23579 IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 23580 } 23581 23582 23583 # EMITTING VPTESTNMD (VPTESTNMD-512-1) 23584 { 23585 ICLASS: VPTESTNMD 23586 CPL: 3 23587 CATEGORY: LOGICAL 23588 EXTENSION: AVX512EVEX 23589 ISA_SET: AVX512F_512 23590 EXCEPTIONS: AVX512-E4 23591 REAL_OPCODE: Y 23592 ATTRIBUTES: MASKOP_EVEX 23593 PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 23594 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 23595 IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 23596 } 23597 23598 { 23599 ICLASS: VPTESTNMD 23600 CPL: 3 23601 CATEGORY: LOGICAL 23602 EXTENSION: AVX512EVEX 23603 ISA_SET: AVX512F_512 23604 EXCEPTIONS: AVX512-E4 23605 REAL_OPCODE: Y 23606 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23607 PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 23608 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 23609 IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 23610 } 23611 23612 23613 # EMITTING VPTESTNMQ (VPTESTNMQ-512-1) 23614 { 23615 ICLASS: VPTESTNMQ 23616 CPL: 3 23617 CATEGORY: LOGICAL 23618 EXTENSION: AVX512EVEX 23619 ISA_SET: AVX512F_512 23620 EXCEPTIONS: AVX512-E4 23621 REAL_OPCODE: Y 23622 ATTRIBUTES: MASKOP_EVEX 23623 PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 23624 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 23625 IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 23626 } 23627 23628 { 23629 ICLASS: VPTESTNMQ 23630 CPL: 3 23631 CATEGORY: LOGICAL 23632 EXTENSION: AVX512EVEX 23633 ISA_SET: AVX512F_512 23634 EXCEPTIONS: AVX512-E4 23635 REAL_OPCODE: Y 23636 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23637 PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 23638 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 23639 IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 23640 } 23641 23642 23643 # EMITTING VPUNPCKHDQ (VPUNPCKHDQ-512-1) 23644 { 23645 ICLASS: VPUNPCKHDQ 23646 CPL: 3 23647 CATEGORY: AVX512 23648 EXTENSION: AVX512EVEX 23649 ISA_SET: AVX512F_512 23650 EXCEPTIONS: AVX512-E4NF 23651 REAL_OPCODE: Y 23652 ATTRIBUTES: MASKOP_EVEX 23653 PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 23654 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 23655 IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 23656 } 23657 23658 { 23659 ICLASS: VPUNPCKHDQ 23660 CPL: 3 23661 CATEGORY: AVX512 23662 EXTENSION: AVX512EVEX 23663 ISA_SET: AVX512F_512 23664 EXCEPTIONS: AVX512-E4NF 23665 REAL_OPCODE: Y 23666 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23667 PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 23668 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 23669 IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 23670 } 23671 23672 23673 # EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-512-1) 23674 { 23675 ICLASS: VPUNPCKHQDQ 23676 CPL: 3 23677 CATEGORY: AVX512 23678 EXTENSION: AVX512EVEX 23679 ISA_SET: AVX512F_512 23680 EXCEPTIONS: AVX512-E4NF 23681 REAL_OPCODE: Y 23682 ATTRIBUTES: MASKOP_EVEX 23683 PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 23684 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 23685 IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 23686 } 23687 23688 { 23689 ICLASS: VPUNPCKHQDQ 23690 CPL: 3 23691 CATEGORY: AVX512 23692 EXTENSION: AVX512EVEX 23693 ISA_SET: AVX512F_512 23694 EXCEPTIONS: AVX512-E4NF 23695 REAL_OPCODE: Y 23696 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23697 PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 23698 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 23699 IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 23700 } 23701 23702 23703 # EMITTING VPUNPCKLDQ (VPUNPCKLDQ-512-1) 23704 { 23705 ICLASS: VPUNPCKLDQ 23706 CPL: 3 23707 CATEGORY: AVX512 23708 EXTENSION: AVX512EVEX 23709 ISA_SET: AVX512F_512 23710 EXCEPTIONS: AVX512-E4NF 23711 REAL_OPCODE: Y 23712 ATTRIBUTES: MASKOP_EVEX 23713 PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 23714 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 23715 IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 23716 } 23717 23718 { 23719 ICLASS: VPUNPCKLDQ 23720 CPL: 3 23721 CATEGORY: AVX512 23722 EXTENSION: AVX512EVEX 23723 ISA_SET: AVX512F_512 23724 EXCEPTIONS: AVX512-E4NF 23725 REAL_OPCODE: Y 23726 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23727 PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 23728 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 23729 IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 23730 } 23731 23732 23733 # EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-512-1) 23734 { 23735 ICLASS: VPUNPCKLQDQ 23736 CPL: 3 23737 CATEGORY: AVX512 23738 EXTENSION: AVX512EVEX 23739 ISA_SET: AVX512F_512 23740 EXCEPTIONS: AVX512-E4NF 23741 REAL_OPCODE: Y 23742 ATTRIBUTES: MASKOP_EVEX 23743 PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 23744 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 23745 IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 23746 } 23747 23748 { 23749 ICLASS: VPUNPCKLQDQ 23750 CPL: 3 23751 CATEGORY: AVX512 23752 EXTENSION: AVX512EVEX 23753 ISA_SET: AVX512F_512 23754 EXCEPTIONS: AVX512-E4NF 23755 REAL_OPCODE: Y 23756 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23757 PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 23758 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 23759 IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 23760 } 23761 23762 23763 # EMITTING VPXORD (VPXORD-512-1) 23764 { 23765 ICLASS: VPXORD 23766 CPL: 3 23767 CATEGORY: LOGICAL 23768 EXTENSION: AVX512EVEX 23769 ISA_SET: AVX512F_512 23770 EXCEPTIONS: AVX512-E4 23771 REAL_OPCODE: Y 23772 ATTRIBUTES: MASKOP_EVEX 23773 PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 23774 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 23775 IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 23776 } 23777 23778 { 23779 ICLASS: VPXORD 23780 CPL: 3 23781 CATEGORY: LOGICAL 23782 EXTENSION: AVX512EVEX 23783 ISA_SET: AVX512F_512 23784 EXCEPTIONS: AVX512-E4 23785 REAL_OPCODE: Y 23786 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23787 PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 23788 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 23789 IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 23790 } 23791 23792 23793 # EMITTING VPXORQ (VPXORQ-512-1) 23794 { 23795 ICLASS: VPXORQ 23796 CPL: 3 23797 CATEGORY: LOGICAL 23798 EXTENSION: AVX512EVEX 23799 ISA_SET: AVX512F_512 23800 EXCEPTIONS: AVX512-E4 23801 REAL_OPCODE: Y 23802 ATTRIBUTES: MASKOP_EVEX 23803 PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 23804 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 23805 IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 23806 } 23807 23808 { 23809 ICLASS: VPXORQ 23810 CPL: 3 23811 CATEGORY: LOGICAL 23812 EXTENSION: AVX512EVEX 23813 ISA_SET: AVX512F_512 23814 EXCEPTIONS: AVX512-E4 23815 REAL_OPCODE: Y 23816 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 23817 PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 23818 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 23819 IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 23820 } 23821 23822 23823 # EMITTING VRCP14PD (VRCP14PD-512-1) 23824 { 23825 ICLASS: VRCP14PD 23826 CPL: 3 23827 CATEGORY: AVX512 23828 EXTENSION: AVX512EVEX 23829 ISA_SET: AVX512F_512 23830 EXCEPTIONS: AVX512-E4 23831 REAL_OPCODE: Y 23832 ATTRIBUTES: MASKOP_EVEX MXCSR 23833 PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 23834 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 23835 IFORM: VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 23836 } 23837 23838 { 23839 ICLASS: VRCP14PD 23840 CPL: 3 23841 CATEGORY: AVX512 23842 EXTENSION: AVX512EVEX 23843 ISA_SET: AVX512F_512 23844 EXCEPTIONS: AVX512-E4 23845 REAL_OPCODE: Y 23846 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 23847 PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 23848 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 23849 IFORM: VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 23850 } 23851 23852 23853 # EMITTING VRCP14PS (VRCP14PS-512-1) 23854 { 23855 ICLASS: VRCP14PS 23856 CPL: 3 23857 CATEGORY: AVX512 23858 EXTENSION: AVX512EVEX 23859 ISA_SET: AVX512F_512 23860 EXCEPTIONS: AVX512-E4 23861 REAL_OPCODE: Y 23862 ATTRIBUTES: MASKOP_EVEX MXCSR 23863 PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 23864 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 23865 IFORM: VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 23866 } 23867 23868 { 23869 ICLASS: VRCP14PS 23870 CPL: 3 23871 CATEGORY: AVX512 23872 EXTENSION: AVX512EVEX 23873 ISA_SET: AVX512F_512 23874 EXCEPTIONS: AVX512-E4 23875 REAL_OPCODE: Y 23876 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 23877 PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 23878 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 23879 IFORM: VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 23880 } 23881 23882 23883 # EMITTING VRCP14SD (VRCP14SD-128-1) 23884 { 23885 ICLASS: VRCP14SD 23886 CPL: 3 23887 CATEGORY: AVX512 23888 EXTENSION: AVX512EVEX 23889 ISA_SET: AVX512F_SCALAR 23890 EXCEPTIONS: AVX512-E10 23891 REAL_OPCODE: Y 23892 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 23893 PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 23894 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 23895 IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 23896 } 23897 23898 { 23899 ICLASS: VRCP14SD 23900 CPL: 3 23901 CATEGORY: AVX512 23902 EXTENSION: AVX512EVEX 23903 ISA_SET: AVX512F_SCALAR 23904 EXCEPTIONS: AVX512-E10 23905 REAL_OPCODE: Y 23906 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 23907 PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 23908 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 23909 IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 23910 } 23911 23912 23913 # EMITTING VRCP14SS (VRCP14SS-128-1) 23914 { 23915 ICLASS: VRCP14SS 23916 CPL: 3 23917 CATEGORY: AVX512 23918 EXTENSION: AVX512EVEX 23919 ISA_SET: AVX512F_SCALAR 23920 EXCEPTIONS: AVX512-E10 23921 REAL_OPCODE: Y 23922 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 23923 PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 23924 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 23925 IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 23926 } 23927 23928 { 23929 ICLASS: VRCP14SS 23930 CPL: 3 23931 CATEGORY: AVX512 23932 EXTENSION: AVX512EVEX 23933 ISA_SET: AVX512F_SCALAR 23934 EXCEPTIONS: AVX512-E10 23935 REAL_OPCODE: Y 23936 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 23937 PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 23938 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 23939 IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 23940 } 23941 23942 23943 # EMITTING VRNDSCALEPD (VRNDSCALEPD-512-1) 23944 { 23945 ICLASS: VRNDSCALEPD 23946 CPL: 3 23947 CATEGORY: AVX512 23948 EXTENSION: AVX512EVEX 23949 ISA_SET: AVX512F_512 23950 EXCEPTIONS: AVX512-E2 23951 REAL_OPCODE: Y 23952 ATTRIBUTES: MASKOP_EVEX MXCSR 23953 PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 23954 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 23955 IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 23956 } 23957 23958 { 23959 ICLASS: VRNDSCALEPD 23960 CPL: 3 23961 CATEGORY: AVX512 23962 EXTENSION: AVX512EVEX 23963 ISA_SET: AVX512F_512 23964 EXCEPTIONS: AVX512-E2 23965 REAL_OPCODE: Y 23966 ATTRIBUTES: MASKOP_EVEX MXCSR 23967 PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() 23968 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 23969 IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 23970 } 23971 23972 { 23973 ICLASS: VRNDSCALEPD 23974 CPL: 3 23975 CATEGORY: AVX512 23976 EXTENSION: AVX512EVEX 23977 ISA_SET: AVX512F_512 23978 EXCEPTIONS: AVX512-E2 23979 REAL_OPCODE: Y 23980 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 23981 PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 23982 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 23983 IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 23984 } 23985 23986 23987 # EMITTING VRNDSCALEPS (VRNDSCALEPS-512-1) 23988 { 23989 ICLASS: VRNDSCALEPS 23990 CPL: 3 23991 CATEGORY: AVX512 23992 EXTENSION: AVX512EVEX 23993 ISA_SET: AVX512F_512 23994 EXCEPTIONS: AVX512-E2 23995 REAL_OPCODE: Y 23996 ATTRIBUTES: MASKOP_EVEX MXCSR 23997 PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 23998 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 23999 IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 24000 } 24001 24002 { 24003 ICLASS: VRNDSCALEPS 24004 CPL: 3 24005 CATEGORY: AVX512 24006 EXTENSION: AVX512EVEX 24007 ISA_SET: AVX512F_512 24008 EXCEPTIONS: AVX512-E2 24009 REAL_OPCODE: Y 24010 ATTRIBUTES: MASKOP_EVEX MXCSR 24011 PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() 24012 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 24013 IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 24014 } 24015 24016 { 24017 ICLASS: VRNDSCALEPS 24018 CPL: 3 24019 CATEGORY: AVX512 24020 EXTENSION: AVX512EVEX 24021 ISA_SET: AVX512F_512 24022 EXCEPTIONS: AVX512-E2 24023 REAL_OPCODE: Y 24024 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 24025 PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 24026 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 24027 IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 24028 } 24029 24030 24031 # EMITTING VRNDSCALESD (VRNDSCALESD-128-1) 24032 { 24033 ICLASS: VRNDSCALESD 24034 CPL: 3 24035 CATEGORY: AVX512 24036 EXTENSION: AVX512EVEX 24037 ISA_SET: AVX512F_SCALAR 24038 EXCEPTIONS: AVX512-E3 24039 REAL_OPCODE: Y 24040 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24041 PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() 24042 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 24043 IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 24044 } 24045 24046 { 24047 ICLASS: VRNDSCALESD 24048 CPL: 3 24049 CATEGORY: AVX512 24050 EXTENSION: AVX512EVEX 24051 ISA_SET: AVX512F_SCALAR 24052 EXCEPTIONS: AVX512-E3 24053 REAL_OPCODE: Y 24054 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24055 PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() 24056 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 24057 IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 24058 } 24059 24060 { 24061 ICLASS: VRNDSCALESD 24062 CPL: 3 24063 CATEGORY: AVX512 24064 EXTENSION: AVX512EVEX 24065 ISA_SET: AVX512F_SCALAR 24066 EXCEPTIONS: AVX512-E3 24067 REAL_OPCODE: Y 24068 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 24069 PATTERN: EVV 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 24070 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 24071 IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 24072 } 24073 24074 24075 # EMITTING VRNDSCALESS (VRNDSCALESS-128-1) 24076 { 24077 ICLASS: VRNDSCALESS 24078 CPL: 3 24079 CATEGORY: AVX512 24080 EXTENSION: AVX512EVEX 24081 ISA_SET: AVX512F_SCALAR 24082 EXCEPTIONS: AVX512-E3 24083 REAL_OPCODE: Y 24084 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24085 PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() 24086 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 24087 IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 24088 } 24089 24090 { 24091 ICLASS: VRNDSCALESS 24092 CPL: 3 24093 CATEGORY: AVX512 24094 EXTENSION: AVX512EVEX 24095 ISA_SET: AVX512F_SCALAR 24096 EXCEPTIONS: AVX512-E3 24097 REAL_OPCODE: Y 24098 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24099 PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() 24100 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 24101 IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 24102 } 24103 24104 { 24105 ICLASS: VRNDSCALESS 24106 CPL: 3 24107 CATEGORY: AVX512 24108 EXTENSION: AVX512EVEX 24109 ISA_SET: AVX512F_SCALAR 24110 EXCEPTIONS: AVX512-E3 24111 REAL_OPCODE: Y 24112 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 24113 PATTERN: EVV 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 24114 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 24115 IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 24116 } 24117 24118 24119 # EMITTING VRSQRT14PD (VRSQRT14PD-512-1) 24120 { 24121 ICLASS: VRSQRT14PD 24122 CPL: 3 24123 CATEGORY: AVX512 24124 EXTENSION: AVX512EVEX 24125 ISA_SET: AVX512F_512 24126 EXCEPTIONS: AVX512-E4 24127 REAL_OPCODE: Y 24128 ATTRIBUTES: MASKOP_EVEX MXCSR 24129 PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 24130 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 24131 IFORM: VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 24132 } 24133 24134 { 24135 ICLASS: VRSQRT14PD 24136 CPL: 3 24137 CATEGORY: AVX512 24138 EXTENSION: AVX512EVEX 24139 ISA_SET: AVX512F_512 24140 EXCEPTIONS: AVX512-E4 24141 REAL_OPCODE: Y 24142 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 24143 PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 24144 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 24145 IFORM: VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 24146 } 24147 24148 24149 # EMITTING VRSQRT14PS (VRSQRT14PS-512-1) 24150 { 24151 ICLASS: VRSQRT14PS 24152 CPL: 3 24153 CATEGORY: AVX512 24154 EXTENSION: AVX512EVEX 24155 ISA_SET: AVX512F_512 24156 EXCEPTIONS: AVX512-E4 24157 REAL_OPCODE: Y 24158 ATTRIBUTES: MASKOP_EVEX MXCSR 24159 PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 24160 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 24161 IFORM: VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 24162 } 24163 24164 { 24165 ICLASS: VRSQRT14PS 24166 CPL: 3 24167 CATEGORY: AVX512 24168 EXTENSION: AVX512EVEX 24169 ISA_SET: AVX512F_512 24170 EXCEPTIONS: AVX512-E4 24171 REAL_OPCODE: Y 24172 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 24173 PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 24174 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 24175 IFORM: VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 24176 } 24177 24178 24179 # EMITTING VRSQRT14SD (VRSQRT14SD-128-1) 24180 { 24181 ICLASS: VRSQRT14SD 24182 CPL: 3 24183 CATEGORY: AVX512 24184 EXTENSION: AVX512EVEX 24185 ISA_SET: AVX512F_SCALAR 24186 EXCEPTIONS: AVX512-E10 24187 REAL_OPCODE: Y 24188 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24189 PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 24190 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 24191 IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 24192 } 24193 24194 { 24195 ICLASS: VRSQRT14SD 24196 CPL: 3 24197 CATEGORY: AVX512 24198 EXTENSION: AVX512EVEX 24199 ISA_SET: AVX512F_SCALAR 24200 EXCEPTIONS: AVX512-E10 24201 REAL_OPCODE: Y 24202 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 24203 PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 24204 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 24205 IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 24206 } 24207 24208 24209 # EMITTING VRSQRT14SS (VRSQRT14SS-128-1) 24210 { 24211 ICLASS: VRSQRT14SS 24212 CPL: 3 24213 CATEGORY: AVX512 24214 EXTENSION: AVX512EVEX 24215 ISA_SET: AVX512F_SCALAR 24216 EXCEPTIONS: AVX512-E10 24217 REAL_OPCODE: Y 24218 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24219 PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 24220 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 24221 IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 24222 } 24223 24224 { 24225 ICLASS: VRSQRT14SS 24226 CPL: 3 24227 CATEGORY: AVX512 24228 EXTENSION: AVX512EVEX 24229 ISA_SET: AVX512F_SCALAR 24230 EXCEPTIONS: AVX512-E10 24231 REAL_OPCODE: Y 24232 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 24233 PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 24234 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 24235 IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 24236 } 24237 24238 24239 # EMITTING VSCALEFPD (VSCALEFPD-512-1) 24240 { 24241 ICLASS: VSCALEFPD 24242 CPL: 3 24243 CATEGORY: AVX512 24244 EXTENSION: AVX512EVEX 24245 ISA_SET: AVX512F_512 24246 EXCEPTIONS: AVX512-E2 24247 REAL_OPCODE: Y 24248 ATTRIBUTES: MASKOP_EVEX MXCSR 24249 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 24250 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 24251 IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 24252 } 24253 24254 { 24255 ICLASS: VSCALEFPD 24256 CPL: 3 24257 CATEGORY: AVX512 24258 EXTENSION: AVX512EVEX 24259 ISA_SET: AVX512F_512 24260 EXCEPTIONS: AVX512-E2 24261 REAL_OPCODE: Y 24262 ATTRIBUTES: MASKOP_EVEX MXCSR 24263 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 24264 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 24265 IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 24266 } 24267 24268 { 24269 ICLASS: VSCALEFPD 24270 CPL: 3 24271 CATEGORY: AVX512 24272 EXTENSION: AVX512EVEX 24273 ISA_SET: AVX512F_512 24274 EXCEPTIONS: AVX512-E2 24275 REAL_OPCODE: Y 24276 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 24277 PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 24278 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 24279 IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 24280 } 24281 24282 24283 # EMITTING VSCALEFPS (VSCALEFPS-512-1) 24284 { 24285 ICLASS: VSCALEFPS 24286 CPL: 3 24287 CATEGORY: AVX512 24288 EXTENSION: AVX512EVEX 24289 ISA_SET: AVX512F_512 24290 EXCEPTIONS: AVX512-E2 24291 REAL_OPCODE: Y 24292 ATTRIBUTES: MASKOP_EVEX MXCSR 24293 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 24294 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 24295 IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 24296 } 24297 24298 { 24299 ICLASS: VSCALEFPS 24300 CPL: 3 24301 CATEGORY: AVX512 24302 EXTENSION: AVX512EVEX 24303 ISA_SET: AVX512F_512 24304 EXCEPTIONS: AVX512-E2 24305 REAL_OPCODE: Y 24306 ATTRIBUTES: MASKOP_EVEX MXCSR 24307 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 24308 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 24309 IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 24310 } 24311 24312 { 24313 ICLASS: VSCALEFPS 24314 CPL: 3 24315 CATEGORY: AVX512 24316 EXTENSION: AVX512EVEX 24317 ISA_SET: AVX512F_512 24318 EXCEPTIONS: AVX512-E2 24319 REAL_OPCODE: Y 24320 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 24321 PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 24322 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 24323 IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 24324 } 24325 24326 24327 # EMITTING VSCALEFSD (VSCALEFSD-128-1) 24328 { 24329 ICLASS: VSCALEFSD 24330 CPL: 3 24331 CATEGORY: AVX512 24332 EXTENSION: AVX512EVEX 24333 ISA_SET: AVX512F_SCALAR 24334 EXCEPTIONS: AVX512-E3 24335 REAL_OPCODE: Y 24336 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24337 PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 24338 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 24339 IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 24340 } 24341 24342 { 24343 ICLASS: VSCALEFSD 24344 CPL: 3 24345 CATEGORY: AVX512 24346 EXTENSION: AVX512EVEX 24347 ISA_SET: AVX512F_SCALAR 24348 EXCEPTIONS: AVX512-E3 24349 REAL_OPCODE: Y 24350 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24351 PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 24352 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 24353 IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 24354 } 24355 24356 { 24357 ICLASS: VSCALEFSD 24358 CPL: 3 24359 CATEGORY: AVX512 24360 EXTENSION: AVX512EVEX 24361 ISA_SET: AVX512F_SCALAR 24362 EXCEPTIONS: AVX512-E3 24363 REAL_OPCODE: Y 24364 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 24365 PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 24366 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 24367 IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 24368 } 24369 24370 24371 # EMITTING VSCALEFSS (VSCALEFSS-128-1) 24372 { 24373 ICLASS: VSCALEFSS 24374 CPL: 3 24375 CATEGORY: AVX512 24376 EXTENSION: AVX512EVEX 24377 ISA_SET: AVX512F_SCALAR 24378 EXCEPTIONS: AVX512-E3 24379 REAL_OPCODE: Y 24380 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24381 PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 24382 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 24383 IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 24384 } 24385 24386 { 24387 ICLASS: VSCALEFSS 24388 CPL: 3 24389 CATEGORY: AVX512 24390 EXTENSION: AVX512EVEX 24391 ISA_SET: AVX512F_SCALAR 24392 EXCEPTIONS: AVX512-E3 24393 REAL_OPCODE: Y 24394 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24395 PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 24396 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 24397 IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 24398 } 24399 24400 { 24401 ICLASS: VSCALEFSS 24402 CPL: 3 24403 CATEGORY: AVX512 24404 EXTENSION: AVX512EVEX 24405 ISA_SET: AVX512F_SCALAR 24406 EXCEPTIONS: AVX512-E3 24407 REAL_OPCODE: Y 24408 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 24409 PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 24410 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 24411 IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 24412 } 24413 24414 24415 # EMITTING VSCATTERDPD (VSCATTERDPD-512-1) 24416 { 24417 ICLASS: VSCATTERDPD 24418 CPL: 3 24419 CATEGORY: SCATTER 24420 EXTENSION: AVX512EVEX 24421 ISA_SET: AVX512F_512 24422 EXCEPTIONS: AVX512-E12 24423 REAL_OPCODE: Y 24424 ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 24425 PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 24426 OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 24427 IFORM: VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 24428 } 24429 24430 24431 # EMITTING VSCATTERDPS (VSCATTERDPS-512-1) 24432 { 24433 ICLASS: VSCATTERDPS 24434 CPL: 3 24435 CATEGORY: SCATTER 24436 EXTENSION: AVX512EVEX 24437 ISA_SET: AVX512F_512 24438 EXCEPTIONS: AVX512-E12 24439 REAL_OPCODE: Y 24440 ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 24441 PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 24442 OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf32 24443 IFORM: VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 24444 } 24445 24446 24447 # EMITTING VSCATTERQPD (VSCATTERQPD-512-1) 24448 { 24449 ICLASS: VSCATTERQPD 24450 CPL: 3 24451 CATEGORY: SCATTER 24452 EXTENSION: AVX512EVEX 24453 ISA_SET: AVX512F_512 24454 EXCEPTIONS: AVX512-E12 24455 REAL_OPCODE: Y 24456 ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 24457 PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 24458 OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 24459 IFORM: VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 24460 } 24461 24462 24463 # EMITTING VSCATTERQPS (VSCATTERQPS-512-1) 24464 { 24465 ICLASS: VSCATTERQPS 24466 CPL: 3 24467 CATEGORY: SCATTER 24468 EXTENSION: AVX512EVEX 24469 ISA_SET: AVX512F_512 24470 EXCEPTIONS: AVX512-E12 24471 REAL_OPCODE: Y 24472 ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 24473 PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 24474 OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 24475 IFORM: VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 24476 } 24477 24478 24479 # EMITTING VSHUFF32X4 (VSHUFF32X4-512-1) 24480 { 24481 ICLASS: VSHUFF32X4 24482 CPL: 3 24483 CATEGORY: AVX512 24484 EXTENSION: AVX512EVEX 24485 ISA_SET: AVX512F_512 24486 EXCEPTIONS: AVX512-E4NF 24487 REAL_OPCODE: Y 24488 ATTRIBUTES: MASKOP_EVEX 24489 PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 24490 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 24491 IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 24492 } 24493 24494 { 24495 ICLASS: VSHUFF32X4 24496 CPL: 3 24497 CATEGORY: AVX512 24498 EXTENSION: AVX512EVEX 24499 ISA_SET: AVX512F_512 24500 EXCEPTIONS: AVX512-E4NF 24501 REAL_OPCODE: Y 24502 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 24503 PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 24504 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 24505 IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 24506 } 24507 24508 24509 # EMITTING VSHUFF64X2 (VSHUFF64X2-512-1) 24510 { 24511 ICLASS: VSHUFF64X2 24512 CPL: 3 24513 CATEGORY: AVX512 24514 EXTENSION: AVX512EVEX 24515 ISA_SET: AVX512F_512 24516 EXCEPTIONS: AVX512-E4NF 24517 REAL_OPCODE: Y 24518 ATTRIBUTES: MASKOP_EVEX 24519 PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 24520 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 24521 IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 24522 } 24523 24524 { 24525 ICLASS: VSHUFF64X2 24526 CPL: 3 24527 CATEGORY: AVX512 24528 EXTENSION: AVX512EVEX 24529 ISA_SET: AVX512F_512 24530 EXCEPTIONS: AVX512-E4NF 24531 REAL_OPCODE: Y 24532 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 24533 PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 24534 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 24535 IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 24536 } 24537 24538 24539 # EMITTING VSHUFI32X4 (VSHUFI32X4-512-1) 24540 { 24541 ICLASS: VSHUFI32X4 24542 CPL: 3 24543 CATEGORY: AVX512 24544 EXTENSION: AVX512EVEX 24545 ISA_SET: AVX512F_512 24546 EXCEPTIONS: AVX512-E4NF 24547 REAL_OPCODE: Y 24548 ATTRIBUTES: MASKOP_EVEX 24549 PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 24550 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b 24551 IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 24552 } 24553 24554 { 24555 ICLASS: VSHUFI32X4 24556 CPL: 3 24557 CATEGORY: AVX512 24558 EXTENSION: AVX512EVEX 24559 ISA_SET: AVX512F_512 24560 EXCEPTIONS: AVX512-E4NF 24561 REAL_OPCODE: Y 24562 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 24563 PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 24564 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 24565 IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 24566 } 24567 24568 24569 # EMITTING VSHUFI64X2 (VSHUFI64X2-512-1) 24570 { 24571 ICLASS: VSHUFI64X2 24572 CPL: 3 24573 CATEGORY: AVX512 24574 EXTENSION: AVX512EVEX 24575 ISA_SET: AVX512F_512 24576 EXCEPTIONS: AVX512-E4NF 24577 REAL_OPCODE: Y 24578 ATTRIBUTES: MASKOP_EVEX 24579 PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 24580 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b 24581 IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 24582 } 24583 24584 { 24585 ICLASS: VSHUFI64X2 24586 CPL: 3 24587 CATEGORY: AVX512 24588 EXTENSION: AVX512EVEX 24589 ISA_SET: AVX512F_512 24590 EXCEPTIONS: AVX512-E4NF 24591 REAL_OPCODE: Y 24592 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 24593 PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 24594 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 24595 IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 24596 } 24597 24598 24599 # EMITTING VSHUFPD (VSHUFPD-512-1) 24600 { 24601 ICLASS: VSHUFPD 24602 CPL: 3 24603 CATEGORY: AVX512 24604 EXTENSION: AVX512EVEX 24605 ISA_SET: AVX512F_512 24606 EXCEPTIONS: AVX512-E4NF 24607 REAL_OPCODE: Y 24608 ATTRIBUTES: MASKOP_EVEX 24609 PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 24610 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 24611 IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 24612 } 24613 24614 { 24615 ICLASS: VSHUFPD 24616 CPL: 3 24617 CATEGORY: AVX512 24618 EXTENSION: AVX512EVEX 24619 ISA_SET: AVX512F_512 24620 EXCEPTIONS: AVX512-E4NF 24621 REAL_OPCODE: Y 24622 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 24623 PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 24624 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 24625 IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 24626 } 24627 24628 24629 # EMITTING VSHUFPS (VSHUFPS-512-1) 24630 { 24631 ICLASS: VSHUFPS 24632 CPL: 3 24633 CATEGORY: AVX512 24634 EXTENSION: AVX512EVEX 24635 ISA_SET: AVX512F_512 24636 EXCEPTIONS: AVX512-E4NF 24637 REAL_OPCODE: Y 24638 ATTRIBUTES: MASKOP_EVEX 24639 PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 24640 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 24641 IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 24642 } 24643 24644 { 24645 ICLASS: VSHUFPS 24646 CPL: 3 24647 CATEGORY: AVX512 24648 EXTENSION: AVX512EVEX 24649 ISA_SET: AVX512F_512 24650 EXCEPTIONS: AVX512-E4NF 24651 REAL_OPCODE: Y 24652 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 24653 PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 24654 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 24655 IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 24656 } 24657 24658 24659 # EMITTING VSQRTPD (VSQRTPD-512-1) 24660 { 24661 ICLASS: VSQRTPD 24662 CPL: 3 24663 CATEGORY: AVX512 24664 EXTENSION: AVX512EVEX 24665 ISA_SET: AVX512F_512 24666 EXCEPTIONS: AVX512-E2 24667 REAL_OPCODE: Y 24668 ATTRIBUTES: MASKOP_EVEX MXCSR 24669 PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 24670 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 24671 IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 24672 } 24673 24674 { 24675 ICLASS: VSQRTPD 24676 CPL: 3 24677 CATEGORY: AVX512 24678 EXTENSION: AVX512EVEX 24679 ISA_SET: AVX512F_512 24680 EXCEPTIONS: AVX512-E2 24681 REAL_OPCODE: Y 24682 ATTRIBUTES: MASKOP_EVEX MXCSR 24683 PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 24684 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 24685 IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 24686 } 24687 24688 { 24689 ICLASS: VSQRTPD 24690 CPL: 3 24691 CATEGORY: AVX512 24692 EXTENSION: AVX512EVEX 24693 ISA_SET: AVX512F_512 24694 EXCEPTIONS: AVX512-E2 24695 REAL_OPCODE: Y 24696 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 24697 PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 24698 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 24699 IFORM: VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 24700 } 24701 24702 24703 # EMITTING VSQRTPS (VSQRTPS-512-1) 24704 { 24705 ICLASS: VSQRTPS 24706 CPL: 3 24707 CATEGORY: AVX512 24708 EXTENSION: AVX512EVEX 24709 ISA_SET: AVX512F_512 24710 EXCEPTIONS: AVX512-E2 24711 REAL_OPCODE: Y 24712 ATTRIBUTES: MASKOP_EVEX MXCSR 24713 PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 24714 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 24715 IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 24716 } 24717 24718 { 24719 ICLASS: VSQRTPS 24720 CPL: 3 24721 CATEGORY: AVX512 24722 EXTENSION: AVX512EVEX 24723 ISA_SET: AVX512F_512 24724 EXCEPTIONS: AVX512-E2 24725 REAL_OPCODE: Y 24726 ATTRIBUTES: MASKOP_EVEX MXCSR 24727 PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 24728 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 24729 IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 24730 } 24731 24732 { 24733 ICLASS: VSQRTPS 24734 CPL: 3 24735 CATEGORY: AVX512 24736 EXTENSION: AVX512EVEX 24737 ISA_SET: AVX512F_512 24738 EXCEPTIONS: AVX512-E2 24739 REAL_OPCODE: Y 24740 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 24741 PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 24742 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 24743 IFORM: VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 24744 } 24745 24746 24747 # EMITTING VSQRTSD (VSQRTSD-128-1) 24748 { 24749 ICLASS: VSQRTSD 24750 CPL: 3 24751 CATEGORY: AVX512 24752 EXTENSION: AVX512EVEX 24753 ISA_SET: AVX512F_SCALAR 24754 EXCEPTIONS: AVX512-E3 24755 REAL_OPCODE: Y 24756 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24757 PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 24758 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 24759 IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 24760 } 24761 24762 { 24763 ICLASS: VSQRTSD 24764 CPL: 3 24765 CATEGORY: AVX512 24766 EXTENSION: AVX512EVEX 24767 ISA_SET: AVX512F_SCALAR 24768 EXCEPTIONS: AVX512-E3 24769 REAL_OPCODE: Y 24770 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24771 PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 24772 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 24773 IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 24774 } 24775 24776 { 24777 ICLASS: VSQRTSD 24778 CPL: 3 24779 CATEGORY: AVX512 24780 EXTENSION: AVX512EVEX 24781 ISA_SET: AVX512F_SCALAR 24782 EXCEPTIONS: AVX512-E3 24783 REAL_OPCODE: Y 24784 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 24785 PATTERN: EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 24786 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 24787 IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 24788 } 24789 24790 24791 # EMITTING VSQRTSS (VSQRTSS-128-1) 24792 { 24793 ICLASS: VSQRTSS 24794 CPL: 3 24795 CATEGORY: AVX512 24796 EXTENSION: AVX512EVEX 24797 ISA_SET: AVX512F_SCALAR 24798 EXCEPTIONS: AVX512-E3 24799 REAL_OPCODE: Y 24800 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24801 PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 24802 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 24803 IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 24804 } 24805 24806 { 24807 ICLASS: VSQRTSS 24808 CPL: 3 24809 CATEGORY: AVX512 24810 EXTENSION: AVX512EVEX 24811 ISA_SET: AVX512F_SCALAR 24812 EXCEPTIONS: AVX512-E3 24813 REAL_OPCODE: Y 24814 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24815 PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 24816 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 24817 IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 24818 } 24819 24820 { 24821 ICLASS: VSQRTSS 24822 CPL: 3 24823 CATEGORY: AVX512 24824 EXTENSION: AVX512EVEX 24825 ISA_SET: AVX512F_SCALAR 24826 EXCEPTIONS: AVX512-E3 24827 REAL_OPCODE: Y 24828 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 24829 PATTERN: EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 24830 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 24831 IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 24832 } 24833 24834 24835 # EMITTING VSUBPD (VSUBPD-512-1) 24836 { 24837 ICLASS: VSUBPD 24838 CPL: 3 24839 CATEGORY: AVX512 24840 EXTENSION: AVX512EVEX 24841 ISA_SET: AVX512F_512 24842 EXCEPTIONS: AVX512-E2 24843 REAL_OPCODE: Y 24844 ATTRIBUTES: MASKOP_EVEX MXCSR 24845 PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 24846 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 24847 IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 24848 } 24849 24850 { 24851 ICLASS: VSUBPD 24852 CPL: 3 24853 CATEGORY: AVX512 24854 EXTENSION: AVX512EVEX 24855 ISA_SET: AVX512F_512 24856 EXCEPTIONS: AVX512-E2 24857 REAL_OPCODE: Y 24858 ATTRIBUTES: MASKOP_EVEX MXCSR 24859 PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 24860 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 24861 IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 24862 } 24863 24864 { 24865 ICLASS: VSUBPD 24866 CPL: 3 24867 CATEGORY: AVX512 24868 EXTENSION: AVX512EVEX 24869 ISA_SET: AVX512F_512 24870 EXCEPTIONS: AVX512-E2 24871 REAL_OPCODE: Y 24872 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 24873 PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 24874 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 24875 IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 24876 } 24877 24878 24879 # EMITTING VSUBPS (VSUBPS-512-1) 24880 { 24881 ICLASS: VSUBPS 24882 CPL: 3 24883 CATEGORY: AVX512 24884 EXTENSION: AVX512EVEX 24885 ISA_SET: AVX512F_512 24886 EXCEPTIONS: AVX512-E2 24887 REAL_OPCODE: Y 24888 ATTRIBUTES: MASKOP_EVEX MXCSR 24889 PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 24890 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 24891 IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 24892 } 24893 24894 { 24895 ICLASS: VSUBPS 24896 CPL: 3 24897 CATEGORY: AVX512 24898 EXTENSION: AVX512EVEX 24899 ISA_SET: AVX512F_512 24900 EXCEPTIONS: AVX512-E2 24901 REAL_OPCODE: Y 24902 ATTRIBUTES: MASKOP_EVEX MXCSR 24903 PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 24904 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 24905 IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 24906 } 24907 24908 { 24909 ICLASS: VSUBPS 24910 CPL: 3 24911 CATEGORY: AVX512 24912 EXTENSION: AVX512EVEX 24913 ISA_SET: AVX512F_512 24914 EXCEPTIONS: AVX512-E2 24915 REAL_OPCODE: Y 24916 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 24917 PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 24918 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 24919 IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 24920 } 24921 24922 24923 # EMITTING VSUBSD (VSUBSD-128-1) 24924 { 24925 ICLASS: VSUBSD 24926 CPL: 3 24927 CATEGORY: AVX512 24928 EXTENSION: AVX512EVEX 24929 ISA_SET: AVX512F_SCALAR 24930 EXCEPTIONS: AVX512-E3 24931 REAL_OPCODE: Y 24932 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24933 PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 24934 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 24935 IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 24936 } 24937 24938 { 24939 ICLASS: VSUBSD 24940 CPL: 3 24941 CATEGORY: AVX512 24942 EXTENSION: AVX512EVEX 24943 ISA_SET: AVX512F_SCALAR 24944 EXCEPTIONS: AVX512-E3 24945 REAL_OPCODE: Y 24946 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24947 PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 24948 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 24949 IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 24950 } 24951 24952 { 24953 ICLASS: VSUBSD 24954 CPL: 3 24955 CATEGORY: AVX512 24956 EXTENSION: AVX512EVEX 24957 ISA_SET: AVX512F_SCALAR 24958 EXCEPTIONS: AVX512-E3 24959 REAL_OPCODE: Y 24960 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 24961 PATTERN: EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() 24962 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 24963 IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 24964 } 24965 24966 24967 # EMITTING VSUBSS (VSUBSS-128-1) 24968 { 24969 ICLASS: VSUBSS 24970 CPL: 3 24971 CATEGORY: AVX512 24972 EXTENSION: AVX512EVEX 24973 ISA_SET: AVX512F_SCALAR 24974 EXCEPTIONS: AVX512-E3 24975 REAL_OPCODE: Y 24976 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24977 PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 24978 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 24979 IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 24980 } 24981 24982 { 24983 ICLASS: VSUBSS 24984 CPL: 3 24985 CATEGORY: AVX512 24986 EXTENSION: AVX512EVEX 24987 ISA_SET: AVX512F_SCALAR 24988 EXCEPTIONS: AVX512-E3 24989 REAL_OPCODE: Y 24990 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 24991 PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 24992 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 24993 IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 24994 } 24995 24996 { 24997 ICLASS: VSUBSS 24998 CPL: 3 24999 CATEGORY: AVX512 25000 EXTENSION: AVX512EVEX 25001 ISA_SET: AVX512F_SCALAR 25002 EXCEPTIONS: AVX512-E3 25003 REAL_OPCODE: Y 25004 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 25005 PATTERN: EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() 25006 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 25007 IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 25008 } 25009 25010 25011 # EMITTING VUCOMISD (VUCOMISD-128-1) 25012 { 25013 ICLASS: VUCOMISD 25014 CPL: 3 25015 CATEGORY: AVX512 25016 EXTENSION: AVX512EVEX 25017 ISA_SET: AVX512F_SCALAR 25018 EXCEPTIONS: AVX512-E3NF 25019 REAL_OPCODE: Y 25020 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 25021 ATTRIBUTES: MXCSR SIMD_SCALAR 25022 PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 25023 OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 25024 IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 25025 } 25026 25027 { 25028 ICLASS: VUCOMISD 25029 CPL: 3 25030 CATEGORY: AVX512 25031 EXTENSION: AVX512EVEX 25032 ISA_SET: AVX512F_SCALAR 25033 EXCEPTIONS: AVX512-E3NF 25034 REAL_OPCODE: Y 25035 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 25036 ATTRIBUTES: MXCSR SIMD_SCALAR 25037 PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 25038 OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 25039 IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 25040 } 25041 25042 { 25043 ICLASS: VUCOMISD 25044 CPL: 3 25045 CATEGORY: AVX512 25046 EXTENSION: AVX512EVEX 25047 ISA_SET: AVX512F_SCALAR 25048 EXCEPTIONS: AVX512-E3NF 25049 REAL_OPCODE: Y 25050 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 25051 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR 25052 PATTERN: EVV 0x2E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() 25053 OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 25054 IFORM: VUCOMISD_XMMf64_MEMf64_AVX512 25055 } 25056 25057 25058 # EMITTING VUCOMISS (VUCOMISS-128-1) 25059 { 25060 ICLASS: VUCOMISS 25061 CPL: 3 25062 CATEGORY: AVX512 25063 EXTENSION: AVX512EVEX 25064 ISA_SET: AVX512F_SCALAR 25065 EXCEPTIONS: AVX512-E3NF 25066 REAL_OPCODE: Y 25067 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 25068 ATTRIBUTES: MXCSR SIMD_SCALAR 25069 PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 25070 OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 25071 IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 25072 } 25073 25074 { 25075 ICLASS: VUCOMISS 25076 CPL: 3 25077 CATEGORY: AVX512 25078 EXTENSION: AVX512EVEX 25079 ISA_SET: AVX512F_SCALAR 25080 EXCEPTIONS: AVX512-E3NF 25081 REAL_OPCODE: Y 25082 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 25083 ATTRIBUTES: MXCSR SIMD_SCALAR 25084 PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 25085 OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 25086 IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 25087 } 25088 25089 { 25090 ICLASS: VUCOMISS 25091 CPL: 3 25092 CATEGORY: AVX512 25093 EXTENSION: AVX512EVEX 25094 ISA_SET: AVX512F_SCALAR 25095 EXCEPTIONS: AVX512-E3NF 25096 REAL_OPCODE: Y 25097 FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] 25098 ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR 25099 PATTERN: EVV 0x2E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() 25100 OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 25101 IFORM: VUCOMISS_XMMf32_MEMf32_AVX512 25102 } 25103 25104 25105 # EMITTING VUNPCKHPD (VUNPCKHPD-512-1) 25106 { 25107 ICLASS: VUNPCKHPD 25108 CPL: 3 25109 CATEGORY: AVX512 25110 EXTENSION: AVX512EVEX 25111 ISA_SET: AVX512F_512 25112 EXCEPTIONS: AVX512-E4NF 25113 REAL_OPCODE: Y 25114 ATTRIBUTES: MASKOP_EVEX 25115 PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 25116 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 25117 IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 25118 } 25119 25120 { 25121 ICLASS: VUNPCKHPD 25122 CPL: 3 25123 CATEGORY: AVX512 25124 EXTENSION: AVX512EVEX 25125 ISA_SET: AVX512F_512 25126 EXCEPTIONS: AVX512-E4NF 25127 REAL_OPCODE: Y 25128 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25129 PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 25130 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 25131 IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 25132 } 25133 25134 25135 # EMITTING VUNPCKHPS (VUNPCKHPS-512-1) 25136 { 25137 ICLASS: VUNPCKHPS 25138 CPL: 3 25139 CATEGORY: AVX512 25140 EXTENSION: AVX512EVEX 25141 ISA_SET: AVX512F_512 25142 EXCEPTIONS: AVX512-E4NF 25143 REAL_OPCODE: Y 25144 ATTRIBUTES: MASKOP_EVEX 25145 PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 25146 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 25147 IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 25148 } 25149 25150 { 25151 ICLASS: VUNPCKHPS 25152 CPL: 3 25153 CATEGORY: AVX512 25154 EXTENSION: AVX512EVEX 25155 ISA_SET: AVX512F_512 25156 EXCEPTIONS: AVX512-E4NF 25157 REAL_OPCODE: Y 25158 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25159 PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 25160 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 25161 IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 25162 } 25163 25164 25165 # EMITTING VUNPCKLPD (VUNPCKLPD-512-1) 25166 { 25167 ICLASS: VUNPCKLPD 25168 CPL: 3 25169 CATEGORY: AVX512 25170 EXTENSION: AVX512EVEX 25171 ISA_SET: AVX512F_512 25172 EXCEPTIONS: AVX512-E4NF 25173 REAL_OPCODE: Y 25174 ATTRIBUTES: MASKOP_EVEX 25175 PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 25176 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 25177 IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 25178 } 25179 25180 { 25181 ICLASS: VUNPCKLPD 25182 CPL: 3 25183 CATEGORY: AVX512 25184 EXTENSION: AVX512EVEX 25185 ISA_SET: AVX512F_512 25186 EXCEPTIONS: AVX512-E4NF 25187 REAL_OPCODE: Y 25188 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25189 PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 25190 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR 25191 IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 25192 } 25193 25194 25195 # EMITTING VUNPCKLPS (VUNPCKLPS-512-1) 25196 { 25197 ICLASS: VUNPCKLPS 25198 CPL: 3 25199 CATEGORY: AVX512 25200 EXTENSION: AVX512EVEX 25201 ISA_SET: AVX512F_512 25202 EXCEPTIONS: AVX512-E4NF 25203 REAL_OPCODE: Y 25204 ATTRIBUTES: MASKOP_EVEX 25205 PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 25206 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 25207 IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 25208 } 25209 25210 { 25211 ICLASS: VUNPCKLPS 25212 CPL: 3 25213 CATEGORY: AVX512 25214 EXTENSION: AVX512EVEX 25215 ISA_SET: AVX512F_512 25216 EXCEPTIONS: AVX512-E4NF 25217 REAL_OPCODE: Y 25218 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25219 PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 25220 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR 25221 IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 25222 } 25223 25224 25225 AVX_INSTRUCTIONS():: 25226 # EMITTING KANDNW (KANDNW-256-1) 25227 { 25228 ICLASS: KANDNW 25229 CPL: 3 25230 CATEGORY: KMASK 25231 EXTENSION: AVX512VEX 25232 ISA_SET: AVX512F_KOP 25233 EXCEPTIONS: AVX512-K20 25234 REAL_OPCODE: Y 25235 ATTRIBUTES: KMASK 25236 PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 25237 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 25238 IFORM: KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 25239 } 25240 25241 25242 # EMITTING KANDW (KANDW-256-1) 25243 { 25244 ICLASS: KANDW 25245 CPL: 3 25246 CATEGORY: KMASK 25247 EXTENSION: AVX512VEX 25248 ISA_SET: AVX512F_KOP 25249 EXCEPTIONS: AVX512-K20 25250 REAL_OPCODE: Y 25251 ATTRIBUTES: KMASK 25252 PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 25253 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 25254 IFORM: KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 25255 } 25256 25257 25258 # EMITTING KMOVW (KMOVW-128-1) 25259 { 25260 ICLASS: KMOVW 25261 CPL: 3 25262 CATEGORY: KMASK 25263 EXTENSION: AVX512VEX 25264 ISA_SET: AVX512F_KOP 25265 EXCEPTIONS: AVX512-K21 25266 REAL_OPCODE: Y 25267 ATTRIBUTES: KMASK 25268 PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 25269 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u16 25270 IFORM: KMOVW_MASKmskw_MASKu16_AVX512 25271 } 25272 25273 { 25274 ICLASS: KMOVW 25275 CPL: 3 25276 CATEGORY: KMASK 25277 EXTENSION: AVX512VEX 25278 ISA_SET: AVX512F_KOP 25279 EXCEPTIONS: AVX512-K21 25280 REAL_OPCODE: Y 25281 ATTRIBUTES: KMASK 25282 PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR 25283 OPERANDS: REG0=MASK_R():w:mskw MEM0:r:wrd:u16 25284 IFORM: KMOVW_MASKmskw_MEMu16_AVX512 25285 } 25286 25287 25288 # EMITTING KMOVW (KMOVW-128-2) 25289 { 25290 ICLASS: KMOVW 25291 CPL: 3 25292 CATEGORY: KMASK 25293 EXTENSION: AVX512VEX 25294 ISA_SET: AVX512F_KOP 25295 EXCEPTIONS: AVX512-K21 25296 REAL_OPCODE: Y 25297 ATTRIBUTES: KMASK 25298 PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR 25299 OPERANDS: MEM0:w:wrd:u16 REG0=MASK_R():r:mskw 25300 IFORM: KMOVW_MEMu16_MASKmskw_AVX512 25301 } 25302 25303 25304 # EMITTING KMOVW (KMOVW-128-3) 25305 { 25306 ICLASS: KMOVW 25307 CPL: 3 25308 CATEGORY: KMASK 25309 EXTENSION: AVX512VEX 25310 ISA_SET: AVX512F_KOP 25311 EXCEPTIONS: AVX512-K21 25312 REAL_OPCODE: Y 25313 ATTRIBUTES: KMASK 25314 PATTERN: VV1 0x92 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 25315 OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 25316 IFORM: KMOVW_MASKmskw_GPR32u32_AVX512 25317 } 25318 25319 25320 # EMITTING KMOVW (KMOVW-128-4) 25321 { 25322 ICLASS: KMOVW 25323 CPL: 3 25324 CATEGORY: KMASK 25325 EXTENSION: AVX512VEX 25326 ISA_SET: AVX512F_KOP 25327 EXCEPTIONS: AVX512-K20 25328 REAL_OPCODE: Y 25329 ATTRIBUTES: KMASK 25330 PATTERN: VV1 0x93 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 25331 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw 25332 IFORM: KMOVW_GPR32u32_MASKmskw_AVX512 25333 } 25334 25335 25336 # EMITTING KNOTW (KNOTW-128-1) 25337 { 25338 ICLASS: KNOTW 25339 CPL: 3 25340 CATEGORY: KMASK 25341 EXTENSION: AVX512VEX 25342 ISA_SET: AVX512F_KOP 25343 EXCEPTIONS: AVX512-K20 25344 REAL_OPCODE: Y 25345 ATTRIBUTES: KMASK 25346 PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 25347 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw 25348 IFORM: KNOTW_MASKmskw_MASKmskw_AVX512 25349 } 25350 25351 25352 # EMITTING KORTESTW (KORTESTW-128-1) 25353 { 25354 ICLASS: KORTESTW 25355 CPL: 3 25356 CATEGORY: KMASK 25357 EXTENSION: AVX512VEX 25358 ISA_SET: AVX512F_KOP 25359 EXCEPTIONS: AVX512-K20 25360 REAL_OPCODE: Y 25361 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 25362 ATTRIBUTES: KMASK 25363 PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 25364 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 25365 IFORM: KORTESTW_MASKmskw_MASKmskw_AVX512 25366 } 25367 25368 25369 # EMITTING KORW (KORW-256-1) 25370 { 25371 ICLASS: KORW 25372 CPL: 3 25373 CATEGORY: KMASK 25374 EXTENSION: AVX512VEX 25375 ISA_SET: AVX512F_KOP 25376 EXCEPTIONS: AVX512-K20 25377 REAL_OPCODE: Y 25378 ATTRIBUTES: KMASK 25379 PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 25380 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 25381 IFORM: KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 25382 } 25383 25384 25385 # EMITTING KSHIFTLW (KSHIFTLW-128-1) 25386 { 25387 ICLASS: KSHIFTLW 25388 CPL: 3 25389 CATEGORY: KMASK 25390 EXTENSION: AVX512VEX 25391 ISA_SET: AVX512F_KOP 25392 EXCEPTIONS: AVX512-K20 25393 REAL_OPCODE: Y 25394 ATTRIBUTES: KMASK 25395 PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() 25396 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 25397 IFORM: KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 25398 } 25399 25400 25401 # EMITTING KSHIFTRW (KSHIFTRW-128-1) 25402 { 25403 ICLASS: KSHIFTRW 25404 CPL: 3 25405 CATEGORY: KMASK 25406 EXTENSION: AVX512VEX 25407 ISA_SET: AVX512F_KOP 25408 EXCEPTIONS: AVX512-K20 25409 REAL_OPCODE: Y 25410 ATTRIBUTES: KMASK 25411 PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() 25412 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 25413 IFORM: KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 25414 } 25415 25416 25417 # EMITTING KUNPCKBW (KUNPCKBW-256-1) 25418 { 25419 ICLASS: KUNPCKBW 25420 CPL: 3 25421 CATEGORY: KMASK 25422 EXTENSION: AVX512VEX 25423 ISA_SET: AVX512F_KOP 25424 EXCEPTIONS: AVX512-K20 25425 REAL_OPCODE: Y 25426 ATTRIBUTES: KMASK 25427 PATTERN: VV1 0x4B V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 25428 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 25429 IFORM: KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 25430 } 25431 25432 25433 # EMITTING KXNORW (KXNORW-256-1) 25434 { 25435 ICLASS: KXNORW 25436 CPL: 3 25437 CATEGORY: KMASK 25438 EXTENSION: AVX512VEX 25439 ISA_SET: AVX512F_KOP 25440 EXCEPTIONS: AVX512-K20 25441 REAL_OPCODE: Y 25442 ATTRIBUTES: KMASK 25443 PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 25444 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 25445 IFORM: KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 25446 } 25447 25448 25449 # EMITTING KXORW (KXORW-256-1) 25450 { 25451 ICLASS: KXORW 25452 CPL: 3 25453 CATEGORY: KMASK 25454 EXTENSION: AVX512VEX 25455 ISA_SET: AVX512F_KOP 25456 EXCEPTIONS: AVX512-K20 25457 REAL_OPCODE: Y 25458 ATTRIBUTES: KMASK 25459 PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 25460 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 25461 IFORM: KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 25462 } 25463 25464 25465 25466 ###FILE: ./datafiles/avx512cd/vconflict-isa.xed.txt 25467 25468 #BEGIN_LEGAL 25469 # 25470 #Copyright (c) 2016 Intel Corporation 25471 # 25472 # Licensed under the Apache License, Version 2.0 (the "License"); 25473 # you may not use this file except in compliance with the License. 25474 # You may obtain a copy of the License at 25475 # 25476 # http://www.apache.org/licenses/LICENSE-2.0 25477 # 25478 # Unless required by applicable law or agreed to in writing, software 25479 # distributed under the License is distributed on an "AS IS" BASIS, 25480 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25481 # See the License for the specific language governing permissions and 25482 # limitations under the License. 25483 # 25484 #END_LEGAL 25485 # 25486 # 25487 # 25488 # ***** GENERATED FILE -- DO NOT EDIT! ***** 25489 # ***** GENERATED FILE -- DO NOT EDIT! ***** 25490 # ***** GENERATED FILE -- DO NOT EDIT! ***** 25491 # 25492 # 25493 # 25494 EVEX_INSTRUCTIONS():: 25495 # EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-512-1) 25496 { 25497 ICLASS: VPBROADCASTMB2Q 25498 CPL: 3 25499 CATEGORY: BROADCAST 25500 EXTENSION: AVX512EVEX 25501 ISA_SET: AVX512CD_512 25502 EXCEPTIONS: AVX512-E6NF 25503 REAL_OPCODE: Y 25504 PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 25505 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO8_8 25506 IFORM: VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD 25507 } 25508 25509 25510 # EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-512-1) 25511 { 25512 ICLASS: VPBROADCASTMW2D 25513 CPL: 3 25514 CATEGORY: BROADCAST 25515 EXTENSION: AVX512EVEX 25516 ISA_SET: AVX512CD_512 25517 EXCEPTIONS: AVX512-E6NF 25518 REAL_OPCODE: Y 25519 PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 25520 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO16_16 25521 IFORM: VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD 25522 } 25523 25524 25525 # EMITTING VPCONFLICTD (VPCONFLICTD-512-1) 25526 { 25527 ICLASS: VPCONFLICTD 25528 CPL: 3 25529 CATEGORY: CONFLICT 25530 EXTENSION: AVX512EVEX 25531 ISA_SET: AVX512CD_512 25532 EXCEPTIONS: AVX512-E4NF 25533 REAL_OPCODE: Y 25534 ATTRIBUTES: MASKOP_EVEX 25535 PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 25536 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 25537 IFORM: VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD 25538 } 25539 25540 { 25541 ICLASS: VPCONFLICTD 25542 CPL: 3 25543 CATEGORY: CONFLICT 25544 EXTENSION: AVX512EVEX 25545 ISA_SET: AVX512CD_512 25546 EXCEPTIONS: AVX512-E4NF 25547 REAL_OPCODE: Y 25548 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25549 PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 25550 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 25551 IFORM: VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD 25552 } 25553 25554 25555 # EMITTING VPCONFLICTQ (VPCONFLICTQ-512-1) 25556 { 25557 ICLASS: VPCONFLICTQ 25558 CPL: 3 25559 CATEGORY: CONFLICT 25560 EXTENSION: AVX512EVEX 25561 ISA_SET: AVX512CD_512 25562 EXCEPTIONS: AVX512-E4NF 25563 REAL_OPCODE: Y 25564 ATTRIBUTES: MASKOP_EVEX 25565 PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 25566 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 25567 IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD 25568 } 25569 25570 { 25571 ICLASS: VPCONFLICTQ 25572 CPL: 3 25573 CATEGORY: CONFLICT 25574 EXTENSION: AVX512EVEX 25575 ISA_SET: AVX512CD_512 25576 EXCEPTIONS: AVX512-E4NF 25577 REAL_OPCODE: Y 25578 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25579 PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 25580 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 25581 IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD 25582 } 25583 25584 25585 # EMITTING VPLZCNTD (VPLZCNTD-512-1) 25586 { 25587 ICLASS: VPLZCNTD 25588 CPL: 3 25589 CATEGORY: CONFLICT 25590 EXTENSION: AVX512EVEX 25591 ISA_SET: AVX512CD_512 25592 EXCEPTIONS: AVX512-E4 25593 REAL_OPCODE: Y 25594 ATTRIBUTES: MASKOP_EVEX 25595 PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 25596 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 25597 IFORM: VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD 25598 } 25599 25600 { 25601 ICLASS: VPLZCNTD 25602 CPL: 3 25603 CATEGORY: CONFLICT 25604 EXTENSION: AVX512EVEX 25605 ISA_SET: AVX512CD_512 25606 EXCEPTIONS: AVX512-E4 25607 REAL_OPCODE: Y 25608 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25609 PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 25610 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 25611 IFORM: VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD 25612 } 25613 25614 25615 # EMITTING VPLZCNTQ (VPLZCNTQ-512-1) 25616 { 25617 ICLASS: VPLZCNTQ 25618 CPL: 3 25619 CATEGORY: CONFLICT 25620 EXTENSION: AVX512EVEX 25621 ISA_SET: AVX512CD_512 25622 EXCEPTIONS: AVX512-E4 25623 REAL_OPCODE: Y 25624 ATTRIBUTES: MASKOP_EVEX 25625 PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 25626 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 25627 IFORM: VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD 25628 } 25629 25630 { 25631 ICLASS: VPLZCNTQ 25632 CPL: 3 25633 CATEGORY: CONFLICT 25634 EXTENSION: AVX512EVEX 25635 ISA_SET: AVX512CD_512 25636 EXCEPTIONS: AVX512-E4 25637 REAL_OPCODE: Y 25638 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25639 PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 25640 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 25641 IFORM: VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD 25642 } 25643 25644 25645 25646 25647 ###FILE: ./datafiles/avx512-skx/skx-isa.xed.txt 25648 #BEGIN_LEGAL 25649 # 25650 #Copyright (c) 2019 Intel Corporation 25651 # 25652 # Licensed under the Apache License, Version 2.0 (the "License"); 25653 # you may not use this file except in compliance with the License. 25654 # You may obtain a copy of the License at 25655 # 25656 # http://www.apache.org/licenses/LICENSE-2.0 25657 # 25658 # Unless required by applicable law or agreed to in writing, software 25659 # distributed under the License is distributed on an "AS IS" BASIS, 25660 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25661 # See the License for the specific language governing permissions and 25662 # limitations under the License. 25663 # 25664 #END_LEGAL 25665 # 25666 # 25667 # 25668 # ***** GENERATED FILE -- DO NOT EDIT! ***** 25669 # ***** GENERATED FILE -- DO NOT EDIT! ***** 25670 # ***** GENERATED FILE -- DO NOT EDIT! ***** 25671 # 25672 # 25673 # 25674 EVEX_INSTRUCTIONS():: 25675 # EMITTING VADDPD (VADDPD-128-1) 25676 { 25677 ICLASS: VADDPD 25678 CPL: 3 25679 CATEGORY: AVX512 25680 EXTENSION: AVX512EVEX 25681 ISA_SET: AVX512F_128 25682 EXCEPTIONS: AVX512-E2 25683 REAL_OPCODE: Y 25684 ATTRIBUTES: MASKOP_EVEX MXCSR 25685 PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 25686 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 25687 IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 25688 } 25689 25690 { 25691 ICLASS: VADDPD 25692 CPL: 3 25693 CATEGORY: AVX512 25694 EXTENSION: AVX512EVEX 25695 ISA_SET: AVX512F_128 25696 EXCEPTIONS: AVX512-E2 25697 REAL_OPCODE: Y 25698 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 25699 PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 25700 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 25701 IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 25702 } 25703 25704 25705 # EMITTING VADDPD (VADDPD-256-1) 25706 { 25707 ICLASS: VADDPD 25708 CPL: 3 25709 CATEGORY: AVX512 25710 EXTENSION: AVX512EVEX 25711 ISA_SET: AVX512F_256 25712 EXCEPTIONS: AVX512-E2 25713 REAL_OPCODE: Y 25714 ATTRIBUTES: MASKOP_EVEX MXCSR 25715 PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 25716 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 25717 IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 25718 } 25719 25720 { 25721 ICLASS: VADDPD 25722 CPL: 3 25723 CATEGORY: AVX512 25724 EXTENSION: AVX512EVEX 25725 ISA_SET: AVX512F_256 25726 EXCEPTIONS: AVX512-E2 25727 REAL_OPCODE: Y 25728 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 25729 PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 25730 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 25731 IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 25732 } 25733 25734 25735 # EMITTING VADDPS (VADDPS-128-1) 25736 { 25737 ICLASS: VADDPS 25738 CPL: 3 25739 CATEGORY: AVX512 25740 EXTENSION: AVX512EVEX 25741 ISA_SET: AVX512F_128 25742 EXCEPTIONS: AVX512-E2 25743 REAL_OPCODE: Y 25744 ATTRIBUTES: MASKOP_EVEX MXCSR 25745 PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 25746 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 25747 IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 25748 } 25749 25750 { 25751 ICLASS: VADDPS 25752 CPL: 3 25753 CATEGORY: AVX512 25754 EXTENSION: AVX512EVEX 25755 ISA_SET: AVX512F_128 25756 EXCEPTIONS: AVX512-E2 25757 REAL_OPCODE: Y 25758 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 25759 PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 25760 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 25761 IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 25762 } 25763 25764 25765 # EMITTING VADDPS (VADDPS-256-1) 25766 { 25767 ICLASS: VADDPS 25768 CPL: 3 25769 CATEGORY: AVX512 25770 EXTENSION: AVX512EVEX 25771 ISA_SET: AVX512F_256 25772 EXCEPTIONS: AVX512-E2 25773 REAL_OPCODE: Y 25774 ATTRIBUTES: MASKOP_EVEX MXCSR 25775 PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 25776 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 25777 IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 25778 } 25779 25780 { 25781 ICLASS: VADDPS 25782 CPL: 3 25783 CATEGORY: AVX512 25784 EXTENSION: AVX512EVEX 25785 ISA_SET: AVX512F_256 25786 EXCEPTIONS: AVX512-E2 25787 REAL_OPCODE: Y 25788 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 25789 PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 25790 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 25791 IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 25792 } 25793 25794 25795 # EMITTING VALIGND (VALIGND-128-1) 25796 { 25797 ICLASS: VALIGND 25798 CPL: 3 25799 CATEGORY: AVX512 25800 EXTENSION: AVX512EVEX 25801 ISA_SET: AVX512F_128 25802 EXCEPTIONS: AVX512-E4NF 25803 REAL_OPCODE: Y 25804 ATTRIBUTES: MASKOP_EVEX 25805 PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 25806 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b 25807 IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 25808 } 25809 25810 { 25811 ICLASS: VALIGND 25812 CPL: 3 25813 CATEGORY: AVX512 25814 EXTENSION: AVX512EVEX 25815 ISA_SET: AVX512F_128 25816 EXCEPTIONS: AVX512-E4NF 25817 REAL_OPCODE: Y 25818 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25819 PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 25820 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 25821 IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 25822 } 25823 25824 25825 # EMITTING VALIGND (VALIGND-256-1) 25826 { 25827 ICLASS: VALIGND 25828 CPL: 3 25829 CATEGORY: AVX512 25830 EXTENSION: AVX512EVEX 25831 ISA_SET: AVX512F_256 25832 EXCEPTIONS: AVX512-E4NF 25833 REAL_OPCODE: Y 25834 ATTRIBUTES: MASKOP_EVEX 25835 PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 25836 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b 25837 IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 25838 } 25839 25840 { 25841 ICLASS: VALIGND 25842 CPL: 3 25843 CATEGORY: AVX512 25844 EXTENSION: AVX512EVEX 25845 ISA_SET: AVX512F_256 25846 EXCEPTIONS: AVX512-E4NF 25847 REAL_OPCODE: Y 25848 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25849 PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 25850 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 25851 IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 25852 } 25853 25854 25855 # EMITTING VALIGNQ (VALIGNQ-128-1) 25856 { 25857 ICLASS: VALIGNQ 25858 CPL: 3 25859 CATEGORY: AVX512 25860 EXTENSION: AVX512EVEX 25861 ISA_SET: AVX512F_128 25862 EXCEPTIONS: AVX512-E4NF 25863 REAL_OPCODE: Y 25864 ATTRIBUTES: MASKOP_EVEX 25865 PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 25866 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b 25867 IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 25868 } 25869 25870 { 25871 ICLASS: VALIGNQ 25872 CPL: 3 25873 CATEGORY: AVX512 25874 EXTENSION: AVX512EVEX 25875 ISA_SET: AVX512F_128 25876 EXCEPTIONS: AVX512-E4NF 25877 REAL_OPCODE: Y 25878 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25879 PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 25880 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 25881 IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 25882 } 25883 25884 25885 # EMITTING VALIGNQ (VALIGNQ-256-1) 25886 { 25887 ICLASS: VALIGNQ 25888 CPL: 3 25889 CATEGORY: AVX512 25890 EXTENSION: AVX512EVEX 25891 ISA_SET: AVX512F_256 25892 EXCEPTIONS: AVX512-E4NF 25893 REAL_OPCODE: Y 25894 ATTRIBUTES: MASKOP_EVEX 25895 PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 25896 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b 25897 IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 25898 } 25899 25900 { 25901 ICLASS: VALIGNQ 25902 CPL: 3 25903 CATEGORY: AVX512 25904 EXTENSION: AVX512EVEX 25905 ISA_SET: AVX512F_256 25906 EXCEPTIONS: AVX512-E4NF 25907 REAL_OPCODE: Y 25908 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25909 PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 25910 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 25911 IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 25912 } 25913 25914 25915 # EMITTING VANDNPD (VANDNPD-128-1) 25916 { 25917 ICLASS: VANDNPD 25918 CPL: 3 25919 CATEGORY: LOGICAL_FP 25920 EXTENSION: AVX512EVEX 25921 ISA_SET: AVX512DQ_128 25922 EXCEPTIONS: AVX512-E4 25923 REAL_OPCODE: Y 25924 ATTRIBUTES: MASKOP_EVEX 25925 PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 25926 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 25927 IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 25928 } 25929 25930 { 25931 ICLASS: VANDNPD 25932 CPL: 3 25933 CATEGORY: LOGICAL_FP 25934 EXTENSION: AVX512EVEX 25935 ISA_SET: AVX512DQ_128 25936 EXCEPTIONS: AVX512-E4 25937 REAL_OPCODE: Y 25938 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25939 PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 25940 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 25941 IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 25942 } 25943 25944 25945 # EMITTING VANDNPD (VANDNPD-256-1) 25946 { 25947 ICLASS: VANDNPD 25948 CPL: 3 25949 CATEGORY: LOGICAL_FP 25950 EXTENSION: AVX512EVEX 25951 ISA_SET: AVX512DQ_256 25952 EXCEPTIONS: AVX512-E4 25953 REAL_OPCODE: Y 25954 ATTRIBUTES: MASKOP_EVEX 25955 PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 25956 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 25957 IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 25958 } 25959 25960 { 25961 ICLASS: VANDNPD 25962 CPL: 3 25963 CATEGORY: LOGICAL_FP 25964 EXTENSION: AVX512EVEX 25965 ISA_SET: AVX512DQ_256 25966 EXCEPTIONS: AVX512-E4 25967 REAL_OPCODE: Y 25968 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25969 PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 25970 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 25971 IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 25972 } 25973 25974 25975 # EMITTING VANDNPD (VANDNPD-512-1) 25976 { 25977 ICLASS: VANDNPD 25978 CPL: 3 25979 CATEGORY: LOGICAL_FP 25980 EXTENSION: AVX512EVEX 25981 ISA_SET: AVX512DQ_512 25982 EXCEPTIONS: AVX512-E4 25983 REAL_OPCODE: Y 25984 ATTRIBUTES: MASKOP_EVEX 25985 PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 25986 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 25987 IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 25988 } 25989 25990 { 25991 ICLASS: VANDNPD 25992 CPL: 3 25993 CATEGORY: LOGICAL_FP 25994 EXTENSION: AVX512EVEX 25995 ISA_SET: AVX512DQ_512 25996 EXCEPTIONS: AVX512-E4 25997 REAL_OPCODE: Y 25998 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 25999 PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 26000 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 26001 IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 26002 } 26003 26004 26005 # EMITTING VANDNPS (VANDNPS-128-1) 26006 { 26007 ICLASS: VANDNPS 26008 CPL: 3 26009 CATEGORY: LOGICAL_FP 26010 EXTENSION: AVX512EVEX 26011 ISA_SET: AVX512DQ_128 26012 EXCEPTIONS: AVX512-E4 26013 REAL_OPCODE: Y 26014 ATTRIBUTES: MASKOP_EVEX 26015 PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 26016 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 26017 IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 26018 } 26019 26020 { 26021 ICLASS: VANDNPS 26022 CPL: 3 26023 CATEGORY: LOGICAL_FP 26024 EXTENSION: AVX512EVEX 26025 ISA_SET: AVX512DQ_128 26026 EXCEPTIONS: AVX512-E4 26027 REAL_OPCODE: Y 26028 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 26029 PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 26030 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 26031 IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 26032 } 26033 26034 26035 # EMITTING VANDNPS (VANDNPS-256-1) 26036 { 26037 ICLASS: VANDNPS 26038 CPL: 3 26039 CATEGORY: LOGICAL_FP 26040 EXTENSION: AVX512EVEX 26041 ISA_SET: AVX512DQ_256 26042 EXCEPTIONS: AVX512-E4 26043 REAL_OPCODE: Y 26044 ATTRIBUTES: MASKOP_EVEX 26045 PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 26046 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 26047 IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 26048 } 26049 26050 { 26051 ICLASS: VANDNPS 26052 CPL: 3 26053 CATEGORY: LOGICAL_FP 26054 EXTENSION: AVX512EVEX 26055 ISA_SET: AVX512DQ_256 26056 EXCEPTIONS: AVX512-E4 26057 REAL_OPCODE: Y 26058 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 26059 PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 26060 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 26061 IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 26062 } 26063 26064 26065 # EMITTING VANDNPS (VANDNPS-512-1) 26066 { 26067 ICLASS: VANDNPS 26068 CPL: 3 26069 CATEGORY: LOGICAL_FP 26070 EXTENSION: AVX512EVEX 26071 ISA_SET: AVX512DQ_512 26072 EXCEPTIONS: AVX512-E4 26073 REAL_OPCODE: Y 26074 ATTRIBUTES: MASKOP_EVEX 26075 PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 26076 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 26077 IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 26078 } 26079 26080 { 26081 ICLASS: VANDNPS 26082 CPL: 3 26083 CATEGORY: LOGICAL_FP 26084 EXTENSION: AVX512EVEX 26085 ISA_SET: AVX512DQ_512 26086 EXCEPTIONS: AVX512-E4 26087 REAL_OPCODE: Y 26088 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 26089 PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 26090 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 26091 IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 26092 } 26093 26094 26095 # EMITTING VANDPD (VANDPD-128-1) 26096 { 26097 ICLASS: VANDPD 26098 CPL: 3 26099 CATEGORY: LOGICAL_FP 26100 EXTENSION: AVX512EVEX 26101 ISA_SET: AVX512DQ_128 26102 EXCEPTIONS: AVX512-E4 26103 REAL_OPCODE: Y 26104 ATTRIBUTES: MASKOP_EVEX 26105 PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 26106 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 26107 IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 26108 } 26109 26110 { 26111 ICLASS: VANDPD 26112 CPL: 3 26113 CATEGORY: LOGICAL_FP 26114 EXTENSION: AVX512EVEX 26115 ISA_SET: AVX512DQ_128 26116 EXCEPTIONS: AVX512-E4 26117 REAL_OPCODE: Y 26118 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 26119 PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 26120 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 26121 IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 26122 } 26123 26124 26125 # EMITTING VANDPD (VANDPD-256-1) 26126 { 26127 ICLASS: VANDPD 26128 CPL: 3 26129 CATEGORY: LOGICAL_FP 26130 EXTENSION: AVX512EVEX 26131 ISA_SET: AVX512DQ_256 26132 EXCEPTIONS: AVX512-E4 26133 REAL_OPCODE: Y 26134 ATTRIBUTES: MASKOP_EVEX 26135 PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 26136 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 26137 IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 26138 } 26139 26140 { 26141 ICLASS: VANDPD 26142 CPL: 3 26143 CATEGORY: LOGICAL_FP 26144 EXTENSION: AVX512EVEX 26145 ISA_SET: AVX512DQ_256 26146 EXCEPTIONS: AVX512-E4 26147 REAL_OPCODE: Y 26148 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 26149 PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 26150 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 26151 IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 26152 } 26153 26154 26155 # EMITTING VANDPD (VANDPD-512-1) 26156 { 26157 ICLASS: VANDPD 26158 CPL: 3 26159 CATEGORY: LOGICAL_FP 26160 EXTENSION: AVX512EVEX 26161 ISA_SET: AVX512DQ_512 26162 EXCEPTIONS: AVX512-E4 26163 REAL_OPCODE: Y 26164 ATTRIBUTES: MASKOP_EVEX 26165 PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 26166 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 26167 IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 26168 } 26169 26170 { 26171 ICLASS: VANDPD 26172 CPL: 3 26173 CATEGORY: LOGICAL_FP 26174 EXTENSION: AVX512EVEX 26175 ISA_SET: AVX512DQ_512 26176 EXCEPTIONS: AVX512-E4 26177 REAL_OPCODE: Y 26178 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 26179 PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 26180 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 26181 IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 26182 } 26183 26184 26185 # EMITTING VANDPS (VANDPS-128-1) 26186 { 26187 ICLASS: VANDPS 26188 CPL: 3 26189 CATEGORY: LOGICAL_FP 26190 EXTENSION: AVX512EVEX 26191 ISA_SET: AVX512DQ_128 26192 EXCEPTIONS: AVX512-E4 26193 REAL_OPCODE: Y 26194 ATTRIBUTES: MASKOP_EVEX 26195 PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 26196 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 26197 IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 26198 } 26199 26200 { 26201 ICLASS: VANDPS 26202 CPL: 3 26203 CATEGORY: LOGICAL_FP 26204 EXTENSION: AVX512EVEX 26205 ISA_SET: AVX512DQ_128 26206 EXCEPTIONS: AVX512-E4 26207 REAL_OPCODE: Y 26208 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 26209 PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 26210 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 26211 IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 26212 } 26213 26214 26215 # EMITTING VANDPS (VANDPS-256-1) 26216 { 26217 ICLASS: VANDPS 26218 CPL: 3 26219 CATEGORY: LOGICAL_FP 26220 EXTENSION: AVX512EVEX 26221 ISA_SET: AVX512DQ_256 26222 EXCEPTIONS: AVX512-E4 26223 REAL_OPCODE: Y 26224 ATTRIBUTES: MASKOP_EVEX 26225 PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 26226 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 26227 IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 26228 } 26229 26230 { 26231 ICLASS: VANDPS 26232 CPL: 3 26233 CATEGORY: LOGICAL_FP 26234 EXTENSION: AVX512EVEX 26235 ISA_SET: AVX512DQ_256 26236 EXCEPTIONS: AVX512-E4 26237 REAL_OPCODE: Y 26238 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 26239 PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 26240 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 26241 IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 26242 } 26243 26244 26245 # EMITTING VANDPS (VANDPS-512-1) 26246 { 26247 ICLASS: VANDPS 26248 CPL: 3 26249 CATEGORY: LOGICAL_FP 26250 EXTENSION: AVX512EVEX 26251 ISA_SET: AVX512DQ_512 26252 EXCEPTIONS: AVX512-E4 26253 REAL_OPCODE: Y 26254 ATTRIBUTES: MASKOP_EVEX 26255 PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 26256 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 26257 IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 26258 } 26259 26260 { 26261 ICLASS: VANDPS 26262 CPL: 3 26263 CATEGORY: LOGICAL_FP 26264 EXTENSION: AVX512EVEX 26265 ISA_SET: AVX512DQ_512 26266 EXCEPTIONS: AVX512-E4 26267 REAL_OPCODE: Y 26268 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 26269 PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 26270 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 26271 IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 26272 } 26273 26274 26275 # EMITTING VBLENDMPD (VBLENDMPD-128-1) 26276 { 26277 ICLASS: VBLENDMPD 26278 CPL: 3 26279 CATEGORY: BLEND 26280 EXTENSION: AVX512EVEX 26281 ISA_SET: AVX512F_128 26282 EXCEPTIONS: AVX512-E4 26283 REAL_OPCODE: Y 26284 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 26285 PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 26286 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 26287 IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 26288 } 26289 26290 { 26291 ICLASS: VBLENDMPD 26292 CPL: 3 26293 CATEGORY: BLEND 26294 EXTENSION: AVX512EVEX 26295 ISA_SET: AVX512F_128 26296 EXCEPTIONS: AVX512-E4 26297 REAL_OPCODE: Y 26298 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL 26299 PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 26300 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 26301 IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 26302 } 26303 26304 26305 # EMITTING VBLENDMPD (VBLENDMPD-256-1) 26306 { 26307 ICLASS: VBLENDMPD 26308 CPL: 3 26309 CATEGORY: BLEND 26310 EXTENSION: AVX512EVEX 26311 ISA_SET: AVX512F_256 26312 EXCEPTIONS: AVX512-E4 26313 REAL_OPCODE: Y 26314 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 26315 PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 26316 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 26317 IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 26318 } 26319 26320 { 26321 ICLASS: VBLENDMPD 26322 CPL: 3 26323 CATEGORY: BLEND 26324 EXTENSION: AVX512EVEX 26325 ISA_SET: AVX512F_256 26326 EXCEPTIONS: AVX512-E4 26327 REAL_OPCODE: Y 26328 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL 26329 PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 26330 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 26331 IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 26332 } 26333 26334 26335 # EMITTING VBLENDMPS (VBLENDMPS-128-1) 26336 { 26337 ICLASS: VBLENDMPS 26338 CPL: 3 26339 CATEGORY: BLEND 26340 EXTENSION: AVX512EVEX 26341 ISA_SET: AVX512F_128 26342 EXCEPTIONS: AVX512-E4 26343 REAL_OPCODE: Y 26344 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 26345 PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 26346 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 26347 IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 26348 } 26349 26350 { 26351 ICLASS: VBLENDMPS 26352 CPL: 3 26353 CATEGORY: BLEND 26354 EXTENSION: AVX512EVEX 26355 ISA_SET: AVX512F_128 26356 EXCEPTIONS: AVX512-E4 26357 REAL_OPCODE: Y 26358 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL 26359 PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 26360 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 26361 IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 26362 } 26363 26364 26365 # EMITTING VBLENDMPS (VBLENDMPS-256-1) 26366 { 26367 ICLASS: VBLENDMPS 26368 CPL: 3 26369 CATEGORY: BLEND 26370 EXTENSION: AVX512EVEX 26371 ISA_SET: AVX512F_256 26372 EXCEPTIONS: AVX512-E4 26373 REAL_OPCODE: Y 26374 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 26375 PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 26376 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 26377 IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 26378 } 26379 26380 { 26381 ICLASS: VBLENDMPS 26382 CPL: 3 26383 CATEGORY: BLEND 26384 EXTENSION: AVX512EVEX 26385 ISA_SET: AVX512F_256 26386 EXCEPTIONS: AVX512-E4 26387 REAL_OPCODE: Y 26388 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL 26389 PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 26390 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 26391 IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 26392 } 26393 26394 26395 # EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-256-1) 26396 { 26397 ICLASS: VBROADCASTF32X2 26398 CPL: 3 26399 CATEGORY: BROADCAST 26400 EXTENSION: AVX512EVEX 26401 ISA_SET: AVX512DQ_256 26402 EXCEPTIONS: AVX512-E6 26403 REAL_OPCODE: Y 26404 ATTRIBUTES: MASKOP_EVEX 26405 PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 26406 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO8_32 26407 IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 26408 } 26409 26410 { 26411 ICLASS: VBROADCASTF32X2 26412 CPL: 3 26413 CATEGORY: BROADCAST 26414 EXTENSION: AVX512EVEX 26415 ISA_SET: AVX512DQ_256 26416 EXCEPTIONS: AVX512-E6 26417 REAL_OPCODE: Y 26418 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 26419 PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() 26420 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO8_32 26421 IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 26422 } 26423 26424 26425 # EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-512-1) 26426 { 26427 ICLASS: VBROADCASTF32X2 26428 CPL: 3 26429 CATEGORY: BROADCAST 26430 EXTENSION: AVX512EVEX 26431 ISA_SET: AVX512DQ_512 26432 EXCEPTIONS: AVX512-E6 26433 REAL_OPCODE: Y 26434 ATTRIBUTES: MASKOP_EVEX 26435 PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 26436 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO16_32 26437 IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 26438 } 26439 26440 { 26441 ICLASS: VBROADCASTF32X2 26442 CPL: 3 26443 CATEGORY: BROADCAST 26444 EXTENSION: AVX512EVEX 26445 ISA_SET: AVX512DQ_512 26446 EXCEPTIONS: AVX512-E6 26447 REAL_OPCODE: Y 26448 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 26449 PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() 26450 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO16_32 26451 IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 26452 } 26453 26454 26455 # EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-256-1) 26456 { 26457 ICLASS: VBROADCASTF32X4 26458 CPL: 3 26459 CATEGORY: BROADCAST 26460 EXTENSION: AVX512EVEX 26461 ISA_SET: AVX512F_256 26462 EXCEPTIONS: AVX512-E6 26463 REAL_OPCODE: Y 26464 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 26465 PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() 26466 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO8_32 26467 IFORM: VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 26468 } 26469 26470 26471 # EMITTING VBROADCASTF32X8 (VBROADCASTF32X8-512-1) 26472 { 26473 ICLASS: VBROADCASTF32X8 26474 CPL: 3 26475 CATEGORY: BROADCAST 26476 EXTENSION: AVX512EVEX 26477 ISA_SET: AVX512DQ_512 26478 EXCEPTIONS: AVX512-E6 26479 REAL_OPCODE: Y 26480 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 26481 PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() 26482 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 EMX_BROADCAST_8TO16_32 26483 IFORM: VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 26484 } 26485 26486 26487 # EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-256-1) 26488 { 26489 ICLASS: VBROADCASTF64X2 26490 CPL: 3 26491 CATEGORY: BROADCAST 26492 EXTENSION: AVX512EVEX 26493 ISA_SET: AVX512DQ_256 26494 EXCEPTIONS: AVX512-E6 26495 REAL_OPCODE: Y 26496 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 26497 PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() 26498 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64 26499 IFORM: VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 26500 } 26501 26502 26503 # EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-512-1) 26504 { 26505 ICLASS: VBROADCASTF64X2 26506 CPL: 3 26507 CATEGORY: BROADCAST 26508 EXTENSION: AVX512EVEX 26509 ISA_SET: AVX512DQ_512 26510 EXCEPTIONS: AVX512-E6 26511 REAL_OPCODE: Y 26512 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 26513 PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() 26514 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO8_64 26515 IFORM: VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 26516 } 26517 26518 26519 # EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-128-1) 26520 { 26521 ICLASS: VBROADCASTI32X2 26522 CPL: 3 26523 CATEGORY: BROADCAST 26524 EXTENSION: AVX512EVEX 26525 ISA_SET: AVX512DQ_128 26526 EXCEPTIONS: AVX512-E6 26527 REAL_OPCODE: Y 26528 ATTRIBUTES: MASKOP_EVEX 26529 PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 26530 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO4_32 26531 IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 26532 } 26533 26534 { 26535 ICLASS: VBROADCASTI32X2 26536 CPL: 3 26537 CATEGORY: BROADCAST 26538 EXTENSION: AVX512EVEX 26539 ISA_SET: AVX512DQ_128 26540 EXCEPTIONS: AVX512-E6 26541 REAL_OPCODE: Y 26542 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 26543 PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() 26544 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO4_32 26545 IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 26546 } 26547 26548 26549 # EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-256-1) 26550 { 26551 ICLASS: VBROADCASTI32X2 26552 CPL: 3 26553 CATEGORY: BROADCAST 26554 EXTENSION: AVX512EVEX 26555 ISA_SET: AVX512DQ_256 26556 EXCEPTIONS: AVX512-E6 26557 REAL_OPCODE: Y 26558 ATTRIBUTES: MASKOP_EVEX 26559 PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 26560 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO8_32 26561 IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 26562 } 26563 26564 { 26565 ICLASS: VBROADCASTI32X2 26566 CPL: 3 26567 CATEGORY: BROADCAST 26568 EXTENSION: AVX512EVEX 26569 ISA_SET: AVX512DQ_256 26570 EXCEPTIONS: AVX512-E6 26571 REAL_OPCODE: Y 26572 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 26573 PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() 26574 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO8_32 26575 IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 26576 } 26577 26578 26579 # EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-512-1) 26580 { 26581 ICLASS: VBROADCASTI32X2 26582 CPL: 3 26583 CATEGORY: BROADCAST 26584 EXTENSION: AVX512EVEX 26585 ISA_SET: AVX512DQ_512 26586 EXCEPTIONS: AVX512-E6 26587 REAL_OPCODE: Y 26588 ATTRIBUTES: MASKOP_EVEX 26589 PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 26590 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO16_32 26591 IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 26592 } 26593 26594 { 26595 ICLASS: VBROADCASTI32X2 26596 CPL: 3 26597 CATEGORY: BROADCAST 26598 EXTENSION: AVX512EVEX 26599 ISA_SET: AVX512DQ_512 26600 EXCEPTIONS: AVX512-E6 26601 REAL_OPCODE: Y 26602 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 26603 PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() 26604 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO16_32 26605 IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 26606 } 26607 26608 26609 # EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-256-1) 26610 { 26611 ICLASS: VBROADCASTI32X4 26612 CPL: 3 26613 CATEGORY: BROADCAST 26614 EXTENSION: AVX512EVEX 26615 ISA_SET: AVX512F_256 26616 EXCEPTIONS: AVX512-E6 26617 REAL_OPCODE: Y 26618 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 26619 PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() 26620 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO8_32 26621 IFORM: VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 26622 } 26623 26624 26625 # EMITTING VBROADCASTI32X8 (VBROADCASTI32X8-512-1) 26626 { 26627 ICLASS: VBROADCASTI32X8 26628 CPL: 3 26629 CATEGORY: BROADCAST 26630 EXTENSION: AVX512EVEX 26631 ISA_SET: AVX512DQ_512 26632 EXCEPTIONS: AVX512-E6 26633 REAL_OPCODE: Y 26634 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 26635 PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() 26636 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 EMX_BROADCAST_8TO16_32 26637 IFORM: VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 26638 } 26639 26640 26641 # EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-256-1) 26642 { 26643 ICLASS: VBROADCASTI64X2 26644 CPL: 3 26645 CATEGORY: BROADCAST 26646 EXTENSION: AVX512EVEX 26647 ISA_SET: AVX512DQ_256 26648 EXCEPTIONS: AVX512-E6 26649 REAL_OPCODE: Y 26650 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 26651 PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() 26652 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO4_64 26653 IFORM: VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 26654 } 26655 26656 26657 # EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-512-1) 26658 { 26659 ICLASS: VBROADCASTI64X2 26660 CPL: 3 26661 CATEGORY: BROADCAST 26662 EXTENSION: AVX512EVEX 26663 ISA_SET: AVX512DQ_512 26664 EXCEPTIONS: AVX512-E6 26665 REAL_OPCODE: Y 26666 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 26667 PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() 26668 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO8_64 26669 IFORM: VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 26670 } 26671 26672 26673 # EMITTING VBROADCASTSD (VBROADCASTSD-256-1) 26674 { 26675 ICLASS: VBROADCASTSD 26676 CPL: 3 26677 CATEGORY: BROADCAST 26678 EXTENSION: AVX512EVEX 26679 ISA_SET: AVX512F_256 26680 EXCEPTIONS: AVX512-E6 26681 REAL_OPCODE: Y 26682 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 26683 PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() 26684 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO4_64 26685 IFORM: VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 26686 } 26687 26688 26689 # EMITTING VBROADCASTSD (VBROADCASTSD-256-2) 26690 { 26691 ICLASS: VBROADCASTSD 26692 CPL: 3 26693 CATEGORY: BROADCAST 26694 EXTENSION: AVX512EVEX 26695 ISA_SET: AVX512F_256 26696 EXCEPTIONS: AVX512-E6 26697 REAL_OPCODE: Y 26698 ATTRIBUTES: MASKOP_EVEX 26699 PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 26700 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO4_64 26701 IFORM: VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 26702 } 26703 26704 26705 # EMITTING VBROADCASTSS (VBROADCASTSS-128-1) 26706 { 26707 ICLASS: VBROADCASTSS 26708 CPL: 3 26709 CATEGORY: BROADCAST 26710 EXTENSION: AVX512EVEX 26711 ISA_SET: AVX512F_128 26712 EXCEPTIONS: AVX512-E6 26713 REAL_OPCODE: Y 26714 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 26715 PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() 26716 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO4_32 26717 IFORM: VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 26718 } 26719 26720 26721 # EMITTING VBROADCASTSS (VBROADCASTSS-128-2) 26722 { 26723 ICLASS: VBROADCASTSS 26724 CPL: 3 26725 CATEGORY: BROADCAST 26726 EXTENSION: AVX512EVEX 26727 ISA_SET: AVX512F_128 26728 EXCEPTIONS: AVX512-E6 26729 REAL_OPCODE: Y 26730 ATTRIBUTES: MASKOP_EVEX 26731 PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 26732 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO4_32 26733 IFORM: VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 26734 } 26735 26736 26737 # EMITTING VBROADCASTSS (VBROADCASTSS-256-1) 26738 { 26739 ICLASS: VBROADCASTSS 26740 CPL: 3 26741 CATEGORY: BROADCAST 26742 EXTENSION: AVX512EVEX 26743 ISA_SET: AVX512F_256 26744 EXCEPTIONS: AVX512-E6 26745 REAL_OPCODE: Y 26746 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 26747 PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() 26748 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO8_32 26749 IFORM: VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 26750 } 26751 26752 26753 # EMITTING VBROADCASTSS (VBROADCASTSS-256-2) 26754 { 26755 ICLASS: VBROADCASTSS 26756 CPL: 3 26757 CATEGORY: BROADCAST 26758 EXTENSION: AVX512EVEX 26759 ISA_SET: AVX512F_256 26760 EXCEPTIONS: AVX512-E6 26761 REAL_OPCODE: Y 26762 ATTRIBUTES: MASKOP_EVEX 26763 PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 26764 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO8_32 26765 IFORM: VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 26766 } 26767 26768 26769 # EMITTING VCMPPD (VCMPPD-128-1) 26770 { 26771 ICLASS: VCMPPD 26772 CPL: 3 26773 CATEGORY: AVX512 26774 EXTENSION: AVX512EVEX 26775 ISA_SET: AVX512F_128 26776 EXCEPTIONS: AVX512-E2 26777 REAL_OPCODE: Y 26778 ATTRIBUTES: MASKOP_EVEX MXCSR 26779 PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() 26780 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 26781 IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 26782 } 26783 26784 { 26785 ICLASS: VCMPPD 26786 CPL: 3 26787 CATEGORY: AVX512 26788 EXTENSION: AVX512EVEX 26789 ISA_SET: AVX512F_128 26790 EXCEPTIONS: AVX512-E2 26791 REAL_OPCODE: Y 26792 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 26793 PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 26794 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 26795 IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 26796 } 26797 26798 26799 # EMITTING VCMPPD (VCMPPD-256-1) 26800 { 26801 ICLASS: VCMPPD 26802 CPL: 3 26803 CATEGORY: AVX512 26804 EXTENSION: AVX512EVEX 26805 ISA_SET: AVX512F_256 26806 EXCEPTIONS: AVX512-E2 26807 REAL_OPCODE: Y 26808 ATTRIBUTES: MASKOP_EVEX MXCSR 26809 PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() 26810 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b 26811 IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 26812 } 26813 26814 { 26815 ICLASS: VCMPPD 26816 CPL: 3 26817 CATEGORY: AVX512 26818 EXTENSION: AVX512EVEX 26819 ISA_SET: AVX512F_256 26820 EXCEPTIONS: AVX512-E2 26821 REAL_OPCODE: Y 26822 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 26823 PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 26824 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 26825 IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 26826 } 26827 26828 26829 # EMITTING VCMPPS (VCMPPS-128-1) 26830 { 26831 ICLASS: VCMPPS 26832 CPL: 3 26833 CATEGORY: AVX512 26834 EXTENSION: AVX512EVEX 26835 ISA_SET: AVX512F_128 26836 EXCEPTIONS: AVX512-E2 26837 REAL_OPCODE: Y 26838 ATTRIBUTES: MASKOP_EVEX MXCSR 26839 PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() 26840 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 26841 IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 26842 } 26843 26844 { 26845 ICLASS: VCMPPS 26846 CPL: 3 26847 CATEGORY: AVX512 26848 EXTENSION: AVX512EVEX 26849 ISA_SET: AVX512F_128 26850 EXCEPTIONS: AVX512-E2 26851 REAL_OPCODE: Y 26852 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 26853 PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 26854 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 26855 IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 26856 } 26857 26858 26859 # EMITTING VCMPPS (VCMPPS-256-1) 26860 { 26861 ICLASS: VCMPPS 26862 CPL: 3 26863 CATEGORY: AVX512 26864 EXTENSION: AVX512EVEX 26865 ISA_SET: AVX512F_256 26866 EXCEPTIONS: AVX512-E2 26867 REAL_OPCODE: Y 26868 ATTRIBUTES: MASKOP_EVEX MXCSR 26869 PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() 26870 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b 26871 IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 26872 } 26873 26874 { 26875 ICLASS: VCMPPS 26876 CPL: 3 26877 CATEGORY: AVX512 26878 EXTENSION: AVX512EVEX 26879 ISA_SET: AVX512F_256 26880 EXCEPTIONS: AVX512-E2 26881 REAL_OPCODE: Y 26882 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 26883 PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 26884 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 26885 IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 26886 } 26887 26888 26889 # EMITTING VCOMPRESSPD (VCOMPRESSPD-128-1) 26890 { 26891 ICLASS: VCOMPRESSPD 26892 CPL: 3 26893 CATEGORY: COMPRESS 26894 EXTENSION: AVX512EVEX 26895 ISA_SET: AVX512F_128 26896 EXCEPTIONS: AVX512-E4 26897 REAL_OPCODE: Y 26898 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 26899 PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 26900 OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 26901 IFORM: VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 26902 } 26903 26904 26905 # EMITTING VCOMPRESSPD (VCOMPRESSPD-128-2) 26906 { 26907 ICLASS: VCOMPRESSPD 26908 CPL: 3 26909 CATEGORY: COMPRESS 26910 EXTENSION: AVX512EVEX 26911 ISA_SET: AVX512F_128 26912 EXCEPTIONS: AVX512-E4 26913 REAL_OPCODE: Y 26914 ATTRIBUTES: MASKOP_EVEX 26915 PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 26916 OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 26917 IFORM: VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 26918 } 26919 26920 26921 # EMITTING VCOMPRESSPD (VCOMPRESSPD-256-1) 26922 { 26923 ICLASS: VCOMPRESSPD 26924 CPL: 3 26925 CATEGORY: COMPRESS 26926 EXTENSION: AVX512EVEX 26927 ISA_SET: AVX512F_256 26928 EXCEPTIONS: AVX512-E4 26929 REAL_OPCODE: Y 26930 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 26931 PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 26932 OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 26933 IFORM: VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 26934 } 26935 26936 26937 # EMITTING VCOMPRESSPD (VCOMPRESSPD-256-2) 26938 { 26939 ICLASS: VCOMPRESSPD 26940 CPL: 3 26941 CATEGORY: COMPRESS 26942 EXTENSION: AVX512EVEX 26943 ISA_SET: AVX512F_256 26944 EXCEPTIONS: AVX512-E4 26945 REAL_OPCODE: Y 26946 ATTRIBUTES: MASKOP_EVEX 26947 PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 26948 OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 26949 IFORM: VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 26950 } 26951 26952 26953 # EMITTING VCOMPRESSPS (VCOMPRESSPS-128-1) 26954 { 26955 ICLASS: VCOMPRESSPS 26956 CPL: 3 26957 CATEGORY: COMPRESS 26958 EXTENSION: AVX512EVEX 26959 ISA_SET: AVX512F_128 26960 EXCEPTIONS: AVX512-E4 26961 REAL_OPCODE: Y 26962 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 26963 PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 26964 OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 26965 IFORM: VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 26966 } 26967 26968 26969 # EMITTING VCOMPRESSPS (VCOMPRESSPS-128-2) 26970 { 26971 ICLASS: VCOMPRESSPS 26972 CPL: 3 26973 CATEGORY: COMPRESS 26974 EXTENSION: AVX512EVEX 26975 ISA_SET: AVX512F_128 26976 EXCEPTIONS: AVX512-E4 26977 REAL_OPCODE: Y 26978 ATTRIBUTES: MASKOP_EVEX 26979 PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 26980 OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 26981 IFORM: VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 26982 } 26983 26984 26985 # EMITTING VCOMPRESSPS (VCOMPRESSPS-256-1) 26986 { 26987 ICLASS: VCOMPRESSPS 26988 CPL: 3 26989 CATEGORY: COMPRESS 26990 EXTENSION: AVX512EVEX 26991 ISA_SET: AVX512F_256 26992 EXCEPTIONS: AVX512-E4 26993 REAL_OPCODE: Y 26994 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 26995 PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 26996 OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 26997 IFORM: VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 26998 } 26999 27000 27001 # EMITTING VCOMPRESSPS (VCOMPRESSPS-256-2) 27002 { 27003 ICLASS: VCOMPRESSPS 27004 CPL: 3 27005 CATEGORY: COMPRESS 27006 EXTENSION: AVX512EVEX 27007 ISA_SET: AVX512F_256 27008 EXCEPTIONS: AVX512-E4 27009 REAL_OPCODE: Y 27010 ATTRIBUTES: MASKOP_EVEX 27011 PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 27012 OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 27013 IFORM: VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 27014 } 27015 27016 27017 # EMITTING VCVTDQ2PD (VCVTDQ2PD-128-1) 27018 { 27019 ICLASS: VCVTDQ2PD 27020 CPL: 3 27021 CATEGORY: CONVERT 27022 EXTENSION: AVX512EVEX 27023 ISA_SET: AVX512F_128 27024 EXCEPTIONS: AVX512-E5 27025 REAL_OPCODE: Y 27026 ATTRIBUTES: MASKOP_EVEX 27027 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 27028 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 27029 IFORM: VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 27030 } 27031 27032 { 27033 ICLASS: VCVTDQ2PD 27034 CPL: 3 27035 CATEGORY: CONVERT 27036 EXTENSION: AVX512EVEX 27037 ISA_SET: AVX512F_128 27038 EXCEPTIONS: AVX512-E5 27039 REAL_OPCODE: Y 27040 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 27041 PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 27042 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 27043 IFORM: VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 27044 } 27045 27046 27047 # EMITTING VCVTDQ2PD (VCVTDQ2PD-256-1) 27048 { 27049 ICLASS: VCVTDQ2PD 27050 CPL: 3 27051 CATEGORY: CONVERT 27052 EXTENSION: AVX512EVEX 27053 ISA_SET: AVX512F_256 27054 EXCEPTIONS: AVX512-E5 27055 REAL_OPCODE: Y 27056 ATTRIBUTES: MASKOP_EVEX 27057 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 27058 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 27059 IFORM: VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 27060 } 27061 27062 { 27063 ICLASS: VCVTDQ2PD 27064 CPL: 3 27065 CATEGORY: CONVERT 27066 EXTENSION: AVX512EVEX 27067 ISA_SET: AVX512F_256 27068 EXCEPTIONS: AVX512-E5 27069 REAL_OPCODE: Y 27070 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 27071 PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 27072 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 27073 IFORM: VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 27074 } 27075 27076 27077 # EMITTING VCVTDQ2PS (VCVTDQ2PS-128-1) 27078 { 27079 ICLASS: VCVTDQ2PS 27080 CPL: 3 27081 CATEGORY: CONVERT 27082 EXTENSION: AVX512EVEX 27083 ISA_SET: AVX512F_128 27084 EXCEPTIONS: AVX512-E2 27085 REAL_OPCODE: Y 27086 ATTRIBUTES: MASKOP_EVEX MXCSR 27087 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 27088 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 27089 IFORM: VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 27090 } 27091 27092 { 27093 ICLASS: VCVTDQ2PS 27094 CPL: 3 27095 CATEGORY: CONVERT 27096 EXTENSION: AVX512EVEX 27097 ISA_SET: AVX512F_128 27098 EXCEPTIONS: AVX512-E2 27099 REAL_OPCODE: Y 27100 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27101 PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 27102 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 27103 IFORM: VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 27104 } 27105 27106 27107 # EMITTING VCVTDQ2PS (VCVTDQ2PS-256-1) 27108 { 27109 ICLASS: VCVTDQ2PS 27110 CPL: 3 27111 CATEGORY: CONVERT 27112 EXTENSION: AVX512EVEX 27113 ISA_SET: AVX512F_256 27114 EXCEPTIONS: AVX512-E2 27115 REAL_OPCODE: Y 27116 ATTRIBUTES: MASKOP_EVEX MXCSR 27117 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 27118 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 27119 IFORM: VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 27120 } 27121 27122 { 27123 ICLASS: VCVTDQ2PS 27124 CPL: 3 27125 CATEGORY: CONVERT 27126 EXTENSION: AVX512EVEX 27127 ISA_SET: AVX512F_256 27128 EXCEPTIONS: AVX512-E2 27129 REAL_OPCODE: Y 27130 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27131 PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 27132 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 27133 IFORM: VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 27134 } 27135 27136 27137 # EMITTING VCVTPD2DQ (VCVTPD2DQ-128-1) 27138 { 27139 ICLASS: VCVTPD2DQ 27140 CPL: 3 27141 CATEGORY: CONVERT 27142 EXTENSION: AVX512EVEX 27143 ISA_SET: AVX512F_128 27144 EXCEPTIONS: AVX512-E2 27145 REAL_OPCODE: Y 27146 ATTRIBUTES: MASKOP_EVEX MXCSR 27147 PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 27148 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 27149 IFORM: VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 27150 } 27151 27152 { 27153 ICLASS: VCVTPD2DQ 27154 CPL: 3 27155 CATEGORY: CONVERT 27156 EXTENSION: AVX512EVEX 27157 ISA_SET: AVX512F_128 27158 EXCEPTIONS: AVX512-E2 27159 REAL_OPCODE: Y 27160 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27161 PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27162 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27163 IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 27164 } 27165 27166 27167 # EMITTING VCVTPD2DQ (VCVTPD2DQ-256-1) 27168 { 27169 ICLASS: VCVTPD2DQ 27170 CPL: 3 27171 CATEGORY: CONVERT 27172 EXTENSION: AVX512EVEX 27173 ISA_SET: AVX512F_256 27174 EXCEPTIONS: AVX512-E2 27175 REAL_OPCODE: Y 27176 ATTRIBUTES: MASKOP_EVEX MXCSR 27177 PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 27178 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 27179 IFORM: VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 27180 } 27181 27182 { 27183 ICLASS: VCVTPD2DQ 27184 CPL: 3 27185 CATEGORY: CONVERT 27186 EXTENSION: AVX512EVEX 27187 ISA_SET: AVX512F_256 27188 EXCEPTIONS: AVX512-E2 27189 REAL_OPCODE: Y 27190 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27191 PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27192 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27193 IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 27194 } 27195 27196 27197 # EMITTING VCVTPD2PS (VCVTPD2PS-128-1) 27198 { 27199 ICLASS: VCVTPD2PS 27200 CPL: 3 27201 CATEGORY: CONVERT 27202 EXTENSION: AVX512EVEX 27203 ISA_SET: AVX512F_128 27204 EXCEPTIONS: AVX512-E2 27205 REAL_OPCODE: Y 27206 ATTRIBUTES: MASKOP_EVEX MXCSR 27207 PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 27208 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 27209 IFORM: VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 27210 } 27211 27212 { 27213 ICLASS: VCVTPD2PS 27214 CPL: 3 27215 CATEGORY: CONVERT 27216 EXTENSION: AVX512EVEX 27217 ISA_SET: AVX512F_128 27218 EXCEPTIONS: AVX512-E2 27219 REAL_OPCODE: Y 27220 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27221 PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27222 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27223 IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 27224 } 27225 27226 27227 # EMITTING VCVTPD2PS (VCVTPD2PS-256-1) 27228 { 27229 ICLASS: VCVTPD2PS 27230 CPL: 3 27231 CATEGORY: CONVERT 27232 EXTENSION: AVX512EVEX 27233 ISA_SET: AVX512F_256 27234 EXCEPTIONS: AVX512-E2 27235 REAL_OPCODE: Y 27236 ATTRIBUTES: MASKOP_EVEX MXCSR 27237 PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 27238 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 27239 IFORM: VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 27240 } 27241 27242 { 27243 ICLASS: VCVTPD2PS 27244 CPL: 3 27245 CATEGORY: CONVERT 27246 EXTENSION: AVX512EVEX 27247 ISA_SET: AVX512F_256 27248 EXCEPTIONS: AVX512-E2 27249 REAL_OPCODE: Y 27250 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27251 PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27252 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27253 IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 27254 } 27255 27256 27257 # EMITTING VCVTPD2QQ (VCVTPD2QQ-128-1) 27258 { 27259 ICLASS: VCVTPD2QQ 27260 CPL: 3 27261 CATEGORY: CONVERT 27262 EXTENSION: AVX512EVEX 27263 ISA_SET: AVX512DQ_128 27264 EXCEPTIONS: AVX512-E2 27265 REAL_OPCODE: Y 27266 ATTRIBUTES: MASKOP_EVEX MXCSR 27267 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 27268 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 27269 IFORM: VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 27270 } 27271 27272 { 27273 ICLASS: VCVTPD2QQ 27274 CPL: 3 27275 CATEGORY: CONVERT 27276 EXTENSION: AVX512EVEX 27277 ISA_SET: AVX512DQ_128 27278 EXCEPTIONS: AVX512-E2 27279 REAL_OPCODE: Y 27280 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27281 PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27282 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27283 IFORM: VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 27284 } 27285 27286 27287 # EMITTING VCVTPD2QQ (VCVTPD2QQ-256-1) 27288 { 27289 ICLASS: VCVTPD2QQ 27290 CPL: 3 27291 CATEGORY: CONVERT 27292 EXTENSION: AVX512EVEX 27293 ISA_SET: AVX512DQ_256 27294 EXCEPTIONS: AVX512-E2 27295 REAL_OPCODE: Y 27296 ATTRIBUTES: MASKOP_EVEX MXCSR 27297 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 27298 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 27299 IFORM: VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 27300 } 27301 27302 { 27303 ICLASS: VCVTPD2QQ 27304 CPL: 3 27305 CATEGORY: CONVERT 27306 EXTENSION: AVX512EVEX 27307 ISA_SET: AVX512DQ_256 27308 EXCEPTIONS: AVX512-E2 27309 REAL_OPCODE: Y 27310 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27311 PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27312 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27313 IFORM: VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 27314 } 27315 27316 27317 # EMITTING VCVTPD2QQ (VCVTPD2QQ-512-1) 27318 { 27319 ICLASS: VCVTPD2QQ 27320 CPL: 3 27321 CATEGORY: CONVERT 27322 EXTENSION: AVX512EVEX 27323 ISA_SET: AVX512DQ_512 27324 EXCEPTIONS: AVX512-E2 27325 REAL_OPCODE: Y 27326 ATTRIBUTES: MASKOP_EVEX MXCSR 27327 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 27328 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 27329 IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 27330 } 27331 27332 { 27333 ICLASS: VCVTPD2QQ 27334 CPL: 3 27335 CATEGORY: CONVERT 27336 EXTENSION: AVX512EVEX 27337 ISA_SET: AVX512DQ_512 27338 EXCEPTIONS: AVX512-E2 27339 REAL_OPCODE: Y 27340 ATTRIBUTES: MASKOP_EVEX MXCSR 27341 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 27342 OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 27343 IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 27344 } 27345 27346 { 27347 ICLASS: VCVTPD2QQ 27348 CPL: 3 27349 CATEGORY: CONVERT 27350 EXTENSION: AVX512EVEX 27351 ISA_SET: AVX512DQ_512 27352 EXCEPTIONS: AVX512-E2 27353 REAL_OPCODE: Y 27354 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27355 PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27356 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27357 IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 27358 } 27359 27360 27361 # EMITTING VCVTPD2UDQ (VCVTPD2UDQ-128-1) 27362 { 27363 ICLASS: VCVTPD2UDQ 27364 CPL: 3 27365 CATEGORY: CONVERT 27366 EXTENSION: AVX512EVEX 27367 ISA_SET: AVX512F_128 27368 EXCEPTIONS: AVX512-E2 27369 REAL_OPCODE: Y 27370 ATTRIBUTES: MASKOP_EVEX MXCSR 27371 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 27372 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 27373 IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 27374 } 27375 27376 { 27377 ICLASS: VCVTPD2UDQ 27378 CPL: 3 27379 CATEGORY: CONVERT 27380 EXTENSION: AVX512EVEX 27381 ISA_SET: AVX512F_128 27382 EXCEPTIONS: AVX512-E2 27383 REAL_OPCODE: Y 27384 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27385 PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27386 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27387 IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 27388 } 27389 27390 27391 # EMITTING VCVTPD2UDQ (VCVTPD2UDQ-256-1) 27392 { 27393 ICLASS: VCVTPD2UDQ 27394 CPL: 3 27395 CATEGORY: CONVERT 27396 EXTENSION: AVX512EVEX 27397 ISA_SET: AVX512F_256 27398 EXCEPTIONS: AVX512-E2 27399 REAL_OPCODE: Y 27400 ATTRIBUTES: MASKOP_EVEX MXCSR 27401 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 27402 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 27403 IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 27404 } 27405 27406 { 27407 ICLASS: VCVTPD2UDQ 27408 CPL: 3 27409 CATEGORY: CONVERT 27410 EXTENSION: AVX512EVEX 27411 ISA_SET: AVX512F_256 27412 EXCEPTIONS: AVX512-E2 27413 REAL_OPCODE: Y 27414 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27415 PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27416 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27417 IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 27418 } 27419 27420 27421 # EMITTING VCVTPD2UQQ (VCVTPD2UQQ-128-1) 27422 { 27423 ICLASS: VCVTPD2UQQ 27424 CPL: 3 27425 CATEGORY: CONVERT 27426 EXTENSION: AVX512EVEX 27427 ISA_SET: AVX512DQ_128 27428 EXCEPTIONS: AVX512-E2 27429 REAL_OPCODE: Y 27430 ATTRIBUTES: MASKOP_EVEX MXCSR 27431 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 27432 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 27433 IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 27434 } 27435 27436 { 27437 ICLASS: VCVTPD2UQQ 27438 CPL: 3 27439 CATEGORY: CONVERT 27440 EXTENSION: AVX512EVEX 27441 ISA_SET: AVX512DQ_128 27442 EXCEPTIONS: AVX512-E2 27443 REAL_OPCODE: Y 27444 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27445 PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27446 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27447 IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 27448 } 27449 27450 27451 # EMITTING VCVTPD2UQQ (VCVTPD2UQQ-256-1) 27452 { 27453 ICLASS: VCVTPD2UQQ 27454 CPL: 3 27455 CATEGORY: CONVERT 27456 EXTENSION: AVX512EVEX 27457 ISA_SET: AVX512DQ_256 27458 EXCEPTIONS: AVX512-E2 27459 REAL_OPCODE: Y 27460 ATTRIBUTES: MASKOP_EVEX MXCSR 27461 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 27462 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 27463 IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 27464 } 27465 27466 { 27467 ICLASS: VCVTPD2UQQ 27468 CPL: 3 27469 CATEGORY: CONVERT 27470 EXTENSION: AVX512EVEX 27471 ISA_SET: AVX512DQ_256 27472 EXCEPTIONS: AVX512-E2 27473 REAL_OPCODE: Y 27474 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27475 PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27476 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27477 IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 27478 } 27479 27480 27481 # EMITTING VCVTPD2UQQ (VCVTPD2UQQ-512-1) 27482 { 27483 ICLASS: VCVTPD2UQQ 27484 CPL: 3 27485 CATEGORY: CONVERT 27486 EXTENSION: AVX512EVEX 27487 ISA_SET: AVX512DQ_512 27488 EXCEPTIONS: AVX512-E2 27489 REAL_OPCODE: Y 27490 ATTRIBUTES: MASKOP_EVEX MXCSR 27491 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 27492 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 27493 IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 27494 } 27495 27496 { 27497 ICLASS: VCVTPD2UQQ 27498 CPL: 3 27499 CATEGORY: CONVERT 27500 EXTENSION: AVX512EVEX 27501 ISA_SET: AVX512DQ_512 27502 EXCEPTIONS: AVX512-E2 27503 REAL_OPCODE: Y 27504 ATTRIBUTES: MASKOP_EVEX MXCSR 27505 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 27506 OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 27507 IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 27508 } 27509 27510 { 27511 ICLASS: VCVTPD2UQQ 27512 CPL: 3 27513 CATEGORY: CONVERT 27514 EXTENSION: AVX512EVEX 27515 ISA_SET: AVX512DQ_512 27516 EXCEPTIONS: AVX512-E2 27517 REAL_OPCODE: Y 27518 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27519 PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 27520 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 27521 IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 27522 } 27523 27524 27525 # EMITTING VCVTPH2PS (VCVTPH2PS-128-2) 27526 { 27527 ICLASS: VCVTPH2PS 27528 CPL: 3 27529 CATEGORY: CONVERT 27530 EXTENSION: AVX512EVEX 27531 ISA_SET: AVX512F_128 27532 EXCEPTIONS: AVX512-E11 27533 REAL_OPCODE: Y 27534 ATTRIBUTES: MASKOP_EVEX MXCSR 27535 PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 27536 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 27537 IFORM: VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 27538 } 27539 27540 { 27541 ICLASS: VCVTPH2PS 27542 CPL: 3 27543 CATEGORY: CONVERT 27544 EXTENSION: AVX512EVEX 27545 ISA_SET: AVX512F_128 27546 EXCEPTIONS: AVX512-E11 27547 REAL_OPCODE: Y 27548 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM 27549 PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 27550 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f16 27551 IFORM: VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 27552 } 27553 27554 27555 # EMITTING VCVTPH2PS (VCVTPH2PS-256-2) 27556 { 27557 ICLASS: VCVTPH2PS 27558 CPL: 3 27559 CATEGORY: CONVERT 27560 EXTENSION: AVX512EVEX 27561 ISA_SET: AVX512F_256 27562 EXCEPTIONS: AVX512-E11 27563 REAL_OPCODE: Y 27564 ATTRIBUTES: MASKOP_EVEX MXCSR 27565 PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 27566 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 27567 IFORM: VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 27568 } 27569 27570 { 27571 ICLASS: VCVTPH2PS 27572 CPL: 3 27573 CATEGORY: CONVERT 27574 EXTENSION: AVX512EVEX 27575 ISA_SET: AVX512F_256 27576 EXCEPTIONS: AVX512-E11 27577 REAL_OPCODE: Y 27578 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM 27579 PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 27580 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f16 27581 IFORM: VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 27582 } 27583 27584 27585 # EMITTING VCVTPS2DQ (VCVTPS2DQ-128-1) 27586 { 27587 ICLASS: VCVTPS2DQ 27588 CPL: 3 27589 CATEGORY: CONVERT 27590 EXTENSION: AVX512EVEX 27591 ISA_SET: AVX512F_128 27592 EXCEPTIONS: AVX512-E2 27593 REAL_OPCODE: Y 27594 ATTRIBUTES: MASKOP_EVEX MXCSR 27595 PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 27596 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 27597 IFORM: VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 27598 } 27599 27600 { 27601 ICLASS: VCVTPS2DQ 27602 CPL: 3 27603 CATEGORY: CONVERT 27604 EXTENSION: AVX512EVEX 27605 ISA_SET: AVX512F_128 27606 EXCEPTIONS: AVX512-E2 27607 REAL_OPCODE: Y 27608 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27609 PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 27610 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27611 IFORM: VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 27612 } 27613 27614 27615 # EMITTING VCVTPS2DQ (VCVTPS2DQ-256-1) 27616 { 27617 ICLASS: VCVTPS2DQ 27618 CPL: 3 27619 CATEGORY: CONVERT 27620 EXTENSION: AVX512EVEX 27621 ISA_SET: AVX512F_256 27622 EXCEPTIONS: AVX512-E2 27623 REAL_OPCODE: Y 27624 ATTRIBUTES: MASKOP_EVEX MXCSR 27625 PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 27626 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 27627 IFORM: VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 27628 } 27629 27630 { 27631 ICLASS: VCVTPS2DQ 27632 CPL: 3 27633 CATEGORY: CONVERT 27634 EXTENSION: AVX512EVEX 27635 ISA_SET: AVX512F_256 27636 EXCEPTIONS: AVX512-E2 27637 REAL_OPCODE: Y 27638 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27639 PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 27640 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27641 IFORM: VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 27642 } 27643 27644 27645 # EMITTING VCVTPS2PD (VCVTPS2PD-128-1) 27646 { 27647 ICLASS: VCVTPS2PD 27648 CPL: 3 27649 CATEGORY: CONVERT 27650 EXTENSION: AVX512EVEX 27651 ISA_SET: AVX512F_128 27652 EXCEPTIONS: AVX512-E3 27653 REAL_OPCODE: Y 27654 ATTRIBUTES: MASKOP_EVEX MXCSR 27655 PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 27656 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 27657 IFORM: VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 27658 } 27659 27660 { 27661 ICLASS: VCVTPS2PD 27662 CPL: 3 27663 CATEGORY: CONVERT 27664 EXTENSION: AVX512EVEX 27665 ISA_SET: AVX512F_128 27666 EXCEPTIONS: AVX512-E3 27667 REAL_OPCODE: Y 27668 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 27669 PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 27670 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27671 IFORM: VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 27672 } 27673 27674 27675 # EMITTING VCVTPS2PD (VCVTPS2PD-256-1) 27676 { 27677 ICLASS: VCVTPS2PD 27678 CPL: 3 27679 CATEGORY: CONVERT 27680 EXTENSION: AVX512EVEX 27681 ISA_SET: AVX512F_256 27682 EXCEPTIONS: AVX512-E3 27683 REAL_OPCODE: Y 27684 ATTRIBUTES: MASKOP_EVEX MXCSR 27685 PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 27686 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 27687 IFORM: VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 27688 } 27689 27690 { 27691 ICLASS: VCVTPS2PD 27692 CPL: 3 27693 CATEGORY: CONVERT 27694 EXTENSION: AVX512EVEX 27695 ISA_SET: AVX512F_256 27696 EXCEPTIONS: AVX512-E3 27697 REAL_OPCODE: Y 27698 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 27699 PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 27700 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27701 IFORM: VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 27702 } 27703 27704 27705 # EMITTING VCVTPS2PH (VCVTPS2PH-128-2) 27706 { 27707 ICLASS: VCVTPS2PH 27708 CPL: 3 27709 CATEGORY: CONVERT 27710 EXTENSION: AVX512EVEX 27711 ISA_SET: AVX512F_128 27712 EXCEPTIONS: AVX512-E11NF 27713 REAL_OPCODE: Y 27714 ATTRIBUTES: MASKOP_EVEX MXCSR 27715 PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() 27716 OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 IMM0:r:b 27717 IFORM: VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 27718 } 27719 27720 27721 # EMITTING VCVTPS2PH (VCVTPS2PH-128-3) 27722 { 27723 ICLASS: VCVTPS2PH 27724 CPL: 3 27725 CATEGORY: CONVERT 27726 EXTENSION: AVX512EVEX 27727 ISA_SET: AVX512F_128 27728 EXCEPTIONS: AVX512-E11 27729 REAL_OPCODE: Y 27730 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM 27731 PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() 27732 OPERANDS: MEM0:w:q:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 IMM0:r:b 27733 IFORM: VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 27734 } 27735 27736 27737 # EMITTING VCVTPS2PH (VCVTPS2PH-256-2) 27738 { 27739 ICLASS: VCVTPS2PH 27740 CPL: 3 27741 CATEGORY: CONVERT 27742 EXTENSION: AVX512EVEX 27743 ISA_SET: AVX512F_256 27744 EXCEPTIONS: AVX512-E11NF 27745 REAL_OPCODE: Y 27746 ATTRIBUTES: MASKOP_EVEX MXCSR 27747 PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 27748 OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b 27749 IFORM: VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 27750 } 27751 27752 27753 # EMITTING VCVTPS2PH (VCVTPS2PH-256-3) 27754 { 27755 ICLASS: VCVTPS2PH 27756 CPL: 3 27757 CATEGORY: CONVERT 27758 EXTENSION: AVX512EVEX 27759 ISA_SET: AVX512F_256 27760 EXCEPTIONS: AVX512-E11 27761 REAL_OPCODE: Y 27762 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM 27763 PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() 27764 OPERANDS: MEM0:w:dq:f16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b 27765 IFORM: VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 27766 } 27767 27768 27769 # EMITTING VCVTPS2QQ (VCVTPS2QQ-128-1) 27770 { 27771 ICLASS: VCVTPS2QQ 27772 CPL: 3 27773 CATEGORY: CONVERT 27774 EXTENSION: AVX512EVEX 27775 ISA_SET: AVX512DQ_128 27776 EXCEPTIONS: AVX512-E3 27777 REAL_OPCODE: Y 27778 ATTRIBUTES: MASKOP_EVEX MXCSR 27779 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 27780 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 27781 IFORM: VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 27782 } 27783 27784 { 27785 ICLASS: VCVTPS2QQ 27786 CPL: 3 27787 CATEGORY: CONVERT 27788 EXTENSION: AVX512EVEX 27789 ISA_SET: AVX512DQ_128 27790 EXCEPTIONS: AVX512-E3 27791 REAL_OPCODE: Y 27792 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 27793 PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 27794 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27795 IFORM: VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 27796 } 27797 27798 27799 # EMITTING VCVTPS2QQ (VCVTPS2QQ-256-1) 27800 { 27801 ICLASS: VCVTPS2QQ 27802 CPL: 3 27803 CATEGORY: CONVERT 27804 EXTENSION: AVX512EVEX 27805 ISA_SET: AVX512DQ_256 27806 EXCEPTIONS: AVX512-E3 27807 REAL_OPCODE: Y 27808 ATTRIBUTES: MASKOP_EVEX MXCSR 27809 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 27810 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 27811 IFORM: VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 27812 } 27813 27814 { 27815 ICLASS: VCVTPS2QQ 27816 CPL: 3 27817 CATEGORY: CONVERT 27818 EXTENSION: AVX512EVEX 27819 ISA_SET: AVX512DQ_256 27820 EXCEPTIONS: AVX512-E3 27821 REAL_OPCODE: Y 27822 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 27823 PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 27824 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27825 IFORM: VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 27826 } 27827 27828 27829 # EMITTING VCVTPS2QQ (VCVTPS2QQ-512-1) 27830 { 27831 ICLASS: VCVTPS2QQ 27832 CPL: 3 27833 CATEGORY: CONVERT 27834 EXTENSION: AVX512EVEX 27835 ISA_SET: AVX512DQ_512 27836 EXCEPTIONS: AVX512-E3 27837 REAL_OPCODE: Y 27838 ATTRIBUTES: MASKOP_EVEX MXCSR 27839 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 27840 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 27841 IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 27842 } 27843 27844 { 27845 ICLASS: VCVTPS2QQ 27846 CPL: 3 27847 CATEGORY: CONVERT 27848 EXTENSION: AVX512EVEX 27849 ISA_SET: AVX512DQ_512 27850 EXCEPTIONS: AVX512-E3 27851 REAL_OPCODE: Y 27852 ATTRIBUTES: MASKOP_EVEX MXCSR 27853 PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 27854 OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 27855 IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 27856 } 27857 27858 { 27859 ICLASS: VCVTPS2QQ 27860 CPL: 3 27861 CATEGORY: CONVERT 27862 EXTENSION: AVX512EVEX 27863 ISA_SET: AVX512DQ_512 27864 EXCEPTIONS: AVX512-E3 27865 REAL_OPCODE: Y 27866 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 27867 PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 27868 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27869 IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 27870 } 27871 27872 27873 # EMITTING VCVTPS2UDQ (VCVTPS2UDQ-128-1) 27874 { 27875 ICLASS: VCVTPS2UDQ 27876 CPL: 3 27877 CATEGORY: CONVERT 27878 EXTENSION: AVX512EVEX 27879 ISA_SET: AVX512F_128 27880 EXCEPTIONS: AVX512-E2 27881 REAL_OPCODE: Y 27882 ATTRIBUTES: MASKOP_EVEX MXCSR 27883 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 27884 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 27885 IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 27886 } 27887 27888 { 27889 ICLASS: VCVTPS2UDQ 27890 CPL: 3 27891 CATEGORY: CONVERT 27892 EXTENSION: AVX512EVEX 27893 ISA_SET: AVX512F_128 27894 EXCEPTIONS: AVX512-E2 27895 REAL_OPCODE: Y 27896 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27897 PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 27898 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27899 IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 27900 } 27901 27902 27903 # EMITTING VCVTPS2UDQ (VCVTPS2UDQ-256-1) 27904 { 27905 ICLASS: VCVTPS2UDQ 27906 CPL: 3 27907 CATEGORY: CONVERT 27908 EXTENSION: AVX512EVEX 27909 ISA_SET: AVX512F_256 27910 EXCEPTIONS: AVX512-E2 27911 REAL_OPCODE: Y 27912 ATTRIBUTES: MASKOP_EVEX MXCSR 27913 PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 27914 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 27915 IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 27916 } 27917 27918 { 27919 ICLASS: VCVTPS2UDQ 27920 CPL: 3 27921 CATEGORY: CONVERT 27922 EXTENSION: AVX512EVEX 27923 ISA_SET: AVX512F_256 27924 EXCEPTIONS: AVX512-E2 27925 REAL_OPCODE: Y 27926 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 27927 PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 27928 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27929 IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 27930 } 27931 27932 27933 # EMITTING VCVTPS2UQQ (VCVTPS2UQQ-128-1) 27934 { 27935 ICLASS: VCVTPS2UQQ 27936 CPL: 3 27937 CATEGORY: CONVERT 27938 EXTENSION: AVX512EVEX 27939 ISA_SET: AVX512DQ_128 27940 EXCEPTIONS: AVX512-E3 27941 REAL_OPCODE: Y 27942 ATTRIBUTES: MASKOP_EVEX MXCSR 27943 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 27944 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 27945 IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 27946 } 27947 27948 { 27949 ICLASS: VCVTPS2UQQ 27950 CPL: 3 27951 CATEGORY: CONVERT 27952 EXTENSION: AVX512EVEX 27953 ISA_SET: AVX512DQ_128 27954 EXCEPTIONS: AVX512-E3 27955 REAL_OPCODE: Y 27956 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 27957 PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 27958 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27959 IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 27960 } 27961 27962 27963 # EMITTING VCVTPS2UQQ (VCVTPS2UQQ-256-1) 27964 { 27965 ICLASS: VCVTPS2UQQ 27966 CPL: 3 27967 CATEGORY: CONVERT 27968 EXTENSION: AVX512EVEX 27969 ISA_SET: AVX512DQ_256 27970 EXCEPTIONS: AVX512-E3 27971 REAL_OPCODE: Y 27972 ATTRIBUTES: MASKOP_EVEX MXCSR 27973 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 27974 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 27975 IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 27976 } 27977 27978 { 27979 ICLASS: VCVTPS2UQQ 27980 CPL: 3 27981 CATEGORY: CONVERT 27982 EXTENSION: AVX512EVEX 27983 ISA_SET: AVX512DQ_256 27984 EXCEPTIONS: AVX512-E3 27985 REAL_OPCODE: Y 27986 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 27987 PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 27988 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 27989 IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 27990 } 27991 27992 27993 # EMITTING VCVTPS2UQQ (VCVTPS2UQQ-512-1) 27994 { 27995 ICLASS: VCVTPS2UQQ 27996 CPL: 3 27997 CATEGORY: CONVERT 27998 EXTENSION: AVX512EVEX 27999 ISA_SET: AVX512DQ_512 28000 EXCEPTIONS: AVX512-E3 28001 REAL_OPCODE: Y 28002 ATTRIBUTES: MASKOP_EVEX MXCSR 28003 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 28004 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 28005 IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 28006 } 28007 28008 { 28009 ICLASS: VCVTPS2UQQ 28010 CPL: 3 28011 CATEGORY: CONVERT 28012 EXTENSION: AVX512EVEX 28013 ISA_SET: AVX512DQ_512 28014 EXCEPTIONS: AVX512-E3 28015 REAL_OPCODE: Y 28016 ATTRIBUTES: MASKOP_EVEX MXCSR 28017 PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR 28018 OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 28019 IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 28020 } 28021 28022 { 28023 ICLASS: VCVTPS2UQQ 28024 CPL: 3 28025 CATEGORY: CONVERT 28026 EXTENSION: AVX512EVEX 28027 ISA_SET: AVX512DQ_512 28028 EXCEPTIONS: AVX512-E3 28029 REAL_OPCODE: Y 28030 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 28031 PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 28032 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 28033 IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 28034 } 28035 28036 28037 # EMITTING VCVTQQ2PD (VCVTQQ2PD-128-1) 28038 { 28039 ICLASS: VCVTQQ2PD 28040 CPL: 3 28041 CATEGORY: CONVERT 28042 EXTENSION: AVX512EVEX 28043 ISA_SET: AVX512DQ_128 28044 EXCEPTIONS: AVX512-E2 28045 REAL_OPCODE: Y 28046 ATTRIBUTES: MASKOP_EVEX MXCSR 28047 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 28048 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 28049 IFORM: VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 28050 } 28051 28052 { 28053 ICLASS: VCVTQQ2PD 28054 CPL: 3 28055 CATEGORY: CONVERT 28056 EXTENSION: AVX512EVEX 28057 ISA_SET: AVX512DQ_128 28058 EXCEPTIONS: AVX512-E2 28059 REAL_OPCODE: Y 28060 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28061 PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28062 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 28063 IFORM: VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 28064 } 28065 28066 28067 # EMITTING VCVTQQ2PD (VCVTQQ2PD-256-1) 28068 { 28069 ICLASS: VCVTQQ2PD 28070 CPL: 3 28071 CATEGORY: CONVERT 28072 EXTENSION: AVX512EVEX 28073 ISA_SET: AVX512DQ_256 28074 EXCEPTIONS: AVX512-E2 28075 REAL_OPCODE: Y 28076 ATTRIBUTES: MASKOP_EVEX MXCSR 28077 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 28078 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 28079 IFORM: VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 28080 } 28081 28082 { 28083 ICLASS: VCVTQQ2PD 28084 CPL: 3 28085 CATEGORY: CONVERT 28086 EXTENSION: AVX512EVEX 28087 ISA_SET: AVX512DQ_256 28088 EXCEPTIONS: AVX512-E2 28089 REAL_OPCODE: Y 28090 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28091 PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28092 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 28093 IFORM: VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 28094 } 28095 28096 28097 # EMITTING VCVTQQ2PD (VCVTQQ2PD-512-1) 28098 { 28099 ICLASS: VCVTQQ2PD 28100 CPL: 3 28101 CATEGORY: CONVERT 28102 EXTENSION: AVX512EVEX 28103 ISA_SET: AVX512DQ_512 28104 EXCEPTIONS: AVX512-E2 28105 REAL_OPCODE: Y 28106 ATTRIBUTES: MASKOP_EVEX MXCSR 28107 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 28108 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 28109 IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 28110 } 28111 28112 { 28113 ICLASS: VCVTQQ2PD 28114 CPL: 3 28115 CATEGORY: CONVERT 28116 EXTENSION: AVX512EVEX 28117 ISA_SET: AVX512DQ_512 28118 EXCEPTIONS: AVX512-E2 28119 REAL_OPCODE: Y 28120 ATTRIBUTES: MASKOP_EVEX MXCSR 28121 PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 28122 OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 28123 IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 28124 } 28125 28126 { 28127 ICLASS: VCVTQQ2PD 28128 CPL: 3 28129 CATEGORY: CONVERT 28130 EXTENSION: AVX512EVEX 28131 ISA_SET: AVX512DQ_512 28132 EXCEPTIONS: AVX512-E2 28133 REAL_OPCODE: Y 28134 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28135 PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28136 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 28137 IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 28138 } 28139 28140 28141 # EMITTING VCVTQQ2PS (VCVTQQ2PS-128-1) 28142 { 28143 ICLASS: VCVTQQ2PS 28144 CPL: 3 28145 CATEGORY: CONVERT 28146 EXTENSION: AVX512EVEX 28147 ISA_SET: AVX512DQ_128 28148 EXCEPTIONS: AVX512-E2 28149 REAL_OPCODE: Y 28150 ATTRIBUTES: MASKOP_EVEX MXCSR 28151 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 28152 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 28153 IFORM: VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 28154 } 28155 28156 { 28157 ICLASS: VCVTQQ2PS 28158 CPL: 3 28159 CATEGORY: CONVERT 28160 EXTENSION: AVX512EVEX 28161 ISA_SET: AVX512DQ_128 28162 EXCEPTIONS: AVX512-E2 28163 REAL_OPCODE: Y 28164 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28165 PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28166 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 28167 IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 28168 } 28169 28170 28171 # EMITTING VCVTQQ2PS (VCVTQQ2PS-256-1) 28172 { 28173 ICLASS: VCVTQQ2PS 28174 CPL: 3 28175 CATEGORY: CONVERT 28176 EXTENSION: AVX512EVEX 28177 ISA_SET: AVX512DQ_256 28178 EXCEPTIONS: AVX512-E2 28179 REAL_OPCODE: Y 28180 ATTRIBUTES: MASKOP_EVEX MXCSR 28181 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 28182 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 28183 IFORM: VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 28184 } 28185 28186 { 28187 ICLASS: VCVTQQ2PS 28188 CPL: 3 28189 CATEGORY: CONVERT 28190 EXTENSION: AVX512EVEX 28191 ISA_SET: AVX512DQ_256 28192 EXCEPTIONS: AVX512-E2 28193 REAL_OPCODE: Y 28194 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28195 PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28196 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 28197 IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 28198 } 28199 28200 28201 # EMITTING VCVTQQ2PS (VCVTQQ2PS-512-1) 28202 { 28203 ICLASS: VCVTQQ2PS 28204 CPL: 3 28205 CATEGORY: CONVERT 28206 EXTENSION: AVX512EVEX 28207 ISA_SET: AVX512DQ_512 28208 EXCEPTIONS: AVX512-E2 28209 REAL_OPCODE: Y 28210 ATTRIBUTES: MASKOP_EVEX MXCSR 28211 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 28212 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 28213 IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 28214 } 28215 28216 { 28217 ICLASS: VCVTQQ2PS 28218 CPL: 3 28219 CATEGORY: CONVERT 28220 EXTENSION: AVX512EVEX 28221 ISA_SET: AVX512DQ_512 28222 EXCEPTIONS: AVX512-E2 28223 REAL_OPCODE: Y 28224 ATTRIBUTES: MASKOP_EVEX MXCSR 28225 PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 28226 OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 28227 IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 28228 } 28229 28230 { 28231 ICLASS: VCVTQQ2PS 28232 CPL: 3 28233 CATEGORY: CONVERT 28234 EXTENSION: AVX512EVEX 28235 ISA_SET: AVX512DQ_512 28236 EXCEPTIONS: AVX512-E2 28237 REAL_OPCODE: Y 28238 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28239 PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28240 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 28241 IFORM: VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 28242 } 28243 28244 28245 # EMITTING VCVTTPD2DQ (VCVTTPD2DQ-128-1) 28246 { 28247 ICLASS: VCVTTPD2DQ 28248 CPL: 3 28249 CATEGORY: CONVERT 28250 EXTENSION: AVX512EVEX 28251 ISA_SET: AVX512F_128 28252 EXCEPTIONS: AVX512-E2 28253 REAL_OPCODE: Y 28254 ATTRIBUTES: MASKOP_EVEX MXCSR 28255 PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 28256 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 28257 IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 28258 } 28259 28260 { 28261 ICLASS: VCVTTPD2DQ 28262 CPL: 3 28263 CATEGORY: CONVERT 28264 EXTENSION: AVX512EVEX 28265 ISA_SET: AVX512F_128 28266 EXCEPTIONS: AVX512-E2 28267 REAL_OPCODE: Y 28268 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28269 PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28270 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 28271 IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 28272 } 28273 28274 28275 # EMITTING VCVTTPD2DQ (VCVTTPD2DQ-256-1) 28276 { 28277 ICLASS: VCVTTPD2DQ 28278 CPL: 3 28279 CATEGORY: CONVERT 28280 EXTENSION: AVX512EVEX 28281 ISA_SET: AVX512F_256 28282 EXCEPTIONS: AVX512-E2 28283 REAL_OPCODE: Y 28284 ATTRIBUTES: MASKOP_EVEX MXCSR 28285 PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 28286 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 28287 IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 28288 } 28289 28290 { 28291 ICLASS: VCVTTPD2DQ 28292 CPL: 3 28293 CATEGORY: CONVERT 28294 EXTENSION: AVX512EVEX 28295 ISA_SET: AVX512F_256 28296 EXCEPTIONS: AVX512-E2 28297 REAL_OPCODE: Y 28298 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28299 PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28300 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 28301 IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 28302 } 28303 28304 28305 # EMITTING VCVTTPD2QQ (VCVTTPD2QQ-128-1) 28306 { 28307 ICLASS: VCVTTPD2QQ 28308 CPL: 3 28309 CATEGORY: CONVERT 28310 EXTENSION: AVX512EVEX 28311 ISA_SET: AVX512DQ_128 28312 EXCEPTIONS: AVX512-E2 28313 REAL_OPCODE: Y 28314 ATTRIBUTES: MASKOP_EVEX MXCSR 28315 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 28316 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 28317 IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 28318 } 28319 28320 { 28321 ICLASS: VCVTTPD2QQ 28322 CPL: 3 28323 CATEGORY: CONVERT 28324 EXTENSION: AVX512EVEX 28325 ISA_SET: AVX512DQ_128 28326 EXCEPTIONS: AVX512-E2 28327 REAL_OPCODE: Y 28328 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28329 PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28330 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 28331 IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 28332 } 28333 28334 28335 # EMITTING VCVTTPD2QQ (VCVTTPD2QQ-256-1) 28336 { 28337 ICLASS: VCVTTPD2QQ 28338 CPL: 3 28339 CATEGORY: CONVERT 28340 EXTENSION: AVX512EVEX 28341 ISA_SET: AVX512DQ_256 28342 EXCEPTIONS: AVX512-E2 28343 REAL_OPCODE: Y 28344 ATTRIBUTES: MASKOP_EVEX MXCSR 28345 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 28346 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 28347 IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 28348 } 28349 28350 { 28351 ICLASS: VCVTTPD2QQ 28352 CPL: 3 28353 CATEGORY: CONVERT 28354 EXTENSION: AVX512EVEX 28355 ISA_SET: AVX512DQ_256 28356 EXCEPTIONS: AVX512-E2 28357 REAL_OPCODE: Y 28358 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28359 PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28360 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 28361 IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 28362 } 28363 28364 28365 # EMITTING VCVTTPD2QQ (VCVTTPD2QQ-512-1) 28366 { 28367 ICLASS: VCVTTPD2QQ 28368 CPL: 3 28369 CATEGORY: CONVERT 28370 EXTENSION: AVX512EVEX 28371 ISA_SET: AVX512DQ_512 28372 EXCEPTIONS: AVX512-E2 28373 REAL_OPCODE: Y 28374 ATTRIBUTES: MASKOP_EVEX MXCSR 28375 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 28376 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 28377 IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 28378 } 28379 28380 { 28381 ICLASS: VCVTTPD2QQ 28382 CPL: 3 28383 CATEGORY: CONVERT 28384 EXTENSION: AVX512EVEX 28385 ISA_SET: AVX512DQ_512 28386 EXCEPTIONS: AVX512-E2 28387 REAL_OPCODE: Y 28388 ATTRIBUTES: MASKOP_EVEX MXCSR 28389 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 28390 OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 28391 IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 28392 } 28393 28394 { 28395 ICLASS: VCVTTPD2QQ 28396 CPL: 3 28397 CATEGORY: CONVERT 28398 EXTENSION: AVX512EVEX 28399 ISA_SET: AVX512DQ_512 28400 EXCEPTIONS: AVX512-E2 28401 REAL_OPCODE: Y 28402 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28403 PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28404 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 28405 IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 28406 } 28407 28408 28409 # EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-128-1) 28410 { 28411 ICLASS: VCVTTPD2UDQ 28412 CPL: 3 28413 CATEGORY: CONVERT 28414 EXTENSION: AVX512EVEX 28415 ISA_SET: AVX512F_128 28416 EXCEPTIONS: AVX512-E2 28417 REAL_OPCODE: Y 28418 ATTRIBUTES: MASKOP_EVEX MXCSR 28419 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 28420 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 28421 IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 28422 } 28423 28424 { 28425 ICLASS: VCVTTPD2UDQ 28426 CPL: 3 28427 CATEGORY: CONVERT 28428 EXTENSION: AVX512EVEX 28429 ISA_SET: AVX512F_128 28430 EXCEPTIONS: AVX512-E2 28431 REAL_OPCODE: Y 28432 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28433 PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28434 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 28435 IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 28436 } 28437 28438 28439 # EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-256-1) 28440 { 28441 ICLASS: VCVTTPD2UDQ 28442 CPL: 3 28443 CATEGORY: CONVERT 28444 EXTENSION: AVX512EVEX 28445 ISA_SET: AVX512F_256 28446 EXCEPTIONS: AVX512-E2 28447 REAL_OPCODE: Y 28448 ATTRIBUTES: MASKOP_EVEX MXCSR 28449 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 28450 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 28451 IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 28452 } 28453 28454 { 28455 ICLASS: VCVTTPD2UDQ 28456 CPL: 3 28457 CATEGORY: CONVERT 28458 EXTENSION: AVX512EVEX 28459 ISA_SET: AVX512F_256 28460 EXCEPTIONS: AVX512-E2 28461 REAL_OPCODE: Y 28462 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28463 PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28464 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 28465 IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 28466 } 28467 28468 28469 # EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-128-1) 28470 { 28471 ICLASS: VCVTTPD2UQQ 28472 CPL: 3 28473 CATEGORY: CONVERT 28474 EXTENSION: AVX512EVEX 28475 ISA_SET: AVX512DQ_128 28476 EXCEPTIONS: AVX512-E2 28477 REAL_OPCODE: Y 28478 ATTRIBUTES: MASKOP_EVEX MXCSR 28479 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 28480 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 28481 IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 28482 } 28483 28484 { 28485 ICLASS: VCVTTPD2UQQ 28486 CPL: 3 28487 CATEGORY: CONVERT 28488 EXTENSION: AVX512EVEX 28489 ISA_SET: AVX512DQ_128 28490 EXCEPTIONS: AVX512-E2 28491 REAL_OPCODE: Y 28492 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28493 PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28494 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 28495 IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 28496 } 28497 28498 28499 # EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-256-1) 28500 { 28501 ICLASS: VCVTTPD2UQQ 28502 CPL: 3 28503 CATEGORY: CONVERT 28504 EXTENSION: AVX512EVEX 28505 ISA_SET: AVX512DQ_256 28506 EXCEPTIONS: AVX512-E2 28507 REAL_OPCODE: Y 28508 ATTRIBUTES: MASKOP_EVEX MXCSR 28509 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 28510 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 28511 IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 28512 } 28513 28514 { 28515 ICLASS: VCVTTPD2UQQ 28516 CPL: 3 28517 CATEGORY: CONVERT 28518 EXTENSION: AVX512EVEX 28519 ISA_SET: AVX512DQ_256 28520 EXCEPTIONS: AVX512-E2 28521 REAL_OPCODE: Y 28522 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28523 PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28524 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 28525 IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 28526 } 28527 28528 28529 # EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-512-1) 28530 { 28531 ICLASS: VCVTTPD2UQQ 28532 CPL: 3 28533 CATEGORY: CONVERT 28534 EXTENSION: AVX512EVEX 28535 ISA_SET: AVX512DQ_512 28536 EXCEPTIONS: AVX512-E2 28537 REAL_OPCODE: Y 28538 ATTRIBUTES: MASKOP_EVEX MXCSR 28539 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 28540 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 28541 IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 28542 } 28543 28544 { 28545 ICLASS: VCVTTPD2UQQ 28546 CPL: 3 28547 CATEGORY: CONVERT 28548 EXTENSION: AVX512EVEX 28549 ISA_SET: AVX512DQ_512 28550 EXCEPTIONS: AVX512-E2 28551 REAL_OPCODE: Y 28552 ATTRIBUTES: MASKOP_EVEX MXCSR 28553 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR 28554 OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 28555 IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 28556 } 28557 28558 { 28559 ICLASS: VCVTTPD2UQQ 28560 CPL: 3 28561 CATEGORY: CONVERT 28562 EXTENSION: AVX512EVEX 28563 ISA_SET: AVX512DQ_512 28564 EXCEPTIONS: AVX512-E2 28565 REAL_OPCODE: Y 28566 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28567 PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 28568 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 28569 IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 28570 } 28571 28572 28573 # EMITTING VCVTTPS2DQ (VCVTTPS2DQ-128-1) 28574 { 28575 ICLASS: VCVTTPS2DQ 28576 CPL: 3 28577 CATEGORY: CONVERT 28578 EXTENSION: AVX512EVEX 28579 ISA_SET: AVX512F_128 28580 EXCEPTIONS: AVX512-E2 28581 REAL_OPCODE: Y 28582 ATTRIBUTES: MASKOP_EVEX MXCSR 28583 PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 28584 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 28585 IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 28586 } 28587 28588 { 28589 ICLASS: VCVTTPS2DQ 28590 CPL: 3 28591 CATEGORY: CONVERT 28592 EXTENSION: AVX512EVEX 28593 ISA_SET: AVX512F_128 28594 EXCEPTIONS: AVX512-E2 28595 REAL_OPCODE: Y 28596 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28597 PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 28598 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 28599 IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 28600 } 28601 28602 28603 # EMITTING VCVTTPS2DQ (VCVTTPS2DQ-256-1) 28604 { 28605 ICLASS: VCVTTPS2DQ 28606 CPL: 3 28607 CATEGORY: CONVERT 28608 EXTENSION: AVX512EVEX 28609 ISA_SET: AVX512F_256 28610 EXCEPTIONS: AVX512-E2 28611 REAL_OPCODE: Y 28612 ATTRIBUTES: MASKOP_EVEX MXCSR 28613 PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 28614 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 28615 IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 28616 } 28617 28618 { 28619 ICLASS: VCVTTPS2DQ 28620 CPL: 3 28621 CATEGORY: CONVERT 28622 EXTENSION: AVX512EVEX 28623 ISA_SET: AVX512F_256 28624 EXCEPTIONS: AVX512-E2 28625 REAL_OPCODE: Y 28626 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28627 PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 28628 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 28629 IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 28630 } 28631 28632 28633 # EMITTING VCVTTPS2QQ (VCVTTPS2QQ-128-1) 28634 { 28635 ICLASS: VCVTTPS2QQ 28636 CPL: 3 28637 CATEGORY: CONVERT 28638 EXTENSION: AVX512EVEX 28639 ISA_SET: AVX512DQ_128 28640 EXCEPTIONS: AVX512-E3 28641 REAL_OPCODE: Y 28642 ATTRIBUTES: MASKOP_EVEX MXCSR 28643 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 28644 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 28645 IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 28646 } 28647 28648 { 28649 ICLASS: VCVTTPS2QQ 28650 CPL: 3 28651 CATEGORY: CONVERT 28652 EXTENSION: AVX512EVEX 28653 ISA_SET: AVX512DQ_128 28654 EXCEPTIONS: AVX512-E3 28655 REAL_OPCODE: Y 28656 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 28657 PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 28658 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 28659 IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 28660 } 28661 28662 28663 # EMITTING VCVTTPS2QQ (VCVTTPS2QQ-256-1) 28664 { 28665 ICLASS: VCVTTPS2QQ 28666 CPL: 3 28667 CATEGORY: CONVERT 28668 EXTENSION: AVX512EVEX 28669 ISA_SET: AVX512DQ_256 28670 EXCEPTIONS: AVX512-E3 28671 REAL_OPCODE: Y 28672 ATTRIBUTES: MASKOP_EVEX MXCSR 28673 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 28674 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 28675 IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 28676 } 28677 28678 { 28679 ICLASS: VCVTTPS2QQ 28680 CPL: 3 28681 CATEGORY: CONVERT 28682 EXTENSION: AVX512EVEX 28683 ISA_SET: AVX512DQ_256 28684 EXCEPTIONS: AVX512-E3 28685 REAL_OPCODE: Y 28686 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 28687 PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 28688 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 28689 IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 28690 } 28691 28692 28693 # EMITTING VCVTTPS2QQ (VCVTTPS2QQ-512-1) 28694 { 28695 ICLASS: VCVTTPS2QQ 28696 CPL: 3 28697 CATEGORY: CONVERT 28698 EXTENSION: AVX512EVEX 28699 ISA_SET: AVX512DQ_512 28700 EXCEPTIONS: AVX512-E3 28701 REAL_OPCODE: Y 28702 ATTRIBUTES: MASKOP_EVEX MXCSR 28703 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 28704 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 28705 IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 28706 } 28707 28708 { 28709 ICLASS: VCVTTPS2QQ 28710 CPL: 3 28711 CATEGORY: CONVERT 28712 EXTENSION: AVX512EVEX 28713 ISA_SET: AVX512DQ_512 28714 EXCEPTIONS: AVX512-E3 28715 REAL_OPCODE: Y 28716 ATTRIBUTES: MASKOP_EVEX MXCSR 28717 PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 28718 OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 28719 IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 28720 } 28721 28722 { 28723 ICLASS: VCVTTPS2QQ 28724 CPL: 3 28725 CATEGORY: CONVERT 28726 EXTENSION: AVX512EVEX 28727 ISA_SET: AVX512DQ_512 28728 EXCEPTIONS: AVX512-E3 28729 REAL_OPCODE: Y 28730 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 28731 PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 28732 OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 28733 IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 28734 } 28735 28736 28737 # EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-128-1) 28738 { 28739 ICLASS: VCVTTPS2UDQ 28740 CPL: 3 28741 CATEGORY: CONVERT 28742 EXTENSION: AVX512EVEX 28743 ISA_SET: AVX512F_128 28744 EXCEPTIONS: AVX512-E2 28745 REAL_OPCODE: Y 28746 ATTRIBUTES: MASKOP_EVEX MXCSR 28747 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 28748 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 28749 IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 28750 } 28751 28752 { 28753 ICLASS: VCVTTPS2UDQ 28754 CPL: 3 28755 CATEGORY: CONVERT 28756 EXTENSION: AVX512EVEX 28757 ISA_SET: AVX512F_128 28758 EXCEPTIONS: AVX512-E2 28759 REAL_OPCODE: Y 28760 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28761 PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 28762 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 28763 IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 28764 } 28765 28766 28767 # EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-256-1) 28768 { 28769 ICLASS: VCVTTPS2UDQ 28770 CPL: 3 28771 CATEGORY: CONVERT 28772 EXTENSION: AVX512EVEX 28773 ISA_SET: AVX512F_256 28774 EXCEPTIONS: AVX512-E2 28775 REAL_OPCODE: Y 28776 ATTRIBUTES: MASKOP_EVEX MXCSR 28777 PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 28778 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 28779 IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 28780 } 28781 28782 { 28783 ICLASS: VCVTTPS2UDQ 28784 CPL: 3 28785 CATEGORY: CONVERT 28786 EXTENSION: AVX512EVEX 28787 ISA_SET: AVX512F_256 28788 EXCEPTIONS: AVX512-E2 28789 REAL_OPCODE: Y 28790 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28791 PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 28792 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 28793 IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 28794 } 28795 28796 28797 # EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-128-1) 28798 { 28799 ICLASS: VCVTTPS2UQQ 28800 CPL: 3 28801 CATEGORY: CONVERT 28802 EXTENSION: AVX512EVEX 28803 ISA_SET: AVX512DQ_128 28804 EXCEPTIONS: AVX512-E3 28805 REAL_OPCODE: Y 28806 ATTRIBUTES: MASKOP_EVEX MXCSR 28807 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 28808 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 28809 IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 28810 } 28811 28812 { 28813 ICLASS: VCVTTPS2UQQ 28814 CPL: 3 28815 CATEGORY: CONVERT 28816 EXTENSION: AVX512EVEX 28817 ISA_SET: AVX512DQ_128 28818 EXCEPTIONS: AVX512-E3 28819 REAL_OPCODE: Y 28820 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 28821 PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 28822 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 28823 IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 28824 } 28825 28826 28827 # EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-256-1) 28828 { 28829 ICLASS: VCVTTPS2UQQ 28830 CPL: 3 28831 CATEGORY: CONVERT 28832 EXTENSION: AVX512EVEX 28833 ISA_SET: AVX512DQ_256 28834 EXCEPTIONS: AVX512-E3 28835 REAL_OPCODE: Y 28836 ATTRIBUTES: MASKOP_EVEX MXCSR 28837 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 28838 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 28839 IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 28840 } 28841 28842 { 28843 ICLASS: VCVTTPS2UQQ 28844 CPL: 3 28845 CATEGORY: CONVERT 28846 EXTENSION: AVX512EVEX 28847 ISA_SET: AVX512DQ_256 28848 EXCEPTIONS: AVX512-E3 28849 REAL_OPCODE: Y 28850 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 28851 PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 28852 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 28853 IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 28854 } 28855 28856 28857 # EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-512-1) 28858 { 28859 ICLASS: VCVTTPS2UQQ 28860 CPL: 3 28861 CATEGORY: CONVERT 28862 EXTENSION: AVX512EVEX 28863 ISA_SET: AVX512DQ_512 28864 EXCEPTIONS: AVX512-E3 28865 REAL_OPCODE: Y 28866 ATTRIBUTES: MASKOP_EVEX MXCSR 28867 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 28868 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 28869 IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 28870 } 28871 28872 { 28873 ICLASS: VCVTTPS2UQQ 28874 CPL: 3 28875 CATEGORY: CONVERT 28876 EXTENSION: AVX512EVEX 28877 ISA_SET: AVX512DQ_512 28878 EXCEPTIONS: AVX512-E3 28879 REAL_OPCODE: Y 28880 ATTRIBUTES: MASKOP_EVEX MXCSR 28881 PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR 28882 OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 28883 IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 28884 } 28885 28886 { 28887 ICLASS: VCVTTPS2UQQ 28888 CPL: 3 28889 CATEGORY: CONVERT 28890 EXTENSION: AVX512EVEX 28891 ISA_SET: AVX512DQ_512 28892 EXCEPTIONS: AVX512-E3 28893 REAL_OPCODE: Y 28894 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED 28895 PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 28896 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 28897 IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 28898 } 28899 28900 28901 # EMITTING VCVTUDQ2PD (VCVTUDQ2PD-128-1) 28902 { 28903 ICLASS: VCVTUDQ2PD 28904 CPL: 3 28905 CATEGORY: CONVERT 28906 EXTENSION: AVX512EVEX 28907 ISA_SET: AVX512F_128 28908 EXCEPTIONS: AVX512-E5 28909 REAL_OPCODE: Y 28910 ATTRIBUTES: MASKOP_EVEX 28911 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 28912 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 28913 IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 28914 } 28915 28916 { 28917 ICLASS: VCVTUDQ2PD 28918 CPL: 3 28919 CATEGORY: CONVERT 28920 EXTENSION: AVX512EVEX 28921 ISA_SET: AVX512F_128 28922 EXCEPTIONS: AVX512-E5 28923 REAL_OPCODE: Y 28924 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 28925 PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 28926 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 28927 IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 28928 } 28929 28930 28931 # EMITTING VCVTUDQ2PD (VCVTUDQ2PD-256-1) 28932 { 28933 ICLASS: VCVTUDQ2PD 28934 CPL: 3 28935 CATEGORY: CONVERT 28936 EXTENSION: AVX512EVEX 28937 ISA_SET: AVX512F_256 28938 EXCEPTIONS: AVX512-E5 28939 REAL_OPCODE: Y 28940 ATTRIBUTES: MASKOP_EVEX 28941 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 28942 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 28943 IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 28944 } 28945 28946 { 28947 ICLASS: VCVTUDQ2PD 28948 CPL: 3 28949 CATEGORY: CONVERT 28950 EXTENSION: AVX512EVEX 28951 ISA_SET: AVX512F_256 28952 EXCEPTIONS: AVX512-E5 28953 REAL_OPCODE: Y 28954 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED 28955 PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() 28956 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 28957 IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 28958 } 28959 28960 28961 # EMITTING VCVTUDQ2PS (VCVTUDQ2PS-128-1) 28962 { 28963 ICLASS: VCVTUDQ2PS 28964 CPL: 3 28965 CATEGORY: CONVERT 28966 EXTENSION: AVX512EVEX 28967 ISA_SET: AVX512F_128 28968 EXCEPTIONS: AVX512-E2 28969 REAL_OPCODE: Y 28970 ATTRIBUTES: MASKOP_EVEX MXCSR 28971 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 28972 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 28973 IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 28974 } 28975 28976 { 28977 ICLASS: VCVTUDQ2PS 28978 CPL: 3 28979 CATEGORY: CONVERT 28980 EXTENSION: AVX512EVEX 28981 ISA_SET: AVX512F_128 28982 EXCEPTIONS: AVX512-E2 28983 REAL_OPCODE: Y 28984 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 28985 PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 28986 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 28987 IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 28988 } 28989 28990 28991 # EMITTING VCVTUDQ2PS (VCVTUDQ2PS-256-1) 28992 { 28993 ICLASS: VCVTUDQ2PS 28994 CPL: 3 28995 CATEGORY: CONVERT 28996 EXTENSION: AVX512EVEX 28997 ISA_SET: AVX512F_256 28998 EXCEPTIONS: AVX512-E2 28999 REAL_OPCODE: Y 29000 ATTRIBUTES: MASKOP_EVEX MXCSR 29001 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 29002 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 29003 IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 29004 } 29005 29006 { 29007 ICLASS: VCVTUDQ2PS 29008 CPL: 3 29009 CATEGORY: CONVERT 29010 EXTENSION: AVX512EVEX 29011 ISA_SET: AVX512F_256 29012 EXCEPTIONS: AVX512-E2 29013 REAL_OPCODE: Y 29014 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29015 PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 29016 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 29017 IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 29018 } 29019 29020 29021 # EMITTING VCVTUQQ2PD (VCVTUQQ2PD-128-1) 29022 { 29023 ICLASS: VCVTUQQ2PD 29024 CPL: 3 29025 CATEGORY: CONVERT 29026 EXTENSION: AVX512EVEX 29027 ISA_SET: AVX512DQ_128 29028 EXCEPTIONS: AVX512-E2 29029 REAL_OPCODE: Y 29030 ATTRIBUTES: MASKOP_EVEX MXCSR 29031 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 29032 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 29033 IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 29034 } 29035 29036 { 29037 ICLASS: VCVTUQQ2PD 29038 CPL: 3 29039 CATEGORY: CONVERT 29040 EXTENSION: AVX512EVEX 29041 ISA_SET: AVX512DQ_128 29042 EXCEPTIONS: AVX512-E2 29043 REAL_OPCODE: Y 29044 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29045 PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 29046 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 29047 IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 29048 } 29049 29050 29051 # EMITTING VCVTUQQ2PD (VCVTUQQ2PD-256-1) 29052 { 29053 ICLASS: VCVTUQQ2PD 29054 CPL: 3 29055 CATEGORY: CONVERT 29056 EXTENSION: AVX512EVEX 29057 ISA_SET: AVX512DQ_256 29058 EXCEPTIONS: AVX512-E2 29059 REAL_OPCODE: Y 29060 ATTRIBUTES: MASKOP_EVEX MXCSR 29061 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 29062 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 29063 IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 29064 } 29065 29066 { 29067 ICLASS: VCVTUQQ2PD 29068 CPL: 3 29069 CATEGORY: CONVERT 29070 EXTENSION: AVX512EVEX 29071 ISA_SET: AVX512DQ_256 29072 EXCEPTIONS: AVX512-E2 29073 REAL_OPCODE: Y 29074 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29075 PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 29076 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 29077 IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 29078 } 29079 29080 29081 # EMITTING VCVTUQQ2PD (VCVTUQQ2PD-512-1) 29082 { 29083 ICLASS: VCVTUQQ2PD 29084 CPL: 3 29085 CATEGORY: CONVERT 29086 EXTENSION: AVX512EVEX 29087 ISA_SET: AVX512DQ_512 29088 EXCEPTIONS: AVX512-E2 29089 REAL_OPCODE: Y 29090 ATTRIBUTES: MASKOP_EVEX MXCSR 29091 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 29092 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 29093 IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 29094 } 29095 29096 { 29097 ICLASS: VCVTUQQ2PD 29098 CPL: 3 29099 CATEGORY: CONVERT 29100 EXTENSION: AVX512EVEX 29101 ISA_SET: AVX512DQ_512 29102 EXCEPTIONS: AVX512-E2 29103 REAL_OPCODE: Y 29104 ATTRIBUTES: MASKOP_EVEX MXCSR 29105 PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 29106 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 29107 IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 29108 } 29109 29110 { 29111 ICLASS: VCVTUQQ2PD 29112 CPL: 3 29113 CATEGORY: CONVERT 29114 EXTENSION: AVX512EVEX 29115 ISA_SET: AVX512DQ_512 29116 EXCEPTIONS: AVX512-E2 29117 REAL_OPCODE: Y 29118 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29119 PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 29120 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 29121 IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 29122 } 29123 29124 29125 # EMITTING VCVTUQQ2PS (VCVTUQQ2PS-128-1) 29126 { 29127 ICLASS: VCVTUQQ2PS 29128 CPL: 3 29129 CATEGORY: CONVERT 29130 EXTENSION: AVX512EVEX 29131 ISA_SET: AVX512DQ_128 29132 EXCEPTIONS: AVX512-E2 29133 REAL_OPCODE: Y 29134 ATTRIBUTES: MASKOP_EVEX MXCSR 29135 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 29136 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 29137 IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 29138 } 29139 29140 { 29141 ICLASS: VCVTUQQ2PS 29142 CPL: 3 29143 CATEGORY: CONVERT 29144 EXTENSION: AVX512EVEX 29145 ISA_SET: AVX512DQ_128 29146 EXCEPTIONS: AVX512-E2 29147 REAL_OPCODE: Y 29148 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29149 PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 29150 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 29151 IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 29152 } 29153 29154 29155 # EMITTING VCVTUQQ2PS (VCVTUQQ2PS-256-1) 29156 { 29157 ICLASS: VCVTUQQ2PS 29158 CPL: 3 29159 CATEGORY: CONVERT 29160 EXTENSION: AVX512EVEX 29161 ISA_SET: AVX512DQ_256 29162 EXCEPTIONS: AVX512-E2 29163 REAL_OPCODE: Y 29164 ATTRIBUTES: MASKOP_EVEX MXCSR 29165 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 29166 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 29167 IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 29168 } 29169 29170 { 29171 ICLASS: VCVTUQQ2PS 29172 CPL: 3 29173 CATEGORY: CONVERT 29174 EXTENSION: AVX512EVEX 29175 ISA_SET: AVX512DQ_256 29176 EXCEPTIONS: AVX512-E2 29177 REAL_OPCODE: Y 29178 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29179 PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 29180 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 29181 IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 29182 } 29183 29184 29185 # EMITTING VCVTUQQ2PS (VCVTUQQ2PS-512-1) 29186 { 29187 ICLASS: VCVTUQQ2PS 29188 CPL: 3 29189 CATEGORY: CONVERT 29190 EXTENSION: AVX512EVEX 29191 ISA_SET: AVX512DQ_512 29192 EXCEPTIONS: AVX512-E2 29193 REAL_OPCODE: Y 29194 ATTRIBUTES: MASKOP_EVEX MXCSR 29195 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 29196 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 29197 IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 29198 } 29199 29200 { 29201 ICLASS: VCVTUQQ2PS 29202 CPL: 3 29203 CATEGORY: CONVERT 29204 EXTENSION: AVX512EVEX 29205 ISA_SET: AVX512DQ_512 29206 EXCEPTIONS: AVX512-E2 29207 REAL_OPCODE: Y 29208 ATTRIBUTES: MASKOP_EVEX MXCSR 29209 PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR 29210 OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 29211 IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 29212 } 29213 29214 { 29215 ICLASS: VCVTUQQ2PS 29216 CPL: 3 29217 CATEGORY: CONVERT 29218 EXTENSION: AVX512EVEX 29219 ISA_SET: AVX512DQ_512 29220 EXCEPTIONS: AVX512-E2 29221 REAL_OPCODE: Y 29222 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29223 PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 29224 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 29225 IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 29226 } 29227 29228 29229 # EMITTING VDBPSADBW (VDBPSADBW-128-1) 29230 { 29231 ICLASS: VDBPSADBW 29232 CPL: 3 29233 CATEGORY: AVX512 29234 EXTENSION: AVX512EVEX 29235 ISA_SET: AVX512BW_128 29236 EXCEPTIONS: AVX512-E4 29237 REAL_OPCODE: Y 29238 ATTRIBUTES: MASKOP_EVEX 29239 PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 29240 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b 29241 IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 29242 } 29243 29244 { 29245 ICLASS: VDBPSADBW 29246 CPL: 3 29247 CATEGORY: AVX512 29248 EXTENSION: AVX512EVEX 29249 ISA_SET: AVX512BW_128 29250 EXCEPTIONS: AVX512-E4 29251 REAL_OPCODE: Y 29252 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 29253 PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 29254 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b 29255 IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 29256 } 29257 29258 29259 # EMITTING VDBPSADBW (VDBPSADBW-256-1) 29260 { 29261 ICLASS: VDBPSADBW 29262 CPL: 3 29263 CATEGORY: AVX512 29264 EXTENSION: AVX512EVEX 29265 ISA_SET: AVX512BW_256 29266 EXCEPTIONS: AVX512-E4 29267 REAL_OPCODE: Y 29268 ATTRIBUTES: MASKOP_EVEX 29269 PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 29270 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b 29271 IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 29272 } 29273 29274 { 29275 ICLASS: VDBPSADBW 29276 CPL: 3 29277 CATEGORY: AVX512 29278 EXTENSION: AVX512EVEX 29279 ISA_SET: AVX512BW_256 29280 EXCEPTIONS: AVX512-E4 29281 REAL_OPCODE: Y 29282 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 29283 PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 29284 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b 29285 IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 29286 } 29287 29288 29289 # EMITTING VDBPSADBW (VDBPSADBW-512-1) 29290 { 29291 ICLASS: VDBPSADBW 29292 CPL: 3 29293 CATEGORY: AVX512 29294 EXTENSION: AVX512EVEX 29295 ISA_SET: AVX512BW_512 29296 EXCEPTIONS: AVX512-E4 29297 REAL_OPCODE: Y 29298 ATTRIBUTES: MASKOP_EVEX 29299 PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 29300 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b 29301 IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 29302 } 29303 29304 { 29305 ICLASS: VDBPSADBW 29306 CPL: 3 29307 CATEGORY: AVX512 29308 EXTENSION: AVX512EVEX 29309 ISA_SET: AVX512BW_512 29310 EXCEPTIONS: AVX512-E4 29311 REAL_OPCODE: Y 29312 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 29313 PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 29314 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b 29315 IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 29316 } 29317 29318 29319 # EMITTING VDIVPD (VDIVPD-128-1) 29320 { 29321 ICLASS: VDIVPD 29322 CPL: 3 29323 CATEGORY: AVX512 29324 EXTENSION: AVX512EVEX 29325 ISA_SET: AVX512F_128 29326 EXCEPTIONS: AVX512-E2 29327 REAL_OPCODE: Y 29328 ATTRIBUTES: MASKOP_EVEX MXCSR 29329 PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 29330 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 29331 IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 29332 } 29333 29334 { 29335 ICLASS: VDIVPD 29336 CPL: 3 29337 CATEGORY: AVX512 29338 EXTENSION: AVX512EVEX 29339 ISA_SET: AVX512F_128 29340 EXCEPTIONS: AVX512-E2 29341 REAL_OPCODE: Y 29342 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29343 PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 29344 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 29345 IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 29346 } 29347 29348 29349 # EMITTING VDIVPD (VDIVPD-256-1) 29350 { 29351 ICLASS: VDIVPD 29352 CPL: 3 29353 CATEGORY: AVX512 29354 EXTENSION: AVX512EVEX 29355 ISA_SET: AVX512F_256 29356 EXCEPTIONS: AVX512-E2 29357 REAL_OPCODE: Y 29358 ATTRIBUTES: MASKOP_EVEX MXCSR 29359 PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 29360 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 29361 IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 29362 } 29363 29364 { 29365 ICLASS: VDIVPD 29366 CPL: 3 29367 CATEGORY: AVX512 29368 EXTENSION: AVX512EVEX 29369 ISA_SET: AVX512F_256 29370 EXCEPTIONS: AVX512-E2 29371 REAL_OPCODE: Y 29372 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29373 PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 29374 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 29375 IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 29376 } 29377 29378 29379 # EMITTING VDIVPS (VDIVPS-128-1) 29380 { 29381 ICLASS: VDIVPS 29382 CPL: 3 29383 CATEGORY: AVX512 29384 EXTENSION: AVX512EVEX 29385 ISA_SET: AVX512F_128 29386 EXCEPTIONS: AVX512-E2 29387 REAL_OPCODE: Y 29388 ATTRIBUTES: MASKOP_EVEX MXCSR 29389 PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 29390 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 29391 IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 29392 } 29393 29394 { 29395 ICLASS: VDIVPS 29396 CPL: 3 29397 CATEGORY: AVX512 29398 EXTENSION: AVX512EVEX 29399 ISA_SET: AVX512F_128 29400 EXCEPTIONS: AVX512-E2 29401 REAL_OPCODE: Y 29402 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29403 PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 29404 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 29405 IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 29406 } 29407 29408 29409 # EMITTING VDIVPS (VDIVPS-256-1) 29410 { 29411 ICLASS: VDIVPS 29412 CPL: 3 29413 CATEGORY: AVX512 29414 EXTENSION: AVX512EVEX 29415 ISA_SET: AVX512F_256 29416 EXCEPTIONS: AVX512-E2 29417 REAL_OPCODE: Y 29418 ATTRIBUTES: MASKOP_EVEX MXCSR 29419 PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 29420 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 29421 IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 29422 } 29423 29424 { 29425 ICLASS: VDIVPS 29426 CPL: 3 29427 CATEGORY: AVX512 29428 EXTENSION: AVX512EVEX 29429 ISA_SET: AVX512F_256 29430 EXCEPTIONS: AVX512-E2 29431 REAL_OPCODE: Y 29432 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29433 PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 29434 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 29435 IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 29436 } 29437 29438 29439 # EMITTING VEXPANDPD (VEXPANDPD-128-1) 29440 { 29441 ICLASS: VEXPANDPD 29442 CPL: 3 29443 CATEGORY: EXPAND 29444 EXTENSION: AVX512EVEX 29445 ISA_SET: AVX512F_128 29446 EXCEPTIONS: AVX512-E4 29447 REAL_OPCODE: Y 29448 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 29449 PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() 29450 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 29451 IFORM: VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 29452 } 29453 29454 29455 # EMITTING VEXPANDPD (VEXPANDPD-128-2) 29456 { 29457 ICLASS: VEXPANDPD 29458 CPL: 3 29459 CATEGORY: EXPAND 29460 EXTENSION: AVX512EVEX 29461 ISA_SET: AVX512F_128 29462 EXCEPTIONS: AVX512-E4 29463 REAL_OPCODE: Y 29464 ATTRIBUTES: MASKOP_EVEX 29465 PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 29466 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 29467 IFORM: VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 29468 } 29469 29470 29471 # EMITTING VEXPANDPD (VEXPANDPD-256-1) 29472 { 29473 ICLASS: VEXPANDPD 29474 CPL: 3 29475 CATEGORY: EXPAND 29476 EXTENSION: AVX512EVEX 29477 ISA_SET: AVX512F_256 29478 EXCEPTIONS: AVX512-E4 29479 REAL_OPCODE: Y 29480 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 29481 PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() 29482 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 29483 IFORM: VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 29484 } 29485 29486 29487 # EMITTING VEXPANDPD (VEXPANDPD-256-2) 29488 { 29489 ICLASS: VEXPANDPD 29490 CPL: 3 29491 CATEGORY: EXPAND 29492 EXTENSION: AVX512EVEX 29493 ISA_SET: AVX512F_256 29494 EXCEPTIONS: AVX512-E4 29495 REAL_OPCODE: Y 29496 ATTRIBUTES: MASKOP_EVEX 29497 PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 29498 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 29499 IFORM: VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 29500 } 29501 29502 29503 # EMITTING VEXPANDPS (VEXPANDPS-128-1) 29504 { 29505 ICLASS: VEXPANDPS 29506 CPL: 3 29507 CATEGORY: EXPAND 29508 EXTENSION: AVX512EVEX 29509 ISA_SET: AVX512F_128 29510 EXCEPTIONS: AVX512-E4 29511 REAL_OPCODE: Y 29512 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 29513 PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() 29514 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 29515 IFORM: VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 29516 } 29517 29518 29519 # EMITTING VEXPANDPS (VEXPANDPS-128-2) 29520 { 29521 ICLASS: VEXPANDPS 29522 CPL: 3 29523 CATEGORY: EXPAND 29524 EXTENSION: AVX512EVEX 29525 ISA_SET: AVX512F_128 29526 EXCEPTIONS: AVX512-E4 29527 REAL_OPCODE: Y 29528 ATTRIBUTES: MASKOP_EVEX 29529 PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 29530 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 29531 IFORM: VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 29532 } 29533 29534 29535 # EMITTING VEXPANDPS (VEXPANDPS-256-1) 29536 { 29537 ICLASS: VEXPANDPS 29538 CPL: 3 29539 CATEGORY: EXPAND 29540 EXTENSION: AVX512EVEX 29541 ISA_SET: AVX512F_256 29542 EXCEPTIONS: AVX512-E4 29543 REAL_OPCODE: Y 29544 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 29545 PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() 29546 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 29547 IFORM: VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 29548 } 29549 29550 29551 # EMITTING VEXPANDPS (VEXPANDPS-256-2) 29552 { 29553 ICLASS: VEXPANDPS 29554 CPL: 3 29555 CATEGORY: EXPAND 29556 EXTENSION: AVX512EVEX 29557 ISA_SET: AVX512F_256 29558 EXCEPTIONS: AVX512-E4 29559 REAL_OPCODE: Y 29560 ATTRIBUTES: MASKOP_EVEX 29561 PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 29562 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 29563 IFORM: VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 29564 } 29565 29566 29567 # EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-1) 29568 { 29569 ICLASS: VEXTRACTF32X4 29570 CPL: 3 29571 CATEGORY: AVX512 29572 EXTENSION: AVX512EVEX 29573 ISA_SET: AVX512F_256 29574 EXCEPTIONS: AVX512-E6NF 29575 REAL_OPCODE: Y 29576 ATTRIBUTES: MASKOP_EVEX 29577 PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 29578 OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b 29579 IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 29580 } 29581 29582 29583 # EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-2) 29584 { 29585 ICLASS: VEXTRACTF32X4 29586 CPL: 3 29587 CATEGORY: AVX512 29588 EXTENSION: AVX512EVEX 29589 ISA_SET: AVX512F_256 29590 EXCEPTIONS: AVX512-E6NF 29591 REAL_OPCODE: Y 29592 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 29593 PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 29594 OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b 29595 IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 29596 } 29597 29598 29599 # EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-1) 29600 { 29601 ICLASS: VEXTRACTF32X8 29602 CPL: 3 29603 CATEGORY: AVX512 29604 EXTENSION: AVX512EVEX 29605 ISA_SET: AVX512DQ_512 29606 EXCEPTIONS: AVX512-E6NF 29607 REAL_OPCODE: Y 29608 ATTRIBUTES: MASKOP_EVEX 29609 PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 29610 OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b 29611 IFORM: VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 29612 } 29613 29614 29615 # EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-2) 29616 { 29617 ICLASS: VEXTRACTF32X8 29618 CPL: 3 29619 CATEGORY: AVX512 29620 EXTENSION: AVX512EVEX 29621 ISA_SET: AVX512DQ_512 29622 EXCEPTIONS: AVX512-E6NF 29623 REAL_OPCODE: Y 29624 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 29625 PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() 29626 OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b 29627 IFORM: VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 29628 } 29629 29630 29631 # EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-1) 29632 { 29633 ICLASS: VEXTRACTF64X2 29634 CPL: 3 29635 CATEGORY: AVX512 29636 EXTENSION: AVX512EVEX 29637 ISA_SET: AVX512DQ_256 29638 EXCEPTIONS: AVX512-E6NF 29639 REAL_OPCODE: Y 29640 ATTRIBUTES: MASKOP_EVEX 29641 PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 29642 OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 IMM0:r:b 29643 IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 29644 } 29645 29646 29647 # EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-2) 29648 { 29649 ICLASS: VEXTRACTF64X2 29650 CPL: 3 29651 CATEGORY: AVX512 29652 EXTENSION: AVX512EVEX 29653 ISA_SET: AVX512DQ_256 29654 EXCEPTIONS: AVX512-E6NF 29655 REAL_OPCODE: Y 29656 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 29657 PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 29658 OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 IMM0:r:b 29659 IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 29660 } 29661 29662 29663 # EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-1) 29664 { 29665 ICLASS: VEXTRACTF64X2 29666 CPL: 3 29667 CATEGORY: AVX512 29668 EXTENSION: AVX512EVEX 29669 ISA_SET: AVX512DQ_512 29670 EXCEPTIONS: AVX512-E6NF 29671 REAL_OPCODE: Y 29672 ATTRIBUTES: MASKOP_EVEX 29673 PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 29674 OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b 29675 IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 29676 } 29677 29678 29679 # EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-2) 29680 { 29681 ICLASS: VEXTRACTF64X2 29682 CPL: 3 29683 CATEGORY: AVX512 29684 EXTENSION: AVX512EVEX 29685 ISA_SET: AVX512DQ_512 29686 EXCEPTIONS: AVX512-E6NF 29687 REAL_OPCODE: Y 29688 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 29689 PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 29690 OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b 29691 IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 29692 } 29693 29694 29695 # EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-1) 29696 { 29697 ICLASS: VEXTRACTI32X4 29698 CPL: 3 29699 CATEGORY: AVX512 29700 EXTENSION: AVX512EVEX 29701 ISA_SET: AVX512F_256 29702 EXCEPTIONS: AVX512-E6NF 29703 REAL_OPCODE: Y 29704 ATTRIBUTES: MASKOP_EVEX 29705 PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 29706 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 IMM0:r:b 29707 IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 29708 } 29709 29710 29711 # EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-2) 29712 { 29713 ICLASS: VEXTRACTI32X4 29714 CPL: 3 29715 CATEGORY: AVX512 29716 EXTENSION: AVX512EVEX 29717 ISA_SET: AVX512F_256 29718 EXCEPTIONS: AVX512-E6NF 29719 REAL_OPCODE: Y 29720 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 29721 PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 29722 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 IMM0:r:b 29723 IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 29724 } 29725 29726 29727 # EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-1) 29728 { 29729 ICLASS: VEXTRACTI32X8 29730 CPL: 3 29731 CATEGORY: AVX512 29732 EXTENSION: AVX512EVEX 29733 ISA_SET: AVX512DQ_512 29734 EXCEPTIONS: AVX512-E6NF 29735 REAL_OPCODE: Y 29736 ATTRIBUTES: MASKOP_EVEX 29737 PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 29738 OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b 29739 IFORM: VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 29740 } 29741 29742 29743 # EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-2) 29744 { 29745 ICLASS: VEXTRACTI32X8 29746 CPL: 3 29747 CATEGORY: AVX512 29748 EXTENSION: AVX512EVEX 29749 ISA_SET: AVX512DQ_512 29750 EXCEPTIONS: AVX512-E6NF 29751 REAL_OPCODE: Y 29752 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 29753 PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() 29754 OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b 29755 IFORM: VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 29756 } 29757 29758 29759 # EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-1) 29760 { 29761 ICLASS: VEXTRACTI64X2 29762 CPL: 3 29763 CATEGORY: AVX512 29764 EXTENSION: AVX512EVEX 29765 ISA_SET: AVX512DQ_256 29766 EXCEPTIONS: AVX512-E6NF 29767 REAL_OPCODE: Y 29768 ATTRIBUTES: MASKOP_EVEX 29769 PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 29770 OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 IMM0:r:b 29771 IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 29772 } 29773 29774 29775 # EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-2) 29776 { 29777 ICLASS: VEXTRACTI64X2 29778 CPL: 3 29779 CATEGORY: AVX512 29780 EXTENSION: AVX512EVEX 29781 ISA_SET: AVX512DQ_256 29782 EXCEPTIONS: AVX512-E6NF 29783 REAL_OPCODE: Y 29784 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 29785 PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 29786 OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 IMM0:r:b 29787 IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 29788 } 29789 29790 29791 # EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-1) 29792 { 29793 ICLASS: VEXTRACTI64X2 29794 CPL: 3 29795 CATEGORY: AVX512 29796 EXTENSION: AVX512EVEX 29797 ISA_SET: AVX512DQ_512 29798 EXCEPTIONS: AVX512-E6NF 29799 REAL_OPCODE: Y 29800 ATTRIBUTES: MASKOP_EVEX 29801 PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 29802 OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b 29803 IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 29804 } 29805 29806 29807 # EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-2) 29808 { 29809 ICLASS: VEXTRACTI64X2 29810 CPL: 3 29811 CATEGORY: AVX512 29812 EXTENSION: AVX512EVEX 29813 ISA_SET: AVX512DQ_512 29814 EXCEPTIONS: AVX512-E6NF 29815 REAL_OPCODE: Y 29816 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 29817 PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 29818 OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b 29819 IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 29820 } 29821 29822 29823 # EMITTING VFIXUPIMMPD (VFIXUPIMMPD-128-1) 29824 { 29825 ICLASS: VFIXUPIMMPD 29826 CPL: 3 29827 CATEGORY: AVX512 29828 EXTENSION: AVX512EVEX 29829 ISA_SET: AVX512F_128 29830 EXCEPTIONS: AVX512-E2 29831 REAL_OPCODE: Y 29832 ATTRIBUTES: MASKOP_EVEX MXCSR 29833 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 29834 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 29835 IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 29836 } 29837 29838 { 29839 ICLASS: VFIXUPIMMPD 29840 CPL: 3 29841 CATEGORY: AVX512 29842 EXTENSION: AVX512EVEX 29843 ISA_SET: AVX512F_128 29844 EXCEPTIONS: AVX512-E2 29845 REAL_OPCODE: Y 29846 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29847 PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 29848 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 29849 IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 29850 } 29851 29852 29853 # EMITTING VFIXUPIMMPD (VFIXUPIMMPD-256-1) 29854 { 29855 ICLASS: VFIXUPIMMPD 29856 CPL: 3 29857 CATEGORY: AVX512 29858 EXTENSION: AVX512EVEX 29859 ISA_SET: AVX512F_256 29860 EXCEPTIONS: AVX512-E2 29861 REAL_OPCODE: Y 29862 ATTRIBUTES: MASKOP_EVEX MXCSR 29863 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 29864 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b 29865 IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 29866 } 29867 29868 { 29869 ICLASS: VFIXUPIMMPD 29870 CPL: 3 29871 CATEGORY: AVX512 29872 EXTENSION: AVX512EVEX 29873 ISA_SET: AVX512F_256 29874 EXCEPTIONS: AVX512-E2 29875 REAL_OPCODE: Y 29876 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29877 PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 29878 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 29879 IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 29880 } 29881 29882 29883 # EMITTING VFIXUPIMMPS (VFIXUPIMMPS-128-1) 29884 { 29885 ICLASS: VFIXUPIMMPS 29886 CPL: 3 29887 CATEGORY: AVX512 29888 EXTENSION: AVX512EVEX 29889 ISA_SET: AVX512F_128 29890 EXCEPTIONS: AVX512-E2 29891 REAL_OPCODE: Y 29892 ATTRIBUTES: MASKOP_EVEX MXCSR 29893 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 29894 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 29895 IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 29896 } 29897 29898 { 29899 ICLASS: VFIXUPIMMPS 29900 CPL: 3 29901 CATEGORY: AVX512 29902 EXTENSION: AVX512EVEX 29903 ISA_SET: AVX512F_128 29904 EXCEPTIONS: AVX512-E2 29905 REAL_OPCODE: Y 29906 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29907 PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 29908 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 29909 IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 29910 } 29911 29912 29913 # EMITTING VFIXUPIMMPS (VFIXUPIMMPS-256-1) 29914 { 29915 ICLASS: VFIXUPIMMPS 29916 CPL: 3 29917 CATEGORY: AVX512 29918 EXTENSION: AVX512EVEX 29919 ISA_SET: AVX512F_256 29920 EXCEPTIONS: AVX512-E2 29921 REAL_OPCODE: Y 29922 ATTRIBUTES: MASKOP_EVEX MXCSR 29923 PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 29924 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b 29925 IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 29926 } 29927 29928 { 29929 ICLASS: VFIXUPIMMPS 29930 CPL: 3 29931 CATEGORY: AVX512 29932 EXTENSION: AVX512EVEX 29933 ISA_SET: AVX512F_256 29934 EXCEPTIONS: AVX512-E2 29935 REAL_OPCODE: Y 29936 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29937 PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 29938 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 29939 IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 29940 } 29941 29942 29943 # EMITTING VFMADD132PD (VFMADD132PD-128-1) 29944 { 29945 ICLASS: VFMADD132PD 29946 CPL: 3 29947 CATEGORY: VFMA 29948 EXTENSION: AVX512EVEX 29949 ISA_SET: AVX512F_128 29950 EXCEPTIONS: AVX512-E2 29951 REAL_OPCODE: Y 29952 ATTRIBUTES: MASKOP_EVEX MXCSR 29953 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 29954 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 29955 IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 29956 } 29957 29958 { 29959 ICLASS: VFMADD132PD 29960 CPL: 3 29961 CATEGORY: VFMA 29962 EXTENSION: AVX512EVEX 29963 ISA_SET: AVX512F_128 29964 EXCEPTIONS: AVX512-E2 29965 REAL_OPCODE: Y 29966 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29967 PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 29968 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 29969 IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 29970 } 29971 29972 29973 # EMITTING VFMADD132PD (VFMADD132PD-256-1) 29974 { 29975 ICLASS: VFMADD132PD 29976 CPL: 3 29977 CATEGORY: VFMA 29978 EXTENSION: AVX512EVEX 29979 ISA_SET: AVX512F_256 29980 EXCEPTIONS: AVX512-E2 29981 REAL_OPCODE: Y 29982 ATTRIBUTES: MASKOP_EVEX MXCSR 29983 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 29984 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 29985 IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 29986 } 29987 29988 { 29989 ICLASS: VFMADD132PD 29990 CPL: 3 29991 CATEGORY: VFMA 29992 EXTENSION: AVX512EVEX 29993 ISA_SET: AVX512F_256 29994 EXCEPTIONS: AVX512-E2 29995 REAL_OPCODE: Y 29996 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 29997 PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 29998 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 29999 IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 30000 } 30001 30002 30003 # EMITTING VFMADD132PS (VFMADD132PS-128-1) 30004 { 30005 ICLASS: VFMADD132PS 30006 CPL: 3 30007 CATEGORY: VFMA 30008 EXTENSION: AVX512EVEX 30009 ISA_SET: AVX512F_128 30010 EXCEPTIONS: AVX512-E2 30011 REAL_OPCODE: Y 30012 ATTRIBUTES: MASKOP_EVEX MXCSR 30013 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 30014 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 30015 IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 30016 } 30017 30018 { 30019 ICLASS: VFMADD132PS 30020 CPL: 3 30021 CATEGORY: VFMA 30022 EXTENSION: AVX512EVEX 30023 ISA_SET: AVX512F_128 30024 EXCEPTIONS: AVX512-E2 30025 REAL_OPCODE: Y 30026 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30027 PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 30028 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30029 IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 30030 } 30031 30032 30033 # EMITTING VFMADD132PS (VFMADD132PS-256-1) 30034 { 30035 ICLASS: VFMADD132PS 30036 CPL: 3 30037 CATEGORY: VFMA 30038 EXTENSION: AVX512EVEX 30039 ISA_SET: AVX512F_256 30040 EXCEPTIONS: AVX512-E2 30041 REAL_OPCODE: Y 30042 ATTRIBUTES: MASKOP_EVEX MXCSR 30043 PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 30044 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 30045 IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 30046 } 30047 30048 { 30049 ICLASS: VFMADD132PS 30050 CPL: 3 30051 CATEGORY: VFMA 30052 EXTENSION: AVX512EVEX 30053 ISA_SET: AVX512F_256 30054 EXCEPTIONS: AVX512-E2 30055 REAL_OPCODE: Y 30056 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30057 PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 30058 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30059 IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 30060 } 30061 30062 30063 # EMITTING VFMADD213PD (VFMADD213PD-128-1) 30064 { 30065 ICLASS: VFMADD213PD 30066 CPL: 3 30067 CATEGORY: VFMA 30068 EXTENSION: AVX512EVEX 30069 ISA_SET: AVX512F_128 30070 EXCEPTIONS: AVX512-E2 30071 REAL_OPCODE: Y 30072 ATTRIBUTES: MASKOP_EVEX MXCSR 30073 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 30074 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 30075 IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 30076 } 30077 30078 { 30079 ICLASS: VFMADD213PD 30080 CPL: 3 30081 CATEGORY: VFMA 30082 EXTENSION: AVX512EVEX 30083 ISA_SET: AVX512F_128 30084 EXCEPTIONS: AVX512-E2 30085 REAL_OPCODE: Y 30086 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30087 PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 30088 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30089 IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 30090 } 30091 30092 30093 # EMITTING VFMADD213PD (VFMADD213PD-256-1) 30094 { 30095 ICLASS: VFMADD213PD 30096 CPL: 3 30097 CATEGORY: VFMA 30098 EXTENSION: AVX512EVEX 30099 ISA_SET: AVX512F_256 30100 EXCEPTIONS: AVX512-E2 30101 REAL_OPCODE: Y 30102 ATTRIBUTES: MASKOP_EVEX MXCSR 30103 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 30104 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 30105 IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 30106 } 30107 30108 { 30109 ICLASS: VFMADD213PD 30110 CPL: 3 30111 CATEGORY: VFMA 30112 EXTENSION: AVX512EVEX 30113 ISA_SET: AVX512F_256 30114 EXCEPTIONS: AVX512-E2 30115 REAL_OPCODE: Y 30116 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30117 PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 30118 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30119 IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 30120 } 30121 30122 30123 # EMITTING VFMADD213PS (VFMADD213PS-128-1) 30124 { 30125 ICLASS: VFMADD213PS 30126 CPL: 3 30127 CATEGORY: VFMA 30128 EXTENSION: AVX512EVEX 30129 ISA_SET: AVX512F_128 30130 EXCEPTIONS: AVX512-E2 30131 REAL_OPCODE: Y 30132 ATTRIBUTES: MASKOP_EVEX MXCSR 30133 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 30134 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 30135 IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 30136 } 30137 30138 { 30139 ICLASS: VFMADD213PS 30140 CPL: 3 30141 CATEGORY: VFMA 30142 EXTENSION: AVX512EVEX 30143 ISA_SET: AVX512F_128 30144 EXCEPTIONS: AVX512-E2 30145 REAL_OPCODE: Y 30146 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30147 PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 30148 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30149 IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 30150 } 30151 30152 30153 # EMITTING VFMADD213PS (VFMADD213PS-256-1) 30154 { 30155 ICLASS: VFMADD213PS 30156 CPL: 3 30157 CATEGORY: VFMA 30158 EXTENSION: AVX512EVEX 30159 ISA_SET: AVX512F_256 30160 EXCEPTIONS: AVX512-E2 30161 REAL_OPCODE: Y 30162 ATTRIBUTES: MASKOP_EVEX MXCSR 30163 PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 30164 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 30165 IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 30166 } 30167 30168 { 30169 ICLASS: VFMADD213PS 30170 CPL: 3 30171 CATEGORY: VFMA 30172 EXTENSION: AVX512EVEX 30173 ISA_SET: AVX512F_256 30174 EXCEPTIONS: AVX512-E2 30175 REAL_OPCODE: Y 30176 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30177 PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 30178 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30179 IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 30180 } 30181 30182 30183 # EMITTING VFMADD231PD (VFMADD231PD-128-1) 30184 { 30185 ICLASS: VFMADD231PD 30186 CPL: 3 30187 CATEGORY: VFMA 30188 EXTENSION: AVX512EVEX 30189 ISA_SET: AVX512F_128 30190 EXCEPTIONS: AVX512-E2 30191 REAL_OPCODE: Y 30192 ATTRIBUTES: MASKOP_EVEX MXCSR 30193 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 30194 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 30195 IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 30196 } 30197 30198 { 30199 ICLASS: VFMADD231PD 30200 CPL: 3 30201 CATEGORY: VFMA 30202 EXTENSION: AVX512EVEX 30203 ISA_SET: AVX512F_128 30204 EXCEPTIONS: AVX512-E2 30205 REAL_OPCODE: Y 30206 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30207 PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 30208 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30209 IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 30210 } 30211 30212 30213 # EMITTING VFMADD231PD (VFMADD231PD-256-1) 30214 { 30215 ICLASS: VFMADD231PD 30216 CPL: 3 30217 CATEGORY: VFMA 30218 EXTENSION: AVX512EVEX 30219 ISA_SET: AVX512F_256 30220 EXCEPTIONS: AVX512-E2 30221 REAL_OPCODE: Y 30222 ATTRIBUTES: MASKOP_EVEX MXCSR 30223 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 30224 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 30225 IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 30226 } 30227 30228 { 30229 ICLASS: VFMADD231PD 30230 CPL: 3 30231 CATEGORY: VFMA 30232 EXTENSION: AVX512EVEX 30233 ISA_SET: AVX512F_256 30234 EXCEPTIONS: AVX512-E2 30235 REAL_OPCODE: Y 30236 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30237 PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 30238 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30239 IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 30240 } 30241 30242 30243 # EMITTING VFMADD231PS (VFMADD231PS-128-1) 30244 { 30245 ICLASS: VFMADD231PS 30246 CPL: 3 30247 CATEGORY: VFMA 30248 EXTENSION: AVX512EVEX 30249 ISA_SET: AVX512F_128 30250 EXCEPTIONS: AVX512-E2 30251 REAL_OPCODE: Y 30252 ATTRIBUTES: MASKOP_EVEX MXCSR 30253 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 30254 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 30255 IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 30256 } 30257 30258 { 30259 ICLASS: VFMADD231PS 30260 CPL: 3 30261 CATEGORY: VFMA 30262 EXTENSION: AVX512EVEX 30263 ISA_SET: AVX512F_128 30264 EXCEPTIONS: AVX512-E2 30265 REAL_OPCODE: Y 30266 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30267 PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 30268 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30269 IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 30270 } 30271 30272 30273 # EMITTING VFMADD231PS (VFMADD231PS-256-1) 30274 { 30275 ICLASS: VFMADD231PS 30276 CPL: 3 30277 CATEGORY: VFMA 30278 EXTENSION: AVX512EVEX 30279 ISA_SET: AVX512F_256 30280 EXCEPTIONS: AVX512-E2 30281 REAL_OPCODE: Y 30282 ATTRIBUTES: MASKOP_EVEX MXCSR 30283 PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 30284 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 30285 IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 30286 } 30287 30288 { 30289 ICLASS: VFMADD231PS 30290 CPL: 3 30291 CATEGORY: VFMA 30292 EXTENSION: AVX512EVEX 30293 ISA_SET: AVX512F_256 30294 EXCEPTIONS: AVX512-E2 30295 REAL_OPCODE: Y 30296 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30297 PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 30298 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30299 IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 30300 } 30301 30302 30303 # EMITTING VFMADDSUB132PD (VFMADDSUB132PD-128-1) 30304 { 30305 ICLASS: VFMADDSUB132PD 30306 CPL: 3 30307 CATEGORY: VFMA 30308 EXTENSION: AVX512EVEX 30309 ISA_SET: AVX512F_128 30310 EXCEPTIONS: AVX512-E2 30311 REAL_OPCODE: Y 30312 ATTRIBUTES: MASKOP_EVEX MXCSR 30313 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 30314 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 30315 IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 30316 } 30317 30318 { 30319 ICLASS: VFMADDSUB132PD 30320 CPL: 3 30321 CATEGORY: VFMA 30322 EXTENSION: AVX512EVEX 30323 ISA_SET: AVX512F_128 30324 EXCEPTIONS: AVX512-E2 30325 REAL_OPCODE: Y 30326 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30327 PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 30328 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30329 IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 30330 } 30331 30332 30333 # EMITTING VFMADDSUB132PD (VFMADDSUB132PD-256-1) 30334 { 30335 ICLASS: VFMADDSUB132PD 30336 CPL: 3 30337 CATEGORY: VFMA 30338 EXTENSION: AVX512EVEX 30339 ISA_SET: AVX512F_256 30340 EXCEPTIONS: AVX512-E2 30341 REAL_OPCODE: Y 30342 ATTRIBUTES: MASKOP_EVEX MXCSR 30343 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 30344 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 30345 IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 30346 } 30347 30348 { 30349 ICLASS: VFMADDSUB132PD 30350 CPL: 3 30351 CATEGORY: VFMA 30352 EXTENSION: AVX512EVEX 30353 ISA_SET: AVX512F_256 30354 EXCEPTIONS: AVX512-E2 30355 REAL_OPCODE: Y 30356 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30357 PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 30358 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30359 IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 30360 } 30361 30362 30363 # EMITTING VFMADDSUB132PS (VFMADDSUB132PS-128-1) 30364 { 30365 ICLASS: VFMADDSUB132PS 30366 CPL: 3 30367 CATEGORY: VFMA 30368 EXTENSION: AVX512EVEX 30369 ISA_SET: AVX512F_128 30370 EXCEPTIONS: AVX512-E2 30371 REAL_OPCODE: Y 30372 ATTRIBUTES: MASKOP_EVEX MXCSR 30373 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 30374 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 30375 IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 30376 } 30377 30378 { 30379 ICLASS: VFMADDSUB132PS 30380 CPL: 3 30381 CATEGORY: VFMA 30382 EXTENSION: AVX512EVEX 30383 ISA_SET: AVX512F_128 30384 EXCEPTIONS: AVX512-E2 30385 REAL_OPCODE: Y 30386 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30387 PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 30388 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30389 IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 30390 } 30391 30392 30393 # EMITTING VFMADDSUB132PS (VFMADDSUB132PS-256-1) 30394 { 30395 ICLASS: VFMADDSUB132PS 30396 CPL: 3 30397 CATEGORY: VFMA 30398 EXTENSION: AVX512EVEX 30399 ISA_SET: AVX512F_256 30400 EXCEPTIONS: AVX512-E2 30401 REAL_OPCODE: Y 30402 ATTRIBUTES: MASKOP_EVEX MXCSR 30403 PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 30404 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 30405 IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 30406 } 30407 30408 { 30409 ICLASS: VFMADDSUB132PS 30410 CPL: 3 30411 CATEGORY: VFMA 30412 EXTENSION: AVX512EVEX 30413 ISA_SET: AVX512F_256 30414 EXCEPTIONS: AVX512-E2 30415 REAL_OPCODE: Y 30416 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30417 PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 30418 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30419 IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 30420 } 30421 30422 30423 # EMITTING VFMADDSUB213PD (VFMADDSUB213PD-128-1) 30424 { 30425 ICLASS: VFMADDSUB213PD 30426 CPL: 3 30427 CATEGORY: VFMA 30428 EXTENSION: AVX512EVEX 30429 ISA_SET: AVX512F_128 30430 EXCEPTIONS: AVX512-E2 30431 REAL_OPCODE: Y 30432 ATTRIBUTES: MASKOP_EVEX MXCSR 30433 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 30434 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 30435 IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 30436 } 30437 30438 { 30439 ICLASS: VFMADDSUB213PD 30440 CPL: 3 30441 CATEGORY: VFMA 30442 EXTENSION: AVX512EVEX 30443 ISA_SET: AVX512F_128 30444 EXCEPTIONS: AVX512-E2 30445 REAL_OPCODE: Y 30446 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30447 PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 30448 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30449 IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 30450 } 30451 30452 30453 # EMITTING VFMADDSUB213PD (VFMADDSUB213PD-256-1) 30454 { 30455 ICLASS: VFMADDSUB213PD 30456 CPL: 3 30457 CATEGORY: VFMA 30458 EXTENSION: AVX512EVEX 30459 ISA_SET: AVX512F_256 30460 EXCEPTIONS: AVX512-E2 30461 REAL_OPCODE: Y 30462 ATTRIBUTES: MASKOP_EVEX MXCSR 30463 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 30464 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 30465 IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 30466 } 30467 30468 { 30469 ICLASS: VFMADDSUB213PD 30470 CPL: 3 30471 CATEGORY: VFMA 30472 EXTENSION: AVX512EVEX 30473 ISA_SET: AVX512F_256 30474 EXCEPTIONS: AVX512-E2 30475 REAL_OPCODE: Y 30476 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30477 PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 30478 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30479 IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 30480 } 30481 30482 30483 # EMITTING VFMADDSUB213PS (VFMADDSUB213PS-128-1) 30484 { 30485 ICLASS: VFMADDSUB213PS 30486 CPL: 3 30487 CATEGORY: VFMA 30488 EXTENSION: AVX512EVEX 30489 ISA_SET: AVX512F_128 30490 EXCEPTIONS: AVX512-E2 30491 REAL_OPCODE: Y 30492 ATTRIBUTES: MASKOP_EVEX MXCSR 30493 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 30494 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 30495 IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 30496 } 30497 30498 { 30499 ICLASS: VFMADDSUB213PS 30500 CPL: 3 30501 CATEGORY: VFMA 30502 EXTENSION: AVX512EVEX 30503 ISA_SET: AVX512F_128 30504 EXCEPTIONS: AVX512-E2 30505 REAL_OPCODE: Y 30506 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30507 PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 30508 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30509 IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 30510 } 30511 30512 30513 # EMITTING VFMADDSUB213PS (VFMADDSUB213PS-256-1) 30514 { 30515 ICLASS: VFMADDSUB213PS 30516 CPL: 3 30517 CATEGORY: VFMA 30518 EXTENSION: AVX512EVEX 30519 ISA_SET: AVX512F_256 30520 EXCEPTIONS: AVX512-E2 30521 REAL_OPCODE: Y 30522 ATTRIBUTES: MASKOP_EVEX MXCSR 30523 PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 30524 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 30525 IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 30526 } 30527 30528 { 30529 ICLASS: VFMADDSUB213PS 30530 CPL: 3 30531 CATEGORY: VFMA 30532 EXTENSION: AVX512EVEX 30533 ISA_SET: AVX512F_256 30534 EXCEPTIONS: AVX512-E2 30535 REAL_OPCODE: Y 30536 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30537 PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 30538 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30539 IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 30540 } 30541 30542 30543 # EMITTING VFMADDSUB231PD (VFMADDSUB231PD-128-1) 30544 { 30545 ICLASS: VFMADDSUB231PD 30546 CPL: 3 30547 CATEGORY: VFMA 30548 EXTENSION: AVX512EVEX 30549 ISA_SET: AVX512F_128 30550 EXCEPTIONS: AVX512-E2 30551 REAL_OPCODE: Y 30552 ATTRIBUTES: MASKOP_EVEX MXCSR 30553 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 30554 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 30555 IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 30556 } 30557 30558 { 30559 ICLASS: VFMADDSUB231PD 30560 CPL: 3 30561 CATEGORY: VFMA 30562 EXTENSION: AVX512EVEX 30563 ISA_SET: AVX512F_128 30564 EXCEPTIONS: AVX512-E2 30565 REAL_OPCODE: Y 30566 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30567 PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 30568 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30569 IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 30570 } 30571 30572 30573 # EMITTING VFMADDSUB231PD (VFMADDSUB231PD-256-1) 30574 { 30575 ICLASS: VFMADDSUB231PD 30576 CPL: 3 30577 CATEGORY: VFMA 30578 EXTENSION: AVX512EVEX 30579 ISA_SET: AVX512F_256 30580 EXCEPTIONS: AVX512-E2 30581 REAL_OPCODE: Y 30582 ATTRIBUTES: MASKOP_EVEX MXCSR 30583 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 30584 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 30585 IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 30586 } 30587 30588 { 30589 ICLASS: VFMADDSUB231PD 30590 CPL: 3 30591 CATEGORY: VFMA 30592 EXTENSION: AVX512EVEX 30593 ISA_SET: AVX512F_256 30594 EXCEPTIONS: AVX512-E2 30595 REAL_OPCODE: Y 30596 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30597 PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 30598 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30599 IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 30600 } 30601 30602 30603 # EMITTING VFMADDSUB231PS (VFMADDSUB231PS-128-1) 30604 { 30605 ICLASS: VFMADDSUB231PS 30606 CPL: 3 30607 CATEGORY: VFMA 30608 EXTENSION: AVX512EVEX 30609 ISA_SET: AVX512F_128 30610 EXCEPTIONS: AVX512-E2 30611 REAL_OPCODE: Y 30612 ATTRIBUTES: MASKOP_EVEX MXCSR 30613 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 30614 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 30615 IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 30616 } 30617 30618 { 30619 ICLASS: VFMADDSUB231PS 30620 CPL: 3 30621 CATEGORY: VFMA 30622 EXTENSION: AVX512EVEX 30623 ISA_SET: AVX512F_128 30624 EXCEPTIONS: AVX512-E2 30625 REAL_OPCODE: Y 30626 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30627 PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 30628 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30629 IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 30630 } 30631 30632 30633 # EMITTING VFMADDSUB231PS (VFMADDSUB231PS-256-1) 30634 { 30635 ICLASS: VFMADDSUB231PS 30636 CPL: 3 30637 CATEGORY: VFMA 30638 EXTENSION: AVX512EVEX 30639 ISA_SET: AVX512F_256 30640 EXCEPTIONS: AVX512-E2 30641 REAL_OPCODE: Y 30642 ATTRIBUTES: MASKOP_EVEX MXCSR 30643 PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 30644 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 30645 IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 30646 } 30647 30648 { 30649 ICLASS: VFMADDSUB231PS 30650 CPL: 3 30651 CATEGORY: VFMA 30652 EXTENSION: AVX512EVEX 30653 ISA_SET: AVX512F_256 30654 EXCEPTIONS: AVX512-E2 30655 REAL_OPCODE: Y 30656 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30657 PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 30658 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30659 IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 30660 } 30661 30662 30663 # EMITTING VFMSUB132PD (VFMSUB132PD-128-1) 30664 { 30665 ICLASS: VFMSUB132PD 30666 CPL: 3 30667 CATEGORY: VFMA 30668 EXTENSION: AVX512EVEX 30669 ISA_SET: AVX512F_128 30670 EXCEPTIONS: AVX512-E2 30671 REAL_OPCODE: Y 30672 ATTRIBUTES: MASKOP_EVEX MXCSR 30673 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 30674 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 30675 IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 30676 } 30677 30678 { 30679 ICLASS: VFMSUB132PD 30680 CPL: 3 30681 CATEGORY: VFMA 30682 EXTENSION: AVX512EVEX 30683 ISA_SET: AVX512F_128 30684 EXCEPTIONS: AVX512-E2 30685 REAL_OPCODE: Y 30686 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30687 PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 30688 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30689 IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 30690 } 30691 30692 30693 # EMITTING VFMSUB132PD (VFMSUB132PD-256-1) 30694 { 30695 ICLASS: VFMSUB132PD 30696 CPL: 3 30697 CATEGORY: VFMA 30698 EXTENSION: AVX512EVEX 30699 ISA_SET: AVX512F_256 30700 EXCEPTIONS: AVX512-E2 30701 REAL_OPCODE: Y 30702 ATTRIBUTES: MASKOP_EVEX MXCSR 30703 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 30704 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 30705 IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 30706 } 30707 30708 { 30709 ICLASS: VFMSUB132PD 30710 CPL: 3 30711 CATEGORY: VFMA 30712 EXTENSION: AVX512EVEX 30713 ISA_SET: AVX512F_256 30714 EXCEPTIONS: AVX512-E2 30715 REAL_OPCODE: Y 30716 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30717 PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 30718 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30719 IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 30720 } 30721 30722 30723 # EMITTING VFMSUB132PS (VFMSUB132PS-128-1) 30724 { 30725 ICLASS: VFMSUB132PS 30726 CPL: 3 30727 CATEGORY: VFMA 30728 EXTENSION: AVX512EVEX 30729 ISA_SET: AVX512F_128 30730 EXCEPTIONS: AVX512-E2 30731 REAL_OPCODE: Y 30732 ATTRIBUTES: MASKOP_EVEX MXCSR 30733 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 30734 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 30735 IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 30736 } 30737 30738 { 30739 ICLASS: VFMSUB132PS 30740 CPL: 3 30741 CATEGORY: VFMA 30742 EXTENSION: AVX512EVEX 30743 ISA_SET: AVX512F_128 30744 EXCEPTIONS: AVX512-E2 30745 REAL_OPCODE: Y 30746 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30747 PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 30748 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30749 IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 30750 } 30751 30752 30753 # EMITTING VFMSUB132PS (VFMSUB132PS-256-1) 30754 { 30755 ICLASS: VFMSUB132PS 30756 CPL: 3 30757 CATEGORY: VFMA 30758 EXTENSION: AVX512EVEX 30759 ISA_SET: AVX512F_256 30760 EXCEPTIONS: AVX512-E2 30761 REAL_OPCODE: Y 30762 ATTRIBUTES: MASKOP_EVEX MXCSR 30763 PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 30764 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 30765 IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 30766 } 30767 30768 { 30769 ICLASS: VFMSUB132PS 30770 CPL: 3 30771 CATEGORY: VFMA 30772 EXTENSION: AVX512EVEX 30773 ISA_SET: AVX512F_256 30774 EXCEPTIONS: AVX512-E2 30775 REAL_OPCODE: Y 30776 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30777 PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 30778 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30779 IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 30780 } 30781 30782 30783 # EMITTING VFMSUB213PD (VFMSUB213PD-128-1) 30784 { 30785 ICLASS: VFMSUB213PD 30786 CPL: 3 30787 CATEGORY: VFMA 30788 EXTENSION: AVX512EVEX 30789 ISA_SET: AVX512F_128 30790 EXCEPTIONS: AVX512-E2 30791 REAL_OPCODE: Y 30792 ATTRIBUTES: MASKOP_EVEX MXCSR 30793 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 30794 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 30795 IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 30796 } 30797 30798 { 30799 ICLASS: VFMSUB213PD 30800 CPL: 3 30801 CATEGORY: VFMA 30802 EXTENSION: AVX512EVEX 30803 ISA_SET: AVX512F_128 30804 EXCEPTIONS: AVX512-E2 30805 REAL_OPCODE: Y 30806 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30807 PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 30808 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30809 IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 30810 } 30811 30812 30813 # EMITTING VFMSUB213PD (VFMSUB213PD-256-1) 30814 { 30815 ICLASS: VFMSUB213PD 30816 CPL: 3 30817 CATEGORY: VFMA 30818 EXTENSION: AVX512EVEX 30819 ISA_SET: AVX512F_256 30820 EXCEPTIONS: AVX512-E2 30821 REAL_OPCODE: Y 30822 ATTRIBUTES: MASKOP_EVEX MXCSR 30823 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 30824 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 30825 IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 30826 } 30827 30828 { 30829 ICLASS: VFMSUB213PD 30830 CPL: 3 30831 CATEGORY: VFMA 30832 EXTENSION: AVX512EVEX 30833 ISA_SET: AVX512F_256 30834 EXCEPTIONS: AVX512-E2 30835 REAL_OPCODE: Y 30836 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30837 PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 30838 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30839 IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 30840 } 30841 30842 30843 # EMITTING VFMSUB213PS (VFMSUB213PS-128-1) 30844 { 30845 ICLASS: VFMSUB213PS 30846 CPL: 3 30847 CATEGORY: VFMA 30848 EXTENSION: AVX512EVEX 30849 ISA_SET: AVX512F_128 30850 EXCEPTIONS: AVX512-E2 30851 REAL_OPCODE: Y 30852 ATTRIBUTES: MASKOP_EVEX MXCSR 30853 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 30854 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 30855 IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 30856 } 30857 30858 { 30859 ICLASS: VFMSUB213PS 30860 CPL: 3 30861 CATEGORY: VFMA 30862 EXTENSION: AVX512EVEX 30863 ISA_SET: AVX512F_128 30864 EXCEPTIONS: AVX512-E2 30865 REAL_OPCODE: Y 30866 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30867 PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 30868 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30869 IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 30870 } 30871 30872 30873 # EMITTING VFMSUB213PS (VFMSUB213PS-256-1) 30874 { 30875 ICLASS: VFMSUB213PS 30876 CPL: 3 30877 CATEGORY: VFMA 30878 EXTENSION: AVX512EVEX 30879 ISA_SET: AVX512F_256 30880 EXCEPTIONS: AVX512-E2 30881 REAL_OPCODE: Y 30882 ATTRIBUTES: MASKOP_EVEX MXCSR 30883 PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 30884 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 30885 IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 30886 } 30887 30888 { 30889 ICLASS: VFMSUB213PS 30890 CPL: 3 30891 CATEGORY: VFMA 30892 EXTENSION: AVX512EVEX 30893 ISA_SET: AVX512F_256 30894 EXCEPTIONS: AVX512-E2 30895 REAL_OPCODE: Y 30896 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30897 PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 30898 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30899 IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 30900 } 30901 30902 30903 # EMITTING VFMSUB231PD (VFMSUB231PD-128-1) 30904 { 30905 ICLASS: VFMSUB231PD 30906 CPL: 3 30907 CATEGORY: VFMA 30908 EXTENSION: AVX512EVEX 30909 ISA_SET: AVX512F_128 30910 EXCEPTIONS: AVX512-E2 30911 REAL_OPCODE: Y 30912 ATTRIBUTES: MASKOP_EVEX MXCSR 30913 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 30914 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 30915 IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 30916 } 30917 30918 { 30919 ICLASS: VFMSUB231PD 30920 CPL: 3 30921 CATEGORY: VFMA 30922 EXTENSION: AVX512EVEX 30923 ISA_SET: AVX512F_128 30924 EXCEPTIONS: AVX512-E2 30925 REAL_OPCODE: Y 30926 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30927 PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 30928 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30929 IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 30930 } 30931 30932 30933 # EMITTING VFMSUB231PD (VFMSUB231PD-256-1) 30934 { 30935 ICLASS: VFMSUB231PD 30936 CPL: 3 30937 CATEGORY: VFMA 30938 EXTENSION: AVX512EVEX 30939 ISA_SET: AVX512F_256 30940 EXCEPTIONS: AVX512-E2 30941 REAL_OPCODE: Y 30942 ATTRIBUTES: MASKOP_EVEX MXCSR 30943 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 30944 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 30945 IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 30946 } 30947 30948 { 30949 ICLASS: VFMSUB231PD 30950 CPL: 3 30951 CATEGORY: VFMA 30952 EXTENSION: AVX512EVEX 30953 ISA_SET: AVX512F_256 30954 EXCEPTIONS: AVX512-E2 30955 REAL_OPCODE: Y 30956 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30957 PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 30958 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 30959 IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 30960 } 30961 30962 30963 # EMITTING VFMSUB231PS (VFMSUB231PS-128-1) 30964 { 30965 ICLASS: VFMSUB231PS 30966 CPL: 3 30967 CATEGORY: VFMA 30968 EXTENSION: AVX512EVEX 30969 ISA_SET: AVX512F_128 30970 EXCEPTIONS: AVX512-E2 30971 REAL_OPCODE: Y 30972 ATTRIBUTES: MASKOP_EVEX MXCSR 30973 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 30974 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 30975 IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 30976 } 30977 30978 { 30979 ICLASS: VFMSUB231PS 30980 CPL: 3 30981 CATEGORY: VFMA 30982 EXTENSION: AVX512EVEX 30983 ISA_SET: AVX512F_128 30984 EXCEPTIONS: AVX512-E2 30985 REAL_OPCODE: Y 30986 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 30987 PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 30988 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 30989 IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 30990 } 30991 30992 30993 # EMITTING VFMSUB231PS (VFMSUB231PS-256-1) 30994 { 30995 ICLASS: VFMSUB231PS 30996 CPL: 3 30997 CATEGORY: VFMA 30998 EXTENSION: AVX512EVEX 30999 ISA_SET: AVX512F_256 31000 EXCEPTIONS: AVX512-E2 31001 REAL_OPCODE: Y 31002 ATTRIBUTES: MASKOP_EVEX MXCSR 31003 PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 31004 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 31005 IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 31006 } 31007 31008 { 31009 ICLASS: VFMSUB231PS 31010 CPL: 3 31011 CATEGORY: VFMA 31012 EXTENSION: AVX512EVEX 31013 ISA_SET: AVX512F_256 31014 EXCEPTIONS: AVX512-E2 31015 REAL_OPCODE: Y 31016 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31017 PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 31018 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31019 IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 31020 } 31021 31022 31023 # EMITTING VFMSUBADD132PD (VFMSUBADD132PD-128-1) 31024 { 31025 ICLASS: VFMSUBADD132PD 31026 CPL: 3 31027 CATEGORY: VFMA 31028 EXTENSION: AVX512EVEX 31029 ISA_SET: AVX512F_128 31030 EXCEPTIONS: AVX512-E2 31031 REAL_OPCODE: Y 31032 ATTRIBUTES: MASKOP_EVEX MXCSR 31033 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 31034 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31035 IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31036 } 31037 31038 { 31039 ICLASS: VFMSUBADD132PD 31040 CPL: 3 31041 CATEGORY: VFMA 31042 EXTENSION: AVX512EVEX 31043 ISA_SET: AVX512F_128 31044 EXCEPTIONS: AVX512-E2 31045 REAL_OPCODE: Y 31046 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31047 PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 31048 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31049 IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 31050 } 31051 31052 31053 # EMITTING VFMSUBADD132PD (VFMSUBADD132PD-256-1) 31054 { 31055 ICLASS: VFMSUBADD132PD 31056 CPL: 3 31057 CATEGORY: VFMA 31058 EXTENSION: AVX512EVEX 31059 ISA_SET: AVX512F_256 31060 EXCEPTIONS: AVX512-E2 31061 REAL_OPCODE: Y 31062 ATTRIBUTES: MASKOP_EVEX MXCSR 31063 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 31064 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 31065 IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 31066 } 31067 31068 { 31069 ICLASS: VFMSUBADD132PD 31070 CPL: 3 31071 CATEGORY: VFMA 31072 EXTENSION: AVX512EVEX 31073 ISA_SET: AVX512F_256 31074 EXCEPTIONS: AVX512-E2 31075 REAL_OPCODE: Y 31076 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31077 PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 31078 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31079 IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 31080 } 31081 31082 31083 # EMITTING VFMSUBADD132PS (VFMSUBADD132PS-128-1) 31084 { 31085 ICLASS: VFMSUBADD132PS 31086 CPL: 3 31087 CATEGORY: VFMA 31088 EXTENSION: AVX512EVEX 31089 ISA_SET: AVX512F_128 31090 EXCEPTIONS: AVX512-E2 31091 REAL_OPCODE: Y 31092 ATTRIBUTES: MASKOP_EVEX MXCSR 31093 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 31094 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31095 IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31096 } 31097 31098 { 31099 ICLASS: VFMSUBADD132PS 31100 CPL: 3 31101 CATEGORY: VFMA 31102 EXTENSION: AVX512EVEX 31103 ISA_SET: AVX512F_128 31104 EXCEPTIONS: AVX512-E2 31105 REAL_OPCODE: Y 31106 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31107 PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 31108 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31109 IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 31110 } 31111 31112 31113 # EMITTING VFMSUBADD132PS (VFMSUBADD132PS-256-1) 31114 { 31115 ICLASS: VFMSUBADD132PS 31116 CPL: 3 31117 CATEGORY: VFMA 31118 EXTENSION: AVX512EVEX 31119 ISA_SET: AVX512F_256 31120 EXCEPTIONS: AVX512-E2 31121 REAL_OPCODE: Y 31122 ATTRIBUTES: MASKOP_EVEX MXCSR 31123 PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 31124 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 31125 IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 31126 } 31127 31128 { 31129 ICLASS: VFMSUBADD132PS 31130 CPL: 3 31131 CATEGORY: VFMA 31132 EXTENSION: AVX512EVEX 31133 ISA_SET: AVX512F_256 31134 EXCEPTIONS: AVX512-E2 31135 REAL_OPCODE: Y 31136 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31137 PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 31138 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31139 IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 31140 } 31141 31142 31143 # EMITTING VFMSUBADD213PD (VFMSUBADD213PD-128-1) 31144 { 31145 ICLASS: VFMSUBADD213PD 31146 CPL: 3 31147 CATEGORY: VFMA 31148 EXTENSION: AVX512EVEX 31149 ISA_SET: AVX512F_128 31150 EXCEPTIONS: AVX512-E2 31151 REAL_OPCODE: Y 31152 ATTRIBUTES: MASKOP_EVEX MXCSR 31153 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 31154 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31155 IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31156 } 31157 31158 { 31159 ICLASS: VFMSUBADD213PD 31160 CPL: 3 31161 CATEGORY: VFMA 31162 EXTENSION: AVX512EVEX 31163 ISA_SET: AVX512F_128 31164 EXCEPTIONS: AVX512-E2 31165 REAL_OPCODE: Y 31166 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31167 PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 31168 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31169 IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 31170 } 31171 31172 31173 # EMITTING VFMSUBADD213PD (VFMSUBADD213PD-256-1) 31174 { 31175 ICLASS: VFMSUBADD213PD 31176 CPL: 3 31177 CATEGORY: VFMA 31178 EXTENSION: AVX512EVEX 31179 ISA_SET: AVX512F_256 31180 EXCEPTIONS: AVX512-E2 31181 REAL_OPCODE: Y 31182 ATTRIBUTES: MASKOP_EVEX MXCSR 31183 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 31184 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 31185 IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 31186 } 31187 31188 { 31189 ICLASS: VFMSUBADD213PD 31190 CPL: 3 31191 CATEGORY: VFMA 31192 EXTENSION: AVX512EVEX 31193 ISA_SET: AVX512F_256 31194 EXCEPTIONS: AVX512-E2 31195 REAL_OPCODE: Y 31196 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31197 PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 31198 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31199 IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 31200 } 31201 31202 31203 # EMITTING VFMSUBADD213PS (VFMSUBADD213PS-128-1) 31204 { 31205 ICLASS: VFMSUBADD213PS 31206 CPL: 3 31207 CATEGORY: VFMA 31208 EXTENSION: AVX512EVEX 31209 ISA_SET: AVX512F_128 31210 EXCEPTIONS: AVX512-E2 31211 REAL_OPCODE: Y 31212 ATTRIBUTES: MASKOP_EVEX MXCSR 31213 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 31214 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31215 IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31216 } 31217 31218 { 31219 ICLASS: VFMSUBADD213PS 31220 CPL: 3 31221 CATEGORY: VFMA 31222 EXTENSION: AVX512EVEX 31223 ISA_SET: AVX512F_128 31224 EXCEPTIONS: AVX512-E2 31225 REAL_OPCODE: Y 31226 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31227 PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 31228 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31229 IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 31230 } 31231 31232 31233 # EMITTING VFMSUBADD213PS (VFMSUBADD213PS-256-1) 31234 { 31235 ICLASS: VFMSUBADD213PS 31236 CPL: 3 31237 CATEGORY: VFMA 31238 EXTENSION: AVX512EVEX 31239 ISA_SET: AVX512F_256 31240 EXCEPTIONS: AVX512-E2 31241 REAL_OPCODE: Y 31242 ATTRIBUTES: MASKOP_EVEX MXCSR 31243 PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 31244 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 31245 IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 31246 } 31247 31248 { 31249 ICLASS: VFMSUBADD213PS 31250 CPL: 3 31251 CATEGORY: VFMA 31252 EXTENSION: AVX512EVEX 31253 ISA_SET: AVX512F_256 31254 EXCEPTIONS: AVX512-E2 31255 REAL_OPCODE: Y 31256 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31257 PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 31258 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31259 IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 31260 } 31261 31262 31263 # EMITTING VFMSUBADD231PD (VFMSUBADD231PD-128-1) 31264 { 31265 ICLASS: VFMSUBADD231PD 31266 CPL: 3 31267 CATEGORY: VFMA 31268 EXTENSION: AVX512EVEX 31269 ISA_SET: AVX512F_128 31270 EXCEPTIONS: AVX512-E2 31271 REAL_OPCODE: Y 31272 ATTRIBUTES: MASKOP_EVEX MXCSR 31273 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 31274 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31275 IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31276 } 31277 31278 { 31279 ICLASS: VFMSUBADD231PD 31280 CPL: 3 31281 CATEGORY: VFMA 31282 EXTENSION: AVX512EVEX 31283 ISA_SET: AVX512F_128 31284 EXCEPTIONS: AVX512-E2 31285 REAL_OPCODE: Y 31286 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31287 PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 31288 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31289 IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 31290 } 31291 31292 31293 # EMITTING VFMSUBADD231PD (VFMSUBADD231PD-256-1) 31294 { 31295 ICLASS: VFMSUBADD231PD 31296 CPL: 3 31297 CATEGORY: VFMA 31298 EXTENSION: AVX512EVEX 31299 ISA_SET: AVX512F_256 31300 EXCEPTIONS: AVX512-E2 31301 REAL_OPCODE: Y 31302 ATTRIBUTES: MASKOP_EVEX MXCSR 31303 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 31304 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 31305 IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 31306 } 31307 31308 { 31309 ICLASS: VFMSUBADD231PD 31310 CPL: 3 31311 CATEGORY: VFMA 31312 EXTENSION: AVX512EVEX 31313 ISA_SET: AVX512F_256 31314 EXCEPTIONS: AVX512-E2 31315 REAL_OPCODE: Y 31316 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31317 PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 31318 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31319 IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 31320 } 31321 31322 31323 # EMITTING VFMSUBADD231PS (VFMSUBADD231PS-128-1) 31324 { 31325 ICLASS: VFMSUBADD231PS 31326 CPL: 3 31327 CATEGORY: VFMA 31328 EXTENSION: AVX512EVEX 31329 ISA_SET: AVX512F_128 31330 EXCEPTIONS: AVX512-E2 31331 REAL_OPCODE: Y 31332 ATTRIBUTES: MASKOP_EVEX MXCSR 31333 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 31334 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31335 IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31336 } 31337 31338 { 31339 ICLASS: VFMSUBADD231PS 31340 CPL: 3 31341 CATEGORY: VFMA 31342 EXTENSION: AVX512EVEX 31343 ISA_SET: AVX512F_128 31344 EXCEPTIONS: AVX512-E2 31345 REAL_OPCODE: Y 31346 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31347 PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 31348 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31349 IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 31350 } 31351 31352 31353 # EMITTING VFMSUBADD231PS (VFMSUBADD231PS-256-1) 31354 { 31355 ICLASS: VFMSUBADD231PS 31356 CPL: 3 31357 CATEGORY: VFMA 31358 EXTENSION: AVX512EVEX 31359 ISA_SET: AVX512F_256 31360 EXCEPTIONS: AVX512-E2 31361 REAL_OPCODE: Y 31362 ATTRIBUTES: MASKOP_EVEX MXCSR 31363 PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 31364 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 31365 IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 31366 } 31367 31368 { 31369 ICLASS: VFMSUBADD231PS 31370 CPL: 3 31371 CATEGORY: VFMA 31372 EXTENSION: AVX512EVEX 31373 ISA_SET: AVX512F_256 31374 EXCEPTIONS: AVX512-E2 31375 REAL_OPCODE: Y 31376 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31377 PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 31378 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31379 IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 31380 } 31381 31382 31383 # EMITTING VFNMADD132PD (VFNMADD132PD-128-1) 31384 { 31385 ICLASS: VFNMADD132PD 31386 CPL: 3 31387 CATEGORY: VFMA 31388 EXTENSION: AVX512EVEX 31389 ISA_SET: AVX512F_128 31390 EXCEPTIONS: AVX512-E2 31391 REAL_OPCODE: Y 31392 ATTRIBUTES: MASKOP_EVEX MXCSR 31393 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 31394 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31395 IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31396 } 31397 31398 { 31399 ICLASS: VFNMADD132PD 31400 CPL: 3 31401 CATEGORY: VFMA 31402 EXTENSION: AVX512EVEX 31403 ISA_SET: AVX512F_128 31404 EXCEPTIONS: AVX512-E2 31405 REAL_OPCODE: Y 31406 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31407 PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 31408 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31409 IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 31410 } 31411 31412 31413 # EMITTING VFNMADD132PD (VFNMADD132PD-256-1) 31414 { 31415 ICLASS: VFNMADD132PD 31416 CPL: 3 31417 CATEGORY: VFMA 31418 EXTENSION: AVX512EVEX 31419 ISA_SET: AVX512F_256 31420 EXCEPTIONS: AVX512-E2 31421 REAL_OPCODE: Y 31422 ATTRIBUTES: MASKOP_EVEX MXCSR 31423 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 31424 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 31425 IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 31426 } 31427 31428 { 31429 ICLASS: VFNMADD132PD 31430 CPL: 3 31431 CATEGORY: VFMA 31432 EXTENSION: AVX512EVEX 31433 ISA_SET: AVX512F_256 31434 EXCEPTIONS: AVX512-E2 31435 REAL_OPCODE: Y 31436 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31437 PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 31438 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31439 IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 31440 } 31441 31442 31443 # EMITTING VFNMADD132PS (VFNMADD132PS-128-1) 31444 { 31445 ICLASS: VFNMADD132PS 31446 CPL: 3 31447 CATEGORY: VFMA 31448 EXTENSION: AVX512EVEX 31449 ISA_SET: AVX512F_128 31450 EXCEPTIONS: AVX512-E2 31451 REAL_OPCODE: Y 31452 ATTRIBUTES: MASKOP_EVEX MXCSR 31453 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 31454 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31455 IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31456 } 31457 31458 { 31459 ICLASS: VFNMADD132PS 31460 CPL: 3 31461 CATEGORY: VFMA 31462 EXTENSION: AVX512EVEX 31463 ISA_SET: AVX512F_128 31464 EXCEPTIONS: AVX512-E2 31465 REAL_OPCODE: Y 31466 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31467 PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 31468 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31469 IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 31470 } 31471 31472 31473 # EMITTING VFNMADD132PS (VFNMADD132PS-256-1) 31474 { 31475 ICLASS: VFNMADD132PS 31476 CPL: 3 31477 CATEGORY: VFMA 31478 EXTENSION: AVX512EVEX 31479 ISA_SET: AVX512F_256 31480 EXCEPTIONS: AVX512-E2 31481 REAL_OPCODE: Y 31482 ATTRIBUTES: MASKOP_EVEX MXCSR 31483 PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 31484 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 31485 IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 31486 } 31487 31488 { 31489 ICLASS: VFNMADD132PS 31490 CPL: 3 31491 CATEGORY: VFMA 31492 EXTENSION: AVX512EVEX 31493 ISA_SET: AVX512F_256 31494 EXCEPTIONS: AVX512-E2 31495 REAL_OPCODE: Y 31496 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31497 PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 31498 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31499 IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 31500 } 31501 31502 31503 # EMITTING VFNMADD213PD (VFNMADD213PD-128-1) 31504 { 31505 ICLASS: VFNMADD213PD 31506 CPL: 3 31507 CATEGORY: VFMA 31508 EXTENSION: AVX512EVEX 31509 ISA_SET: AVX512F_128 31510 EXCEPTIONS: AVX512-E2 31511 REAL_OPCODE: Y 31512 ATTRIBUTES: MASKOP_EVEX MXCSR 31513 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 31514 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31515 IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31516 } 31517 31518 { 31519 ICLASS: VFNMADD213PD 31520 CPL: 3 31521 CATEGORY: VFMA 31522 EXTENSION: AVX512EVEX 31523 ISA_SET: AVX512F_128 31524 EXCEPTIONS: AVX512-E2 31525 REAL_OPCODE: Y 31526 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31527 PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 31528 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31529 IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 31530 } 31531 31532 31533 # EMITTING VFNMADD213PD (VFNMADD213PD-256-1) 31534 { 31535 ICLASS: VFNMADD213PD 31536 CPL: 3 31537 CATEGORY: VFMA 31538 EXTENSION: AVX512EVEX 31539 ISA_SET: AVX512F_256 31540 EXCEPTIONS: AVX512-E2 31541 REAL_OPCODE: Y 31542 ATTRIBUTES: MASKOP_EVEX MXCSR 31543 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 31544 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 31545 IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 31546 } 31547 31548 { 31549 ICLASS: VFNMADD213PD 31550 CPL: 3 31551 CATEGORY: VFMA 31552 EXTENSION: AVX512EVEX 31553 ISA_SET: AVX512F_256 31554 EXCEPTIONS: AVX512-E2 31555 REAL_OPCODE: Y 31556 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31557 PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 31558 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31559 IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 31560 } 31561 31562 31563 # EMITTING VFNMADD213PS (VFNMADD213PS-128-1) 31564 { 31565 ICLASS: VFNMADD213PS 31566 CPL: 3 31567 CATEGORY: VFMA 31568 EXTENSION: AVX512EVEX 31569 ISA_SET: AVX512F_128 31570 EXCEPTIONS: AVX512-E2 31571 REAL_OPCODE: Y 31572 ATTRIBUTES: MASKOP_EVEX MXCSR 31573 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 31574 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31575 IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31576 } 31577 31578 { 31579 ICLASS: VFNMADD213PS 31580 CPL: 3 31581 CATEGORY: VFMA 31582 EXTENSION: AVX512EVEX 31583 ISA_SET: AVX512F_128 31584 EXCEPTIONS: AVX512-E2 31585 REAL_OPCODE: Y 31586 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31587 PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 31588 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31589 IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 31590 } 31591 31592 31593 # EMITTING VFNMADD213PS (VFNMADD213PS-256-1) 31594 { 31595 ICLASS: VFNMADD213PS 31596 CPL: 3 31597 CATEGORY: VFMA 31598 EXTENSION: AVX512EVEX 31599 ISA_SET: AVX512F_256 31600 EXCEPTIONS: AVX512-E2 31601 REAL_OPCODE: Y 31602 ATTRIBUTES: MASKOP_EVEX MXCSR 31603 PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 31604 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 31605 IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 31606 } 31607 31608 { 31609 ICLASS: VFNMADD213PS 31610 CPL: 3 31611 CATEGORY: VFMA 31612 EXTENSION: AVX512EVEX 31613 ISA_SET: AVX512F_256 31614 EXCEPTIONS: AVX512-E2 31615 REAL_OPCODE: Y 31616 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31617 PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 31618 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31619 IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 31620 } 31621 31622 31623 # EMITTING VFNMADD231PD (VFNMADD231PD-128-1) 31624 { 31625 ICLASS: VFNMADD231PD 31626 CPL: 3 31627 CATEGORY: VFMA 31628 EXTENSION: AVX512EVEX 31629 ISA_SET: AVX512F_128 31630 EXCEPTIONS: AVX512-E2 31631 REAL_OPCODE: Y 31632 ATTRIBUTES: MASKOP_EVEX MXCSR 31633 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 31634 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31635 IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31636 } 31637 31638 { 31639 ICLASS: VFNMADD231PD 31640 CPL: 3 31641 CATEGORY: VFMA 31642 EXTENSION: AVX512EVEX 31643 ISA_SET: AVX512F_128 31644 EXCEPTIONS: AVX512-E2 31645 REAL_OPCODE: Y 31646 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31647 PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 31648 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31649 IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 31650 } 31651 31652 31653 # EMITTING VFNMADD231PD (VFNMADD231PD-256-1) 31654 { 31655 ICLASS: VFNMADD231PD 31656 CPL: 3 31657 CATEGORY: VFMA 31658 EXTENSION: AVX512EVEX 31659 ISA_SET: AVX512F_256 31660 EXCEPTIONS: AVX512-E2 31661 REAL_OPCODE: Y 31662 ATTRIBUTES: MASKOP_EVEX MXCSR 31663 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 31664 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 31665 IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 31666 } 31667 31668 { 31669 ICLASS: VFNMADD231PD 31670 CPL: 3 31671 CATEGORY: VFMA 31672 EXTENSION: AVX512EVEX 31673 ISA_SET: AVX512F_256 31674 EXCEPTIONS: AVX512-E2 31675 REAL_OPCODE: Y 31676 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31677 PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 31678 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31679 IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 31680 } 31681 31682 31683 # EMITTING VFNMADD231PS (VFNMADD231PS-128-1) 31684 { 31685 ICLASS: VFNMADD231PS 31686 CPL: 3 31687 CATEGORY: VFMA 31688 EXTENSION: AVX512EVEX 31689 ISA_SET: AVX512F_128 31690 EXCEPTIONS: AVX512-E2 31691 REAL_OPCODE: Y 31692 ATTRIBUTES: MASKOP_EVEX MXCSR 31693 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 31694 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31695 IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31696 } 31697 31698 { 31699 ICLASS: VFNMADD231PS 31700 CPL: 3 31701 CATEGORY: VFMA 31702 EXTENSION: AVX512EVEX 31703 ISA_SET: AVX512F_128 31704 EXCEPTIONS: AVX512-E2 31705 REAL_OPCODE: Y 31706 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31707 PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 31708 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31709 IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 31710 } 31711 31712 31713 # EMITTING VFNMADD231PS (VFNMADD231PS-256-1) 31714 { 31715 ICLASS: VFNMADD231PS 31716 CPL: 3 31717 CATEGORY: VFMA 31718 EXTENSION: AVX512EVEX 31719 ISA_SET: AVX512F_256 31720 EXCEPTIONS: AVX512-E2 31721 REAL_OPCODE: Y 31722 ATTRIBUTES: MASKOP_EVEX MXCSR 31723 PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 31724 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 31725 IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 31726 } 31727 31728 { 31729 ICLASS: VFNMADD231PS 31730 CPL: 3 31731 CATEGORY: VFMA 31732 EXTENSION: AVX512EVEX 31733 ISA_SET: AVX512F_256 31734 EXCEPTIONS: AVX512-E2 31735 REAL_OPCODE: Y 31736 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31737 PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 31738 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31739 IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 31740 } 31741 31742 31743 # EMITTING VFNMSUB132PD (VFNMSUB132PD-128-1) 31744 { 31745 ICLASS: VFNMSUB132PD 31746 CPL: 3 31747 CATEGORY: VFMA 31748 EXTENSION: AVX512EVEX 31749 ISA_SET: AVX512F_128 31750 EXCEPTIONS: AVX512-E2 31751 REAL_OPCODE: Y 31752 ATTRIBUTES: MASKOP_EVEX MXCSR 31753 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 31754 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31755 IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31756 } 31757 31758 { 31759 ICLASS: VFNMSUB132PD 31760 CPL: 3 31761 CATEGORY: VFMA 31762 EXTENSION: AVX512EVEX 31763 ISA_SET: AVX512F_128 31764 EXCEPTIONS: AVX512-E2 31765 REAL_OPCODE: Y 31766 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31767 PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 31768 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31769 IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 31770 } 31771 31772 31773 # EMITTING VFNMSUB132PD (VFNMSUB132PD-256-1) 31774 { 31775 ICLASS: VFNMSUB132PD 31776 CPL: 3 31777 CATEGORY: VFMA 31778 EXTENSION: AVX512EVEX 31779 ISA_SET: AVX512F_256 31780 EXCEPTIONS: AVX512-E2 31781 REAL_OPCODE: Y 31782 ATTRIBUTES: MASKOP_EVEX MXCSR 31783 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 31784 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 31785 IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 31786 } 31787 31788 { 31789 ICLASS: VFNMSUB132PD 31790 CPL: 3 31791 CATEGORY: VFMA 31792 EXTENSION: AVX512EVEX 31793 ISA_SET: AVX512F_256 31794 EXCEPTIONS: AVX512-E2 31795 REAL_OPCODE: Y 31796 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31797 PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 31798 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31799 IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 31800 } 31801 31802 31803 # EMITTING VFNMSUB132PS (VFNMSUB132PS-128-1) 31804 { 31805 ICLASS: VFNMSUB132PS 31806 CPL: 3 31807 CATEGORY: VFMA 31808 EXTENSION: AVX512EVEX 31809 ISA_SET: AVX512F_128 31810 EXCEPTIONS: AVX512-E2 31811 REAL_OPCODE: Y 31812 ATTRIBUTES: MASKOP_EVEX MXCSR 31813 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 31814 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31815 IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31816 } 31817 31818 { 31819 ICLASS: VFNMSUB132PS 31820 CPL: 3 31821 CATEGORY: VFMA 31822 EXTENSION: AVX512EVEX 31823 ISA_SET: AVX512F_128 31824 EXCEPTIONS: AVX512-E2 31825 REAL_OPCODE: Y 31826 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31827 PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 31828 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31829 IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 31830 } 31831 31832 31833 # EMITTING VFNMSUB132PS (VFNMSUB132PS-256-1) 31834 { 31835 ICLASS: VFNMSUB132PS 31836 CPL: 3 31837 CATEGORY: VFMA 31838 EXTENSION: AVX512EVEX 31839 ISA_SET: AVX512F_256 31840 EXCEPTIONS: AVX512-E2 31841 REAL_OPCODE: Y 31842 ATTRIBUTES: MASKOP_EVEX MXCSR 31843 PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 31844 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 31845 IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 31846 } 31847 31848 { 31849 ICLASS: VFNMSUB132PS 31850 CPL: 3 31851 CATEGORY: VFMA 31852 EXTENSION: AVX512EVEX 31853 ISA_SET: AVX512F_256 31854 EXCEPTIONS: AVX512-E2 31855 REAL_OPCODE: Y 31856 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31857 PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 31858 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31859 IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 31860 } 31861 31862 31863 # EMITTING VFNMSUB213PD (VFNMSUB213PD-128-1) 31864 { 31865 ICLASS: VFNMSUB213PD 31866 CPL: 3 31867 CATEGORY: VFMA 31868 EXTENSION: AVX512EVEX 31869 ISA_SET: AVX512F_128 31870 EXCEPTIONS: AVX512-E2 31871 REAL_OPCODE: Y 31872 ATTRIBUTES: MASKOP_EVEX MXCSR 31873 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 31874 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31875 IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31876 } 31877 31878 { 31879 ICLASS: VFNMSUB213PD 31880 CPL: 3 31881 CATEGORY: VFMA 31882 EXTENSION: AVX512EVEX 31883 ISA_SET: AVX512F_128 31884 EXCEPTIONS: AVX512-E2 31885 REAL_OPCODE: Y 31886 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31887 PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 31888 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31889 IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 31890 } 31891 31892 31893 # EMITTING VFNMSUB213PD (VFNMSUB213PD-256-1) 31894 { 31895 ICLASS: VFNMSUB213PD 31896 CPL: 3 31897 CATEGORY: VFMA 31898 EXTENSION: AVX512EVEX 31899 ISA_SET: AVX512F_256 31900 EXCEPTIONS: AVX512-E2 31901 REAL_OPCODE: Y 31902 ATTRIBUTES: MASKOP_EVEX MXCSR 31903 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 31904 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 31905 IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 31906 } 31907 31908 { 31909 ICLASS: VFNMSUB213PD 31910 CPL: 3 31911 CATEGORY: VFMA 31912 EXTENSION: AVX512EVEX 31913 ISA_SET: AVX512F_256 31914 EXCEPTIONS: AVX512-E2 31915 REAL_OPCODE: Y 31916 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31917 PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 31918 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 31919 IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 31920 } 31921 31922 31923 # EMITTING VFNMSUB213PS (VFNMSUB213PS-128-1) 31924 { 31925 ICLASS: VFNMSUB213PS 31926 CPL: 3 31927 CATEGORY: VFMA 31928 EXTENSION: AVX512EVEX 31929 ISA_SET: AVX512F_128 31930 EXCEPTIONS: AVX512-E2 31931 REAL_OPCODE: Y 31932 ATTRIBUTES: MASKOP_EVEX MXCSR 31933 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 31934 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 31935 IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 31936 } 31937 31938 { 31939 ICLASS: VFNMSUB213PS 31940 CPL: 3 31941 CATEGORY: VFMA 31942 EXTENSION: AVX512EVEX 31943 ISA_SET: AVX512F_128 31944 EXCEPTIONS: AVX512-E2 31945 REAL_OPCODE: Y 31946 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31947 PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 31948 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31949 IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 31950 } 31951 31952 31953 # EMITTING VFNMSUB213PS (VFNMSUB213PS-256-1) 31954 { 31955 ICLASS: VFNMSUB213PS 31956 CPL: 3 31957 CATEGORY: VFMA 31958 EXTENSION: AVX512EVEX 31959 ISA_SET: AVX512F_256 31960 EXCEPTIONS: AVX512-E2 31961 REAL_OPCODE: Y 31962 ATTRIBUTES: MASKOP_EVEX MXCSR 31963 PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 31964 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 31965 IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 31966 } 31967 31968 { 31969 ICLASS: VFNMSUB213PS 31970 CPL: 3 31971 CATEGORY: VFMA 31972 EXTENSION: AVX512EVEX 31973 ISA_SET: AVX512F_256 31974 EXCEPTIONS: AVX512-E2 31975 REAL_OPCODE: Y 31976 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 31977 PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 31978 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 31979 IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 31980 } 31981 31982 31983 # EMITTING VFNMSUB231PD (VFNMSUB231PD-128-1) 31984 { 31985 ICLASS: VFNMSUB231PD 31986 CPL: 3 31987 CATEGORY: VFMA 31988 EXTENSION: AVX512EVEX 31989 ISA_SET: AVX512F_128 31990 EXCEPTIONS: AVX512-E2 31991 REAL_OPCODE: Y 31992 ATTRIBUTES: MASKOP_EVEX MXCSR 31993 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 31994 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 31995 IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 31996 } 31997 31998 { 31999 ICLASS: VFNMSUB231PD 32000 CPL: 3 32001 CATEGORY: VFMA 32002 EXTENSION: AVX512EVEX 32003 ISA_SET: AVX512F_128 32004 EXCEPTIONS: AVX512-E2 32005 REAL_OPCODE: Y 32006 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32007 PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 32008 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 32009 IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 32010 } 32011 32012 32013 # EMITTING VFNMSUB231PD (VFNMSUB231PD-256-1) 32014 { 32015 ICLASS: VFNMSUB231PD 32016 CPL: 3 32017 CATEGORY: VFMA 32018 EXTENSION: AVX512EVEX 32019 ISA_SET: AVX512F_256 32020 EXCEPTIONS: AVX512-E2 32021 REAL_OPCODE: Y 32022 ATTRIBUTES: MASKOP_EVEX MXCSR 32023 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 32024 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 32025 IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 32026 } 32027 32028 { 32029 ICLASS: VFNMSUB231PD 32030 CPL: 3 32031 CATEGORY: VFMA 32032 EXTENSION: AVX512EVEX 32033 ISA_SET: AVX512F_256 32034 EXCEPTIONS: AVX512-E2 32035 REAL_OPCODE: Y 32036 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32037 PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 32038 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 32039 IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 32040 } 32041 32042 32043 # EMITTING VFNMSUB231PS (VFNMSUB231PS-128-1) 32044 { 32045 ICLASS: VFNMSUB231PS 32046 CPL: 3 32047 CATEGORY: VFMA 32048 EXTENSION: AVX512EVEX 32049 ISA_SET: AVX512F_128 32050 EXCEPTIONS: AVX512-E2 32051 REAL_OPCODE: Y 32052 ATTRIBUTES: MASKOP_EVEX MXCSR 32053 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 32054 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 32055 IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 32056 } 32057 32058 { 32059 ICLASS: VFNMSUB231PS 32060 CPL: 3 32061 CATEGORY: VFMA 32062 EXTENSION: AVX512EVEX 32063 ISA_SET: AVX512F_128 32064 EXCEPTIONS: AVX512-E2 32065 REAL_OPCODE: Y 32066 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32067 PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 32068 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 32069 IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 32070 } 32071 32072 32073 # EMITTING VFNMSUB231PS (VFNMSUB231PS-256-1) 32074 { 32075 ICLASS: VFNMSUB231PS 32076 CPL: 3 32077 CATEGORY: VFMA 32078 EXTENSION: AVX512EVEX 32079 ISA_SET: AVX512F_256 32080 EXCEPTIONS: AVX512-E2 32081 REAL_OPCODE: Y 32082 ATTRIBUTES: MASKOP_EVEX MXCSR 32083 PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 32084 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 32085 IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 32086 } 32087 32088 { 32089 ICLASS: VFNMSUB231PS 32090 CPL: 3 32091 CATEGORY: VFMA 32092 EXTENSION: AVX512EVEX 32093 ISA_SET: AVX512F_256 32094 EXCEPTIONS: AVX512-E2 32095 REAL_OPCODE: Y 32096 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32097 PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 32098 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 32099 IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 32100 } 32101 32102 32103 # EMITTING VFPCLASSPD (VFPCLASSPD-128-1) 32104 { 32105 ICLASS: VFPCLASSPD 32106 CPL: 3 32107 CATEGORY: AVX512 32108 EXTENSION: AVX512EVEX 32109 ISA_SET: AVX512DQ_128 32110 EXCEPTIONS: AVX512-E4 32111 REAL_OPCODE: Y 32112 ATTRIBUTES: MASKOP_EVEX MXCSR 32113 PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 UIMM8() 32114 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b 32115 IFORM: VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 32116 } 32117 32118 { 32119 ICLASS: VFPCLASSPD 32120 CPL: 3 32121 CATEGORY: AVX512 32122 EXTENSION: AVX512EVEX 32123 ISA_SET: AVX512DQ_128 32124 EXCEPTIONS: AVX512-E4 32125 REAL_OPCODE: Y 32126 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32127 PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 32128 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 32129 IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 32130 } 32131 32132 32133 # EMITTING VFPCLASSPD (VFPCLASSPD-256-1) 32134 { 32135 ICLASS: VFPCLASSPD 32136 CPL: 3 32137 CATEGORY: AVX512 32138 EXTENSION: AVX512EVEX 32139 ISA_SET: AVX512DQ_256 32140 EXCEPTIONS: AVX512-E4 32141 REAL_OPCODE: Y 32142 ATTRIBUTES: MASKOP_EVEX MXCSR 32143 PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 UIMM8() 32144 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f64 IMM0:r:b 32145 IFORM: VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 32146 } 32147 32148 { 32149 ICLASS: VFPCLASSPD 32150 CPL: 3 32151 CATEGORY: AVX512 32152 EXTENSION: AVX512EVEX 32153 ISA_SET: AVX512DQ_256 32154 EXCEPTIONS: AVX512-E4 32155 REAL_OPCODE: Y 32156 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32157 PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 32158 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 32159 IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 32160 } 32161 32162 32163 # EMITTING VFPCLASSPD (VFPCLASSPD-512-1) 32164 { 32165 ICLASS: VFPCLASSPD 32166 CPL: 3 32167 CATEGORY: AVX512 32168 EXTENSION: AVX512EVEX 32169 ISA_SET: AVX512DQ_512 32170 EXCEPTIONS: AVX512-E4 32171 REAL_OPCODE: Y 32172 ATTRIBUTES: MASKOP_EVEX MXCSR 32173 PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 UIMM8() 32174 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b 32175 IFORM: VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 32176 } 32177 32178 { 32179 ICLASS: VFPCLASSPD 32180 CPL: 3 32181 CATEGORY: AVX512 32182 EXTENSION: AVX512EVEX 32183 ISA_SET: AVX512DQ_512 32184 EXCEPTIONS: AVX512-E4 32185 REAL_OPCODE: Y 32186 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32187 PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 32188 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 32189 IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 32190 } 32191 32192 32193 # EMITTING VFPCLASSPS (VFPCLASSPS-128-1) 32194 { 32195 ICLASS: VFPCLASSPS 32196 CPL: 3 32197 CATEGORY: AVX512 32198 EXTENSION: AVX512EVEX 32199 ISA_SET: AVX512DQ_128 32200 EXCEPTIONS: AVX512-E4 32201 REAL_OPCODE: Y 32202 ATTRIBUTES: MASKOP_EVEX MXCSR 32203 PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8() 32204 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b 32205 IFORM: VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 32206 } 32207 32208 { 32209 ICLASS: VFPCLASSPS 32210 CPL: 3 32211 CATEGORY: AVX512 32212 EXTENSION: AVX512EVEX 32213 ISA_SET: AVX512DQ_128 32214 EXCEPTIONS: AVX512-E4 32215 REAL_OPCODE: Y 32216 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32217 PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 32218 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 32219 IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 32220 } 32221 32222 32223 # EMITTING VFPCLASSPS (VFPCLASSPS-256-1) 32224 { 32225 ICLASS: VFPCLASSPS 32226 CPL: 3 32227 CATEGORY: AVX512 32228 EXTENSION: AVX512EVEX 32229 ISA_SET: AVX512DQ_256 32230 EXCEPTIONS: AVX512-E4 32231 REAL_OPCODE: Y 32232 ATTRIBUTES: MASKOP_EVEX MXCSR 32233 PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8() 32234 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f32 IMM0:r:b 32235 IFORM: VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 32236 } 32237 32238 { 32239 ICLASS: VFPCLASSPS 32240 CPL: 3 32241 CATEGORY: AVX512 32242 EXTENSION: AVX512EVEX 32243 ISA_SET: AVX512DQ_256 32244 EXCEPTIONS: AVX512-E4 32245 REAL_OPCODE: Y 32246 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32247 PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 32248 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 32249 IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 32250 } 32251 32252 32253 # EMITTING VFPCLASSPS (VFPCLASSPS-512-1) 32254 { 32255 ICLASS: VFPCLASSPS 32256 CPL: 3 32257 CATEGORY: AVX512 32258 EXTENSION: AVX512EVEX 32259 ISA_SET: AVX512DQ_512 32260 EXCEPTIONS: AVX512-E4 32261 REAL_OPCODE: Y 32262 ATTRIBUTES: MASKOP_EVEX MXCSR 32263 PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8() 32264 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 IMM0:r:b 32265 IFORM: VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 32266 } 32267 32268 { 32269 ICLASS: VFPCLASSPS 32270 CPL: 3 32271 CATEGORY: AVX512 32272 EXTENSION: AVX512EVEX 32273 ISA_SET: AVX512DQ_512 32274 EXCEPTIONS: AVX512-E4 32275 REAL_OPCODE: Y 32276 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32277 PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 32278 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 32279 IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 32280 } 32281 32282 32283 # EMITTING VFPCLASSSD (VFPCLASSSD-128-1) 32284 { 32285 ICLASS: VFPCLASSSD 32286 CPL: 3 32287 CATEGORY: AVX512 32288 EXTENSION: AVX512EVEX 32289 ISA_SET: AVX512DQ_SCALAR 32290 EXCEPTIONS: AVX512-E6 32291 REAL_OPCODE: Y 32292 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 32293 PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 UIMM8() 32294 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b 32295 IFORM: VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 32296 } 32297 32298 { 32299 ICLASS: VFPCLASSSD 32300 CPL: 3 32301 CATEGORY: AVX512 32302 EXTENSION: AVX512EVEX 32303 ISA_SET: AVX512DQ_SCALAR 32304 EXCEPTIONS: AVX512-E6 32305 REAL_OPCODE: Y 32306 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 32307 PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 32308 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:q:f64 IMM0:r:b 32309 IFORM: VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 32310 } 32311 32312 32313 # EMITTING VFPCLASSSS (VFPCLASSSS-128-1) 32314 { 32315 ICLASS: VFPCLASSSS 32316 CPL: 3 32317 CATEGORY: AVX512 32318 EXTENSION: AVX512EVEX 32319 ISA_SET: AVX512DQ_SCALAR 32320 EXCEPTIONS: AVX512-E6 32321 REAL_OPCODE: Y 32322 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 32323 PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 UIMM8() 32324 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b 32325 IFORM: VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 32326 } 32327 32328 { 32329 ICLASS: VFPCLASSSS 32330 CPL: 3 32331 CATEGORY: AVX512 32332 EXTENSION: AVX512EVEX 32333 ISA_SET: AVX512DQ_SCALAR 32334 EXCEPTIONS: AVX512-E6 32335 REAL_OPCODE: Y 32336 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 32337 PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 32338 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:d:f32 IMM0:r:b 32339 IFORM: VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 32340 } 32341 32342 32343 # EMITTING VGATHERDPD (VGATHERDPD-128-2) 32344 { 32345 ICLASS: VGATHERDPD 32346 CPL: 3 32347 CATEGORY: GATHER 32348 EXTENSION: AVX512EVEX 32349 ISA_SET: AVX512F_128 32350 EXCEPTIONS: AVX512-E12 32351 REAL_OPCODE: Y 32352 ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 32353 PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 32354 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 32355 IFORM: VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 32356 } 32357 32358 32359 # EMITTING VGATHERDPD (VGATHERDPD-256-2) 32360 { 32361 ICLASS: VGATHERDPD 32362 CPL: 3 32363 CATEGORY: GATHER 32364 EXTENSION: AVX512EVEX 32365 ISA_SET: AVX512F_256 32366 EXCEPTIONS: AVX512-E12 32367 REAL_OPCODE: Y 32368 ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 32369 PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 32370 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 32371 IFORM: VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 32372 } 32373 32374 32375 # EMITTING VGATHERDPS (VGATHERDPS-128-2) 32376 { 32377 ICLASS: VGATHERDPS 32378 CPL: 3 32379 CATEGORY: GATHER 32380 EXTENSION: AVX512EVEX 32381 ISA_SET: AVX512F_128 32382 EXCEPTIONS: AVX512-E12 32383 REAL_OPCODE: Y 32384 ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 32385 PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 32386 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 32387 IFORM: VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 32388 } 32389 32390 32391 # EMITTING VGATHERDPS (VGATHERDPS-256-2) 32392 { 32393 ICLASS: VGATHERDPS 32394 CPL: 3 32395 CATEGORY: GATHER 32396 EXTENSION: AVX512EVEX 32397 ISA_SET: AVX512F_256 32398 EXCEPTIONS: AVX512-E12 32399 REAL_OPCODE: Y 32400 ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 32401 PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 32402 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 32403 IFORM: VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 32404 } 32405 32406 32407 # EMITTING VGATHERQPD (VGATHERQPD-128-2) 32408 { 32409 ICLASS: VGATHERQPD 32410 CPL: 3 32411 CATEGORY: GATHER 32412 EXTENSION: AVX512EVEX 32413 ISA_SET: AVX512F_128 32414 EXCEPTIONS: AVX512-E12 32415 REAL_OPCODE: Y 32416 ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 32417 PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 32418 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 32419 IFORM: VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 32420 } 32421 32422 32423 # EMITTING VGATHERQPD (VGATHERQPD-256-2) 32424 { 32425 ICLASS: VGATHERQPD 32426 CPL: 3 32427 CATEGORY: GATHER 32428 EXTENSION: AVX512EVEX 32429 ISA_SET: AVX512F_256 32430 EXCEPTIONS: AVX512-E12 32431 REAL_OPCODE: Y 32432 ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 32433 PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 32434 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 32435 IFORM: VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 32436 } 32437 32438 32439 # EMITTING VGATHERQPS (VGATHERQPS-128-2) 32440 { 32441 ICLASS: VGATHERQPS 32442 CPL: 3 32443 CATEGORY: GATHER 32444 EXTENSION: AVX512EVEX 32445 ISA_SET: AVX512F_128 32446 EXCEPTIONS: AVX512-E12 32447 REAL_OPCODE: Y 32448 ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 32449 PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 32450 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 32451 IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 32452 } 32453 32454 32455 # EMITTING VGATHERQPS (VGATHERQPS-256-2) 32456 { 32457 ICLASS: VGATHERQPS 32458 CPL: 3 32459 CATEGORY: GATHER 32460 EXTENSION: AVX512EVEX 32461 ISA_SET: AVX512F_256 32462 EXCEPTIONS: AVX512-E12 32463 REAL_OPCODE: Y 32464 ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 32465 PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 32466 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 32467 IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 32468 } 32469 32470 32471 # EMITTING VGETEXPPD (VGETEXPPD-128-1) 32472 { 32473 ICLASS: VGETEXPPD 32474 CPL: 3 32475 CATEGORY: AVX512 32476 EXTENSION: AVX512EVEX 32477 ISA_SET: AVX512F_128 32478 EXCEPTIONS: AVX512-E2 32479 REAL_OPCODE: Y 32480 ATTRIBUTES: MASKOP_EVEX MXCSR 32481 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 32482 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 32483 IFORM: VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 32484 } 32485 32486 { 32487 ICLASS: VGETEXPPD 32488 CPL: 3 32489 CATEGORY: AVX512 32490 EXTENSION: AVX512EVEX 32491 ISA_SET: AVX512F_128 32492 EXCEPTIONS: AVX512-E2 32493 REAL_OPCODE: Y 32494 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32495 PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 32496 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 32497 IFORM: VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 32498 } 32499 32500 32501 # EMITTING VGETEXPPD (VGETEXPPD-256-1) 32502 { 32503 ICLASS: VGETEXPPD 32504 CPL: 3 32505 CATEGORY: AVX512 32506 EXTENSION: AVX512EVEX 32507 ISA_SET: AVX512F_256 32508 EXCEPTIONS: AVX512-E2 32509 REAL_OPCODE: Y 32510 ATTRIBUTES: MASKOP_EVEX MXCSR 32511 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 32512 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 32513 IFORM: VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 32514 } 32515 32516 { 32517 ICLASS: VGETEXPPD 32518 CPL: 3 32519 CATEGORY: AVX512 32520 EXTENSION: AVX512EVEX 32521 ISA_SET: AVX512F_256 32522 EXCEPTIONS: AVX512-E2 32523 REAL_OPCODE: Y 32524 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32525 PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 32526 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 32527 IFORM: VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 32528 } 32529 32530 32531 # EMITTING VGETEXPPS (VGETEXPPS-128-1) 32532 { 32533 ICLASS: VGETEXPPS 32534 CPL: 3 32535 CATEGORY: AVX512 32536 EXTENSION: AVX512EVEX 32537 ISA_SET: AVX512F_128 32538 EXCEPTIONS: AVX512-E2 32539 REAL_OPCODE: Y 32540 ATTRIBUTES: MASKOP_EVEX MXCSR 32541 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 32542 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 32543 IFORM: VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 32544 } 32545 32546 { 32547 ICLASS: VGETEXPPS 32548 CPL: 3 32549 CATEGORY: AVX512 32550 EXTENSION: AVX512EVEX 32551 ISA_SET: AVX512F_128 32552 EXCEPTIONS: AVX512-E2 32553 REAL_OPCODE: Y 32554 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32555 PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 32556 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 32557 IFORM: VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 32558 } 32559 32560 32561 # EMITTING VGETEXPPS (VGETEXPPS-256-1) 32562 { 32563 ICLASS: VGETEXPPS 32564 CPL: 3 32565 CATEGORY: AVX512 32566 EXTENSION: AVX512EVEX 32567 ISA_SET: AVX512F_256 32568 EXCEPTIONS: AVX512-E2 32569 REAL_OPCODE: Y 32570 ATTRIBUTES: MASKOP_EVEX MXCSR 32571 PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 32572 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 32573 IFORM: VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 32574 } 32575 32576 { 32577 ICLASS: VGETEXPPS 32578 CPL: 3 32579 CATEGORY: AVX512 32580 EXTENSION: AVX512EVEX 32581 ISA_SET: AVX512F_256 32582 EXCEPTIONS: AVX512-E2 32583 REAL_OPCODE: Y 32584 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32585 PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 32586 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 32587 IFORM: VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 32588 } 32589 32590 32591 # EMITTING VGETMANTPD (VGETMANTPD-128-1) 32592 { 32593 ICLASS: VGETMANTPD 32594 CPL: 3 32595 CATEGORY: AVX512 32596 EXTENSION: AVX512EVEX 32597 ISA_SET: AVX512F_128 32598 EXCEPTIONS: AVX512-E2 32599 REAL_OPCODE: Y 32600 ATTRIBUTES: MASKOP_EVEX MXCSR 32601 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() 32602 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b 32603 IFORM: VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 32604 } 32605 32606 { 32607 ICLASS: VGETMANTPD 32608 CPL: 3 32609 CATEGORY: AVX512 32610 EXTENSION: AVX512EVEX 32611 ISA_SET: AVX512F_128 32612 EXCEPTIONS: AVX512-E2 32613 REAL_OPCODE: Y 32614 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32615 PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 32616 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 32617 IFORM: VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 32618 } 32619 32620 32621 # EMITTING VGETMANTPD (VGETMANTPD-256-1) 32622 { 32623 ICLASS: VGETMANTPD 32624 CPL: 3 32625 CATEGORY: AVX512 32626 EXTENSION: AVX512EVEX 32627 ISA_SET: AVX512F_256 32628 EXCEPTIONS: AVX512-E2 32629 REAL_OPCODE: Y 32630 ATTRIBUTES: MASKOP_EVEX MXCSR 32631 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 32632 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b 32633 IFORM: VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 32634 } 32635 32636 { 32637 ICLASS: VGETMANTPD 32638 CPL: 3 32639 CATEGORY: AVX512 32640 EXTENSION: AVX512EVEX 32641 ISA_SET: AVX512F_256 32642 EXCEPTIONS: AVX512-E2 32643 REAL_OPCODE: Y 32644 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32645 PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 32646 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 32647 IFORM: VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 32648 } 32649 32650 32651 # EMITTING VGETMANTPS (VGETMANTPS-128-1) 32652 { 32653 ICLASS: VGETMANTPS 32654 CPL: 3 32655 CATEGORY: AVX512 32656 EXTENSION: AVX512EVEX 32657 ISA_SET: AVX512F_128 32658 EXCEPTIONS: AVX512-E2 32659 REAL_OPCODE: Y 32660 ATTRIBUTES: MASKOP_EVEX MXCSR 32661 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() 32662 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b 32663 IFORM: VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 32664 } 32665 32666 { 32667 ICLASS: VGETMANTPS 32668 CPL: 3 32669 CATEGORY: AVX512 32670 EXTENSION: AVX512EVEX 32671 ISA_SET: AVX512F_128 32672 EXCEPTIONS: AVX512-E2 32673 REAL_OPCODE: Y 32674 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32675 PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 32676 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 32677 IFORM: VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 32678 } 32679 32680 32681 # EMITTING VGETMANTPS (VGETMANTPS-256-1) 32682 { 32683 ICLASS: VGETMANTPS 32684 CPL: 3 32685 CATEGORY: AVX512 32686 EXTENSION: AVX512EVEX 32687 ISA_SET: AVX512F_256 32688 EXCEPTIONS: AVX512-E2 32689 REAL_OPCODE: Y 32690 ATTRIBUTES: MASKOP_EVEX MXCSR 32691 PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 32692 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b 32693 IFORM: VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 32694 } 32695 32696 { 32697 ICLASS: VGETMANTPS 32698 CPL: 3 32699 CATEGORY: AVX512 32700 EXTENSION: AVX512EVEX 32701 ISA_SET: AVX512F_256 32702 EXCEPTIONS: AVX512-E2 32703 REAL_OPCODE: Y 32704 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32705 PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 32706 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 32707 IFORM: VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 32708 } 32709 32710 32711 # EMITTING VINSERTF32X4 (VINSERTF32X4-256-1) 32712 { 32713 ICLASS: VINSERTF32X4 32714 CPL: 3 32715 CATEGORY: AVX512 32716 EXTENSION: AVX512EVEX 32717 ISA_SET: AVX512F_256 32718 EXCEPTIONS: AVX512-E6NF 32719 REAL_OPCODE: Y 32720 ATTRIBUTES: MASKOP_EVEX 32721 PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 32722 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 32723 IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 32724 } 32725 32726 { 32727 ICLASS: VINSERTF32X4 32728 CPL: 3 32729 CATEGORY: AVX512 32730 EXTENSION: AVX512EVEX 32731 ISA_SET: AVX512F_256 32732 EXCEPTIONS: AVX512-E6NF 32733 REAL_OPCODE: Y 32734 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 32735 PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 32736 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:dq:f32 IMM0:r:b 32737 IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 32738 } 32739 32740 32741 # EMITTING VINSERTF32X8 (VINSERTF32X8-512-1) 32742 { 32743 ICLASS: VINSERTF32X8 32744 CPL: 3 32745 CATEGORY: AVX512 32746 EXTENSION: AVX512EVEX 32747 ISA_SET: AVX512DQ_512 32748 EXCEPTIONS: AVX512-E6NF 32749 REAL_OPCODE: Y 32750 ATTRIBUTES: MASKOP_EVEX 32751 PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 32752 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=YMM_B3():r:qq:f32 IMM0:r:b 32753 IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 32754 } 32755 32756 { 32757 ICLASS: VINSERTF32X8 32758 CPL: 3 32759 CATEGORY: AVX512 32760 EXTENSION: AVX512EVEX 32761 ISA_SET: AVX512DQ_512 32762 EXCEPTIONS: AVX512-E6NF 32763 REAL_OPCODE: Y 32764 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 32765 PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() 32766 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:qq:f32 IMM0:r:b 32767 IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 32768 } 32769 32770 32771 # EMITTING VINSERTF64X2 (VINSERTF64X2-256-1) 32772 { 32773 ICLASS: VINSERTF64X2 32774 CPL: 3 32775 CATEGORY: AVX512 32776 EXTENSION: AVX512EVEX 32777 ISA_SET: AVX512DQ_256 32778 EXCEPTIONS: AVX512-E6NF 32779 REAL_OPCODE: Y 32780 ATTRIBUTES: MASKOP_EVEX 32781 PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 32782 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 32783 IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 32784 } 32785 32786 { 32787 ICLASS: VINSERTF64X2 32788 CPL: 3 32789 CATEGORY: AVX512 32790 EXTENSION: AVX512EVEX 32791 ISA_SET: AVX512DQ_256 32792 EXCEPTIONS: AVX512-E6NF 32793 REAL_OPCODE: Y 32794 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 32795 PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 32796 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b 32797 IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 32798 } 32799 32800 32801 # EMITTING VINSERTF64X2 (VINSERTF64X2-512-1) 32802 { 32803 ICLASS: VINSERTF64X2 32804 CPL: 3 32805 CATEGORY: AVX512 32806 EXTENSION: AVX512EVEX 32807 ISA_SET: AVX512DQ_512 32808 EXCEPTIONS: AVX512-E6NF 32809 REAL_OPCODE: Y 32810 ATTRIBUTES: MASKOP_EVEX 32811 PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 32812 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 32813 IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 32814 } 32815 32816 { 32817 ICLASS: VINSERTF64X2 32818 CPL: 3 32819 CATEGORY: AVX512 32820 EXTENSION: AVX512EVEX 32821 ISA_SET: AVX512DQ_512 32822 EXCEPTIONS: AVX512-E6NF 32823 REAL_OPCODE: Y 32824 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 32825 PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 32826 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:dq:f64 IMM0:r:b 32827 IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 32828 } 32829 32830 32831 # EMITTING VINSERTI32X4 (VINSERTI32X4-256-1) 32832 { 32833 ICLASS: VINSERTI32X4 32834 CPL: 3 32835 CATEGORY: AVX512 32836 EXTENSION: AVX512EVEX 32837 ISA_SET: AVX512F_256 32838 EXCEPTIONS: AVX512-E6NF 32839 REAL_OPCODE: Y 32840 ATTRIBUTES: MASKOP_EVEX 32841 PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 32842 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b 32843 IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 32844 } 32845 32846 { 32847 ICLASS: VINSERTI32X4 32848 CPL: 3 32849 CATEGORY: AVX512 32850 EXTENSION: AVX512EVEX 32851 ISA_SET: AVX512F_256 32852 EXCEPTIONS: AVX512-E6NF 32853 REAL_OPCODE: Y 32854 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 32855 PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() 32856 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 IMM0:r:b 32857 IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 32858 } 32859 32860 32861 # EMITTING VINSERTI32X8 (VINSERTI32X8-512-1) 32862 { 32863 ICLASS: VINSERTI32X8 32864 CPL: 3 32865 CATEGORY: AVX512 32866 EXTENSION: AVX512EVEX 32867 ISA_SET: AVX512DQ_512 32868 EXCEPTIONS: AVX512-E6NF 32869 REAL_OPCODE: Y 32870 ATTRIBUTES: MASKOP_EVEX 32871 PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 32872 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=YMM_B3():r:qq:u32 IMM0:r:b 32873 IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 32874 } 32875 32876 { 32877 ICLASS: VINSERTI32X8 32878 CPL: 3 32879 CATEGORY: AVX512 32880 EXTENSION: AVX512EVEX 32881 ISA_SET: AVX512DQ_512 32882 EXCEPTIONS: AVX512-E6NF 32883 REAL_OPCODE: Y 32884 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 32885 PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() 32886 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:qq:u32 IMM0:r:b 32887 IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 32888 } 32889 32890 32891 # EMITTING VINSERTI64X2 (VINSERTI64X2-256-1) 32892 { 32893 ICLASS: VINSERTI64X2 32894 CPL: 3 32895 CATEGORY: AVX512 32896 EXTENSION: AVX512EVEX 32897 ISA_SET: AVX512DQ_256 32898 EXCEPTIONS: AVX512-E6NF 32899 REAL_OPCODE: Y 32900 ATTRIBUTES: MASKOP_EVEX 32901 PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 32902 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b 32903 IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 32904 } 32905 32906 { 32907 ICLASS: VINSERTI64X2 32908 CPL: 3 32909 CATEGORY: AVX512 32910 EXTENSION: AVX512EVEX 32911 ISA_SET: AVX512DQ_256 32912 EXCEPTIONS: AVX512-E6NF 32913 REAL_OPCODE: Y 32914 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 32915 PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 32916 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 IMM0:r:b 32917 IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 32918 } 32919 32920 32921 # EMITTING VINSERTI64X2 (VINSERTI64X2-512-1) 32922 { 32923 ICLASS: VINSERTI64X2 32924 CPL: 3 32925 CATEGORY: AVX512 32926 EXTENSION: AVX512EVEX 32927 ISA_SET: AVX512DQ_512 32928 EXCEPTIONS: AVX512-E6NF 32929 REAL_OPCODE: Y 32930 ATTRIBUTES: MASKOP_EVEX 32931 PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 32932 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 IMM0:r:b 32933 IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 32934 } 32935 32936 { 32937 ICLASS: VINSERTI64X2 32938 CPL: 3 32939 CATEGORY: AVX512 32940 EXTENSION: AVX512EVEX 32941 ISA_SET: AVX512DQ_512 32942 EXCEPTIONS: AVX512-E6NF 32943 REAL_OPCODE: Y 32944 ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 32945 PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() 32946 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 IMM0:r:b 32947 IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 32948 } 32949 32950 32951 # EMITTING VMAXPD (VMAXPD-128-1) 32952 { 32953 ICLASS: VMAXPD 32954 CPL: 3 32955 CATEGORY: AVX512 32956 EXTENSION: AVX512EVEX 32957 ISA_SET: AVX512F_128 32958 EXCEPTIONS: AVX512-E2 32959 REAL_OPCODE: Y 32960 ATTRIBUTES: MASKOP_EVEX MXCSR 32961 PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 32962 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 32963 IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 32964 } 32965 32966 { 32967 ICLASS: VMAXPD 32968 CPL: 3 32969 CATEGORY: AVX512 32970 EXTENSION: AVX512EVEX 32971 ISA_SET: AVX512F_128 32972 EXCEPTIONS: AVX512-E2 32973 REAL_OPCODE: Y 32974 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 32975 PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 32976 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 32977 IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 32978 } 32979 32980 32981 # EMITTING VMAXPD (VMAXPD-256-1) 32982 { 32983 ICLASS: VMAXPD 32984 CPL: 3 32985 CATEGORY: AVX512 32986 EXTENSION: AVX512EVEX 32987 ISA_SET: AVX512F_256 32988 EXCEPTIONS: AVX512-E2 32989 REAL_OPCODE: Y 32990 ATTRIBUTES: MASKOP_EVEX MXCSR 32991 PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 32992 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 32993 IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 32994 } 32995 32996 { 32997 ICLASS: VMAXPD 32998 CPL: 3 32999 CATEGORY: AVX512 33000 EXTENSION: AVX512EVEX 33001 ISA_SET: AVX512F_256 33002 EXCEPTIONS: AVX512-E2 33003 REAL_OPCODE: Y 33004 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 33005 PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 33006 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 33007 IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 33008 } 33009 33010 33011 # EMITTING VMAXPS (VMAXPS-128-1) 33012 { 33013 ICLASS: VMAXPS 33014 CPL: 3 33015 CATEGORY: AVX512 33016 EXTENSION: AVX512EVEX 33017 ISA_SET: AVX512F_128 33018 EXCEPTIONS: AVX512-E2 33019 REAL_OPCODE: Y 33020 ATTRIBUTES: MASKOP_EVEX MXCSR 33021 PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 33022 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 33023 IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 33024 } 33025 33026 { 33027 ICLASS: VMAXPS 33028 CPL: 3 33029 CATEGORY: AVX512 33030 EXTENSION: AVX512EVEX 33031 ISA_SET: AVX512F_128 33032 EXCEPTIONS: AVX512-E2 33033 REAL_OPCODE: Y 33034 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 33035 PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 33036 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 33037 IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 33038 } 33039 33040 33041 # EMITTING VMAXPS (VMAXPS-256-1) 33042 { 33043 ICLASS: VMAXPS 33044 CPL: 3 33045 CATEGORY: AVX512 33046 EXTENSION: AVX512EVEX 33047 ISA_SET: AVX512F_256 33048 EXCEPTIONS: AVX512-E2 33049 REAL_OPCODE: Y 33050 ATTRIBUTES: MASKOP_EVEX MXCSR 33051 PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 33052 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 33053 IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 33054 } 33055 33056 { 33057 ICLASS: VMAXPS 33058 CPL: 3 33059 CATEGORY: AVX512 33060 EXTENSION: AVX512EVEX 33061 ISA_SET: AVX512F_256 33062 EXCEPTIONS: AVX512-E2 33063 REAL_OPCODE: Y 33064 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 33065 PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 33066 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 33067 IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 33068 } 33069 33070 33071 # EMITTING VMINPD (VMINPD-128-1) 33072 { 33073 ICLASS: VMINPD 33074 CPL: 3 33075 CATEGORY: AVX512 33076 EXTENSION: AVX512EVEX 33077 ISA_SET: AVX512F_128 33078 EXCEPTIONS: AVX512-E2 33079 REAL_OPCODE: Y 33080 ATTRIBUTES: MASKOP_EVEX MXCSR 33081 PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 33082 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 33083 IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 33084 } 33085 33086 { 33087 ICLASS: VMINPD 33088 CPL: 3 33089 CATEGORY: AVX512 33090 EXTENSION: AVX512EVEX 33091 ISA_SET: AVX512F_128 33092 EXCEPTIONS: AVX512-E2 33093 REAL_OPCODE: Y 33094 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 33095 PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 33096 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 33097 IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 33098 } 33099 33100 33101 # EMITTING VMINPD (VMINPD-256-1) 33102 { 33103 ICLASS: VMINPD 33104 CPL: 3 33105 CATEGORY: AVX512 33106 EXTENSION: AVX512EVEX 33107 ISA_SET: AVX512F_256 33108 EXCEPTIONS: AVX512-E2 33109 REAL_OPCODE: Y 33110 ATTRIBUTES: MASKOP_EVEX MXCSR 33111 PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 33112 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 33113 IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 33114 } 33115 33116 { 33117 ICLASS: VMINPD 33118 CPL: 3 33119 CATEGORY: AVX512 33120 EXTENSION: AVX512EVEX 33121 ISA_SET: AVX512F_256 33122 EXCEPTIONS: AVX512-E2 33123 REAL_OPCODE: Y 33124 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 33125 PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 33126 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 33127 IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 33128 } 33129 33130 33131 # EMITTING VMINPS (VMINPS-128-1) 33132 { 33133 ICLASS: VMINPS 33134 CPL: 3 33135 CATEGORY: AVX512 33136 EXTENSION: AVX512EVEX 33137 ISA_SET: AVX512F_128 33138 EXCEPTIONS: AVX512-E2 33139 REAL_OPCODE: Y 33140 ATTRIBUTES: MASKOP_EVEX MXCSR 33141 PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 33142 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 33143 IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 33144 } 33145 33146 { 33147 ICLASS: VMINPS 33148 CPL: 3 33149 CATEGORY: AVX512 33150 EXTENSION: AVX512EVEX 33151 ISA_SET: AVX512F_128 33152 EXCEPTIONS: AVX512-E2 33153 REAL_OPCODE: Y 33154 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 33155 PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 33156 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 33157 IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 33158 } 33159 33160 33161 # EMITTING VMINPS (VMINPS-256-1) 33162 { 33163 ICLASS: VMINPS 33164 CPL: 3 33165 CATEGORY: AVX512 33166 EXTENSION: AVX512EVEX 33167 ISA_SET: AVX512F_256 33168 EXCEPTIONS: AVX512-E2 33169 REAL_OPCODE: Y 33170 ATTRIBUTES: MASKOP_EVEX MXCSR 33171 PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 33172 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 33173 IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 33174 } 33175 33176 { 33177 ICLASS: VMINPS 33178 CPL: 3 33179 CATEGORY: AVX512 33180 EXTENSION: AVX512EVEX 33181 ISA_SET: AVX512F_256 33182 EXCEPTIONS: AVX512-E2 33183 REAL_OPCODE: Y 33184 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 33185 PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 33186 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 33187 IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 33188 } 33189 33190 33191 # EMITTING VMOVAPD (VMOVAPD-128-1) 33192 { 33193 ICLASS: VMOVAPD 33194 CPL: 3 33195 CATEGORY: DATAXFER 33196 EXTENSION: AVX512EVEX 33197 ISA_SET: AVX512F_128 33198 EXCEPTIONS: AVX512-E1 33199 REAL_OPCODE: Y 33200 ATTRIBUTES: MASKOP_EVEX 33201 PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 33202 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 33203 IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 33204 } 33205 33206 { 33207 ICLASS: VMOVAPD 33208 CPL: 3 33209 CATEGORY: DATAXFER 33210 EXTENSION: AVX512EVEX 33211 ISA_SET: AVX512F_128 33212 EXCEPTIONS: AVX512-E1 33213 REAL_OPCODE: Y 33214 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33215 PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 33216 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 33217 IFORM: VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 33218 } 33219 33220 33221 # EMITTING VMOVAPD (VMOVAPD-128-2) 33222 { 33223 ICLASS: VMOVAPD 33224 CPL: 3 33225 CATEGORY: DATAXFER 33226 EXTENSION: AVX512EVEX 33227 ISA_SET: AVX512F_128 33228 EXCEPTIONS: AVX512-E1 33229 REAL_OPCODE: Y 33230 ATTRIBUTES: MASKOP_EVEX 33231 PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 33232 OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 33233 IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 33234 } 33235 33236 33237 # EMITTING VMOVAPD (VMOVAPD-128-3) 33238 { 33239 ICLASS: VMOVAPD 33240 CPL: 3 33241 CATEGORY: DATAXFER 33242 EXTENSION: AVX512EVEX 33243 ISA_SET: AVX512F_128 33244 EXCEPTIONS: AVX512-E1 33245 REAL_OPCODE: Y 33246 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33247 PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 33248 OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 33249 IFORM: VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 33250 } 33251 33252 33253 # EMITTING VMOVAPD (VMOVAPD-256-1) 33254 { 33255 ICLASS: VMOVAPD 33256 CPL: 3 33257 CATEGORY: DATAXFER 33258 EXTENSION: AVX512EVEX 33259 ISA_SET: AVX512F_256 33260 EXCEPTIONS: AVX512-E1 33261 REAL_OPCODE: Y 33262 ATTRIBUTES: MASKOP_EVEX 33263 PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 33264 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 33265 IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 33266 } 33267 33268 { 33269 ICLASS: VMOVAPD 33270 CPL: 3 33271 CATEGORY: DATAXFER 33272 EXTENSION: AVX512EVEX 33273 ISA_SET: AVX512F_256 33274 EXCEPTIONS: AVX512-E1 33275 REAL_OPCODE: Y 33276 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33277 PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 33278 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 33279 IFORM: VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 33280 } 33281 33282 33283 # EMITTING VMOVAPD (VMOVAPD-256-2) 33284 { 33285 ICLASS: VMOVAPD 33286 CPL: 3 33287 CATEGORY: DATAXFER 33288 EXTENSION: AVX512EVEX 33289 ISA_SET: AVX512F_256 33290 EXCEPTIONS: AVX512-E1 33291 REAL_OPCODE: Y 33292 ATTRIBUTES: MASKOP_EVEX 33293 PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 33294 OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 33295 IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 33296 } 33297 33298 33299 # EMITTING VMOVAPD (VMOVAPD-256-3) 33300 { 33301 ICLASS: VMOVAPD 33302 CPL: 3 33303 CATEGORY: DATAXFER 33304 EXTENSION: AVX512EVEX 33305 ISA_SET: AVX512F_256 33306 EXCEPTIONS: AVX512-E1 33307 REAL_OPCODE: Y 33308 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33309 PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 33310 OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 33311 IFORM: VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 33312 } 33313 33314 33315 # EMITTING VMOVAPS (VMOVAPS-128-1) 33316 { 33317 ICLASS: VMOVAPS 33318 CPL: 3 33319 CATEGORY: DATAXFER 33320 EXTENSION: AVX512EVEX 33321 ISA_SET: AVX512F_128 33322 EXCEPTIONS: AVX512-E1 33323 REAL_OPCODE: Y 33324 ATTRIBUTES: MASKOP_EVEX 33325 PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 33326 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 33327 IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 33328 } 33329 33330 { 33331 ICLASS: VMOVAPS 33332 CPL: 3 33333 CATEGORY: DATAXFER 33334 EXTENSION: AVX512EVEX 33335 ISA_SET: AVX512F_128 33336 EXCEPTIONS: AVX512-E1 33337 REAL_OPCODE: Y 33338 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33339 PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 33340 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 33341 IFORM: VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 33342 } 33343 33344 33345 # EMITTING VMOVAPS (VMOVAPS-128-2) 33346 { 33347 ICLASS: VMOVAPS 33348 CPL: 3 33349 CATEGORY: DATAXFER 33350 EXTENSION: AVX512EVEX 33351 ISA_SET: AVX512F_128 33352 EXCEPTIONS: AVX512-E1 33353 REAL_OPCODE: Y 33354 ATTRIBUTES: MASKOP_EVEX 33355 PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 33356 OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 33357 IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 33358 } 33359 33360 33361 # EMITTING VMOVAPS (VMOVAPS-128-3) 33362 { 33363 ICLASS: VMOVAPS 33364 CPL: 3 33365 CATEGORY: DATAXFER 33366 EXTENSION: AVX512EVEX 33367 ISA_SET: AVX512F_128 33368 EXCEPTIONS: AVX512-E1 33369 REAL_OPCODE: Y 33370 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33371 PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 33372 OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 33373 IFORM: VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 33374 } 33375 33376 33377 # EMITTING VMOVAPS (VMOVAPS-256-1) 33378 { 33379 ICLASS: VMOVAPS 33380 CPL: 3 33381 CATEGORY: DATAXFER 33382 EXTENSION: AVX512EVEX 33383 ISA_SET: AVX512F_256 33384 EXCEPTIONS: AVX512-E1 33385 REAL_OPCODE: Y 33386 ATTRIBUTES: MASKOP_EVEX 33387 PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 33388 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 33389 IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 33390 } 33391 33392 { 33393 ICLASS: VMOVAPS 33394 CPL: 3 33395 CATEGORY: DATAXFER 33396 EXTENSION: AVX512EVEX 33397 ISA_SET: AVX512F_256 33398 EXCEPTIONS: AVX512-E1 33399 REAL_OPCODE: Y 33400 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33401 PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 33402 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 33403 IFORM: VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 33404 } 33405 33406 33407 # EMITTING VMOVAPS (VMOVAPS-256-2) 33408 { 33409 ICLASS: VMOVAPS 33410 CPL: 3 33411 CATEGORY: DATAXFER 33412 EXTENSION: AVX512EVEX 33413 ISA_SET: AVX512F_256 33414 EXCEPTIONS: AVX512-E1 33415 REAL_OPCODE: Y 33416 ATTRIBUTES: MASKOP_EVEX 33417 PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 33418 OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 33419 IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 33420 } 33421 33422 33423 # EMITTING VMOVAPS (VMOVAPS-256-3) 33424 { 33425 ICLASS: VMOVAPS 33426 CPL: 3 33427 CATEGORY: DATAXFER 33428 EXTENSION: AVX512EVEX 33429 ISA_SET: AVX512F_256 33430 EXCEPTIONS: AVX512-E1 33431 REAL_OPCODE: Y 33432 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33433 PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 33434 OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 33435 IFORM: VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 33436 } 33437 33438 33439 # EMITTING VMOVDDUP (VMOVDDUP-128-1) 33440 { 33441 ICLASS: VMOVDDUP 33442 CPL: 3 33443 CATEGORY: DATAXFER 33444 EXTENSION: AVX512EVEX 33445 ISA_SET: AVX512F_128 33446 EXCEPTIONS: AVX512-E5NF 33447 REAL_OPCODE: Y 33448 ATTRIBUTES: MASKOP_EVEX 33449 PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 33450 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 33451 IFORM: VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 33452 } 33453 33454 { 33455 ICLASS: VMOVDDUP 33456 CPL: 3 33457 CATEGORY: DATAXFER 33458 EXTENSION: AVX512EVEX 33459 ISA_SET: AVX512F_128 33460 EXCEPTIONS: AVX512-E5NF 33461 REAL_OPCODE: Y 33462 ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP 33463 PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() 33464 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 33465 IFORM: VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 33466 } 33467 33468 33469 # EMITTING VMOVDDUP (VMOVDDUP-256-1) 33470 { 33471 ICLASS: VMOVDDUP 33472 CPL: 3 33473 CATEGORY: DATAXFER 33474 EXTENSION: AVX512EVEX 33475 ISA_SET: AVX512F_256 33476 EXCEPTIONS: AVX512-E5NF 33477 REAL_OPCODE: Y 33478 ATTRIBUTES: MASKOP_EVEX 33479 PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 33480 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 33481 IFORM: VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 33482 } 33483 33484 { 33485 ICLASS: VMOVDDUP 33486 CPL: 3 33487 CATEGORY: DATAXFER 33488 EXTENSION: AVX512EVEX 33489 ISA_SET: AVX512F_256 33490 EXCEPTIONS: AVX512-E5NF 33491 REAL_OPCODE: Y 33492 ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP 33493 PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() 33494 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 33495 IFORM: VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 33496 } 33497 33498 33499 # EMITTING VMOVDQA32 (VMOVDQA32-128-1) 33500 { 33501 ICLASS: VMOVDQA32 33502 CPL: 3 33503 CATEGORY: DATAXFER 33504 EXTENSION: AVX512EVEX 33505 ISA_SET: AVX512F_128 33506 EXCEPTIONS: AVX512-E1 33507 REAL_OPCODE: Y 33508 ATTRIBUTES: MASKOP_EVEX 33509 PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 33510 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 33511 IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 33512 } 33513 33514 { 33515 ICLASS: VMOVDQA32 33516 CPL: 3 33517 CATEGORY: DATAXFER 33518 EXTENSION: AVX512EVEX 33519 ISA_SET: AVX512F_128 33520 EXCEPTIONS: AVX512-E1 33521 REAL_OPCODE: Y 33522 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33523 PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 33524 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 33525 IFORM: VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 33526 } 33527 33528 33529 # EMITTING VMOVDQA32 (VMOVDQA32-128-2) 33530 { 33531 ICLASS: VMOVDQA32 33532 CPL: 3 33533 CATEGORY: DATAXFER 33534 EXTENSION: AVX512EVEX 33535 ISA_SET: AVX512F_128 33536 EXCEPTIONS: AVX512-E1 33537 REAL_OPCODE: Y 33538 ATTRIBUTES: MASKOP_EVEX 33539 PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 33540 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 33541 IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 33542 } 33543 33544 33545 # EMITTING VMOVDQA32 (VMOVDQA32-128-3) 33546 { 33547 ICLASS: VMOVDQA32 33548 CPL: 3 33549 CATEGORY: DATAXFER 33550 EXTENSION: AVX512EVEX 33551 ISA_SET: AVX512F_128 33552 EXCEPTIONS: AVX512-E1 33553 REAL_OPCODE: Y 33554 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33555 PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 33556 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 33557 IFORM: VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 33558 } 33559 33560 33561 # EMITTING VMOVDQA32 (VMOVDQA32-256-1) 33562 { 33563 ICLASS: VMOVDQA32 33564 CPL: 3 33565 CATEGORY: DATAXFER 33566 EXTENSION: AVX512EVEX 33567 ISA_SET: AVX512F_256 33568 EXCEPTIONS: AVX512-E1 33569 REAL_OPCODE: Y 33570 ATTRIBUTES: MASKOP_EVEX 33571 PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 33572 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 33573 IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 33574 } 33575 33576 { 33577 ICLASS: VMOVDQA32 33578 CPL: 3 33579 CATEGORY: DATAXFER 33580 EXTENSION: AVX512EVEX 33581 ISA_SET: AVX512F_256 33582 EXCEPTIONS: AVX512-E1 33583 REAL_OPCODE: Y 33584 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33585 PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 33586 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 33587 IFORM: VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 33588 } 33589 33590 33591 # EMITTING VMOVDQA32 (VMOVDQA32-256-2) 33592 { 33593 ICLASS: VMOVDQA32 33594 CPL: 3 33595 CATEGORY: DATAXFER 33596 EXTENSION: AVX512EVEX 33597 ISA_SET: AVX512F_256 33598 EXCEPTIONS: AVX512-E1 33599 REAL_OPCODE: Y 33600 ATTRIBUTES: MASKOP_EVEX 33601 PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 33602 OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 33603 IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 33604 } 33605 33606 33607 # EMITTING VMOVDQA32 (VMOVDQA32-256-3) 33608 { 33609 ICLASS: VMOVDQA32 33610 CPL: 3 33611 CATEGORY: DATAXFER 33612 EXTENSION: AVX512EVEX 33613 ISA_SET: AVX512F_256 33614 EXCEPTIONS: AVX512-E1 33615 REAL_OPCODE: Y 33616 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33617 PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 33618 OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 33619 IFORM: VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 33620 } 33621 33622 33623 # EMITTING VMOVDQA64 (VMOVDQA64-128-1) 33624 { 33625 ICLASS: VMOVDQA64 33626 CPL: 3 33627 CATEGORY: DATAXFER 33628 EXTENSION: AVX512EVEX 33629 ISA_SET: AVX512F_128 33630 EXCEPTIONS: AVX512-E1 33631 REAL_OPCODE: Y 33632 ATTRIBUTES: MASKOP_EVEX 33633 PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 33634 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 33635 IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 33636 } 33637 33638 { 33639 ICLASS: VMOVDQA64 33640 CPL: 3 33641 CATEGORY: DATAXFER 33642 EXTENSION: AVX512EVEX 33643 ISA_SET: AVX512F_128 33644 EXCEPTIONS: AVX512-E1 33645 REAL_OPCODE: Y 33646 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33647 PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 33648 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 33649 IFORM: VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 33650 } 33651 33652 33653 # EMITTING VMOVDQA64 (VMOVDQA64-128-2) 33654 { 33655 ICLASS: VMOVDQA64 33656 CPL: 3 33657 CATEGORY: DATAXFER 33658 EXTENSION: AVX512EVEX 33659 ISA_SET: AVX512F_128 33660 EXCEPTIONS: AVX512-E1 33661 REAL_OPCODE: Y 33662 ATTRIBUTES: MASKOP_EVEX 33663 PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 33664 OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 33665 IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 33666 } 33667 33668 33669 # EMITTING VMOVDQA64 (VMOVDQA64-128-3) 33670 { 33671 ICLASS: VMOVDQA64 33672 CPL: 3 33673 CATEGORY: DATAXFER 33674 EXTENSION: AVX512EVEX 33675 ISA_SET: AVX512F_128 33676 EXCEPTIONS: AVX512-E1 33677 REAL_OPCODE: Y 33678 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33679 PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 33680 OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 33681 IFORM: VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 33682 } 33683 33684 33685 # EMITTING VMOVDQA64 (VMOVDQA64-256-1) 33686 { 33687 ICLASS: VMOVDQA64 33688 CPL: 3 33689 CATEGORY: DATAXFER 33690 EXTENSION: AVX512EVEX 33691 ISA_SET: AVX512F_256 33692 EXCEPTIONS: AVX512-E1 33693 REAL_OPCODE: Y 33694 ATTRIBUTES: MASKOP_EVEX 33695 PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 33696 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 33697 IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 33698 } 33699 33700 { 33701 ICLASS: VMOVDQA64 33702 CPL: 3 33703 CATEGORY: DATAXFER 33704 EXTENSION: AVX512EVEX 33705 ISA_SET: AVX512F_256 33706 EXCEPTIONS: AVX512-E1 33707 REAL_OPCODE: Y 33708 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33709 PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 33710 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 33711 IFORM: VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 33712 } 33713 33714 33715 # EMITTING VMOVDQA64 (VMOVDQA64-256-2) 33716 { 33717 ICLASS: VMOVDQA64 33718 CPL: 3 33719 CATEGORY: DATAXFER 33720 EXTENSION: AVX512EVEX 33721 ISA_SET: AVX512F_256 33722 EXCEPTIONS: AVX512-E1 33723 REAL_OPCODE: Y 33724 ATTRIBUTES: MASKOP_EVEX 33725 PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 33726 OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 33727 IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 33728 } 33729 33730 33731 # EMITTING VMOVDQA64 (VMOVDQA64-256-3) 33732 { 33733 ICLASS: VMOVDQA64 33734 CPL: 3 33735 CATEGORY: DATAXFER 33736 EXTENSION: AVX512EVEX 33737 ISA_SET: AVX512F_256 33738 EXCEPTIONS: AVX512-E1 33739 REAL_OPCODE: Y 33740 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM 33741 PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 33742 OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 33743 IFORM: VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 33744 } 33745 33746 33747 # EMITTING VMOVDQU16 (VMOVDQU16-128-1) 33748 { 33749 ICLASS: VMOVDQU16 33750 CPL: 3 33751 CATEGORY: DATAXFER 33752 EXTENSION: AVX512EVEX 33753 ISA_SET: AVX512BW_128 33754 EXCEPTIONS: AVX512-E4 33755 REAL_OPCODE: Y 33756 ATTRIBUTES: MASKOP_EVEX 33757 PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 33758 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 33759 IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 33760 } 33761 33762 { 33763 ICLASS: VMOVDQU16 33764 CPL: 3 33765 CATEGORY: DATAXFER 33766 EXTENSION: AVX512EVEX 33767 ISA_SET: AVX512BW_128 33768 EXCEPTIONS: AVX512-E4 33769 REAL_OPCODE: Y 33770 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 33771 PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 33772 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 33773 IFORM: VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 33774 } 33775 33776 33777 # EMITTING VMOVDQU16 (VMOVDQU16-128-2) 33778 { 33779 ICLASS: VMOVDQU16 33780 CPL: 3 33781 CATEGORY: DATAXFER 33782 EXTENSION: AVX512EVEX 33783 ISA_SET: AVX512BW_128 33784 EXCEPTIONS: AVX512-E4 33785 REAL_OPCODE: Y 33786 ATTRIBUTES: MASKOP_EVEX 33787 PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 33788 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 33789 IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 33790 } 33791 33792 33793 # EMITTING VMOVDQU16 (VMOVDQU16-128-3) 33794 { 33795 ICLASS: VMOVDQU16 33796 CPL: 3 33797 CATEGORY: DATAXFER 33798 EXTENSION: AVX512EVEX 33799 ISA_SET: AVX512BW_128 33800 EXCEPTIONS: AVX512-E4 33801 REAL_OPCODE: Y 33802 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 33803 PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 33804 OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 33805 IFORM: VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 33806 } 33807 33808 33809 # EMITTING VMOVDQU16 (VMOVDQU16-256-1) 33810 { 33811 ICLASS: VMOVDQU16 33812 CPL: 3 33813 CATEGORY: DATAXFER 33814 EXTENSION: AVX512EVEX 33815 ISA_SET: AVX512BW_256 33816 EXCEPTIONS: AVX512-E4 33817 REAL_OPCODE: Y 33818 ATTRIBUTES: MASKOP_EVEX 33819 PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 33820 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 33821 IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 33822 } 33823 33824 { 33825 ICLASS: VMOVDQU16 33826 CPL: 3 33827 CATEGORY: DATAXFER 33828 EXTENSION: AVX512EVEX 33829 ISA_SET: AVX512BW_256 33830 EXCEPTIONS: AVX512-E4 33831 REAL_OPCODE: Y 33832 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 33833 PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 33834 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 33835 IFORM: VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 33836 } 33837 33838 33839 # EMITTING VMOVDQU16 (VMOVDQU16-256-2) 33840 { 33841 ICLASS: VMOVDQU16 33842 CPL: 3 33843 CATEGORY: DATAXFER 33844 EXTENSION: AVX512EVEX 33845 ISA_SET: AVX512BW_256 33846 EXCEPTIONS: AVX512-E4 33847 REAL_OPCODE: Y 33848 ATTRIBUTES: MASKOP_EVEX 33849 PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 33850 OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 33851 IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 33852 } 33853 33854 33855 # EMITTING VMOVDQU16 (VMOVDQU16-256-3) 33856 { 33857 ICLASS: VMOVDQU16 33858 CPL: 3 33859 CATEGORY: DATAXFER 33860 EXTENSION: AVX512EVEX 33861 ISA_SET: AVX512BW_256 33862 EXCEPTIONS: AVX512-E4 33863 REAL_OPCODE: Y 33864 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 33865 PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 33866 OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 33867 IFORM: VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 33868 } 33869 33870 33871 # EMITTING VMOVDQU16 (VMOVDQU16-512-1) 33872 { 33873 ICLASS: VMOVDQU16 33874 CPL: 3 33875 CATEGORY: DATAXFER 33876 EXTENSION: AVX512EVEX 33877 ISA_SET: AVX512BW_512 33878 EXCEPTIONS: AVX512-E4 33879 REAL_OPCODE: Y 33880 ATTRIBUTES: MASKOP_EVEX 33881 PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 33882 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 33883 IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 33884 } 33885 33886 { 33887 ICLASS: VMOVDQU16 33888 CPL: 3 33889 CATEGORY: DATAXFER 33890 EXTENSION: AVX512EVEX 33891 ISA_SET: AVX512BW_512 33892 EXCEPTIONS: AVX512-E4 33893 REAL_OPCODE: Y 33894 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 33895 PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 33896 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 33897 IFORM: VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 33898 } 33899 33900 33901 # EMITTING VMOVDQU16 (VMOVDQU16-512-2) 33902 { 33903 ICLASS: VMOVDQU16 33904 CPL: 3 33905 CATEGORY: DATAXFER 33906 EXTENSION: AVX512EVEX 33907 ISA_SET: AVX512BW_512 33908 EXCEPTIONS: AVX512-E4 33909 REAL_OPCODE: Y 33910 ATTRIBUTES: MASKOP_EVEX 33911 PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 33912 OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 33913 IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 33914 } 33915 33916 33917 # EMITTING VMOVDQU16 (VMOVDQU16-512-3) 33918 { 33919 ICLASS: VMOVDQU16 33920 CPL: 3 33921 CATEGORY: DATAXFER 33922 EXTENSION: AVX512EVEX 33923 ISA_SET: AVX512BW_512 33924 EXCEPTIONS: AVX512-E4 33925 REAL_OPCODE: Y 33926 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 33927 PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 33928 OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 33929 IFORM: VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 33930 } 33931 33932 33933 # EMITTING VMOVDQU32 (VMOVDQU32-128-1) 33934 { 33935 ICLASS: VMOVDQU32 33936 CPL: 3 33937 CATEGORY: DATAXFER 33938 EXTENSION: AVX512EVEX 33939 ISA_SET: AVX512F_128 33940 EXCEPTIONS: AVX512-E4 33941 REAL_OPCODE: Y 33942 ATTRIBUTES: MASKOP_EVEX 33943 PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 33944 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 33945 IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 33946 } 33947 33948 { 33949 ICLASS: VMOVDQU32 33950 CPL: 3 33951 CATEGORY: DATAXFER 33952 EXTENSION: AVX512EVEX 33953 ISA_SET: AVX512F_128 33954 EXCEPTIONS: AVX512-E4 33955 REAL_OPCODE: Y 33956 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 33957 PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 33958 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 33959 IFORM: VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 33960 } 33961 33962 33963 # EMITTING VMOVDQU32 (VMOVDQU32-128-2) 33964 { 33965 ICLASS: VMOVDQU32 33966 CPL: 3 33967 CATEGORY: DATAXFER 33968 EXTENSION: AVX512EVEX 33969 ISA_SET: AVX512F_128 33970 EXCEPTIONS: AVX512-E4 33971 REAL_OPCODE: Y 33972 ATTRIBUTES: MASKOP_EVEX 33973 PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 33974 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 33975 IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 33976 } 33977 33978 33979 # EMITTING VMOVDQU32 (VMOVDQU32-128-3) 33980 { 33981 ICLASS: VMOVDQU32 33982 CPL: 3 33983 CATEGORY: DATAXFER 33984 EXTENSION: AVX512EVEX 33985 ISA_SET: AVX512F_128 33986 EXCEPTIONS: AVX512-E4 33987 REAL_OPCODE: Y 33988 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 33989 PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 33990 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 33991 IFORM: VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 33992 } 33993 33994 33995 # EMITTING VMOVDQU32 (VMOVDQU32-256-1) 33996 { 33997 ICLASS: VMOVDQU32 33998 CPL: 3 33999 CATEGORY: DATAXFER 34000 EXTENSION: AVX512EVEX 34001 ISA_SET: AVX512F_256 34002 EXCEPTIONS: AVX512-E4 34003 REAL_OPCODE: Y 34004 ATTRIBUTES: MASKOP_EVEX 34005 PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 34006 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 34007 IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 34008 } 34009 34010 { 34011 ICLASS: VMOVDQU32 34012 CPL: 3 34013 CATEGORY: DATAXFER 34014 EXTENSION: AVX512EVEX 34015 ISA_SET: AVX512F_256 34016 EXCEPTIONS: AVX512-E4 34017 REAL_OPCODE: Y 34018 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34019 PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 34020 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 34021 IFORM: VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 34022 } 34023 34024 34025 # EMITTING VMOVDQU32 (VMOVDQU32-256-2) 34026 { 34027 ICLASS: VMOVDQU32 34028 CPL: 3 34029 CATEGORY: DATAXFER 34030 EXTENSION: AVX512EVEX 34031 ISA_SET: AVX512F_256 34032 EXCEPTIONS: AVX512-E4 34033 REAL_OPCODE: Y 34034 ATTRIBUTES: MASKOP_EVEX 34035 PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 34036 OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 34037 IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 34038 } 34039 34040 34041 # EMITTING VMOVDQU32 (VMOVDQU32-256-3) 34042 { 34043 ICLASS: VMOVDQU32 34044 CPL: 3 34045 CATEGORY: DATAXFER 34046 EXTENSION: AVX512EVEX 34047 ISA_SET: AVX512F_256 34048 EXCEPTIONS: AVX512-E4 34049 REAL_OPCODE: Y 34050 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34051 PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 34052 OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 34053 IFORM: VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 34054 } 34055 34056 34057 # EMITTING VMOVDQU64 (VMOVDQU64-128-1) 34058 { 34059 ICLASS: VMOVDQU64 34060 CPL: 3 34061 CATEGORY: DATAXFER 34062 EXTENSION: AVX512EVEX 34063 ISA_SET: AVX512F_128 34064 EXCEPTIONS: AVX512-E4 34065 REAL_OPCODE: Y 34066 ATTRIBUTES: MASKOP_EVEX 34067 PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 34068 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 34069 IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 34070 } 34071 34072 { 34073 ICLASS: VMOVDQU64 34074 CPL: 3 34075 CATEGORY: DATAXFER 34076 EXTENSION: AVX512EVEX 34077 ISA_SET: AVX512F_128 34078 EXCEPTIONS: AVX512-E4 34079 REAL_OPCODE: Y 34080 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34081 PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 34082 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 34083 IFORM: VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 34084 } 34085 34086 34087 # EMITTING VMOVDQU64 (VMOVDQU64-128-2) 34088 { 34089 ICLASS: VMOVDQU64 34090 CPL: 3 34091 CATEGORY: DATAXFER 34092 EXTENSION: AVX512EVEX 34093 ISA_SET: AVX512F_128 34094 EXCEPTIONS: AVX512-E4 34095 REAL_OPCODE: Y 34096 ATTRIBUTES: MASKOP_EVEX 34097 PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 34098 OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 34099 IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 34100 } 34101 34102 34103 # EMITTING VMOVDQU64 (VMOVDQU64-128-3) 34104 { 34105 ICLASS: VMOVDQU64 34106 CPL: 3 34107 CATEGORY: DATAXFER 34108 EXTENSION: AVX512EVEX 34109 ISA_SET: AVX512F_128 34110 EXCEPTIONS: AVX512-E4 34111 REAL_OPCODE: Y 34112 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34113 PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 34114 OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 34115 IFORM: VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 34116 } 34117 34118 34119 # EMITTING VMOVDQU64 (VMOVDQU64-256-1) 34120 { 34121 ICLASS: VMOVDQU64 34122 CPL: 3 34123 CATEGORY: DATAXFER 34124 EXTENSION: AVX512EVEX 34125 ISA_SET: AVX512F_256 34126 EXCEPTIONS: AVX512-E4 34127 REAL_OPCODE: Y 34128 ATTRIBUTES: MASKOP_EVEX 34129 PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 34130 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 34131 IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 34132 } 34133 34134 { 34135 ICLASS: VMOVDQU64 34136 CPL: 3 34137 CATEGORY: DATAXFER 34138 EXTENSION: AVX512EVEX 34139 ISA_SET: AVX512F_256 34140 EXCEPTIONS: AVX512-E4 34141 REAL_OPCODE: Y 34142 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34143 PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 34144 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 34145 IFORM: VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 34146 } 34147 34148 34149 # EMITTING VMOVDQU64 (VMOVDQU64-256-2) 34150 { 34151 ICLASS: VMOVDQU64 34152 CPL: 3 34153 CATEGORY: DATAXFER 34154 EXTENSION: AVX512EVEX 34155 ISA_SET: AVX512F_256 34156 EXCEPTIONS: AVX512-E4 34157 REAL_OPCODE: Y 34158 ATTRIBUTES: MASKOP_EVEX 34159 PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 34160 OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 34161 IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 34162 } 34163 34164 34165 # EMITTING VMOVDQU64 (VMOVDQU64-256-3) 34166 { 34167 ICLASS: VMOVDQU64 34168 CPL: 3 34169 CATEGORY: DATAXFER 34170 EXTENSION: AVX512EVEX 34171 ISA_SET: AVX512F_256 34172 EXCEPTIONS: AVX512-E4 34173 REAL_OPCODE: Y 34174 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34175 PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 34176 OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 34177 IFORM: VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 34178 } 34179 34180 34181 # EMITTING VMOVDQU8 (VMOVDQU8-128-1) 34182 { 34183 ICLASS: VMOVDQU8 34184 CPL: 3 34185 CATEGORY: DATAXFER 34186 EXTENSION: AVX512EVEX 34187 ISA_SET: AVX512BW_128 34188 EXCEPTIONS: AVX512-E4 34189 REAL_OPCODE: Y 34190 ATTRIBUTES: MASKOP_EVEX 34191 PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 34192 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 34193 IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 34194 } 34195 34196 { 34197 ICLASS: VMOVDQU8 34198 CPL: 3 34199 CATEGORY: DATAXFER 34200 EXTENSION: AVX512EVEX 34201 ISA_SET: AVX512BW_128 34202 EXCEPTIONS: AVX512-E4 34203 REAL_OPCODE: Y 34204 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34205 PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 34206 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 34207 IFORM: VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 34208 } 34209 34210 34211 # EMITTING VMOVDQU8 (VMOVDQU8-128-2) 34212 { 34213 ICLASS: VMOVDQU8 34214 CPL: 3 34215 CATEGORY: DATAXFER 34216 EXTENSION: AVX512EVEX 34217 ISA_SET: AVX512BW_128 34218 EXCEPTIONS: AVX512-E4 34219 REAL_OPCODE: Y 34220 ATTRIBUTES: MASKOP_EVEX 34221 PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 34222 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8 34223 IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 34224 } 34225 34226 34227 # EMITTING VMOVDQU8 (VMOVDQU8-128-3) 34228 { 34229 ICLASS: VMOVDQU8 34230 CPL: 3 34231 CATEGORY: DATAXFER 34232 EXTENSION: AVX512EVEX 34233 ISA_SET: AVX512BW_128 34234 EXCEPTIONS: AVX512-E4 34235 REAL_OPCODE: Y 34236 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34237 PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 34238 OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8 34239 IFORM: VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 34240 } 34241 34242 34243 # EMITTING VMOVDQU8 (VMOVDQU8-256-1) 34244 { 34245 ICLASS: VMOVDQU8 34246 CPL: 3 34247 CATEGORY: DATAXFER 34248 EXTENSION: AVX512EVEX 34249 ISA_SET: AVX512BW_256 34250 EXCEPTIONS: AVX512-E4 34251 REAL_OPCODE: Y 34252 ATTRIBUTES: MASKOP_EVEX 34253 PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 34254 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 34255 IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 34256 } 34257 34258 { 34259 ICLASS: VMOVDQU8 34260 CPL: 3 34261 CATEGORY: DATAXFER 34262 EXTENSION: AVX512EVEX 34263 ISA_SET: AVX512BW_256 34264 EXCEPTIONS: AVX512-E4 34265 REAL_OPCODE: Y 34266 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34267 PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 34268 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 34269 IFORM: VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 34270 } 34271 34272 34273 # EMITTING VMOVDQU8 (VMOVDQU8-256-2) 34274 { 34275 ICLASS: VMOVDQU8 34276 CPL: 3 34277 CATEGORY: DATAXFER 34278 EXTENSION: AVX512EVEX 34279 ISA_SET: AVX512BW_256 34280 EXCEPTIONS: AVX512-E4 34281 REAL_OPCODE: Y 34282 ATTRIBUTES: MASKOP_EVEX 34283 PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 34284 OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8 34285 IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 34286 } 34287 34288 34289 # EMITTING VMOVDQU8 (VMOVDQU8-256-3) 34290 { 34291 ICLASS: VMOVDQU8 34292 CPL: 3 34293 CATEGORY: DATAXFER 34294 EXTENSION: AVX512EVEX 34295 ISA_SET: AVX512BW_256 34296 EXCEPTIONS: AVX512-E4 34297 REAL_OPCODE: Y 34298 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34299 PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 34300 OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8 34301 IFORM: VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 34302 } 34303 34304 34305 # EMITTING VMOVDQU8 (VMOVDQU8-512-1) 34306 { 34307 ICLASS: VMOVDQU8 34308 CPL: 3 34309 CATEGORY: DATAXFER 34310 EXTENSION: AVX512EVEX 34311 ISA_SET: AVX512BW_512 34312 EXCEPTIONS: AVX512-E4 34313 REAL_OPCODE: Y 34314 ATTRIBUTES: MASKOP_EVEX 34315 PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 34316 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 34317 IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 34318 } 34319 34320 { 34321 ICLASS: VMOVDQU8 34322 CPL: 3 34323 CATEGORY: DATAXFER 34324 EXTENSION: AVX512EVEX 34325 ISA_SET: AVX512BW_512 34326 EXCEPTIONS: AVX512-E4 34327 REAL_OPCODE: Y 34328 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34329 PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 34330 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 34331 IFORM: VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 34332 } 34333 34334 34335 # EMITTING VMOVDQU8 (VMOVDQU8-512-2) 34336 { 34337 ICLASS: VMOVDQU8 34338 CPL: 3 34339 CATEGORY: DATAXFER 34340 EXTENSION: AVX512EVEX 34341 ISA_SET: AVX512BW_512 34342 EXCEPTIONS: AVX512-E4 34343 REAL_OPCODE: Y 34344 ATTRIBUTES: MASKOP_EVEX 34345 PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 34346 OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8 34347 IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 34348 } 34349 34350 34351 # EMITTING VMOVDQU8 (VMOVDQU8-512-3) 34352 { 34353 ICLASS: VMOVDQU8 34354 CPL: 3 34355 CATEGORY: DATAXFER 34356 EXTENSION: AVX512EVEX 34357 ISA_SET: AVX512BW_512 34358 EXCEPTIONS: AVX512-E4 34359 REAL_OPCODE: Y 34360 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34361 PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 34362 OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8 34363 IFORM: VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 34364 } 34365 34366 34367 # EMITTING VMOVNTDQ (VMOVNTDQ-128-1) 34368 { 34369 ICLASS: VMOVNTDQ 34370 CPL: 3 34371 CATEGORY: DATAXFER 34372 EXTENSION: AVX512EVEX 34373 ISA_SET: AVX512F_128 34374 EXCEPTIONS: AVX512-E1NF 34375 REAL_OPCODE: Y 34376 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 34377 PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 34378 OPERANDS: MEM0:w:dq:u32 REG0=XMM_R3():r:dq:u32 34379 IFORM: VMOVNTDQ_MEMu32_XMMu32_AVX512 34380 } 34381 34382 34383 # EMITTING VMOVNTDQ (VMOVNTDQ-256-1) 34384 { 34385 ICLASS: VMOVNTDQ 34386 CPL: 3 34387 CATEGORY: DATAXFER 34388 EXTENSION: AVX512EVEX 34389 ISA_SET: AVX512F_256 34390 EXCEPTIONS: AVX512-E1NF 34391 REAL_OPCODE: Y 34392 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 34393 PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 34394 OPERANDS: MEM0:w:qq:u32 REG0=YMM_R3():r:qq:u32 34395 IFORM: VMOVNTDQ_MEMu32_YMMu32_AVX512 34396 } 34397 34398 34399 # EMITTING VMOVNTDQA (VMOVNTDQA-128-1) 34400 { 34401 ICLASS: VMOVNTDQA 34402 CPL: 3 34403 CATEGORY: DATAXFER 34404 EXTENSION: AVX512EVEX 34405 ISA_SET: AVX512F_128 34406 EXCEPTIONS: AVX512-E1NF 34407 REAL_OPCODE: Y 34408 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 34409 PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 34410 OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:dq:u32 34411 IFORM: VMOVNTDQA_XMMu32_MEMu32_AVX512 34412 } 34413 34414 34415 # EMITTING VMOVNTDQA (VMOVNTDQA-256-1) 34416 { 34417 ICLASS: VMOVNTDQA 34418 CPL: 3 34419 CATEGORY: DATAXFER 34420 EXTENSION: AVX512EVEX 34421 ISA_SET: AVX512F_256 34422 EXCEPTIONS: AVX512-E1NF 34423 REAL_OPCODE: Y 34424 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 34425 PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 34426 OPERANDS: REG0=YMM_R3():w:qq:u32 MEM0:r:qq:u32 34427 IFORM: VMOVNTDQA_YMMu32_MEMu32_AVX512 34428 } 34429 34430 34431 # EMITTING VMOVNTPD (VMOVNTPD-128-1) 34432 { 34433 ICLASS: VMOVNTPD 34434 CPL: 3 34435 CATEGORY: DATAXFER 34436 EXTENSION: AVX512EVEX 34437 ISA_SET: AVX512F_128 34438 EXCEPTIONS: AVX512-E1NF 34439 REAL_OPCODE: Y 34440 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 34441 PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() 34442 OPERANDS: MEM0:w:dq:f64 REG0=XMM_R3():r:dq:f64 34443 IFORM: VMOVNTPD_MEMf64_XMMf64_AVX512 34444 } 34445 34446 34447 # EMITTING VMOVNTPD (VMOVNTPD-256-1) 34448 { 34449 ICLASS: VMOVNTPD 34450 CPL: 3 34451 CATEGORY: DATAXFER 34452 EXTENSION: AVX512EVEX 34453 ISA_SET: AVX512F_256 34454 EXCEPTIONS: AVX512-E1NF 34455 REAL_OPCODE: Y 34456 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 34457 PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() 34458 OPERANDS: MEM0:w:qq:f64 REG0=YMM_R3():r:qq:f64 34459 IFORM: VMOVNTPD_MEMf64_YMMf64_AVX512 34460 } 34461 34462 34463 # EMITTING VMOVNTPS (VMOVNTPS-128-1) 34464 { 34465 ICLASS: VMOVNTPS 34466 CPL: 3 34467 CATEGORY: DATAXFER 34468 EXTENSION: AVX512EVEX 34469 ISA_SET: AVX512F_128 34470 EXCEPTIONS: AVX512-E1NF 34471 REAL_OPCODE: Y 34472 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 34473 PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 34474 OPERANDS: MEM0:w:dq:f32 REG0=XMM_R3():r:dq:f32 34475 IFORM: VMOVNTPS_MEMf32_XMMf32_AVX512 34476 } 34477 34478 34479 # EMITTING VMOVNTPS (VMOVNTPS-256-1) 34480 { 34481 ICLASS: VMOVNTPS 34482 CPL: 3 34483 CATEGORY: DATAXFER 34484 EXTENSION: AVX512EVEX 34485 ISA_SET: AVX512F_256 34486 EXCEPTIONS: AVX512-E1NF 34487 REAL_OPCODE: Y 34488 ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM 34489 PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() 34490 OPERANDS: MEM0:w:qq:f32 REG0=YMM_R3():r:qq:f32 34491 IFORM: VMOVNTPS_MEMf32_YMMf32_AVX512 34492 } 34493 34494 34495 # EMITTING VMOVSHDUP (VMOVSHDUP-128-1) 34496 { 34497 ICLASS: VMOVSHDUP 34498 CPL: 3 34499 CATEGORY: DATAXFER 34500 EXTENSION: AVX512EVEX 34501 ISA_SET: AVX512F_128 34502 EXCEPTIONS: AVX512-E4NF 34503 REAL_OPCODE: Y 34504 ATTRIBUTES: MASKOP_EVEX 34505 PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 34506 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 34507 IFORM: VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 34508 } 34509 34510 { 34511 ICLASS: VMOVSHDUP 34512 CPL: 3 34513 CATEGORY: DATAXFER 34514 EXTENSION: AVX512EVEX 34515 ISA_SET: AVX512F_128 34516 EXCEPTIONS: AVX512-E4NF 34517 REAL_OPCODE: Y 34518 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 34519 PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 34520 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 34521 IFORM: VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 34522 } 34523 34524 34525 # EMITTING VMOVSHDUP (VMOVSHDUP-256-1) 34526 { 34527 ICLASS: VMOVSHDUP 34528 CPL: 3 34529 CATEGORY: DATAXFER 34530 EXTENSION: AVX512EVEX 34531 ISA_SET: AVX512F_256 34532 EXCEPTIONS: AVX512-E4NF 34533 REAL_OPCODE: Y 34534 ATTRIBUTES: MASKOP_EVEX 34535 PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 34536 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 34537 IFORM: VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 34538 } 34539 34540 { 34541 ICLASS: VMOVSHDUP 34542 CPL: 3 34543 CATEGORY: DATAXFER 34544 EXTENSION: AVX512EVEX 34545 ISA_SET: AVX512F_256 34546 EXCEPTIONS: AVX512-E4NF 34547 REAL_OPCODE: Y 34548 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 34549 PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 34550 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 34551 IFORM: VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 34552 } 34553 34554 34555 # EMITTING VMOVSLDUP (VMOVSLDUP-128-1) 34556 { 34557 ICLASS: VMOVSLDUP 34558 CPL: 3 34559 CATEGORY: DATAXFER 34560 EXTENSION: AVX512EVEX 34561 ISA_SET: AVX512F_128 34562 EXCEPTIONS: AVX512-E4NF 34563 REAL_OPCODE: Y 34564 ATTRIBUTES: MASKOP_EVEX 34565 PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 34566 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 34567 IFORM: VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 34568 } 34569 34570 { 34571 ICLASS: VMOVSLDUP 34572 CPL: 3 34573 CATEGORY: DATAXFER 34574 EXTENSION: AVX512EVEX 34575 ISA_SET: AVX512F_128 34576 EXCEPTIONS: AVX512-E4NF 34577 REAL_OPCODE: Y 34578 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 34579 PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 34580 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 34581 IFORM: VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 34582 } 34583 34584 34585 # EMITTING VMOVSLDUP (VMOVSLDUP-256-1) 34586 { 34587 ICLASS: VMOVSLDUP 34588 CPL: 3 34589 CATEGORY: DATAXFER 34590 EXTENSION: AVX512EVEX 34591 ISA_SET: AVX512F_256 34592 EXCEPTIONS: AVX512-E4NF 34593 REAL_OPCODE: Y 34594 ATTRIBUTES: MASKOP_EVEX 34595 PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 34596 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 34597 IFORM: VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 34598 } 34599 34600 { 34601 ICLASS: VMOVSLDUP 34602 CPL: 3 34603 CATEGORY: DATAXFER 34604 EXTENSION: AVX512EVEX 34605 ISA_SET: AVX512F_256 34606 EXCEPTIONS: AVX512-E4NF 34607 REAL_OPCODE: Y 34608 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 34609 PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 34610 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 34611 IFORM: VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 34612 } 34613 34614 34615 # EMITTING VMOVUPD (VMOVUPD-128-1) 34616 { 34617 ICLASS: VMOVUPD 34618 CPL: 3 34619 CATEGORY: DATAXFER 34620 EXTENSION: AVX512EVEX 34621 ISA_SET: AVX512F_128 34622 EXCEPTIONS: AVX512-E4 34623 REAL_OPCODE: Y 34624 ATTRIBUTES: MASKOP_EVEX 34625 PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 34626 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 34627 IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 34628 } 34629 34630 { 34631 ICLASS: VMOVUPD 34632 CPL: 3 34633 CATEGORY: DATAXFER 34634 EXTENSION: AVX512EVEX 34635 ISA_SET: AVX512F_128 34636 EXCEPTIONS: AVX512-E4 34637 REAL_OPCODE: Y 34638 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34639 PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 34640 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 34641 IFORM: VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 34642 } 34643 34644 34645 # EMITTING VMOVUPD (VMOVUPD-128-2) 34646 { 34647 ICLASS: VMOVUPD 34648 CPL: 3 34649 CATEGORY: DATAXFER 34650 EXTENSION: AVX512EVEX 34651 ISA_SET: AVX512F_128 34652 EXCEPTIONS: AVX512-E4 34653 REAL_OPCODE: Y 34654 ATTRIBUTES: MASKOP_EVEX 34655 PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 34656 OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 34657 IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 34658 } 34659 34660 34661 # EMITTING VMOVUPD (VMOVUPD-128-3) 34662 { 34663 ICLASS: VMOVUPD 34664 CPL: 3 34665 CATEGORY: DATAXFER 34666 EXTENSION: AVX512EVEX 34667 ISA_SET: AVX512F_128 34668 EXCEPTIONS: AVX512-E4 34669 REAL_OPCODE: Y 34670 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34671 PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 34672 OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 34673 IFORM: VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 34674 } 34675 34676 34677 # EMITTING VMOVUPD (VMOVUPD-256-1) 34678 { 34679 ICLASS: VMOVUPD 34680 CPL: 3 34681 CATEGORY: DATAXFER 34682 EXTENSION: AVX512EVEX 34683 ISA_SET: AVX512F_256 34684 EXCEPTIONS: AVX512-E4 34685 REAL_OPCODE: Y 34686 ATTRIBUTES: MASKOP_EVEX 34687 PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 34688 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 34689 IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 34690 } 34691 34692 { 34693 ICLASS: VMOVUPD 34694 CPL: 3 34695 CATEGORY: DATAXFER 34696 EXTENSION: AVX512EVEX 34697 ISA_SET: AVX512F_256 34698 EXCEPTIONS: AVX512-E4 34699 REAL_OPCODE: Y 34700 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34701 PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() 34702 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 34703 IFORM: VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 34704 } 34705 34706 34707 # EMITTING VMOVUPD (VMOVUPD-256-2) 34708 { 34709 ICLASS: VMOVUPD 34710 CPL: 3 34711 CATEGORY: DATAXFER 34712 EXTENSION: AVX512EVEX 34713 ISA_SET: AVX512F_256 34714 EXCEPTIONS: AVX512-E4 34715 REAL_OPCODE: Y 34716 ATTRIBUTES: MASKOP_EVEX 34717 PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 34718 OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 34719 IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 34720 } 34721 34722 34723 # EMITTING VMOVUPD (VMOVUPD-256-3) 34724 { 34725 ICLASS: VMOVUPD 34726 CPL: 3 34727 CATEGORY: DATAXFER 34728 EXTENSION: AVX512EVEX 34729 ISA_SET: AVX512F_256 34730 EXCEPTIONS: AVX512-E4 34731 REAL_OPCODE: Y 34732 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34733 PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() 34734 OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 34735 IFORM: VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 34736 } 34737 34738 34739 # EMITTING VMOVUPS (VMOVUPS-128-1) 34740 { 34741 ICLASS: VMOVUPS 34742 CPL: 3 34743 CATEGORY: DATAXFER 34744 EXTENSION: AVX512EVEX 34745 ISA_SET: AVX512F_128 34746 EXCEPTIONS: AVX512-E4 34747 REAL_OPCODE: Y 34748 ATTRIBUTES: MASKOP_EVEX 34749 PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 34750 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 34751 IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 34752 } 34753 34754 { 34755 ICLASS: VMOVUPS 34756 CPL: 3 34757 CATEGORY: DATAXFER 34758 EXTENSION: AVX512EVEX 34759 ISA_SET: AVX512F_128 34760 EXCEPTIONS: AVX512-E4 34761 REAL_OPCODE: Y 34762 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34763 PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 34764 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 34765 IFORM: VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 34766 } 34767 34768 34769 # EMITTING VMOVUPS (VMOVUPS-128-2) 34770 { 34771 ICLASS: VMOVUPS 34772 CPL: 3 34773 CATEGORY: DATAXFER 34774 EXTENSION: AVX512EVEX 34775 ISA_SET: AVX512F_128 34776 EXCEPTIONS: AVX512-E4 34777 REAL_OPCODE: Y 34778 ATTRIBUTES: MASKOP_EVEX 34779 PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 34780 OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 34781 IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 34782 } 34783 34784 34785 # EMITTING VMOVUPS (VMOVUPS-128-3) 34786 { 34787 ICLASS: VMOVUPS 34788 CPL: 3 34789 CATEGORY: DATAXFER 34790 EXTENSION: AVX512EVEX 34791 ISA_SET: AVX512F_128 34792 EXCEPTIONS: AVX512-E4 34793 REAL_OPCODE: Y 34794 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34795 PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 34796 OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 34797 IFORM: VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 34798 } 34799 34800 34801 # EMITTING VMOVUPS (VMOVUPS-256-1) 34802 { 34803 ICLASS: VMOVUPS 34804 CPL: 3 34805 CATEGORY: DATAXFER 34806 EXTENSION: AVX512EVEX 34807 ISA_SET: AVX512F_256 34808 EXCEPTIONS: AVX512-E4 34809 REAL_OPCODE: Y 34810 ATTRIBUTES: MASKOP_EVEX 34811 PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 34812 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 34813 IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 34814 } 34815 34816 { 34817 ICLASS: VMOVUPS 34818 CPL: 3 34819 CATEGORY: DATAXFER 34820 EXTENSION: AVX512EVEX 34821 ISA_SET: AVX512F_256 34822 EXCEPTIONS: AVX512-E4 34823 REAL_OPCODE: Y 34824 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34825 PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() 34826 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 34827 IFORM: VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 34828 } 34829 34830 34831 # EMITTING VMOVUPS (VMOVUPS-256-2) 34832 { 34833 ICLASS: VMOVUPS 34834 CPL: 3 34835 CATEGORY: DATAXFER 34836 EXTENSION: AVX512EVEX 34837 ISA_SET: AVX512F_256 34838 EXCEPTIONS: AVX512-E4 34839 REAL_OPCODE: Y 34840 ATTRIBUTES: MASKOP_EVEX 34841 PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 34842 OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 34843 IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 34844 } 34845 34846 34847 # EMITTING VMOVUPS (VMOVUPS-256-3) 34848 { 34849 ICLASS: VMOVUPS 34850 CPL: 3 34851 CATEGORY: DATAXFER 34852 EXTENSION: AVX512EVEX 34853 ISA_SET: AVX512F_256 34854 EXCEPTIONS: AVX512-E4 34855 REAL_OPCODE: Y 34856 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 34857 PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() 34858 OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 34859 IFORM: VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 34860 } 34861 34862 34863 # EMITTING VMULPD (VMULPD-128-1) 34864 { 34865 ICLASS: VMULPD 34866 CPL: 3 34867 CATEGORY: AVX512 34868 EXTENSION: AVX512EVEX 34869 ISA_SET: AVX512F_128 34870 EXCEPTIONS: AVX512-E2 34871 REAL_OPCODE: Y 34872 ATTRIBUTES: MASKOP_EVEX MXCSR 34873 PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 34874 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 34875 IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 34876 } 34877 34878 { 34879 ICLASS: VMULPD 34880 CPL: 3 34881 CATEGORY: AVX512 34882 EXTENSION: AVX512EVEX 34883 ISA_SET: AVX512F_128 34884 EXCEPTIONS: AVX512-E2 34885 REAL_OPCODE: Y 34886 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 34887 PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 34888 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 34889 IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 34890 } 34891 34892 34893 # EMITTING VMULPD (VMULPD-256-1) 34894 { 34895 ICLASS: VMULPD 34896 CPL: 3 34897 CATEGORY: AVX512 34898 EXTENSION: AVX512EVEX 34899 ISA_SET: AVX512F_256 34900 EXCEPTIONS: AVX512-E2 34901 REAL_OPCODE: Y 34902 ATTRIBUTES: MASKOP_EVEX MXCSR 34903 PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 34904 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 34905 IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 34906 } 34907 34908 { 34909 ICLASS: VMULPD 34910 CPL: 3 34911 CATEGORY: AVX512 34912 EXTENSION: AVX512EVEX 34913 ISA_SET: AVX512F_256 34914 EXCEPTIONS: AVX512-E2 34915 REAL_OPCODE: Y 34916 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 34917 PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 34918 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 34919 IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 34920 } 34921 34922 34923 # EMITTING VMULPS (VMULPS-128-1) 34924 { 34925 ICLASS: VMULPS 34926 CPL: 3 34927 CATEGORY: AVX512 34928 EXTENSION: AVX512EVEX 34929 ISA_SET: AVX512F_128 34930 EXCEPTIONS: AVX512-E2 34931 REAL_OPCODE: Y 34932 ATTRIBUTES: MASKOP_EVEX MXCSR 34933 PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 34934 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 34935 IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 34936 } 34937 34938 { 34939 ICLASS: VMULPS 34940 CPL: 3 34941 CATEGORY: AVX512 34942 EXTENSION: AVX512EVEX 34943 ISA_SET: AVX512F_128 34944 EXCEPTIONS: AVX512-E2 34945 REAL_OPCODE: Y 34946 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 34947 PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 34948 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 34949 IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 34950 } 34951 34952 34953 # EMITTING VMULPS (VMULPS-256-1) 34954 { 34955 ICLASS: VMULPS 34956 CPL: 3 34957 CATEGORY: AVX512 34958 EXTENSION: AVX512EVEX 34959 ISA_SET: AVX512F_256 34960 EXCEPTIONS: AVX512-E2 34961 REAL_OPCODE: Y 34962 ATTRIBUTES: MASKOP_EVEX MXCSR 34963 PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 34964 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 34965 IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 34966 } 34967 34968 { 34969 ICLASS: VMULPS 34970 CPL: 3 34971 CATEGORY: AVX512 34972 EXTENSION: AVX512EVEX 34973 ISA_SET: AVX512F_256 34974 EXCEPTIONS: AVX512-E2 34975 REAL_OPCODE: Y 34976 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 34977 PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 34978 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 34979 IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 34980 } 34981 34982 34983 # EMITTING VORPD (VORPD-128-1) 34984 { 34985 ICLASS: VORPD 34986 CPL: 3 34987 CATEGORY: LOGICAL_FP 34988 EXTENSION: AVX512EVEX 34989 ISA_SET: AVX512DQ_128 34990 EXCEPTIONS: AVX512-E4 34991 REAL_OPCODE: Y 34992 ATTRIBUTES: MASKOP_EVEX 34993 PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 34994 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 34995 IFORM: VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 34996 } 34997 34998 { 34999 ICLASS: VORPD 35000 CPL: 3 35001 CATEGORY: LOGICAL_FP 35002 EXTENSION: AVX512EVEX 35003 ISA_SET: AVX512DQ_128 35004 EXCEPTIONS: AVX512-E4 35005 REAL_OPCODE: Y 35006 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35007 PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 35008 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 35009 IFORM: VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 35010 } 35011 35012 35013 # EMITTING VORPD (VORPD-256-1) 35014 { 35015 ICLASS: VORPD 35016 CPL: 3 35017 CATEGORY: LOGICAL_FP 35018 EXTENSION: AVX512EVEX 35019 ISA_SET: AVX512DQ_256 35020 EXCEPTIONS: AVX512-E4 35021 REAL_OPCODE: Y 35022 ATTRIBUTES: MASKOP_EVEX 35023 PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 35024 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 35025 IFORM: VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 35026 } 35027 35028 { 35029 ICLASS: VORPD 35030 CPL: 3 35031 CATEGORY: LOGICAL_FP 35032 EXTENSION: AVX512EVEX 35033 ISA_SET: AVX512DQ_256 35034 EXCEPTIONS: AVX512-E4 35035 REAL_OPCODE: Y 35036 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35037 PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 35038 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 35039 IFORM: VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 35040 } 35041 35042 35043 # EMITTING VORPD (VORPD-512-1) 35044 { 35045 ICLASS: VORPD 35046 CPL: 3 35047 CATEGORY: LOGICAL_FP 35048 EXTENSION: AVX512EVEX 35049 ISA_SET: AVX512DQ_512 35050 EXCEPTIONS: AVX512-E4 35051 REAL_OPCODE: Y 35052 ATTRIBUTES: MASKOP_EVEX 35053 PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 35054 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 35055 IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 35056 } 35057 35058 { 35059 ICLASS: VORPD 35060 CPL: 3 35061 CATEGORY: LOGICAL_FP 35062 EXTENSION: AVX512EVEX 35063 ISA_SET: AVX512DQ_512 35064 EXCEPTIONS: AVX512-E4 35065 REAL_OPCODE: Y 35066 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35067 PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 35068 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 35069 IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 35070 } 35071 35072 35073 # EMITTING VORPS (VORPS-128-1) 35074 { 35075 ICLASS: VORPS 35076 CPL: 3 35077 CATEGORY: LOGICAL_FP 35078 EXTENSION: AVX512EVEX 35079 ISA_SET: AVX512DQ_128 35080 EXCEPTIONS: AVX512-E4 35081 REAL_OPCODE: Y 35082 ATTRIBUTES: MASKOP_EVEX 35083 PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 35084 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 35085 IFORM: VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 35086 } 35087 35088 { 35089 ICLASS: VORPS 35090 CPL: 3 35091 CATEGORY: LOGICAL_FP 35092 EXTENSION: AVX512EVEX 35093 ISA_SET: AVX512DQ_128 35094 EXCEPTIONS: AVX512-E4 35095 REAL_OPCODE: Y 35096 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35097 PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 35098 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 35099 IFORM: VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 35100 } 35101 35102 35103 # EMITTING VORPS (VORPS-256-1) 35104 { 35105 ICLASS: VORPS 35106 CPL: 3 35107 CATEGORY: LOGICAL_FP 35108 EXTENSION: AVX512EVEX 35109 ISA_SET: AVX512DQ_256 35110 EXCEPTIONS: AVX512-E4 35111 REAL_OPCODE: Y 35112 ATTRIBUTES: MASKOP_EVEX 35113 PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 35114 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 35115 IFORM: VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 35116 } 35117 35118 { 35119 ICLASS: VORPS 35120 CPL: 3 35121 CATEGORY: LOGICAL_FP 35122 EXTENSION: AVX512EVEX 35123 ISA_SET: AVX512DQ_256 35124 EXCEPTIONS: AVX512-E4 35125 REAL_OPCODE: Y 35126 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35127 PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 35128 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 35129 IFORM: VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 35130 } 35131 35132 35133 # EMITTING VORPS (VORPS-512-1) 35134 { 35135 ICLASS: VORPS 35136 CPL: 3 35137 CATEGORY: LOGICAL_FP 35138 EXTENSION: AVX512EVEX 35139 ISA_SET: AVX512DQ_512 35140 EXCEPTIONS: AVX512-E4 35141 REAL_OPCODE: Y 35142 ATTRIBUTES: MASKOP_EVEX 35143 PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 35144 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 35145 IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 35146 } 35147 35148 { 35149 ICLASS: VORPS 35150 CPL: 3 35151 CATEGORY: LOGICAL_FP 35152 EXTENSION: AVX512EVEX 35153 ISA_SET: AVX512DQ_512 35154 EXCEPTIONS: AVX512-E4 35155 REAL_OPCODE: Y 35156 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35157 PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 35158 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 35159 IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 35160 } 35161 35162 35163 # EMITTING VPABSB (VPABSB-128-1) 35164 { 35165 ICLASS: VPABSB 35166 CPL: 3 35167 CATEGORY: AVX512 35168 EXTENSION: AVX512EVEX 35169 ISA_SET: AVX512BW_128 35170 EXCEPTIONS: AVX512-E4 35171 REAL_OPCODE: Y 35172 ATTRIBUTES: MASKOP_EVEX 35173 PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 35174 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 35175 IFORM: VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 35176 } 35177 35178 { 35179 ICLASS: VPABSB 35180 CPL: 3 35181 CATEGORY: AVX512 35182 EXTENSION: AVX512EVEX 35183 ISA_SET: AVX512BW_128 35184 EXCEPTIONS: AVX512-E4 35185 REAL_OPCODE: Y 35186 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35187 PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 35188 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 35189 IFORM: VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 35190 } 35191 35192 35193 # EMITTING VPABSB (VPABSB-256-1) 35194 { 35195 ICLASS: VPABSB 35196 CPL: 3 35197 CATEGORY: AVX512 35198 EXTENSION: AVX512EVEX 35199 ISA_SET: AVX512BW_256 35200 EXCEPTIONS: AVX512-E4 35201 REAL_OPCODE: Y 35202 ATTRIBUTES: MASKOP_EVEX 35203 PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 35204 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 35205 IFORM: VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 35206 } 35207 35208 { 35209 ICLASS: VPABSB 35210 CPL: 3 35211 CATEGORY: AVX512 35212 EXTENSION: AVX512EVEX 35213 ISA_SET: AVX512BW_256 35214 EXCEPTIONS: AVX512-E4 35215 REAL_OPCODE: Y 35216 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35217 PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 35218 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 35219 IFORM: VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 35220 } 35221 35222 35223 # EMITTING VPABSB (VPABSB-512-1) 35224 { 35225 ICLASS: VPABSB 35226 CPL: 3 35227 CATEGORY: AVX512 35228 EXTENSION: AVX512EVEX 35229 ISA_SET: AVX512BW_512 35230 EXCEPTIONS: AVX512-E4 35231 REAL_OPCODE: Y 35232 ATTRIBUTES: MASKOP_EVEX 35233 PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 35234 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi8 35235 IFORM: VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 35236 } 35237 35238 { 35239 ICLASS: VPABSB 35240 CPL: 3 35241 CATEGORY: AVX512 35242 EXTENSION: AVX512EVEX 35243 ISA_SET: AVX512BW_512 35244 EXCEPTIONS: AVX512-E4 35245 REAL_OPCODE: Y 35246 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35247 PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 35248 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i8 35249 IFORM: VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 35250 } 35251 35252 35253 # EMITTING VPABSD (VPABSD-128-1) 35254 { 35255 ICLASS: VPABSD 35256 CPL: 3 35257 CATEGORY: AVX512 35258 EXTENSION: AVX512EVEX 35259 ISA_SET: AVX512F_128 35260 EXCEPTIONS: AVX512-E4 35261 REAL_OPCODE: Y 35262 ATTRIBUTES: MASKOP_EVEX 35263 PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 35264 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 35265 IFORM: VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 35266 } 35267 35268 { 35269 ICLASS: VPABSD 35270 CPL: 3 35271 CATEGORY: AVX512 35272 EXTENSION: AVX512EVEX 35273 ISA_SET: AVX512F_128 35274 EXCEPTIONS: AVX512-E4 35275 REAL_OPCODE: Y 35276 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35277 PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 35278 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 35279 IFORM: VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 35280 } 35281 35282 35283 # EMITTING VPABSD (VPABSD-256-1) 35284 { 35285 ICLASS: VPABSD 35286 CPL: 3 35287 CATEGORY: AVX512 35288 EXTENSION: AVX512EVEX 35289 ISA_SET: AVX512F_256 35290 EXCEPTIONS: AVX512-E4 35291 REAL_OPCODE: Y 35292 ATTRIBUTES: MASKOP_EVEX 35293 PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 35294 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 35295 IFORM: VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 35296 } 35297 35298 { 35299 ICLASS: VPABSD 35300 CPL: 3 35301 CATEGORY: AVX512 35302 EXTENSION: AVX512EVEX 35303 ISA_SET: AVX512F_256 35304 EXCEPTIONS: AVX512-E4 35305 REAL_OPCODE: Y 35306 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35307 PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 35308 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR 35309 IFORM: VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 35310 } 35311 35312 35313 # EMITTING VPABSQ (VPABSQ-128-1) 35314 { 35315 ICLASS: VPABSQ 35316 CPL: 3 35317 CATEGORY: AVX512 35318 EXTENSION: AVX512EVEX 35319 ISA_SET: AVX512F_128 35320 EXCEPTIONS: AVX512-E4 35321 REAL_OPCODE: Y 35322 ATTRIBUTES: MASKOP_EVEX 35323 PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 35324 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i64 35325 IFORM: VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 35326 } 35327 35328 { 35329 ICLASS: VPABSQ 35330 CPL: 3 35331 CATEGORY: AVX512 35332 EXTENSION: AVX512EVEX 35333 ISA_SET: AVX512F_128 35334 EXCEPTIONS: AVX512-E4 35335 REAL_OPCODE: Y 35336 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35337 PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 35338 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR 35339 IFORM: VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 35340 } 35341 35342 35343 # EMITTING VPABSQ (VPABSQ-256-1) 35344 { 35345 ICLASS: VPABSQ 35346 CPL: 3 35347 CATEGORY: AVX512 35348 EXTENSION: AVX512EVEX 35349 ISA_SET: AVX512F_256 35350 EXCEPTIONS: AVX512-E4 35351 REAL_OPCODE: Y 35352 ATTRIBUTES: MASKOP_EVEX 35353 PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 35354 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i64 35355 IFORM: VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 35356 } 35357 35358 { 35359 ICLASS: VPABSQ 35360 CPL: 3 35361 CATEGORY: AVX512 35362 EXTENSION: AVX512EVEX 35363 ISA_SET: AVX512F_256 35364 EXCEPTIONS: AVX512-E4 35365 REAL_OPCODE: Y 35366 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35367 PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 35368 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR 35369 IFORM: VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 35370 } 35371 35372 35373 # EMITTING VPABSW (VPABSW-128-1) 35374 { 35375 ICLASS: VPABSW 35376 CPL: 3 35377 CATEGORY: AVX512 35378 EXTENSION: AVX512EVEX 35379 ISA_SET: AVX512BW_128 35380 EXCEPTIONS: AVX512-E4 35381 REAL_OPCODE: Y 35382 ATTRIBUTES: MASKOP_EVEX 35383 PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 35384 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 35385 IFORM: VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 35386 } 35387 35388 { 35389 ICLASS: VPABSW 35390 CPL: 3 35391 CATEGORY: AVX512 35392 EXTENSION: AVX512EVEX 35393 ISA_SET: AVX512BW_128 35394 EXCEPTIONS: AVX512-E4 35395 REAL_OPCODE: Y 35396 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35397 PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 35398 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 35399 IFORM: VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 35400 } 35401 35402 35403 # EMITTING VPABSW (VPABSW-256-1) 35404 { 35405 ICLASS: VPABSW 35406 CPL: 3 35407 CATEGORY: AVX512 35408 EXTENSION: AVX512EVEX 35409 ISA_SET: AVX512BW_256 35410 EXCEPTIONS: AVX512-E4 35411 REAL_OPCODE: Y 35412 ATTRIBUTES: MASKOP_EVEX 35413 PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 35414 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 35415 IFORM: VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 35416 } 35417 35418 { 35419 ICLASS: VPABSW 35420 CPL: 3 35421 CATEGORY: AVX512 35422 EXTENSION: AVX512EVEX 35423 ISA_SET: AVX512BW_256 35424 EXCEPTIONS: AVX512-E4 35425 REAL_OPCODE: Y 35426 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35427 PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 35428 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 35429 IFORM: VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 35430 } 35431 35432 35433 # EMITTING VPABSW (VPABSW-512-1) 35434 { 35435 ICLASS: VPABSW 35436 CPL: 3 35437 CATEGORY: AVX512 35438 EXTENSION: AVX512EVEX 35439 ISA_SET: AVX512BW_512 35440 EXCEPTIONS: AVX512-E4 35441 REAL_OPCODE: Y 35442 ATTRIBUTES: MASKOP_EVEX 35443 PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 35444 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16 35445 IFORM: VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 35446 } 35447 35448 { 35449 ICLASS: VPABSW 35450 CPL: 3 35451 CATEGORY: AVX512 35452 EXTENSION: AVX512EVEX 35453 ISA_SET: AVX512BW_512 35454 EXCEPTIONS: AVX512-E4 35455 REAL_OPCODE: Y 35456 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35457 PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 35458 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i16 35459 IFORM: VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 35460 } 35461 35462 35463 # EMITTING VPACKSSDW (VPACKSSDW-128-1) 35464 { 35465 ICLASS: VPACKSSDW 35466 CPL: 3 35467 CATEGORY: AVX512 35468 EXTENSION: AVX512EVEX 35469 ISA_SET: AVX512BW_128 35470 EXCEPTIONS: AVX512-E4NF 35471 REAL_OPCODE: Y 35472 ATTRIBUTES: MASKOP_EVEX 35473 PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 35474 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 35475 IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 35476 } 35477 35478 { 35479 ICLASS: VPACKSSDW 35480 CPL: 3 35481 CATEGORY: AVX512 35482 EXTENSION: AVX512EVEX 35483 ISA_SET: AVX512BW_128 35484 EXCEPTIONS: AVX512-E4NF 35485 REAL_OPCODE: Y 35486 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35487 PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 35488 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 35489 IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 35490 } 35491 35492 35493 # EMITTING VPACKSSDW (VPACKSSDW-256-1) 35494 { 35495 ICLASS: VPACKSSDW 35496 CPL: 3 35497 CATEGORY: AVX512 35498 EXTENSION: AVX512EVEX 35499 ISA_SET: AVX512BW_256 35500 EXCEPTIONS: AVX512-E4NF 35501 REAL_OPCODE: Y 35502 ATTRIBUTES: MASKOP_EVEX 35503 PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 35504 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 35505 IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 35506 } 35507 35508 { 35509 ICLASS: VPACKSSDW 35510 CPL: 3 35511 CATEGORY: AVX512 35512 EXTENSION: AVX512EVEX 35513 ISA_SET: AVX512BW_256 35514 EXCEPTIONS: AVX512-E4NF 35515 REAL_OPCODE: Y 35516 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35517 PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 35518 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 35519 IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 35520 } 35521 35522 35523 # EMITTING VPACKSSDW (VPACKSSDW-512-1) 35524 { 35525 ICLASS: VPACKSSDW 35526 CPL: 3 35527 CATEGORY: AVX512 35528 EXTENSION: AVX512EVEX 35529 ISA_SET: AVX512BW_512 35530 EXCEPTIONS: AVX512-E4NF 35531 REAL_OPCODE: Y 35532 ATTRIBUTES: MASKOP_EVEX 35533 PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 35534 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 35535 IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 35536 } 35537 35538 { 35539 ICLASS: VPACKSSDW 35540 CPL: 3 35541 CATEGORY: AVX512 35542 EXTENSION: AVX512EVEX 35543 ISA_SET: AVX512BW_512 35544 EXCEPTIONS: AVX512-E4NF 35545 REAL_OPCODE: Y 35546 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35547 PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 35548 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR 35549 IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 35550 } 35551 35552 35553 # EMITTING VPACKSSWB (VPACKSSWB-128-1) 35554 { 35555 ICLASS: VPACKSSWB 35556 CPL: 3 35557 CATEGORY: AVX512 35558 EXTENSION: AVX512EVEX 35559 ISA_SET: AVX512BW_128 35560 EXCEPTIONS: AVX512-E4NF 35561 REAL_OPCODE: Y 35562 ATTRIBUTES: MASKOP_EVEX 35563 PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 35564 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 35565 IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 35566 } 35567 35568 { 35569 ICLASS: VPACKSSWB 35570 CPL: 3 35571 CATEGORY: AVX512 35572 EXTENSION: AVX512EVEX 35573 ISA_SET: AVX512BW_128 35574 EXCEPTIONS: AVX512-E4NF 35575 REAL_OPCODE: Y 35576 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 35577 PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 35578 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 35579 IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 35580 } 35581 35582 35583 # EMITTING VPACKSSWB (VPACKSSWB-256-1) 35584 { 35585 ICLASS: VPACKSSWB 35586 CPL: 3 35587 CATEGORY: AVX512 35588 EXTENSION: AVX512EVEX 35589 ISA_SET: AVX512BW_256 35590 EXCEPTIONS: AVX512-E4NF 35591 REAL_OPCODE: Y 35592 ATTRIBUTES: MASKOP_EVEX 35593 PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 35594 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 35595 IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 35596 } 35597 35598 { 35599 ICLASS: VPACKSSWB 35600 CPL: 3 35601 CATEGORY: AVX512 35602 EXTENSION: AVX512EVEX 35603 ISA_SET: AVX512BW_256 35604 EXCEPTIONS: AVX512-E4NF 35605 REAL_OPCODE: Y 35606 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 35607 PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 35608 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 35609 IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 35610 } 35611 35612 35613 # EMITTING VPACKSSWB (VPACKSSWB-512-1) 35614 { 35615 ICLASS: VPACKSSWB 35616 CPL: 3 35617 CATEGORY: AVX512 35618 EXTENSION: AVX512EVEX 35619 ISA_SET: AVX512BW_512 35620 EXCEPTIONS: AVX512-E4NF 35621 REAL_OPCODE: Y 35622 ATTRIBUTES: MASKOP_EVEX 35623 PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 35624 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 35625 IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 35626 } 35627 35628 { 35629 ICLASS: VPACKSSWB 35630 CPL: 3 35631 CATEGORY: AVX512 35632 EXTENSION: AVX512EVEX 35633 ISA_SET: AVX512BW_512 35634 EXCEPTIONS: AVX512-E4NF 35635 REAL_OPCODE: Y 35636 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 35637 PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 35638 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 35639 IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 35640 } 35641 35642 35643 # EMITTING VPACKUSDW (VPACKUSDW-128-1) 35644 { 35645 ICLASS: VPACKUSDW 35646 CPL: 3 35647 CATEGORY: AVX512 35648 EXTENSION: AVX512EVEX 35649 ISA_SET: AVX512BW_128 35650 EXCEPTIONS: AVX512-E4NF 35651 REAL_OPCODE: Y 35652 ATTRIBUTES: MASKOP_EVEX 35653 PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 35654 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 35655 IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 35656 } 35657 35658 { 35659 ICLASS: VPACKUSDW 35660 CPL: 3 35661 CATEGORY: AVX512 35662 EXTENSION: AVX512EVEX 35663 ISA_SET: AVX512BW_128 35664 EXCEPTIONS: AVX512-E4NF 35665 REAL_OPCODE: Y 35666 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35667 PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 35668 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 35669 IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 35670 } 35671 35672 35673 # EMITTING VPACKUSDW (VPACKUSDW-256-1) 35674 { 35675 ICLASS: VPACKUSDW 35676 CPL: 3 35677 CATEGORY: AVX512 35678 EXTENSION: AVX512EVEX 35679 ISA_SET: AVX512BW_256 35680 EXCEPTIONS: AVX512-E4NF 35681 REAL_OPCODE: Y 35682 ATTRIBUTES: MASKOP_EVEX 35683 PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 35684 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 35685 IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 35686 } 35687 35688 { 35689 ICLASS: VPACKUSDW 35690 CPL: 3 35691 CATEGORY: AVX512 35692 EXTENSION: AVX512EVEX 35693 ISA_SET: AVX512BW_256 35694 EXCEPTIONS: AVX512-E4NF 35695 REAL_OPCODE: Y 35696 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35697 PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 35698 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 35699 IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 35700 } 35701 35702 35703 # EMITTING VPACKUSDW (VPACKUSDW-512-1) 35704 { 35705 ICLASS: VPACKUSDW 35706 CPL: 3 35707 CATEGORY: AVX512 35708 EXTENSION: AVX512EVEX 35709 ISA_SET: AVX512BW_512 35710 EXCEPTIONS: AVX512-E4NF 35711 REAL_OPCODE: Y 35712 ATTRIBUTES: MASKOP_EVEX 35713 PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 35714 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 35715 IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 35716 } 35717 35718 { 35719 ICLASS: VPACKUSDW 35720 CPL: 3 35721 CATEGORY: AVX512 35722 EXTENSION: AVX512EVEX 35723 ISA_SET: AVX512BW_512 35724 EXCEPTIONS: AVX512-E4NF 35725 REAL_OPCODE: Y 35726 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35727 PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 35728 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 35729 IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 35730 } 35731 35732 35733 # EMITTING VPACKUSWB (VPACKUSWB-128-1) 35734 { 35735 ICLASS: VPACKUSWB 35736 CPL: 3 35737 CATEGORY: AVX512 35738 EXTENSION: AVX512EVEX 35739 ISA_SET: AVX512BW_128 35740 EXCEPTIONS: AVX512-E4NF 35741 REAL_OPCODE: Y 35742 ATTRIBUTES: MASKOP_EVEX 35743 PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 35744 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 35745 IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 35746 } 35747 35748 { 35749 ICLASS: VPACKUSWB 35750 CPL: 3 35751 CATEGORY: AVX512 35752 EXTENSION: AVX512EVEX 35753 ISA_SET: AVX512BW_128 35754 EXCEPTIONS: AVX512-E4NF 35755 REAL_OPCODE: Y 35756 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 35757 PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 35758 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 35759 IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 35760 } 35761 35762 35763 # EMITTING VPACKUSWB (VPACKUSWB-256-1) 35764 { 35765 ICLASS: VPACKUSWB 35766 CPL: 3 35767 CATEGORY: AVX512 35768 EXTENSION: AVX512EVEX 35769 ISA_SET: AVX512BW_256 35770 EXCEPTIONS: AVX512-E4NF 35771 REAL_OPCODE: Y 35772 ATTRIBUTES: MASKOP_EVEX 35773 PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 35774 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 35775 IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 35776 } 35777 35778 { 35779 ICLASS: VPACKUSWB 35780 CPL: 3 35781 CATEGORY: AVX512 35782 EXTENSION: AVX512EVEX 35783 ISA_SET: AVX512BW_256 35784 EXCEPTIONS: AVX512-E4NF 35785 REAL_OPCODE: Y 35786 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 35787 PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 35788 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 35789 IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 35790 } 35791 35792 35793 # EMITTING VPACKUSWB (VPACKUSWB-512-1) 35794 { 35795 ICLASS: VPACKUSWB 35796 CPL: 3 35797 CATEGORY: AVX512 35798 EXTENSION: AVX512EVEX 35799 ISA_SET: AVX512BW_512 35800 EXCEPTIONS: AVX512-E4NF 35801 REAL_OPCODE: Y 35802 ATTRIBUTES: MASKOP_EVEX 35803 PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 35804 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 35805 IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 35806 } 35807 35808 { 35809 ICLASS: VPACKUSWB 35810 CPL: 3 35811 CATEGORY: AVX512 35812 EXTENSION: AVX512EVEX 35813 ISA_SET: AVX512BW_512 35814 EXCEPTIONS: AVX512-E4NF 35815 REAL_OPCODE: Y 35816 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 35817 PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 35818 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 35819 IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 35820 } 35821 35822 35823 # EMITTING VPADDB (VPADDB-128-1) 35824 { 35825 ICLASS: VPADDB 35826 CPL: 3 35827 CATEGORY: AVX512 35828 EXTENSION: AVX512EVEX 35829 ISA_SET: AVX512BW_128 35830 EXCEPTIONS: AVX512-E4 35831 REAL_OPCODE: Y 35832 ATTRIBUTES: MASKOP_EVEX 35833 PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 35834 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 35835 IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 35836 } 35837 35838 { 35839 ICLASS: VPADDB 35840 CPL: 3 35841 CATEGORY: AVX512 35842 EXTENSION: AVX512EVEX 35843 ISA_SET: AVX512BW_128 35844 EXCEPTIONS: AVX512-E4 35845 REAL_OPCODE: Y 35846 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35847 PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 35848 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 35849 IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 35850 } 35851 35852 35853 # EMITTING VPADDB (VPADDB-256-1) 35854 { 35855 ICLASS: VPADDB 35856 CPL: 3 35857 CATEGORY: AVX512 35858 EXTENSION: AVX512EVEX 35859 ISA_SET: AVX512BW_256 35860 EXCEPTIONS: AVX512-E4 35861 REAL_OPCODE: Y 35862 ATTRIBUTES: MASKOP_EVEX 35863 PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 35864 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 35865 IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 35866 } 35867 35868 { 35869 ICLASS: VPADDB 35870 CPL: 3 35871 CATEGORY: AVX512 35872 EXTENSION: AVX512EVEX 35873 ISA_SET: AVX512BW_256 35874 EXCEPTIONS: AVX512-E4 35875 REAL_OPCODE: Y 35876 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35877 PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 35878 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 35879 IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 35880 } 35881 35882 35883 # EMITTING VPADDB (VPADDB-512-1) 35884 { 35885 ICLASS: VPADDB 35886 CPL: 3 35887 CATEGORY: AVX512 35888 EXTENSION: AVX512EVEX 35889 ISA_SET: AVX512BW_512 35890 EXCEPTIONS: AVX512-E4 35891 REAL_OPCODE: Y 35892 ATTRIBUTES: MASKOP_EVEX 35893 PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 35894 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 35895 IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 35896 } 35897 35898 { 35899 ICLASS: VPADDB 35900 CPL: 3 35901 CATEGORY: AVX512 35902 EXTENSION: AVX512EVEX 35903 ISA_SET: AVX512BW_512 35904 EXCEPTIONS: AVX512-E4 35905 REAL_OPCODE: Y 35906 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 35907 PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 35908 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 35909 IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 35910 } 35911 35912 35913 # EMITTING VPADDD (VPADDD-128-1) 35914 { 35915 ICLASS: VPADDD 35916 CPL: 3 35917 CATEGORY: AVX512 35918 EXTENSION: AVX512EVEX 35919 ISA_SET: AVX512F_128 35920 EXCEPTIONS: AVX512-E4 35921 REAL_OPCODE: Y 35922 ATTRIBUTES: MASKOP_EVEX 35923 PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 35924 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 35925 IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 35926 } 35927 35928 { 35929 ICLASS: VPADDD 35930 CPL: 3 35931 CATEGORY: AVX512 35932 EXTENSION: AVX512EVEX 35933 ISA_SET: AVX512F_128 35934 EXCEPTIONS: AVX512-E4 35935 REAL_OPCODE: Y 35936 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35937 PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 35938 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 35939 IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 35940 } 35941 35942 35943 # EMITTING VPADDD (VPADDD-256-1) 35944 { 35945 ICLASS: VPADDD 35946 CPL: 3 35947 CATEGORY: AVX512 35948 EXTENSION: AVX512EVEX 35949 ISA_SET: AVX512F_256 35950 EXCEPTIONS: AVX512-E4 35951 REAL_OPCODE: Y 35952 ATTRIBUTES: MASKOP_EVEX 35953 PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 35954 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 35955 IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 35956 } 35957 35958 { 35959 ICLASS: VPADDD 35960 CPL: 3 35961 CATEGORY: AVX512 35962 EXTENSION: AVX512EVEX 35963 ISA_SET: AVX512F_256 35964 EXCEPTIONS: AVX512-E4 35965 REAL_OPCODE: Y 35966 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35967 PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 35968 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 35969 IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 35970 } 35971 35972 35973 # EMITTING VPADDQ (VPADDQ-128-1) 35974 { 35975 ICLASS: VPADDQ 35976 CPL: 3 35977 CATEGORY: AVX512 35978 EXTENSION: AVX512EVEX 35979 ISA_SET: AVX512F_128 35980 EXCEPTIONS: AVX512-E4 35981 REAL_OPCODE: Y 35982 ATTRIBUTES: MASKOP_EVEX 35983 PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 35984 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 35985 IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 35986 } 35987 35988 { 35989 ICLASS: VPADDQ 35990 CPL: 3 35991 CATEGORY: AVX512 35992 EXTENSION: AVX512EVEX 35993 ISA_SET: AVX512F_128 35994 EXCEPTIONS: AVX512-E4 35995 REAL_OPCODE: Y 35996 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 35997 PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 35998 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 35999 IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 36000 } 36001 36002 36003 # EMITTING VPADDQ (VPADDQ-256-1) 36004 { 36005 ICLASS: VPADDQ 36006 CPL: 3 36007 CATEGORY: AVX512 36008 EXTENSION: AVX512EVEX 36009 ISA_SET: AVX512F_256 36010 EXCEPTIONS: AVX512-E4 36011 REAL_OPCODE: Y 36012 ATTRIBUTES: MASKOP_EVEX 36013 PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 36014 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 36015 IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 36016 } 36017 36018 { 36019 ICLASS: VPADDQ 36020 CPL: 3 36021 CATEGORY: AVX512 36022 EXTENSION: AVX512EVEX 36023 ISA_SET: AVX512F_256 36024 EXCEPTIONS: AVX512-E4 36025 REAL_OPCODE: Y 36026 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36027 PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 36028 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 36029 IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 36030 } 36031 36032 36033 # EMITTING VPADDSB (VPADDSB-128-1) 36034 { 36035 ICLASS: VPADDSB 36036 CPL: 3 36037 CATEGORY: AVX512 36038 EXTENSION: AVX512EVEX 36039 ISA_SET: AVX512BW_128 36040 EXCEPTIONS: AVX512-E4 36041 REAL_OPCODE: Y 36042 ATTRIBUTES: MASKOP_EVEX 36043 PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 36044 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 36045 IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 36046 } 36047 36048 { 36049 ICLASS: VPADDSB 36050 CPL: 3 36051 CATEGORY: AVX512 36052 EXTENSION: AVX512EVEX 36053 ISA_SET: AVX512BW_128 36054 EXCEPTIONS: AVX512-E4 36055 REAL_OPCODE: Y 36056 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36057 PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 36058 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 36059 IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 36060 } 36061 36062 36063 # EMITTING VPADDSB (VPADDSB-256-1) 36064 { 36065 ICLASS: VPADDSB 36066 CPL: 3 36067 CATEGORY: AVX512 36068 EXTENSION: AVX512EVEX 36069 ISA_SET: AVX512BW_256 36070 EXCEPTIONS: AVX512-E4 36071 REAL_OPCODE: Y 36072 ATTRIBUTES: MASKOP_EVEX 36073 PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 36074 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 36075 IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 36076 } 36077 36078 { 36079 ICLASS: VPADDSB 36080 CPL: 3 36081 CATEGORY: AVX512 36082 EXTENSION: AVX512EVEX 36083 ISA_SET: AVX512BW_256 36084 EXCEPTIONS: AVX512-E4 36085 REAL_OPCODE: Y 36086 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36087 PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 36088 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 36089 IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 36090 } 36091 36092 36093 # EMITTING VPADDSB (VPADDSB-512-1) 36094 { 36095 ICLASS: VPADDSB 36096 CPL: 3 36097 CATEGORY: AVX512 36098 EXTENSION: AVX512EVEX 36099 ISA_SET: AVX512BW_512 36100 EXCEPTIONS: AVX512-E4 36101 REAL_OPCODE: Y 36102 ATTRIBUTES: MASKOP_EVEX 36103 PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 36104 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 36105 IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 36106 } 36107 36108 { 36109 ICLASS: VPADDSB 36110 CPL: 3 36111 CATEGORY: AVX512 36112 EXTENSION: AVX512EVEX 36113 ISA_SET: AVX512BW_512 36114 EXCEPTIONS: AVX512-E4 36115 REAL_OPCODE: Y 36116 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36117 PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 36118 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 36119 IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 36120 } 36121 36122 36123 # EMITTING VPADDSW (VPADDSW-128-1) 36124 { 36125 ICLASS: VPADDSW 36126 CPL: 3 36127 CATEGORY: AVX512 36128 EXTENSION: AVX512EVEX 36129 ISA_SET: AVX512BW_128 36130 EXCEPTIONS: AVX512-E4 36131 REAL_OPCODE: Y 36132 ATTRIBUTES: MASKOP_EVEX 36133 PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 36134 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 36135 IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 36136 } 36137 36138 { 36139 ICLASS: VPADDSW 36140 CPL: 3 36141 CATEGORY: AVX512 36142 EXTENSION: AVX512EVEX 36143 ISA_SET: AVX512BW_128 36144 EXCEPTIONS: AVX512-E4 36145 REAL_OPCODE: Y 36146 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36147 PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 36148 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 36149 IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 36150 } 36151 36152 36153 # EMITTING VPADDSW (VPADDSW-256-1) 36154 { 36155 ICLASS: VPADDSW 36156 CPL: 3 36157 CATEGORY: AVX512 36158 EXTENSION: AVX512EVEX 36159 ISA_SET: AVX512BW_256 36160 EXCEPTIONS: AVX512-E4 36161 REAL_OPCODE: Y 36162 ATTRIBUTES: MASKOP_EVEX 36163 PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 36164 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 36165 IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 36166 } 36167 36168 { 36169 ICLASS: VPADDSW 36170 CPL: 3 36171 CATEGORY: AVX512 36172 EXTENSION: AVX512EVEX 36173 ISA_SET: AVX512BW_256 36174 EXCEPTIONS: AVX512-E4 36175 REAL_OPCODE: Y 36176 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36177 PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 36178 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 36179 IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 36180 } 36181 36182 36183 # EMITTING VPADDSW (VPADDSW-512-1) 36184 { 36185 ICLASS: VPADDSW 36186 CPL: 3 36187 CATEGORY: AVX512 36188 EXTENSION: AVX512EVEX 36189 ISA_SET: AVX512BW_512 36190 EXCEPTIONS: AVX512-E4 36191 REAL_OPCODE: Y 36192 ATTRIBUTES: MASKOP_EVEX 36193 PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 36194 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 36195 IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 36196 } 36197 36198 { 36199 ICLASS: VPADDSW 36200 CPL: 3 36201 CATEGORY: AVX512 36202 EXTENSION: AVX512EVEX 36203 ISA_SET: AVX512BW_512 36204 EXCEPTIONS: AVX512-E4 36205 REAL_OPCODE: Y 36206 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36207 PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 36208 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 36209 IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 36210 } 36211 36212 36213 # EMITTING VPADDUSB (VPADDUSB-128-1) 36214 { 36215 ICLASS: VPADDUSB 36216 CPL: 3 36217 CATEGORY: AVX512 36218 EXTENSION: AVX512EVEX 36219 ISA_SET: AVX512BW_128 36220 EXCEPTIONS: AVX512-E4 36221 REAL_OPCODE: Y 36222 ATTRIBUTES: MASKOP_EVEX 36223 PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 36224 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 36225 IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 36226 } 36227 36228 { 36229 ICLASS: VPADDUSB 36230 CPL: 3 36231 CATEGORY: AVX512 36232 EXTENSION: AVX512EVEX 36233 ISA_SET: AVX512BW_128 36234 EXCEPTIONS: AVX512-E4 36235 REAL_OPCODE: Y 36236 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36237 PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 36238 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 36239 IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 36240 } 36241 36242 36243 # EMITTING VPADDUSB (VPADDUSB-256-1) 36244 { 36245 ICLASS: VPADDUSB 36246 CPL: 3 36247 CATEGORY: AVX512 36248 EXTENSION: AVX512EVEX 36249 ISA_SET: AVX512BW_256 36250 EXCEPTIONS: AVX512-E4 36251 REAL_OPCODE: Y 36252 ATTRIBUTES: MASKOP_EVEX 36253 PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 36254 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 36255 IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 36256 } 36257 36258 { 36259 ICLASS: VPADDUSB 36260 CPL: 3 36261 CATEGORY: AVX512 36262 EXTENSION: AVX512EVEX 36263 ISA_SET: AVX512BW_256 36264 EXCEPTIONS: AVX512-E4 36265 REAL_OPCODE: Y 36266 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36267 PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 36268 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 36269 IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 36270 } 36271 36272 36273 # EMITTING VPADDUSB (VPADDUSB-512-1) 36274 { 36275 ICLASS: VPADDUSB 36276 CPL: 3 36277 CATEGORY: AVX512 36278 EXTENSION: AVX512EVEX 36279 ISA_SET: AVX512BW_512 36280 EXCEPTIONS: AVX512-E4 36281 REAL_OPCODE: Y 36282 ATTRIBUTES: MASKOP_EVEX 36283 PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 36284 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 36285 IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 36286 } 36287 36288 { 36289 ICLASS: VPADDUSB 36290 CPL: 3 36291 CATEGORY: AVX512 36292 EXTENSION: AVX512EVEX 36293 ISA_SET: AVX512BW_512 36294 EXCEPTIONS: AVX512-E4 36295 REAL_OPCODE: Y 36296 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36297 PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 36298 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 36299 IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 36300 } 36301 36302 36303 # EMITTING VPADDUSW (VPADDUSW-128-1) 36304 { 36305 ICLASS: VPADDUSW 36306 CPL: 3 36307 CATEGORY: AVX512 36308 EXTENSION: AVX512EVEX 36309 ISA_SET: AVX512BW_128 36310 EXCEPTIONS: AVX512-E4 36311 REAL_OPCODE: Y 36312 ATTRIBUTES: MASKOP_EVEX 36313 PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 36314 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 36315 IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 36316 } 36317 36318 { 36319 ICLASS: VPADDUSW 36320 CPL: 3 36321 CATEGORY: AVX512 36322 EXTENSION: AVX512EVEX 36323 ISA_SET: AVX512BW_128 36324 EXCEPTIONS: AVX512-E4 36325 REAL_OPCODE: Y 36326 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36327 PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 36328 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 36329 IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 36330 } 36331 36332 36333 # EMITTING VPADDUSW (VPADDUSW-256-1) 36334 { 36335 ICLASS: VPADDUSW 36336 CPL: 3 36337 CATEGORY: AVX512 36338 EXTENSION: AVX512EVEX 36339 ISA_SET: AVX512BW_256 36340 EXCEPTIONS: AVX512-E4 36341 REAL_OPCODE: Y 36342 ATTRIBUTES: MASKOP_EVEX 36343 PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 36344 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 36345 IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 36346 } 36347 36348 { 36349 ICLASS: VPADDUSW 36350 CPL: 3 36351 CATEGORY: AVX512 36352 EXTENSION: AVX512EVEX 36353 ISA_SET: AVX512BW_256 36354 EXCEPTIONS: AVX512-E4 36355 REAL_OPCODE: Y 36356 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36357 PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 36358 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 36359 IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 36360 } 36361 36362 36363 # EMITTING VPADDUSW (VPADDUSW-512-1) 36364 { 36365 ICLASS: VPADDUSW 36366 CPL: 3 36367 CATEGORY: AVX512 36368 EXTENSION: AVX512EVEX 36369 ISA_SET: AVX512BW_512 36370 EXCEPTIONS: AVX512-E4 36371 REAL_OPCODE: Y 36372 ATTRIBUTES: MASKOP_EVEX 36373 PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 36374 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 36375 IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 36376 } 36377 36378 { 36379 ICLASS: VPADDUSW 36380 CPL: 3 36381 CATEGORY: AVX512 36382 EXTENSION: AVX512EVEX 36383 ISA_SET: AVX512BW_512 36384 EXCEPTIONS: AVX512-E4 36385 REAL_OPCODE: Y 36386 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36387 PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 36388 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 36389 IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 36390 } 36391 36392 36393 # EMITTING VPADDW (VPADDW-128-1) 36394 { 36395 ICLASS: VPADDW 36396 CPL: 3 36397 CATEGORY: AVX512 36398 EXTENSION: AVX512EVEX 36399 ISA_SET: AVX512BW_128 36400 EXCEPTIONS: AVX512-E4 36401 REAL_OPCODE: Y 36402 ATTRIBUTES: MASKOP_EVEX 36403 PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 36404 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 36405 IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 36406 } 36407 36408 { 36409 ICLASS: VPADDW 36410 CPL: 3 36411 CATEGORY: AVX512 36412 EXTENSION: AVX512EVEX 36413 ISA_SET: AVX512BW_128 36414 EXCEPTIONS: AVX512-E4 36415 REAL_OPCODE: Y 36416 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36417 PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 36418 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 36419 IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 36420 } 36421 36422 36423 # EMITTING VPADDW (VPADDW-256-1) 36424 { 36425 ICLASS: VPADDW 36426 CPL: 3 36427 CATEGORY: AVX512 36428 EXTENSION: AVX512EVEX 36429 ISA_SET: AVX512BW_256 36430 EXCEPTIONS: AVX512-E4 36431 REAL_OPCODE: Y 36432 ATTRIBUTES: MASKOP_EVEX 36433 PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 36434 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 36435 IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 36436 } 36437 36438 { 36439 ICLASS: VPADDW 36440 CPL: 3 36441 CATEGORY: AVX512 36442 EXTENSION: AVX512EVEX 36443 ISA_SET: AVX512BW_256 36444 EXCEPTIONS: AVX512-E4 36445 REAL_OPCODE: Y 36446 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36447 PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 36448 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 36449 IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 36450 } 36451 36452 36453 # EMITTING VPADDW (VPADDW-512-1) 36454 { 36455 ICLASS: VPADDW 36456 CPL: 3 36457 CATEGORY: AVX512 36458 EXTENSION: AVX512EVEX 36459 ISA_SET: AVX512BW_512 36460 EXCEPTIONS: AVX512-E4 36461 REAL_OPCODE: Y 36462 ATTRIBUTES: MASKOP_EVEX 36463 PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 36464 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 36465 IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 36466 } 36467 36468 { 36469 ICLASS: VPADDW 36470 CPL: 3 36471 CATEGORY: AVX512 36472 EXTENSION: AVX512EVEX 36473 ISA_SET: AVX512BW_512 36474 EXCEPTIONS: AVX512-E4 36475 REAL_OPCODE: Y 36476 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36477 PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 36478 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 36479 IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 36480 } 36481 36482 36483 # EMITTING VPALIGNR (VPALIGNR-128-1) 36484 { 36485 ICLASS: VPALIGNR 36486 CPL: 3 36487 CATEGORY: AVX512 36488 EXTENSION: AVX512EVEX 36489 ISA_SET: AVX512BW_128 36490 EXCEPTIONS: AVX512-E4NF 36491 REAL_OPCODE: Y 36492 ATTRIBUTES: MASKOP_EVEX 36493 PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 UIMM8() 36494 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b 36495 IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 36496 } 36497 36498 { 36499 ICLASS: VPALIGNR 36500 CPL: 3 36501 CATEGORY: AVX512 36502 EXTENSION: AVX512EVEX 36503 ISA_SET: AVX512BW_128 36504 EXCEPTIONS: AVX512-E4NF 36505 REAL_OPCODE: Y 36506 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 36507 PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() 36508 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b 36509 IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 36510 } 36511 36512 36513 # EMITTING VPALIGNR (VPALIGNR-256-1) 36514 { 36515 ICLASS: VPALIGNR 36516 CPL: 3 36517 CATEGORY: AVX512 36518 EXTENSION: AVX512EVEX 36519 ISA_SET: AVX512BW_256 36520 EXCEPTIONS: AVX512-E4NF 36521 REAL_OPCODE: Y 36522 ATTRIBUTES: MASKOP_EVEX 36523 PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 UIMM8() 36524 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b 36525 IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 36526 } 36527 36528 { 36529 ICLASS: VPALIGNR 36530 CPL: 3 36531 CATEGORY: AVX512 36532 EXTENSION: AVX512EVEX 36533 ISA_SET: AVX512BW_256 36534 EXCEPTIONS: AVX512-E4NF 36535 REAL_OPCODE: Y 36536 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 36537 PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() 36538 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b 36539 IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 36540 } 36541 36542 36543 # EMITTING VPALIGNR (VPALIGNR-512-1) 36544 { 36545 ICLASS: VPALIGNR 36546 CPL: 3 36547 CATEGORY: AVX512 36548 EXTENSION: AVX512EVEX 36549 ISA_SET: AVX512BW_512 36550 EXCEPTIONS: AVX512-E4NF 36551 REAL_OPCODE: Y 36552 ATTRIBUTES: MASKOP_EVEX 36553 PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 UIMM8() 36554 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b 36555 IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 36556 } 36557 36558 { 36559 ICLASS: VPALIGNR 36560 CPL: 3 36561 CATEGORY: AVX512 36562 EXTENSION: AVX512EVEX 36563 ISA_SET: AVX512BW_512 36564 EXCEPTIONS: AVX512-E4NF 36565 REAL_OPCODE: Y 36566 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 36567 PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() 36568 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b 36569 IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 36570 } 36571 36572 36573 # EMITTING VPANDD (VPANDD-128-1) 36574 { 36575 ICLASS: VPANDD 36576 CPL: 3 36577 CATEGORY: LOGICAL 36578 EXTENSION: AVX512EVEX 36579 ISA_SET: AVX512F_128 36580 EXCEPTIONS: AVX512-E4 36581 REAL_OPCODE: Y 36582 ATTRIBUTES: MASKOP_EVEX 36583 PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 36584 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 36585 IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 36586 } 36587 36588 { 36589 ICLASS: VPANDD 36590 CPL: 3 36591 CATEGORY: LOGICAL 36592 EXTENSION: AVX512EVEX 36593 ISA_SET: AVX512F_128 36594 EXCEPTIONS: AVX512-E4 36595 REAL_OPCODE: Y 36596 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36597 PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 36598 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 36599 IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 36600 } 36601 36602 36603 # EMITTING VPANDD (VPANDD-256-1) 36604 { 36605 ICLASS: VPANDD 36606 CPL: 3 36607 CATEGORY: LOGICAL 36608 EXTENSION: AVX512EVEX 36609 ISA_SET: AVX512F_256 36610 EXCEPTIONS: AVX512-E4 36611 REAL_OPCODE: Y 36612 ATTRIBUTES: MASKOP_EVEX 36613 PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 36614 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 36615 IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 36616 } 36617 36618 { 36619 ICLASS: VPANDD 36620 CPL: 3 36621 CATEGORY: LOGICAL 36622 EXTENSION: AVX512EVEX 36623 ISA_SET: AVX512F_256 36624 EXCEPTIONS: AVX512-E4 36625 REAL_OPCODE: Y 36626 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36627 PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 36628 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 36629 IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 36630 } 36631 36632 36633 # EMITTING VPANDND (VPANDND-128-1) 36634 { 36635 ICLASS: VPANDND 36636 CPL: 3 36637 CATEGORY: LOGICAL 36638 EXTENSION: AVX512EVEX 36639 ISA_SET: AVX512F_128 36640 EXCEPTIONS: AVX512-E4 36641 REAL_OPCODE: Y 36642 ATTRIBUTES: MASKOP_EVEX 36643 PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 36644 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 36645 IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 36646 } 36647 36648 { 36649 ICLASS: VPANDND 36650 CPL: 3 36651 CATEGORY: LOGICAL 36652 EXTENSION: AVX512EVEX 36653 ISA_SET: AVX512F_128 36654 EXCEPTIONS: AVX512-E4 36655 REAL_OPCODE: Y 36656 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36657 PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 36658 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 36659 IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 36660 } 36661 36662 36663 # EMITTING VPANDND (VPANDND-256-1) 36664 { 36665 ICLASS: VPANDND 36666 CPL: 3 36667 CATEGORY: LOGICAL 36668 EXTENSION: AVX512EVEX 36669 ISA_SET: AVX512F_256 36670 EXCEPTIONS: AVX512-E4 36671 REAL_OPCODE: Y 36672 ATTRIBUTES: MASKOP_EVEX 36673 PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 36674 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 36675 IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 36676 } 36677 36678 { 36679 ICLASS: VPANDND 36680 CPL: 3 36681 CATEGORY: LOGICAL 36682 EXTENSION: AVX512EVEX 36683 ISA_SET: AVX512F_256 36684 EXCEPTIONS: AVX512-E4 36685 REAL_OPCODE: Y 36686 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36687 PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 36688 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 36689 IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 36690 } 36691 36692 36693 # EMITTING VPANDNQ (VPANDNQ-128-1) 36694 { 36695 ICLASS: VPANDNQ 36696 CPL: 3 36697 CATEGORY: LOGICAL 36698 EXTENSION: AVX512EVEX 36699 ISA_SET: AVX512F_128 36700 EXCEPTIONS: AVX512-E4 36701 REAL_OPCODE: Y 36702 ATTRIBUTES: MASKOP_EVEX 36703 PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 36704 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 36705 IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 36706 } 36707 36708 { 36709 ICLASS: VPANDNQ 36710 CPL: 3 36711 CATEGORY: LOGICAL 36712 EXTENSION: AVX512EVEX 36713 ISA_SET: AVX512F_128 36714 EXCEPTIONS: AVX512-E4 36715 REAL_OPCODE: Y 36716 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36717 PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 36718 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 36719 IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 36720 } 36721 36722 36723 # EMITTING VPANDNQ (VPANDNQ-256-1) 36724 { 36725 ICLASS: VPANDNQ 36726 CPL: 3 36727 CATEGORY: LOGICAL 36728 EXTENSION: AVX512EVEX 36729 ISA_SET: AVX512F_256 36730 EXCEPTIONS: AVX512-E4 36731 REAL_OPCODE: Y 36732 ATTRIBUTES: MASKOP_EVEX 36733 PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 36734 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 36735 IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 36736 } 36737 36738 { 36739 ICLASS: VPANDNQ 36740 CPL: 3 36741 CATEGORY: LOGICAL 36742 EXTENSION: AVX512EVEX 36743 ISA_SET: AVX512F_256 36744 EXCEPTIONS: AVX512-E4 36745 REAL_OPCODE: Y 36746 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36747 PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 36748 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 36749 IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 36750 } 36751 36752 36753 # EMITTING VPANDQ (VPANDQ-128-1) 36754 { 36755 ICLASS: VPANDQ 36756 CPL: 3 36757 CATEGORY: LOGICAL 36758 EXTENSION: AVX512EVEX 36759 ISA_SET: AVX512F_128 36760 EXCEPTIONS: AVX512-E4 36761 REAL_OPCODE: Y 36762 ATTRIBUTES: MASKOP_EVEX 36763 PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 36764 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 36765 IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 36766 } 36767 36768 { 36769 ICLASS: VPANDQ 36770 CPL: 3 36771 CATEGORY: LOGICAL 36772 EXTENSION: AVX512EVEX 36773 ISA_SET: AVX512F_128 36774 EXCEPTIONS: AVX512-E4 36775 REAL_OPCODE: Y 36776 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36777 PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 36778 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 36779 IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 36780 } 36781 36782 36783 # EMITTING VPANDQ (VPANDQ-256-1) 36784 { 36785 ICLASS: VPANDQ 36786 CPL: 3 36787 CATEGORY: LOGICAL 36788 EXTENSION: AVX512EVEX 36789 ISA_SET: AVX512F_256 36790 EXCEPTIONS: AVX512-E4 36791 REAL_OPCODE: Y 36792 ATTRIBUTES: MASKOP_EVEX 36793 PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 36794 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 36795 IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 36796 } 36797 36798 { 36799 ICLASS: VPANDQ 36800 CPL: 3 36801 CATEGORY: LOGICAL 36802 EXTENSION: AVX512EVEX 36803 ISA_SET: AVX512F_256 36804 EXCEPTIONS: AVX512-E4 36805 REAL_OPCODE: Y 36806 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 36807 PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 36808 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 36809 IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 36810 } 36811 36812 36813 # EMITTING VPAVGB (VPAVGB-128-1) 36814 { 36815 ICLASS: VPAVGB 36816 CPL: 3 36817 CATEGORY: AVX512 36818 EXTENSION: AVX512EVEX 36819 ISA_SET: AVX512BW_128 36820 EXCEPTIONS: AVX512-E4 36821 REAL_OPCODE: Y 36822 ATTRIBUTES: MASKOP_EVEX 36823 PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 36824 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 36825 IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 36826 } 36827 36828 { 36829 ICLASS: VPAVGB 36830 CPL: 3 36831 CATEGORY: AVX512 36832 EXTENSION: AVX512EVEX 36833 ISA_SET: AVX512BW_128 36834 EXCEPTIONS: AVX512-E4 36835 REAL_OPCODE: Y 36836 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36837 PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 36838 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 36839 IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 36840 } 36841 36842 36843 # EMITTING VPAVGB (VPAVGB-256-1) 36844 { 36845 ICLASS: VPAVGB 36846 CPL: 3 36847 CATEGORY: AVX512 36848 EXTENSION: AVX512EVEX 36849 ISA_SET: AVX512BW_256 36850 EXCEPTIONS: AVX512-E4 36851 REAL_OPCODE: Y 36852 ATTRIBUTES: MASKOP_EVEX 36853 PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 36854 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 36855 IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 36856 } 36857 36858 { 36859 ICLASS: VPAVGB 36860 CPL: 3 36861 CATEGORY: AVX512 36862 EXTENSION: AVX512EVEX 36863 ISA_SET: AVX512BW_256 36864 EXCEPTIONS: AVX512-E4 36865 REAL_OPCODE: Y 36866 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36867 PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 36868 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 36869 IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 36870 } 36871 36872 36873 # EMITTING VPAVGB (VPAVGB-512-1) 36874 { 36875 ICLASS: VPAVGB 36876 CPL: 3 36877 CATEGORY: AVX512 36878 EXTENSION: AVX512EVEX 36879 ISA_SET: AVX512BW_512 36880 EXCEPTIONS: AVX512-E4 36881 REAL_OPCODE: Y 36882 ATTRIBUTES: MASKOP_EVEX 36883 PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 36884 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 36885 IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 36886 } 36887 36888 { 36889 ICLASS: VPAVGB 36890 CPL: 3 36891 CATEGORY: AVX512 36892 EXTENSION: AVX512EVEX 36893 ISA_SET: AVX512BW_512 36894 EXCEPTIONS: AVX512-E4 36895 REAL_OPCODE: Y 36896 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36897 PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 36898 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 36899 IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 36900 } 36901 36902 36903 # EMITTING VPAVGW (VPAVGW-128-1) 36904 { 36905 ICLASS: VPAVGW 36906 CPL: 3 36907 CATEGORY: AVX512 36908 EXTENSION: AVX512EVEX 36909 ISA_SET: AVX512BW_128 36910 EXCEPTIONS: AVX512-E4 36911 REAL_OPCODE: Y 36912 ATTRIBUTES: MASKOP_EVEX 36913 PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 36914 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 36915 IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 36916 } 36917 36918 { 36919 ICLASS: VPAVGW 36920 CPL: 3 36921 CATEGORY: AVX512 36922 EXTENSION: AVX512EVEX 36923 ISA_SET: AVX512BW_128 36924 EXCEPTIONS: AVX512-E4 36925 REAL_OPCODE: Y 36926 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36927 PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 36928 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 36929 IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 36930 } 36931 36932 36933 # EMITTING VPAVGW (VPAVGW-256-1) 36934 { 36935 ICLASS: VPAVGW 36936 CPL: 3 36937 CATEGORY: AVX512 36938 EXTENSION: AVX512EVEX 36939 ISA_SET: AVX512BW_256 36940 EXCEPTIONS: AVX512-E4 36941 REAL_OPCODE: Y 36942 ATTRIBUTES: MASKOP_EVEX 36943 PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 36944 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 36945 IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 36946 } 36947 36948 { 36949 ICLASS: VPAVGW 36950 CPL: 3 36951 CATEGORY: AVX512 36952 EXTENSION: AVX512EVEX 36953 ISA_SET: AVX512BW_256 36954 EXCEPTIONS: AVX512-E4 36955 REAL_OPCODE: Y 36956 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36957 PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 36958 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 36959 IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 36960 } 36961 36962 36963 # EMITTING VPAVGW (VPAVGW-512-1) 36964 { 36965 ICLASS: VPAVGW 36966 CPL: 3 36967 CATEGORY: AVX512 36968 EXTENSION: AVX512EVEX 36969 ISA_SET: AVX512BW_512 36970 EXCEPTIONS: AVX512-E4 36971 REAL_OPCODE: Y 36972 ATTRIBUTES: MASKOP_EVEX 36973 PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 36974 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 36975 IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 36976 } 36977 36978 { 36979 ICLASS: VPAVGW 36980 CPL: 3 36981 CATEGORY: AVX512 36982 EXTENSION: AVX512EVEX 36983 ISA_SET: AVX512BW_512 36984 EXCEPTIONS: AVX512-E4 36985 REAL_OPCODE: Y 36986 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 36987 PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 36988 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 36989 IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 36990 } 36991 36992 36993 # EMITTING VPBLENDMB (VPBLENDMB-128-1) 36994 { 36995 ICLASS: VPBLENDMB 36996 CPL: 3 36997 CATEGORY: BLEND 36998 EXTENSION: AVX512EVEX 36999 ISA_SET: AVX512BW_128 37000 EXCEPTIONS: AVX512-E4 37001 REAL_OPCODE: Y 37002 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 37003 PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 37004 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 37005 IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 37006 } 37007 37008 { 37009 ICLASS: VPBLENDMB 37010 CPL: 3 37011 CATEGORY: BLEND 37012 EXTENSION: AVX512EVEX 37013 ISA_SET: AVX512BW_128 37014 EXCEPTIONS: AVX512-E4 37015 REAL_OPCODE: Y 37016 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL 37017 PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() 37018 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 37019 IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 37020 } 37021 37022 37023 # EMITTING VPBLENDMB (VPBLENDMB-256-1) 37024 { 37025 ICLASS: VPBLENDMB 37026 CPL: 3 37027 CATEGORY: BLEND 37028 EXTENSION: AVX512EVEX 37029 ISA_SET: AVX512BW_256 37030 EXCEPTIONS: AVX512-E4 37031 REAL_OPCODE: Y 37032 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 37033 PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 37034 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 37035 IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 37036 } 37037 37038 { 37039 ICLASS: VPBLENDMB 37040 CPL: 3 37041 CATEGORY: BLEND 37042 EXTENSION: AVX512EVEX 37043 ISA_SET: AVX512BW_256 37044 EXCEPTIONS: AVX512-E4 37045 REAL_OPCODE: Y 37046 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL 37047 PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() 37048 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 37049 IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 37050 } 37051 37052 37053 # EMITTING VPBLENDMB (VPBLENDMB-512-1) 37054 { 37055 ICLASS: VPBLENDMB 37056 CPL: 3 37057 CATEGORY: BLEND 37058 EXTENSION: AVX512EVEX 37059 ISA_SET: AVX512BW_512 37060 EXCEPTIONS: AVX512-E4 37061 REAL_OPCODE: Y 37062 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 37063 PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 37064 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 37065 IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 37066 } 37067 37068 { 37069 ICLASS: VPBLENDMB 37070 CPL: 3 37071 CATEGORY: BLEND 37072 EXTENSION: AVX512EVEX 37073 ISA_SET: AVX512BW_512 37074 EXCEPTIONS: AVX512-E4 37075 REAL_OPCODE: Y 37076 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL 37077 PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() 37078 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 37079 IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 37080 } 37081 37082 37083 # EMITTING VPBLENDMD (VPBLENDMD-128-1) 37084 { 37085 ICLASS: VPBLENDMD 37086 CPL: 3 37087 CATEGORY: BLEND 37088 EXTENSION: AVX512EVEX 37089 ISA_SET: AVX512F_128 37090 EXCEPTIONS: AVX512-E4 37091 REAL_OPCODE: Y 37092 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 37093 PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 37094 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 37095 IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 37096 } 37097 37098 { 37099 ICLASS: VPBLENDMD 37100 CPL: 3 37101 CATEGORY: BLEND 37102 EXTENSION: AVX512EVEX 37103 ISA_SET: AVX512F_128 37104 EXCEPTIONS: AVX512-E4 37105 REAL_OPCODE: Y 37106 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL 37107 PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 37108 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 37109 IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 37110 } 37111 37112 37113 # EMITTING VPBLENDMD (VPBLENDMD-256-1) 37114 { 37115 ICLASS: VPBLENDMD 37116 CPL: 3 37117 CATEGORY: BLEND 37118 EXTENSION: AVX512EVEX 37119 ISA_SET: AVX512F_256 37120 EXCEPTIONS: AVX512-E4 37121 REAL_OPCODE: Y 37122 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 37123 PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 37124 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 37125 IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 37126 } 37127 37128 { 37129 ICLASS: VPBLENDMD 37130 CPL: 3 37131 CATEGORY: BLEND 37132 EXTENSION: AVX512EVEX 37133 ISA_SET: AVX512F_256 37134 EXCEPTIONS: AVX512-E4 37135 REAL_OPCODE: Y 37136 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL 37137 PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 37138 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 37139 IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 37140 } 37141 37142 37143 # EMITTING VPBLENDMQ (VPBLENDMQ-128-1) 37144 { 37145 ICLASS: VPBLENDMQ 37146 CPL: 3 37147 CATEGORY: BLEND 37148 EXTENSION: AVX512EVEX 37149 ISA_SET: AVX512F_128 37150 EXCEPTIONS: AVX512-E4 37151 REAL_OPCODE: Y 37152 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 37153 PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 37154 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 37155 IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 37156 } 37157 37158 { 37159 ICLASS: VPBLENDMQ 37160 CPL: 3 37161 CATEGORY: BLEND 37162 EXTENSION: AVX512EVEX 37163 ISA_SET: AVX512F_128 37164 EXCEPTIONS: AVX512-E4 37165 REAL_OPCODE: Y 37166 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL 37167 PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 37168 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 37169 IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 37170 } 37171 37172 37173 # EMITTING VPBLENDMQ (VPBLENDMQ-256-1) 37174 { 37175 ICLASS: VPBLENDMQ 37176 CPL: 3 37177 CATEGORY: BLEND 37178 EXTENSION: AVX512EVEX 37179 ISA_SET: AVX512F_256 37180 EXCEPTIONS: AVX512-E4 37181 REAL_OPCODE: Y 37182 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 37183 PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 37184 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 37185 IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 37186 } 37187 37188 { 37189 ICLASS: VPBLENDMQ 37190 CPL: 3 37191 CATEGORY: BLEND 37192 EXTENSION: AVX512EVEX 37193 ISA_SET: AVX512F_256 37194 EXCEPTIONS: AVX512-E4 37195 REAL_OPCODE: Y 37196 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL 37197 PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 37198 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 37199 IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 37200 } 37201 37202 37203 # EMITTING VPBLENDMW (VPBLENDMW-128-1) 37204 { 37205 ICLASS: VPBLENDMW 37206 CPL: 3 37207 CATEGORY: BLEND 37208 EXTENSION: AVX512EVEX 37209 ISA_SET: AVX512BW_128 37210 EXCEPTIONS: AVX512-E4 37211 REAL_OPCODE: Y 37212 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 37213 PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 37214 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 37215 IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 37216 } 37217 37218 { 37219 ICLASS: VPBLENDMW 37220 CPL: 3 37221 CATEGORY: BLEND 37222 EXTENSION: AVX512EVEX 37223 ISA_SET: AVX512BW_128 37224 EXCEPTIONS: AVX512-E4 37225 REAL_OPCODE: Y 37226 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL 37227 PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 37228 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 37229 IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 37230 } 37231 37232 37233 # EMITTING VPBLENDMW (VPBLENDMW-256-1) 37234 { 37235 ICLASS: VPBLENDMW 37236 CPL: 3 37237 CATEGORY: BLEND 37238 EXTENSION: AVX512EVEX 37239 ISA_SET: AVX512BW_256 37240 EXCEPTIONS: AVX512-E4 37241 REAL_OPCODE: Y 37242 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 37243 PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 37244 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 37245 IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 37246 } 37247 37248 { 37249 ICLASS: VPBLENDMW 37250 CPL: 3 37251 CATEGORY: BLEND 37252 EXTENSION: AVX512EVEX 37253 ISA_SET: AVX512BW_256 37254 EXCEPTIONS: AVX512-E4 37255 REAL_OPCODE: Y 37256 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL 37257 PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 37258 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 37259 IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 37260 } 37261 37262 37263 # EMITTING VPBLENDMW (VPBLENDMW-512-1) 37264 { 37265 ICLASS: VPBLENDMW 37266 CPL: 3 37267 CATEGORY: BLEND 37268 EXTENSION: AVX512EVEX 37269 ISA_SET: AVX512BW_512 37270 EXCEPTIONS: AVX512-E4 37271 REAL_OPCODE: Y 37272 ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL 37273 PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 37274 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 37275 IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 37276 } 37277 37278 { 37279 ICLASS: VPBLENDMW 37280 CPL: 3 37281 CATEGORY: BLEND 37282 EXTENSION: AVX512EVEX 37283 ISA_SET: AVX512BW_512 37284 EXCEPTIONS: AVX512-E4 37285 REAL_OPCODE: Y 37286 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL 37287 PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 37288 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 37289 IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 37290 } 37291 37292 37293 # EMITTING VPBROADCASTB (VPBROADCASTB-128-1) 37294 { 37295 ICLASS: VPBROADCASTB 37296 CPL: 3 37297 CATEGORY: BROADCAST 37298 EXTENSION: AVX512EVEX 37299 ISA_SET: AVX512BW_128 37300 EXCEPTIONS: AVX512-E6 37301 REAL_OPCODE: Y 37302 ATTRIBUTES: MASKOP_EVEX 37303 PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 37304 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO16_8 37305 IFORM: VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 37306 } 37307 37308 { 37309 ICLASS: VPBROADCASTB 37310 CPL: 3 37311 CATEGORY: BROADCAST 37312 EXTENSION: AVX512EVEX 37313 ISA_SET: AVX512BW_128 37314 EXCEPTIONS: AVX512-E6 37315 REAL_OPCODE: Y 37316 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE 37317 PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() 37318 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 37319 IFORM: VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 37320 } 37321 37322 37323 # EMITTING VPBROADCASTB (VPBROADCASTB-128-2) 37324 { 37325 ICLASS: VPBROADCASTB 37326 CPL: 3 37327 CATEGORY: BROADCAST 37328 EXTENSION: AVX512EVEX 37329 ISA_SET: AVX512BW_128 37330 EXCEPTIONS: AVX512-E7NM 37331 REAL_OPCODE: Y 37332 ATTRIBUTES: MASKOP_EVEX 37333 PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 37334 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO16_8 37335 IFORM: VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 37336 } 37337 37338 37339 # EMITTING VPBROADCASTB (VPBROADCASTB-256-1) 37340 { 37341 ICLASS: VPBROADCASTB 37342 CPL: 3 37343 CATEGORY: BROADCAST 37344 EXTENSION: AVX512EVEX 37345 ISA_SET: AVX512BW_256 37346 EXCEPTIONS: AVX512-E6 37347 REAL_OPCODE: Y 37348 ATTRIBUTES: MASKOP_EVEX 37349 PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 37350 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO32_8 37351 IFORM: VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 37352 } 37353 37354 { 37355 ICLASS: VPBROADCASTB 37356 CPL: 3 37357 CATEGORY: BROADCAST 37358 EXTENSION: AVX512EVEX 37359 ISA_SET: AVX512BW_256 37360 EXCEPTIONS: AVX512-E6 37361 REAL_OPCODE: Y 37362 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE 37363 PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() 37364 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 37365 IFORM: VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 37366 } 37367 37368 37369 # EMITTING VPBROADCASTB (VPBROADCASTB-256-2) 37370 { 37371 ICLASS: VPBROADCASTB 37372 CPL: 3 37373 CATEGORY: BROADCAST 37374 EXTENSION: AVX512EVEX 37375 ISA_SET: AVX512BW_256 37376 EXCEPTIONS: AVX512-E7NM 37377 REAL_OPCODE: Y 37378 ATTRIBUTES: MASKOP_EVEX 37379 PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 37380 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO32_8 37381 IFORM: VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 37382 } 37383 37384 37385 # EMITTING VPBROADCASTB (VPBROADCASTB-512-1) 37386 { 37387 ICLASS: VPBROADCASTB 37388 CPL: 3 37389 CATEGORY: BROADCAST 37390 EXTENSION: AVX512EVEX 37391 ISA_SET: AVX512BW_512 37392 EXCEPTIONS: AVX512-E6 37393 REAL_OPCODE: Y 37394 ATTRIBUTES: MASKOP_EVEX 37395 PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 37396 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO64_8 37397 IFORM: VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 37398 } 37399 37400 { 37401 ICLASS: VPBROADCASTB 37402 CPL: 3 37403 CATEGORY: BROADCAST 37404 EXTENSION: AVX512EVEX 37405 ISA_SET: AVX512BW_512 37406 EXCEPTIONS: AVX512-E6 37407 REAL_OPCODE: Y 37408 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE 37409 PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() 37410 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO64_8 37411 IFORM: VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 37412 } 37413 37414 37415 # EMITTING VPBROADCASTB (VPBROADCASTB-512-2) 37416 { 37417 ICLASS: VPBROADCASTB 37418 CPL: 3 37419 CATEGORY: BROADCAST 37420 EXTENSION: AVX512EVEX 37421 ISA_SET: AVX512BW_512 37422 EXCEPTIONS: AVX512-E7NM 37423 REAL_OPCODE: Y 37424 ATTRIBUTES: MASKOP_EVEX 37425 PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 37426 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO64_8 37427 IFORM: VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 37428 } 37429 37430 37431 # EMITTING VPBROADCASTD (VPBROADCASTD-128-1) 37432 { 37433 ICLASS: VPBROADCASTD 37434 CPL: 3 37435 CATEGORY: BROADCAST 37436 EXTENSION: AVX512EVEX 37437 ISA_SET: AVX512F_128 37438 EXCEPTIONS: AVX512-E6 37439 REAL_OPCODE: Y 37440 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 37441 PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() 37442 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 37443 IFORM: VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 37444 } 37445 37446 37447 # EMITTING VPBROADCASTD (VPBROADCASTD-128-2) 37448 { 37449 ICLASS: VPBROADCASTD 37450 CPL: 3 37451 CATEGORY: BROADCAST 37452 EXTENSION: AVX512EVEX 37453 ISA_SET: AVX512F_128 37454 EXCEPTIONS: AVX512-E6 37455 REAL_OPCODE: Y 37456 ATTRIBUTES: MASKOP_EVEX 37457 PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 37458 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO4_32 37459 IFORM: VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 37460 } 37461 37462 37463 # EMITTING VPBROADCASTD (VPBROADCASTD-128-3) 37464 { 37465 ICLASS: VPBROADCASTD 37466 CPL: 3 37467 CATEGORY: BROADCAST 37468 EXTENSION: AVX512EVEX 37469 ISA_SET: AVX512F_128 37470 EXCEPTIONS: AVX512-E7NM 37471 REAL_OPCODE: Y 37472 ATTRIBUTES: MASKOP_EVEX 37473 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR 37474 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32 37475 IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 37476 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR 37477 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32 37478 IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 37479 } 37480 37481 37482 # EMITTING VPBROADCASTD (VPBROADCASTD-256-1) 37483 { 37484 ICLASS: VPBROADCASTD 37485 CPL: 3 37486 CATEGORY: BROADCAST 37487 EXTENSION: AVX512EVEX 37488 ISA_SET: AVX512F_256 37489 EXCEPTIONS: AVX512-E6 37490 REAL_OPCODE: Y 37491 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 37492 PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() 37493 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 37494 IFORM: VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 37495 } 37496 37497 37498 # EMITTING VPBROADCASTD (VPBROADCASTD-256-2) 37499 { 37500 ICLASS: VPBROADCASTD 37501 CPL: 3 37502 CATEGORY: BROADCAST 37503 EXTENSION: AVX512EVEX 37504 ISA_SET: AVX512F_256 37505 EXCEPTIONS: AVX512-E6 37506 REAL_OPCODE: Y 37507 ATTRIBUTES: MASKOP_EVEX 37508 PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 37509 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO8_32 37510 IFORM: VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 37511 } 37512 37513 37514 # EMITTING VPBROADCASTD (VPBROADCASTD-256-3) 37515 { 37516 ICLASS: VPBROADCASTD 37517 CPL: 3 37518 CATEGORY: BROADCAST 37519 EXTENSION: AVX512EVEX 37520 ISA_SET: AVX512F_256 37521 EXCEPTIONS: AVX512-E7NM 37522 REAL_OPCODE: Y 37523 ATTRIBUTES: MASKOP_EVEX 37524 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 not64 NOEVSR 37525 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32 37526 IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 37527 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 mode64 W0 NOEVSR 37528 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32 37529 IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 37530 } 37531 37532 37533 # EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-128-1) 37534 { 37535 ICLASS: VPBROADCASTMB2Q 37536 CPL: 3 37537 CATEGORY: BROADCAST 37538 EXTENSION: AVX512EVEX 37539 ISA_SET: AVX512CD_128 37540 EXCEPTIONS: AVX512-E6NF 37541 REAL_OPCODE: Y 37542 PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 37543 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO2_8 37544 IFORM: VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 37545 } 37546 37547 37548 # EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-256-1) 37549 { 37550 ICLASS: VPBROADCASTMB2Q 37551 CPL: 3 37552 CATEGORY: BROADCAST 37553 EXTENSION: AVX512EVEX 37554 ISA_SET: AVX512CD_256 37555 EXCEPTIONS: AVX512-E6NF 37556 REAL_OPCODE: Y 37557 PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 37558 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO4_8 37559 IFORM: VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 37560 } 37561 37562 37563 # EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-128-1) 37564 { 37565 ICLASS: VPBROADCASTMW2D 37566 CPL: 3 37567 CATEGORY: BROADCAST 37568 EXTENSION: AVX512EVEX 37569 ISA_SET: AVX512CD_128 37570 EXCEPTIONS: AVX512-E6NF 37571 REAL_OPCODE: Y 37572 PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 37573 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO4_16 37574 IFORM: VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 37575 } 37576 37577 37578 # EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-256-1) 37579 { 37580 ICLASS: VPBROADCASTMW2D 37581 CPL: 3 37582 CATEGORY: BROADCAST 37583 EXTENSION: AVX512EVEX 37584 ISA_SET: AVX512CD_256 37585 EXCEPTIONS: AVX512-E6NF 37586 REAL_OPCODE: Y 37587 PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 37588 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO8_16 37589 IFORM: VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 37590 } 37591 37592 37593 # EMITTING VPBROADCASTQ (VPBROADCASTQ-128-1) 37594 { 37595 ICLASS: VPBROADCASTQ 37596 CPL: 3 37597 CATEGORY: BROADCAST 37598 EXTENSION: AVX512EVEX 37599 ISA_SET: AVX512F_128 37600 EXCEPTIONS: AVX512-E6 37601 REAL_OPCODE: Y 37602 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 37603 PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() 37604 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 37605 IFORM: VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 37606 } 37607 37608 37609 # EMITTING VPBROADCASTQ (VPBROADCASTQ-128-2) 37610 { 37611 ICLASS: VPBROADCASTQ 37612 CPL: 3 37613 CATEGORY: BROADCAST 37614 EXTENSION: AVX512EVEX 37615 ISA_SET: AVX512F_128 37616 EXCEPTIONS: AVX512-E6 37617 REAL_OPCODE: Y 37618 ATTRIBUTES: MASKOP_EVEX 37619 PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 37620 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO2_64 37621 IFORM: VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 37622 } 37623 37624 37625 # EMITTING VPBROADCASTQ (VPBROADCASTQ-128-3) 37626 { 37627 ICLASS: VPBROADCASTQ 37628 CPL: 3 37629 CATEGORY: BROADCAST 37630 EXTENSION: AVX512EVEX 37631 ISA_SET: AVX512F_128 37632 EXCEPTIONS: AVX512-E7NM 37633 REAL_OPCODE: Y 37634 ATTRIBUTES: MASKOP_EVEX 37635 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR 37636 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO2_64 37637 IFORM: VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 37638 } 37639 37640 37641 # EMITTING VPBROADCASTQ (VPBROADCASTQ-256-1) 37642 { 37643 ICLASS: VPBROADCASTQ 37644 CPL: 3 37645 CATEGORY: BROADCAST 37646 EXTENSION: AVX512EVEX 37647 ISA_SET: AVX512F_256 37648 EXCEPTIONS: AVX512-E6 37649 REAL_OPCODE: Y 37650 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 37651 PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() 37652 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 37653 IFORM: VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 37654 } 37655 37656 37657 # EMITTING VPBROADCASTQ (VPBROADCASTQ-256-2) 37658 { 37659 ICLASS: VPBROADCASTQ 37660 CPL: 3 37661 CATEGORY: BROADCAST 37662 EXTENSION: AVX512EVEX 37663 ISA_SET: AVX512F_256 37664 EXCEPTIONS: AVX512-E6 37665 REAL_OPCODE: Y 37666 ATTRIBUTES: MASKOP_EVEX 37667 PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 37668 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO4_64 37669 IFORM: VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 37670 } 37671 37672 37673 # EMITTING VPBROADCASTQ (VPBROADCASTQ-256-3) 37674 { 37675 ICLASS: VPBROADCASTQ 37676 CPL: 3 37677 CATEGORY: BROADCAST 37678 EXTENSION: AVX512EVEX 37679 ISA_SET: AVX512F_256 37680 EXCEPTIONS: AVX512-E7NM 37681 REAL_OPCODE: Y 37682 ATTRIBUTES: MASKOP_EVEX 37683 PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 mode64 NOEVSR 37684 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO4_64 37685 IFORM: VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 37686 } 37687 37688 37689 # EMITTING VPBROADCASTW (VPBROADCASTW-128-1) 37690 { 37691 ICLASS: VPBROADCASTW 37692 CPL: 3 37693 CATEGORY: BROADCAST 37694 EXTENSION: AVX512EVEX 37695 ISA_SET: AVX512BW_128 37696 EXCEPTIONS: AVX512-E6 37697 REAL_OPCODE: Y 37698 ATTRIBUTES: MASKOP_EVEX 37699 PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 37700 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO8_16 37701 IFORM: VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 37702 } 37703 37704 { 37705 ICLASS: VPBROADCASTW 37706 CPL: 3 37707 CATEGORY: BROADCAST 37708 EXTENSION: AVX512EVEX 37709 ISA_SET: AVX512BW_128 37710 EXCEPTIONS: AVX512-E6 37711 REAL_OPCODE: Y 37712 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD 37713 PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() 37714 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO8_16 37715 IFORM: VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 37716 } 37717 37718 37719 # EMITTING VPBROADCASTW (VPBROADCASTW-128-2) 37720 { 37721 ICLASS: VPBROADCASTW 37722 CPL: 3 37723 CATEGORY: BROADCAST 37724 EXTENSION: AVX512EVEX 37725 ISA_SET: AVX512BW_128 37726 EXCEPTIONS: AVX512-E7NM 37727 REAL_OPCODE: Y 37728 ATTRIBUTES: MASKOP_EVEX 37729 PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 37730 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO8_16 37731 IFORM: VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 37732 } 37733 37734 37735 # EMITTING VPBROADCASTW (VPBROADCASTW-256-1) 37736 { 37737 ICLASS: VPBROADCASTW 37738 CPL: 3 37739 CATEGORY: BROADCAST 37740 EXTENSION: AVX512EVEX 37741 ISA_SET: AVX512BW_256 37742 EXCEPTIONS: AVX512-E6 37743 REAL_OPCODE: Y 37744 ATTRIBUTES: MASKOP_EVEX 37745 PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 37746 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO16_16 37747 IFORM: VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 37748 } 37749 37750 { 37751 ICLASS: VPBROADCASTW 37752 CPL: 3 37753 CATEGORY: BROADCAST 37754 EXTENSION: AVX512EVEX 37755 ISA_SET: AVX512BW_256 37756 EXCEPTIONS: AVX512-E6 37757 REAL_OPCODE: Y 37758 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD 37759 PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() 37760 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO16_16 37761 IFORM: VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 37762 } 37763 37764 37765 # EMITTING VPBROADCASTW (VPBROADCASTW-256-2) 37766 { 37767 ICLASS: VPBROADCASTW 37768 CPL: 3 37769 CATEGORY: BROADCAST 37770 EXTENSION: AVX512EVEX 37771 ISA_SET: AVX512BW_256 37772 EXCEPTIONS: AVX512-E7NM 37773 REAL_OPCODE: Y 37774 ATTRIBUTES: MASKOP_EVEX 37775 PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 37776 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO16_16 37777 IFORM: VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 37778 } 37779 37780 37781 # EMITTING VPBROADCASTW (VPBROADCASTW-512-1) 37782 { 37783 ICLASS: VPBROADCASTW 37784 CPL: 3 37785 CATEGORY: BROADCAST 37786 EXTENSION: AVX512EVEX 37787 ISA_SET: AVX512BW_512 37788 EXCEPTIONS: AVX512-E6 37789 REAL_OPCODE: Y 37790 ATTRIBUTES: MASKOP_EVEX 37791 PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 37792 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO32_16 37793 IFORM: VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 37794 } 37795 37796 { 37797 ICLASS: VPBROADCASTW 37798 CPL: 3 37799 CATEGORY: BROADCAST 37800 EXTENSION: AVX512EVEX 37801 ISA_SET: AVX512BW_512 37802 EXCEPTIONS: AVX512-E6 37803 REAL_OPCODE: Y 37804 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD 37805 PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() 37806 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO32_16 37807 IFORM: VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 37808 } 37809 37810 37811 # EMITTING VPBROADCASTW (VPBROADCASTW-512-2) 37812 { 37813 ICLASS: VPBROADCASTW 37814 CPL: 3 37815 CATEGORY: BROADCAST 37816 EXTENSION: AVX512EVEX 37817 ISA_SET: AVX512BW_512 37818 EXCEPTIONS: AVX512-E7NM 37819 REAL_OPCODE: Y 37820 ATTRIBUTES: MASKOP_EVEX 37821 PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 37822 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO32_16 37823 IFORM: VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 37824 } 37825 37826 37827 # EMITTING VPCMPB (VPCMPB-128-1) 37828 { 37829 ICLASS: VPCMPB 37830 CPL: 3 37831 CATEGORY: AVX512 37832 EXTENSION: AVX512EVEX 37833 ISA_SET: AVX512BW_128 37834 EXCEPTIONS: AVX512-E4 37835 REAL_OPCODE: Y 37836 ATTRIBUTES: MASKOP_EVEX 37837 PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() 37838 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 IMM0:r:b 37839 IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 37840 } 37841 37842 { 37843 ICLASS: VPCMPB 37844 CPL: 3 37845 CATEGORY: AVX512 37846 EXTENSION: AVX512EVEX 37847 ISA_SET: AVX512BW_128 37848 EXCEPTIONS: AVX512-E4 37849 REAL_OPCODE: Y 37850 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 37851 PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 37852 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b 37853 IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 37854 } 37855 37856 37857 # EMITTING VPCMPB (VPCMPB-256-1) 37858 { 37859 ICLASS: VPCMPB 37860 CPL: 3 37861 CATEGORY: AVX512 37862 EXTENSION: AVX512EVEX 37863 ISA_SET: AVX512BW_256 37864 EXCEPTIONS: AVX512-E4 37865 REAL_OPCODE: Y 37866 ATTRIBUTES: MASKOP_EVEX 37867 PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() 37868 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 IMM0:r:b 37869 IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 37870 } 37871 37872 { 37873 ICLASS: VPCMPB 37874 CPL: 3 37875 CATEGORY: AVX512 37876 EXTENSION: AVX512EVEX 37877 ISA_SET: AVX512BW_256 37878 EXCEPTIONS: AVX512-E4 37879 REAL_OPCODE: Y 37880 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 37881 PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 37882 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 IMM0:r:b 37883 IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 37884 } 37885 37886 37887 # EMITTING VPCMPB (VPCMPB-512-1) 37888 { 37889 ICLASS: VPCMPB 37890 CPL: 3 37891 CATEGORY: AVX512 37892 EXTENSION: AVX512EVEX 37893 ISA_SET: AVX512BW_512 37894 EXCEPTIONS: AVX512-E4 37895 REAL_OPCODE: Y 37896 ATTRIBUTES: MASKOP_EVEX 37897 PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() 37898 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 IMM0:r:b 37899 IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 37900 } 37901 37902 { 37903 ICLASS: VPCMPB 37904 CPL: 3 37905 CATEGORY: AVX512 37906 EXTENSION: AVX512EVEX 37907 ISA_SET: AVX512BW_512 37908 EXCEPTIONS: AVX512-E4 37909 REAL_OPCODE: Y 37910 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 37911 PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 37912 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 IMM0:r:b 37913 IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 37914 } 37915 37916 37917 # EMITTING VPCMPD (VPCMPD-128-1) 37918 { 37919 ICLASS: VPCMPD 37920 CPL: 3 37921 CATEGORY: AVX512 37922 EXTENSION: AVX512EVEX 37923 ISA_SET: AVX512F_128 37924 EXCEPTIONS: AVX512-E4 37925 REAL_OPCODE: Y 37926 ATTRIBUTES: MASKOP_EVEX 37927 PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() 37928 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 IMM0:r:b 37929 IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 37930 } 37931 37932 { 37933 ICLASS: VPCMPD 37934 CPL: 3 37935 CATEGORY: AVX512 37936 EXTENSION: AVX512EVEX 37937 ISA_SET: AVX512F_128 37938 EXCEPTIONS: AVX512-E4 37939 REAL_OPCODE: Y 37940 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37941 PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 37942 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b 37943 IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 37944 } 37945 37946 37947 # EMITTING VPCMPD (VPCMPD-256-1) 37948 { 37949 ICLASS: VPCMPD 37950 CPL: 3 37951 CATEGORY: AVX512 37952 EXTENSION: AVX512EVEX 37953 ISA_SET: AVX512F_256 37954 EXCEPTIONS: AVX512-E4 37955 REAL_OPCODE: Y 37956 ATTRIBUTES: MASKOP_EVEX 37957 PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() 37958 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 IMM0:r:b 37959 IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 37960 } 37961 37962 { 37963 ICLASS: VPCMPD 37964 CPL: 3 37965 CATEGORY: AVX512 37966 EXTENSION: AVX512EVEX 37967 ISA_SET: AVX512F_256 37968 EXCEPTIONS: AVX512-E4 37969 REAL_OPCODE: Y 37970 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 37971 PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 37972 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b 37973 IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 37974 } 37975 37976 37977 # EMITTING VPCMPEQB (VPCMPEQB-128-1) 37978 { 37979 ICLASS: VPCMPEQB 37980 CPL: 3 37981 CATEGORY: AVX512 37982 EXTENSION: AVX512EVEX 37983 ISA_SET: AVX512BW_128 37984 EXCEPTIONS: AVX512-E4 37985 REAL_OPCODE: Y 37986 ATTRIBUTES: MASKOP_EVEX 37987 PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 37988 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 37989 IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 37990 } 37991 37992 { 37993 ICLASS: VPCMPEQB 37994 CPL: 3 37995 CATEGORY: AVX512 37996 EXTENSION: AVX512EVEX 37997 ISA_SET: AVX512BW_128 37998 EXCEPTIONS: AVX512-E4 37999 REAL_OPCODE: Y 38000 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38001 PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 38002 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 38003 IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 38004 } 38005 38006 38007 # EMITTING VPCMPEQB (VPCMPEQB-256-1) 38008 { 38009 ICLASS: VPCMPEQB 38010 CPL: 3 38011 CATEGORY: AVX512 38012 EXTENSION: AVX512EVEX 38013 ISA_SET: AVX512BW_256 38014 EXCEPTIONS: AVX512-E4 38015 REAL_OPCODE: Y 38016 ATTRIBUTES: MASKOP_EVEX 38017 PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 38018 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 38019 IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 38020 } 38021 38022 { 38023 ICLASS: VPCMPEQB 38024 CPL: 3 38025 CATEGORY: AVX512 38026 EXTENSION: AVX512EVEX 38027 ISA_SET: AVX512BW_256 38028 EXCEPTIONS: AVX512-E4 38029 REAL_OPCODE: Y 38030 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38031 PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 38032 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 38033 IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 38034 } 38035 38036 38037 # EMITTING VPCMPEQB (VPCMPEQB-512-1) 38038 { 38039 ICLASS: VPCMPEQB 38040 CPL: 3 38041 CATEGORY: AVX512 38042 EXTENSION: AVX512EVEX 38043 ISA_SET: AVX512BW_512 38044 EXCEPTIONS: AVX512-E4 38045 REAL_OPCODE: Y 38046 ATTRIBUTES: MASKOP_EVEX 38047 PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 38048 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 38049 IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 38050 } 38051 38052 { 38053 ICLASS: VPCMPEQB 38054 CPL: 3 38055 CATEGORY: AVX512 38056 EXTENSION: AVX512EVEX 38057 ISA_SET: AVX512BW_512 38058 EXCEPTIONS: AVX512-E4 38059 REAL_OPCODE: Y 38060 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38061 PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 38062 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 38063 IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 38064 } 38065 38066 38067 # EMITTING VPCMPEQD (VPCMPEQD-128-1) 38068 { 38069 ICLASS: VPCMPEQD 38070 CPL: 3 38071 CATEGORY: AVX512 38072 EXTENSION: AVX512EVEX 38073 ISA_SET: AVX512F_128 38074 EXCEPTIONS: AVX512-E4 38075 REAL_OPCODE: Y 38076 ATTRIBUTES: MASKOP_EVEX 38077 PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 38078 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 38079 IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 38080 } 38081 38082 { 38083 ICLASS: VPCMPEQD 38084 CPL: 3 38085 CATEGORY: AVX512 38086 EXTENSION: AVX512EVEX 38087 ISA_SET: AVX512F_128 38088 EXCEPTIONS: AVX512-E4 38089 REAL_OPCODE: Y 38090 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38091 PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 38092 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 38093 IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 38094 } 38095 38096 38097 # EMITTING VPCMPEQD (VPCMPEQD-256-1) 38098 { 38099 ICLASS: VPCMPEQD 38100 CPL: 3 38101 CATEGORY: AVX512 38102 EXTENSION: AVX512EVEX 38103 ISA_SET: AVX512F_256 38104 EXCEPTIONS: AVX512-E4 38105 REAL_OPCODE: Y 38106 ATTRIBUTES: MASKOP_EVEX 38107 PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 38108 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 38109 IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 38110 } 38111 38112 { 38113 ICLASS: VPCMPEQD 38114 CPL: 3 38115 CATEGORY: AVX512 38116 EXTENSION: AVX512EVEX 38117 ISA_SET: AVX512F_256 38118 EXCEPTIONS: AVX512-E4 38119 REAL_OPCODE: Y 38120 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38121 PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 38122 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 38123 IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 38124 } 38125 38126 38127 # EMITTING VPCMPEQQ (VPCMPEQQ-128-1) 38128 { 38129 ICLASS: VPCMPEQQ 38130 CPL: 3 38131 CATEGORY: AVX512 38132 EXTENSION: AVX512EVEX 38133 ISA_SET: AVX512F_128 38134 EXCEPTIONS: AVX512-E4 38135 REAL_OPCODE: Y 38136 ATTRIBUTES: MASKOP_EVEX 38137 PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 38138 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 38139 IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 38140 } 38141 38142 { 38143 ICLASS: VPCMPEQQ 38144 CPL: 3 38145 CATEGORY: AVX512 38146 EXTENSION: AVX512EVEX 38147 ISA_SET: AVX512F_128 38148 EXCEPTIONS: AVX512-E4 38149 REAL_OPCODE: Y 38150 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38151 PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 38152 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 38153 IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 38154 } 38155 38156 38157 # EMITTING VPCMPEQQ (VPCMPEQQ-256-1) 38158 { 38159 ICLASS: VPCMPEQQ 38160 CPL: 3 38161 CATEGORY: AVX512 38162 EXTENSION: AVX512EVEX 38163 ISA_SET: AVX512F_256 38164 EXCEPTIONS: AVX512-E4 38165 REAL_OPCODE: Y 38166 ATTRIBUTES: MASKOP_EVEX 38167 PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 38168 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 38169 IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 38170 } 38171 38172 { 38173 ICLASS: VPCMPEQQ 38174 CPL: 3 38175 CATEGORY: AVX512 38176 EXTENSION: AVX512EVEX 38177 ISA_SET: AVX512F_256 38178 EXCEPTIONS: AVX512-E4 38179 REAL_OPCODE: Y 38180 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38181 PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 38182 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 38183 IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 38184 } 38185 38186 38187 # EMITTING VPCMPEQW (VPCMPEQW-128-1) 38188 { 38189 ICLASS: VPCMPEQW 38190 CPL: 3 38191 CATEGORY: AVX512 38192 EXTENSION: AVX512EVEX 38193 ISA_SET: AVX512BW_128 38194 EXCEPTIONS: AVX512-E4 38195 REAL_OPCODE: Y 38196 ATTRIBUTES: MASKOP_EVEX 38197 PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 38198 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 38199 IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 38200 } 38201 38202 { 38203 ICLASS: VPCMPEQW 38204 CPL: 3 38205 CATEGORY: AVX512 38206 EXTENSION: AVX512EVEX 38207 ISA_SET: AVX512BW_128 38208 EXCEPTIONS: AVX512-E4 38209 REAL_OPCODE: Y 38210 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38211 PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 38212 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 38213 IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 38214 } 38215 38216 38217 # EMITTING VPCMPEQW (VPCMPEQW-256-1) 38218 { 38219 ICLASS: VPCMPEQW 38220 CPL: 3 38221 CATEGORY: AVX512 38222 EXTENSION: AVX512EVEX 38223 ISA_SET: AVX512BW_256 38224 EXCEPTIONS: AVX512-E4 38225 REAL_OPCODE: Y 38226 ATTRIBUTES: MASKOP_EVEX 38227 PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 38228 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 38229 IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 38230 } 38231 38232 { 38233 ICLASS: VPCMPEQW 38234 CPL: 3 38235 CATEGORY: AVX512 38236 EXTENSION: AVX512EVEX 38237 ISA_SET: AVX512BW_256 38238 EXCEPTIONS: AVX512-E4 38239 REAL_OPCODE: Y 38240 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38241 PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 38242 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 38243 IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 38244 } 38245 38246 38247 # EMITTING VPCMPEQW (VPCMPEQW-512-1) 38248 { 38249 ICLASS: VPCMPEQW 38250 CPL: 3 38251 CATEGORY: AVX512 38252 EXTENSION: AVX512EVEX 38253 ISA_SET: AVX512BW_512 38254 EXCEPTIONS: AVX512-E4 38255 REAL_OPCODE: Y 38256 ATTRIBUTES: MASKOP_EVEX 38257 PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 38258 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 38259 IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 38260 } 38261 38262 { 38263 ICLASS: VPCMPEQW 38264 CPL: 3 38265 CATEGORY: AVX512 38266 EXTENSION: AVX512EVEX 38267 ISA_SET: AVX512BW_512 38268 EXCEPTIONS: AVX512-E4 38269 REAL_OPCODE: Y 38270 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38271 PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 38272 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 38273 IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 38274 } 38275 38276 38277 # EMITTING VPCMPGTB (VPCMPGTB-128-1) 38278 { 38279 ICLASS: VPCMPGTB 38280 CPL: 3 38281 CATEGORY: AVX512 38282 EXTENSION: AVX512EVEX 38283 ISA_SET: AVX512BW_128 38284 EXCEPTIONS: AVX512-E4 38285 REAL_OPCODE: Y 38286 ATTRIBUTES: MASKOP_EVEX 38287 PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 38288 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 38289 IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 38290 } 38291 38292 { 38293 ICLASS: VPCMPGTB 38294 CPL: 3 38295 CATEGORY: AVX512 38296 EXTENSION: AVX512EVEX 38297 ISA_SET: AVX512BW_128 38298 EXCEPTIONS: AVX512-E4 38299 REAL_OPCODE: Y 38300 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38301 PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 38302 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 38303 IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 38304 } 38305 38306 38307 # EMITTING VPCMPGTB (VPCMPGTB-256-1) 38308 { 38309 ICLASS: VPCMPGTB 38310 CPL: 3 38311 CATEGORY: AVX512 38312 EXTENSION: AVX512EVEX 38313 ISA_SET: AVX512BW_256 38314 EXCEPTIONS: AVX512-E4 38315 REAL_OPCODE: Y 38316 ATTRIBUTES: MASKOP_EVEX 38317 PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 38318 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 38319 IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 38320 } 38321 38322 { 38323 ICLASS: VPCMPGTB 38324 CPL: 3 38325 CATEGORY: AVX512 38326 EXTENSION: AVX512EVEX 38327 ISA_SET: AVX512BW_256 38328 EXCEPTIONS: AVX512-E4 38329 REAL_OPCODE: Y 38330 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38331 PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 38332 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 38333 IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 38334 } 38335 38336 38337 # EMITTING VPCMPGTB (VPCMPGTB-512-1) 38338 { 38339 ICLASS: VPCMPGTB 38340 CPL: 3 38341 CATEGORY: AVX512 38342 EXTENSION: AVX512EVEX 38343 ISA_SET: AVX512BW_512 38344 EXCEPTIONS: AVX512-E4 38345 REAL_OPCODE: Y 38346 ATTRIBUTES: MASKOP_EVEX 38347 PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 38348 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 38349 IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 38350 } 38351 38352 { 38353 ICLASS: VPCMPGTB 38354 CPL: 3 38355 CATEGORY: AVX512 38356 EXTENSION: AVX512EVEX 38357 ISA_SET: AVX512BW_512 38358 EXCEPTIONS: AVX512-E4 38359 REAL_OPCODE: Y 38360 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38361 PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 38362 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 38363 IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 38364 } 38365 38366 38367 # EMITTING VPCMPGTD (VPCMPGTD-128-1) 38368 { 38369 ICLASS: VPCMPGTD 38370 CPL: 3 38371 CATEGORY: AVX512 38372 EXTENSION: AVX512EVEX 38373 ISA_SET: AVX512F_128 38374 EXCEPTIONS: AVX512-E4 38375 REAL_OPCODE: Y 38376 ATTRIBUTES: MASKOP_EVEX 38377 PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 38378 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 38379 IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 38380 } 38381 38382 { 38383 ICLASS: VPCMPGTD 38384 CPL: 3 38385 CATEGORY: AVX512 38386 EXTENSION: AVX512EVEX 38387 ISA_SET: AVX512F_128 38388 EXCEPTIONS: AVX512-E4 38389 REAL_OPCODE: Y 38390 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38391 PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 38392 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 38393 IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 38394 } 38395 38396 38397 # EMITTING VPCMPGTD (VPCMPGTD-256-1) 38398 { 38399 ICLASS: VPCMPGTD 38400 CPL: 3 38401 CATEGORY: AVX512 38402 EXTENSION: AVX512EVEX 38403 ISA_SET: AVX512F_256 38404 EXCEPTIONS: AVX512-E4 38405 REAL_OPCODE: Y 38406 ATTRIBUTES: MASKOP_EVEX 38407 PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 38408 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 38409 IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 38410 } 38411 38412 { 38413 ICLASS: VPCMPGTD 38414 CPL: 3 38415 CATEGORY: AVX512 38416 EXTENSION: AVX512EVEX 38417 ISA_SET: AVX512F_256 38418 EXCEPTIONS: AVX512-E4 38419 REAL_OPCODE: Y 38420 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38421 PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 38422 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 38423 IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 38424 } 38425 38426 38427 # EMITTING VPCMPGTQ (VPCMPGTQ-128-1) 38428 { 38429 ICLASS: VPCMPGTQ 38430 CPL: 3 38431 CATEGORY: AVX512 38432 EXTENSION: AVX512EVEX 38433 ISA_SET: AVX512F_128 38434 EXCEPTIONS: AVX512-E4 38435 REAL_OPCODE: Y 38436 ATTRIBUTES: MASKOP_EVEX 38437 PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 38438 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 38439 IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 38440 } 38441 38442 { 38443 ICLASS: VPCMPGTQ 38444 CPL: 3 38445 CATEGORY: AVX512 38446 EXTENSION: AVX512EVEX 38447 ISA_SET: AVX512F_128 38448 EXCEPTIONS: AVX512-E4 38449 REAL_OPCODE: Y 38450 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38451 PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 38452 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 38453 IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 38454 } 38455 38456 38457 # EMITTING VPCMPGTQ (VPCMPGTQ-256-1) 38458 { 38459 ICLASS: VPCMPGTQ 38460 CPL: 3 38461 CATEGORY: AVX512 38462 EXTENSION: AVX512EVEX 38463 ISA_SET: AVX512F_256 38464 EXCEPTIONS: AVX512-E4 38465 REAL_OPCODE: Y 38466 ATTRIBUTES: MASKOP_EVEX 38467 PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 38468 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 38469 IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 38470 } 38471 38472 { 38473 ICLASS: VPCMPGTQ 38474 CPL: 3 38475 CATEGORY: AVX512 38476 EXTENSION: AVX512EVEX 38477 ISA_SET: AVX512F_256 38478 EXCEPTIONS: AVX512-E4 38479 REAL_OPCODE: Y 38480 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38481 PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 38482 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 38483 IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 38484 } 38485 38486 38487 # EMITTING VPCMPGTW (VPCMPGTW-128-1) 38488 { 38489 ICLASS: VPCMPGTW 38490 CPL: 3 38491 CATEGORY: AVX512 38492 EXTENSION: AVX512EVEX 38493 ISA_SET: AVX512BW_128 38494 EXCEPTIONS: AVX512-E4 38495 REAL_OPCODE: Y 38496 ATTRIBUTES: MASKOP_EVEX 38497 PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 38498 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 38499 IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 38500 } 38501 38502 { 38503 ICLASS: VPCMPGTW 38504 CPL: 3 38505 CATEGORY: AVX512 38506 EXTENSION: AVX512EVEX 38507 ISA_SET: AVX512BW_128 38508 EXCEPTIONS: AVX512-E4 38509 REAL_OPCODE: Y 38510 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38511 PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 38512 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 38513 IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 38514 } 38515 38516 38517 # EMITTING VPCMPGTW (VPCMPGTW-256-1) 38518 { 38519 ICLASS: VPCMPGTW 38520 CPL: 3 38521 CATEGORY: AVX512 38522 EXTENSION: AVX512EVEX 38523 ISA_SET: AVX512BW_256 38524 EXCEPTIONS: AVX512-E4 38525 REAL_OPCODE: Y 38526 ATTRIBUTES: MASKOP_EVEX 38527 PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 38528 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 38529 IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 38530 } 38531 38532 { 38533 ICLASS: VPCMPGTW 38534 CPL: 3 38535 CATEGORY: AVX512 38536 EXTENSION: AVX512EVEX 38537 ISA_SET: AVX512BW_256 38538 EXCEPTIONS: AVX512-E4 38539 REAL_OPCODE: Y 38540 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38541 PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 38542 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 38543 IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 38544 } 38545 38546 38547 # EMITTING VPCMPGTW (VPCMPGTW-512-1) 38548 { 38549 ICLASS: VPCMPGTW 38550 CPL: 3 38551 CATEGORY: AVX512 38552 EXTENSION: AVX512EVEX 38553 ISA_SET: AVX512BW_512 38554 EXCEPTIONS: AVX512-E4 38555 REAL_OPCODE: Y 38556 ATTRIBUTES: MASKOP_EVEX 38557 PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 38558 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 38559 IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 38560 } 38561 38562 { 38563 ICLASS: VPCMPGTW 38564 CPL: 3 38565 CATEGORY: AVX512 38566 EXTENSION: AVX512EVEX 38567 ISA_SET: AVX512BW_512 38568 EXCEPTIONS: AVX512-E4 38569 REAL_OPCODE: Y 38570 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38571 PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 38572 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 38573 IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 38574 } 38575 38576 38577 # EMITTING VPCMPQ (VPCMPQ-128-1) 38578 { 38579 ICLASS: VPCMPQ 38580 CPL: 3 38581 CATEGORY: AVX512 38582 EXTENSION: AVX512EVEX 38583 ISA_SET: AVX512F_128 38584 EXCEPTIONS: AVX512-E4 38585 REAL_OPCODE: Y 38586 ATTRIBUTES: MASKOP_EVEX 38587 PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() 38588 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 IMM0:r:b 38589 IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 38590 } 38591 38592 { 38593 ICLASS: VPCMPQ 38594 CPL: 3 38595 CATEGORY: AVX512 38596 EXTENSION: AVX512EVEX 38597 ISA_SET: AVX512F_128 38598 EXCEPTIONS: AVX512-E4 38599 REAL_OPCODE: Y 38600 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38601 PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 38602 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b 38603 IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 38604 } 38605 38606 38607 # EMITTING VPCMPQ (VPCMPQ-256-1) 38608 { 38609 ICLASS: VPCMPQ 38610 CPL: 3 38611 CATEGORY: AVX512 38612 EXTENSION: AVX512EVEX 38613 ISA_SET: AVX512F_256 38614 EXCEPTIONS: AVX512-E4 38615 REAL_OPCODE: Y 38616 ATTRIBUTES: MASKOP_EVEX 38617 PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() 38618 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 IMM0:r:b 38619 IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 38620 } 38621 38622 { 38623 ICLASS: VPCMPQ 38624 CPL: 3 38625 CATEGORY: AVX512 38626 EXTENSION: AVX512EVEX 38627 ISA_SET: AVX512F_256 38628 EXCEPTIONS: AVX512-E4 38629 REAL_OPCODE: Y 38630 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38631 PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 38632 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b 38633 IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 38634 } 38635 38636 38637 # EMITTING VPCMPUB (VPCMPUB-128-1) 38638 { 38639 ICLASS: VPCMPUB 38640 CPL: 3 38641 CATEGORY: AVX512 38642 EXTENSION: AVX512EVEX 38643 ISA_SET: AVX512BW_128 38644 EXCEPTIONS: AVX512-E4 38645 REAL_OPCODE: Y 38646 ATTRIBUTES: MASKOP_EVEX 38647 PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() 38648 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b 38649 IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 38650 } 38651 38652 { 38653 ICLASS: VPCMPUB 38654 CPL: 3 38655 CATEGORY: AVX512 38656 EXTENSION: AVX512EVEX 38657 ISA_SET: AVX512BW_128 38658 EXCEPTIONS: AVX512-E4 38659 REAL_OPCODE: Y 38660 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38661 PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 38662 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b 38663 IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 38664 } 38665 38666 38667 # EMITTING VPCMPUB (VPCMPUB-256-1) 38668 { 38669 ICLASS: VPCMPUB 38670 CPL: 3 38671 CATEGORY: AVX512 38672 EXTENSION: AVX512EVEX 38673 ISA_SET: AVX512BW_256 38674 EXCEPTIONS: AVX512-E4 38675 REAL_OPCODE: Y 38676 ATTRIBUTES: MASKOP_EVEX 38677 PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() 38678 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b 38679 IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 38680 } 38681 38682 { 38683 ICLASS: VPCMPUB 38684 CPL: 3 38685 CATEGORY: AVX512 38686 EXTENSION: AVX512EVEX 38687 ISA_SET: AVX512BW_256 38688 EXCEPTIONS: AVX512-E4 38689 REAL_OPCODE: Y 38690 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38691 PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 38692 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b 38693 IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 38694 } 38695 38696 38697 # EMITTING VPCMPUB (VPCMPUB-512-1) 38698 { 38699 ICLASS: VPCMPUB 38700 CPL: 3 38701 CATEGORY: AVX512 38702 EXTENSION: AVX512EVEX 38703 ISA_SET: AVX512BW_512 38704 EXCEPTIONS: AVX512-E4 38705 REAL_OPCODE: Y 38706 ATTRIBUTES: MASKOP_EVEX 38707 PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() 38708 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b 38709 IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 38710 } 38711 38712 { 38713 ICLASS: VPCMPUB 38714 CPL: 3 38715 CATEGORY: AVX512 38716 EXTENSION: AVX512EVEX 38717 ISA_SET: AVX512BW_512 38718 EXCEPTIONS: AVX512-E4 38719 REAL_OPCODE: Y 38720 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38721 PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 38722 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b 38723 IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 38724 } 38725 38726 38727 # EMITTING VPCMPUD (VPCMPUD-128-1) 38728 { 38729 ICLASS: VPCMPUD 38730 CPL: 3 38731 CATEGORY: AVX512 38732 EXTENSION: AVX512EVEX 38733 ISA_SET: AVX512F_128 38734 EXCEPTIONS: AVX512-E4 38735 REAL_OPCODE: Y 38736 ATTRIBUTES: MASKOP_EVEX 38737 PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() 38738 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b 38739 IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 38740 } 38741 38742 { 38743 ICLASS: VPCMPUD 38744 CPL: 3 38745 CATEGORY: AVX512 38746 EXTENSION: AVX512EVEX 38747 ISA_SET: AVX512F_128 38748 EXCEPTIONS: AVX512-E4 38749 REAL_OPCODE: Y 38750 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38751 PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 38752 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 38753 IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 38754 } 38755 38756 38757 # EMITTING VPCMPUD (VPCMPUD-256-1) 38758 { 38759 ICLASS: VPCMPUD 38760 CPL: 3 38761 CATEGORY: AVX512 38762 EXTENSION: AVX512EVEX 38763 ISA_SET: AVX512F_256 38764 EXCEPTIONS: AVX512-E4 38765 REAL_OPCODE: Y 38766 ATTRIBUTES: MASKOP_EVEX 38767 PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() 38768 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b 38769 IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 38770 } 38771 38772 { 38773 ICLASS: VPCMPUD 38774 CPL: 3 38775 CATEGORY: AVX512 38776 EXTENSION: AVX512EVEX 38777 ISA_SET: AVX512F_256 38778 EXCEPTIONS: AVX512-E4 38779 REAL_OPCODE: Y 38780 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38781 PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 38782 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 38783 IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 38784 } 38785 38786 38787 # EMITTING VPCMPUQ (VPCMPUQ-128-1) 38788 { 38789 ICLASS: VPCMPUQ 38790 CPL: 3 38791 CATEGORY: AVX512 38792 EXTENSION: AVX512EVEX 38793 ISA_SET: AVX512F_128 38794 EXCEPTIONS: AVX512-E4 38795 REAL_OPCODE: Y 38796 ATTRIBUTES: MASKOP_EVEX 38797 PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() 38798 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b 38799 IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 38800 } 38801 38802 { 38803 ICLASS: VPCMPUQ 38804 CPL: 3 38805 CATEGORY: AVX512 38806 EXTENSION: AVX512EVEX 38807 ISA_SET: AVX512F_128 38808 EXCEPTIONS: AVX512-E4 38809 REAL_OPCODE: Y 38810 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38811 PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 38812 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 38813 IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 38814 } 38815 38816 38817 # EMITTING VPCMPUQ (VPCMPUQ-256-1) 38818 { 38819 ICLASS: VPCMPUQ 38820 CPL: 3 38821 CATEGORY: AVX512 38822 EXTENSION: AVX512EVEX 38823 ISA_SET: AVX512F_256 38824 EXCEPTIONS: AVX512-E4 38825 REAL_OPCODE: Y 38826 ATTRIBUTES: MASKOP_EVEX 38827 PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() 38828 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b 38829 IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 38830 } 38831 38832 { 38833 ICLASS: VPCMPUQ 38834 CPL: 3 38835 CATEGORY: AVX512 38836 EXTENSION: AVX512EVEX 38837 ISA_SET: AVX512F_256 38838 EXCEPTIONS: AVX512-E4 38839 REAL_OPCODE: Y 38840 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 38841 PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() 38842 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 38843 IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 38844 } 38845 38846 38847 # EMITTING VPCMPUW (VPCMPUW-128-1) 38848 { 38849 ICLASS: VPCMPUW 38850 CPL: 3 38851 CATEGORY: AVX512 38852 EXTENSION: AVX512EVEX 38853 ISA_SET: AVX512BW_128 38854 EXCEPTIONS: AVX512-E4 38855 REAL_OPCODE: Y 38856 ATTRIBUTES: MASKOP_EVEX 38857 PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() 38858 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b 38859 IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 38860 } 38861 38862 { 38863 ICLASS: VPCMPUW 38864 CPL: 3 38865 CATEGORY: AVX512 38866 EXTENSION: AVX512EVEX 38867 ISA_SET: AVX512BW_128 38868 EXCEPTIONS: AVX512-E4 38869 REAL_OPCODE: Y 38870 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38871 PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 38872 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b 38873 IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 38874 } 38875 38876 38877 # EMITTING VPCMPUW (VPCMPUW-256-1) 38878 { 38879 ICLASS: VPCMPUW 38880 CPL: 3 38881 CATEGORY: AVX512 38882 EXTENSION: AVX512EVEX 38883 ISA_SET: AVX512BW_256 38884 EXCEPTIONS: AVX512-E4 38885 REAL_OPCODE: Y 38886 ATTRIBUTES: MASKOP_EVEX 38887 PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() 38888 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b 38889 IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 38890 } 38891 38892 { 38893 ICLASS: VPCMPUW 38894 CPL: 3 38895 CATEGORY: AVX512 38896 EXTENSION: AVX512EVEX 38897 ISA_SET: AVX512BW_256 38898 EXCEPTIONS: AVX512-E4 38899 REAL_OPCODE: Y 38900 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38901 PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 38902 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b 38903 IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 38904 } 38905 38906 38907 # EMITTING VPCMPUW (VPCMPUW-512-1) 38908 { 38909 ICLASS: VPCMPUW 38910 CPL: 3 38911 CATEGORY: AVX512 38912 EXTENSION: AVX512EVEX 38913 ISA_SET: AVX512BW_512 38914 EXCEPTIONS: AVX512-E4 38915 REAL_OPCODE: Y 38916 ATTRIBUTES: MASKOP_EVEX 38917 PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() 38918 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b 38919 IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 38920 } 38921 38922 { 38923 ICLASS: VPCMPUW 38924 CPL: 3 38925 CATEGORY: AVX512 38926 EXTENSION: AVX512EVEX 38927 ISA_SET: AVX512BW_512 38928 EXCEPTIONS: AVX512-E4 38929 REAL_OPCODE: Y 38930 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38931 PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 38932 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b 38933 IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 38934 } 38935 38936 38937 # EMITTING VPCMPW (VPCMPW-128-1) 38938 { 38939 ICLASS: VPCMPW 38940 CPL: 3 38941 CATEGORY: AVX512 38942 EXTENSION: AVX512EVEX 38943 ISA_SET: AVX512BW_128 38944 EXCEPTIONS: AVX512-E4 38945 REAL_OPCODE: Y 38946 ATTRIBUTES: MASKOP_EVEX 38947 PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() 38948 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 IMM0:r:b 38949 IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 38950 } 38951 38952 { 38953 ICLASS: VPCMPW 38954 CPL: 3 38955 CATEGORY: AVX512 38956 EXTENSION: AVX512EVEX 38957 ISA_SET: AVX512BW_128 38958 EXCEPTIONS: AVX512-E4 38959 REAL_OPCODE: Y 38960 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38961 PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 38962 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b 38963 IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 38964 } 38965 38966 38967 # EMITTING VPCMPW (VPCMPW-256-1) 38968 { 38969 ICLASS: VPCMPW 38970 CPL: 3 38971 CATEGORY: AVX512 38972 EXTENSION: AVX512EVEX 38973 ISA_SET: AVX512BW_256 38974 EXCEPTIONS: AVX512-E4 38975 REAL_OPCODE: Y 38976 ATTRIBUTES: MASKOP_EVEX 38977 PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() 38978 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 IMM0:r:b 38979 IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 38980 } 38981 38982 { 38983 ICLASS: VPCMPW 38984 CPL: 3 38985 CATEGORY: AVX512 38986 EXTENSION: AVX512EVEX 38987 ISA_SET: AVX512BW_256 38988 EXCEPTIONS: AVX512-E4 38989 REAL_OPCODE: Y 38990 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 38991 PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 38992 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 IMM0:r:b 38993 IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 38994 } 38995 38996 38997 # EMITTING VPCMPW (VPCMPW-512-1) 38998 { 38999 ICLASS: VPCMPW 39000 CPL: 3 39001 CATEGORY: AVX512 39002 EXTENSION: AVX512EVEX 39003 ISA_SET: AVX512BW_512 39004 EXCEPTIONS: AVX512-E4 39005 REAL_OPCODE: Y 39006 ATTRIBUTES: MASKOP_EVEX 39007 PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() 39008 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 IMM0:r:b 39009 IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 39010 } 39011 39012 { 39013 ICLASS: VPCMPW 39014 CPL: 3 39015 CATEGORY: AVX512 39016 EXTENSION: AVX512EVEX 39017 ISA_SET: AVX512BW_512 39018 EXCEPTIONS: AVX512-E4 39019 REAL_OPCODE: Y 39020 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 39021 PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 39022 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 IMM0:r:b 39023 IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 39024 } 39025 39026 39027 # EMITTING VPCOMPRESSD (VPCOMPRESSD-128-1) 39028 { 39029 ICLASS: VPCOMPRESSD 39030 CPL: 3 39031 CATEGORY: COMPRESS 39032 EXTENSION: AVX512EVEX 39033 ISA_SET: AVX512F_128 39034 EXCEPTIONS: AVX512-E4 39035 REAL_OPCODE: Y 39036 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 39037 PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 39038 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 39039 IFORM: VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 39040 } 39041 39042 39043 # EMITTING VPCOMPRESSD (VPCOMPRESSD-128-2) 39044 { 39045 ICLASS: VPCOMPRESSD 39046 CPL: 3 39047 CATEGORY: COMPRESS 39048 EXTENSION: AVX512EVEX 39049 ISA_SET: AVX512F_128 39050 EXCEPTIONS: AVX512-E4 39051 REAL_OPCODE: Y 39052 ATTRIBUTES: MASKOP_EVEX 39053 PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 39054 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 39055 IFORM: VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 39056 } 39057 39058 39059 # EMITTING VPCOMPRESSD (VPCOMPRESSD-256-1) 39060 { 39061 ICLASS: VPCOMPRESSD 39062 CPL: 3 39063 CATEGORY: COMPRESS 39064 EXTENSION: AVX512EVEX 39065 ISA_SET: AVX512F_256 39066 EXCEPTIONS: AVX512-E4 39067 REAL_OPCODE: Y 39068 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 39069 PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 39070 OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 39071 IFORM: VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 39072 } 39073 39074 39075 # EMITTING VPCOMPRESSD (VPCOMPRESSD-256-2) 39076 { 39077 ICLASS: VPCOMPRESSD 39078 CPL: 3 39079 CATEGORY: COMPRESS 39080 EXTENSION: AVX512EVEX 39081 ISA_SET: AVX512F_256 39082 EXCEPTIONS: AVX512-E4 39083 REAL_OPCODE: Y 39084 ATTRIBUTES: MASKOP_EVEX 39085 PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 39086 OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 39087 IFORM: VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 39088 } 39089 39090 39091 # EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-1) 39092 { 39093 ICLASS: VPCOMPRESSQ 39094 CPL: 3 39095 CATEGORY: COMPRESS 39096 EXTENSION: AVX512EVEX 39097 ISA_SET: AVX512F_128 39098 EXCEPTIONS: AVX512-E4 39099 REAL_OPCODE: Y 39100 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 39101 PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 39102 OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 39103 IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 39104 } 39105 39106 39107 # EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-2) 39108 { 39109 ICLASS: VPCOMPRESSQ 39110 CPL: 3 39111 CATEGORY: COMPRESS 39112 EXTENSION: AVX512EVEX 39113 ISA_SET: AVX512F_128 39114 EXCEPTIONS: AVX512-E4 39115 REAL_OPCODE: Y 39116 ATTRIBUTES: MASKOP_EVEX 39117 PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 39118 OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 39119 IFORM: VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 39120 } 39121 39122 39123 # EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-1) 39124 { 39125 ICLASS: VPCOMPRESSQ 39126 CPL: 3 39127 CATEGORY: COMPRESS 39128 EXTENSION: AVX512EVEX 39129 ISA_SET: AVX512F_256 39130 EXCEPTIONS: AVX512-E4 39131 REAL_OPCODE: Y 39132 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 39133 PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 39134 OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 39135 IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 39136 } 39137 39138 39139 # EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-2) 39140 { 39141 ICLASS: VPCOMPRESSQ 39142 CPL: 3 39143 CATEGORY: COMPRESS 39144 EXTENSION: AVX512EVEX 39145 ISA_SET: AVX512F_256 39146 EXCEPTIONS: AVX512-E4 39147 REAL_OPCODE: Y 39148 ATTRIBUTES: MASKOP_EVEX 39149 PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 39150 OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 39151 IFORM: VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 39152 } 39153 39154 39155 # EMITTING VPCONFLICTD (VPCONFLICTD-128-1) 39156 { 39157 ICLASS: VPCONFLICTD 39158 CPL: 3 39159 CATEGORY: CONFLICT 39160 EXTENSION: AVX512EVEX 39161 ISA_SET: AVX512CD_128 39162 EXCEPTIONS: AVX512-E4NF 39163 REAL_OPCODE: Y 39164 ATTRIBUTES: MASKOP_EVEX 39165 PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 39166 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 39167 IFORM: VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 39168 } 39169 39170 { 39171 ICLASS: VPCONFLICTD 39172 CPL: 3 39173 CATEGORY: CONFLICT 39174 EXTENSION: AVX512EVEX 39175 ISA_SET: AVX512CD_128 39176 EXCEPTIONS: AVX512-E4NF 39177 REAL_OPCODE: Y 39178 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39179 PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 39180 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 39181 IFORM: VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 39182 } 39183 39184 39185 # EMITTING VPCONFLICTD (VPCONFLICTD-256-1) 39186 { 39187 ICLASS: VPCONFLICTD 39188 CPL: 3 39189 CATEGORY: CONFLICT 39190 EXTENSION: AVX512EVEX 39191 ISA_SET: AVX512CD_256 39192 EXCEPTIONS: AVX512-E4NF 39193 REAL_OPCODE: Y 39194 ATTRIBUTES: MASKOP_EVEX 39195 PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 39196 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 39197 IFORM: VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 39198 } 39199 39200 { 39201 ICLASS: VPCONFLICTD 39202 CPL: 3 39203 CATEGORY: CONFLICT 39204 EXTENSION: AVX512EVEX 39205 ISA_SET: AVX512CD_256 39206 EXCEPTIONS: AVX512-E4NF 39207 REAL_OPCODE: Y 39208 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39209 PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 39210 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 39211 IFORM: VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 39212 } 39213 39214 39215 # EMITTING VPCONFLICTQ (VPCONFLICTQ-128-1) 39216 { 39217 ICLASS: VPCONFLICTQ 39218 CPL: 3 39219 CATEGORY: CONFLICT 39220 EXTENSION: AVX512EVEX 39221 ISA_SET: AVX512CD_128 39222 EXCEPTIONS: AVX512-E4NF 39223 REAL_OPCODE: Y 39224 ATTRIBUTES: MASKOP_EVEX 39225 PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 39226 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 39227 IFORM: VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 39228 } 39229 39230 { 39231 ICLASS: VPCONFLICTQ 39232 CPL: 3 39233 CATEGORY: CONFLICT 39234 EXTENSION: AVX512EVEX 39235 ISA_SET: AVX512CD_128 39236 EXCEPTIONS: AVX512-E4NF 39237 REAL_OPCODE: Y 39238 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39239 PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 39240 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 39241 IFORM: VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 39242 } 39243 39244 39245 # EMITTING VPCONFLICTQ (VPCONFLICTQ-256-1) 39246 { 39247 ICLASS: VPCONFLICTQ 39248 CPL: 3 39249 CATEGORY: CONFLICT 39250 EXTENSION: AVX512EVEX 39251 ISA_SET: AVX512CD_256 39252 EXCEPTIONS: AVX512-E4NF 39253 REAL_OPCODE: Y 39254 ATTRIBUTES: MASKOP_EVEX 39255 PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 39256 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 39257 IFORM: VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 39258 } 39259 39260 { 39261 ICLASS: VPCONFLICTQ 39262 CPL: 3 39263 CATEGORY: CONFLICT 39264 EXTENSION: AVX512EVEX 39265 ISA_SET: AVX512CD_256 39266 EXCEPTIONS: AVX512-E4NF 39267 REAL_OPCODE: Y 39268 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39269 PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 39270 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 39271 IFORM: VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 39272 } 39273 39274 39275 # EMITTING VPERMD (VPERMD-256-1) 39276 { 39277 ICLASS: VPERMD 39278 CPL: 3 39279 CATEGORY: AVX512 39280 EXTENSION: AVX512EVEX 39281 ISA_SET: AVX512F_256 39282 EXCEPTIONS: AVX512-E4NF 39283 REAL_OPCODE: Y 39284 ATTRIBUTES: MASKOP_EVEX 39285 PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 39286 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 39287 IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 39288 } 39289 39290 { 39291 ICLASS: VPERMD 39292 CPL: 3 39293 CATEGORY: AVX512 39294 EXTENSION: AVX512EVEX 39295 ISA_SET: AVX512F_256 39296 EXCEPTIONS: AVX512-E4NF 39297 REAL_OPCODE: Y 39298 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39299 PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 39300 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 39301 IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 39302 } 39303 39304 39305 # EMITTING VPERMI2D (VPERMI2D-128-1) 39306 { 39307 ICLASS: VPERMI2D 39308 CPL: 3 39309 CATEGORY: AVX512 39310 EXTENSION: AVX512EVEX 39311 ISA_SET: AVX512F_128 39312 EXCEPTIONS: AVX512-E4NF 39313 REAL_OPCODE: Y 39314 ATTRIBUTES: MASKOP_EVEX 39315 PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 39316 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 39317 IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 39318 } 39319 39320 { 39321 ICLASS: VPERMI2D 39322 CPL: 3 39323 CATEGORY: AVX512 39324 EXTENSION: AVX512EVEX 39325 ISA_SET: AVX512F_128 39326 EXCEPTIONS: AVX512-E4NF 39327 REAL_OPCODE: Y 39328 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39329 PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 39330 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 39331 IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 39332 } 39333 39334 39335 # EMITTING VPERMI2D (VPERMI2D-256-1) 39336 { 39337 ICLASS: VPERMI2D 39338 CPL: 3 39339 CATEGORY: AVX512 39340 EXTENSION: AVX512EVEX 39341 ISA_SET: AVX512F_256 39342 EXCEPTIONS: AVX512-E4NF 39343 REAL_OPCODE: Y 39344 ATTRIBUTES: MASKOP_EVEX 39345 PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 39346 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 39347 IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 39348 } 39349 39350 { 39351 ICLASS: VPERMI2D 39352 CPL: 3 39353 CATEGORY: AVX512 39354 EXTENSION: AVX512EVEX 39355 ISA_SET: AVX512F_256 39356 EXCEPTIONS: AVX512-E4NF 39357 REAL_OPCODE: Y 39358 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39359 PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 39360 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 39361 IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 39362 } 39363 39364 39365 # EMITTING VPERMI2PD (VPERMI2PD-128-1) 39366 { 39367 ICLASS: VPERMI2PD 39368 CPL: 3 39369 CATEGORY: AVX512 39370 EXTENSION: AVX512EVEX 39371 ISA_SET: AVX512F_128 39372 EXCEPTIONS: AVX512-E4NF 39373 REAL_OPCODE: Y 39374 ATTRIBUTES: MASKOP_EVEX 39375 PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 39376 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 39377 IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 39378 } 39379 39380 { 39381 ICLASS: VPERMI2PD 39382 CPL: 3 39383 CATEGORY: AVX512 39384 EXTENSION: AVX512EVEX 39385 ISA_SET: AVX512F_128 39386 EXCEPTIONS: AVX512-E4NF 39387 REAL_OPCODE: Y 39388 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39389 PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 39390 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 39391 IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 39392 } 39393 39394 39395 # EMITTING VPERMI2PD (VPERMI2PD-256-1) 39396 { 39397 ICLASS: VPERMI2PD 39398 CPL: 3 39399 CATEGORY: AVX512 39400 EXTENSION: AVX512EVEX 39401 ISA_SET: AVX512F_256 39402 EXCEPTIONS: AVX512-E4NF 39403 REAL_OPCODE: Y 39404 ATTRIBUTES: MASKOP_EVEX 39405 PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 39406 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 39407 IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 39408 } 39409 39410 { 39411 ICLASS: VPERMI2PD 39412 CPL: 3 39413 CATEGORY: AVX512 39414 EXTENSION: AVX512EVEX 39415 ISA_SET: AVX512F_256 39416 EXCEPTIONS: AVX512-E4NF 39417 REAL_OPCODE: Y 39418 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39419 PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 39420 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 39421 IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 39422 } 39423 39424 39425 # EMITTING VPERMI2PS (VPERMI2PS-128-1) 39426 { 39427 ICLASS: VPERMI2PS 39428 CPL: 3 39429 CATEGORY: AVX512 39430 EXTENSION: AVX512EVEX 39431 ISA_SET: AVX512F_128 39432 EXCEPTIONS: AVX512-E4NF 39433 REAL_OPCODE: Y 39434 ATTRIBUTES: MASKOP_EVEX 39435 PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 39436 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 39437 IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 39438 } 39439 39440 { 39441 ICLASS: VPERMI2PS 39442 CPL: 3 39443 CATEGORY: AVX512 39444 EXTENSION: AVX512EVEX 39445 ISA_SET: AVX512F_128 39446 EXCEPTIONS: AVX512-E4NF 39447 REAL_OPCODE: Y 39448 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39449 PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 39450 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 39451 IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 39452 } 39453 39454 39455 # EMITTING VPERMI2PS (VPERMI2PS-256-1) 39456 { 39457 ICLASS: VPERMI2PS 39458 CPL: 3 39459 CATEGORY: AVX512 39460 EXTENSION: AVX512EVEX 39461 ISA_SET: AVX512F_256 39462 EXCEPTIONS: AVX512-E4NF 39463 REAL_OPCODE: Y 39464 ATTRIBUTES: MASKOP_EVEX 39465 PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 39466 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 39467 IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 39468 } 39469 39470 { 39471 ICLASS: VPERMI2PS 39472 CPL: 3 39473 CATEGORY: AVX512 39474 EXTENSION: AVX512EVEX 39475 ISA_SET: AVX512F_256 39476 EXCEPTIONS: AVX512-E4NF 39477 REAL_OPCODE: Y 39478 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39479 PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 39480 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 39481 IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 39482 } 39483 39484 39485 # EMITTING VPERMI2Q (VPERMI2Q-128-1) 39486 { 39487 ICLASS: VPERMI2Q 39488 CPL: 3 39489 CATEGORY: AVX512 39490 EXTENSION: AVX512EVEX 39491 ISA_SET: AVX512F_128 39492 EXCEPTIONS: AVX512-E4NF 39493 REAL_OPCODE: Y 39494 ATTRIBUTES: MASKOP_EVEX 39495 PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 39496 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 39497 IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 39498 } 39499 39500 { 39501 ICLASS: VPERMI2Q 39502 CPL: 3 39503 CATEGORY: AVX512 39504 EXTENSION: AVX512EVEX 39505 ISA_SET: AVX512F_128 39506 EXCEPTIONS: AVX512-E4NF 39507 REAL_OPCODE: Y 39508 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39509 PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 39510 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 39511 IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 39512 } 39513 39514 39515 # EMITTING VPERMI2Q (VPERMI2Q-256-1) 39516 { 39517 ICLASS: VPERMI2Q 39518 CPL: 3 39519 CATEGORY: AVX512 39520 EXTENSION: AVX512EVEX 39521 ISA_SET: AVX512F_256 39522 EXCEPTIONS: AVX512-E4NF 39523 REAL_OPCODE: Y 39524 ATTRIBUTES: MASKOP_EVEX 39525 PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 39526 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 39527 IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 39528 } 39529 39530 { 39531 ICLASS: VPERMI2Q 39532 CPL: 3 39533 CATEGORY: AVX512 39534 EXTENSION: AVX512EVEX 39535 ISA_SET: AVX512F_256 39536 EXCEPTIONS: AVX512-E4NF 39537 REAL_OPCODE: Y 39538 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39539 PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 39540 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 39541 IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 39542 } 39543 39544 39545 # EMITTING VPERMI2W (VPERMI2W-128-1) 39546 { 39547 ICLASS: VPERMI2W 39548 CPL: 3 39549 CATEGORY: AVX512 39550 EXTENSION: AVX512EVEX 39551 ISA_SET: AVX512BW_128 39552 EXCEPTIONS: AVX512-E4NF 39553 REAL_OPCODE: Y 39554 ATTRIBUTES: MASKOP_EVEX 39555 PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 39556 OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 39557 IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 39558 } 39559 39560 { 39561 ICLASS: VPERMI2W 39562 CPL: 3 39563 CATEGORY: AVX512 39564 EXTENSION: AVX512EVEX 39565 ISA_SET: AVX512BW_128 39566 EXCEPTIONS: AVX512-E4NF 39567 REAL_OPCODE: Y 39568 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 39569 PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 39570 OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 39571 IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 39572 } 39573 39574 39575 # EMITTING VPERMI2W (VPERMI2W-256-1) 39576 { 39577 ICLASS: VPERMI2W 39578 CPL: 3 39579 CATEGORY: AVX512 39580 EXTENSION: AVX512EVEX 39581 ISA_SET: AVX512BW_256 39582 EXCEPTIONS: AVX512-E4NF 39583 REAL_OPCODE: Y 39584 ATTRIBUTES: MASKOP_EVEX 39585 PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 39586 OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 39587 IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 39588 } 39589 39590 { 39591 ICLASS: VPERMI2W 39592 CPL: 3 39593 CATEGORY: AVX512 39594 EXTENSION: AVX512EVEX 39595 ISA_SET: AVX512BW_256 39596 EXCEPTIONS: AVX512-E4NF 39597 REAL_OPCODE: Y 39598 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 39599 PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 39600 OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 39601 IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 39602 } 39603 39604 39605 # EMITTING VPERMI2W (VPERMI2W-512-1) 39606 { 39607 ICLASS: VPERMI2W 39608 CPL: 3 39609 CATEGORY: AVX512 39610 EXTENSION: AVX512EVEX 39611 ISA_SET: AVX512BW_512 39612 EXCEPTIONS: AVX512-E4NF 39613 REAL_OPCODE: Y 39614 ATTRIBUTES: MASKOP_EVEX 39615 PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 39616 OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 39617 IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 39618 } 39619 39620 { 39621 ICLASS: VPERMI2W 39622 CPL: 3 39623 CATEGORY: AVX512 39624 EXTENSION: AVX512EVEX 39625 ISA_SET: AVX512BW_512 39626 EXCEPTIONS: AVX512-E4NF 39627 REAL_OPCODE: Y 39628 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 39629 PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 39630 OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 39631 IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 39632 } 39633 39634 39635 # EMITTING VPERMILPD (VPERMILPD-128-1) 39636 { 39637 ICLASS: VPERMILPD 39638 CPL: 3 39639 CATEGORY: AVX512 39640 EXTENSION: AVX512EVEX 39641 ISA_SET: AVX512F_128 39642 EXCEPTIONS: AVX512-E4NF 39643 REAL_OPCODE: Y 39644 ATTRIBUTES: MASKOP_EVEX 39645 PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() 39646 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b 39647 IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 39648 } 39649 39650 { 39651 ICLASS: VPERMILPD 39652 CPL: 3 39653 CATEGORY: AVX512 39654 EXTENSION: AVX512EVEX 39655 ISA_SET: AVX512F_128 39656 EXCEPTIONS: AVX512-E4NF 39657 REAL_OPCODE: Y 39658 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39659 PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 39660 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 39661 IFORM: VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 39662 } 39663 39664 39665 # EMITTING VPERMILPD (VPERMILPD-128-2) 39666 { 39667 ICLASS: VPERMILPD 39668 CPL: 3 39669 CATEGORY: AVX512 39670 EXTENSION: AVX512EVEX 39671 ISA_SET: AVX512F_128 39672 EXCEPTIONS: AVX512-E4NF 39673 REAL_OPCODE: Y 39674 ATTRIBUTES: MASKOP_EVEX 39675 PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 39676 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 39677 IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 39678 } 39679 39680 { 39681 ICLASS: VPERMILPD 39682 CPL: 3 39683 CATEGORY: AVX512 39684 EXTENSION: AVX512EVEX 39685 ISA_SET: AVX512F_128 39686 EXCEPTIONS: AVX512-E4NF 39687 REAL_OPCODE: Y 39688 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39689 PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 39690 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 39691 IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 39692 } 39693 39694 39695 # EMITTING VPERMILPD (VPERMILPD-256-1) 39696 { 39697 ICLASS: VPERMILPD 39698 CPL: 3 39699 CATEGORY: AVX512 39700 EXTENSION: AVX512EVEX 39701 ISA_SET: AVX512F_256 39702 EXCEPTIONS: AVX512-E4NF 39703 REAL_OPCODE: Y 39704 ATTRIBUTES: MASKOP_EVEX 39705 PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 39706 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b 39707 IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 39708 } 39709 39710 { 39711 ICLASS: VPERMILPD 39712 CPL: 3 39713 CATEGORY: AVX512 39714 EXTENSION: AVX512EVEX 39715 ISA_SET: AVX512F_256 39716 EXCEPTIONS: AVX512-E4NF 39717 REAL_OPCODE: Y 39718 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39719 PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 39720 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 39721 IFORM: VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 39722 } 39723 39724 39725 # EMITTING VPERMILPD (VPERMILPD-256-2) 39726 { 39727 ICLASS: VPERMILPD 39728 CPL: 3 39729 CATEGORY: AVX512 39730 EXTENSION: AVX512EVEX 39731 ISA_SET: AVX512F_256 39732 EXCEPTIONS: AVX512-E4NF 39733 REAL_OPCODE: Y 39734 ATTRIBUTES: MASKOP_EVEX 39735 PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 39736 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 39737 IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 39738 } 39739 39740 { 39741 ICLASS: VPERMILPD 39742 CPL: 3 39743 CATEGORY: AVX512 39744 EXTENSION: AVX512EVEX 39745 ISA_SET: AVX512F_256 39746 EXCEPTIONS: AVX512-E4NF 39747 REAL_OPCODE: Y 39748 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39749 PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 39750 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 39751 IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 39752 } 39753 39754 39755 # EMITTING VPERMILPS (VPERMILPS-128-1) 39756 { 39757 ICLASS: VPERMILPS 39758 CPL: 3 39759 CATEGORY: AVX512 39760 EXTENSION: AVX512EVEX 39761 ISA_SET: AVX512F_128 39762 EXCEPTIONS: AVX512-E4NF 39763 REAL_OPCODE: Y 39764 ATTRIBUTES: MASKOP_EVEX 39765 PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() 39766 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b 39767 IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 39768 } 39769 39770 { 39771 ICLASS: VPERMILPS 39772 CPL: 3 39773 CATEGORY: AVX512 39774 EXTENSION: AVX512EVEX 39775 ISA_SET: AVX512F_128 39776 EXCEPTIONS: AVX512-E4NF 39777 REAL_OPCODE: Y 39778 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39779 PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 39780 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 39781 IFORM: VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 39782 } 39783 39784 39785 # EMITTING VPERMILPS (VPERMILPS-128-2) 39786 { 39787 ICLASS: VPERMILPS 39788 CPL: 3 39789 CATEGORY: AVX512 39790 EXTENSION: AVX512EVEX 39791 ISA_SET: AVX512F_128 39792 EXCEPTIONS: AVX512-E4NF 39793 REAL_OPCODE: Y 39794 ATTRIBUTES: MASKOP_EVEX 39795 PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 39796 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 39797 IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 39798 } 39799 39800 { 39801 ICLASS: VPERMILPS 39802 CPL: 3 39803 CATEGORY: AVX512 39804 EXTENSION: AVX512EVEX 39805 ISA_SET: AVX512F_128 39806 EXCEPTIONS: AVX512-E4NF 39807 REAL_OPCODE: Y 39808 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39809 PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 39810 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 39811 IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 39812 } 39813 39814 39815 # EMITTING VPERMILPS (VPERMILPS-256-1) 39816 { 39817 ICLASS: VPERMILPS 39818 CPL: 3 39819 CATEGORY: AVX512 39820 EXTENSION: AVX512EVEX 39821 ISA_SET: AVX512F_256 39822 EXCEPTIONS: AVX512-E4NF 39823 REAL_OPCODE: Y 39824 ATTRIBUTES: MASKOP_EVEX 39825 PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 39826 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b 39827 IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 39828 } 39829 39830 { 39831 ICLASS: VPERMILPS 39832 CPL: 3 39833 CATEGORY: AVX512 39834 EXTENSION: AVX512EVEX 39835 ISA_SET: AVX512F_256 39836 EXCEPTIONS: AVX512-E4NF 39837 REAL_OPCODE: Y 39838 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39839 PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 39840 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 39841 IFORM: VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 39842 } 39843 39844 39845 # EMITTING VPERMILPS (VPERMILPS-256-2) 39846 { 39847 ICLASS: VPERMILPS 39848 CPL: 3 39849 CATEGORY: AVX512 39850 EXTENSION: AVX512EVEX 39851 ISA_SET: AVX512F_256 39852 EXCEPTIONS: AVX512-E4NF 39853 REAL_OPCODE: Y 39854 ATTRIBUTES: MASKOP_EVEX 39855 PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 39856 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 39857 IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 39858 } 39859 39860 { 39861 ICLASS: VPERMILPS 39862 CPL: 3 39863 CATEGORY: AVX512 39864 EXTENSION: AVX512EVEX 39865 ISA_SET: AVX512F_256 39866 EXCEPTIONS: AVX512-E4NF 39867 REAL_OPCODE: Y 39868 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39869 PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 39870 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 39871 IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 39872 } 39873 39874 39875 # EMITTING VPERMPD (VPERMPD-256-1) 39876 { 39877 ICLASS: VPERMPD 39878 CPL: 3 39879 CATEGORY: AVX512 39880 EXTENSION: AVX512EVEX 39881 ISA_SET: AVX512F_256 39882 EXCEPTIONS: AVX512-E4NF 39883 REAL_OPCODE: Y 39884 ATTRIBUTES: MASKOP_EVEX 39885 PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 39886 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b 39887 IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 39888 } 39889 39890 { 39891 ICLASS: VPERMPD 39892 CPL: 3 39893 CATEGORY: AVX512 39894 EXTENSION: AVX512EVEX 39895 ISA_SET: AVX512F_256 39896 EXCEPTIONS: AVX512-E4NF 39897 REAL_OPCODE: Y 39898 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39899 PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 39900 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 39901 IFORM: VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 39902 } 39903 39904 39905 # EMITTING VPERMPD (VPERMPD-256-2) 39906 { 39907 ICLASS: VPERMPD 39908 CPL: 3 39909 CATEGORY: AVX512 39910 EXTENSION: AVX512EVEX 39911 ISA_SET: AVX512F_256 39912 EXCEPTIONS: AVX512-E4NF 39913 REAL_OPCODE: Y 39914 ATTRIBUTES: MASKOP_EVEX 39915 PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 39916 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 39917 IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 39918 } 39919 39920 { 39921 ICLASS: VPERMPD 39922 CPL: 3 39923 CATEGORY: AVX512 39924 EXTENSION: AVX512EVEX 39925 ISA_SET: AVX512F_256 39926 EXCEPTIONS: AVX512-E4NF 39927 REAL_OPCODE: Y 39928 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39929 PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 39930 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 39931 IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 39932 } 39933 39934 39935 # EMITTING VPERMPS (VPERMPS-256-1) 39936 { 39937 ICLASS: VPERMPS 39938 CPL: 3 39939 CATEGORY: AVX512 39940 EXTENSION: AVX512EVEX 39941 ISA_SET: AVX512F_256 39942 EXCEPTIONS: AVX512-E4NF 39943 REAL_OPCODE: Y 39944 ATTRIBUTES: MASKOP_EVEX 39945 PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 39946 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 39947 IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 39948 } 39949 39950 { 39951 ICLASS: VPERMPS 39952 CPL: 3 39953 CATEGORY: AVX512 39954 EXTENSION: AVX512EVEX 39955 ISA_SET: AVX512F_256 39956 EXCEPTIONS: AVX512-E4NF 39957 REAL_OPCODE: Y 39958 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39959 PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 39960 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 39961 IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 39962 } 39963 39964 39965 # EMITTING VPERMQ (VPERMQ-256-1) 39966 { 39967 ICLASS: VPERMQ 39968 CPL: 3 39969 CATEGORY: AVX512 39970 EXTENSION: AVX512EVEX 39971 ISA_SET: AVX512F_256 39972 EXCEPTIONS: AVX512-E4NF 39973 REAL_OPCODE: Y 39974 ATTRIBUTES: MASKOP_EVEX 39975 PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 39976 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b 39977 IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 39978 } 39979 39980 { 39981 ICLASS: VPERMQ 39982 CPL: 3 39983 CATEGORY: AVX512 39984 EXTENSION: AVX512EVEX 39985 ISA_SET: AVX512F_256 39986 EXCEPTIONS: AVX512-E4NF 39987 REAL_OPCODE: Y 39988 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 39989 PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 39990 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 39991 IFORM: VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 39992 } 39993 39994 39995 # EMITTING VPERMQ (VPERMQ-256-2) 39996 { 39997 ICLASS: VPERMQ 39998 CPL: 3 39999 CATEGORY: AVX512 40000 EXTENSION: AVX512EVEX 40001 ISA_SET: AVX512F_256 40002 EXCEPTIONS: AVX512-E4NF 40003 REAL_OPCODE: Y 40004 ATTRIBUTES: MASKOP_EVEX 40005 PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 40006 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 40007 IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 40008 } 40009 40010 { 40011 ICLASS: VPERMQ 40012 CPL: 3 40013 CATEGORY: AVX512 40014 EXTENSION: AVX512EVEX 40015 ISA_SET: AVX512F_256 40016 EXCEPTIONS: AVX512-E4NF 40017 REAL_OPCODE: Y 40018 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40019 PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 40020 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 40021 IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 40022 } 40023 40024 40025 # EMITTING VPERMT2D (VPERMT2D-128-1) 40026 { 40027 ICLASS: VPERMT2D 40028 CPL: 3 40029 CATEGORY: AVX512 40030 EXTENSION: AVX512EVEX 40031 ISA_SET: AVX512F_128 40032 EXCEPTIONS: AVX512-E4NF 40033 REAL_OPCODE: Y 40034 ATTRIBUTES: MASKOP_EVEX 40035 PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 40036 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 40037 IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 40038 } 40039 40040 { 40041 ICLASS: VPERMT2D 40042 CPL: 3 40043 CATEGORY: AVX512 40044 EXTENSION: AVX512EVEX 40045 ISA_SET: AVX512F_128 40046 EXCEPTIONS: AVX512-E4NF 40047 REAL_OPCODE: Y 40048 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40049 PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 40050 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 40051 IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 40052 } 40053 40054 40055 # EMITTING VPERMT2D (VPERMT2D-256-1) 40056 { 40057 ICLASS: VPERMT2D 40058 CPL: 3 40059 CATEGORY: AVX512 40060 EXTENSION: AVX512EVEX 40061 ISA_SET: AVX512F_256 40062 EXCEPTIONS: AVX512-E4NF 40063 REAL_OPCODE: Y 40064 ATTRIBUTES: MASKOP_EVEX 40065 PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 40066 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 40067 IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 40068 } 40069 40070 { 40071 ICLASS: VPERMT2D 40072 CPL: 3 40073 CATEGORY: AVX512 40074 EXTENSION: AVX512EVEX 40075 ISA_SET: AVX512F_256 40076 EXCEPTIONS: AVX512-E4NF 40077 REAL_OPCODE: Y 40078 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40079 PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 40080 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 40081 IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 40082 } 40083 40084 40085 # EMITTING VPERMT2PD (VPERMT2PD-128-1) 40086 { 40087 ICLASS: VPERMT2PD 40088 CPL: 3 40089 CATEGORY: AVX512 40090 EXTENSION: AVX512EVEX 40091 ISA_SET: AVX512F_128 40092 EXCEPTIONS: AVX512-E4NF 40093 REAL_OPCODE: Y 40094 ATTRIBUTES: MASKOP_EVEX 40095 PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 40096 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 40097 IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 40098 } 40099 40100 { 40101 ICLASS: VPERMT2PD 40102 CPL: 3 40103 CATEGORY: AVX512 40104 EXTENSION: AVX512EVEX 40105 ISA_SET: AVX512F_128 40106 EXCEPTIONS: AVX512-E4NF 40107 REAL_OPCODE: Y 40108 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40109 PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 40110 OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 40111 IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 40112 } 40113 40114 40115 # EMITTING VPERMT2PD (VPERMT2PD-256-1) 40116 { 40117 ICLASS: VPERMT2PD 40118 CPL: 3 40119 CATEGORY: AVX512 40120 EXTENSION: AVX512EVEX 40121 ISA_SET: AVX512F_256 40122 EXCEPTIONS: AVX512-E4NF 40123 REAL_OPCODE: Y 40124 ATTRIBUTES: MASKOP_EVEX 40125 PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 40126 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 40127 IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 40128 } 40129 40130 { 40131 ICLASS: VPERMT2PD 40132 CPL: 3 40133 CATEGORY: AVX512 40134 EXTENSION: AVX512EVEX 40135 ISA_SET: AVX512F_256 40136 EXCEPTIONS: AVX512-E4NF 40137 REAL_OPCODE: Y 40138 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40139 PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 40140 OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 40141 IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 40142 } 40143 40144 40145 # EMITTING VPERMT2PS (VPERMT2PS-128-1) 40146 { 40147 ICLASS: VPERMT2PS 40148 CPL: 3 40149 CATEGORY: AVX512 40150 EXTENSION: AVX512EVEX 40151 ISA_SET: AVX512F_128 40152 EXCEPTIONS: AVX512-E4NF 40153 REAL_OPCODE: Y 40154 ATTRIBUTES: MASKOP_EVEX 40155 PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 40156 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 40157 IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 40158 } 40159 40160 { 40161 ICLASS: VPERMT2PS 40162 CPL: 3 40163 CATEGORY: AVX512 40164 EXTENSION: AVX512EVEX 40165 ISA_SET: AVX512F_128 40166 EXCEPTIONS: AVX512-E4NF 40167 REAL_OPCODE: Y 40168 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40169 PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 40170 OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 40171 IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 40172 } 40173 40174 40175 # EMITTING VPERMT2PS (VPERMT2PS-256-1) 40176 { 40177 ICLASS: VPERMT2PS 40178 CPL: 3 40179 CATEGORY: AVX512 40180 EXTENSION: AVX512EVEX 40181 ISA_SET: AVX512F_256 40182 EXCEPTIONS: AVX512-E4NF 40183 REAL_OPCODE: Y 40184 ATTRIBUTES: MASKOP_EVEX 40185 PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 40186 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 40187 IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 40188 } 40189 40190 { 40191 ICLASS: VPERMT2PS 40192 CPL: 3 40193 CATEGORY: AVX512 40194 EXTENSION: AVX512EVEX 40195 ISA_SET: AVX512F_256 40196 EXCEPTIONS: AVX512-E4NF 40197 REAL_OPCODE: Y 40198 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40199 PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 40200 OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 40201 IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 40202 } 40203 40204 40205 # EMITTING VPERMT2Q (VPERMT2Q-128-1) 40206 { 40207 ICLASS: VPERMT2Q 40208 CPL: 3 40209 CATEGORY: AVX512 40210 EXTENSION: AVX512EVEX 40211 ISA_SET: AVX512F_128 40212 EXCEPTIONS: AVX512-E4NF 40213 REAL_OPCODE: Y 40214 ATTRIBUTES: MASKOP_EVEX 40215 PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 40216 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 40217 IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 40218 } 40219 40220 { 40221 ICLASS: VPERMT2Q 40222 CPL: 3 40223 CATEGORY: AVX512 40224 EXTENSION: AVX512EVEX 40225 ISA_SET: AVX512F_128 40226 EXCEPTIONS: AVX512-E4NF 40227 REAL_OPCODE: Y 40228 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40229 PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 40230 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 40231 IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 40232 } 40233 40234 40235 # EMITTING VPERMT2Q (VPERMT2Q-256-1) 40236 { 40237 ICLASS: VPERMT2Q 40238 CPL: 3 40239 CATEGORY: AVX512 40240 EXTENSION: AVX512EVEX 40241 ISA_SET: AVX512F_256 40242 EXCEPTIONS: AVX512-E4NF 40243 REAL_OPCODE: Y 40244 ATTRIBUTES: MASKOP_EVEX 40245 PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 40246 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 40247 IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 40248 } 40249 40250 { 40251 ICLASS: VPERMT2Q 40252 CPL: 3 40253 CATEGORY: AVX512 40254 EXTENSION: AVX512EVEX 40255 ISA_SET: AVX512F_256 40256 EXCEPTIONS: AVX512-E4NF 40257 REAL_OPCODE: Y 40258 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40259 PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 40260 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 40261 IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 40262 } 40263 40264 40265 # EMITTING VPERMT2W (VPERMT2W-128-1) 40266 { 40267 ICLASS: VPERMT2W 40268 CPL: 3 40269 CATEGORY: AVX512 40270 EXTENSION: AVX512EVEX 40271 ISA_SET: AVX512BW_128 40272 EXCEPTIONS: AVX512-E4NF 40273 REAL_OPCODE: Y 40274 ATTRIBUTES: MASKOP_EVEX 40275 PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 40276 OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 40277 IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 40278 } 40279 40280 { 40281 ICLASS: VPERMT2W 40282 CPL: 3 40283 CATEGORY: AVX512 40284 EXTENSION: AVX512EVEX 40285 ISA_SET: AVX512BW_128 40286 EXCEPTIONS: AVX512-E4NF 40287 REAL_OPCODE: Y 40288 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 40289 PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 40290 OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 40291 IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 40292 } 40293 40294 40295 # EMITTING VPERMT2W (VPERMT2W-256-1) 40296 { 40297 ICLASS: VPERMT2W 40298 CPL: 3 40299 CATEGORY: AVX512 40300 EXTENSION: AVX512EVEX 40301 ISA_SET: AVX512BW_256 40302 EXCEPTIONS: AVX512-E4NF 40303 REAL_OPCODE: Y 40304 ATTRIBUTES: MASKOP_EVEX 40305 PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 40306 OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 40307 IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 40308 } 40309 40310 { 40311 ICLASS: VPERMT2W 40312 CPL: 3 40313 CATEGORY: AVX512 40314 EXTENSION: AVX512EVEX 40315 ISA_SET: AVX512BW_256 40316 EXCEPTIONS: AVX512-E4NF 40317 REAL_OPCODE: Y 40318 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 40319 PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 40320 OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 40321 IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 40322 } 40323 40324 40325 # EMITTING VPERMT2W (VPERMT2W-512-1) 40326 { 40327 ICLASS: VPERMT2W 40328 CPL: 3 40329 CATEGORY: AVX512 40330 EXTENSION: AVX512EVEX 40331 ISA_SET: AVX512BW_512 40332 EXCEPTIONS: AVX512-E4NF 40333 REAL_OPCODE: Y 40334 ATTRIBUTES: MASKOP_EVEX 40335 PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 40336 OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 40337 IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 40338 } 40339 40340 { 40341 ICLASS: VPERMT2W 40342 CPL: 3 40343 CATEGORY: AVX512 40344 EXTENSION: AVX512EVEX 40345 ISA_SET: AVX512BW_512 40346 EXCEPTIONS: AVX512-E4NF 40347 REAL_OPCODE: Y 40348 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 40349 PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 40350 OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 40351 IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 40352 } 40353 40354 40355 # EMITTING VPERMW (VPERMW-128-1) 40356 { 40357 ICLASS: VPERMW 40358 CPL: 3 40359 CATEGORY: AVX512 40360 EXTENSION: AVX512EVEX 40361 ISA_SET: AVX512BW_128 40362 EXCEPTIONS: AVX512-E4NF 40363 REAL_OPCODE: Y 40364 ATTRIBUTES: MASKOP_EVEX 40365 PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 40366 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 40367 IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 40368 } 40369 40370 { 40371 ICLASS: VPERMW 40372 CPL: 3 40373 CATEGORY: AVX512 40374 EXTENSION: AVX512EVEX 40375 ISA_SET: AVX512BW_128 40376 EXCEPTIONS: AVX512-E4NF 40377 REAL_OPCODE: Y 40378 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 40379 PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 40380 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 40381 IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 40382 } 40383 40384 40385 # EMITTING VPERMW (VPERMW-256-1) 40386 { 40387 ICLASS: VPERMW 40388 CPL: 3 40389 CATEGORY: AVX512 40390 EXTENSION: AVX512EVEX 40391 ISA_SET: AVX512BW_256 40392 EXCEPTIONS: AVX512-E4NF 40393 REAL_OPCODE: Y 40394 ATTRIBUTES: MASKOP_EVEX 40395 PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 40396 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 40397 IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 40398 } 40399 40400 { 40401 ICLASS: VPERMW 40402 CPL: 3 40403 CATEGORY: AVX512 40404 EXTENSION: AVX512EVEX 40405 ISA_SET: AVX512BW_256 40406 EXCEPTIONS: AVX512-E4NF 40407 REAL_OPCODE: Y 40408 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 40409 PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 40410 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 40411 IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 40412 } 40413 40414 40415 # EMITTING VPERMW (VPERMW-512-1) 40416 { 40417 ICLASS: VPERMW 40418 CPL: 3 40419 CATEGORY: AVX512 40420 EXTENSION: AVX512EVEX 40421 ISA_SET: AVX512BW_512 40422 EXCEPTIONS: AVX512-E4NF 40423 REAL_OPCODE: Y 40424 ATTRIBUTES: MASKOP_EVEX 40425 PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 40426 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 40427 IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 40428 } 40429 40430 { 40431 ICLASS: VPERMW 40432 CPL: 3 40433 CATEGORY: AVX512 40434 EXTENSION: AVX512EVEX 40435 ISA_SET: AVX512BW_512 40436 EXCEPTIONS: AVX512-E4NF 40437 REAL_OPCODE: Y 40438 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 40439 PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 40440 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 40441 IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 40442 } 40443 40444 40445 # EMITTING VPEXPANDD (VPEXPANDD-128-1) 40446 { 40447 ICLASS: VPEXPANDD 40448 CPL: 3 40449 CATEGORY: EXPAND 40450 EXTENSION: AVX512EVEX 40451 ISA_SET: AVX512F_128 40452 EXCEPTIONS: AVX512-E4 40453 REAL_OPCODE: Y 40454 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 40455 PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() 40456 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 40457 IFORM: VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 40458 } 40459 40460 40461 # EMITTING VPEXPANDD (VPEXPANDD-128-2) 40462 { 40463 ICLASS: VPEXPANDD 40464 CPL: 3 40465 CATEGORY: EXPAND 40466 EXTENSION: AVX512EVEX 40467 ISA_SET: AVX512F_128 40468 EXCEPTIONS: AVX512-E4 40469 REAL_OPCODE: Y 40470 ATTRIBUTES: MASKOP_EVEX 40471 PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 40472 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 40473 IFORM: VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 40474 } 40475 40476 40477 # EMITTING VPEXPANDD (VPEXPANDD-256-1) 40478 { 40479 ICLASS: VPEXPANDD 40480 CPL: 3 40481 CATEGORY: EXPAND 40482 EXTENSION: AVX512EVEX 40483 ISA_SET: AVX512F_256 40484 EXCEPTIONS: AVX512-E4 40485 REAL_OPCODE: Y 40486 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 40487 PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() 40488 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 40489 IFORM: VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 40490 } 40491 40492 40493 # EMITTING VPEXPANDD (VPEXPANDD-256-2) 40494 { 40495 ICLASS: VPEXPANDD 40496 CPL: 3 40497 CATEGORY: EXPAND 40498 EXTENSION: AVX512EVEX 40499 ISA_SET: AVX512F_256 40500 EXCEPTIONS: AVX512-E4 40501 REAL_OPCODE: Y 40502 ATTRIBUTES: MASKOP_EVEX 40503 PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 40504 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 40505 IFORM: VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 40506 } 40507 40508 40509 # EMITTING VPEXPANDQ (VPEXPANDQ-128-1) 40510 { 40511 ICLASS: VPEXPANDQ 40512 CPL: 3 40513 CATEGORY: EXPAND 40514 EXTENSION: AVX512EVEX 40515 ISA_SET: AVX512F_128 40516 EXCEPTIONS: AVX512-E4 40517 REAL_OPCODE: Y 40518 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 40519 PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() 40520 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 40521 IFORM: VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 40522 } 40523 40524 40525 # EMITTING VPEXPANDQ (VPEXPANDQ-128-2) 40526 { 40527 ICLASS: VPEXPANDQ 40528 CPL: 3 40529 CATEGORY: EXPAND 40530 EXTENSION: AVX512EVEX 40531 ISA_SET: AVX512F_128 40532 EXCEPTIONS: AVX512-E4 40533 REAL_OPCODE: Y 40534 ATTRIBUTES: MASKOP_EVEX 40535 PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 40536 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 40537 IFORM: VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 40538 } 40539 40540 40541 # EMITTING VPEXPANDQ (VPEXPANDQ-256-1) 40542 { 40543 ICLASS: VPEXPANDQ 40544 CPL: 3 40545 CATEGORY: EXPAND 40546 EXTENSION: AVX512EVEX 40547 ISA_SET: AVX512F_256 40548 EXCEPTIONS: AVX512-E4 40549 REAL_OPCODE: Y 40550 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 40551 PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() 40552 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 40553 IFORM: VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 40554 } 40555 40556 40557 # EMITTING VPEXPANDQ (VPEXPANDQ-256-2) 40558 { 40559 ICLASS: VPEXPANDQ 40560 CPL: 3 40561 CATEGORY: EXPAND 40562 EXTENSION: AVX512EVEX 40563 ISA_SET: AVX512F_256 40564 EXCEPTIONS: AVX512-E4 40565 REAL_OPCODE: Y 40566 ATTRIBUTES: MASKOP_EVEX 40567 PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 40568 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 40569 IFORM: VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 40570 } 40571 40572 40573 # EMITTING VPEXTRB (VPEXTRB-128-1) 40574 { 40575 ICLASS: VPEXTRB 40576 CPL: 3 40577 CATEGORY: AVX512 40578 EXTENSION: AVX512EVEX 40579 ISA_SET: AVX512BW_128N 40580 EXCEPTIONS: AVX512-E9NF 40581 REAL_OPCODE: Y 40582 PATTERN: EVV 0x14 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() 40583 OPERANDS: REG0=GPR32_B():w:d:u8 REG1=XMM_R3():r:dq:u8 IMM0:r:b 40584 IFORM: VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 40585 } 40586 40587 { 40588 ICLASS: VPEXTRB 40589 CPL: 3 40590 CATEGORY: AVX512 40591 EXTENSION: AVX512EVEX 40592 ISA_SET: AVX512BW_128N 40593 EXCEPTIONS: AVX512-E9NF 40594 REAL_OPCODE: Y 40595 ATTRIBUTES: DISP8_GPR_WRITER_STORE_BYTE 40596 PATTERN: EVV 0x14 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_WRITER_STORE_BYTE() 40597 OPERANDS: MEM0:w:b:u8 REG0=XMM_R3():r:dq:u8 IMM0:r:b 40598 IFORM: VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 40599 } 40600 40601 40602 # EMITTING VPEXTRD (VPEXTRD-128-1) 40603 { 40604 ICLASS: VPEXTRD 40605 CPL: 3 40606 CATEGORY: AVX512 40607 EXTENSION: AVX512EVEX 40608 ISA_SET: AVX512DQ_128N 40609 EXCEPTIONS: AVX512-E9NF 40610 REAL_OPCODE: Y 40611 PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() 40612 OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b 40613 IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 40614 PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() 40615 OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b 40616 IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 40617 } 40618 40619 { 40620 ICLASS: VPEXTRD 40621 CPL: 3 40622 CATEGORY: AVX512 40623 EXTENSION: AVX512EVEX 40624 ISA_SET: AVX512DQ_128N 40625 EXCEPTIONS: AVX512-E9NF 40626 REAL_OPCODE: Y 40627 ATTRIBUTES: DISP8_GPR_WRITER_STORE 40628 PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() 40629 OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b 40630 IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 40631 PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() 40632 OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b 40633 IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 40634 } 40635 40636 40637 # EMITTING VPEXTRQ (VPEXTRQ-128-1) 40638 { 40639 ICLASS: VPEXTRQ 40640 CPL: 3 40641 CATEGORY: AVX512 40642 EXTENSION: AVX512EVEX 40643 ISA_SET: AVX512DQ_128N 40644 EXCEPTIONS: AVX512-E9NF 40645 REAL_OPCODE: Y 40646 PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() 40647 OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 IMM0:r:b 40648 IFORM: VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 40649 } 40650 40651 { 40652 ICLASS: VPEXTRQ 40653 CPL: 3 40654 CATEGORY: AVX512 40655 EXTENSION: AVX512EVEX 40656 ISA_SET: AVX512DQ_128N 40657 EXCEPTIONS: AVX512-E9NF 40658 REAL_OPCODE: Y 40659 ATTRIBUTES: DISP8_GPR_WRITER_STORE 40660 PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() 40661 OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 IMM0:r:b 40662 IFORM: VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 40663 } 40664 40665 40666 # EMITTING VPEXTRW (VPEXTRW-128-1) 40667 { 40668 ICLASS: VPEXTRW 40669 CPL: 3 40670 CATEGORY: AVX512 40671 EXTENSION: AVX512EVEX 40672 ISA_SET: AVX512BW_128N 40673 EXCEPTIONS: AVX512-E9NF 40674 REAL_OPCODE: Y 40675 PATTERN: EVV 0x15 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() 40676 OPERANDS: REG0=GPR32_B():w:d:u16 REG1=XMM_R3():r:dq:u16 IMM0:r:b 40677 IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 40678 } 40679 40680 { 40681 ICLASS: VPEXTRW 40682 CPL: 3 40683 CATEGORY: AVX512 40684 EXTENSION: AVX512EVEX 40685 ISA_SET: AVX512BW_128N 40686 EXCEPTIONS: AVX512-E9NF 40687 REAL_OPCODE: Y 40688 ATTRIBUTES: DISP8_GPR_WRITER_STORE_WORD 40689 PATTERN: EVV 0x15 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_WRITER_STORE_WORD() 40690 OPERANDS: MEM0:w:wrd:u16 REG0=XMM_R3():r:dq:u16 IMM0:r:b 40691 IFORM: VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 40692 } 40693 40694 40695 # EMITTING VPEXTRW (VPEXTRW-128-2) 40696 { 40697 ICLASS: VPEXTRW_C5 40698 DISASM: vpextrw 40699 CPL: 3 40700 CATEGORY: AVX512 40701 EXTENSION: AVX512EVEX 40702 ISA_SET: AVX512BW_128N 40703 EXCEPTIONS: AVX512-E9NF 40704 REAL_OPCODE: Y 40705 40706 PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() not64 40707 OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b 40708 IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 40709 40710 PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() mode64 EVEXRR_ONE 40711 OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b 40712 IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 40713 } 40714 40715 40716 # EMITTING VPGATHERDD (VPGATHERDD-128-2) 40717 { 40718 ICLASS: VPGATHERDD 40719 CPL: 3 40720 CATEGORY: GATHER 40721 EXTENSION: AVX512EVEX 40722 ISA_SET: AVX512F_128 40723 EXCEPTIONS: AVX512-E12 40724 REAL_OPCODE: Y 40725 ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 40726 PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 40727 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 40728 IFORM: VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 40729 } 40730 40731 40732 # EMITTING VPGATHERDD (VPGATHERDD-256-2) 40733 { 40734 ICLASS: VPGATHERDD 40735 CPL: 3 40736 CATEGORY: GATHER 40737 EXTENSION: AVX512EVEX 40738 ISA_SET: AVX512F_256 40739 EXCEPTIONS: AVX512-E12 40740 REAL_OPCODE: Y 40741 ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 40742 PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 40743 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 40744 IFORM: VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 40745 } 40746 40747 40748 # EMITTING VPGATHERDQ (VPGATHERDQ-128-2) 40749 { 40750 ICLASS: VPGATHERDQ 40751 CPL: 3 40752 CATEGORY: GATHER 40753 EXTENSION: AVX512EVEX 40754 ISA_SET: AVX512F_128 40755 EXCEPTIONS: AVX512-E12 40756 REAL_OPCODE: Y 40757 ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 40758 PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 40759 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 40760 IFORM: VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 40761 } 40762 40763 40764 # EMITTING VPGATHERDQ (VPGATHERDQ-256-2) 40765 { 40766 ICLASS: VPGATHERDQ 40767 CPL: 3 40768 CATEGORY: GATHER 40769 EXTENSION: AVX512EVEX 40770 ISA_SET: AVX512F_256 40771 EXCEPTIONS: AVX512-E12 40772 REAL_OPCODE: Y 40773 ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 40774 PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 40775 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 40776 IFORM: VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 40777 } 40778 40779 40780 # EMITTING VPGATHERQD (VPGATHERQD-128-2) 40781 { 40782 ICLASS: VPGATHERQD 40783 CPL: 3 40784 CATEGORY: GATHER 40785 EXTENSION: AVX512EVEX 40786 ISA_SET: AVX512F_128 40787 EXCEPTIONS: AVX512-E12 40788 REAL_OPCODE: Y 40789 ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 40790 PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 40791 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 40792 IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 40793 } 40794 40795 40796 # EMITTING VPGATHERQD (VPGATHERQD-256-2) 40797 { 40798 ICLASS: VPGATHERQD 40799 CPL: 3 40800 CATEGORY: GATHER 40801 EXTENSION: AVX512EVEX 40802 ISA_SET: AVX512F_256 40803 EXCEPTIONS: AVX512-E12 40804 REAL_OPCODE: Y 40805 ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 40806 PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 40807 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 40808 IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 40809 } 40810 40811 40812 # EMITTING VPGATHERQQ (VPGATHERQQ-128-2) 40813 { 40814 ICLASS: VPGATHERQQ 40815 CPL: 3 40816 CATEGORY: GATHER 40817 EXTENSION: AVX512EVEX 40818 ISA_SET: AVX512F_128 40819 EXCEPTIONS: AVX512-E12 40820 REAL_OPCODE: Y 40821 ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 40822 PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 40823 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 40824 IFORM: VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 40825 } 40826 40827 40828 # EMITTING VPGATHERQQ (VPGATHERQQ-256-2) 40829 { 40830 ICLASS: VPGATHERQQ 40831 CPL: 3 40832 CATEGORY: GATHER 40833 EXTENSION: AVX512EVEX 40834 ISA_SET: AVX512F_256 40835 EXCEPTIONS: AVX512-E12 40836 REAL_OPCODE: Y 40837 ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED 40838 PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 40839 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 40840 IFORM: VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 40841 } 40842 40843 40844 # EMITTING VPINSRB (VPINSRB-128-1) 40845 { 40846 ICLASS: VPINSRB 40847 CPL: 3 40848 CATEGORY: AVX512 40849 EXTENSION: AVX512EVEX 40850 ISA_SET: AVX512BW_128N 40851 EXCEPTIONS: AVX512-E9NF 40852 REAL_OPCODE: Y 40853 PATTERN: EVV 0x20 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() 40854 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b 40855 IFORM: VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 40856 } 40857 40858 { 40859 ICLASS: VPINSRB 40860 CPL: 3 40861 CATEGORY: AVX512 40862 EXTENSION: AVX512EVEX 40863 ISA_SET: AVX512BW_128N 40864 EXCEPTIONS: AVX512-E9NF 40865 REAL_OPCODE: Y 40866 ATTRIBUTES: DISP8_GPR_READER_BYTE 40867 PATTERN: EVV 0x20 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_READER_BYTE() 40868 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 MEM0:r:b:u8 IMM0:r:b 40869 IFORM: VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 40870 } 40871 40872 40873 # EMITTING VPINSRD (VPINSRD-128-1) 40874 { 40875 ICLASS: VPINSRD 40876 CPL: 3 40877 CATEGORY: AVX512 40878 EXTENSION: AVX512EVEX 40879 ISA_SET: AVX512DQ_128N 40880 EXCEPTIONS: AVX512-E9NF 40881 REAL_OPCODE: Y 40882 PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 ZEROING=0 MASK=0 UIMM8() 40883 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b 40884 IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 40885 PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() 40886 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b 40887 IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 40888 } 40889 40890 { 40891 ICLASS: VPINSRD 40892 CPL: 3 40893 CATEGORY: AVX512 40894 EXTENSION: AVX512EVEX 40895 ISA_SET: AVX512DQ_128N 40896 EXCEPTIONS: AVX512-E9NF 40897 REAL_OPCODE: Y 40898 ATTRIBUTES: DISP8_GPR_READER 40899 PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() 40900 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b 40901 IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 40902 PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() 40903 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b 40904 IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 40905 } 40906 40907 40908 # EMITTING VPINSRQ (VPINSRQ-128-1) 40909 { 40910 ICLASS: VPINSRQ 40911 CPL: 3 40912 CATEGORY: AVX512 40913 EXTENSION: AVX512EVEX 40914 ISA_SET: AVX512DQ_128N 40915 EXCEPTIONS: AVX512-E9NF 40916 REAL_OPCODE: Y 40917 PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() 40918 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b 40919 IFORM: VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 40920 } 40921 40922 { 40923 ICLASS: VPINSRQ 40924 CPL: 3 40925 CATEGORY: AVX512 40926 EXTENSION: AVX512EVEX 40927 ISA_SET: AVX512DQ_128N 40928 EXCEPTIONS: AVX512-E9NF 40929 REAL_OPCODE: Y 40930 ATTRIBUTES: DISP8_GPR_READER 40931 PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER() 40932 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 MEM0:r:q:u64 IMM0:r:b 40933 IFORM: VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 40934 } 40935 40936 40937 # EMITTING VPINSRW (VPINSRW-128-1) 40938 { 40939 ICLASS: VPINSRW 40940 CPL: 3 40941 CATEGORY: AVX512 40942 EXTENSION: AVX512EVEX 40943 ISA_SET: AVX512BW_128N 40944 EXCEPTIONS: AVX512-E9NF 40945 REAL_OPCODE: Y 40946 PATTERN: EVV 0xC4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() 40947 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b 40948 IFORM: VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 40949 } 40950 40951 { 40952 ICLASS: VPINSRW 40953 CPL: 3 40954 CATEGORY: AVX512 40955 EXTENSION: AVX512EVEX 40956 ISA_SET: AVX512BW_128N 40957 EXCEPTIONS: AVX512-E9NF 40958 REAL_OPCODE: Y 40959 ATTRIBUTES: DISP8_GPR_READER_WORD 40960 PATTERN: EVV 0xC4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_READER_WORD() 40961 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 MEM0:r:wrd:u16 IMM0:r:b 40962 IFORM: VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 40963 } 40964 40965 40966 # EMITTING VPLZCNTD (VPLZCNTD-128-1) 40967 { 40968 ICLASS: VPLZCNTD 40969 CPL: 3 40970 CATEGORY: CONFLICT 40971 EXTENSION: AVX512EVEX 40972 ISA_SET: AVX512CD_128 40973 EXCEPTIONS: AVX512-E4 40974 REAL_OPCODE: Y 40975 ATTRIBUTES: MASKOP_EVEX 40976 PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 40977 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 40978 IFORM: VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 40979 } 40980 40981 { 40982 ICLASS: VPLZCNTD 40983 CPL: 3 40984 CATEGORY: CONFLICT 40985 EXTENSION: AVX512EVEX 40986 ISA_SET: AVX512CD_128 40987 EXCEPTIONS: AVX512-E4 40988 REAL_OPCODE: Y 40989 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 40990 PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 40991 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 40992 IFORM: VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 40993 } 40994 40995 40996 # EMITTING VPLZCNTD (VPLZCNTD-256-1) 40997 { 40998 ICLASS: VPLZCNTD 40999 CPL: 3 41000 CATEGORY: CONFLICT 41001 EXTENSION: AVX512EVEX 41002 ISA_SET: AVX512CD_256 41003 EXCEPTIONS: AVX512-E4 41004 REAL_OPCODE: Y 41005 ATTRIBUTES: MASKOP_EVEX 41006 PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 41007 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 41008 IFORM: VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 41009 } 41010 41011 { 41012 ICLASS: VPLZCNTD 41013 CPL: 3 41014 CATEGORY: CONFLICT 41015 EXTENSION: AVX512EVEX 41016 ISA_SET: AVX512CD_256 41017 EXCEPTIONS: AVX512-E4 41018 REAL_OPCODE: Y 41019 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41020 PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 41021 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 41022 IFORM: VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 41023 } 41024 41025 41026 # EMITTING VPLZCNTQ (VPLZCNTQ-128-1) 41027 { 41028 ICLASS: VPLZCNTQ 41029 CPL: 3 41030 CATEGORY: CONFLICT 41031 EXTENSION: AVX512EVEX 41032 ISA_SET: AVX512CD_128 41033 EXCEPTIONS: AVX512-E4 41034 REAL_OPCODE: Y 41035 ATTRIBUTES: MASKOP_EVEX 41036 PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 41037 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 41038 IFORM: VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 41039 } 41040 41041 { 41042 ICLASS: VPLZCNTQ 41043 CPL: 3 41044 CATEGORY: CONFLICT 41045 EXTENSION: AVX512EVEX 41046 ISA_SET: AVX512CD_128 41047 EXCEPTIONS: AVX512-E4 41048 REAL_OPCODE: Y 41049 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41050 PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 41051 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 41052 IFORM: VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 41053 } 41054 41055 41056 # EMITTING VPLZCNTQ (VPLZCNTQ-256-1) 41057 { 41058 ICLASS: VPLZCNTQ 41059 CPL: 3 41060 CATEGORY: CONFLICT 41061 EXTENSION: AVX512EVEX 41062 ISA_SET: AVX512CD_256 41063 EXCEPTIONS: AVX512-E4 41064 REAL_OPCODE: Y 41065 ATTRIBUTES: MASKOP_EVEX 41066 PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 41067 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 41068 IFORM: VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 41069 } 41070 41071 { 41072 ICLASS: VPLZCNTQ 41073 CPL: 3 41074 CATEGORY: CONFLICT 41075 EXTENSION: AVX512EVEX 41076 ISA_SET: AVX512CD_256 41077 EXCEPTIONS: AVX512-E4 41078 REAL_OPCODE: Y 41079 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41080 PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 41081 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 41082 IFORM: VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 41083 } 41084 41085 41086 # EMITTING VPMADDUBSW (VPMADDUBSW-128-1) 41087 { 41088 ICLASS: VPMADDUBSW 41089 CPL: 3 41090 CATEGORY: AVX512 41091 EXTENSION: AVX512EVEX 41092 ISA_SET: AVX512BW_128 41093 EXCEPTIONS: AVX512-E4NF 41094 REAL_OPCODE: Y 41095 ATTRIBUTES: MASKOP_EVEX 41096 PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 41097 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 41098 IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 41099 } 41100 41101 { 41102 ICLASS: VPMADDUBSW 41103 CPL: 3 41104 CATEGORY: AVX512 41105 EXTENSION: AVX512EVEX 41106 ISA_SET: AVX512BW_128 41107 EXCEPTIONS: AVX512-E4NF 41108 REAL_OPCODE: Y 41109 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 41110 PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 41111 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 41112 IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 41113 } 41114 41115 41116 # EMITTING VPMADDUBSW (VPMADDUBSW-256-1) 41117 { 41118 ICLASS: VPMADDUBSW 41119 CPL: 3 41120 CATEGORY: AVX512 41121 EXTENSION: AVX512EVEX 41122 ISA_SET: AVX512BW_256 41123 EXCEPTIONS: AVX512-E4NF 41124 REAL_OPCODE: Y 41125 ATTRIBUTES: MASKOP_EVEX 41126 PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 41127 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 41128 IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 41129 } 41130 41131 { 41132 ICLASS: VPMADDUBSW 41133 CPL: 3 41134 CATEGORY: AVX512 41135 EXTENSION: AVX512EVEX 41136 ISA_SET: AVX512BW_256 41137 EXCEPTIONS: AVX512-E4NF 41138 REAL_OPCODE: Y 41139 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 41140 PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 41141 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 41142 IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 41143 } 41144 41145 41146 # EMITTING VPMADDUBSW (VPMADDUBSW-512-1) 41147 { 41148 ICLASS: VPMADDUBSW 41149 CPL: 3 41150 CATEGORY: AVX512 41151 EXTENSION: AVX512EVEX 41152 ISA_SET: AVX512BW_512 41153 EXCEPTIONS: AVX512-E4NF 41154 REAL_OPCODE: Y 41155 ATTRIBUTES: MASKOP_EVEX 41156 PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 41157 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 41158 IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 41159 } 41160 41161 { 41162 ICLASS: VPMADDUBSW 41163 CPL: 3 41164 CATEGORY: AVX512 41165 EXTENSION: AVX512EVEX 41166 ISA_SET: AVX512BW_512 41167 EXCEPTIONS: AVX512-E4NF 41168 REAL_OPCODE: Y 41169 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 41170 PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 41171 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 41172 IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 41173 } 41174 41175 41176 # EMITTING VPMADDWD (VPMADDWD-128-1) 41177 { 41178 ICLASS: VPMADDWD 41179 CPL: 3 41180 CATEGORY: AVX512 41181 EXTENSION: AVX512EVEX 41182 ISA_SET: AVX512BW_128 41183 EXCEPTIONS: AVX512-E4NF 41184 REAL_OPCODE: Y 41185 ATTRIBUTES: MASKOP_EVEX 41186 PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 41187 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 41188 IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 41189 } 41190 41191 { 41192 ICLASS: VPMADDWD 41193 CPL: 3 41194 CATEGORY: AVX512 41195 EXTENSION: AVX512EVEX 41196 ISA_SET: AVX512BW_128 41197 EXCEPTIONS: AVX512-E4NF 41198 REAL_OPCODE: Y 41199 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 41200 PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 41201 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 41202 IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 41203 } 41204 41205 41206 # EMITTING VPMADDWD (VPMADDWD-256-1) 41207 { 41208 ICLASS: VPMADDWD 41209 CPL: 3 41210 CATEGORY: AVX512 41211 EXTENSION: AVX512EVEX 41212 ISA_SET: AVX512BW_256 41213 EXCEPTIONS: AVX512-E4NF 41214 REAL_OPCODE: Y 41215 ATTRIBUTES: MASKOP_EVEX 41216 PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 41217 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 41218 IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 41219 } 41220 41221 { 41222 ICLASS: VPMADDWD 41223 CPL: 3 41224 CATEGORY: AVX512 41225 EXTENSION: AVX512EVEX 41226 ISA_SET: AVX512BW_256 41227 EXCEPTIONS: AVX512-E4NF 41228 REAL_OPCODE: Y 41229 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 41230 PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 41231 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 41232 IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 41233 } 41234 41235 41236 # EMITTING VPMADDWD (VPMADDWD-512-1) 41237 { 41238 ICLASS: VPMADDWD 41239 CPL: 3 41240 CATEGORY: AVX512 41241 EXTENSION: AVX512EVEX 41242 ISA_SET: AVX512BW_512 41243 EXCEPTIONS: AVX512-E4NF 41244 REAL_OPCODE: Y 41245 ATTRIBUTES: MASKOP_EVEX 41246 PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 41247 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 41248 IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 41249 } 41250 41251 { 41252 ICLASS: VPMADDWD 41253 CPL: 3 41254 CATEGORY: AVX512 41255 EXTENSION: AVX512EVEX 41256 ISA_SET: AVX512BW_512 41257 EXCEPTIONS: AVX512-E4NF 41258 REAL_OPCODE: Y 41259 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 41260 PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 41261 OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 41262 IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 41263 } 41264 41265 41266 # EMITTING VPMAXSB (VPMAXSB-128-1) 41267 { 41268 ICLASS: VPMAXSB 41269 CPL: 3 41270 CATEGORY: AVX512 41271 EXTENSION: AVX512EVEX 41272 ISA_SET: AVX512BW_128 41273 EXCEPTIONS: AVX512-E4 41274 REAL_OPCODE: Y 41275 ATTRIBUTES: MASKOP_EVEX 41276 PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 41277 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 41278 IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 41279 } 41280 41281 { 41282 ICLASS: VPMAXSB 41283 CPL: 3 41284 CATEGORY: AVX512 41285 EXTENSION: AVX512EVEX 41286 ISA_SET: AVX512BW_128 41287 EXCEPTIONS: AVX512-E4 41288 REAL_OPCODE: Y 41289 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41290 PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 41291 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 41292 IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 41293 } 41294 41295 41296 # EMITTING VPMAXSB (VPMAXSB-256-1) 41297 { 41298 ICLASS: VPMAXSB 41299 CPL: 3 41300 CATEGORY: AVX512 41301 EXTENSION: AVX512EVEX 41302 ISA_SET: AVX512BW_256 41303 EXCEPTIONS: AVX512-E4 41304 REAL_OPCODE: Y 41305 ATTRIBUTES: MASKOP_EVEX 41306 PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 41307 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 41308 IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 41309 } 41310 41311 { 41312 ICLASS: VPMAXSB 41313 CPL: 3 41314 CATEGORY: AVX512 41315 EXTENSION: AVX512EVEX 41316 ISA_SET: AVX512BW_256 41317 EXCEPTIONS: AVX512-E4 41318 REAL_OPCODE: Y 41319 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41320 PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 41321 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 41322 IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 41323 } 41324 41325 41326 # EMITTING VPMAXSB (VPMAXSB-512-1) 41327 { 41328 ICLASS: VPMAXSB 41329 CPL: 3 41330 CATEGORY: AVX512 41331 EXTENSION: AVX512EVEX 41332 ISA_SET: AVX512BW_512 41333 EXCEPTIONS: AVX512-E4 41334 REAL_OPCODE: Y 41335 ATTRIBUTES: MASKOP_EVEX 41336 PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 41337 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 41338 IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 41339 } 41340 41341 { 41342 ICLASS: VPMAXSB 41343 CPL: 3 41344 CATEGORY: AVX512 41345 EXTENSION: AVX512EVEX 41346 ISA_SET: AVX512BW_512 41347 EXCEPTIONS: AVX512-E4 41348 REAL_OPCODE: Y 41349 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41350 PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 41351 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 41352 IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 41353 } 41354 41355 41356 # EMITTING VPMAXSD (VPMAXSD-128-1) 41357 { 41358 ICLASS: VPMAXSD 41359 CPL: 3 41360 CATEGORY: AVX512 41361 EXTENSION: AVX512EVEX 41362 ISA_SET: AVX512F_128 41363 EXCEPTIONS: AVX512-E4 41364 REAL_OPCODE: Y 41365 ATTRIBUTES: MASKOP_EVEX 41366 PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 41367 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 41368 IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 41369 } 41370 41371 { 41372 ICLASS: VPMAXSD 41373 CPL: 3 41374 CATEGORY: AVX512 41375 EXTENSION: AVX512EVEX 41376 ISA_SET: AVX512F_128 41377 EXCEPTIONS: AVX512-E4 41378 REAL_OPCODE: Y 41379 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41380 PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 41381 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 41382 IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 41383 } 41384 41385 41386 # EMITTING VPMAXSD (VPMAXSD-256-1) 41387 { 41388 ICLASS: VPMAXSD 41389 CPL: 3 41390 CATEGORY: AVX512 41391 EXTENSION: AVX512EVEX 41392 ISA_SET: AVX512F_256 41393 EXCEPTIONS: AVX512-E4 41394 REAL_OPCODE: Y 41395 ATTRIBUTES: MASKOP_EVEX 41396 PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 41397 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 41398 IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 41399 } 41400 41401 { 41402 ICLASS: VPMAXSD 41403 CPL: 3 41404 CATEGORY: AVX512 41405 EXTENSION: AVX512EVEX 41406 ISA_SET: AVX512F_256 41407 EXCEPTIONS: AVX512-E4 41408 REAL_OPCODE: Y 41409 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41410 PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 41411 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 41412 IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 41413 } 41414 41415 41416 # EMITTING VPMAXSQ (VPMAXSQ-128-1) 41417 { 41418 ICLASS: VPMAXSQ 41419 CPL: 3 41420 CATEGORY: AVX512 41421 EXTENSION: AVX512EVEX 41422 ISA_SET: AVX512F_128 41423 EXCEPTIONS: AVX512-E4 41424 REAL_OPCODE: Y 41425 ATTRIBUTES: MASKOP_EVEX 41426 PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 41427 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 41428 IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 41429 } 41430 41431 { 41432 ICLASS: VPMAXSQ 41433 CPL: 3 41434 CATEGORY: AVX512 41435 EXTENSION: AVX512EVEX 41436 ISA_SET: AVX512F_128 41437 EXCEPTIONS: AVX512-E4 41438 REAL_OPCODE: Y 41439 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41440 PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 41441 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 41442 IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 41443 } 41444 41445 41446 # EMITTING VPMAXSQ (VPMAXSQ-256-1) 41447 { 41448 ICLASS: VPMAXSQ 41449 CPL: 3 41450 CATEGORY: AVX512 41451 EXTENSION: AVX512EVEX 41452 ISA_SET: AVX512F_256 41453 EXCEPTIONS: AVX512-E4 41454 REAL_OPCODE: Y 41455 ATTRIBUTES: MASKOP_EVEX 41456 PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 41457 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 41458 IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 41459 } 41460 41461 { 41462 ICLASS: VPMAXSQ 41463 CPL: 3 41464 CATEGORY: AVX512 41465 EXTENSION: AVX512EVEX 41466 ISA_SET: AVX512F_256 41467 EXCEPTIONS: AVX512-E4 41468 REAL_OPCODE: Y 41469 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41470 PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 41471 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 41472 IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 41473 } 41474 41475 41476 # EMITTING VPMAXSW (VPMAXSW-128-1) 41477 { 41478 ICLASS: VPMAXSW 41479 CPL: 3 41480 CATEGORY: AVX512 41481 EXTENSION: AVX512EVEX 41482 ISA_SET: AVX512BW_128 41483 EXCEPTIONS: AVX512-E4 41484 REAL_OPCODE: Y 41485 ATTRIBUTES: MASKOP_EVEX 41486 PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 41487 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 41488 IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 41489 } 41490 41491 { 41492 ICLASS: VPMAXSW 41493 CPL: 3 41494 CATEGORY: AVX512 41495 EXTENSION: AVX512EVEX 41496 ISA_SET: AVX512BW_128 41497 EXCEPTIONS: AVX512-E4 41498 REAL_OPCODE: Y 41499 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41500 PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 41501 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 41502 IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 41503 } 41504 41505 41506 # EMITTING VPMAXSW (VPMAXSW-256-1) 41507 { 41508 ICLASS: VPMAXSW 41509 CPL: 3 41510 CATEGORY: AVX512 41511 EXTENSION: AVX512EVEX 41512 ISA_SET: AVX512BW_256 41513 EXCEPTIONS: AVX512-E4 41514 REAL_OPCODE: Y 41515 ATTRIBUTES: MASKOP_EVEX 41516 PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 41517 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 41518 IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 41519 } 41520 41521 { 41522 ICLASS: VPMAXSW 41523 CPL: 3 41524 CATEGORY: AVX512 41525 EXTENSION: AVX512EVEX 41526 ISA_SET: AVX512BW_256 41527 EXCEPTIONS: AVX512-E4 41528 REAL_OPCODE: Y 41529 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41530 PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 41531 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 41532 IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 41533 } 41534 41535 41536 # EMITTING VPMAXSW (VPMAXSW-512-1) 41537 { 41538 ICLASS: VPMAXSW 41539 CPL: 3 41540 CATEGORY: AVX512 41541 EXTENSION: AVX512EVEX 41542 ISA_SET: AVX512BW_512 41543 EXCEPTIONS: AVX512-E4 41544 REAL_OPCODE: Y 41545 ATTRIBUTES: MASKOP_EVEX 41546 PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 41547 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 41548 IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 41549 } 41550 41551 { 41552 ICLASS: VPMAXSW 41553 CPL: 3 41554 CATEGORY: AVX512 41555 EXTENSION: AVX512EVEX 41556 ISA_SET: AVX512BW_512 41557 EXCEPTIONS: AVX512-E4 41558 REAL_OPCODE: Y 41559 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41560 PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 41561 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 41562 IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 41563 } 41564 41565 41566 # EMITTING VPMAXUB (VPMAXUB-128-1) 41567 { 41568 ICLASS: VPMAXUB 41569 CPL: 3 41570 CATEGORY: AVX512 41571 EXTENSION: AVX512EVEX 41572 ISA_SET: AVX512BW_128 41573 EXCEPTIONS: AVX512-E4 41574 REAL_OPCODE: Y 41575 ATTRIBUTES: MASKOP_EVEX 41576 PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 41577 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 41578 IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 41579 } 41580 41581 { 41582 ICLASS: VPMAXUB 41583 CPL: 3 41584 CATEGORY: AVX512 41585 EXTENSION: AVX512EVEX 41586 ISA_SET: AVX512BW_128 41587 EXCEPTIONS: AVX512-E4 41588 REAL_OPCODE: Y 41589 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41590 PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 41591 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 41592 IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 41593 } 41594 41595 41596 # EMITTING VPMAXUB (VPMAXUB-256-1) 41597 { 41598 ICLASS: VPMAXUB 41599 CPL: 3 41600 CATEGORY: AVX512 41601 EXTENSION: AVX512EVEX 41602 ISA_SET: AVX512BW_256 41603 EXCEPTIONS: AVX512-E4 41604 REAL_OPCODE: Y 41605 ATTRIBUTES: MASKOP_EVEX 41606 PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 41607 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 41608 IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 41609 } 41610 41611 { 41612 ICLASS: VPMAXUB 41613 CPL: 3 41614 CATEGORY: AVX512 41615 EXTENSION: AVX512EVEX 41616 ISA_SET: AVX512BW_256 41617 EXCEPTIONS: AVX512-E4 41618 REAL_OPCODE: Y 41619 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41620 PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 41621 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 41622 IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 41623 } 41624 41625 41626 # EMITTING VPMAXUB (VPMAXUB-512-1) 41627 { 41628 ICLASS: VPMAXUB 41629 CPL: 3 41630 CATEGORY: AVX512 41631 EXTENSION: AVX512EVEX 41632 ISA_SET: AVX512BW_512 41633 EXCEPTIONS: AVX512-E4 41634 REAL_OPCODE: Y 41635 ATTRIBUTES: MASKOP_EVEX 41636 PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 41637 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 41638 IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 41639 } 41640 41641 { 41642 ICLASS: VPMAXUB 41643 CPL: 3 41644 CATEGORY: AVX512 41645 EXTENSION: AVX512EVEX 41646 ISA_SET: AVX512BW_512 41647 EXCEPTIONS: AVX512-E4 41648 REAL_OPCODE: Y 41649 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41650 PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 41651 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 41652 IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 41653 } 41654 41655 41656 # EMITTING VPMAXUD (VPMAXUD-128-1) 41657 { 41658 ICLASS: VPMAXUD 41659 CPL: 3 41660 CATEGORY: AVX512 41661 EXTENSION: AVX512EVEX 41662 ISA_SET: AVX512F_128 41663 EXCEPTIONS: AVX512-E4 41664 REAL_OPCODE: Y 41665 ATTRIBUTES: MASKOP_EVEX 41666 PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 41667 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 41668 IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 41669 } 41670 41671 { 41672 ICLASS: VPMAXUD 41673 CPL: 3 41674 CATEGORY: AVX512 41675 EXTENSION: AVX512EVEX 41676 ISA_SET: AVX512F_128 41677 EXCEPTIONS: AVX512-E4 41678 REAL_OPCODE: Y 41679 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41680 PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 41681 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 41682 IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 41683 } 41684 41685 41686 # EMITTING VPMAXUD (VPMAXUD-256-1) 41687 { 41688 ICLASS: VPMAXUD 41689 CPL: 3 41690 CATEGORY: AVX512 41691 EXTENSION: AVX512EVEX 41692 ISA_SET: AVX512F_256 41693 EXCEPTIONS: AVX512-E4 41694 REAL_OPCODE: Y 41695 ATTRIBUTES: MASKOP_EVEX 41696 PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 41697 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 41698 IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 41699 } 41700 41701 { 41702 ICLASS: VPMAXUD 41703 CPL: 3 41704 CATEGORY: AVX512 41705 EXTENSION: AVX512EVEX 41706 ISA_SET: AVX512F_256 41707 EXCEPTIONS: AVX512-E4 41708 REAL_OPCODE: Y 41709 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41710 PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 41711 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 41712 IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 41713 } 41714 41715 41716 # EMITTING VPMAXUQ (VPMAXUQ-128-1) 41717 { 41718 ICLASS: VPMAXUQ 41719 CPL: 3 41720 CATEGORY: AVX512 41721 EXTENSION: AVX512EVEX 41722 ISA_SET: AVX512F_128 41723 EXCEPTIONS: AVX512-E4 41724 REAL_OPCODE: Y 41725 ATTRIBUTES: MASKOP_EVEX 41726 PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 41727 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 41728 IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 41729 } 41730 41731 { 41732 ICLASS: VPMAXUQ 41733 CPL: 3 41734 CATEGORY: AVX512 41735 EXTENSION: AVX512EVEX 41736 ISA_SET: AVX512F_128 41737 EXCEPTIONS: AVX512-E4 41738 REAL_OPCODE: Y 41739 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41740 PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 41741 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 41742 IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 41743 } 41744 41745 41746 # EMITTING VPMAXUQ (VPMAXUQ-256-1) 41747 { 41748 ICLASS: VPMAXUQ 41749 CPL: 3 41750 CATEGORY: AVX512 41751 EXTENSION: AVX512EVEX 41752 ISA_SET: AVX512F_256 41753 EXCEPTIONS: AVX512-E4 41754 REAL_OPCODE: Y 41755 ATTRIBUTES: MASKOP_EVEX 41756 PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 41757 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 41758 IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 41759 } 41760 41761 { 41762 ICLASS: VPMAXUQ 41763 CPL: 3 41764 CATEGORY: AVX512 41765 EXTENSION: AVX512EVEX 41766 ISA_SET: AVX512F_256 41767 EXCEPTIONS: AVX512-E4 41768 REAL_OPCODE: Y 41769 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41770 PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 41771 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 41772 IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 41773 } 41774 41775 41776 # EMITTING VPMAXUW (VPMAXUW-128-1) 41777 { 41778 ICLASS: VPMAXUW 41779 CPL: 3 41780 CATEGORY: AVX512 41781 EXTENSION: AVX512EVEX 41782 ISA_SET: AVX512BW_128 41783 EXCEPTIONS: AVX512-E4 41784 REAL_OPCODE: Y 41785 ATTRIBUTES: MASKOP_EVEX 41786 PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 41787 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 41788 IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 41789 } 41790 41791 { 41792 ICLASS: VPMAXUW 41793 CPL: 3 41794 CATEGORY: AVX512 41795 EXTENSION: AVX512EVEX 41796 ISA_SET: AVX512BW_128 41797 EXCEPTIONS: AVX512-E4 41798 REAL_OPCODE: Y 41799 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41800 PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 41801 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 41802 IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 41803 } 41804 41805 41806 # EMITTING VPMAXUW (VPMAXUW-256-1) 41807 { 41808 ICLASS: VPMAXUW 41809 CPL: 3 41810 CATEGORY: AVX512 41811 EXTENSION: AVX512EVEX 41812 ISA_SET: AVX512BW_256 41813 EXCEPTIONS: AVX512-E4 41814 REAL_OPCODE: Y 41815 ATTRIBUTES: MASKOP_EVEX 41816 PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 41817 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 41818 IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 41819 } 41820 41821 { 41822 ICLASS: VPMAXUW 41823 CPL: 3 41824 CATEGORY: AVX512 41825 EXTENSION: AVX512EVEX 41826 ISA_SET: AVX512BW_256 41827 EXCEPTIONS: AVX512-E4 41828 REAL_OPCODE: Y 41829 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41830 PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 41831 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 41832 IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 41833 } 41834 41835 41836 # EMITTING VPMAXUW (VPMAXUW-512-1) 41837 { 41838 ICLASS: VPMAXUW 41839 CPL: 3 41840 CATEGORY: AVX512 41841 EXTENSION: AVX512EVEX 41842 ISA_SET: AVX512BW_512 41843 EXCEPTIONS: AVX512-E4 41844 REAL_OPCODE: Y 41845 ATTRIBUTES: MASKOP_EVEX 41846 PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 41847 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 41848 IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 41849 } 41850 41851 { 41852 ICLASS: VPMAXUW 41853 CPL: 3 41854 CATEGORY: AVX512 41855 EXTENSION: AVX512EVEX 41856 ISA_SET: AVX512BW_512 41857 EXCEPTIONS: AVX512-E4 41858 REAL_OPCODE: Y 41859 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41860 PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 41861 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 41862 IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 41863 } 41864 41865 41866 # EMITTING VPMINSB (VPMINSB-128-1) 41867 { 41868 ICLASS: VPMINSB 41869 CPL: 3 41870 CATEGORY: AVX512 41871 EXTENSION: AVX512EVEX 41872 ISA_SET: AVX512BW_128 41873 EXCEPTIONS: AVX512-E4 41874 REAL_OPCODE: Y 41875 ATTRIBUTES: MASKOP_EVEX 41876 PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 41877 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 41878 IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 41879 } 41880 41881 { 41882 ICLASS: VPMINSB 41883 CPL: 3 41884 CATEGORY: AVX512 41885 EXTENSION: AVX512EVEX 41886 ISA_SET: AVX512BW_128 41887 EXCEPTIONS: AVX512-E4 41888 REAL_OPCODE: Y 41889 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41890 PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 41891 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 41892 IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 41893 } 41894 41895 41896 # EMITTING VPMINSB (VPMINSB-256-1) 41897 { 41898 ICLASS: VPMINSB 41899 CPL: 3 41900 CATEGORY: AVX512 41901 EXTENSION: AVX512EVEX 41902 ISA_SET: AVX512BW_256 41903 EXCEPTIONS: AVX512-E4 41904 REAL_OPCODE: Y 41905 ATTRIBUTES: MASKOP_EVEX 41906 PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 41907 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 41908 IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 41909 } 41910 41911 { 41912 ICLASS: VPMINSB 41913 CPL: 3 41914 CATEGORY: AVX512 41915 EXTENSION: AVX512EVEX 41916 ISA_SET: AVX512BW_256 41917 EXCEPTIONS: AVX512-E4 41918 REAL_OPCODE: Y 41919 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41920 PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 41921 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 41922 IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 41923 } 41924 41925 41926 # EMITTING VPMINSB (VPMINSB-512-1) 41927 { 41928 ICLASS: VPMINSB 41929 CPL: 3 41930 CATEGORY: AVX512 41931 EXTENSION: AVX512EVEX 41932 ISA_SET: AVX512BW_512 41933 EXCEPTIONS: AVX512-E4 41934 REAL_OPCODE: Y 41935 ATTRIBUTES: MASKOP_EVEX 41936 PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 41937 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 41938 IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 41939 } 41940 41941 { 41942 ICLASS: VPMINSB 41943 CPL: 3 41944 CATEGORY: AVX512 41945 EXTENSION: AVX512EVEX 41946 ISA_SET: AVX512BW_512 41947 EXCEPTIONS: AVX512-E4 41948 REAL_OPCODE: Y 41949 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 41950 PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 41951 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 41952 IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 41953 } 41954 41955 41956 # EMITTING VPMINSD (VPMINSD-128-1) 41957 { 41958 ICLASS: VPMINSD 41959 CPL: 3 41960 CATEGORY: AVX512 41961 EXTENSION: AVX512EVEX 41962 ISA_SET: AVX512F_128 41963 EXCEPTIONS: AVX512-E4 41964 REAL_OPCODE: Y 41965 ATTRIBUTES: MASKOP_EVEX 41966 PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 41967 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 41968 IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 41969 } 41970 41971 { 41972 ICLASS: VPMINSD 41973 CPL: 3 41974 CATEGORY: AVX512 41975 EXTENSION: AVX512EVEX 41976 ISA_SET: AVX512F_128 41977 EXCEPTIONS: AVX512-E4 41978 REAL_OPCODE: Y 41979 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 41980 PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 41981 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 41982 IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 41983 } 41984 41985 41986 # EMITTING VPMINSD (VPMINSD-256-1) 41987 { 41988 ICLASS: VPMINSD 41989 CPL: 3 41990 CATEGORY: AVX512 41991 EXTENSION: AVX512EVEX 41992 ISA_SET: AVX512F_256 41993 EXCEPTIONS: AVX512-E4 41994 REAL_OPCODE: Y 41995 ATTRIBUTES: MASKOP_EVEX 41996 PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 41997 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 41998 IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 41999 } 42000 42001 { 42002 ICLASS: VPMINSD 42003 CPL: 3 42004 CATEGORY: AVX512 42005 EXTENSION: AVX512EVEX 42006 ISA_SET: AVX512F_256 42007 EXCEPTIONS: AVX512-E4 42008 REAL_OPCODE: Y 42009 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42010 PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 42011 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR 42012 IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 42013 } 42014 42015 42016 # EMITTING VPMINSQ (VPMINSQ-128-1) 42017 { 42018 ICLASS: VPMINSQ 42019 CPL: 3 42020 CATEGORY: AVX512 42021 EXTENSION: AVX512EVEX 42022 ISA_SET: AVX512F_128 42023 EXCEPTIONS: AVX512-E4 42024 REAL_OPCODE: Y 42025 ATTRIBUTES: MASKOP_EVEX 42026 PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 42027 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 42028 IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 42029 } 42030 42031 { 42032 ICLASS: VPMINSQ 42033 CPL: 3 42034 CATEGORY: AVX512 42035 EXTENSION: AVX512EVEX 42036 ISA_SET: AVX512F_128 42037 EXCEPTIONS: AVX512-E4 42038 REAL_OPCODE: Y 42039 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42040 PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 42041 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 42042 IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 42043 } 42044 42045 42046 # EMITTING VPMINSQ (VPMINSQ-256-1) 42047 { 42048 ICLASS: VPMINSQ 42049 CPL: 3 42050 CATEGORY: AVX512 42051 EXTENSION: AVX512EVEX 42052 ISA_SET: AVX512F_256 42053 EXCEPTIONS: AVX512-E4 42054 REAL_OPCODE: Y 42055 ATTRIBUTES: MASKOP_EVEX 42056 PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 42057 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 42058 IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 42059 } 42060 42061 { 42062 ICLASS: VPMINSQ 42063 CPL: 3 42064 CATEGORY: AVX512 42065 EXTENSION: AVX512EVEX 42066 ISA_SET: AVX512F_256 42067 EXCEPTIONS: AVX512-E4 42068 REAL_OPCODE: Y 42069 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42070 PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 42071 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 42072 IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 42073 } 42074 42075 42076 # EMITTING VPMINSW (VPMINSW-128-1) 42077 { 42078 ICLASS: VPMINSW 42079 CPL: 3 42080 CATEGORY: AVX512 42081 EXTENSION: AVX512EVEX 42082 ISA_SET: AVX512BW_128 42083 EXCEPTIONS: AVX512-E4 42084 REAL_OPCODE: Y 42085 ATTRIBUTES: MASKOP_EVEX 42086 PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 42087 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 42088 IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 42089 } 42090 42091 { 42092 ICLASS: VPMINSW 42093 CPL: 3 42094 CATEGORY: AVX512 42095 EXTENSION: AVX512EVEX 42096 ISA_SET: AVX512BW_128 42097 EXCEPTIONS: AVX512-E4 42098 REAL_OPCODE: Y 42099 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 42100 PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 42101 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 42102 IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 42103 } 42104 42105 42106 # EMITTING VPMINSW (VPMINSW-256-1) 42107 { 42108 ICLASS: VPMINSW 42109 CPL: 3 42110 CATEGORY: AVX512 42111 EXTENSION: AVX512EVEX 42112 ISA_SET: AVX512BW_256 42113 EXCEPTIONS: AVX512-E4 42114 REAL_OPCODE: Y 42115 ATTRIBUTES: MASKOP_EVEX 42116 PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 42117 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 42118 IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 42119 } 42120 42121 { 42122 ICLASS: VPMINSW 42123 CPL: 3 42124 CATEGORY: AVX512 42125 EXTENSION: AVX512EVEX 42126 ISA_SET: AVX512BW_256 42127 EXCEPTIONS: AVX512-E4 42128 REAL_OPCODE: Y 42129 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 42130 PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 42131 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 42132 IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 42133 } 42134 42135 42136 # EMITTING VPMINSW (VPMINSW-512-1) 42137 { 42138 ICLASS: VPMINSW 42139 CPL: 3 42140 CATEGORY: AVX512 42141 EXTENSION: AVX512EVEX 42142 ISA_SET: AVX512BW_512 42143 EXCEPTIONS: AVX512-E4 42144 REAL_OPCODE: Y 42145 ATTRIBUTES: MASKOP_EVEX 42146 PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 42147 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 42148 IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 42149 } 42150 42151 { 42152 ICLASS: VPMINSW 42153 CPL: 3 42154 CATEGORY: AVX512 42155 EXTENSION: AVX512EVEX 42156 ISA_SET: AVX512BW_512 42157 EXCEPTIONS: AVX512-E4 42158 REAL_OPCODE: Y 42159 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 42160 PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 42161 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 42162 IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 42163 } 42164 42165 42166 # EMITTING VPMINUB (VPMINUB-128-1) 42167 { 42168 ICLASS: VPMINUB 42169 CPL: 3 42170 CATEGORY: AVX512 42171 EXTENSION: AVX512EVEX 42172 ISA_SET: AVX512BW_128 42173 EXCEPTIONS: AVX512-E4 42174 REAL_OPCODE: Y 42175 ATTRIBUTES: MASKOP_EVEX 42176 PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 42177 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 42178 IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 42179 } 42180 42181 { 42182 ICLASS: VPMINUB 42183 CPL: 3 42184 CATEGORY: AVX512 42185 EXTENSION: AVX512EVEX 42186 ISA_SET: AVX512BW_128 42187 EXCEPTIONS: AVX512-E4 42188 REAL_OPCODE: Y 42189 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 42190 PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 42191 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 42192 IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 42193 } 42194 42195 42196 # EMITTING VPMINUB (VPMINUB-256-1) 42197 { 42198 ICLASS: VPMINUB 42199 CPL: 3 42200 CATEGORY: AVX512 42201 EXTENSION: AVX512EVEX 42202 ISA_SET: AVX512BW_256 42203 EXCEPTIONS: AVX512-E4 42204 REAL_OPCODE: Y 42205 ATTRIBUTES: MASKOP_EVEX 42206 PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 42207 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 42208 IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 42209 } 42210 42211 { 42212 ICLASS: VPMINUB 42213 CPL: 3 42214 CATEGORY: AVX512 42215 EXTENSION: AVX512EVEX 42216 ISA_SET: AVX512BW_256 42217 EXCEPTIONS: AVX512-E4 42218 REAL_OPCODE: Y 42219 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 42220 PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 42221 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 42222 IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 42223 } 42224 42225 42226 # EMITTING VPMINUB (VPMINUB-512-1) 42227 { 42228 ICLASS: VPMINUB 42229 CPL: 3 42230 CATEGORY: AVX512 42231 EXTENSION: AVX512EVEX 42232 ISA_SET: AVX512BW_512 42233 EXCEPTIONS: AVX512-E4 42234 REAL_OPCODE: Y 42235 ATTRIBUTES: MASKOP_EVEX 42236 PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 42237 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 42238 IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 42239 } 42240 42241 { 42242 ICLASS: VPMINUB 42243 CPL: 3 42244 CATEGORY: AVX512 42245 EXTENSION: AVX512EVEX 42246 ISA_SET: AVX512BW_512 42247 EXCEPTIONS: AVX512-E4 42248 REAL_OPCODE: Y 42249 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 42250 PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 42251 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 42252 IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 42253 } 42254 42255 42256 # EMITTING VPMINUD (VPMINUD-128-1) 42257 { 42258 ICLASS: VPMINUD 42259 CPL: 3 42260 CATEGORY: AVX512 42261 EXTENSION: AVX512EVEX 42262 ISA_SET: AVX512F_128 42263 EXCEPTIONS: AVX512-E4 42264 REAL_OPCODE: Y 42265 ATTRIBUTES: MASKOP_EVEX 42266 PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 42267 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 42268 IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 42269 } 42270 42271 { 42272 ICLASS: VPMINUD 42273 CPL: 3 42274 CATEGORY: AVX512 42275 EXTENSION: AVX512EVEX 42276 ISA_SET: AVX512F_128 42277 EXCEPTIONS: AVX512-E4 42278 REAL_OPCODE: Y 42279 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42280 PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 42281 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 42282 IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 42283 } 42284 42285 42286 # EMITTING VPMINUD (VPMINUD-256-1) 42287 { 42288 ICLASS: VPMINUD 42289 CPL: 3 42290 CATEGORY: AVX512 42291 EXTENSION: AVX512EVEX 42292 ISA_SET: AVX512F_256 42293 EXCEPTIONS: AVX512-E4 42294 REAL_OPCODE: Y 42295 ATTRIBUTES: MASKOP_EVEX 42296 PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 42297 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 42298 IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 42299 } 42300 42301 { 42302 ICLASS: VPMINUD 42303 CPL: 3 42304 CATEGORY: AVX512 42305 EXTENSION: AVX512EVEX 42306 ISA_SET: AVX512F_256 42307 EXCEPTIONS: AVX512-E4 42308 REAL_OPCODE: Y 42309 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42310 PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 42311 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 42312 IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 42313 } 42314 42315 42316 # EMITTING VPMINUQ (VPMINUQ-128-1) 42317 { 42318 ICLASS: VPMINUQ 42319 CPL: 3 42320 CATEGORY: AVX512 42321 EXTENSION: AVX512EVEX 42322 ISA_SET: AVX512F_128 42323 EXCEPTIONS: AVX512-E4 42324 REAL_OPCODE: Y 42325 ATTRIBUTES: MASKOP_EVEX 42326 PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 42327 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 42328 IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 42329 } 42330 42331 { 42332 ICLASS: VPMINUQ 42333 CPL: 3 42334 CATEGORY: AVX512 42335 EXTENSION: AVX512EVEX 42336 ISA_SET: AVX512F_128 42337 EXCEPTIONS: AVX512-E4 42338 REAL_OPCODE: Y 42339 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42340 PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 42341 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 42342 IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 42343 } 42344 42345 42346 # EMITTING VPMINUQ (VPMINUQ-256-1) 42347 { 42348 ICLASS: VPMINUQ 42349 CPL: 3 42350 CATEGORY: AVX512 42351 EXTENSION: AVX512EVEX 42352 ISA_SET: AVX512F_256 42353 EXCEPTIONS: AVX512-E4 42354 REAL_OPCODE: Y 42355 ATTRIBUTES: MASKOP_EVEX 42356 PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 42357 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 42358 IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 42359 } 42360 42361 { 42362 ICLASS: VPMINUQ 42363 CPL: 3 42364 CATEGORY: AVX512 42365 EXTENSION: AVX512EVEX 42366 ISA_SET: AVX512F_256 42367 EXCEPTIONS: AVX512-E4 42368 REAL_OPCODE: Y 42369 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 42370 PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 42371 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 42372 IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 42373 } 42374 42375 42376 # EMITTING VPMINUW (VPMINUW-128-1) 42377 { 42378 ICLASS: VPMINUW 42379 CPL: 3 42380 CATEGORY: AVX512 42381 EXTENSION: AVX512EVEX 42382 ISA_SET: AVX512BW_128 42383 EXCEPTIONS: AVX512-E4 42384 REAL_OPCODE: Y 42385 ATTRIBUTES: MASKOP_EVEX 42386 PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 42387 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 42388 IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 42389 } 42390 42391 { 42392 ICLASS: VPMINUW 42393 CPL: 3 42394 CATEGORY: AVX512 42395 EXTENSION: AVX512EVEX 42396 ISA_SET: AVX512BW_128 42397 EXCEPTIONS: AVX512-E4 42398 REAL_OPCODE: Y 42399 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 42400 PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 42401 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 42402 IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 42403 } 42404 42405 42406 # EMITTING VPMINUW (VPMINUW-256-1) 42407 { 42408 ICLASS: VPMINUW 42409 CPL: 3 42410 CATEGORY: AVX512 42411 EXTENSION: AVX512EVEX 42412 ISA_SET: AVX512BW_256 42413 EXCEPTIONS: AVX512-E4 42414 REAL_OPCODE: Y 42415 ATTRIBUTES: MASKOP_EVEX 42416 PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 42417 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 42418 IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 42419 } 42420 42421 { 42422 ICLASS: VPMINUW 42423 CPL: 3 42424 CATEGORY: AVX512 42425 EXTENSION: AVX512EVEX 42426 ISA_SET: AVX512BW_256 42427 EXCEPTIONS: AVX512-E4 42428 REAL_OPCODE: Y 42429 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 42430 PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 42431 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 42432 IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 42433 } 42434 42435 42436 # EMITTING VPMINUW (VPMINUW-512-1) 42437 { 42438 ICLASS: VPMINUW 42439 CPL: 3 42440 CATEGORY: AVX512 42441 EXTENSION: AVX512EVEX 42442 ISA_SET: AVX512BW_512 42443 EXCEPTIONS: AVX512-E4 42444 REAL_OPCODE: Y 42445 ATTRIBUTES: MASKOP_EVEX 42446 PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 42447 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 42448 IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 42449 } 42450 42451 { 42452 ICLASS: VPMINUW 42453 CPL: 3 42454 CATEGORY: AVX512 42455 EXTENSION: AVX512EVEX 42456 ISA_SET: AVX512BW_512 42457 EXCEPTIONS: AVX512-E4 42458 REAL_OPCODE: Y 42459 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 42460 PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 42461 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 42462 IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 42463 } 42464 42465 42466 # EMITTING VPMOVB2M (VPMOVB2M-128-1) 42467 { 42468 ICLASS: VPMOVB2M 42469 CPL: 3 42470 CATEGORY: DATAXFER 42471 EXTENSION: AVX512EVEX 42472 ISA_SET: AVX512BW_128 42473 EXCEPTIONS: AVX512-E7NM 42474 REAL_OPCODE: Y 42475 PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 42476 OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u8 42477 IFORM: VPMOVB2M_MASKmskw_XMMu8_AVX512 42478 } 42479 42480 42481 # EMITTING VPMOVB2M (VPMOVB2M-256-1) 42482 { 42483 ICLASS: VPMOVB2M 42484 CPL: 3 42485 CATEGORY: DATAXFER 42486 EXTENSION: AVX512EVEX 42487 ISA_SET: AVX512BW_256 42488 EXCEPTIONS: AVX512-E7NM 42489 REAL_OPCODE: Y 42490 PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 42491 OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u8 42492 IFORM: VPMOVB2M_MASKmskw_YMMu8_AVX512 42493 } 42494 42495 42496 # EMITTING VPMOVB2M (VPMOVB2M-512-1) 42497 { 42498 ICLASS: VPMOVB2M 42499 CPL: 3 42500 CATEGORY: DATAXFER 42501 EXTENSION: AVX512EVEX 42502 ISA_SET: AVX512BW_512 42503 EXCEPTIONS: AVX512-E7NM 42504 REAL_OPCODE: Y 42505 PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 42506 OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu8 42507 IFORM: VPMOVB2M_MASKmskw_ZMMu8_AVX512 42508 } 42509 42510 42511 # EMITTING VPMOVD2M (VPMOVD2M-128-1) 42512 { 42513 ICLASS: VPMOVD2M 42514 CPL: 3 42515 CATEGORY: DATAXFER 42516 EXTENSION: AVX512EVEX 42517 ISA_SET: AVX512DQ_128 42518 EXCEPTIONS: AVX512-E7NM 42519 REAL_OPCODE: Y 42520 PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 42521 OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u32 42522 IFORM: VPMOVD2M_MASKmskw_XMMu32_AVX512 42523 } 42524 42525 42526 # EMITTING VPMOVD2M (VPMOVD2M-256-1) 42527 { 42528 ICLASS: VPMOVD2M 42529 CPL: 3 42530 CATEGORY: DATAXFER 42531 EXTENSION: AVX512EVEX 42532 ISA_SET: AVX512DQ_256 42533 EXCEPTIONS: AVX512-E7NM 42534 REAL_OPCODE: Y 42535 PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 42536 OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u32 42537 IFORM: VPMOVD2M_MASKmskw_YMMu32_AVX512 42538 } 42539 42540 42541 # EMITTING VPMOVD2M (VPMOVD2M-512-1) 42542 { 42543 ICLASS: VPMOVD2M 42544 CPL: 3 42545 CATEGORY: DATAXFER 42546 EXTENSION: AVX512EVEX 42547 ISA_SET: AVX512DQ_512 42548 EXCEPTIONS: AVX512-E7NM 42549 REAL_OPCODE: Y 42550 PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 42551 OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu32 42552 IFORM: VPMOVD2M_MASKmskw_ZMMu32_AVX512 42553 } 42554 42555 42556 # EMITTING VPMOVDB (VPMOVDB-128-1) 42557 { 42558 ICLASS: VPMOVDB 42559 CPL: 3 42560 CATEGORY: DATAXFER 42561 EXTENSION: AVX512EVEX 42562 ISA_SET: AVX512F_128 42563 EXCEPTIONS: AVX512-E6NF 42564 REAL_OPCODE: Y 42565 ATTRIBUTES: MASKOP_EVEX 42566 PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 42567 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 42568 IFORM: VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 42569 } 42570 42571 42572 # EMITTING VPMOVDB (VPMOVDB-128-2) 42573 { 42574 ICLASS: VPMOVDB 42575 CPL: 3 42576 CATEGORY: DATAXFER 42577 EXTENSION: AVX512EVEX 42578 ISA_SET: AVX512F_128 42579 EXCEPTIONS: AVX512-E6 42580 REAL_OPCODE: Y 42581 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 42582 PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 42583 OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 42584 IFORM: VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 42585 } 42586 42587 42588 # EMITTING VPMOVDB (VPMOVDB-256-1) 42589 { 42590 ICLASS: VPMOVDB 42591 CPL: 3 42592 CATEGORY: DATAXFER 42593 EXTENSION: AVX512EVEX 42594 ISA_SET: AVX512F_256 42595 EXCEPTIONS: AVX512-E6NF 42596 REAL_OPCODE: Y 42597 ATTRIBUTES: MASKOP_EVEX 42598 PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 42599 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 42600 IFORM: VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 42601 } 42602 42603 42604 # EMITTING VPMOVDB (VPMOVDB-256-2) 42605 { 42606 ICLASS: VPMOVDB 42607 CPL: 3 42608 CATEGORY: DATAXFER 42609 EXTENSION: AVX512EVEX 42610 ISA_SET: AVX512F_256 42611 EXCEPTIONS: AVX512-E6 42612 REAL_OPCODE: Y 42613 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 42614 PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 42615 OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 42616 IFORM: VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 42617 } 42618 42619 42620 # EMITTING VPMOVDW (VPMOVDW-128-1) 42621 { 42622 ICLASS: VPMOVDW 42623 CPL: 3 42624 CATEGORY: DATAXFER 42625 EXTENSION: AVX512EVEX 42626 ISA_SET: AVX512F_128 42627 EXCEPTIONS: AVX512-E6NF 42628 REAL_OPCODE: Y 42629 ATTRIBUTES: MASKOP_EVEX 42630 PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 42631 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 42632 IFORM: VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 42633 } 42634 42635 42636 # EMITTING VPMOVDW (VPMOVDW-128-2) 42637 { 42638 ICLASS: VPMOVDW 42639 CPL: 3 42640 CATEGORY: DATAXFER 42641 EXTENSION: AVX512EVEX 42642 ISA_SET: AVX512F_128 42643 EXCEPTIONS: AVX512-E6 42644 REAL_OPCODE: Y 42645 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 42646 PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 42647 OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 42648 IFORM: VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 42649 } 42650 42651 42652 # EMITTING VPMOVDW (VPMOVDW-256-1) 42653 { 42654 ICLASS: VPMOVDW 42655 CPL: 3 42656 CATEGORY: DATAXFER 42657 EXTENSION: AVX512EVEX 42658 ISA_SET: AVX512F_256 42659 EXCEPTIONS: AVX512-E6NF 42660 REAL_OPCODE: Y 42661 ATTRIBUTES: MASKOP_EVEX 42662 PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 42663 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 42664 IFORM: VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 42665 } 42666 42667 42668 # EMITTING VPMOVDW (VPMOVDW-256-2) 42669 { 42670 ICLASS: VPMOVDW 42671 CPL: 3 42672 CATEGORY: DATAXFER 42673 EXTENSION: AVX512EVEX 42674 ISA_SET: AVX512F_256 42675 EXCEPTIONS: AVX512-E6 42676 REAL_OPCODE: Y 42677 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 42678 PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 42679 OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 42680 IFORM: VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 42681 } 42682 42683 42684 # EMITTING VPMOVM2B (VPMOVM2B-128-1) 42685 { 42686 ICLASS: VPMOVM2B 42687 CPL: 3 42688 CATEGORY: DATAXFER 42689 EXTENSION: AVX512EVEX 42690 ISA_SET: AVX512BW_128 42691 EXCEPTIONS: AVX512-E7NM 42692 REAL_OPCODE: Y 42693 PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 42694 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK_B():r:mskw 42695 IFORM: VPMOVM2B_XMMu8_MASKmskw_AVX512 42696 } 42697 42698 42699 # EMITTING VPMOVM2B (VPMOVM2B-256-1) 42700 { 42701 ICLASS: VPMOVM2B 42702 CPL: 3 42703 CATEGORY: DATAXFER 42704 EXTENSION: AVX512EVEX 42705 ISA_SET: AVX512BW_256 42706 EXCEPTIONS: AVX512-E7NM 42707 REAL_OPCODE: Y 42708 PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 42709 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK_B():r:mskw 42710 IFORM: VPMOVM2B_YMMu8_MASKmskw_AVX512 42711 } 42712 42713 42714 # EMITTING VPMOVM2B (VPMOVM2B-512-1) 42715 { 42716 ICLASS: VPMOVM2B 42717 CPL: 3 42718 CATEGORY: DATAXFER 42719 EXTENSION: AVX512EVEX 42720 ISA_SET: AVX512BW_512 42721 EXCEPTIONS: AVX512-E7NM 42722 REAL_OPCODE: Y 42723 PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 42724 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK_B():r:mskw 42725 IFORM: VPMOVM2B_ZMMu8_MASKmskw_AVX512 42726 } 42727 42728 42729 # EMITTING VPMOVM2D (VPMOVM2D-128-1) 42730 { 42731 ICLASS: VPMOVM2D 42732 CPL: 3 42733 CATEGORY: DATAXFER 42734 EXTENSION: AVX512EVEX 42735 ISA_SET: AVX512DQ_128 42736 EXCEPTIONS: AVX512-E7NM 42737 REAL_OPCODE: Y 42738 PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 42739 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw 42740 IFORM: VPMOVM2D_XMMu32_MASKmskw_AVX512 42741 } 42742 42743 42744 # EMITTING VPMOVM2D (VPMOVM2D-256-1) 42745 { 42746 ICLASS: VPMOVM2D 42747 CPL: 3 42748 CATEGORY: DATAXFER 42749 EXTENSION: AVX512EVEX 42750 ISA_SET: AVX512DQ_256 42751 EXCEPTIONS: AVX512-E7NM 42752 REAL_OPCODE: Y 42753 PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 42754 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw 42755 IFORM: VPMOVM2D_YMMu32_MASKmskw_AVX512 42756 } 42757 42758 42759 # EMITTING VPMOVM2D (VPMOVM2D-512-1) 42760 { 42761 ICLASS: VPMOVM2D 42762 CPL: 3 42763 CATEGORY: DATAXFER 42764 EXTENSION: AVX512EVEX 42765 ISA_SET: AVX512DQ_512 42766 EXCEPTIONS: AVX512-E7NM 42767 REAL_OPCODE: Y 42768 PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 42769 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw 42770 IFORM: VPMOVM2D_ZMMu32_MASKmskw_AVX512 42771 } 42772 42773 42774 # EMITTING VPMOVM2Q (VPMOVM2Q-128-1) 42775 { 42776 ICLASS: VPMOVM2Q 42777 CPL: 3 42778 CATEGORY: DATAXFER 42779 EXTENSION: AVX512EVEX 42780 ISA_SET: AVX512DQ_128 42781 EXCEPTIONS: AVX512-E7NM 42782 REAL_OPCODE: Y 42783 PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 42784 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw 42785 IFORM: VPMOVM2Q_XMMu64_MASKmskw_AVX512 42786 } 42787 42788 42789 # EMITTING VPMOVM2Q (VPMOVM2Q-256-1) 42790 { 42791 ICLASS: VPMOVM2Q 42792 CPL: 3 42793 CATEGORY: DATAXFER 42794 EXTENSION: AVX512EVEX 42795 ISA_SET: AVX512DQ_256 42796 EXCEPTIONS: AVX512-E7NM 42797 REAL_OPCODE: Y 42798 PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 42799 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw 42800 IFORM: VPMOVM2Q_YMMu64_MASKmskw_AVX512 42801 } 42802 42803 42804 # EMITTING VPMOVM2Q (VPMOVM2Q-512-1) 42805 { 42806 ICLASS: VPMOVM2Q 42807 CPL: 3 42808 CATEGORY: DATAXFER 42809 EXTENSION: AVX512EVEX 42810 ISA_SET: AVX512DQ_512 42811 EXCEPTIONS: AVX512-E7NM 42812 REAL_OPCODE: Y 42813 PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 42814 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw 42815 IFORM: VPMOVM2Q_ZMMu64_MASKmskw_AVX512 42816 } 42817 42818 42819 # EMITTING VPMOVM2W (VPMOVM2W-128-1) 42820 { 42821 ICLASS: VPMOVM2W 42822 CPL: 3 42823 CATEGORY: DATAXFER 42824 EXTENSION: AVX512EVEX 42825 ISA_SET: AVX512BW_128 42826 EXCEPTIONS: AVX512-E7NM 42827 REAL_OPCODE: Y 42828 PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 42829 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK_B():r:mskw 42830 IFORM: VPMOVM2W_XMMu16_MASKmskw_AVX512 42831 } 42832 42833 42834 # EMITTING VPMOVM2W (VPMOVM2W-256-1) 42835 { 42836 ICLASS: VPMOVM2W 42837 CPL: 3 42838 CATEGORY: DATAXFER 42839 EXTENSION: AVX512EVEX 42840 ISA_SET: AVX512BW_256 42841 EXCEPTIONS: AVX512-E7NM 42842 REAL_OPCODE: Y 42843 PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 42844 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK_B():r:mskw 42845 IFORM: VPMOVM2W_YMMu16_MASKmskw_AVX512 42846 } 42847 42848 42849 # EMITTING VPMOVM2W (VPMOVM2W-512-1) 42850 { 42851 ICLASS: VPMOVM2W 42852 CPL: 3 42853 CATEGORY: DATAXFER 42854 EXTENSION: AVX512EVEX 42855 ISA_SET: AVX512BW_512 42856 EXCEPTIONS: AVX512-E7NM 42857 REAL_OPCODE: Y 42858 PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 42859 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK_B():r:mskw 42860 IFORM: VPMOVM2W_ZMMu16_MASKmskw_AVX512 42861 } 42862 42863 42864 # EMITTING VPMOVQ2M (VPMOVQ2M-128-1) 42865 { 42866 ICLASS: VPMOVQ2M 42867 CPL: 3 42868 CATEGORY: DATAXFER 42869 EXTENSION: AVX512EVEX 42870 ISA_SET: AVX512DQ_128 42871 EXCEPTIONS: AVX512-E7NM 42872 REAL_OPCODE: Y 42873 PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 42874 OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u64 42875 IFORM: VPMOVQ2M_MASKmskw_XMMu64_AVX512 42876 } 42877 42878 42879 # EMITTING VPMOVQ2M (VPMOVQ2M-256-1) 42880 { 42881 ICLASS: VPMOVQ2M 42882 CPL: 3 42883 CATEGORY: DATAXFER 42884 EXTENSION: AVX512EVEX 42885 ISA_SET: AVX512DQ_256 42886 EXCEPTIONS: AVX512-E7NM 42887 REAL_OPCODE: Y 42888 PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 42889 OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u64 42890 IFORM: VPMOVQ2M_MASKmskw_YMMu64_AVX512 42891 } 42892 42893 42894 # EMITTING VPMOVQ2M (VPMOVQ2M-512-1) 42895 { 42896 ICLASS: VPMOVQ2M 42897 CPL: 3 42898 CATEGORY: DATAXFER 42899 EXTENSION: AVX512EVEX 42900 ISA_SET: AVX512DQ_512 42901 EXCEPTIONS: AVX512-E7NM 42902 REAL_OPCODE: Y 42903 PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 42904 OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu64 42905 IFORM: VPMOVQ2M_MASKmskw_ZMMu64_AVX512 42906 } 42907 42908 42909 # EMITTING VPMOVQB (VPMOVQB-128-1) 42910 { 42911 ICLASS: VPMOVQB 42912 CPL: 3 42913 CATEGORY: DATAXFER 42914 EXTENSION: AVX512EVEX 42915 ISA_SET: AVX512F_128 42916 EXCEPTIONS: AVX512-E6NF 42917 REAL_OPCODE: Y 42918 ATTRIBUTES: MASKOP_EVEX 42919 PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 42920 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 42921 IFORM: VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 42922 } 42923 42924 42925 # EMITTING VPMOVQB (VPMOVQB-128-2) 42926 { 42927 ICLASS: VPMOVQB 42928 CPL: 3 42929 CATEGORY: DATAXFER 42930 EXTENSION: AVX512EVEX 42931 ISA_SET: AVX512F_128 42932 EXCEPTIONS: AVX512-E6 42933 REAL_OPCODE: Y 42934 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 42935 PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 42936 OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 42937 IFORM: VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 42938 } 42939 42940 42941 # EMITTING VPMOVQB (VPMOVQB-256-1) 42942 { 42943 ICLASS: VPMOVQB 42944 CPL: 3 42945 CATEGORY: DATAXFER 42946 EXTENSION: AVX512EVEX 42947 ISA_SET: AVX512F_256 42948 EXCEPTIONS: AVX512-E6NF 42949 REAL_OPCODE: Y 42950 ATTRIBUTES: MASKOP_EVEX 42951 PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 42952 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 42953 IFORM: VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 42954 } 42955 42956 42957 # EMITTING VPMOVQB (VPMOVQB-256-2) 42958 { 42959 ICLASS: VPMOVQB 42960 CPL: 3 42961 CATEGORY: DATAXFER 42962 EXTENSION: AVX512EVEX 42963 ISA_SET: AVX512F_256 42964 EXCEPTIONS: AVX512-E6 42965 REAL_OPCODE: Y 42966 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 42967 PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 42968 OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 42969 IFORM: VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 42970 } 42971 42972 42973 # EMITTING VPMOVQD (VPMOVQD-128-1) 42974 { 42975 ICLASS: VPMOVQD 42976 CPL: 3 42977 CATEGORY: DATAXFER 42978 EXTENSION: AVX512EVEX 42979 ISA_SET: AVX512F_128 42980 EXCEPTIONS: AVX512-E6NF 42981 REAL_OPCODE: Y 42982 ATTRIBUTES: MASKOP_EVEX 42983 PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 42984 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 42985 IFORM: VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 42986 } 42987 42988 42989 # EMITTING VPMOVQD (VPMOVQD-128-2) 42990 { 42991 ICLASS: VPMOVQD 42992 CPL: 3 42993 CATEGORY: DATAXFER 42994 EXTENSION: AVX512EVEX 42995 ISA_SET: AVX512F_128 42996 EXCEPTIONS: AVX512-E6 42997 REAL_OPCODE: Y 42998 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 42999 PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 43000 OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 43001 IFORM: VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 43002 } 43003 43004 43005 # EMITTING VPMOVQD (VPMOVQD-256-1) 43006 { 43007 ICLASS: VPMOVQD 43008 CPL: 3 43009 CATEGORY: DATAXFER 43010 EXTENSION: AVX512EVEX 43011 ISA_SET: AVX512F_256 43012 EXCEPTIONS: AVX512-E6NF 43013 REAL_OPCODE: Y 43014 ATTRIBUTES: MASKOP_EVEX 43015 PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43016 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 43017 IFORM: VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 43018 } 43019 43020 43021 # EMITTING VPMOVQD (VPMOVQD-256-2) 43022 { 43023 ICLASS: VPMOVQD 43024 CPL: 3 43025 CATEGORY: DATAXFER 43026 EXTENSION: AVX512EVEX 43027 ISA_SET: AVX512F_256 43028 EXCEPTIONS: AVX512-E6 43029 REAL_OPCODE: Y 43030 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43031 PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 43032 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 43033 IFORM: VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 43034 } 43035 43036 43037 # EMITTING VPMOVQW (VPMOVQW-128-1) 43038 { 43039 ICLASS: VPMOVQW 43040 CPL: 3 43041 CATEGORY: DATAXFER 43042 EXTENSION: AVX512EVEX 43043 ISA_SET: AVX512F_128 43044 EXCEPTIONS: AVX512-E6NF 43045 REAL_OPCODE: Y 43046 ATTRIBUTES: MASKOP_EVEX 43047 PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43048 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 43049 IFORM: VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 43050 } 43051 43052 43053 # EMITTING VPMOVQW (VPMOVQW-128-2) 43054 { 43055 ICLASS: VPMOVQW 43056 CPL: 3 43057 CATEGORY: DATAXFER 43058 EXTENSION: AVX512EVEX 43059 ISA_SET: AVX512F_128 43060 EXCEPTIONS: AVX512-E6 43061 REAL_OPCODE: Y 43062 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 43063 PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 43064 OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 43065 IFORM: VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 43066 } 43067 43068 43069 # EMITTING VPMOVQW (VPMOVQW-256-1) 43070 { 43071 ICLASS: VPMOVQW 43072 CPL: 3 43073 CATEGORY: DATAXFER 43074 EXTENSION: AVX512EVEX 43075 ISA_SET: AVX512F_256 43076 EXCEPTIONS: AVX512-E6NF 43077 REAL_OPCODE: Y 43078 ATTRIBUTES: MASKOP_EVEX 43079 PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43080 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 43081 IFORM: VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 43082 } 43083 43084 43085 # EMITTING VPMOVQW (VPMOVQW-256-2) 43086 { 43087 ICLASS: VPMOVQW 43088 CPL: 3 43089 CATEGORY: DATAXFER 43090 EXTENSION: AVX512EVEX 43091 ISA_SET: AVX512F_256 43092 EXCEPTIONS: AVX512-E6 43093 REAL_OPCODE: Y 43094 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 43095 PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 43096 OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 43097 IFORM: VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 43098 } 43099 43100 43101 # EMITTING VPMOVSDB (VPMOVSDB-128-1) 43102 { 43103 ICLASS: VPMOVSDB 43104 CPL: 3 43105 CATEGORY: DATAXFER 43106 EXTENSION: AVX512EVEX 43107 ISA_SET: AVX512F_128 43108 EXCEPTIONS: AVX512-E6NF 43109 REAL_OPCODE: Y 43110 ATTRIBUTES: MASKOP_EVEX 43111 PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43112 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 43113 IFORM: VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 43114 } 43115 43116 43117 # EMITTING VPMOVSDB (VPMOVSDB-128-2) 43118 { 43119 ICLASS: VPMOVSDB 43120 CPL: 3 43121 CATEGORY: DATAXFER 43122 EXTENSION: AVX512EVEX 43123 ISA_SET: AVX512F_128 43124 EXCEPTIONS: AVX512-E6 43125 REAL_OPCODE: Y 43126 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 43127 PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 43128 OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 43129 IFORM: VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 43130 } 43131 43132 43133 # EMITTING VPMOVSDB (VPMOVSDB-256-1) 43134 { 43135 ICLASS: VPMOVSDB 43136 CPL: 3 43137 CATEGORY: DATAXFER 43138 EXTENSION: AVX512EVEX 43139 ISA_SET: AVX512F_256 43140 EXCEPTIONS: AVX512-E6NF 43141 REAL_OPCODE: Y 43142 ATTRIBUTES: MASKOP_EVEX 43143 PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43144 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 43145 IFORM: VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 43146 } 43147 43148 43149 # EMITTING VPMOVSDB (VPMOVSDB-256-2) 43150 { 43151 ICLASS: VPMOVSDB 43152 CPL: 3 43153 CATEGORY: DATAXFER 43154 EXTENSION: AVX512EVEX 43155 ISA_SET: AVX512F_256 43156 EXCEPTIONS: AVX512-E6 43157 REAL_OPCODE: Y 43158 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 43159 PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 43160 OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 43161 IFORM: VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 43162 } 43163 43164 43165 # EMITTING VPMOVSDW (VPMOVSDW-128-1) 43166 { 43167 ICLASS: VPMOVSDW 43168 CPL: 3 43169 CATEGORY: DATAXFER 43170 EXTENSION: AVX512EVEX 43171 ISA_SET: AVX512F_128 43172 EXCEPTIONS: AVX512-E6NF 43173 REAL_OPCODE: Y 43174 ATTRIBUTES: MASKOP_EVEX 43175 PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43176 OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 43177 IFORM: VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 43178 } 43179 43180 43181 # EMITTING VPMOVSDW (VPMOVSDW-128-2) 43182 { 43183 ICLASS: VPMOVSDW 43184 CPL: 3 43185 CATEGORY: DATAXFER 43186 EXTENSION: AVX512EVEX 43187 ISA_SET: AVX512F_128 43188 EXCEPTIONS: AVX512-E6 43189 REAL_OPCODE: Y 43190 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43191 PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 43192 OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 43193 IFORM: VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 43194 } 43195 43196 43197 # EMITTING VPMOVSDW (VPMOVSDW-256-1) 43198 { 43199 ICLASS: VPMOVSDW 43200 CPL: 3 43201 CATEGORY: DATAXFER 43202 EXTENSION: AVX512EVEX 43203 ISA_SET: AVX512F_256 43204 EXCEPTIONS: AVX512-E6NF 43205 REAL_OPCODE: Y 43206 ATTRIBUTES: MASKOP_EVEX 43207 PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43208 OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 43209 IFORM: VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 43210 } 43211 43212 43213 # EMITTING VPMOVSDW (VPMOVSDW-256-2) 43214 { 43215 ICLASS: VPMOVSDW 43216 CPL: 3 43217 CATEGORY: DATAXFER 43218 EXTENSION: AVX512EVEX 43219 ISA_SET: AVX512F_256 43220 EXCEPTIONS: AVX512-E6 43221 REAL_OPCODE: Y 43222 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43223 PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 43224 OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 43225 IFORM: VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 43226 } 43227 43228 43229 # EMITTING VPMOVSQB (VPMOVSQB-128-1) 43230 { 43231 ICLASS: VPMOVSQB 43232 CPL: 3 43233 CATEGORY: DATAXFER 43234 EXTENSION: AVX512EVEX 43235 ISA_SET: AVX512F_128 43236 EXCEPTIONS: AVX512-E6NF 43237 REAL_OPCODE: Y 43238 ATTRIBUTES: MASKOP_EVEX 43239 PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43240 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 43241 IFORM: VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 43242 } 43243 43244 43245 # EMITTING VPMOVSQB (VPMOVSQB-128-2) 43246 { 43247 ICLASS: VPMOVSQB 43248 CPL: 3 43249 CATEGORY: DATAXFER 43250 EXTENSION: AVX512EVEX 43251 ISA_SET: AVX512F_128 43252 EXCEPTIONS: AVX512-E6 43253 REAL_OPCODE: Y 43254 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 43255 PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 43256 OPERANDS: MEM0:w:wrd:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 43257 IFORM: VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 43258 } 43259 43260 43261 # EMITTING VPMOVSQB (VPMOVSQB-256-1) 43262 { 43263 ICLASS: VPMOVSQB 43264 CPL: 3 43265 CATEGORY: DATAXFER 43266 EXTENSION: AVX512EVEX 43267 ISA_SET: AVX512F_256 43268 EXCEPTIONS: AVX512-E6NF 43269 REAL_OPCODE: Y 43270 ATTRIBUTES: MASKOP_EVEX 43271 PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43272 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 43273 IFORM: VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 43274 } 43275 43276 43277 # EMITTING VPMOVSQB (VPMOVSQB-256-2) 43278 { 43279 ICLASS: VPMOVSQB 43280 CPL: 3 43281 CATEGORY: DATAXFER 43282 EXTENSION: AVX512EVEX 43283 ISA_SET: AVX512F_256 43284 EXCEPTIONS: AVX512-E6 43285 REAL_OPCODE: Y 43286 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 43287 PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 43288 OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 43289 IFORM: VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 43290 } 43291 43292 43293 # EMITTING VPMOVSQD (VPMOVSQD-128-1) 43294 { 43295 ICLASS: VPMOVSQD 43296 CPL: 3 43297 CATEGORY: DATAXFER 43298 EXTENSION: AVX512EVEX 43299 ISA_SET: AVX512F_128 43300 EXCEPTIONS: AVX512-E6NF 43301 REAL_OPCODE: Y 43302 ATTRIBUTES: MASKOP_EVEX 43303 PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43304 OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 43305 IFORM: VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 43306 } 43307 43308 43309 # EMITTING VPMOVSQD (VPMOVSQD-128-2) 43310 { 43311 ICLASS: VPMOVSQD 43312 CPL: 3 43313 CATEGORY: DATAXFER 43314 EXTENSION: AVX512EVEX 43315 ISA_SET: AVX512F_128 43316 EXCEPTIONS: AVX512-E6 43317 REAL_OPCODE: Y 43318 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43319 PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 43320 OPERANDS: MEM0:w:q:i32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 43321 IFORM: VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 43322 } 43323 43324 43325 # EMITTING VPMOVSQD (VPMOVSQD-256-1) 43326 { 43327 ICLASS: VPMOVSQD 43328 CPL: 3 43329 CATEGORY: DATAXFER 43330 EXTENSION: AVX512EVEX 43331 ISA_SET: AVX512F_256 43332 EXCEPTIONS: AVX512-E6NF 43333 REAL_OPCODE: Y 43334 ATTRIBUTES: MASKOP_EVEX 43335 PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43336 OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 43337 IFORM: VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 43338 } 43339 43340 43341 # EMITTING VPMOVSQD (VPMOVSQD-256-2) 43342 { 43343 ICLASS: VPMOVSQD 43344 CPL: 3 43345 CATEGORY: DATAXFER 43346 EXTENSION: AVX512EVEX 43347 ISA_SET: AVX512F_256 43348 EXCEPTIONS: AVX512-E6 43349 REAL_OPCODE: Y 43350 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43351 PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 43352 OPERANDS: MEM0:w:dq:i32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 43353 IFORM: VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 43354 } 43355 43356 43357 # EMITTING VPMOVSQW (VPMOVSQW-128-1) 43358 { 43359 ICLASS: VPMOVSQW 43360 CPL: 3 43361 CATEGORY: DATAXFER 43362 EXTENSION: AVX512EVEX 43363 ISA_SET: AVX512F_128 43364 EXCEPTIONS: AVX512-E6NF 43365 REAL_OPCODE: Y 43366 ATTRIBUTES: MASKOP_EVEX 43367 PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43368 OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 43369 IFORM: VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 43370 } 43371 43372 43373 # EMITTING VPMOVSQW (VPMOVSQW-128-2) 43374 { 43375 ICLASS: VPMOVSQW 43376 CPL: 3 43377 CATEGORY: DATAXFER 43378 EXTENSION: AVX512EVEX 43379 ISA_SET: AVX512F_128 43380 EXCEPTIONS: AVX512-E6 43381 REAL_OPCODE: Y 43382 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 43383 PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 43384 OPERANDS: MEM0:w:d:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 43385 IFORM: VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 43386 } 43387 43388 43389 # EMITTING VPMOVSQW (VPMOVSQW-256-1) 43390 { 43391 ICLASS: VPMOVSQW 43392 CPL: 3 43393 CATEGORY: DATAXFER 43394 EXTENSION: AVX512EVEX 43395 ISA_SET: AVX512F_256 43396 EXCEPTIONS: AVX512-E6NF 43397 REAL_OPCODE: Y 43398 ATTRIBUTES: MASKOP_EVEX 43399 PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43400 OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 43401 IFORM: VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 43402 } 43403 43404 43405 # EMITTING VPMOVSQW (VPMOVSQW-256-2) 43406 { 43407 ICLASS: VPMOVSQW 43408 CPL: 3 43409 CATEGORY: DATAXFER 43410 EXTENSION: AVX512EVEX 43411 ISA_SET: AVX512F_256 43412 EXCEPTIONS: AVX512-E6 43413 REAL_OPCODE: Y 43414 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 43415 PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 43416 OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 43417 IFORM: VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 43418 } 43419 43420 43421 # EMITTING VPMOVSWB (VPMOVSWB-128-1) 43422 { 43423 ICLASS: VPMOVSWB 43424 CPL: 3 43425 CATEGORY: DATAXFER 43426 EXTENSION: AVX512EVEX 43427 ISA_SET: AVX512BW_128 43428 EXCEPTIONS: AVX512-E6NF 43429 REAL_OPCODE: Y 43430 ATTRIBUTES: MASKOP_EVEX 43431 PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43432 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i16 43433 IFORM: VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 43434 } 43435 43436 43437 # EMITTING VPMOVSWB (VPMOVSWB-128-2) 43438 { 43439 ICLASS: VPMOVSWB 43440 CPL: 3 43441 CATEGORY: DATAXFER 43442 EXTENSION: AVX512EVEX 43443 ISA_SET: AVX512BW_128 43444 EXCEPTIONS: AVX512-E6 43445 REAL_OPCODE: Y 43446 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43447 PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 43448 OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i16 43449 IFORM: VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 43450 } 43451 43452 43453 # EMITTING VPMOVSWB (VPMOVSWB-256-1) 43454 { 43455 ICLASS: VPMOVSWB 43456 CPL: 3 43457 CATEGORY: DATAXFER 43458 EXTENSION: AVX512EVEX 43459 ISA_SET: AVX512BW_256 43460 EXCEPTIONS: AVX512-E6NF 43461 REAL_OPCODE: Y 43462 ATTRIBUTES: MASKOP_EVEX 43463 PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43464 OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i16 43465 IFORM: VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 43466 } 43467 43468 43469 # EMITTING VPMOVSWB (VPMOVSWB-256-2) 43470 { 43471 ICLASS: VPMOVSWB 43472 CPL: 3 43473 CATEGORY: DATAXFER 43474 EXTENSION: AVX512EVEX 43475 ISA_SET: AVX512BW_256 43476 EXCEPTIONS: AVX512-E6 43477 REAL_OPCODE: Y 43478 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43479 PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 43480 OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i16 43481 IFORM: VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 43482 } 43483 43484 43485 # EMITTING VPMOVSWB (VPMOVSWB-512-1) 43486 { 43487 ICLASS: VPMOVSWB 43488 CPL: 3 43489 CATEGORY: DATAXFER 43490 EXTENSION: AVX512EVEX 43491 ISA_SET: AVX512BW_512 43492 EXCEPTIONS: AVX512-E6NF 43493 REAL_OPCODE: Y 43494 ATTRIBUTES: MASKOP_EVEX 43495 PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 43496 OPERANDS: REG0=YMM_B3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi16 43497 IFORM: VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 43498 } 43499 43500 43501 # EMITTING VPMOVSWB (VPMOVSWB-512-2) 43502 { 43503 ICLASS: VPMOVSWB 43504 CPL: 3 43505 CATEGORY: DATAXFER 43506 EXTENSION: AVX512EVEX 43507 ISA_SET: AVX512BW_512 43508 EXCEPTIONS: AVX512-E6 43509 REAL_OPCODE: Y 43510 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43511 PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 43512 OPERANDS: MEM0:w:qq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi16 43513 IFORM: VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 43514 } 43515 43516 43517 # EMITTING VPMOVSXBD (VPMOVSXBD-128-1) 43518 { 43519 ICLASS: VPMOVSXBD 43520 CPL: 3 43521 CATEGORY: DATAXFER 43522 EXTENSION: AVX512EVEX 43523 ISA_SET: AVX512F_128 43524 EXCEPTIONS: AVX512-E5 43525 REAL_OPCODE: Y 43526 ATTRIBUTES: MASKOP_EVEX 43527 PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 43528 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 43529 IFORM: VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 43530 } 43531 43532 { 43533 ICLASS: VPMOVSXBD 43534 CPL: 3 43535 CATEGORY: DATAXFER 43536 EXTENSION: AVX512EVEX 43537 ISA_SET: AVX512F_128 43538 EXCEPTIONS: AVX512-E5 43539 REAL_OPCODE: Y 43540 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 43541 PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() 43542 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 43543 IFORM: VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 43544 } 43545 43546 43547 # EMITTING VPMOVSXBD (VPMOVSXBD-256-1) 43548 { 43549 ICLASS: VPMOVSXBD 43550 CPL: 3 43551 CATEGORY: DATAXFER 43552 EXTENSION: AVX512EVEX 43553 ISA_SET: AVX512F_256 43554 EXCEPTIONS: AVX512-E5 43555 REAL_OPCODE: Y 43556 ATTRIBUTES: MASKOP_EVEX 43557 PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 43558 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 43559 IFORM: VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 43560 } 43561 43562 { 43563 ICLASS: VPMOVSXBD 43564 CPL: 3 43565 CATEGORY: DATAXFER 43566 EXTENSION: AVX512EVEX 43567 ISA_SET: AVX512F_256 43568 EXCEPTIONS: AVX512-E5 43569 REAL_OPCODE: Y 43570 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 43571 PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() 43572 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 43573 IFORM: VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 43574 } 43575 43576 43577 # EMITTING VPMOVSXBQ (VPMOVSXBQ-128-1) 43578 { 43579 ICLASS: VPMOVSXBQ 43580 CPL: 3 43581 CATEGORY: DATAXFER 43582 EXTENSION: AVX512EVEX 43583 ISA_SET: AVX512F_128 43584 EXCEPTIONS: AVX512-E5 43585 REAL_OPCODE: Y 43586 ATTRIBUTES: MASKOP_EVEX 43587 PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 43588 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 43589 IFORM: VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 43590 } 43591 43592 { 43593 ICLASS: VPMOVSXBQ 43594 CPL: 3 43595 CATEGORY: DATAXFER 43596 EXTENSION: AVX512EVEX 43597 ISA_SET: AVX512F_128 43598 EXCEPTIONS: AVX512-E5 43599 REAL_OPCODE: Y 43600 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 43601 PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() 43602 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 43603 IFORM: VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 43604 } 43605 43606 43607 # EMITTING VPMOVSXBQ (VPMOVSXBQ-256-1) 43608 { 43609 ICLASS: VPMOVSXBQ 43610 CPL: 3 43611 CATEGORY: DATAXFER 43612 EXTENSION: AVX512EVEX 43613 ISA_SET: AVX512F_256 43614 EXCEPTIONS: AVX512-E5 43615 REAL_OPCODE: Y 43616 ATTRIBUTES: MASKOP_EVEX 43617 PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 43618 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 43619 IFORM: VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 43620 } 43621 43622 { 43623 ICLASS: VPMOVSXBQ 43624 CPL: 3 43625 CATEGORY: DATAXFER 43626 EXTENSION: AVX512EVEX 43627 ISA_SET: AVX512F_256 43628 EXCEPTIONS: AVX512-E5 43629 REAL_OPCODE: Y 43630 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 43631 PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() 43632 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 43633 IFORM: VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 43634 } 43635 43636 43637 # EMITTING VPMOVSXBW (VPMOVSXBW-128-1) 43638 { 43639 ICLASS: VPMOVSXBW 43640 CPL: 3 43641 CATEGORY: DATAXFER 43642 EXTENSION: AVX512EVEX 43643 ISA_SET: AVX512BW_128 43644 EXCEPTIONS: AVX512-E5 43645 REAL_OPCODE: Y 43646 ATTRIBUTES: MASKOP_EVEX 43647 PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 43648 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 43649 IFORM: VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 43650 } 43651 43652 { 43653 ICLASS: VPMOVSXBW 43654 CPL: 3 43655 CATEGORY: DATAXFER 43656 EXTENSION: AVX512EVEX 43657 ISA_SET: AVX512BW_128 43658 EXCEPTIONS: AVX512-E5 43659 REAL_OPCODE: Y 43660 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43661 PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() 43662 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 43663 IFORM: VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 43664 } 43665 43666 43667 # EMITTING VPMOVSXBW (VPMOVSXBW-256-1) 43668 { 43669 ICLASS: VPMOVSXBW 43670 CPL: 3 43671 CATEGORY: DATAXFER 43672 EXTENSION: AVX512EVEX 43673 ISA_SET: AVX512BW_256 43674 EXCEPTIONS: AVX512-E5 43675 REAL_OPCODE: Y 43676 ATTRIBUTES: MASKOP_EVEX 43677 PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 43678 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 43679 IFORM: VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 43680 } 43681 43682 { 43683 ICLASS: VPMOVSXBW 43684 CPL: 3 43685 CATEGORY: DATAXFER 43686 EXTENSION: AVX512EVEX 43687 ISA_SET: AVX512BW_256 43688 EXCEPTIONS: AVX512-E5 43689 REAL_OPCODE: Y 43690 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43691 PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() 43692 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 43693 IFORM: VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 43694 } 43695 43696 43697 # EMITTING VPMOVSXBW (VPMOVSXBW-512-1) 43698 { 43699 ICLASS: VPMOVSXBW 43700 CPL: 3 43701 CATEGORY: DATAXFER 43702 EXTENSION: AVX512EVEX 43703 ISA_SET: AVX512BW_512 43704 EXCEPTIONS: AVX512-E5 43705 REAL_OPCODE: Y 43706 ATTRIBUTES: MASKOP_EVEX 43707 PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 43708 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 43709 IFORM: VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 43710 } 43711 43712 { 43713 ICLASS: VPMOVSXBW 43714 CPL: 3 43715 CATEGORY: DATAXFER 43716 EXTENSION: AVX512EVEX 43717 ISA_SET: AVX512BW_512 43718 EXCEPTIONS: AVX512-E5 43719 REAL_OPCODE: Y 43720 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43721 PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() 43722 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 43723 IFORM: VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 43724 } 43725 43726 43727 # EMITTING VPMOVSXDQ (VPMOVSXDQ-128-1) 43728 { 43729 ICLASS: VPMOVSXDQ 43730 CPL: 3 43731 CATEGORY: DATAXFER 43732 EXTENSION: AVX512EVEX 43733 ISA_SET: AVX512F_128 43734 EXCEPTIONS: AVX512-E5 43735 REAL_OPCODE: Y 43736 ATTRIBUTES: MASKOP_EVEX 43737 PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43738 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 43739 IFORM: VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 43740 } 43741 43742 { 43743 ICLASS: VPMOVSXDQ 43744 CPL: 3 43745 CATEGORY: DATAXFER 43746 EXTENSION: AVX512EVEX 43747 ISA_SET: AVX512F_128 43748 EXCEPTIONS: AVX512-E5 43749 REAL_OPCODE: Y 43750 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43751 PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() 43752 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 43753 IFORM: VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 43754 } 43755 43756 43757 # EMITTING VPMOVSXDQ (VPMOVSXDQ-256-1) 43758 { 43759 ICLASS: VPMOVSXDQ 43760 CPL: 3 43761 CATEGORY: DATAXFER 43762 EXTENSION: AVX512EVEX 43763 ISA_SET: AVX512F_256 43764 EXCEPTIONS: AVX512-E5 43765 REAL_OPCODE: Y 43766 ATTRIBUTES: MASKOP_EVEX 43767 PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43768 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 43769 IFORM: VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 43770 } 43771 43772 { 43773 ICLASS: VPMOVSXDQ 43774 CPL: 3 43775 CATEGORY: DATAXFER 43776 EXTENSION: AVX512EVEX 43777 ISA_SET: AVX512F_256 43778 EXCEPTIONS: AVX512-E5 43779 REAL_OPCODE: Y 43780 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43781 PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() 43782 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 43783 IFORM: VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 43784 } 43785 43786 43787 # EMITTING VPMOVSXWD (VPMOVSXWD-128-1) 43788 { 43789 ICLASS: VPMOVSXWD 43790 CPL: 3 43791 CATEGORY: DATAXFER 43792 EXTENSION: AVX512EVEX 43793 ISA_SET: AVX512F_128 43794 EXCEPTIONS: AVX512-E5 43795 REAL_OPCODE: Y 43796 ATTRIBUTES: MASKOP_EVEX 43797 PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 43798 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 43799 IFORM: VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 43800 } 43801 43802 { 43803 ICLASS: VPMOVSXWD 43804 CPL: 3 43805 CATEGORY: DATAXFER 43806 EXTENSION: AVX512EVEX 43807 ISA_SET: AVX512F_128 43808 EXCEPTIONS: AVX512-E5 43809 REAL_OPCODE: Y 43810 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43811 PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 43812 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 43813 IFORM: VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 43814 } 43815 43816 43817 # EMITTING VPMOVSXWD (VPMOVSXWD-256-1) 43818 { 43819 ICLASS: VPMOVSXWD 43820 CPL: 3 43821 CATEGORY: DATAXFER 43822 EXTENSION: AVX512EVEX 43823 ISA_SET: AVX512F_256 43824 EXCEPTIONS: AVX512-E5 43825 REAL_OPCODE: Y 43826 ATTRIBUTES: MASKOP_EVEX 43827 PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 43828 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 43829 IFORM: VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 43830 } 43831 43832 { 43833 ICLASS: VPMOVSXWD 43834 CPL: 3 43835 CATEGORY: DATAXFER 43836 EXTENSION: AVX512EVEX 43837 ISA_SET: AVX512F_256 43838 EXCEPTIONS: AVX512-E5 43839 REAL_OPCODE: Y 43840 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43841 PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 43842 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 43843 IFORM: VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 43844 } 43845 43846 43847 # EMITTING VPMOVSXWQ (VPMOVSXWQ-128-1) 43848 { 43849 ICLASS: VPMOVSXWQ 43850 CPL: 3 43851 CATEGORY: DATAXFER 43852 EXTENSION: AVX512EVEX 43853 ISA_SET: AVX512F_128 43854 EXCEPTIONS: AVX512-E5 43855 REAL_OPCODE: Y 43856 ATTRIBUTES: MASKOP_EVEX 43857 PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 43858 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 43859 IFORM: VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 43860 } 43861 43862 { 43863 ICLASS: VPMOVSXWQ 43864 CPL: 3 43865 CATEGORY: DATAXFER 43866 EXTENSION: AVX512EVEX 43867 ISA_SET: AVX512F_128 43868 EXCEPTIONS: AVX512-E5 43869 REAL_OPCODE: Y 43870 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 43871 PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() 43872 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 43873 IFORM: VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 43874 } 43875 43876 43877 # EMITTING VPMOVSXWQ (VPMOVSXWQ-256-1) 43878 { 43879 ICLASS: VPMOVSXWQ 43880 CPL: 3 43881 CATEGORY: DATAXFER 43882 EXTENSION: AVX512EVEX 43883 ISA_SET: AVX512F_256 43884 EXCEPTIONS: AVX512-E5 43885 REAL_OPCODE: Y 43886 ATTRIBUTES: MASKOP_EVEX 43887 PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 43888 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 43889 IFORM: VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 43890 } 43891 43892 { 43893 ICLASS: VPMOVSXWQ 43894 CPL: 3 43895 CATEGORY: DATAXFER 43896 EXTENSION: AVX512EVEX 43897 ISA_SET: AVX512F_256 43898 EXCEPTIONS: AVX512-E5 43899 REAL_OPCODE: Y 43900 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 43901 PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() 43902 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 43903 IFORM: VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 43904 } 43905 43906 43907 # EMITTING VPMOVUSDB (VPMOVUSDB-128-1) 43908 { 43909 ICLASS: VPMOVUSDB 43910 CPL: 3 43911 CATEGORY: DATAXFER 43912 EXTENSION: AVX512EVEX 43913 ISA_SET: AVX512F_128 43914 EXCEPTIONS: AVX512-E6NF 43915 REAL_OPCODE: Y 43916 ATTRIBUTES: MASKOP_EVEX 43917 PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43918 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 43919 IFORM: VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 43920 } 43921 43922 43923 # EMITTING VPMOVUSDB (VPMOVUSDB-128-2) 43924 { 43925 ICLASS: VPMOVUSDB 43926 CPL: 3 43927 CATEGORY: DATAXFER 43928 EXTENSION: AVX512EVEX 43929 ISA_SET: AVX512F_128 43930 EXCEPTIONS: AVX512-E6 43931 REAL_OPCODE: Y 43932 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 43933 PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 43934 OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 43935 IFORM: VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 43936 } 43937 43938 43939 # EMITTING VPMOVUSDB (VPMOVUSDB-256-1) 43940 { 43941 ICLASS: VPMOVUSDB 43942 CPL: 3 43943 CATEGORY: DATAXFER 43944 EXTENSION: AVX512EVEX 43945 ISA_SET: AVX512F_256 43946 EXCEPTIONS: AVX512-E6NF 43947 REAL_OPCODE: Y 43948 ATTRIBUTES: MASKOP_EVEX 43949 PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 43950 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 43951 IFORM: VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 43952 } 43953 43954 43955 # EMITTING VPMOVUSDB (VPMOVUSDB-256-2) 43956 { 43957 ICLASS: VPMOVUSDB 43958 CPL: 3 43959 CATEGORY: DATAXFER 43960 EXTENSION: AVX512EVEX 43961 ISA_SET: AVX512F_256 43962 EXCEPTIONS: AVX512-E6 43963 REAL_OPCODE: Y 43964 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 43965 PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() 43966 OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 43967 IFORM: VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 43968 } 43969 43970 43971 # EMITTING VPMOVUSDW (VPMOVUSDW-128-1) 43972 { 43973 ICLASS: VPMOVUSDW 43974 CPL: 3 43975 CATEGORY: DATAXFER 43976 EXTENSION: AVX512EVEX 43977 ISA_SET: AVX512F_128 43978 EXCEPTIONS: AVX512-E6NF 43979 REAL_OPCODE: Y 43980 ATTRIBUTES: MASKOP_EVEX 43981 PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 43982 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 43983 IFORM: VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 43984 } 43985 43986 43987 # EMITTING VPMOVUSDW (VPMOVUSDW-128-2) 43988 { 43989 ICLASS: VPMOVUSDW 43990 CPL: 3 43991 CATEGORY: DATAXFER 43992 EXTENSION: AVX512EVEX 43993 ISA_SET: AVX512F_128 43994 EXCEPTIONS: AVX512-E6 43995 REAL_OPCODE: Y 43996 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 43997 PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 43998 OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 43999 IFORM: VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 44000 } 44001 44002 44003 # EMITTING VPMOVUSDW (VPMOVUSDW-256-1) 44004 { 44005 ICLASS: VPMOVUSDW 44006 CPL: 3 44007 CATEGORY: DATAXFER 44008 EXTENSION: AVX512EVEX 44009 ISA_SET: AVX512F_256 44010 EXCEPTIONS: AVX512-E6NF 44011 REAL_OPCODE: Y 44012 ATTRIBUTES: MASKOP_EVEX 44013 PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 44014 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 44015 IFORM: VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 44016 } 44017 44018 44019 # EMITTING VPMOVUSDW (VPMOVUSDW-256-2) 44020 { 44021 ICLASS: VPMOVUSDW 44022 CPL: 3 44023 CATEGORY: DATAXFER 44024 EXTENSION: AVX512EVEX 44025 ISA_SET: AVX512F_256 44026 EXCEPTIONS: AVX512-E6 44027 REAL_OPCODE: Y 44028 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44029 PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() 44030 OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 44031 IFORM: VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 44032 } 44033 44034 44035 # EMITTING VPMOVUSQB (VPMOVUSQB-128-1) 44036 { 44037 ICLASS: VPMOVUSQB 44038 CPL: 3 44039 CATEGORY: DATAXFER 44040 EXTENSION: AVX512EVEX 44041 ISA_SET: AVX512F_128 44042 EXCEPTIONS: AVX512-E6NF 44043 REAL_OPCODE: Y 44044 ATTRIBUTES: MASKOP_EVEX 44045 PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 44046 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 44047 IFORM: VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 44048 } 44049 44050 44051 # EMITTING VPMOVUSQB (VPMOVUSQB-128-2) 44052 { 44053 ICLASS: VPMOVUSQB 44054 CPL: 3 44055 CATEGORY: DATAXFER 44056 EXTENSION: AVX512EVEX 44057 ISA_SET: AVX512F_128 44058 EXCEPTIONS: AVX512-E6 44059 REAL_OPCODE: Y 44060 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 44061 PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 44062 OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 44063 IFORM: VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 44064 } 44065 44066 44067 # EMITTING VPMOVUSQB (VPMOVUSQB-256-1) 44068 { 44069 ICLASS: VPMOVUSQB 44070 CPL: 3 44071 CATEGORY: DATAXFER 44072 EXTENSION: AVX512EVEX 44073 ISA_SET: AVX512F_256 44074 EXCEPTIONS: AVX512-E6NF 44075 REAL_OPCODE: Y 44076 ATTRIBUTES: MASKOP_EVEX 44077 PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 44078 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 44079 IFORM: VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 44080 } 44081 44082 44083 # EMITTING VPMOVUSQB (VPMOVUSQB-256-2) 44084 { 44085 ICLASS: VPMOVUSQB 44086 CPL: 3 44087 CATEGORY: DATAXFER 44088 EXTENSION: AVX512EVEX 44089 ISA_SET: AVX512F_256 44090 EXCEPTIONS: AVX512-E6 44091 REAL_OPCODE: Y 44092 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 44093 PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() 44094 OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 44095 IFORM: VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 44096 } 44097 44098 44099 # EMITTING VPMOVUSQD (VPMOVUSQD-128-1) 44100 { 44101 ICLASS: VPMOVUSQD 44102 CPL: 3 44103 CATEGORY: DATAXFER 44104 EXTENSION: AVX512EVEX 44105 ISA_SET: AVX512F_128 44106 EXCEPTIONS: AVX512-E6NF 44107 REAL_OPCODE: Y 44108 ATTRIBUTES: MASKOP_EVEX 44109 PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 44110 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 44111 IFORM: VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 44112 } 44113 44114 44115 # EMITTING VPMOVUSQD (VPMOVUSQD-128-2) 44116 { 44117 ICLASS: VPMOVUSQD 44118 CPL: 3 44119 CATEGORY: DATAXFER 44120 EXTENSION: AVX512EVEX 44121 ISA_SET: AVX512F_128 44122 EXCEPTIONS: AVX512-E6 44123 REAL_OPCODE: Y 44124 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44125 PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 44126 OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 44127 IFORM: VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 44128 } 44129 44130 44131 # EMITTING VPMOVUSQD (VPMOVUSQD-256-1) 44132 { 44133 ICLASS: VPMOVUSQD 44134 CPL: 3 44135 CATEGORY: DATAXFER 44136 EXTENSION: AVX512EVEX 44137 ISA_SET: AVX512F_256 44138 EXCEPTIONS: AVX512-E6NF 44139 REAL_OPCODE: Y 44140 ATTRIBUTES: MASKOP_EVEX 44141 PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 44142 OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 44143 IFORM: VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 44144 } 44145 44146 44147 # EMITTING VPMOVUSQD (VPMOVUSQD-256-2) 44148 { 44149 ICLASS: VPMOVUSQD 44150 CPL: 3 44151 CATEGORY: DATAXFER 44152 EXTENSION: AVX512EVEX 44153 ISA_SET: AVX512F_256 44154 EXCEPTIONS: AVX512-E6 44155 REAL_OPCODE: Y 44156 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44157 PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() 44158 OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 44159 IFORM: VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 44160 } 44161 44162 44163 # EMITTING VPMOVUSQW (VPMOVUSQW-128-1) 44164 { 44165 ICLASS: VPMOVUSQW 44166 CPL: 3 44167 CATEGORY: DATAXFER 44168 EXTENSION: AVX512EVEX 44169 ISA_SET: AVX512F_128 44170 EXCEPTIONS: AVX512-E6NF 44171 REAL_OPCODE: Y 44172 ATTRIBUTES: MASKOP_EVEX 44173 PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 44174 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 44175 IFORM: VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 44176 } 44177 44178 44179 # EMITTING VPMOVUSQW (VPMOVUSQW-128-2) 44180 { 44181 ICLASS: VPMOVUSQW 44182 CPL: 3 44183 CATEGORY: DATAXFER 44184 EXTENSION: AVX512EVEX 44185 ISA_SET: AVX512F_128 44186 EXCEPTIONS: AVX512-E6 44187 REAL_OPCODE: Y 44188 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 44189 PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 44190 OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 44191 IFORM: VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 44192 } 44193 44194 44195 # EMITTING VPMOVUSQW (VPMOVUSQW-256-1) 44196 { 44197 ICLASS: VPMOVUSQW 44198 CPL: 3 44199 CATEGORY: DATAXFER 44200 EXTENSION: AVX512EVEX 44201 ISA_SET: AVX512F_256 44202 EXCEPTIONS: AVX512-E6NF 44203 REAL_OPCODE: Y 44204 ATTRIBUTES: MASKOP_EVEX 44205 PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 44206 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 44207 IFORM: VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 44208 } 44209 44210 44211 # EMITTING VPMOVUSQW (VPMOVUSQW-256-2) 44212 { 44213 ICLASS: VPMOVUSQW 44214 CPL: 3 44215 CATEGORY: DATAXFER 44216 EXTENSION: AVX512EVEX 44217 ISA_SET: AVX512F_256 44218 EXCEPTIONS: AVX512-E6 44219 REAL_OPCODE: Y 44220 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 44221 PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() 44222 OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 44223 IFORM: VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 44224 } 44225 44226 44227 # EMITTING VPMOVUSWB (VPMOVUSWB-128-1) 44228 { 44229 ICLASS: VPMOVUSWB 44230 CPL: 3 44231 CATEGORY: DATAXFER 44232 EXTENSION: AVX512EVEX 44233 ISA_SET: AVX512BW_128 44234 EXCEPTIONS: AVX512-E6NF 44235 REAL_OPCODE: Y 44236 ATTRIBUTES: MASKOP_EVEX 44237 PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 44238 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 44239 IFORM: VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 44240 } 44241 44242 44243 # EMITTING VPMOVUSWB (VPMOVUSWB-128-2) 44244 { 44245 ICLASS: VPMOVUSWB 44246 CPL: 3 44247 CATEGORY: DATAXFER 44248 EXTENSION: AVX512EVEX 44249 ISA_SET: AVX512BW_128 44250 EXCEPTIONS: AVX512-E6 44251 REAL_OPCODE: Y 44252 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44253 PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 44254 OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 44255 IFORM: VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 44256 } 44257 44258 44259 # EMITTING VPMOVUSWB (VPMOVUSWB-256-1) 44260 { 44261 ICLASS: VPMOVUSWB 44262 CPL: 3 44263 CATEGORY: DATAXFER 44264 EXTENSION: AVX512EVEX 44265 ISA_SET: AVX512BW_256 44266 EXCEPTIONS: AVX512-E6NF 44267 REAL_OPCODE: Y 44268 ATTRIBUTES: MASKOP_EVEX 44269 PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 44270 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 44271 IFORM: VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 44272 } 44273 44274 44275 # EMITTING VPMOVUSWB (VPMOVUSWB-256-2) 44276 { 44277 ICLASS: VPMOVUSWB 44278 CPL: 3 44279 CATEGORY: DATAXFER 44280 EXTENSION: AVX512EVEX 44281 ISA_SET: AVX512BW_256 44282 EXCEPTIONS: AVX512-E6 44283 REAL_OPCODE: Y 44284 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44285 PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 44286 OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 44287 IFORM: VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 44288 } 44289 44290 44291 # EMITTING VPMOVUSWB (VPMOVUSWB-512-1) 44292 { 44293 ICLASS: VPMOVUSWB 44294 CPL: 3 44295 CATEGORY: DATAXFER 44296 EXTENSION: AVX512EVEX 44297 ISA_SET: AVX512BW_512 44298 EXCEPTIONS: AVX512-E6NF 44299 REAL_OPCODE: Y 44300 ATTRIBUTES: MASKOP_EVEX 44301 PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 44302 OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 44303 IFORM: VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 44304 } 44305 44306 44307 # EMITTING VPMOVUSWB (VPMOVUSWB-512-2) 44308 { 44309 ICLASS: VPMOVUSWB 44310 CPL: 3 44311 CATEGORY: DATAXFER 44312 EXTENSION: AVX512EVEX 44313 ISA_SET: AVX512BW_512 44314 EXCEPTIONS: AVX512-E6 44315 REAL_OPCODE: Y 44316 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44317 PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 44318 OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 44319 IFORM: VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 44320 } 44321 44322 44323 # EMITTING VPMOVW2M (VPMOVW2M-128-1) 44324 { 44325 ICLASS: VPMOVW2M 44326 CPL: 3 44327 CATEGORY: DATAXFER 44328 EXTENSION: AVX512EVEX 44329 ISA_SET: AVX512BW_128 44330 EXCEPTIONS: AVX512-E7NM 44331 REAL_OPCODE: Y 44332 PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 44333 OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u16 44334 IFORM: VPMOVW2M_MASKmskw_XMMu16_AVX512 44335 } 44336 44337 44338 # EMITTING VPMOVW2M (VPMOVW2M-256-1) 44339 { 44340 ICLASS: VPMOVW2M 44341 CPL: 3 44342 CATEGORY: DATAXFER 44343 EXTENSION: AVX512EVEX 44344 ISA_SET: AVX512BW_256 44345 EXCEPTIONS: AVX512-E7NM 44346 REAL_OPCODE: Y 44347 PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 44348 OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u16 44349 IFORM: VPMOVW2M_MASKmskw_YMMu16_AVX512 44350 } 44351 44352 44353 # EMITTING VPMOVW2M (VPMOVW2M-512-1) 44354 { 44355 ICLASS: VPMOVW2M 44356 CPL: 3 44357 CATEGORY: DATAXFER 44358 EXTENSION: AVX512EVEX 44359 ISA_SET: AVX512BW_512 44360 EXCEPTIONS: AVX512-E7NM 44361 REAL_OPCODE: Y 44362 PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 44363 OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu16 44364 IFORM: VPMOVW2M_MASKmskw_ZMMu16_AVX512 44365 } 44366 44367 44368 # EMITTING VPMOVWB (VPMOVWB-128-1) 44369 { 44370 ICLASS: VPMOVWB 44371 CPL: 3 44372 CATEGORY: DATAXFER 44373 EXTENSION: AVX512EVEX 44374 ISA_SET: AVX512BW_128 44375 EXCEPTIONS: AVX512-E6NF 44376 REAL_OPCODE: Y 44377 ATTRIBUTES: MASKOP_EVEX 44378 PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 44379 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 44380 IFORM: VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 44381 } 44382 44383 44384 # EMITTING VPMOVWB (VPMOVWB-128-2) 44385 { 44386 ICLASS: VPMOVWB 44387 CPL: 3 44388 CATEGORY: DATAXFER 44389 EXTENSION: AVX512EVEX 44390 ISA_SET: AVX512BW_128 44391 EXCEPTIONS: AVX512-E6 44392 REAL_OPCODE: Y 44393 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44394 PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 44395 OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 44396 IFORM: VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 44397 } 44398 44399 44400 # EMITTING VPMOVWB (VPMOVWB-256-1) 44401 { 44402 ICLASS: VPMOVWB 44403 CPL: 3 44404 CATEGORY: DATAXFER 44405 EXTENSION: AVX512EVEX 44406 ISA_SET: AVX512BW_256 44407 EXCEPTIONS: AVX512-E6NF 44408 REAL_OPCODE: Y 44409 ATTRIBUTES: MASKOP_EVEX 44410 PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 44411 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 44412 IFORM: VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 44413 } 44414 44415 44416 # EMITTING VPMOVWB (VPMOVWB-256-2) 44417 { 44418 ICLASS: VPMOVWB 44419 CPL: 3 44420 CATEGORY: DATAXFER 44421 EXTENSION: AVX512EVEX 44422 ISA_SET: AVX512BW_256 44423 EXCEPTIONS: AVX512-E6 44424 REAL_OPCODE: Y 44425 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44426 PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 44427 OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 44428 IFORM: VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 44429 } 44430 44431 44432 # EMITTING VPMOVWB (VPMOVWB-512-1) 44433 { 44434 ICLASS: VPMOVWB 44435 CPL: 3 44436 CATEGORY: DATAXFER 44437 EXTENSION: AVX512EVEX 44438 ISA_SET: AVX512BW_512 44439 EXCEPTIONS: AVX512-E6NF 44440 REAL_OPCODE: Y 44441 ATTRIBUTES: MASKOP_EVEX 44442 PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 44443 OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 44444 IFORM: VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 44445 } 44446 44447 44448 # EMITTING VPMOVWB (VPMOVWB-512-2) 44449 { 44450 ICLASS: VPMOVWB 44451 CPL: 3 44452 CATEGORY: DATAXFER 44453 EXTENSION: AVX512EVEX 44454 ISA_SET: AVX512BW_512 44455 EXCEPTIONS: AVX512-E6 44456 REAL_OPCODE: Y 44457 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44458 PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() 44459 OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 44460 IFORM: VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 44461 } 44462 44463 44464 # EMITTING VPMOVZXBD (VPMOVZXBD-128-1) 44465 { 44466 ICLASS: VPMOVZXBD 44467 CPL: 3 44468 CATEGORY: DATAXFER 44469 EXTENSION: AVX512EVEX 44470 ISA_SET: AVX512F_128 44471 EXCEPTIONS: AVX512-E5 44472 REAL_OPCODE: Y 44473 ATTRIBUTES: MASKOP_EVEX 44474 PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 44475 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 44476 IFORM: VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 44477 } 44478 44479 { 44480 ICLASS: VPMOVZXBD 44481 CPL: 3 44482 CATEGORY: DATAXFER 44483 EXTENSION: AVX512EVEX 44484 ISA_SET: AVX512F_128 44485 EXCEPTIONS: AVX512-E5 44486 REAL_OPCODE: Y 44487 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 44488 PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() 44489 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 44490 IFORM: VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 44491 } 44492 44493 44494 # EMITTING VPMOVZXBD (VPMOVZXBD-256-1) 44495 { 44496 ICLASS: VPMOVZXBD 44497 CPL: 3 44498 CATEGORY: DATAXFER 44499 EXTENSION: AVX512EVEX 44500 ISA_SET: AVX512F_256 44501 EXCEPTIONS: AVX512-E5 44502 REAL_OPCODE: Y 44503 ATTRIBUTES: MASKOP_EVEX 44504 PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 44505 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 44506 IFORM: VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 44507 } 44508 44509 { 44510 ICLASS: VPMOVZXBD 44511 CPL: 3 44512 CATEGORY: DATAXFER 44513 EXTENSION: AVX512EVEX 44514 ISA_SET: AVX512F_256 44515 EXCEPTIONS: AVX512-E5 44516 REAL_OPCODE: Y 44517 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 44518 PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() 44519 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 44520 IFORM: VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 44521 } 44522 44523 44524 # EMITTING VPMOVZXBQ (VPMOVZXBQ-128-1) 44525 { 44526 ICLASS: VPMOVZXBQ 44527 CPL: 3 44528 CATEGORY: DATAXFER 44529 EXTENSION: AVX512EVEX 44530 ISA_SET: AVX512F_128 44531 EXCEPTIONS: AVX512-E5 44532 REAL_OPCODE: Y 44533 ATTRIBUTES: MASKOP_EVEX 44534 PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 44535 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 44536 IFORM: VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 44537 } 44538 44539 { 44540 ICLASS: VPMOVZXBQ 44541 CPL: 3 44542 CATEGORY: DATAXFER 44543 EXTENSION: AVX512EVEX 44544 ISA_SET: AVX512F_128 44545 EXCEPTIONS: AVX512-E5 44546 REAL_OPCODE: Y 44547 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 44548 PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() 44549 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 44550 IFORM: VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 44551 } 44552 44553 44554 # EMITTING VPMOVZXBQ (VPMOVZXBQ-256-1) 44555 { 44556 ICLASS: VPMOVZXBQ 44557 CPL: 3 44558 CATEGORY: DATAXFER 44559 EXTENSION: AVX512EVEX 44560 ISA_SET: AVX512F_256 44561 EXCEPTIONS: AVX512-E5 44562 REAL_OPCODE: Y 44563 ATTRIBUTES: MASKOP_EVEX 44564 PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 44565 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 44566 IFORM: VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 44567 } 44568 44569 { 44570 ICLASS: VPMOVZXBQ 44571 CPL: 3 44572 CATEGORY: DATAXFER 44573 EXTENSION: AVX512EVEX 44574 ISA_SET: AVX512F_256 44575 EXCEPTIONS: AVX512-E5 44576 REAL_OPCODE: Y 44577 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM 44578 PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() 44579 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 44580 IFORM: VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 44581 } 44582 44583 44584 # EMITTING VPMOVZXBW (VPMOVZXBW-128-1) 44585 { 44586 ICLASS: VPMOVZXBW 44587 CPL: 3 44588 CATEGORY: DATAXFER 44589 EXTENSION: AVX512EVEX 44590 ISA_SET: AVX512BW_128 44591 EXCEPTIONS: AVX512-E5 44592 REAL_OPCODE: Y 44593 ATTRIBUTES: MASKOP_EVEX 44594 PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 44595 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 44596 IFORM: VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 44597 } 44598 44599 { 44600 ICLASS: VPMOVZXBW 44601 CPL: 3 44602 CATEGORY: DATAXFER 44603 EXTENSION: AVX512EVEX 44604 ISA_SET: AVX512BW_128 44605 EXCEPTIONS: AVX512-E5 44606 REAL_OPCODE: Y 44607 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44608 PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() 44609 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 44610 IFORM: VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 44611 } 44612 44613 44614 # EMITTING VPMOVZXBW (VPMOVZXBW-256-1) 44615 { 44616 ICLASS: VPMOVZXBW 44617 CPL: 3 44618 CATEGORY: DATAXFER 44619 EXTENSION: AVX512EVEX 44620 ISA_SET: AVX512BW_256 44621 EXCEPTIONS: AVX512-E5 44622 REAL_OPCODE: Y 44623 ATTRIBUTES: MASKOP_EVEX 44624 PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 44625 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 44626 IFORM: VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 44627 } 44628 44629 { 44630 ICLASS: VPMOVZXBW 44631 CPL: 3 44632 CATEGORY: DATAXFER 44633 EXTENSION: AVX512EVEX 44634 ISA_SET: AVX512BW_256 44635 EXCEPTIONS: AVX512-E5 44636 REAL_OPCODE: Y 44637 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44638 PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() 44639 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 44640 IFORM: VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 44641 } 44642 44643 44644 # EMITTING VPMOVZXBW (VPMOVZXBW-512-1) 44645 { 44646 ICLASS: VPMOVZXBW 44647 CPL: 3 44648 CATEGORY: DATAXFER 44649 EXTENSION: AVX512EVEX 44650 ISA_SET: AVX512BW_512 44651 EXCEPTIONS: AVX512-E5 44652 REAL_OPCODE: Y 44653 ATTRIBUTES: MASKOP_EVEX 44654 PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR 44655 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 44656 IFORM: VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 44657 } 44658 44659 { 44660 ICLASS: VPMOVZXBW 44661 CPL: 3 44662 CATEGORY: DATAXFER 44663 EXTENSION: AVX512EVEX 44664 ISA_SET: AVX512BW_512 44665 EXCEPTIONS: AVX512-E5 44666 REAL_OPCODE: Y 44667 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44668 PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() 44669 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 44670 IFORM: VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 44671 } 44672 44673 44674 # EMITTING VPMOVZXDQ (VPMOVZXDQ-128-1) 44675 { 44676 ICLASS: VPMOVZXDQ 44677 CPL: 3 44678 CATEGORY: DATAXFER 44679 EXTENSION: AVX512EVEX 44680 ISA_SET: AVX512F_128 44681 EXCEPTIONS: AVX512-E5 44682 REAL_OPCODE: Y 44683 ATTRIBUTES: MASKOP_EVEX 44684 PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 44685 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 44686 IFORM: VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 44687 } 44688 44689 { 44690 ICLASS: VPMOVZXDQ 44691 CPL: 3 44692 CATEGORY: DATAXFER 44693 EXTENSION: AVX512EVEX 44694 ISA_SET: AVX512F_128 44695 EXCEPTIONS: AVX512-E5 44696 REAL_OPCODE: Y 44697 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44698 PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() 44699 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 44700 IFORM: VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 44701 } 44702 44703 44704 # EMITTING VPMOVZXDQ (VPMOVZXDQ-256-1) 44705 { 44706 ICLASS: VPMOVZXDQ 44707 CPL: 3 44708 CATEGORY: DATAXFER 44709 EXTENSION: AVX512EVEX 44710 ISA_SET: AVX512F_256 44711 EXCEPTIONS: AVX512-E5 44712 REAL_OPCODE: Y 44713 ATTRIBUTES: MASKOP_EVEX 44714 PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 44715 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 44716 IFORM: VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 44717 } 44718 44719 { 44720 ICLASS: VPMOVZXDQ 44721 CPL: 3 44722 CATEGORY: DATAXFER 44723 EXTENSION: AVX512EVEX 44724 ISA_SET: AVX512F_256 44725 EXCEPTIONS: AVX512-E5 44726 REAL_OPCODE: Y 44727 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44728 PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() 44729 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 44730 IFORM: VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 44731 } 44732 44733 44734 # EMITTING VPMOVZXWD (VPMOVZXWD-128-1) 44735 { 44736 ICLASS: VPMOVZXWD 44737 CPL: 3 44738 CATEGORY: DATAXFER 44739 EXTENSION: AVX512EVEX 44740 ISA_SET: AVX512F_128 44741 EXCEPTIONS: AVX512-E5 44742 REAL_OPCODE: Y 44743 ATTRIBUTES: MASKOP_EVEX 44744 PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 44745 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 44746 IFORM: VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 44747 } 44748 44749 { 44750 ICLASS: VPMOVZXWD 44751 CPL: 3 44752 CATEGORY: DATAXFER 44753 EXTENSION: AVX512EVEX 44754 ISA_SET: AVX512F_128 44755 EXCEPTIONS: AVX512-E5 44756 REAL_OPCODE: Y 44757 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44758 PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 44759 OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 44760 IFORM: VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 44761 } 44762 44763 44764 # EMITTING VPMOVZXWD (VPMOVZXWD-256-1) 44765 { 44766 ICLASS: VPMOVZXWD 44767 CPL: 3 44768 CATEGORY: DATAXFER 44769 EXTENSION: AVX512EVEX 44770 ISA_SET: AVX512F_256 44771 EXCEPTIONS: AVX512-E5 44772 REAL_OPCODE: Y 44773 ATTRIBUTES: MASKOP_EVEX 44774 PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 44775 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 44776 IFORM: VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 44777 } 44778 44779 { 44780 ICLASS: VPMOVZXWD 44781 CPL: 3 44782 CATEGORY: DATAXFER 44783 EXTENSION: AVX512EVEX 44784 ISA_SET: AVX512F_256 44785 EXCEPTIONS: AVX512-E5 44786 REAL_OPCODE: Y 44787 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM 44788 PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() 44789 OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 44790 IFORM: VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 44791 } 44792 44793 44794 # EMITTING VPMOVZXWQ (VPMOVZXWQ-128-1) 44795 { 44796 ICLASS: VPMOVZXWQ 44797 CPL: 3 44798 CATEGORY: DATAXFER 44799 EXTENSION: AVX512EVEX 44800 ISA_SET: AVX512F_128 44801 EXCEPTIONS: AVX512-E5 44802 REAL_OPCODE: Y 44803 ATTRIBUTES: MASKOP_EVEX 44804 PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR 44805 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 44806 IFORM: VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 44807 } 44808 44809 { 44810 ICLASS: VPMOVZXWQ 44811 CPL: 3 44812 CATEGORY: DATAXFER 44813 EXTENSION: AVX512EVEX 44814 ISA_SET: AVX512F_128 44815 EXCEPTIONS: AVX512-E5 44816 REAL_OPCODE: Y 44817 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 44818 PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() 44819 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 44820 IFORM: VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 44821 } 44822 44823 44824 # EMITTING VPMOVZXWQ (VPMOVZXWQ-256-1) 44825 { 44826 ICLASS: VPMOVZXWQ 44827 CPL: 3 44828 CATEGORY: DATAXFER 44829 EXTENSION: AVX512EVEX 44830 ISA_SET: AVX512F_256 44831 EXCEPTIONS: AVX512-E5 44832 REAL_OPCODE: Y 44833 ATTRIBUTES: MASKOP_EVEX 44834 PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR 44835 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 44836 IFORM: VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 44837 } 44838 44839 { 44840 ICLASS: VPMOVZXWQ 44841 CPL: 3 44842 CATEGORY: DATAXFER 44843 EXTENSION: AVX512EVEX 44844 ISA_SET: AVX512F_256 44845 EXCEPTIONS: AVX512-E5 44846 REAL_OPCODE: Y 44847 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM 44848 PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() 44849 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 44850 IFORM: VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 44851 } 44852 44853 44854 # EMITTING VPMULDQ (VPMULDQ-128-1) 44855 { 44856 ICLASS: VPMULDQ 44857 CPL: 3 44858 CATEGORY: AVX512 44859 EXTENSION: AVX512EVEX 44860 ISA_SET: AVX512F_128 44861 EXCEPTIONS: AVX512-E4 44862 REAL_OPCODE: Y 44863 COMMENT: Strange instruction that uses 32b of each 64b input element 44864 ATTRIBUTES: MASKOP_EVEX 44865 PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 44866 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 44867 IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 44868 } 44869 44870 { 44871 ICLASS: VPMULDQ 44872 CPL: 3 44873 CATEGORY: AVX512 44874 EXTENSION: AVX512EVEX 44875 ISA_SET: AVX512F_128 44876 EXCEPTIONS: AVX512-E4 44877 REAL_OPCODE: Y 44878 COMMENT: Strange instruction that uses 32b of each 64b input element 44879 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX 44880 PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 44881 OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 44882 IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 44883 } 44884 44885 44886 # EMITTING VPMULDQ (VPMULDQ-256-1) 44887 { 44888 ICLASS: VPMULDQ 44889 CPL: 3 44890 CATEGORY: AVX512 44891 EXTENSION: AVX512EVEX 44892 ISA_SET: AVX512F_256 44893 EXCEPTIONS: AVX512-E4 44894 REAL_OPCODE: Y 44895 COMMENT: Strange instruction that uses 32b of each 64b input element 44896 ATTRIBUTES: MASKOP_EVEX 44897 PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 44898 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 44899 IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 44900 } 44901 44902 { 44903 ICLASS: VPMULDQ 44904 CPL: 3 44905 CATEGORY: AVX512 44906 EXTENSION: AVX512EVEX 44907 ISA_SET: AVX512F_256 44908 EXCEPTIONS: AVX512-E4 44909 REAL_OPCODE: Y 44910 COMMENT: Strange instruction that uses 32b of each 64b input element 44911 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX 44912 PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 44913 OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR 44914 IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 44915 } 44916 44917 44918 # EMITTING VPMULHRSW (VPMULHRSW-128-1) 44919 { 44920 ICLASS: VPMULHRSW 44921 CPL: 3 44922 CATEGORY: AVX512 44923 EXTENSION: AVX512EVEX 44924 ISA_SET: AVX512BW_128 44925 EXCEPTIONS: AVX512-E4 44926 REAL_OPCODE: Y 44927 ATTRIBUTES: MASKOP_EVEX 44928 PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 44929 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 44930 IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 44931 } 44932 44933 { 44934 ICLASS: VPMULHRSW 44935 CPL: 3 44936 CATEGORY: AVX512 44937 EXTENSION: AVX512EVEX 44938 ISA_SET: AVX512BW_128 44939 EXCEPTIONS: AVX512-E4 44940 REAL_OPCODE: Y 44941 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 44942 PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 44943 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 44944 IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 44945 } 44946 44947 44948 # EMITTING VPMULHRSW (VPMULHRSW-256-1) 44949 { 44950 ICLASS: VPMULHRSW 44951 CPL: 3 44952 CATEGORY: AVX512 44953 EXTENSION: AVX512EVEX 44954 ISA_SET: AVX512BW_256 44955 EXCEPTIONS: AVX512-E4 44956 REAL_OPCODE: Y 44957 ATTRIBUTES: MASKOP_EVEX 44958 PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 44959 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 44960 IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 44961 } 44962 44963 { 44964 ICLASS: VPMULHRSW 44965 CPL: 3 44966 CATEGORY: AVX512 44967 EXTENSION: AVX512EVEX 44968 ISA_SET: AVX512BW_256 44969 EXCEPTIONS: AVX512-E4 44970 REAL_OPCODE: Y 44971 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 44972 PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 44973 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 44974 IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 44975 } 44976 44977 44978 # EMITTING VPMULHRSW (VPMULHRSW-512-1) 44979 { 44980 ICLASS: VPMULHRSW 44981 CPL: 3 44982 CATEGORY: AVX512 44983 EXTENSION: AVX512EVEX 44984 ISA_SET: AVX512BW_512 44985 EXCEPTIONS: AVX512-E4 44986 REAL_OPCODE: Y 44987 ATTRIBUTES: MASKOP_EVEX 44988 PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 44989 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 44990 IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 44991 } 44992 44993 { 44994 ICLASS: VPMULHRSW 44995 CPL: 3 44996 CATEGORY: AVX512 44997 EXTENSION: AVX512EVEX 44998 ISA_SET: AVX512BW_512 44999 EXCEPTIONS: AVX512-E4 45000 REAL_OPCODE: Y 45001 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 45002 PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 45003 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 45004 IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 45005 } 45006 45007 45008 # EMITTING VPMULHUW (VPMULHUW-128-1) 45009 { 45010 ICLASS: VPMULHUW 45011 CPL: 3 45012 CATEGORY: AVX512 45013 EXTENSION: AVX512EVEX 45014 ISA_SET: AVX512BW_128 45015 EXCEPTIONS: AVX512-E4 45016 REAL_OPCODE: Y 45017 ATTRIBUTES: MASKOP_EVEX 45018 PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 45019 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 45020 IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 45021 } 45022 45023 { 45024 ICLASS: VPMULHUW 45025 CPL: 3 45026 CATEGORY: AVX512 45027 EXTENSION: AVX512EVEX 45028 ISA_SET: AVX512BW_128 45029 EXCEPTIONS: AVX512-E4 45030 REAL_OPCODE: Y 45031 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 45032 PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 45033 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 45034 IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 45035 } 45036 45037 45038 # EMITTING VPMULHUW (VPMULHUW-256-1) 45039 { 45040 ICLASS: VPMULHUW 45041 CPL: 3 45042 CATEGORY: AVX512 45043 EXTENSION: AVX512EVEX 45044 ISA_SET: AVX512BW_256 45045 EXCEPTIONS: AVX512-E4 45046 REAL_OPCODE: Y 45047 ATTRIBUTES: MASKOP_EVEX 45048 PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 45049 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 45050 IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 45051 } 45052 45053 { 45054 ICLASS: VPMULHUW 45055 CPL: 3 45056 CATEGORY: AVX512 45057 EXTENSION: AVX512EVEX 45058 ISA_SET: AVX512BW_256 45059 EXCEPTIONS: AVX512-E4 45060 REAL_OPCODE: Y 45061 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 45062 PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 45063 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 45064 IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 45065 } 45066 45067 45068 # EMITTING VPMULHUW (VPMULHUW-512-1) 45069 { 45070 ICLASS: VPMULHUW 45071 CPL: 3 45072 CATEGORY: AVX512 45073 EXTENSION: AVX512EVEX 45074 ISA_SET: AVX512BW_512 45075 EXCEPTIONS: AVX512-E4 45076 REAL_OPCODE: Y 45077 ATTRIBUTES: MASKOP_EVEX 45078 PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 45079 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 45080 IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 45081 } 45082 45083 { 45084 ICLASS: VPMULHUW 45085 CPL: 3 45086 CATEGORY: AVX512 45087 EXTENSION: AVX512EVEX 45088 ISA_SET: AVX512BW_512 45089 EXCEPTIONS: AVX512-E4 45090 REAL_OPCODE: Y 45091 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 45092 PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 45093 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 45094 IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 45095 } 45096 45097 45098 # EMITTING VPMULHW (VPMULHW-128-1) 45099 { 45100 ICLASS: VPMULHW 45101 CPL: 3 45102 CATEGORY: AVX512 45103 EXTENSION: AVX512EVEX 45104 ISA_SET: AVX512BW_128 45105 EXCEPTIONS: AVX512-E4 45106 REAL_OPCODE: Y 45107 ATTRIBUTES: MASKOP_EVEX 45108 PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 45109 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 45110 IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 45111 } 45112 45113 { 45114 ICLASS: VPMULHW 45115 CPL: 3 45116 CATEGORY: AVX512 45117 EXTENSION: AVX512EVEX 45118 ISA_SET: AVX512BW_128 45119 EXCEPTIONS: AVX512-E4 45120 REAL_OPCODE: Y 45121 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 45122 PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 45123 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 45124 IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 45125 } 45126 45127 45128 # EMITTING VPMULHW (VPMULHW-256-1) 45129 { 45130 ICLASS: VPMULHW 45131 CPL: 3 45132 CATEGORY: AVX512 45133 EXTENSION: AVX512EVEX 45134 ISA_SET: AVX512BW_256 45135 EXCEPTIONS: AVX512-E4 45136 REAL_OPCODE: Y 45137 ATTRIBUTES: MASKOP_EVEX 45138 PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 45139 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 45140 IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 45141 } 45142 45143 { 45144 ICLASS: VPMULHW 45145 CPL: 3 45146 CATEGORY: AVX512 45147 EXTENSION: AVX512EVEX 45148 ISA_SET: AVX512BW_256 45149 EXCEPTIONS: AVX512-E4 45150 REAL_OPCODE: Y 45151 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 45152 PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 45153 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 45154 IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 45155 } 45156 45157 45158 # EMITTING VPMULHW (VPMULHW-512-1) 45159 { 45160 ICLASS: VPMULHW 45161 CPL: 3 45162 CATEGORY: AVX512 45163 EXTENSION: AVX512EVEX 45164 ISA_SET: AVX512BW_512 45165 EXCEPTIONS: AVX512-E4 45166 REAL_OPCODE: Y 45167 ATTRIBUTES: MASKOP_EVEX 45168 PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 45169 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 45170 IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 45171 } 45172 45173 { 45174 ICLASS: VPMULHW 45175 CPL: 3 45176 CATEGORY: AVX512 45177 EXTENSION: AVX512EVEX 45178 ISA_SET: AVX512BW_512 45179 EXCEPTIONS: AVX512-E4 45180 REAL_OPCODE: Y 45181 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 45182 PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 45183 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 45184 IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 45185 } 45186 45187 45188 # EMITTING VPMULLD (VPMULLD-128-1) 45189 { 45190 ICLASS: VPMULLD 45191 CPL: 3 45192 CATEGORY: AVX512 45193 EXTENSION: AVX512EVEX 45194 ISA_SET: AVX512F_128 45195 EXCEPTIONS: AVX512-E4 45196 REAL_OPCODE: Y 45197 ATTRIBUTES: MASKOP_EVEX 45198 PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 45199 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 45200 IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 45201 } 45202 45203 { 45204 ICLASS: VPMULLD 45205 CPL: 3 45206 CATEGORY: AVX512 45207 EXTENSION: AVX512EVEX 45208 ISA_SET: AVX512F_128 45209 EXCEPTIONS: AVX512-E4 45210 REAL_OPCODE: Y 45211 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45212 PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 45213 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 45214 IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 45215 } 45216 45217 45218 # EMITTING VPMULLD (VPMULLD-256-1) 45219 { 45220 ICLASS: VPMULLD 45221 CPL: 3 45222 CATEGORY: AVX512 45223 EXTENSION: AVX512EVEX 45224 ISA_SET: AVX512F_256 45225 EXCEPTIONS: AVX512-E4 45226 REAL_OPCODE: Y 45227 ATTRIBUTES: MASKOP_EVEX 45228 PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 45229 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 45230 IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 45231 } 45232 45233 { 45234 ICLASS: VPMULLD 45235 CPL: 3 45236 CATEGORY: AVX512 45237 EXTENSION: AVX512EVEX 45238 ISA_SET: AVX512F_256 45239 EXCEPTIONS: AVX512-E4 45240 REAL_OPCODE: Y 45241 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45242 PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 45243 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 45244 IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 45245 } 45246 45247 45248 # EMITTING VPMULLQ (VPMULLQ-128-1) 45249 { 45250 ICLASS: VPMULLQ 45251 CPL: 3 45252 CATEGORY: AVX512 45253 EXTENSION: AVX512EVEX 45254 ISA_SET: AVX512DQ_128 45255 EXCEPTIONS: AVX512-E4 45256 REAL_OPCODE: Y 45257 ATTRIBUTES: MASKOP_EVEX 45258 PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 45259 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 45260 IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 45261 } 45262 45263 { 45264 ICLASS: VPMULLQ 45265 CPL: 3 45266 CATEGORY: AVX512 45267 EXTENSION: AVX512EVEX 45268 ISA_SET: AVX512DQ_128 45269 EXCEPTIONS: AVX512-E4 45270 REAL_OPCODE: Y 45271 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45272 PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 45273 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 45274 IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 45275 } 45276 45277 45278 # EMITTING VPMULLQ (VPMULLQ-256-1) 45279 { 45280 ICLASS: VPMULLQ 45281 CPL: 3 45282 CATEGORY: AVX512 45283 EXTENSION: AVX512EVEX 45284 ISA_SET: AVX512DQ_256 45285 EXCEPTIONS: AVX512-E4 45286 REAL_OPCODE: Y 45287 ATTRIBUTES: MASKOP_EVEX 45288 PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 45289 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 45290 IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 45291 } 45292 45293 { 45294 ICLASS: VPMULLQ 45295 CPL: 3 45296 CATEGORY: AVX512 45297 EXTENSION: AVX512EVEX 45298 ISA_SET: AVX512DQ_256 45299 EXCEPTIONS: AVX512-E4 45300 REAL_OPCODE: Y 45301 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45302 PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 45303 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 45304 IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 45305 } 45306 45307 45308 # EMITTING VPMULLQ (VPMULLQ-512-1) 45309 { 45310 ICLASS: VPMULLQ 45311 CPL: 3 45312 CATEGORY: AVX512 45313 EXTENSION: AVX512EVEX 45314 ISA_SET: AVX512DQ_512 45315 EXCEPTIONS: AVX512-E4 45316 REAL_OPCODE: Y 45317 ATTRIBUTES: MASKOP_EVEX 45318 PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 45319 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 45320 IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 45321 } 45322 45323 { 45324 ICLASS: VPMULLQ 45325 CPL: 3 45326 CATEGORY: AVX512 45327 EXTENSION: AVX512EVEX 45328 ISA_SET: AVX512DQ_512 45329 EXCEPTIONS: AVX512-E4 45330 REAL_OPCODE: Y 45331 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45332 PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 45333 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 45334 IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 45335 } 45336 45337 45338 # EMITTING VPMULLW (VPMULLW-128-1) 45339 { 45340 ICLASS: VPMULLW 45341 CPL: 3 45342 CATEGORY: AVX512 45343 EXTENSION: AVX512EVEX 45344 ISA_SET: AVX512BW_128 45345 EXCEPTIONS: AVX512-E4 45346 REAL_OPCODE: Y 45347 ATTRIBUTES: MASKOP_EVEX 45348 PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 45349 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 45350 IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 45351 } 45352 45353 { 45354 ICLASS: VPMULLW 45355 CPL: 3 45356 CATEGORY: AVX512 45357 EXTENSION: AVX512EVEX 45358 ISA_SET: AVX512BW_128 45359 EXCEPTIONS: AVX512-E4 45360 REAL_OPCODE: Y 45361 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 45362 PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 45363 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 45364 IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 45365 } 45366 45367 45368 # EMITTING VPMULLW (VPMULLW-256-1) 45369 { 45370 ICLASS: VPMULLW 45371 CPL: 3 45372 CATEGORY: AVX512 45373 EXTENSION: AVX512EVEX 45374 ISA_SET: AVX512BW_256 45375 EXCEPTIONS: AVX512-E4 45376 REAL_OPCODE: Y 45377 ATTRIBUTES: MASKOP_EVEX 45378 PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 45379 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 45380 IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 45381 } 45382 45383 { 45384 ICLASS: VPMULLW 45385 CPL: 3 45386 CATEGORY: AVX512 45387 EXTENSION: AVX512EVEX 45388 ISA_SET: AVX512BW_256 45389 EXCEPTIONS: AVX512-E4 45390 REAL_OPCODE: Y 45391 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 45392 PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 45393 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 45394 IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 45395 } 45396 45397 45398 # EMITTING VPMULLW (VPMULLW-512-1) 45399 { 45400 ICLASS: VPMULLW 45401 CPL: 3 45402 CATEGORY: AVX512 45403 EXTENSION: AVX512EVEX 45404 ISA_SET: AVX512BW_512 45405 EXCEPTIONS: AVX512-E4 45406 REAL_OPCODE: Y 45407 ATTRIBUTES: MASKOP_EVEX 45408 PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 45409 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 45410 IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 45411 } 45412 45413 { 45414 ICLASS: VPMULLW 45415 CPL: 3 45416 CATEGORY: AVX512 45417 EXTENSION: AVX512EVEX 45418 ISA_SET: AVX512BW_512 45419 EXCEPTIONS: AVX512-E4 45420 REAL_OPCODE: Y 45421 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 45422 PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 45423 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 45424 IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 45425 } 45426 45427 45428 # EMITTING VPMULUDQ (VPMULUDQ-128-1) 45429 { 45430 ICLASS: VPMULUDQ 45431 CPL: 3 45432 CATEGORY: AVX512 45433 EXTENSION: AVX512EVEX 45434 ISA_SET: AVX512F_128 45435 EXCEPTIONS: AVX512-E4 45436 REAL_OPCODE: Y 45437 COMMENT: Strange instruction that uses 32b of each 64b input element 45438 ATTRIBUTES: MASKOP_EVEX 45439 PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 45440 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 45441 IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 45442 } 45443 45444 { 45445 ICLASS: VPMULUDQ 45446 CPL: 3 45447 CATEGORY: AVX512 45448 EXTENSION: AVX512EVEX 45449 ISA_SET: AVX512F_128 45450 EXCEPTIONS: AVX512-E4 45451 REAL_OPCODE: Y 45452 COMMENT: Strange instruction that uses 32b of each 64b input element 45453 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX 45454 PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 45455 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 45456 IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 45457 } 45458 45459 45460 # EMITTING VPMULUDQ (VPMULUDQ-256-1) 45461 { 45462 ICLASS: VPMULUDQ 45463 CPL: 3 45464 CATEGORY: AVX512 45465 EXTENSION: AVX512EVEX 45466 ISA_SET: AVX512F_256 45467 EXCEPTIONS: AVX512-E4 45468 REAL_OPCODE: Y 45469 COMMENT: Strange instruction that uses 32b of each 64b input element 45470 ATTRIBUTES: MASKOP_EVEX 45471 PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 45472 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 45473 IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 45474 } 45475 45476 { 45477 ICLASS: VPMULUDQ 45478 CPL: 3 45479 CATEGORY: AVX512 45480 EXTENSION: AVX512EVEX 45481 ISA_SET: AVX512F_256 45482 EXCEPTIONS: AVX512-E4 45483 REAL_OPCODE: Y 45484 COMMENT: Strange instruction that uses 32b of each 64b input element 45485 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX 45486 PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 45487 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 45488 IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 45489 } 45490 45491 45492 # EMITTING VPORD (VPORD-128-1) 45493 { 45494 ICLASS: VPORD 45495 CPL: 3 45496 CATEGORY: LOGICAL 45497 EXTENSION: AVX512EVEX 45498 ISA_SET: AVX512F_128 45499 EXCEPTIONS: AVX512-E4 45500 REAL_OPCODE: Y 45501 ATTRIBUTES: MASKOP_EVEX 45502 PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 45503 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 45504 IFORM: VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 45505 } 45506 45507 { 45508 ICLASS: VPORD 45509 CPL: 3 45510 CATEGORY: LOGICAL 45511 EXTENSION: AVX512EVEX 45512 ISA_SET: AVX512F_128 45513 EXCEPTIONS: AVX512-E4 45514 REAL_OPCODE: Y 45515 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45516 PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 45517 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 45518 IFORM: VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 45519 } 45520 45521 45522 # EMITTING VPORD (VPORD-256-1) 45523 { 45524 ICLASS: VPORD 45525 CPL: 3 45526 CATEGORY: LOGICAL 45527 EXTENSION: AVX512EVEX 45528 ISA_SET: AVX512F_256 45529 EXCEPTIONS: AVX512-E4 45530 REAL_OPCODE: Y 45531 ATTRIBUTES: MASKOP_EVEX 45532 PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 45533 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 45534 IFORM: VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 45535 } 45536 45537 { 45538 ICLASS: VPORD 45539 CPL: 3 45540 CATEGORY: LOGICAL 45541 EXTENSION: AVX512EVEX 45542 ISA_SET: AVX512F_256 45543 EXCEPTIONS: AVX512-E4 45544 REAL_OPCODE: Y 45545 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45546 PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 45547 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 45548 IFORM: VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 45549 } 45550 45551 45552 # EMITTING VPORQ (VPORQ-128-1) 45553 { 45554 ICLASS: VPORQ 45555 CPL: 3 45556 CATEGORY: LOGICAL 45557 EXTENSION: AVX512EVEX 45558 ISA_SET: AVX512F_128 45559 EXCEPTIONS: AVX512-E4 45560 REAL_OPCODE: Y 45561 ATTRIBUTES: MASKOP_EVEX 45562 PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 45563 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 45564 IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 45565 } 45566 45567 { 45568 ICLASS: VPORQ 45569 CPL: 3 45570 CATEGORY: LOGICAL 45571 EXTENSION: AVX512EVEX 45572 ISA_SET: AVX512F_128 45573 EXCEPTIONS: AVX512-E4 45574 REAL_OPCODE: Y 45575 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45576 PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 45577 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 45578 IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 45579 } 45580 45581 45582 # EMITTING VPORQ (VPORQ-256-1) 45583 { 45584 ICLASS: VPORQ 45585 CPL: 3 45586 CATEGORY: LOGICAL 45587 EXTENSION: AVX512EVEX 45588 ISA_SET: AVX512F_256 45589 EXCEPTIONS: AVX512-E4 45590 REAL_OPCODE: Y 45591 ATTRIBUTES: MASKOP_EVEX 45592 PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 45593 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 45594 IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 45595 } 45596 45597 { 45598 ICLASS: VPORQ 45599 CPL: 3 45600 CATEGORY: LOGICAL 45601 EXTENSION: AVX512EVEX 45602 ISA_SET: AVX512F_256 45603 EXCEPTIONS: AVX512-E4 45604 REAL_OPCODE: Y 45605 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45606 PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 45607 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 45608 IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 45609 } 45610 45611 45612 # EMITTING VPROLD (VPROLD-128-1) 45613 { 45614 ICLASS: VPROLD 45615 CPL: 3 45616 CATEGORY: AVX512 45617 EXTENSION: AVX512EVEX 45618 ISA_SET: AVX512F_128 45619 EXCEPTIONS: AVX512-E4 45620 REAL_OPCODE: Y 45621 ATTRIBUTES: MASKOP_EVEX 45622 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W0 UIMM8() 45623 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b 45624 IFORM: VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 45625 } 45626 45627 { 45628 ICLASS: VPROLD 45629 CPL: 3 45630 CATEGORY: AVX512 45631 EXTENSION: AVX512EVEX 45632 ISA_SET: AVX512F_128 45633 EXCEPTIONS: AVX512-E4 45634 REAL_OPCODE: Y 45635 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45636 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 45637 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 45638 IFORM: VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 45639 } 45640 45641 45642 # EMITTING VPROLD (VPROLD-256-1) 45643 { 45644 ICLASS: VPROLD 45645 CPL: 3 45646 CATEGORY: AVX512 45647 EXTENSION: AVX512EVEX 45648 ISA_SET: AVX512F_256 45649 EXCEPTIONS: AVX512-E4 45650 REAL_OPCODE: Y 45651 ATTRIBUTES: MASKOP_EVEX 45652 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W0 UIMM8() 45653 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b 45654 IFORM: VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 45655 } 45656 45657 { 45658 ICLASS: VPROLD 45659 CPL: 3 45660 CATEGORY: AVX512 45661 EXTENSION: AVX512EVEX 45662 ISA_SET: AVX512F_256 45663 EXCEPTIONS: AVX512-E4 45664 REAL_OPCODE: Y 45665 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45666 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 45667 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 45668 IFORM: VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 45669 } 45670 45671 45672 # EMITTING VPROLQ (VPROLQ-128-1) 45673 { 45674 ICLASS: VPROLQ 45675 CPL: 3 45676 CATEGORY: AVX512 45677 EXTENSION: AVX512EVEX 45678 ISA_SET: AVX512F_128 45679 EXCEPTIONS: AVX512-E4 45680 REAL_OPCODE: Y 45681 ATTRIBUTES: MASKOP_EVEX 45682 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W1 UIMM8() 45683 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b 45684 IFORM: VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 45685 } 45686 45687 { 45688 ICLASS: VPROLQ 45689 CPL: 3 45690 CATEGORY: AVX512 45691 EXTENSION: AVX512EVEX 45692 ISA_SET: AVX512F_128 45693 EXCEPTIONS: AVX512-E4 45694 REAL_OPCODE: Y 45695 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45696 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 45697 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 45698 IFORM: VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 45699 } 45700 45701 45702 # EMITTING VPROLQ (VPROLQ-256-1) 45703 { 45704 ICLASS: VPROLQ 45705 CPL: 3 45706 CATEGORY: AVX512 45707 EXTENSION: AVX512EVEX 45708 ISA_SET: AVX512F_256 45709 EXCEPTIONS: AVX512-E4 45710 REAL_OPCODE: Y 45711 ATTRIBUTES: MASKOP_EVEX 45712 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W1 UIMM8() 45713 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b 45714 IFORM: VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 45715 } 45716 45717 { 45718 ICLASS: VPROLQ 45719 CPL: 3 45720 CATEGORY: AVX512 45721 EXTENSION: AVX512EVEX 45722 ISA_SET: AVX512F_256 45723 EXCEPTIONS: AVX512-E4 45724 REAL_OPCODE: Y 45725 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45726 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 45727 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 45728 IFORM: VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 45729 } 45730 45731 45732 # EMITTING VPROLVD (VPROLVD-128-1) 45733 { 45734 ICLASS: VPROLVD 45735 CPL: 3 45736 CATEGORY: AVX512 45737 EXTENSION: AVX512EVEX 45738 ISA_SET: AVX512F_128 45739 EXCEPTIONS: AVX512-E4 45740 REAL_OPCODE: Y 45741 ATTRIBUTES: MASKOP_EVEX 45742 PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 45743 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 45744 IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 45745 } 45746 45747 { 45748 ICLASS: VPROLVD 45749 CPL: 3 45750 CATEGORY: AVX512 45751 EXTENSION: AVX512EVEX 45752 ISA_SET: AVX512F_128 45753 EXCEPTIONS: AVX512-E4 45754 REAL_OPCODE: Y 45755 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45756 PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 45757 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 45758 IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 45759 } 45760 45761 45762 # EMITTING VPROLVD (VPROLVD-256-1) 45763 { 45764 ICLASS: VPROLVD 45765 CPL: 3 45766 CATEGORY: AVX512 45767 EXTENSION: AVX512EVEX 45768 ISA_SET: AVX512F_256 45769 EXCEPTIONS: AVX512-E4 45770 REAL_OPCODE: Y 45771 ATTRIBUTES: MASKOP_EVEX 45772 PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 45773 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 45774 IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 45775 } 45776 45777 { 45778 ICLASS: VPROLVD 45779 CPL: 3 45780 CATEGORY: AVX512 45781 EXTENSION: AVX512EVEX 45782 ISA_SET: AVX512F_256 45783 EXCEPTIONS: AVX512-E4 45784 REAL_OPCODE: Y 45785 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45786 PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 45787 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 45788 IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 45789 } 45790 45791 45792 # EMITTING VPROLVQ (VPROLVQ-128-1) 45793 { 45794 ICLASS: VPROLVQ 45795 CPL: 3 45796 CATEGORY: AVX512 45797 EXTENSION: AVX512EVEX 45798 ISA_SET: AVX512F_128 45799 EXCEPTIONS: AVX512-E4 45800 REAL_OPCODE: Y 45801 ATTRIBUTES: MASKOP_EVEX 45802 PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 45803 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 45804 IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 45805 } 45806 45807 { 45808 ICLASS: VPROLVQ 45809 CPL: 3 45810 CATEGORY: AVX512 45811 EXTENSION: AVX512EVEX 45812 ISA_SET: AVX512F_128 45813 EXCEPTIONS: AVX512-E4 45814 REAL_OPCODE: Y 45815 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45816 PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 45817 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 45818 IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 45819 } 45820 45821 45822 # EMITTING VPROLVQ (VPROLVQ-256-1) 45823 { 45824 ICLASS: VPROLVQ 45825 CPL: 3 45826 CATEGORY: AVX512 45827 EXTENSION: AVX512EVEX 45828 ISA_SET: AVX512F_256 45829 EXCEPTIONS: AVX512-E4 45830 REAL_OPCODE: Y 45831 ATTRIBUTES: MASKOP_EVEX 45832 PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 45833 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 45834 IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 45835 } 45836 45837 { 45838 ICLASS: VPROLVQ 45839 CPL: 3 45840 CATEGORY: AVX512 45841 EXTENSION: AVX512EVEX 45842 ISA_SET: AVX512F_256 45843 EXCEPTIONS: AVX512-E4 45844 REAL_OPCODE: Y 45845 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45846 PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 45847 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 45848 IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 45849 } 45850 45851 45852 # EMITTING VPRORD (VPRORD-128-1) 45853 { 45854 ICLASS: VPRORD 45855 CPL: 3 45856 CATEGORY: AVX512 45857 EXTENSION: AVX512EVEX 45858 ISA_SET: AVX512F_128 45859 EXCEPTIONS: AVX512-E4 45860 REAL_OPCODE: Y 45861 ATTRIBUTES: MASKOP_EVEX 45862 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W0 UIMM8() 45863 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b 45864 IFORM: VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 45865 } 45866 45867 { 45868 ICLASS: VPRORD 45869 CPL: 3 45870 CATEGORY: AVX512 45871 EXTENSION: AVX512EVEX 45872 ISA_SET: AVX512F_128 45873 EXCEPTIONS: AVX512-E4 45874 REAL_OPCODE: Y 45875 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45876 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 45877 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 45878 IFORM: VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 45879 } 45880 45881 45882 # EMITTING VPRORD (VPRORD-256-1) 45883 { 45884 ICLASS: VPRORD 45885 CPL: 3 45886 CATEGORY: AVX512 45887 EXTENSION: AVX512EVEX 45888 ISA_SET: AVX512F_256 45889 EXCEPTIONS: AVX512-E4 45890 REAL_OPCODE: Y 45891 ATTRIBUTES: MASKOP_EVEX 45892 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W0 UIMM8() 45893 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b 45894 IFORM: VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 45895 } 45896 45897 { 45898 ICLASS: VPRORD 45899 CPL: 3 45900 CATEGORY: AVX512 45901 EXTENSION: AVX512EVEX 45902 ISA_SET: AVX512F_256 45903 EXCEPTIONS: AVX512-E4 45904 REAL_OPCODE: Y 45905 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45906 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 45907 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 45908 IFORM: VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 45909 } 45910 45911 45912 # EMITTING VPRORQ (VPRORQ-128-1) 45913 { 45914 ICLASS: VPRORQ 45915 CPL: 3 45916 CATEGORY: AVX512 45917 EXTENSION: AVX512EVEX 45918 ISA_SET: AVX512F_128 45919 EXCEPTIONS: AVX512-E4 45920 REAL_OPCODE: Y 45921 ATTRIBUTES: MASKOP_EVEX 45922 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W1 UIMM8() 45923 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b 45924 IFORM: VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 45925 } 45926 45927 { 45928 ICLASS: VPRORQ 45929 CPL: 3 45930 CATEGORY: AVX512 45931 EXTENSION: AVX512EVEX 45932 ISA_SET: AVX512F_128 45933 EXCEPTIONS: AVX512-E4 45934 REAL_OPCODE: Y 45935 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45936 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 45937 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 45938 IFORM: VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 45939 } 45940 45941 45942 # EMITTING VPRORQ (VPRORQ-256-1) 45943 { 45944 ICLASS: VPRORQ 45945 CPL: 3 45946 CATEGORY: AVX512 45947 EXTENSION: AVX512EVEX 45948 ISA_SET: AVX512F_256 45949 EXCEPTIONS: AVX512-E4 45950 REAL_OPCODE: Y 45951 ATTRIBUTES: MASKOP_EVEX 45952 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W1 UIMM8() 45953 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b 45954 IFORM: VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 45955 } 45956 45957 { 45958 ICLASS: VPRORQ 45959 CPL: 3 45960 CATEGORY: AVX512 45961 EXTENSION: AVX512EVEX 45962 ISA_SET: AVX512F_256 45963 EXCEPTIONS: AVX512-E4 45964 REAL_OPCODE: Y 45965 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45966 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 45967 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 45968 IFORM: VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 45969 } 45970 45971 45972 # EMITTING VPRORVD (VPRORVD-128-1) 45973 { 45974 ICLASS: VPRORVD 45975 CPL: 3 45976 CATEGORY: AVX512 45977 EXTENSION: AVX512EVEX 45978 ISA_SET: AVX512F_128 45979 EXCEPTIONS: AVX512-E4 45980 REAL_OPCODE: Y 45981 ATTRIBUTES: MASKOP_EVEX 45982 PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 45983 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 45984 IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 45985 } 45986 45987 { 45988 ICLASS: VPRORVD 45989 CPL: 3 45990 CATEGORY: AVX512 45991 EXTENSION: AVX512EVEX 45992 ISA_SET: AVX512F_128 45993 EXCEPTIONS: AVX512-E4 45994 REAL_OPCODE: Y 45995 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 45996 PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 45997 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 45998 IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 45999 } 46000 46001 46002 # EMITTING VPRORVD (VPRORVD-256-1) 46003 { 46004 ICLASS: VPRORVD 46005 CPL: 3 46006 CATEGORY: AVX512 46007 EXTENSION: AVX512EVEX 46008 ISA_SET: AVX512F_256 46009 EXCEPTIONS: AVX512-E4 46010 REAL_OPCODE: Y 46011 ATTRIBUTES: MASKOP_EVEX 46012 PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 46013 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 46014 IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 46015 } 46016 46017 { 46018 ICLASS: VPRORVD 46019 CPL: 3 46020 CATEGORY: AVX512 46021 EXTENSION: AVX512EVEX 46022 ISA_SET: AVX512F_256 46023 EXCEPTIONS: AVX512-E4 46024 REAL_OPCODE: Y 46025 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46026 PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 46027 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 46028 IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 46029 } 46030 46031 46032 # EMITTING VPRORVQ (VPRORVQ-128-1) 46033 { 46034 ICLASS: VPRORVQ 46035 CPL: 3 46036 CATEGORY: AVX512 46037 EXTENSION: AVX512EVEX 46038 ISA_SET: AVX512F_128 46039 EXCEPTIONS: AVX512-E4 46040 REAL_OPCODE: Y 46041 ATTRIBUTES: MASKOP_EVEX 46042 PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 46043 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 46044 IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 46045 } 46046 46047 { 46048 ICLASS: VPRORVQ 46049 CPL: 3 46050 CATEGORY: AVX512 46051 EXTENSION: AVX512EVEX 46052 ISA_SET: AVX512F_128 46053 EXCEPTIONS: AVX512-E4 46054 REAL_OPCODE: Y 46055 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46056 PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 46057 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 46058 IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 46059 } 46060 46061 46062 # EMITTING VPRORVQ (VPRORVQ-256-1) 46063 { 46064 ICLASS: VPRORVQ 46065 CPL: 3 46066 CATEGORY: AVX512 46067 EXTENSION: AVX512EVEX 46068 ISA_SET: AVX512F_256 46069 EXCEPTIONS: AVX512-E4 46070 REAL_OPCODE: Y 46071 ATTRIBUTES: MASKOP_EVEX 46072 PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 46073 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 46074 IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 46075 } 46076 46077 { 46078 ICLASS: VPRORVQ 46079 CPL: 3 46080 CATEGORY: AVX512 46081 EXTENSION: AVX512EVEX 46082 ISA_SET: AVX512F_256 46083 EXCEPTIONS: AVX512-E4 46084 REAL_OPCODE: Y 46085 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46086 PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 46087 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 46088 IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 46089 } 46090 46091 46092 # EMITTING VPSADBW (VPSADBW-128-1) 46093 { 46094 ICLASS: VPSADBW 46095 CPL: 3 46096 CATEGORY: AVX512 46097 EXTENSION: AVX512EVEX 46098 ISA_SET: AVX512BW_128 46099 EXCEPTIONS: AVX512-E4NF 46100 REAL_OPCODE: Y 46101 PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 46102 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 REG2=XMM_B3():r:dq:u8 46103 IFORM: VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 46104 } 46105 46106 { 46107 ICLASS: VPSADBW 46108 CPL: 3 46109 CATEGORY: AVX512 46110 EXTENSION: AVX512EVEX 46111 ISA_SET: AVX512BW_128 46112 EXCEPTIONS: AVX512-E4NF 46113 REAL_OPCODE: Y 46114 ATTRIBUTES: DISP8_FULLMEM 46115 PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() 46116 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 MEM0:r:dq:u8 46117 IFORM: VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 46118 } 46119 46120 46121 # EMITTING VPSADBW (VPSADBW-256-1) 46122 { 46123 ICLASS: VPSADBW 46124 CPL: 3 46125 CATEGORY: AVX512 46126 EXTENSION: AVX512EVEX 46127 ISA_SET: AVX512BW_256 46128 EXCEPTIONS: AVX512-E4NF 46129 REAL_OPCODE: Y 46130 PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 46131 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 REG2=YMM_B3():r:qq:u8 46132 IFORM: VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 46133 } 46134 46135 { 46136 ICLASS: VPSADBW 46137 CPL: 3 46138 CATEGORY: AVX512 46139 EXTENSION: AVX512EVEX 46140 ISA_SET: AVX512BW_256 46141 EXCEPTIONS: AVX512-E4NF 46142 REAL_OPCODE: Y 46143 ATTRIBUTES: DISP8_FULLMEM 46144 PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() 46145 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 MEM0:r:qq:u8 46146 IFORM: VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 46147 } 46148 46149 46150 # EMITTING VPSADBW (VPSADBW-512-1) 46151 { 46152 ICLASS: VPSADBW 46153 CPL: 3 46154 CATEGORY: AVX512 46155 EXTENSION: AVX512EVEX 46156 ISA_SET: AVX512BW_512 46157 EXCEPTIONS: AVX512-E4NF 46158 REAL_OPCODE: Y 46159 PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 46160 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 REG2=ZMM_B3():r:zu8 46161 IFORM: VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 46162 } 46163 46164 { 46165 ICLASS: VPSADBW 46166 CPL: 3 46167 CATEGORY: AVX512 46168 EXTENSION: AVX512EVEX 46169 ISA_SET: AVX512BW_512 46170 EXCEPTIONS: AVX512-E4NF 46171 REAL_OPCODE: Y 46172 ATTRIBUTES: DISP8_FULLMEM 46173 PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() 46174 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 MEM0:r:zd:u8 46175 IFORM: VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 46176 } 46177 46178 46179 # EMITTING VPSCATTERDD (VPSCATTERDD-128-1) 46180 { 46181 ICLASS: VPSCATTERDD 46182 CPL: 3 46183 CATEGORY: SCATTER 46184 EXTENSION: AVX512EVEX 46185 ISA_SET: AVX512F_128 46186 EXCEPTIONS: AVX512-E12 46187 REAL_OPCODE: Y 46188 ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 46189 PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 46190 OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 46191 IFORM: VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 46192 } 46193 46194 46195 # EMITTING VPSCATTERDD (VPSCATTERDD-256-1) 46196 { 46197 ICLASS: VPSCATTERDD 46198 CPL: 3 46199 CATEGORY: SCATTER 46200 EXTENSION: AVX512EVEX 46201 ISA_SET: AVX512F_256 46202 EXCEPTIONS: AVX512-E12 46203 REAL_OPCODE: Y 46204 ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 46205 PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 46206 OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 46207 IFORM: VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 46208 } 46209 46210 46211 # EMITTING VPSCATTERDQ (VPSCATTERDQ-128-1) 46212 { 46213 ICLASS: VPSCATTERDQ 46214 CPL: 3 46215 CATEGORY: SCATTER 46216 EXTENSION: AVX512EVEX 46217 ISA_SET: AVX512F_128 46218 EXCEPTIONS: AVX512-E12 46219 REAL_OPCODE: Y 46220 ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 46221 PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 46222 OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 46223 IFORM: VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 46224 } 46225 46226 46227 # EMITTING VPSCATTERDQ (VPSCATTERDQ-256-1) 46228 { 46229 ICLASS: VPSCATTERDQ 46230 CPL: 3 46231 CATEGORY: SCATTER 46232 EXTENSION: AVX512EVEX 46233 ISA_SET: AVX512F_256 46234 EXCEPTIONS: AVX512-E12 46235 REAL_OPCODE: Y 46236 ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 46237 PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 46238 OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 46239 IFORM: VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 46240 } 46241 46242 46243 # EMITTING VPSCATTERQD (VPSCATTERQD-128-1) 46244 { 46245 ICLASS: VPSCATTERQD 46246 CPL: 3 46247 CATEGORY: SCATTER 46248 EXTENSION: AVX512EVEX 46249 ISA_SET: AVX512F_128 46250 EXCEPTIONS: AVX512-E12 46251 REAL_OPCODE: Y 46252 ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 46253 PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 46254 OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 46255 IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 46256 } 46257 46258 46259 # EMITTING VPSCATTERQD (VPSCATTERQD-256-1) 46260 { 46261 ICLASS: VPSCATTERQD 46262 CPL: 3 46263 CATEGORY: SCATTER 46264 EXTENSION: AVX512EVEX 46265 ISA_SET: AVX512F_256 46266 EXCEPTIONS: AVX512-E12 46267 REAL_OPCODE: Y 46268 ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 46269 PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 46270 OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 46271 IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 46272 } 46273 46274 46275 # EMITTING VPSCATTERQQ (VPSCATTERQQ-128-1) 46276 { 46277 ICLASS: VPSCATTERQQ 46278 CPL: 3 46279 CATEGORY: SCATTER 46280 EXTENSION: AVX512EVEX 46281 ISA_SET: AVX512F_128 46282 EXCEPTIONS: AVX512-E12 46283 REAL_OPCODE: Y 46284 ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 46285 PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 46286 OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 46287 IFORM: VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 46288 } 46289 46290 46291 # EMITTING VPSCATTERQQ (VPSCATTERQQ-256-1) 46292 { 46293 ICLASS: VPSCATTERQQ 46294 CPL: 3 46295 CATEGORY: SCATTER 46296 EXTENSION: AVX512EVEX 46297 ISA_SET: AVX512F_256 46298 EXCEPTIONS: AVX512-E12 46299 REAL_OPCODE: Y 46300 ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 46301 PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 46302 OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 46303 IFORM: VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 46304 } 46305 46306 46307 # EMITTING VPSHUFB (VPSHUFB-128-1) 46308 { 46309 ICLASS: VPSHUFB 46310 CPL: 3 46311 CATEGORY: AVX512 46312 EXTENSION: AVX512EVEX 46313 ISA_SET: AVX512BW_128 46314 EXCEPTIONS: AVX512-E4NF 46315 REAL_OPCODE: Y 46316 ATTRIBUTES: MASKOP_EVEX 46317 PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 46318 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 46319 IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 46320 } 46321 46322 { 46323 ICLASS: VPSHUFB 46324 CPL: 3 46325 CATEGORY: AVX512 46326 EXTENSION: AVX512EVEX 46327 ISA_SET: AVX512BW_128 46328 EXCEPTIONS: AVX512-E4NF 46329 REAL_OPCODE: Y 46330 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 46331 PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 46332 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 46333 IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 46334 } 46335 46336 46337 # EMITTING VPSHUFB (VPSHUFB-256-1) 46338 { 46339 ICLASS: VPSHUFB 46340 CPL: 3 46341 CATEGORY: AVX512 46342 EXTENSION: AVX512EVEX 46343 ISA_SET: AVX512BW_256 46344 EXCEPTIONS: AVX512-E4NF 46345 REAL_OPCODE: Y 46346 ATTRIBUTES: MASKOP_EVEX 46347 PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 46348 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 46349 IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 46350 } 46351 46352 { 46353 ICLASS: VPSHUFB 46354 CPL: 3 46355 CATEGORY: AVX512 46356 EXTENSION: AVX512EVEX 46357 ISA_SET: AVX512BW_256 46358 EXCEPTIONS: AVX512-E4NF 46359 REAL_OPCODE: Y 46360 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 46361 PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 46362 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 46363 IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 46364 } 46365 46366 46367 # EMITTING VPSHUFB (VPSHUFB-512-1) 46368 { 46369 ICLASS: VPSHUFB 46370 CPL: 3 46371 CATEGORY: AVX512 46372 EXTENSION: AVX512EVEX 46373 ISA_SET: AVX512BW_512 46374 EXCEPTIONS: AVX512-E4NF 46375 REAL_OPCODE: Y 46376 ATTRIBUTES: MASKOP_EVEX 46377 PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 46378 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 46379 IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 46380 } 46381 46382 { 46383 ICLASS: VPSHUFB 46384 CPL: 3 46385 CATEGORY: AVX512 46386 EXTENSION: AVX512EVEX 46387 ISA_SET: AVX512BW_512 46388 EXCEPTIONS: AVX512-E4NF 46389 REAL_OPCODE: Y 46390 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 46391 PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 46392 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 46393 IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 46394 } 46395 46396 46397 # EMITTING VPSHUFD (VPSHUFD-128-1) 46398 { 46399 ICLASS: VPSHUFD 46400 CPL: 3 46401 CATEGORY: AVX512 46402 EXTENSION: AVX512EVEX 46403 ISA_SET: AVX512F_128 46404 EXCEPTIONS: AVX512-E4NF 46405 REAL_OPCODE: Y 46406 ATTRIBUTES: MASKOP_EVEX 46407 PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() 46408 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b 46409 IFORM: VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 46410 } 46411 46412 { 46413 ICLASS: VPSHUFD 46414 CPL: 3 46415 CATEGORY: AVX512 46416 EXTENSION: AVX512EVEX 46417 ISA_SET: AVX512F_128 46418 EXCEPTIONS: AVX512-E4NF 46419 REAL_OPCODE: Y 46420 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46421 PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 46422 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 46423 IFORM: VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 46424 } 46425 46426 46427 # EMITTING VPSHUFD (VPSHUFD-256-1) 46428 { 46429 ICLASS: VPSHUFD 46430 CPL: 3 46431 CATEGORY: AVX512 46432 EXTENSION: AVX512EVEX 46433 ISA_SET: AVX512F_256 46434 EXCEPTIONS: AVX512-E4NF 46435 REAL_OPCODE: Y 46436 ATTRIBUTES: MASKOP_EVEX 46437 PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 46438 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b 46439 IFORM: VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 46440 } 46441 46442 { 46443 ICLASS: VPSHUFD 46444 CPL: 3 46445 CATEGORY: AVX512 46446 EXTENSION: AVX512EVEX 46447 ISA_SET: AVX512F_256 46448 EXCEPTIONS: AVX512-E4NF 46449 REAL_OPCODE: Y 46450 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46451 PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 46452 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 46453 IFORM: VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 46454 } 46455 46456 46457 # EMITTING VPSHUFHW (VPSHUFHW-128-1) 46458 { 46459 ICLASS: VPSHUFHW 46460 CPL: 3 46461 CATEGORY: AVX512 46462 EXTENSION: AVX512EVEX 46463 ISA_SET: AVX512BW_128 46464 EXCEPTIONS: AVX512-E4NF 46465 REAL_OPCODE: Y 46466 ATTRIBUTES: MASKOP_EVEX 46467 PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() 46468 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b 46469 IFORM: VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 46470 } 46471 46472 { 46473 ICLASS: VPSHUFHW 46474 CPL: 3 46475 CATEGORY: AVX512 46476 EXTENSION: AVX512EVEX 46477 ISA_SET: AVX512BW_128 46478 EXCEPTIONS: AVX512-E4NF 46479 REAL_OPCODE: Y 46480 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 46481 PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 46482 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b 46483 IFORM: VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 46484 } 46485 46486 46487 # EMITTING VPSHUFHW (VPSHUFHW-256-1) 46488 { 46489 ICLASS: VPSHUFHW 46490 CPL: 3 46491 CATEGORY: AVX512 46492 EXTENSION: AVX512EVEX 46493 ISA_SET: AVX512BW_256 46494 EXCEPTIONS: AVX512-E4NF 46495 REAL_OPCODE: Y 46496 ATTRIBUTES: MASKOP_EVEX 46497 PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() 46498 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b 46499 IFORM: VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 46500 } 46501 46502 { 46503 ICLASS: VPSHUFHW 46504 CPL: 3 46505 CATEGORY: AVX512 46506 EXTENSION: AVX512EVEX 46507 ISA_SET: AVX512BW_256 46508 EXCEPTIONS: AVX512-E4NF 46509 REAL_OPCODE: Y 46510 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 46511 PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 46512 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b 46513 IFORM: VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 46514 } 46515 46516 46517 # EMITTING VPSHUFHW (VPSHUFHW-512-1) 46518 { 46519 ICLASS: VPSHUFHW 46520 CPL: 3 46521 CATEGORY: AVX512 46522 EXTENSION: AVX512EVEX 46523 ISA_SET: AVX512BW_512 46524 EXCEPTIONS: AVX512-E4NF 46525 REAL_OPCODE: Y 46526 ATTRIBUTES: MASKOP_EVEX 46527 PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() 46528 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b 46529 IFORM: VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 46530 } 46531 46532 { 46533 ICLASS: VPSHUFHW 46534 CPL: 3 46535 CATEGORY: AVX512 46536 EXTENSION: AVX512EVEX 46537 ISA_SET: AVX512BW_512 46538 EXCEPTIONS: AVX512-E4NF 46539 REAL_OPCODE: Y 46540 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 46541 PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 46542 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b 46543 IFORM: VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 46544 } 46545 46546 46547 # EMITTING VPSHUFLW (VPSHUFLW-128-1) 46548 { 46549 ICLASS: VPSHUFLW 46550 CPL: 3 46551 CATEGORY: AVX512 46552 EXTENSION: AVX512EVEX 46553 ISA_SET: AVX512BW_128 46554 EXCEPTIONS: AVX512-E4NF 46555 REAL_OPCODE: Y 46556 ATTRIBUTES: MASKOP_EVEX 46557 PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() 46558 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b 46559 IFORM: VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 46560 } 46561 46562 { 46563 ICLASS: VPSHUFLW 46564 CPL: 3 46565 CATEGORY: AVX512 46566 EXTENSION: AVX512EVEX 46567 ISA_SET: AVX512BW_128 46568 EXCEPTIONS: AVX512-E4NF 46569 REAL_OPCODE: Y 46570 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 46571 PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 46572 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b 46573 IFORM: VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 46574 } 46575 46576 46577 # EMITTING VPSHUFLW (VPSHUFLW-256-1) 46578 { 46579 ICLASS: VPSHUFLW 46580 CPL: 3 46581 CATEGORY: AVX512 46582 EXTENSION: AVX512EVEX 46583 ISA_SET: AVX512BW_256 46584 EXCEPTIONS: AVX512-E4NF 46585 REAL_OPCODE: Y 46586 ATTRIBUTES: MASKOP_EVEX 46587 PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() 46588 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b 46589 IFORM: VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 46590 } 46591 46592 { 46593 ICLASS: VPSHUFLW 46594 CPL: 3 46595 CATEGORY: AVX512 46596 EXTENSION: AVX512EVEX 46597 ISA_SET: AVX512BW_256 46598 EXCEPTIONS: AVX512-E4NF 46599 REAL_OPCODE: Y 46600 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 46601 PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 46602 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b 46603 IFORM: VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 46604 } 46605 46606 46607 # EMITTING VPSHUFLW (VPSHUFLW-512-1) 46608 { 46609 ICLASS: VPSHUFLW 46610 CPL: 3 46611 CATEGORY: AVX512 46612 EXTENSION: AVX512EVEX 46613 ISA_SET: AVX512BW_512 46614 EXCEPTIONS: AVX512-E4NF 46615 REAL_OPCODE: Y 46616 ATTRIBUTES: MASKOP_EVEX 46617 PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() 46618 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b 46619 IFORM: VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 46620 } 46621 46622 { 46623 ICLASS: VPSHUFLW 46624 CPL: 3 46625 CATEGORY: AVX512 46626 EXTENSION: AVX512EVEX 46627 ISA_SET: AVX512BW_512 46628 EXCEPTIONS: AVX512-E4NF 46629 REAL_OPCODE: Y 46630 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 46631 PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 46632 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b 46633 IFORM: VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 46634 } 46635 46636 46637 # EMITTING VPSLLD (VPSLLD-128-1) 46638 { 46639 ICLASS: VPSLLD 46640 CPL: 3 46641 CATEGORY: AVX512 46642 EXTENSION: AVX512EVEX 46643 ISA_SET: AVX512F_128 46644 EXCEPTIONS: AVX512-E4NF 46645 REAL_OPCODE: Y 46646 ATTRIBUTES: MASKOP_EVEX 46647 PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 46648 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 46649 IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 46650 } 46651 46652 { 46653 ICLASS: VPSLLD 46654 CPL: 3 46655 CATEGORY: AVX512 46656 EXTENSION: AVX512EVEX 46657 ISA_SET: AVX512F_128 46658 EXCEPTIONS: AVX512-E4NF 46659 REAL_OPCODE: Y 46660 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 46661 PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() 46662 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 46663 IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 46664 } 46665 46666 46667 # EMITTING VPSLLD (VPSLLD-128-3) 46668 { 46669 ICLASS: VPSLLD 46670 CPL: 3 46671 CATEGORY: AVX512 46672 EXTENSION: AVX512EVEX 46673 ISA_SET: AVX512F_128 46674 EXCEPTIONS: AVX512-E4 46675 REAL_OPCODE: Y 46676 ATTRIBUTES: MASKOP_EVEX 46677 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W0 UIMM8() 46678 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b 46679 IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 46680 } 46681 46682 { 46683 ICLASS: VPSLLD 46684 CPL: 3 46685 CATEGORY: AVX512 46686 EXTENSION: AVX512EVEX 46687 ISA_SET: AVX512F_128 46688 EXCEPTIONS: AVX512-E4 46689 REAL_OPCODE: Y 46690 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46691 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 46692 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 46693 IFORM: VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 46694 } 46695 46696 46697 # EMITTING VPSLLD (VPSLLD-256-1) 46698 { 46699 ICLASS: VPSLLD 46700 CPL: 3 46701 CATEGORY: AVX512 46702 EXTENSION: AVX512EVEX 46703 ISA_SET: AVX512F_256 46704 EXCEPTIONS: AVX512-E4NF 46705 REAL_OPCODE: Y 46706 ATTRIBUTES: MASKOP_EVEX 46707 PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 46708 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 46709 IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 46710 } 46711 46712 { 46713 ICLASS: VPSLLD 46714 CPL: 3 46715 CATEGORY: AVX512 46716 EXTENSION: AVX512EVEX 46717 ISA_SET: AVX512F_256 46718 EXCEPTIONS: AVX512-E4NF 46719 REAL_OPCODE: Y 46720 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 46721 PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() 46722 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 46723 IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 46724 } 46725 46726 46727 # EMITTING VPSLLD (VPSLLD-256-3) 46728 { 46729 ICLASS: VPSLLD 46730 CPL: 3 46731 CATEGORY: AVX512 46732 EXTENSION: AVX512EVEX 46733 ISA_SET: AVX512F_256 46734 EXCEPTIONS: AVX512-E4 46735 REAL_OPCODE: Y 46736 ATTRIBUTES: MASKOP_EVEX 46737 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W0 UIMM8() 46738 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b 46739 IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 46740 } 46741 46742 { 46743 ICLASS: VPSLLD 46744 CPL: 3 46745 CATEGORY: AVX512 46746 EXTENSION: AVX512EVEX 46747 ISA_SET: AVX512F_256 46748 EXCEPTIONS: AVX512-E4 46749 REAL_OPCODE: Y 46750 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46751 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 46752 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 46753 IFORM: VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 46754 } 46755 46756 46757 # EMITTING VPSLLDQ (VPSLLDQ-128-2) 46758 { 46759 ICLASS: VPSLLDQ 46760 CPL: 3 46761 CATEGORY: AVX512 46762 EXTENSION: AVX512EVEX 46763 ISA_SET: AVX512BW_128 46764 EXCEPTIONS: AVX512-E4NF 46765 REAL_OPCODE: Y 46766 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() 46767 OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b 46768 IFORM: VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 46769 } 46770 46771 { 46772 ICLASS: VPSLLDQ 46773 CPL: 3 46774 CATEGORY: AVX512 46775 EXTENSION: AVX512EVEX 46776 ISA_SET: AVX512BW_128 46777 EXCEPTIONS: AVX512-E4NF 46778 REAL_OPCODE: Y 46779 ATTRIBUTES: DISP8_FULLMEM 46780 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 46781 OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b 46782 IFORM: VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 46783 } 46784 46785 46786 # EMITTING VPSLLDQ (VPSLLDQ-256-2) 46787 { 46788 ICLASS: VPSLLDQ 46789 CPL: 3 46790 CATEGORY: AVX512 46791 EXTENSION: AVX512EVEX 46792 ISA_SET: AVX512BW_256 46793 EXCEPTIONS: AVX512-E4NF 46794 REAL_OPCODE: Y 46795 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() 46796 OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b 46797 IFORM: VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 46798 } 46799 46800 { 46801 ICLASS: VPSLLDQ 46802 CPL: 3 46803 CATEGORY: AVX512 46804 EXTENSION: AVX512EVEX 46805 ISA_SET: AVX512BW_256 46806 EXCEPTIONS: AVX512-E4NF 46807 REAL_OPCODE: Y 46808 ATTRIBUTES: DISP8_FULLMEM 46809 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 46810 OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b 46811 IFORM: VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 46812 } 46813 46814 46815 # EMITTING VPSLLDQ (VPSLLDQ-512-1) 46816 { 46817 ICLASS: VPSLLDQ 46818 CPL: 3 46819 CATEGORY: AVX512 46820 EXTENSION: AVX512EVEX 46821 ISA_SET: AVX512BW_512 46822 EXCEPTIONS: AVX512-E4NF 46823 REAL_OPCODE: Y 46824 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() 46825 OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b 46826 IFORM: VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 46827 } 46828 46829 { 46830 ICLASS: VPSLLDQ 46831 CPL: 3 46832 CATEGORY: AVX512 46833 EXTENSION: AVX512EVEX 46834 ISA_SET: AVX512BW_512 46835 EXCEPTIONS: AVX512-E4NF 46836 REAL_OPCODE: Y 46837 ATTRIBUTES: DISP8_FULLMEM 46838 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 46839 OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b 46840 IFORM: VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 46841 } 46842 46843 46844 # EMITTING VPSLLQ (VPSLLQ-128-1) 46845 { 46846 ICLASS: VPSLLQ 46847 CPL: 3 46848 CATEGORY: AVX512 46849 EXTENSION: AVX512EVEX 46850 ISA_SET: AVX512F_128 46851 EXCEPTIONS: AVX512-E4NF 46852 REAL_OPCODE: Y 46853 ATTRIBUTES: MASKOP_EVEX 46854 PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 46855 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 46856 IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 46857 } 46858 46859 { 46860 ICLASS: VPSLLQ 46861 CPL: 3 46862 CATEGORY: AVX512 46863 EXTENSION: AVX512EVEX 46864 ISA_SET: AVX512F_128 46865 EXCEPTIONS: AVX512-E4NF 46866 REAL_OPCODE: Y 46867 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 46868 PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() 46869 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 46870 IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 46871 } 46872 46873 46874 # EMITTING VPSLLQ (VPSLLQ-128-3) 46875 { 46876 ICLASS: VPSLLQ 46877 CPL: 3 46878 CATEGORY: AVX512 46879 EXTENSION: AVX512EVEX 46880 ISA_SET: AVX512F_128 46881 EXCEPTIONS: AVX512-E4 46882 REAL_OPCODE: Y 46883 ATTRIBUTES: MASKOP_EVEX 46884 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8() 46885 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b 46886 IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 46887 } 46888 46889 { 46890 ICLASS: VPSLLQ 46891 CPL: 3 46892 CATEGORY: AVX512 46893 EXTENSION: AVX512EVEX 46894 ISA_SET: AVX512F_128 46895 EXCEPTIONS: AVX512-E4 46896 REAL_OPCODE: Y 46897 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46898 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 46899 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 46900 IFORM: VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 46901 } 46902 46903 46904 # EMITTING VPSLLQ (VPSLLQ-256-1) 46905 { 46906 ICLASS: VPSLLQ 46907 CPL: 3 46908 CATEGORY: AVX512 46909 EXTENSION: AVX512EVEX 46910 ISA_SET: AVX512F_256 46911 EXCEPTIONS: AVX512-E4NF 46912 REAL_OPCODE: Y 46913 ATTRIBUTES: MASKOP_EVEX 46914 PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 46915 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 46916 IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 46917 } 46918 46919 { 46920 ICLASS: VPSLLQ 46921 CPL: 3 46922 CATEGORY: AVX512 46923 EXTENSION: AVX512EVEX 46924 ISA_SET: AVX512F_256 46925 EXCEPTIONS: AVX512-E4NF 46926 REAL_OPCODE: Y 46927 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 46928 PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() 46929 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 46930 IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 46931 } 46932 46933 46934 # EMITTING VPSLLQ (VPSLLQ-256-3) 46935 { 46936 ICLASS: VPSLLQ 46937 CPL: 3 46938 CATEGORY: AVX512 46939 EXTENSION: AVX512EVEX 46940 ISA_SET: AVX512F_256 46941 EXCEPTIONS: AVX512-E4 46942 REAL_OPCODE: Y 46943 ATTRIBUTES: MASKOP_EVEX 46944 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8() 46945 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b 46946 IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 46947 } 46948 46949 { 46950 ICLASS: VPSLLQ 46951 CPL: 3 46952 CATEGORY: AVX512 46953 EXTENSION: AVX512EVEX 46954 ISA_SET: AVX512F_256 46955 EXCEPTIONS: AVX512-E4 46956 REAL_OPCODE: Y 46957 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46958 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 46959 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 46960 IFORM: VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 46961 } 46962 46963 46964 # EMITTING VPSLLVD (VPSLLVD-128-1) 46965 { 46966 ICLASS: VPSLLVD 46967 CPL: 3 46968 CATEGORY: AVX512 46969 EXTENSION: AVX512EVEX 46970 ISA_SET: AVX512F_128 46971 EXCEPTIONS: AVX512-E4 46972 REAL_OPCODE: Y 46973 ATTRIBUTES: MASKOP_EVEX 46974 PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 46975 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 46976 IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 46977 } 46978 46979 { 46980 ICLASS: VPSLLVD 46981 CPL: 3 46982 CATEGORY: AVX512 46983 EXTENSION: AVX512EVEX 46984 ISA_SET: AVX512F_128 46985 EXCEPTIONS: AVX512-E4 46986 REAL_OPCODE: Y 46987 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 46988 PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 46989 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 46990 IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 46991 } 46992 46993 46994 # EMITTING VPSLLVD (VPSLLVD-256-1) 46995 { 46996 ICLASS: VPSLLVD 46997 CPL: 3 46998 CATEGORY: AVX512 46999 EXTENSION: AVX512EVEX 47000 ISA_SET: AVX512F_256 47001 EXCEPTIONS: AVX512-E4 47002 REAL_OPCODE: Y 47003 ATTRIBUTES: MASKOP_EVEX 47004 PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 47005 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 47006 IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 47007 } 47008 47009 { 47010 ICLASS: VPSLLVD 47011 CPL: 3 47012 CATEGORY: AVX512 47013 EXTENSION: AVX512EVEX 47014 ISA_SET: AVX512F_256 47015 EXCEPTIONS: AVX512-E4 47016 REAL_OPCODE: Y 47017 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47018 PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 47019 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 47020 IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 47021 } 47022 47023 47024 # EMITTING VPSLLVQ (VPSLLVQ-128-1) 47025 { 47026 ICLASS: VPSLLVQ 47027 CPL: 3 47028 CATEGORY: AVX512 47029 EXTENSION: AVX512EVEX 47030 ISA_SET: AVX512F_128 47031 EXCEPTIONS: AVX512-E4 47032 REAL_OPCODE: Y 47033 ATTRIBUTES: MASKOP_EVEX 47034 PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 47035 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 47036 IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 47037 } 47038 47039 { 47040 ICLASS: VPSLLVQ 47041 CPL: 3 47042 CATEGORY: AVX512 47043 EXTENSION: AVX512EVEX 47044 ISA_SET: AVX512F_128 47045 EXCEPTIONS: AVX512-E4 47046 REAL_OPCODE: Y 47047 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47048 PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 47049 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 47050 IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 47051 } 47052 47053 47054 # EMITTING VPSLLVQ (VPSLLVQ-256-1) 47055 { 47056 ICLASS: VPSLLVQ 47057 CPL: 3 47058 CATEGORY: AVX512 47059 EXTENSION: AVX512EVEX 47060 ISA_SET: AVX512F_256 47061 EXCEPTIONS: AVX512-E4 47062 REAL_OPCODE: Y 47063 ATTRIBUTES: MASKOP_EVEX 47064 PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47065 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 47066 IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 47067 } 47068 47069 { 47070 ICLASS: VPSLLVQ 47071 CPL: 3 47072 CATEGORY: AVX512 47073 EXTENSION: AVX512EVEX 47074 ISA_SET: AVX512F_256 47075 EXCEPTIONS: AVX512-E4 47076 REAL_OPCODE: Y 47077 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47078 PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 47079 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 47080 IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 47081 } 47082 47083 47084 # EMITTING VPSLLVW (VPSLLVW-128-1) 47085 { 47086 ICLASS: VPSLLVW 47087 CPL: 3 47088 CATEGORY: AVX512 47089 EXTENSION: AVX512EVEX 47090 ISA_SET: AVX512BW_128 47091 EXCEPTIONS: AVX512-E4 47092 REAL_OPCODE: Y 47093 ATTRIBUTES: MASKOP_EVEX 47094 PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 47095 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 47096 IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 47097 } 47098 47099 { 47100 ICLASS: VPSLLVW 47101 CPL: 3 47102 CATEGORY: AVX512 47103 EXTENSION: AVX512EVEX 47104 ISA_SET: AVX512BW_128 47105 EXCEPTIONS: AVX512-E4 47106 REAL_OPCODE: Y 47107 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 47108 PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 47109 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 47110 IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 47111 } 47112 47113 47114 # EMITTING VPSLLVW (VPSLLVW-256-1) 47115 { 47116 ICLASS: VPSLLVW 47117 CPL: 3 47118 CATEGORY: AVX512 47119 EXTENSION: AVX512EVEX 47120 ISA_SET: AVX512BW_256 47121 EXCEPTIONS: AVX512-E4 47122 REAL_OPCODE: Y 47123 ATTRIBUTES: MASKOP_EVEX 47124 PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47125 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 47126 IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 47127 } 47128 47129 { 47130 ICLASS: VPSLLVW 47131 CPL: 3 47132 CATEGORY: AVX512 47133 EXTENSION: AVX512EVEX 47134 ISA_SET: AVX512BW_256 47135 EXCEPTIONS: AVX512-E4 47136 REAL_OPCODE: Y 47137 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 47138 PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 47139 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 47140 IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 47141 } 47142 47143 47144 # EMITTING VPSLLVW (VPSLLVW-512-1) 47145 { 47146 ICLASS: VPSLLVW 47147 CPL: 3 47148 CATEGORY: AVX512 47149 EXTENSION: AVX512EVEX 47150 ISA_SET: AVX512BW_512 47151 EXCEPTIONS: AVX512-E4 47152 REAL_OPCODE: Y 47153 ATTRIBUTES: MASKOP_EVEX 47154 PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 47155 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 47156 IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 47157 } 47158 47159 { 47160 ICLASS: VPSLLVW 47161 CPL: 3 47162 CATEGORY: AVX512 47163 EXTENSION: AVX512EVEX 47164 ISA_SET: AVX512BW_512 47165 EXCEPTIONS: AVX512-E4 47166 REAL_OPCODE: Y 47167 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 47168 PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 47169 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 47170 IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 47171 } 47172 47173 47174 # EMITTING VPSLLW (VPSLLW-128-1) 47175 { 47176 ICLASS: VPSLLW 47177 CPL: 3 47178 CATEGORY: AVX512 47179 EXTENSION: AVX512EVEX 47180 ISA_SET: AVX512BW_128 47181 EXCEPTIONS: AVX512-E4NF 47182 REAL_OPCODE: Y 47183 ATTRIBUTES: MASKOP_EVEX 47184 PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 47185 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 47186 IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 47187 } 47188 47189 { 47190 ICLASS: VPSLLW 47191 CPL: 3 47192 CATEGORY: AVX512 47193 EXTENSION: AVX512EVEX 47194 ISA_SET: AVX512BW_128 47195 EXCEPTIONS: AVX512-E4NF 47196 REAL_OPCODE: Y 47197 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 47198 PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() 47199 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 47200 IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 47201 } 47202 47203 47204 # EMITTING VPSLLW (VPSLLW-128-3) 47205 { 47206 ICLASS: VPSLLW 47207 CPL: 3 47208 CATEGORY: AVX512 47209 EXTENSION: AVX512EVEX 47210 ISA_SET: AVX512BW_128 47211 EXCEPTIONS: AVX512-E4 47212 REAL_OPCODE: Y 47213 ATTRIBUTES: MASKOP_EVEX 47214 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 UIMM8() 47215 OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b 47216 IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 47217 } 47218 47219 { 47220 ICLASS: VPSLLW 47221 CPL: 3 47222 CATEGORY: AVX512 47223 EXTENSION: AVX512EVEX 47224 ISA_SET: AVX512BW_128 47225 EXCEPTIONS: AVX512-E4 47226 REAL_OPCODE: Y 47227 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 47228 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 47229 OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b 47230 IFORM: VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 47231 } 47232 47233 47234 # EMITTING VPSLLW (VPSLLW-256-1) 47235 { 47236 ICLASS: VPSLLW 47237 CPL: 3 47238 CATEGORY: AVX512 47239 EXTENSION: AVX512EVEX 47240 ISA_SET: AVX512BW_256 47241 EXCEPTIONS: AVX512-E4NF 47242 REAL_OPCODE: Y 47243 ATTRIBUTES: MASKOP_EVEX 47244 PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 47245 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 47246 IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 47247 } 47248 47249 { 47250 ICLASS: VPSLLW 47251 CPL: 3 47252 CATEGORY: AVX512 47253 EXTENSION: AVX512EVEX 47254 ISA_SET: AVX512BW_256 47255 EXCEPTIONS: AVX512-E4NF 47256 REAL_OPCODE: Y 47257 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 47258 PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() 47259 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 47260 IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 47261 } 47262 47263 47264 # EMITTING VPSLLW (VPSLLW-256-3) 47265 { 47266 ICLASS: VPSLLW 47267 CPL: 3 47268 CATEGORY: AVX512 47269 EXTENSION: AVX512EVEX 47270 ISA_SET: AVX512BW_256 47271 EXCEPTIONS: AVX512-E4 47272 REAL_OPCODE: Y 47273 ATTRIBUTES: MASKOP_EVEX 47274 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 UIMM8() 47275 OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b 47276 IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 47277 } 47278 47279 { 47280 ICLASS: VPSLLW 47281 CPL: 3 47282 CATEGORY: AVX512 47283 EXTENSION: AVX512EVEX 47284 ISA_SET: AVX512BW_256 47285 EXCEPTIONS: AVX512-E4 47286 REAL_OPCODE: Y 47287 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 47288 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 47289 OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b 47290 IFORM: VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 47291 } 47292 47293 47294 # EMITTING VPSLLW (VPSLLW-512-1) 47295 { 47296 ICLASS: VPSLLW 47297 CPL: 3 47298 CATEGORY: AVX512 47299 EXTENSION: AVX512EVEX 47300 ISA_SET: AVX512BW_512 47301 EXCEPTIONS: AVX512-E4NF 47302 REAL_OPCODE: Y 47303 ATTRIBUTES: MASKOP_EVEX 47304 PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 47305 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 47306 IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 47307 } 47308 47309 { 47310 ICLASS: VPSLLW 47311 CPL: 3 47312 CATEGORY: AVX512 47313 EXTENSION: AVX512EVEX 47314 ISA_SET: AVX512BW_512 47315 EXCEPTIONS: AVX512-E4NF 47316 REAL_OPCODE: Y 47317 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 47318 PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() 47319 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 47320 IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 47321 } 47322 47323 47324 # EMITTING VPSLLW (VPSLLW-512-2) 47325 { 47326 ICLASS: VPSLLW 47327 CPL: 3 47328 CATEGORY: AVX512 47329 EXTENSION: AVX512EVEX 47330 ISA_SET: AVX512BW_512 47331 EXCEPTIONS: AVX512-E4 47332 REAL_OPCODE: Y 47333 ATTRIBUTES: MASKOP_EVEX 47334 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 UIMM8() 47335 OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b 47336 IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 47337 } 47338 47339 { 47340 ICLASS: VPSLLW 47341 CPL: 3 47342 CATEGORY: AVX512 47343 EXTENSION: AVX512EVEX 47344 ISA_SET: AVX512BW_512 47345 EXCEPTIONS: AVX512-E4 47346 REAL_OPCODE: Y 47347 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 47348 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 47349 OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b 47350 IFORM: VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 47351 } 47352 47353 47354 # EMITTING VPSRAD (VPSRAD-128-1) 47355 { 47356 ICLASS: VPSRAD 47357 CPL: 3 47358 CATEGORY: AVX512 47359 EXTENSION: AVX512EVEX 47360 ISA_SET: AVX512F_128 47361 EXCEPTIONS: AVX512-E4NF 47362 REAL_OPCODE: Y 47363 ATTRIBUTES: MASKOP_EVEX 47364 PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 47365 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 47366 IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 47367 } 47368 47369 { 47370 ICLASS: VPSRAD 47371 CPL: 3 47372 CATEGORY: AVX512 47373 EXTENSION: AVX512EVEX 47374 ISA_SET: AVX512F_128 47375 EXCEPTIONS: AVX512-E4NF 47376 REAL_OPCODE: Y 47377 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 47378 PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() 47379 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 47380 IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 47381 } 47382 47383 47384 # EMITTING VPSRAD (VPSRAD-128-3) 47385 { 47386 ICLASS: VPSRAD 47387 CPL: 3 47388 CATEGORY: AVX512 47389 EXTENSION: AVX512EVEX 47390 ISA_SET: AVX512F_128 47391 EXCEPTIONS: AVX512-E4 47392 REAL_OPCODE: Y 47393 ATTRIBUTES: MASKOP_EVEX 47394 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W0 UIMM8() 47395 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b 47396 IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 47397 } 47398 47399 { 47400 ICLASS: VPSRAD 47401 CPL: 3 47402 CATEGORY: AVX512 47403 EXTENSION: AVX512EVEX 47404 ISA_SET: AVX512F_128 47405 EXCEPTIONS: AVX512-E4 47406 REAL_OPCODE: Y 47407 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47408 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 47409 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 47410 IFORM: VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 47411 } 47412 47413 47414 # EMITTING VPSRAD (VPSRAD-256-1) 47415 { 47416 ICLASS: VPSRAD 47417 CPL: 3 47418 CATEGORY: AVX512 47419 EXTENSION: AVX512EVEX 47420 ISA_SET: AVX512F_256 47421 EXCEPTIONS: AVX512-E4NF 47422 REAL_OPCODE: Y 47423 ATTRIBUTES: MASKOP_EVEX 47424 PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 47425 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 47426 IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 47427 } 47428 47429 { 47430 ICLASS: VPSRAD 47431 CPL: 3 47432 CATEGORY: AVX512 47433 EXTENSION: AVX512EVEX 47434 ISA_SET: AVX512F_256 47435 EXCEPTIONS: AVX512-E4NF 47436 REAL_OPCODE: Y 47437 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 47438 PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() 47439 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 47440 IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 47441 } 47442 47443 47444 # EMITTING VPSRAD (VPSRAD-256-3) 47445 { 47446 ICLASS: VPSRAD 47447 CPL: 3 47448 CATEGORY: AVX512 47449 EXTENSION: AVX512EVEX 47450 ISA_SET: AVX512F_256 47451 EXCEPTIONS: AVX512-E4 47452 REAL_OPCODE: Y 47453 ATTRIBUTES: MASKOP_EVEX 47454 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W0 UIMM8() 47455 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b 47456 IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 47457 } 47458 47459 { 47460 ICLASS: VPSRAD 47461 CPL: 3 47462 CATEGORY: AVX512 47463 EXTENSION: AVX512EVEX 47464 ISA_SET: AVX512F_256 47465 EXCEPTIONS: AVX512-E4 47466 REAL_OPCODE: Y 47467 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47468 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 47469 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 47470 IFORM: VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 47471 } 47472 47473 47474 # EMITTING VPSRAQ (VPSRAQ-128-1) 47475 { 47476 ICLASS: VPSRAQ 47477 CPL: 3 47478 CATEGORY: AVX512 47479 EXTENSION: AVX512EVEX 47480 ISA_SET: AVX512F_128 47481 EXCEPTIONS: AVX512-E4NF 47482 REAL_OPCODE: Y 47483 ATTRIBUTES: MASKOP_EVEX 47484 PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 47485 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 47486 IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 47487 } 47488 47489 { 47490 ICLASS: VPSRAQ 47491 CPL: 3 47492 CATEGORY: AVX512 47493 EXTENSION: AVX512EVEX 47494 ISA_SET: AVX512F_128 47495 EXCEPTIONS: AVX512-E4NF 47496 REAL_OPCODE: Y 47497 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 47498 PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() 47499 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 47500 IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 47501 } 47502 47503 47504 # EMITTING VPSRAQ (VPSRAQ-128-2) 47505 { 47506 ICLASS: VPSRAQ 47507 CPL: 3 47508 CATEGORY: AVX512 47509 EXTENSION: AVX512EVEX 47510 ISA_SET: AVX512F_128 47511 EXCEPTIONS: AVX512-E4 47512 REAL_OPCODE: Y 47513 ATTRIBUTES: MASKOP_EVEX 47514 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W1 UIMM8() 47515 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b 47516 IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 47517 } 47518 47519 { 47520 ICLASS: VPSRAQ 47521 CPL: 3 47522 CATEGORY: AVX512 47523 EXTENSION: AVX512EVEX 47524 ISA_SET: AVX512F_128 47525 EXCEPTIONS: AVX512-E4 47526 REAL_OPCODE: Y 47527 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47528 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 47529 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 47530 IFORM: VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 47531 } 47532 47533 47534 # EMITTING VPSRAQ (VPSRAQ-256-1) 47535 { 47536 ICLASS: VPSRAQ 47537 CPL: 3 47538 CATEGORY: AVX512 47539 EXTENSION: AVX512EVEX 47540 ISA_SET: AVX512F_256 47541 EXCEPTIONS: AVX512-E4NF 47542 REAL_OPCODE: Y 47543 ATTRIBUTES: MASKOP_EVEX 47544 PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47545 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 47546 IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 47547 } 47548 47549 { 47550 ICLASS: VPSRAQ 47551 CPL: 3 47552 CATEGORY: AVX512 47553 EXTENSION: AVX512EVEX 47554 ISA_SET: AVX512F_256 47555 EXCEPTIONS: AVX512-E4NF 47556 REAL_OPCODE: Y 47557 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 47558 PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() 47559 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 47560 IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 47561 } 47562 47563 47564 # EMITTING VPSRAQ (VPSRAQ-256-2) 47565 { 47566 ICLASS: VPSRAQ 47567 CPL: 3 47568 CATEGORY: AVX512 47569 EXTENSION: AVX512EVEX 47570 ISA_SET: AVX512F_256 47571 EXCEPTIONS: AVX512-E4 47572 REAL_OPCODE: Y 47573 ATTRIBUTES: MASKOP_EVEX 47574 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W1 UIMM8() 47575 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b 47576 IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 47577 } 47578 47579 { 47580 ICLASS: VPSRAQ 47581 CPL: 3 47582 CATEGORY: AVX512 47583 EXTENSION: AVX512EVEX 47584 ISA_SET: AVX512F_256 47585 EXCEPTIONS: AVX512-E4 47586 REAL_OPCODE: Y 47587 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47588 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 47589 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 47590 IFORM: VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 47591 } 47592 47593 47594 # EMITTING VPSRAVD (VPSRAVD-128-1) 47595 { 47596 ICLASS: VPSRAVD 47597 CPL: 3 47598 CATEGORY: AVX512 47599 EXTENSION: AVX512EVEX 47600 ISA_SET: AVX512F_128 47601 EXCEPTIONS: AVX512-E4 47602 REAL_OPCODE: Y 47603 ATTRIBUTES: MASKOP_EVEX 47604 PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 47605 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 47606 IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 47607 } 47608 47609 { 47610 ICLASS: VPSRAVD 47611 CPL: 3 47612 CATEGORY: AVX512 47613 EXTENSION: AVX512EVEX 47614 ISA_SET: AVX512F_128 47615 EXCEPTIONS: AVX512-E4 47616 REAL_OPCODE: Y 47617 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47618 PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 47619 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 47620 IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 47621 } 47622 47623 47624 # EMITTING VPSRAVD (VPSRAVD-256-1) 47625 { 47626 ICLASS: VPSRAVD 47627 CPL: 3 47628 CATEGORY: AVX512 47629 EXTENSION: AVX512EVEX 47630 ISA_SET: AVX512F_256 47631 EXCEPTIONS: AVX512-E4 47632 REAL_OPCODE: Y 47633 ATTRIBUTES: MASKOP_EVEX 47634 PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 47635 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 47636 IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 47637 } 47638 47639 { 47640 ICLASS: VPSRAVD 47641 CPL: 3 47642 CATEGORY: AVX512 47643 EXTENSION: AVX512EVEX 47644 ISA_SET: AVX512F_256 47645 EXCEPTIONS: AVX512-E4 47646 REAL_OPCODE: Y 47647 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47648 PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 47649 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 47650 IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 47651 } 47652 47653 47654 # EMITTING VPSRAVQ (VPSRAVQ-128-1) 47655 { 47656 ICLASS: VPSRAVQ 47657 CPL: 3 47658 CATEGORY: AVX512 47659 EXTENSION: AVX512EVEX 47660 ISA_SET: AVX512F_128 47661 EXCEPTIONS: AVX512-E4 47662 REAL_OPCODE: Y 47663 ATTRIBUTES: MASKOP_EVEX 47664 PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 47665 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 47666 IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 47667 } 47668 47669 { 47670 ICLASS: VPSRAVQ 47671 CPL: 3 47672 CATEGORY: AVX512 47673 EXTENSION: AVX512EVEX 47674 ISA_SET: AVX512F_128 47675 EXCEPTIONS: AVX512-E4 47676 REAL_OPCODE: Y 47677 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47678 PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 47679 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 47680 IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 47681 } 47682 47683 47684 # EMITTING VPSRAVQ (VPSRAVQ-256-1) 47685 { 47686 ICLASS: VPSRAVQ 47687 CPL: 3 47688 CATEGORY: AVX512 47689 EXTENSION: AVX512EVEX 47690 ISA_SET: AVX512F_256 47691 EXCEPTIONS: AVX512-E4 47692 REAL_OPCODE: Y 47693 ATTRIBUTES: MASKOP_EVEX 47694 PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47695 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 47696 IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 47697 } 47698 47699 { 47700 ICLASS: VPSRAVQ 47701 CPL: 3 47702 CATEGORY: AVX512 47703 EXTENSION: AVX512EVEX 47704 ISA_SET: AVX512F_256 47705 EXCEPTIONS: AVX512-E4 47706 REAL_OPCODE: Y 47707 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 47708 PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 47709 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 47710 IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 47711 } 47712 47713 47714 # EMITTING VPSRAVW (VPSRAVW-128-1) 47715 { 47716 ICLASS: VPSRAVW 47717 CPL: 3 47718 CATEGORY: AVX512 47719 EXTENSION: AVX512EVEX 47720 ISA_SET: AVX512BW_128 47721 EXCEPTIONS: AVX512-E4 47722 REAL_OPCODE: Y 47723 ATTRIBUTES: MASKOP_EVEX 47724 PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 47725 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 47726 IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 47727 } 47728 47729 { 47730 ICLASS: VPSRAVW 47731 CPL: 3 47732 CATEGORY: AVX512 47733 EXTENSION: AVX512EVEX 47734 ISA_SET: AVX512BW_128 47735 EXCEPTIONS: AVX512-E4 47736 REAL_OPCODE: Y 47737 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 47738 PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 47739 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 47740 IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 47741 } 47742 47743 47744 # EMITTING VPSRAVW (VPSRAVW-256-1) 47745 { 47746 ICLASS: VPSRAVW 47747 CPL: 3 47748 CATEGORY: AVX512 47749 EXTENSION: AVX512EVEX 47750 ISA_SET: AVX512BW_256 47751 EXCEPTIONS: AVX512-E4 47752 REAL_OPCODE: Y 47753 ATTRIBUTES: MASKOP_EVEX 47754 PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 47755 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 47756 IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 47757 } 47758 47759 { 47760 ICLASS: VPSRAVW 47761 CPL: 3 47762 CATEGORY: AVX512 47763 EXTENSION: AVX512EVEX 47764 ISA_SET: AVX512BW_256 47765 EXCEPTIONS: AVX512-E4 47766 REAL_OPCODE: Y 47767 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 47768 PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 47769 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 47770 IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 47771 } 47772 47773 47774 # EMITTING VPSRAVW (VPSRAVW-512-1) 47775 { 47776 ICLASS: VPSRAVW 47777 CPL: 3 47778 CATEGORY: AVX512 47779 EXTENSION: AVX512EVEX 47780 ISA_SET: AVX512BW_512 47781 EXCEPTIONS: AVX512-E4 47782 REAL_OPCODE: Y 47783 ATTRIBUTES: MASKOP_EVEX 47784 PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 47785 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 47786 IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 47787 } 47788 47789 { 47790 ICLASS: VPSRAVW 47791 CPL: 3 47792 CATEGORY: AVX512 47793 EXTENSION: AVX512EVEX 47794 ISA_SET: AVX512BW_512 47795 EXCEPTIONS: AVX512-E4 47796 REAL_OPCODE: Y 47797 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 47798 PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 47799 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 47800 IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 47801 } 47802 47803 47804 # EMITTING VPSRAW (VPSRAW-128-1) 47805 { 47806 ICLASS: VPSRAW 47807 CPL: 3 47808 CATEGORY: AVX512 47809 EXTENSION: AVX512EVEX 47810 ISA_SET: AVX512BW_128 47811 EXCEPTIONS: AVX512-E4NF 47812 REAL_OPCODE: Y 47813 ATTRIBUTES: MASKOP_EVEX 47814 PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 47815 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 47816 IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 47817 } 47818 47819 { 47820 ICLASS: VPSRAW 47821 CPL: 3 47822 CATEGORY: AVX512 47823 EXTENSION: AVX512EVEX 47824 ISA_SET: AVX512BW_128 47825 EXCEPTIONS: AVX512-E4NF 47826 REAL_OPCODE: Y 47827 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 47828 PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() 47829 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 47830 IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 47831 } 47832 47833 47834 # EMITTING VPSRAW (VPSRAW-128-2) 47835 { 47836 ICLASS: VPSRAW 47837 CPL: 3 47838 CATEGORY: AVX512 47839 EXTENSION: AVX512EVEX 47840 ISA_SET: AVX512BW_128 47841 EXCEPTIONS: AVX512-E4 47842 REAL_OPCODE: Y 47843 ATTRIBUTES: MASKOP_EVEX 47844 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 UIMM8() 47845 OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b 47846 IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 47847 } 47848 47849 { 47850 ICLASS: VPSRAW 47851 CPL: 3 47852 CATEGORY: AVX512 47853 EXTENSION: AVX512EVEX 47854 ISA_SET: AVX512BW_128 47855 EXCEPTIONS: AVX512-E4 47856 REAL_OPCODE: Y 47857 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 47858 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 47859 OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b 47860 IFORM: VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 47861 } 47862 47863 47864 # EMITTING VPSRAW (VPSRAW-256-1) 47865 { 47866 ICLASS: VPSRAW 47867 CPL: 3 47868 CATEGORY: AVX512 47869 EXTENSION: AVX512EVEX 47870 ISA_SET: AVX512BW_256 47871 EXCEPTIONS: AVX512-E4NF 47872 REAL_OPCODE: Y 47873 ATTRIBUTES: MASKOP_EVEX 47874 PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 47875 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 47876 IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 47877 } 47878 47879 { 47880 ICLASS: VPSRAW 47881 CPL: 3 47882 CATEGORY: AVX512 47883 EXTENSION: AVX512EVEX 47884 ISA_SET: AVX512BW_256 47885 EXCEPTIONS: AVX512-E4NF 47886 REAL_OPCODE: Y 47887 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 47888 PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() 47889 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 47890 IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 47891 } 47892 47893 47894 # EMITTING VPSRAW (VPSRAW-256-2) 47895 { 47896 ICLASS: VPSRAW 47897 CPL: 3 47898 CATEGORY: AVX512 47899 EXTENSION: AVX512EVEX 47900 ISA_SET: AVX512BW_256 47901 EXCEPTIONS: AVX512-E4 47902 REAL_OPCODE: Y 47903 ATTRIBUTES: MASKOP_EVEX 47904 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 UIMM8() 47905 OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b 47906 IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 47907 } 47908 47909 { 47910 ICLASS: VPSRAW 47911 CPL: 3 47912 CATEGORY: AVX512 47913 EXTENSION: AVX512EVEX 47914 ISA_SET: AVX512BW_256 47915 EXCEPTIONS: AVX512-E4 47916 REAL_OPCODE: Y 47917 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 47918 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 47919 OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b 47920 IFORM: VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 47921 } 47922 47923 47924 # EMITTING VPSRAW (VPSRAW-512-1) 47925 { 47926 ICLASS: VPSRAW 47927 CPL: 3 47928 CATEGORY: AVX512 47929 EXTENSION: AVX512EVEX 47930 ISA_SET: AVX512BW_512 47931 EXCEPTIONS: AVX512-E4NF 47932 REAL_OPCODE: Y 47933 ATTRIBUTES: MASKOP_EVEX 47934 PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 47935 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 47936 IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 47937 } 47938 47939 { 47940 ICLASS: VPSRAW 47941 CPL: 3 47942 CATEGORY: AVX512 47943 EXTENSION: AVX512EVEX 47944 ISA_SET: AVX512BW_512 47945 EXCEPTIONS: AVX512-E4NF 47946 REAL_OPCODE: Y 47947 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 47948 PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() 47949 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 47950 IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 47951 } 47952 47953 47954 # EMITTING VPSRAW (VPSRAW-512-2) 47955 { 47956 ICLASS: VPSRAW 47957 CPL: 3 47958 CATEGORY: AVX512 47959 EXTENSION: AVX512EVEX 47960 ISA_SET: AVX512BW_512 47961 EXCEPTIONS: AVX512-E4 47962 REAL_OPCODE: Y 47963 ATTRIBUTES: MASKOP_EVEX 47964 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 UIMM8() 47965 OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b 47966 IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 47967 } 47968 47969 { 47970 ICLASS: VPSRAW 47971 CPL: 3 47972 CATEGORY: AVX512 47973 EXTENSION: AVX512EVEX 47974 ISA_SET: AVX512BW_512 47975 EXCEPTIONS: AVX512-E4 47976 REAL_OPCODE: Y 47977 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 47978 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 47979 OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b 47980 IFORM: VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 47981 } 47982 47983 47984 # EMITTING VPSRLD (VPSRLD-128-1) 47985 { 47986 ICLASS: VPSRLD 47987 CPL: 3 47988 CATEGORY: AVX512 47989 EXTENSION: AVX512EVEX 47990 ISA_SET: AVX512F_128 47991 EXCEPTIONS: AVX512-E4NF 47992 REAL_OPCODE: Y 47993 ATTRIBUTES: MASKOP_EVEX 47994 PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 47995 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 47996 IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 47997 } 47998 47999 { 48000 ICLASS: VPSRLD 48001 CPL: 3 48002 CATEGORY: AVX512 48003 EXTENSION: AVX512EVEX 48004 ISA_SET: AVX512F_128 48005 EXCEPTIONS: AVX512-E4NF 48006 REAL_OPCODE: Y 48007 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 48008 PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() 48009 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 48010 IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 48011 } 48012 48013 48014 # EMITTING VPSRLD (VPSRLD-128-2) 48015 { 48016 ICLASS: VPSRLD 48017 CPL: 3 48018 CATEGORY: AVX512 48019 EXTENSION: AVX512EVEX 48020 ISA_SET: AVX512F_128 48021 EXCEPTIONS: AVX512-E4 48022 REAL_OPCODE: Y 48023 ATTRIBUTES: MASKOP_EVEX 48024 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W0 UIMM8() 48025 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b 48026 IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 48027 } 48028 48029 { 48030 ICLASS: VPSRLD 48031 CPL: 3 48032 CATEGORY: AVX512 48033 EXTENSION: AVX512EVEX 48034 ISA_SET: AVX512F_128 48035 EXCEPTIONS: AVX512-E4 48036 REAL_OPCODE: Y 48037 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48038 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 48039 OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 48040 IFORM: VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 48041 } 48042 48043 48044 # EMITTING VPSRLD (VPSRLD-256-1) 48045 { 48046 ICLASS: VPSRLD 48047 CPL: 3 48048 CATEGORY: AVX512 48049 EXTENSION: AVX512EVEX 48050 ISA_SET: AVX512F_256 48051 EXCEPTIONS: AVX512-E4NF 48052 REAL_OPCODE: Y 48053 ATTRIBUTES: MASKOP_EVEX 48054 PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 48055 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 48056 IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 48057 } 48058 48059 { 48060 ICLASS: VPSRLD 48061 CPL: 3 48062 CATEGORY: AVX512 48063 EXTENSION: AVX512EVEX 48064 ISA_SET: AVX512F_256 48065 EXCEPTIONS: AVX512-E4NF 48066 REAL_OPCODE: Y 48067 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 48068 PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() 48069 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 48070 IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 48071 } 48072 48073 48074 # EMITTING VPSRLD (VPSRLD-256-2) 48075 { 48076 ICLASS: VPSRLD 48077 CPL: 3 48078 CATEGORY: AVX512 48079 EXTENSION: AVX512EVEX 48080 ISA_SET: AVX512F_256 48081 EXCEPTIONS: AVX512-E4 48082 REAL_OPCODE: Y 48083 ATTRIBUTES: MASKOP_EVEX 48084 PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W0 UIMM8() 48085 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b 48086 IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 48087 } 48088 48089 { 48090 ICLASS: VPSRLD 48091 CPL: 3 48092 CATEGORY: AVX512 48093 EXTENSION: AVX512EVEX 48094 ISA_SET: AVX512F_256 48095 EXCEPTIONS: AVX512-E4 48096 REAL_OPCODE: Y 48097 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48098 PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 48099 OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 48100 IFORM: VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 48101 } 48102 48103 48104 # EMITTING VPSRLDQ (VPSRLDQ-128-1) 48105 { 48106 ICLASS: VPSRLDQ 48107 CPL: 3 48108 CATEGORY: AVX512 48109 EXTENSION: AVX512EVEX 48110 ISA_SET: AVX512BW_128 48111 EXCEPTIONS: AVX512-E4NF 48112 REAL_OPCODE: Y 48113 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() 48114 OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b 48115 IFORM: VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 48116 } 48117 48118 { 48119 ICLASS: VPSRLDQ 48120 CPL: 3 48121 CATEGORY: AVX512 48122 EXTENSION: AVX512EVEX 48123 ISA_SET: AVX512BW_128 48124 EXCEPTIONS: AVX512-E4NF 48125 REAL_OPCODE: Y 48126 ATTRIBUTES: DISP8_FULLMEM 48127 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 48128 OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b 48129 IFORM: VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 48130 } 48131 48132 48133 # EMITTING VPSRLDQ (VPSRLDQ-256-1) 48134 { 48135 ICLASS: VPSRLDQ 48136 CPL: 3 48137 CATEGORY: AVX512 48138 EXTENSION: AVX512EVEX 48139 ISA_SET: AVX512BW_256 48140 EXCEPTIONS: AVX512-E4NF 48141 REAL_OPCODE: Y 48142 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() 48143 OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b 48144 IFORM: VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 48145 } 48146 48147 { 48148 ICLASS: VPSRLDQ 48149 CPL: 3 48150 CATEGORY: AVX512 48151 EXTENSION: AVX512EVEX 48152 ISA_SET: AVX512BW_256 48153 EXCEPTIONS: AVX512-E4NF 48154 REAL_OPCODE: Y 48155 ATTRIBUTES: DISP8_FULLMEM 48156 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 48157 OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b 48158 IFORM: VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 48159 } 48160 48161 48162 # EMITTING VPSRLDQ (VPSRLDQ-512-1) 48163 { 48164 ICLASS: VPSRLDQ 48165 CPL: 3 48166 CATEGORY: AVX512 48167 EXTENSION: AVX512EVEX 48168 ISA_SET: AVX512BW_512 48169 EXCEPTIONS: AVX512-E4NF 48170 REAL_OPCODE: Y 48171 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() 48172 OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b 48173 IFORM: VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 48174 } 48175 48176 { 48177 ICLASS: VPSRLDQ 48178 CPL: 3 48179 CATEGORY: AVX512 48180 EXTENSION: AVX512EVEX 48181 ISA_SET: AVX512BW_512 48182 EXCEPTIONS: AVX512-E4NF 48183 REAL_OPCODE: Y 48184 ATTRIBUTES: DISP8_FULLMEM 48185 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() 48186 OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b 48187 IFORM: VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 48188 } 48189 48190 48191 # EMITTING VPSRLQ (VPSRLQ-128-1) 48192 { 48193 ICLASS: VPSRLQ 48194 CPL: 3 48195 CATEGORY: AVX512 48196 EXTENSION: AVX512EVEX 48197 ISA_SET: AVX512F_128 48198 EXCEPTIONS: AVX512-E4NF 48199 REAL_OPCODE: Y 48200 ATTRIBUTES: MASKOP_EVEX 48201 PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 48202 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 48203 IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 48204 } 48205 48206 { 48207 ICLASS: VPSRLQ 48208 CPL: 3 48209 CATEGORY: AVX512 48210 EXTENSION: AVX512EVEX 48211 ISA_SET: AVX512F_128 48212 EXCEPTIONS: AVX512-E4NF 48213 REAL_OPCODE: Y 48214 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 48215 PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() 48216 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 48217 IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 48218 } 48219 48220 48221 # EMITTING VPSRLQ (VPSRLQ-128-2) 48222 { 48223 ICLASS: VPSRLQ 48224 CPL: 3 48225 CATEGORY: AVX512 48226 EXTENSION: AVX512EVEX 48227 ISA_SET: AVX512F_128 48228 EXCEPTIONS: AVX512-E4 48229 REAL_OPCODE: Y 48230 ATTRIBUTES: MASKOP_EVEX 48231 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8() 48232 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b 48233 IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 48234 } 48235 48236 { 48237 ICLASS: VPSRLQ 48238 CPL: 3 48239 CATEGORY: AVX512 48240 EXTENSION: AVX512EVEX 48241 ISA_SET: AVX512F_128 48242 EXCEPTIONS: AVX512-E4 48243 REAL_OPCODE: Y 48244 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48245 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 48246 OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 48247 IFORM: VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 48248 } 48249 48250 48251 # EMITTING VPSRLQ (VPSRLQ-256-1) 48252 { 48253 ICLASS: VPSRLQ 48254 CPL: 3 48255 CATEGORY: AVX512 48256 EXTENSION: AVX512EVEX 48257 ISA_SET: AVX512F_256 48258 EXCEPTIONS: AVX512-E4NF 48259 REAL_OPCODE: Y 48260 ATTRIBUTES: MASKOP_EVEX 48261 PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 48262 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 48263 IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 48264 } 48265 48266 { 48267 ICLASS: VPSRLQ 48268 CPL: 3 48269 CATEGORY: AVX512 48270 EXTENSION: AVX512EVEX 48271 ISA_SET: AVX512F_256 48272 EXCEPTIONS: AVX512-E4NF 48273 REAL_OPCODE: Y 48274 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 48275 PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() 48276 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 48277 IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 48278 } 48279 48280 48281 # EMITTING VPSRLQ (VPSRLQ-256-2) 48282 { 48283 ICLASS: VPSRLQ 48284 CPL: 3 48285 CATEGORY: AVX512 48286 EXTENSION: AVX512EVEX 48287 ISA_SET: AVX512F_256 48288 EXCEPTIONS: AVX512-E4 48289 REAL_OPCODE: Y 48290 ATTRIBUTES: MASKOP_EVEX 48291 PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8() 48292 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b 48293 IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 48294 } 48295 48296 { 48297 ICLASS: VPSRLQ 48298 CPL: 3 48299 CATEGORY: AVX512 48300 EXTENSION: AVX512EVEX 48301 ISA_SET: AVX512F_256 48302 EXCEPTIONS: AVX512-E4 48303 REAL_OPCODE: Y 48304 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48305 PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 48306 OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 48307 IFORM: VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 48308 } 48309 48310 48311 # EMITTING VPSRLVD (VPSRLVD-128-1) 48312 { 48313 ICLASS: VPSRLVD 48314 CPL: 3 48315 CATEGORY: AVX512 48316 EXTENSION: AVX512EVEX 48317 ISA_SET: AVX512F_128 48318 EXCEPTIONS: AVX512-E4 48319 REAL_OPCODE: Y 48320 ATTRIBUTES: MASKOP_EVEX 48321 PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 48322 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 48323 IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 48324 } 48325 48326 { 48327 ICLASS: VPSRLVD 48328 CPL: 3 48329 CATEGORY: AVX512 48330 EXTENSION: AVX512EVEX 48331 ISA_SET: AVX512F_128 48332 EXCEPTIONS: AVX512-E4 48333 REAL_OPCODE: Y 48334 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48335 PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 48336 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 48337 IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 48338 } 48339 48340 48341 # EMITTING VPSRLVD (VPSRLVD-256-1) 48342 { 48343 ICLASS: VPSRLVD 48344 CPL: 3 48345 CATEGORY: AVX512 48346 EXTENSION: AVX512EVEX 48347 ISA_SET: AVX512F_256 48348 EXCEPTIONS: AVX512-E4 48349 REAL_OPCODE: Y 48350 ATTRIBUTES: MASKOP_EVEX 48351 PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 48352 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 48353 IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 48354 } 48355 48356 { 48357 ICLASS: VPSRLVD 48358 CPL: 3 48359 CATEGORY: AVX512 48360 EXTENSION: AVX512EVEX 48361 ISA_SET: AVX512F_256 48362 EXCEPTIONS: AVX512-E4 48363 REAL_OPCODE: Y 48364 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48365 PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 48366 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 48367 IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 48368 } 48369 48370 48371 # EMITTING VPSRLVQ (VPSRLVQ-128-1) 48372 { 48373 ICLASS: VPSRLVQ 48374 CPL: 3 48375 CATEGORY: AVX512 48376 EXTENSION: AVX512EVEX 48377 ISA_SET: AVX512F_128 48378 EXCEPTIONS: AVX512-E4 48379 REAL_OPCODE: Y 48380 ATTRIBUTES: MASKOP_EVEX 48381 PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 48382 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 48383 IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 48384 } 48385 48386 { 48387 ICLASS: VPSRLVQ 48388 CPL: 3 48389 CATEGORY: AVX512 48390 EXTENSION: AVX512EVEX 48391 ISA_SET: AVX512F_128 48392 EXCEPTIONS: AVX512-E4 48393 REAL_OPCODE: Y 48394 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48395 PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 48396 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 48397 IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 48398 } 48399 48400 48401 # EMITTING VPSRLVQ (VPSRLVQ-256-1) 48402 { 48403 ICLASS: VPSRLVQ 48404 CPL: 3 48405 CATEGORY: AVX512 48406 EXTENSION: AVX512EVEX 48407 ISA_SET: AVX512F_256 48408 EXCEPTIONS: AVX512-E4 48409 REAL_OPCODE: Y 48410 ATTRIBUTES: MASKOP_EVEX 48411 PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 48412 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 48413 IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 48414 } 48415 48416 { 48417 ICLASS: VPSRLVQ 48418 CPL: 3 48419 CATEGORY: AVX512 48420 EXTENSION: AVX512EVEX 48421 ISA_SET: AVX512F_256 48422 EXCEPTIONS: AVX512-E4 48423 REAL_OPCODE: Y 48424 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48425 PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 48426 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 48427 IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 48428 } 48429 48430 48431 # EMITTING VPSRLVW (VPSRLVW-128-1) 48432 { 48433 ICLASS: VPSRLVW 48434 CPL: 3 48435 CATEGORY: AVX512 48436 EXTENSION: AVX512EVEX 48437 ISA_SET: AVX512BW_128 48438 EXCEPTIONS: AVX512-E4 48439 REAL_OPCODE: Y 48440 ATTRIBUTES: MASKOP_EVEX 48441 PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 48442 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 48443 IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 48444 } 48445 48446 { 48447 ICLASS: VPSRLVW 48448 CPL: 3 48449 CATEGORY: AVX512 48450 EXTENSION: AVX512EVEX 48451 ISA_SET: AVX512BW_128 48452 EXCEPTIONS: AVX512-E4 48453 REAL_OPCODE: Y 48454 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 48455 PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 48456 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 48457 IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 48458 } 48459 48460 48461 # EMITTING VPSRLVW (VPSRLVW-256-1) 48462 { 48463 ICLASS: VPSRLVW 48464 CPL: 3 48465 CATEGORY: AVX512 48466 EXTENSION: AVX512EVEX 48467 ISA_SET: AVX512BW_256 48468 EXCEPTIONS: AVX512-E4 48469 REAL_OPCODE: Y 48470 ATTRIBUTES: MASKOP_EVEX 48471 PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 48472 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 48473 IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 48474 } 48475 48476 { 48477 ICLASS: VPSRLVW 48478 CPL: 3 48479 CATEGORY: AVX512 48480 EXTENSION: AVX512EVEX 48481 ISA_SET: AVX512BW_256 48482 EXCEPTIONS: AVX512-E4 48483 REAL_OPCODE: Y 48484 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 48485 PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 48486 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 48487 IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 48488 } 48489 48490 48491 # EMITTING VPSRLVW (VPSRLVW-512-1) 48492 { 48493 ICLASS: VPSRLVW 48494 CPL: 3 48495 CATEGORY: AVX512 48496 EXTENSION: AVX512EVEX 48497 ISA_SET: AVX512BW_512 48498 EXCEPTIONS: AVX512-E4 48499 REAL_OPCODE: Y 48500 ATTRIBUTES: MASKOP_EVEX 48501 PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 48502 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 48503 IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 48504 } 48505 48506 { 48507 ICLASS: VPSRLVW 48508 CPL: 3 48509 CATEGORY: AVX512 48510 EXTENSION: AVX512EVEX 48511 ISA_SET: AVX512BW_512 48512 EXCEPTIONS: AVX512-E4 48513 REAL_OPCODE: Y 48514 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 48515 PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 48516 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 48517 IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 48518 } 48519 48520 48521 # EMITTING VPSRLW (VPSRLW-128-1) 48522 { 48523 ICLASS: VPSRLW 48524 CPL: 3 48525 CATEGORY: AVX512 48526 EXTENSION: AVX512EVEX 48527 ISA_SET: AVX512BW_128 48528 EXCEPTIONS: AVX512-E4NF 48529 REAL_OPCODE: Y 48530 ATTRIBUTES: MASKOP_EVEX 48531 PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 48532 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 48533 IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 48534 } 48535 48536 { 48537 ICLASS: VPSRLW 48538 CPL: 3 48539 CATEGORY: AVX512 48540 EXTENSION: AVX512EVEX 48541 ISA_SET: AVX512BW_128 48542 EXCEPTIONS: AVX512-E4NF 48543 REAL_OPCODE: Y 48544 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 48545 PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() 48546 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 48547 IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 48548 } 48549 48550 48551 # EMITTING VPSRLW (VPSRLW-128-2) 48552 { 48553 ICLASS: VPSRLW 48554 CPL: 3 48555 CATEGORY: AVX512 48556 EXTENSION: AVX512EVEX 48557 ISA_SET: AVX512BW_128 48558 EXCEPTIONS: AVX512-E4 48559 REAL_OPCODE: Y 48560 ATTRIBUTES: MASKOP_EVEX 48561 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 UIMM8() 48562 OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b 48563 IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 48564 } 48565 48566 { 48567 ICLASS: VPSRLW 48568 CPL: 3 48569 CATEGORY: AVX512 48570 EXTENSION: AVX512EVEX 48571 ISA_SET: AVX512BW_128 48572 EXCEPTIONS: AVX512-E4 48573 REAL_OPCODE: Y 48574 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 48575 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 48576 OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b 48577 IFORM: VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 48578 } 48579 48580 48581 # EMITTING VPSRLW (VPSRLW-256-1) 48582 { 48583 ICLASS: VPSRLW 48584 CPL: 3 48585 CATEGORY: AVX512 48586 EXTENSION: AVX512EVEX 48587 ISA_SET: AVX512BW_256 48588 EXCEPTIONS: AVX512-E4NF 48589 REAL_OPCODE: Y 48590 ATTRIBUTES: MASKOP_EVEX 48591 PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 48592 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 48593 IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 48594 } 48595 48596 { 48597 ICLASS: VPSRLW 48598 CPL: 3 48599 CATEGORY: AVX512 48600 EXTENSION: AVX512EVEX 48601 ISA_SET: AVX512BW_256 48602 EXCEPTIONS: AVX512-E4NF 48603 REAL_OPCODE: Y 48604 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 48605 PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() 48606 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 48607 IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 48608 } 48609 48610 48611 # EMITTING VPSRLW (VPSRLW-256-2) 48612 { 48613 ICLASS: VPSRLW 48614 CPL: 3 48615 CATEGORY: AVX512 48616 EXTENSION: AVX512EVEX 48617 ISA_SET: AVX512BW_256 48618 EXCEPTIONS: AVX512-E4 48619 REAL_OPCODE: Y 48620 ATTRIBUTES: MASKOP_EVEX 48621 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 UIMM8() 48622 OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b 48623 IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 48624 } 48625 48626 { 48627 ICLASS: VPSRLW 48628 CPL: 3 48629 CATEGORY: AVX512 48630 EXTENSION: AVX512EVEX 48631 ISA_SET: AVX512BW_256 48632 EXCEPTIONS: AVX512-E4 48633 REAL_OPCODE: Y 48634 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 48635 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 48636 OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b 48637 IFORM: VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 48638 } 48639 48640 48641 # EMITTING VPSRLW (VPSRLW-512-1) 48642 { 48643 ICLASS: VPSRLW 48644 CPL: 3 48645 CATEGORY: AVX512 48646 EXTENSION: AVX512EVEX 48647 ISA_SET: AVX512BW_512 48648 EXCEPTIONS: AVX512-E4NF 48649 REAL_OPCODE: Y 48650 ATTRIBUTES: MASKOP_EVEX 48651 PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 48652 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 48653 IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 48654 } 48655 48656 { 48657 ICLASS: VPSRLW 48658 CPL: 3 48659 CATEGORY: AVX512 48660 EXTENSION: AVX512EVEX 48661 ISA_SET: AVX512BW_512 48662 EXCEPTIONS: AVX512-E4NF 48663 REAL_OPCODE: Y 48664 ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 48665 PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() 48666 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 48667 IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 48668 } 48669 48670 48671 # EMITTING VPSRLW (VPSRLW-512-2) 48672 { 48673 ICLASS: VPSRLW 48674 CPL: 3 48675 CATEGORY: AVX512 48676 EXTENSION: AVX512EVEX 48677 ISA_SET: AVX512BW_512 48678 EXCEPTIONS: AVX512-E4 48679 REAL_OPCODE: Y 48680 ATTRIBUTES: MASKOP_EVEX 48681 PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 UIMM8() 48682 OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b 48683 IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 48684 } 48685 48686 { 48687 ICLASS: VPSRLW 48688 CPL: 3 48689 CATEGORY: AVX512 48690 EXTENSION: AVX512EVEX 48691 ISA_SET: AVX512BW_512 48692 EXCEPTIONS: AVX512-E4 48693 REAL_OPCODE: Y 48694 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 48695 PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 48696 OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b 48697 IFORM: VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 48698 } 48699 48700 48701 # EMITTING VPSUBB (VPSUBB-128-1) 48702 { 48703 ICLASS: VPSUBB 48704 CPL: 3 48705 CATEGORY: AVX512 48706 EXTENSION: AVX512EVEX 48707 ISA_SET: AVX512BW_128 48708 EXCEPTIONS: AVX512-E4 48709 REAL_OPCODE: Y 48710 ATTRIBUTES: MASKOP_EVEX 48711 PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 48712 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 48713 IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 48714 } 48715 48716 { 48717 ICLASS: VPSUBB 48718 CPL: 3 48719 CATEGORY: AVX512 48720 EXTENSION: AVX512EVEX 48721 ISA_SET: AVX512BW_128 48722 EXCEPTIONS: AVX512-E4 48723 REAL_OPCODE: Y 48724 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 48725 PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 48726 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 48727 IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 48728 } 48729 48730 48731 # EMITTING VPSUBB (VPSUBB-256-1) 48732 { 48733 ICLASS: VPSUBB 48734 CPL: 3 48735 CATEGORY: AVX512 48736 EXTENSION: AVX512EVEX 48737 ISA_SET: AVX512BW_256 48738 EXCEPTIONS: AVX512-E4 48739 REAL_OPCODE: Y 48740 ATTRIBUTES: MASKOP_EVEX 48741 PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 48742 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 48743 IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 48744 } 48745 48746 { 48747 ICLASS: VPSUBB 48748 CPL: 3 48749 CATEGORY: AVX512 48750 EXTENSION: AVX512EVEX 48751 ISA_SET: AVX512BW_256 48752 EXCEPTIONS: AVX512-E4 48753 REAL_OPCODE: Y 48754 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 48755 PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 48756 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 48757 IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 48758 } 48759 48760 48761 # EMITTING VPSUBB (VPSUBB-512-1) 48762 { 48763 ICLASS: VPSUBB 48764 CPL: 3 48765 CATEGORY: AVX512 48766 EXTENSION: AVX512EVEX 48767 ISA_SET: AVX512BW_512 48768 EXCEPTIONS: AVX512-E4 48769 REAL_OPCODE: Y 48770 ATTRIBUTES: MASKOP_EVEX 48771 PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 48772 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 48773 IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 48774 } 48775 48776 { 48777 ICLASS: VPSUBB 48778 CPL: 3 48779 CATEGORY: AVX512 48780 EXTENSION: AVX512EVEX 48781 ISA_SET: AVX512BW_512 48782 EXCEPTIONS: AVX512-E4 48783 REAL_OPCODE: Y 48784 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 48785 PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 48786 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 48787 IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 48788 } 48789 48790 48791 # EMITTING VPSUBD (VPSUBD-128-1) 48792 { 48793 ICLASS: VPSUBD 48794 CPL: 3 48795 CATEGORY: AVX512 48796 EXTENSION: AVX512EVEX 48797 ISA_SET: AVX512F_128 48798 EXCEPTIONS: AVX512-E4 48799 REAL_OPCODE: Y 48800 ATTRIBUTES: MASKOP_EVEX 48801 PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 48802 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 48803 IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 48804 } 48805 48806 { 48807 ICLASS: VPSUBD 48808 CPL: 3 48809 CATEGORY: AVX512 48810 EXTENSION: AVX512EVEX 48811 ISA_SET: AVX512F_128 48812 EXCEPTIONS: AVX512-E4 48813 REAL_OPCODE: Y 48814 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48815 PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 48816 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 48817 IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 48818 } 48819 48820 48821 # EMITTING VPSUBD (VPSUBD-256-1) 48822 { 48823 ICLASS: VPSUBD 48824 CPL: 3 48825 CATEGORY: AVX512 48826 EXTENSION: AVX512EVEX 48827 ISA_SET: AVX512F_256 48828 EXCEPTIONS: AVX512-E4 48829 REAL_OPCODE: Y 48830 ATTRIBUTES: MASKOP_EVEX 48831 PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 48832 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 48833 IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 48834 } 48835 48836 { 48837 ICLASS: VPSUBD 48838 CPL: 3 48839 CATEGORY: AVX512 48840 EXTENSION: AVX512EVEX 48841 ISA_SET: AVX512F_256 48842 EXCEPTIONS: AVX512-E4 48843 REAL_OPCODE: Y 48844 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48845 PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 48846 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 48847 IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 48848 } 48849 48850 48851 # EMITTING VPSUBQ (VPSUBQ-128-1) 48852 { 48853 ICLASS: VPSUBQ 48854 CPL: 3 48855 CATEGORY: AVX512 48856 EXTENSION: AVX512EVEX 48857 ISA_SET: AVX512F_128 48858 EXCEPTIONS: AVX512-E4 48859 REAL_OPCODE: Y 48860 ATTRIBUTES: MASKOP_EVEX 48861 PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 48862 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 48863 IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 48864 } 48865 48866 { 48867 ICLASS: VPSUBQ 48868 CPL: 3 48869 CATEGORY: AVX512 48870 EXTENSION: AVX512EVEX 48871 ISA_SET: AVX512F_128 48872 EXCEPTIONS: AVX512-E4 48873 REAL_OPCODE: Y 48874 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48875 PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 48876 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 48877 IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 48878 } 48879 48880 48881 # EMITTING VPSUBQ (VPSUBQ-256-1) 48882 { 48883 ICLASS: VPSUBQ 48884 CPL: 3 48885 CATEGORY: AVX512 48886 EXTENSION: AVX512EVEX 48887 ISA_SET: AVX512F_256 48888 EXCEPTIONS: AVX512-E4 48889 REAL_OPCODE: Y 48890 ATTRIBUTES: MASKOP_EVEX 48891 PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 48892 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 48893 IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 48894 } 48895 48896 { 48897 ICLASS: VPSUBQ 48898 CPL: 3 48899 CATEGORY: AVX512 48900 EXTENSION: AVX512EVEX 48901 ISA_SET: AVX512F_256 48902 EXCEPTIONS: AVX512-E4 48903 REAL_OPCODE: Y 48904 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 48905 PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 48906 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 48907 IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 48908 } 48909 48910 48911 # EMITTING VPSUBSB (VPSUBSB-128-1) 48912 { 48913 ICLASS: VPSUBSB 48914 CPL: 3 48915 CATEGORY: AVX512 48916 EXTENSION: AVX512EVEX 48917 ISA_SET: AVX512BW_128 48918 EXCEPTIONS: AVX512-E4 48919 REAL_OPCODE: Y 48920 ATTRIBUTES: MASKOP_EVEX 48921 PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 48922 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 48923 IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 48924 } 48925 48926 { 48927 ICLASS: VPSUBSB 48928 CPL: 3 48929 CATEGORY: AVX512 48930 EXTENSION: AVX512EVEX 48931 ISA_SET: AVX512BW_128 48932 EXCEPTIONS: AVX512-E4 48933 REAL_OPCODE: Y 48934 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 48935 PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 48936 OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 48937 IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 48938 } 48939 48940 48941 # EMITTING VPSUBSB (VPSUBSB-256-1) 48942 { 48943 ICLASS: VPSUBSB 48944 CPL: 3 48945 CATEGORY: AVX512 48946 EXTENSION: AVX512EVEX 48947 ISA_SET: AVX512BW_256 48948 EXCEPTIONS: AVX512-E4 48949 REAL_OPCODE: Y 48950 ATTRIBUTES: MASKOP_EVEX 48951 PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 48952 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 48953 IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 48954 } 48955 48956 { 48957 ICLASS: VPSUBSB 48958 CPL: 3 48959 CATEGORY: AVX512 48960 EXTENSION: AVX512EVEX 48961 ISA_SET: AVX512BW_256 48962 EXCEPTIONS: AVX512-E4 48963 REAL_OPCODE: Y 48964 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 48965 PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 48966 OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 48967 IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 48968 } 48969 48970 48971 # EMITTING VPSUBSB (VPSUBSB-512-1) 48972 { 48973 ICLASS: VPSUBSB 48974 CPL: 3 48975 CATEGORY: AVX512 48976 EXTENSION: AVX512EVEX 48977 ISA_SET: AVX512BW_512 48978 EXCEPTIONS: AVX512-E4 48979 REAL_OPCODE: Y 48980 ATTRIBUTES: MASKOP_EVEX 48981 PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 48982 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 48983 IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 48984 } 48985 48986 { 48987 ICLASS: VPSUBSB 48988 CPL: 3 48989 CATEGORY: AVX512 48990 EXTENSION: AVX512EVEX 48991 ISA_SET: AVX512BW_512 48992 EXCEPTIONS: AVX512-E4 48993 REAL_OPCODE: Y 48994 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 48995 PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 48996 OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 48997 IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 48998 } 48999 49000 49001 # EMITTING VPSUBSW (VPSUBSW-128-1) 49002 { 49003 ICLASS: VPSUBSW 49004 CPL: 3 49005 CATEGORY: AVX512 49006 EXTENSION: AVX512EVEX 49007 ISA_SET: AVX512BW_128 49008 EXCEPTIONS: AVX512-E4 49009 REAL_OPCODE: Y 49010 ATTRIBUTES: MASKOP_EVEX 49011 PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 49012 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 49013 IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 49014 } 49015 49016 { 49017 ICLASS: VPSUBSW 49018 CPL: 3 49019 CATEGORY: AVX512 49020 EXTENSION: AVX512EVEX 49021 ISA_SET: AVX512BW_128 49022 EXCEPTIONS: AVX512-E4 49023 REAL_OPCODE: Y 49024 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49025 PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 49026 OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 49027 IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 49028 } 49029 49030 49031 # EMITTING VPSUBSW (VPSUBSW-256-1) 49032 { 49033 ICLASS: VPSUBSW 49034 CPL: 3 49035 CATEGORY: AVX512 49036 EXTENSION: AVX512EVEX 49037 ISA_SET: AVX512BW_256 49038 EXCEPTIONS: AVX512-E4 49039 REAL_OPCODE: Y 49040 ATTRIBUTES: MASKOP_EVEX 49041 PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 49042 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 49043 IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 49044 } 49045 49046 { 49047 ICLASS: VPSUBSW 49048 CPL: 3 49049 CATEGORY: AVX512 49050 EXTENSION: AVX512EVEX 49051 ISA_SET: AVX512BW_256 49052 EXCEPTIONS: AVX512-E4 49053 REAL_OPCODE: Y 49054 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49055 PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 49056 OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 49057 IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 49058 } 49059 49060 49061 # EMITTING VPSUBSW (VPSUBSW-512-1) 49062 { 49063 ICLASS: VPSUBSW 49064 CPL: 3 49065 CATEGORY: AVX512 49066 EXTENSION: AVX512EVEX 49067 ISA_SET: AVX512BW_512 49068 EXCEPTIONS: AVX512-E4 49069 REAL_OPCODE: Y 49070 ATTRIBUTES: MASKOP_EVEX 49071 PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 49072 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 49073 IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 49074 } 49075 49076 { 49077 ICLASS: VPSUBSW 49078 CPL: 3 49079 CATEGORY: AVX512 49080 EXTENSION: AVX512EVEX 49081 ISA_SET: AVX512BW_512 49082 EXCEPTIONS: AVX512-E4 49083 REAL_OPCODE: Y 49084 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49085 PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 49086 OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 49087 IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 49088 } 49089 49090 49091 # EMITTING VPSUBUSB (VPSUBUSB-128-1) 49092 { 49093 ICLASS: VPSUBUSB 49094 CPL: 3 49095 CATEGORY: AVX512 49096 EXTENSION: AVX512EVEX 49097 ISA_SET: AVX512BW_128 49098 EXCEPTIONS: AVX512-E4 49099 REAL_OPCODE: Y 49100 ATTRIBUTES: MASKOP_EVEX 49101 PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 49102 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 49103 IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 49104 } 49105 49106 { 49107 ICLASS: VPSUBUSB 49108 CPL: 3 49109 CATEGORY: AVX512 49110 EXTENSION: AVX512EVEX 49111 ISA_SET: AVX512BW_128 49112 EXCEPTIONS: AVX512-E4 49113 REAL_OPCODE: Y 49114 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49115 PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 49116 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 49117 IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 49118 } 49119 49120 49121 # EMITTING VPSUBUSB (VPSUBUSB-256-1) 49122 { 49123 ICLASS: VPSUBUSB 49124 CPL: 3 49125 CATEGORY: AVX512 49126 EXTENSION: AVX512EVEX 49127 ISA_SET: AVX512BW_256 49128 EXCEPTIONS: AVX512-E4 49129 REAL_OPCODE: Y 49130 ATTRIBUTES: MASKOP_EVEX 49131 PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 49132 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 49133 IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 49134 } 49135 49136 { 49137 ICLASS: VPSUBUSB 49138 CPL: 3 49139 CATEGORY: AVX512 49140 EXTENSION: AVX512EVEX 49141 ISA_SET: AVX512BW_256 49142 EXCEPTIONS: AVX512-E4 49143 REAL_OPCODE: Y 49144 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49145 PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 49146 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 49147 IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 49148 } 49149 49150 49151 # EMITTING VPSUBUSB (VPSUBUSB-512-1) 49152 { 49153 ICLASS: VPSUBUSB 49154 CPL: 3 49155 CATEGORY: AVX512 49156 EXTENSION: AVX512EVEX 49157 ISA_SET: AVX512BW_512 49158 EXCEPTIONS: AVX512-E4 49159 REAL_OPCODE: Y 49160 ATTRIBUTES: MASKOP_EVEX 49161 PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 49162 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 49163 IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 49164 } 49165 49166 { 49167 ICLASS: VPSUBUSB 49168 CPL: 3 49169 CATEGORY: AVX512 49170 EXTENSION: AVX512EVEX 49171 ISA_SET: AVX512BW_512 49172 EXCEPTIONS: AVX512-E4 49173 REAL_OPCODE: Y 49174 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49175 PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 49176 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 49177 IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 49178 } 49179 49180 49181 # EMITTING VPSUBUSW (VPSUBUSW-128-1) 49182 { 49183 ICLASS: VPSUBUSW 49184 CPL: 3 49185 CATEGORY: AVX512 49186 EXTENSION: AVX512EVEX 49187 ISA_SET: AVX512BW_128 49188 EXCEPTIONS: AVX512-E4 49189 REAL_OPCODE: Y 49190 ATTRIBUTES: MASKOP_EVEX 49191 PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 49192 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 49193 IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 49194 } 49195 49196 { 49197 ICLASS: VPSUBUSW 49198 CPL: 3 49199 CATEGORY: AVX512 49200 EXTENSION: AVX512EVEX 49201 ISA_SET: AVX512BW_128 49202 EXCEPTIONS: AVX512-E4 49203 REAL_OPCODE: Y 49204 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49205 PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 49206 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 49207 IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 49208 } 49209 49210 49211 # EMITTING VPSUBUSW (VPSUBUSW-256-1) 49212 { 49213 ICLASS: VPSUBUSW 49214 CPL: 3 49215 CATEGORY: AVX512 49216 EXTENSION: AVX512EVEX 49217 ISA_SET: AVX512BW_256 49218 EXCEPTIONS: AVX512-E4 49219 REAL_OPCODE: Y 49220 ATTRIBUTES: MASKOP_EVEX 49221 PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 49222 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 49223 IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 49224 } 49225 49226 { 49227 ICLASS: VPSUBUSW 49228 CPL: 3 49229 CATEGORY: AVX512 49230 EXTENSION: AVX512EVEX 49231 ISA_SET: AVX512BW_256 49232 EXCEPTIONS: AVX512-E4 49233 REAL_OPCODE: Y 49234 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49235 PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 49236 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 49237 IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 49238 } 49239 49240 49241 # EMITTING VPSUBUSW (VPSUBUSW-512-1) 49242 { 49243 ICLASS: VPSUBUSW 49244 CPL: 3 49245 CATEGORY: AVX512 49246 EXTENSION: AVX512EVEX 49247 ISA_SET: AVX512BW_512 49248 EXCEPTIONS: AVX512-E4 49249 REAL_OPCODE: Y 49250 ATTRIBUTES: MASKOP_EVEX 49251 PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 49252 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 49253 IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 49254 } 49255 49256 { 49257 ICLASS: VPSUBUSW 49258 CPL: 3 49259 CATEGORY: AVX512 49260 EXTENSION: AVX512EVEX 49261 ISA_SET: AVX512BW_512 49262 EXCEPTIONS: AVX512-E4 49263 REAL_OPCODE: Y 49264 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49265 PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 49266 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 49267 IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 49268 } 49269 49270 49271 # EMITTING VPSUBW (VPSUBW-128-1) 49272 { 49273 ICLASS: VPSUBW 49274 CPL: 3 49275 CATEGORY: AVX512 49276 EXTENSION: AVX512EVEX 49277 ISA_SET: AVX512BW_128 49278 EXCEPTIONS: AVX512-E4 49279 REAL_OPCODE: Y 49280 ATTRIBUTES: MASKOP_EVEX 49281 PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 49282 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 49283 IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 49284 } 49285 49286 { 49287 ICLASS: VPSUBW 49288 CPL: 3 49289 CATEGORY: AVX512 49290 EXTENSION: AVX512EVEX 49291 ISA_SET: AVX512BW_128 49292 EXCEPTIONS: AVX512-E4 49293 REAL_OPCODE: Y 49294 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49295 PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 49296 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 49297 IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 49298 } 49299 49300 49301 # EMITTING VPSUBW (VPSUBW-256-1) 49302 { 49303 ICLASS: VPSUBW 49304 CPL: 3 49305 CATEGORY: AVX512 49306 EXTENSION: AVX512EVEX 49307 ISA_SET: AVX512BW_256 49308 EXCEPTIONS: AVX512-E4 49309 REAL_OPCODE: Y 49310 ATTRIBUTES: MASKOP_EVEX 49311 PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 49312 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 49313 IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 49314 } 49315 49316 { 49317 ICLASS: VPSUBW 49318 CPL: 3 49319 CATEGORY: AVX512 49320 EXTENSION: AVX512EVEX 49321 ISA_SET: AVX512BW_256 49322 EXCEPTIONS: AVX512-E4 49323 REAL_OPCODE: Y 49324 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49325 PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 49326 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 49327 IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 49328 } 49329 49330 49331 # EMITTING VPSUBW (VPSUBW-512-1) 49332 { 49333 ICLASS: VPSUBW 49334 CPL: 3 49335 CATEGORY: AVX512 49336 EXTENSION: AVX512EVEX 49337 ISA_SET: AVX512BW_512 49338 EXCEPTIONS: AVX512-E4 49339 REAL_OPCODE: Y 49340 ATTRIBUTES: MASKOP_EVEX 49341 PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 49342 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 49343 IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 49344 } 49345 49346 { 49347 ICLASS: VPSUBW 49348 CPL: 3 49349 CATEGORY: AVX512 49350 EXTENSION: AVX512EVEX 49351 ISA_SET: AVX512BW_512 49352 EXCEPTIONS: AVX512-E4 49353 REAL_OPCODE: Y 49354 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49355 PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 49356 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 49357 IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 49358 } 49359 49360 49361 # EMITTING VPTERNLOGD (VPTERNLOGD-128-1) 49362 { 49363 ICLASS: VPTERNLOGD 49364 CPL: 3 49365 CATEGORY: LOGICAL 49366 EXTENSION: AVX512EVEX 49367 ISA_SET: AVX512F_128 49368 EXCEPTIONS: AVX512-E4 49369 REAL_OPCODE: Y 49370 ATTRIBUTES: MASKOP_EVEX 49371 PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 49372 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b 49373 IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 49374 } 49375 49376 { 49377 ICLASS: VPTERNLOGD 49378 CPL: 3 49379 CATEGORY: LOGICAL 49380 EXTENSION: AVX512EVEX 49381 ISA_SET: AVX512F_128 49382 EXCEPTIONS: AVX512-E4 49383 REAL_OPCODE: Y 49384 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49385 PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 49386 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 49387 IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 49388 } 49389 49390 49391 # EMITTING VPTERNLOGD (VPTERNLOGD-256-1) 49392 { 49393 ICLASS: VPTERNLOGD 49394 CPL: 3 49395 CATEGORY: LOGICAL 49396 EXTENSION: AVX512EVEX 49397 ISA_SET: AVX512F_256 49398 EXCEPTIONS: AVX512-E4 49399 REAL_OPCODE: Y 49400 ATTRIBUTES: MASKOP_EVEX 49401 PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 49402 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b 49403 IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 49404 } 49405 49406 { 49407 ICLASS: VPTERNLOGD 49408 CPL: 3 49409 CATEGORY: LOGICAL 49410 EXTENSION: AVX512EVEX 49411 ISA_SET: AVX512F_256 49412 EXCEPTIONS: AVX512-E4 49413 REAL_OPCODE: Y 49414 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49415 PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 49416 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 49417 IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 49418 } 49419 49420 49421 # EMITTING VPTERNLOGQ (VPTERNLOGQ-128-1) 49422 { 49423 ICLASS: VPTERNLOGQ 49424 CPL: 3 49425 CATEGORY: LOGICAL 49426 EXTENSION: AVX512EVEX 49427 ISA_SET: AVX512F_128 49428 EXCEPTIONS: AVX512-E4 49429 REAL_OPCODE: Y 49430 ATTRIBUTES: MASKOP_EVEX 49431 PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 49432 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b 49433 IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 49434 } 49435 49436 { 49437 ICLASS: VPTERNLOGQ 49438 CPL: 3 49439 CATEGORY: LOGICAL 49440 EXTENSION: AVX512EVEX 49441 ISA_SET: AVX512F_128 49442 EXCEPTIONS: AVX512-E4 49443 REAL_OPCODE: Y 49444 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49445 PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 49446 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 49447 IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 49448 } 49449 49450 49451 # EMITTING VPTERNLOGQ (VPTERNLOGQ-256-1) 49452 { 49453 ICLASS: VPTERNLOGQ 49454 CPL: 3 49455 CATEGORY: LOGICAL 49456 EXTENSION: AVX512EVEX 49457 ISA_SET: AVX512F_256 49458 EXCEPTIONS: AVX512-E4 49459 REAL_OPCODE: Y 49460 ATTRIBUTES: MASKOP_EVEX 49461 PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 49462 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b 49463 IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 49464 } 49465 49466 { 49467 ICLASS: VPTERNLOGQ 49468 CPL: 3 49469 CATEGORY: LOGICAL 49470 EXTENSION: AVX512EVEX 49471 ISA_SET: AVX512F_256 49472 EXCEPTIONS: AVX512-E4 49473 REAL_OPCODE: Y 49474 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49475 PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 49476 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 49477 IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 49478 } 49479 49480 49481 # EMITTING VPTESTMB (VPTESTMB-128-1) 49482 { 49483 ICLASS: VPTESTMB 49484 CPL: 3 49485 CATEGORY: LOGICAL 49486 EXTENSION: AVX512EVEX 49487 ISA_SET: AVX512BW_128 49488 EXCEPTIONS: AVX512-E4 49489 REAL_OPCODE: Y 49490 ATTRIBUTES: MASKOP_EVEX 49491 PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 49492 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 49493 IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 49494 } 49495 49496 { 49497 ICLASS: VPTESTMB 49498 CPL: 3 49499 CATEGORY: LOGICAL 49500 EXTENSION: AVX512EVEX 49501 ISA_SET: AVX512BW_128 49502 EXCEPTIONS: AVX512-E4 49503 REAL_OPCODE: Y 49504 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49505 PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 49506 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 49507 IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 49508 } 49509 49510 49511 # EMITTING VPTESTMB (VPTESTMB-256-1) 49512 { 49513 ICLASS: VPTESTMB 49514 CPL: 3 49515 CATEGORY: LOGICAL 49516 EXTENSION: AVX512EVEX 49517 ISA_SET: AVX512BW_256 49518 EXCEPTIONS: AVX512-E4 49519 REAL_OPCODE: Y 49520 ATTRIBUTES: MASKOP_EVEX 49521 PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 49522 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 49523 IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 49524 } 49525 49526 { 49527 ICLASS: VPTESTMB 49528 CPL: 3 49529 CATEGORY: LOGICAL 49530 EXTENSION: AVX512EVEX 49531 ISA_SET: AVX512BW_256 49532 EXCEPTIONS: AVX512-E4 49533 REAL_OPCODE: Y 49534 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49535 PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 49536 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 49537 IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 49538 } 49539 49540 49541 # EMITTING VPTESTMB (VPTESTMB-512-1) 49542 { 49543 ICLASS: VPTESTMB 49544 CPL: 3 49545 CATEGORY: LOGICAL 49546 EXTENSION: AVX512EVEX 49547 ISA_SET: AVX512BW_512 49548 EXCEPTIONS: AVX512-E4 49549 REAL_OPCODE: Y 49550 ATTRIBUTES: MASKOP_EVEX 49551 PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 49552 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 49553 IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 49554 } 49555 49556 { 49557 ICLASS: VPTESTMB 49558 CPL: 3 49559 CATEGORY: LOGICAL 49560 EXTENSION: AVX512EVEX 49561 ISA_SET: AVX512BW_512 49562 EXCEPTIONS: AVX512-E4 49563 REAL_OPCODE: Y 49564 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49565 PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 49566 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 49567 IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 49568 } 49569 49570 49571 # EMITTING VPTESTMD (VPTESTMD-128-1) 49572 { 49573 ICLASS: VPTESTMD 49574 CPL: 3 49575 CATEGORY: LOGICAL 49576 EXTENSION: AVX512EVEX 49577 ISA_SET: AVX512F_128 49578 EXCEPTIONS: AVX512-E4 49579 REAL_OPCODE: Y 49580 ATTRIBUTES: MASKOP_EVEX 49581 PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 49582 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 49583 IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 49584 } 49585 49586 { 49587 ICLASS: VPTESTMD 49588 CPL: 3 49589 CATEGORY: LOGICAL 49590 EXTENSION: AVX512EVEX 49591 ISA_SET: AVX512F_128 49592 EXCEPTIONS: AVX512-E4 49593 REAL_OPCODE: Y 49594 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49595 PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 49596 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 49597 IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 49598 } 49599 49600 49601 # EMITTING VPTESTMD (VPTESTMD-256-1) 49602 { 49603 ICLASS: VPTESTMD 49604 CPL: 3 49605 CATEGORY: LOGICAL 49606 EXTENSION: AVX512EVEX 49607 ISA_SET: AVX512F_256 49608 EXCEPTIONS: AVX512-E4 49609 REAL_OPCODE: Y 49610 ATTRIBUTES: MASKOP_EVEX 49611 PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 49612 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 49613 IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 49614 } 49615 49616 { 49617 ICLASS: VPTESTMD 49618 CPL: 3 49619 CATEGORY: LOGICAL 49620 EXTENSION: AVX512EVEX 49621 ISA_SET: AVX512F_256 49622 EXCEPTIONS: AVX512-E4 49623 REAL_OPCODE: Y 49624 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49625 PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 49626 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 49627 IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 49628 } 49629 49630 49631 # EMITTING VPTESTMQ (VPTESTMQ-128-1) 49632 { 49633 ICLASS: VPTESTMQ 49634 CPL: 3 49635 CATEGORY: LOGICAL 49636 EXTENSION: AVX512EVEX 49637 ISA_SET: AVX512F_128 49638 EXCEPTIONS: AVX512-E4 49639 REAL_OPCODE: Y 49640 ATTRIBUTES: MASKOP_EVEX 49641 PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 49642 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 49643 IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 49644 } 49645 49646 { 49647 ICLASS: VPTESTMQ 49648 CPL: 3 49649 CATEGORY: LOGICAL 49650 EXTENSION: AVX512EVEX 49651 ISA_SET: AVX512F_128 49652 EXCEPTIONS: AVX512-E4 49653 REAL_OPCODE: Y 49654 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49655 PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 49656 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 49657 IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 49658 } 49659 49660 49661 # EMITTING VPTESTMQ (VPTESTMQ-256-1) 49662 { 49663 ICLASS: VPTESTMQ 49664 CPL: 3 49665 CATEGORY: LOGICAL 49666 EXTENSION: AVX512EVEX 49667 ISA_SET: AVX512F_256 49668 EXCEPTIONS: AVX512-E4 49669 REAL_OPCODE: Y 49670 ATTRIBUTES: MASKOP_EVEX 49671 PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 49672 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 49673 IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 49674 } 49675 49676 { 49677 ICLASS: VPTESTMQ 49678 CPL: 3 49679 CATEGORY: LOGICAL 49680 EXTENSION: AVX512EVEX 49681 ISA_SET: AVX512F_256 49682 EXCEPTIONS: AVX512-E4 49683 REAL_OPCODE: Y 49684 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49685 PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 49686 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 49687 IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 49688 } 49689 49690 49691 # EMITTING VPTESTMW (VPTESTMW-128-1) 49692 { 49693 ICLASS: VPTESTMW 49694 CPL: 3 49695 CATEGORY: LOGICAL 49696 EXTENSION: AVX512EVEX 49697 ISA_SET: AVX512BW_128 49698 EXCEPTIONS: AVX512-E4 49699 REAL_OPCODE: Y 49700 ATTRIBUTES: MASKOP_EVEX 49701 PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 49702 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 49703 IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 49704 } 49705 49706 { 49707 ICLASS: VPTESTMW 49708 CPL: 3 49709 CATEGORY: LOGICAL 49710 EXTENSION: AVX512EVEX 49711 ISA_SET: AVX512BW_128 49712 EXCEPTIONS: AVX512-E4 49713 REAL_OPCODE: Y 49714 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49715 PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 49716 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 49717 IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 49718 } 49719 49720 49721 # EMITTING VPTESTMW (VPTESTMW-256-1) 49722 { 49723 ICLASS: VPTESTMW 49724 CPL: 3 49725 CATEGORY: LOGICAL 49726 EXTENSION: AVX512EVEX 49727 ISA_SET: AVX512BW_256 49728 EXCEPTIONS: AVX512-E4 49729 REAL_OPCODE: Y 49730 ATTRIBUTES: MASKOP_EVEX 49731 PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 49732 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 49733 IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 49734 } 49735 49736 { 49737 ICLASS: VPTESTMW 49738 CPL: 3 49739 CATEGORY: LOGICAL 49740 EXTENSION: AVX512EVEX 49741 ISA_SET: AVX512BW_256 49742 EXCEPTIONS: AVX512-E4 49743 REAL_OPCODE: Y 49744 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49745 PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 49746 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 49747 IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 49748 } 49749 49750 49751 # EMITTING VPTESTMW (VPTESTMW-512-1) 49752 { 49753 ICLASS: VPTESTMW 49754 CPL: 3 49755 CATEGORY: LOGICAL 49756 EXTENSION: AVX512EVEX 49757 ISA_SET: AVX512BW_512 49758 EXCEPTIONS: AVX512-E4 49759 REAL_OPCODE: Y 49760 ATTRIBUTES: MASKOP_EVEX 49761 PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 49762 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 49763 IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 49764 } 49765 49766 { 49767 ICLASS: VPTESTMW 49768 CPL: 3 49769 CATEGORY: LOGICAL 49770 EXTENSION: AVX512EVEX 49771 ISA_SET: AVX512BW_512 49772 EXCEPTIONS: AVX512-E4 49773 REAL_OPCODE: Y 49774 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49775 PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 49776 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 49777 IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 49778 } 49779 49780 49781 # EMITTING VPTESTNMB (VPTESTNMB-128-1) 49782 { 49783 ICLASS: VPTESTNMB 49784 CPL: 3 49785 CATEGORY: LOGICAL 49786 EXTENSION: AVX512EVEX 49787 ISA_SET: AVX512BW_128 49788 EXCEPTIONS: AVX512-E4 49789 REAL_OPCODE: Y 49790 ATTRIBUTES: MASKOP_EVEX 49791 PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 49792 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 49793 IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 49794 } 49795 49796 { 49797 ICLASS: VPTESTNMB 49798 CPL: 3 49799 CATEGORY: LOGICAL 49800 EXTENSION: AVX512EVEX 49801 ISA_SET: AVX512BW_128 49802 EXCEPTIONS: AVX512-E4 49803 REAL_OPCODE: Y 49804 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49805 PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 49806 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 49807 IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 49808 } 49809 49810 49811 # EMITTING VPTESTNMB (VPTESTNMB-256-1) 49812 { 49813 ICLASS: VPTESTNMB 49814 CPL: 3 49815 CATEGORY: LOGICAL 49816 EXTENSION: AVX512EVEX 49817 ISA_SET: AVX512BW_256 49818 EXCEPTIONS: AVX512-E4 49819 REAL_OPCODE: Y 49820 ATTRIBUTES: MASKOP_EVEX 49821 PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 49822 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 49823 IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 49824 } 49825 49826 { 49827 ICLASS: VPTESTNMB 49828 CPL: 3 49829 CATEGORY: LOGICAL 49830 EXTENSION: AVX512EVEX 49831 ISA_SET: AVX512BW_256 49832 EXCEPTIONS: AVX512-E4 49833 REAL_OPCODE: Y 49834 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49835 PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 49836 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 49837 IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 49838 } 49839 49840 49841 # EMITTING VPTESTNMB (VPTESTNMB-512-1) 49842 { 49843 ICLASS: VPTESTNMB 49844 CPL: 3 49845 CATEGORY: LOGICAL 49846 EXTENSION: AVX512EVEX 49847 ISA_SET: AVX512BW_512 49848 EXCEPTIONS: AVX512-E4 49849 REAL_OPCODE: Y 49850 ATTRIBUTES: MASKOP_EVEX 49851 PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 49852 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 49853 IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 49854 } 49855 49856 { 49857 ICLASS: VPTESTNMB 49858 CPL: 3 49859 CATEGORY: LOGICAL 49860 EXTENSION: AVX512EVEX 49861 ISA_SET: AVX512BW_512 49862 EXCEPTIONS: AVX512-E4 49863 REAL_OPCODE: Y 49864 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 49865 PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 49866 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 49867 IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 49868 } 49869 49870 49871 # EMITTING VPTESTNMD (VPTESTNMD-128-1) 49872 { 49873 ICLASS: VPTESTNMD 49874 CPL: 3 49875 CATEGORY: LOGICAL 49876 EXTENSION: AVX512EVEX 49877 ISA_SET: AVX512F_128 49878 EXCEPTIONS: AVX512-E4 49879 REAL_OPCODE: Y 49880 ATTRIBUTES: MASKOP_EVEX 49881 PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 49882 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 49883 IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 49884 } 49885 49886 { 49887 ICLASS: VPTESTNMD 49888 CPL: 3 49889 CATEGORY: LOGICAL 49890 EXTENSION: AVX512EVEX 49891 ISA_SET: AVX512F_128 49892 EXCEPTIONS: AVX512-E4 49893 REAL_OPCODE: Y 49894 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49895 PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 49896 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 49897 IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 49898 } 49899 49900 49901 # EMITTING VPTESTNMD (VPTESTNMD-256-1) 49902 { 49903 ICLASS: VPTESTNMD 49904 CPL: 3 49905 CATEGORY: LOGICAL 49906 EXTENSION: AVX512EVEX 49907 ISA_SET: AVX512F_256 49908 EXCEPTIONS: AVX512-E4 49909 REAL_OPCODE: Y 49910 ATTRIBUTES: MASKOP_EVEX 49911 PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 49912 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 49913 IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 49914 } 49915 49916 { 49917 ICLASS: VPTESTNMD 49918 CPL: 3 49919 CATEGORY: LOGICAL 49920 EXTENSION: AVX512EVEX 49921 ISA_SET: AVX512F_256 49922 EXCEPTIONS: AVX512-E4 49923 REAL_OPCODE: Y 49924 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49925 PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() 49926 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 49927 IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 49928 } 49929 49930 49931 # EMITTING VPTESTNMQ (VPTESTNMQ-128-1) 49932 { 49933 ICLASS: VPTESTNMQ 49934 CPL: 3 49935 CATEGORY: LOGICAL 49936 EXTENSION: AVX512EVEX 49937 ISA_SET: AVX512F_128 49938 EXCEPTIONS: AVX512-E4 49939 REAL_OPCODE: Y 49940 ATTRIBUTES: MASKOP_EVEX 49941 PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 49942 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 49943 IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 49944 } 49945 49946 { 49947 ICLASS: VPTESTNMQ 49948 CPL: 3 49949 CATEGORY: LOGICAL 49950 EXTENSION: AVX512EVEX 49951 ISA_SET: AVX512F_128 49952 EXCEPTIONS: AVX512-E4 49953 REAL_OPCODE: Y 49954 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49955 PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 49956 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 49957 IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 49958 } 49959 49960 49961 # EMITTING VPTESTNMQ (VPTESTNMQ-256-1) 49962 { 49963 ICLASS: VPTESTNMQ 49964 CPL: 3 49965 CATEGORY: LOGICAL 49966 EXTENSION: AVX512EVEX 49967 ISA_SET: AVX512F_256 49968 EXCEPTIONS: AVX512-E4 49969 REAL_OPCODE: Y 49970 ATTRIBUTES: MASKOP_EVEX 49971 PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 49972 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 49973 IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 49974 } 49975 49976 { 49977 ICLASS: VPTESTNMQ 49978 CPL: 3 49979 CATEGORY: LOGICAL 49980 EXTENSION: AVX512EVEX 49981 ISA_SET: AVX512F_256 49982 EXCEPTIONS: AVX512-E4 49983 REAL_OPCODE: Y 49984 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 49985 PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() 49986 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 49987 IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 49988 } 49989 49990 49991 # EMITTING VPTESTNMW (VPTESTNMW-128-1) 49992 { 49993 ICLASS: VPTESTNMW 49994 CPL: 3 49995 CATEGORY: LOGICAL 49996 EXTENSION: AVX512EVEX 49997 ISA_SET: AVX512BW_128 49998 EXCEPTIONS: AVX512-E4 49999 REAL_OPCODE: Y 50000 ATTRIBUTES: MASKOP_EVEX 50001 PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 50002 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 50003 IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 50004 } 50005 50006 { 50007 ICLASS: VPTESTNMW 50008 CPL: 3 50009 CATEGORY: LOGICAL 50010 EXTENSION: AVX512EVEX 50011 ISA_SET: AVX512BW_128 50012 EXCEPTIONS: AVX512-E4 50013 REAL_OPCODE: Y 50014 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50015 PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 50016 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 50017 IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 50018 } 50019 50020 50021 # EMITTING VPTESTNMW (VPTESTNMW-256-1) 50022 { 50023 ICLASS: VPTESTNMW 50024 CPL: 3 50025 CATEGORY: LOGICAL 50026 EXTENSION: AVX512EVEX 50027 ISA_SET: AVX512BW_256 50028 EXCEPTIONS: AVX512-E4 50029 REAL_OPCODE: Y 50030 ATTRIBUTES: MASKOP_EVEX 50031 PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 50032 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 50033 IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 50034 } 50035 50036 { 50037 ICLASS: VPTESTNMW 50038 CPL: 3 50039 CATEGORY: LOGICAL 50040 EXTENSION: AVX512EVEX 50041 ISA_SET: AVX512BW_256 50042 EXCEPTIONS: AVX512-E4 50043 REAL_OPCODE: Y 50044 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50045 PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 50046 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 50047 IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 50048 } 50049 50050 50051 # EMITTING VPTESTNMW (VPTESTNMW-512-1) 50052 { 50053 ICLASS: VPTESTNMW 50054 CPL: 3 50055 CATEGORY: LOGICAL 50056 EXTENSION: AVX512EVEX 50057 ISA_SET: AVX512BW_512 50058 EXCEPTIONS: AVX512-E4 50059 REAL_OPCODE: Y 50060 ATTRIBUTES: MASKOP_EVEX 50061 PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 50062 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 50063 IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 50064 } 50065 50066 { 50067 ICLASS: VPTESTNMW 50068 CPL: 3 50069 CATEGORY: LOGICAL 50070 EXTENSION: AVX512EVEX 50071 ISA_SET: AVX512BW_512 50072 EXCEPTIONS: AVX512-E4 50073 REAL_OPCODE: Y 50074 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 50075 PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() 50076 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 50077 IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 50078 } 50079 50080 50081 # EMITTING VPUNPCKHBW (VPUNPCKHBW-128-1) 50082 { 50083 ICLASS: VPUNPCKHBW 50084 CPL: 3 50085 CATEGORY: AVX512 50086 EXTENSION: AVX512EVEX 50087 ISA_SET: AVX512BW_128 50088 EXCEPTIONS: AVX512-E4NF 50089 REAL_OPCODE: Y 50090 ATTRIBUTES: MASKOP_EVEX 50091 PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 50092 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 50093 IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 50094 } 50095 50096 { 50097 ICLASS: VPUNPCKHBW 50098 CPL: 3 50099 CATEGORY: AVX512 50100 EXTENSION: AVX512EVEX 50101 ISA_SET: AVX512BW_128 50102 EXCEPTIONS: AVX512-E4NF 50103 REAL_OPCODE: Y 50104 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50105 PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 50106 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 50107 IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 50108 } 50109 50110 50111 # EMITTING VPUNPCKHBW (VPUNPCKHBW-256-1) 50112 { 50113 ICLASS: VPUNPCKHBW 50114 CPL: 3 50115 CATEGORY: AVX512 50116 EXTENSION: AVX512EVEX 50117 ISA_SET: AVX512BW_256 50118 EXCEPTIONS: AVX512-E4NF 50119 REAL_OPCODE: Y 50120 ATTRIBUTES: MASKOP_EVEX 50121 PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 50122 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 50123 IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 50124 } 50125 50126 { 50127 ICLASS: VPUNPCKHBW 50128 CPL: 3 50129 CATEGORY: AVX512 50130 EXTENSION: AVX512EVEX 50131 ISA_SET: AVX512BW_256 50132 EXCEPTIONS: AVX512-E4NF 50133 REAL_OPCODE: Y 50134 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50135 PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 50136 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 50137 IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 50138 } 50139 50140 50141 # EMITTING VPUNPCKHBW (VPUNPCKHBW-512-1) 50142 { 50143 ICLASS: VPUNPCKHBW 50144 CPL: 3 50145 CATEGORY: AVX512 50146 EXTENSION: AVX512EVEX 50147 ISA_SET: AVX512BW_512 50148 EXCEPTIONS: AVX512-E4NF 50149 REAL_OPCODE: Y 50150 ATTRIBUTES: MASKOP_EVEX 50151 PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 50152 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 50153 IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 50154 } 50155 50156 { 50157 ICLASS: VPUNPCKHBW 50158 CPL: 3 50159 CATEGORY: AVX512 50160 EXTENSION: AVX512EVEX 50161 ISA_SET: AVX512BW_512 50162 EXCEPTIONS: AVX512-E4NF 50163 REAL_OPCODE: Y 50164 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50165 PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 50166 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 50167 IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 50168 } 50169 50170 50171 # EMITTING VPUNPCKHDQ (VPUNPCKHDQ-128-1) 50172 { 50173 ICLASS: VPUNPCKHDQ 50174 CPL: 3 50175 CATEGORY: AVX512 50176 EXTENSION: AVX512EVEX 50177 ISA_SET: AVX512F_128 50178 EXCEPTIONS: AVX512-E4NF 50179 REAL_OPCODE: Y 50180 ATTRIBUTES: MASKOP_EVEX 50181 PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 50182 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 50183 IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 50184 } 50185 50186 { 50187 ICLASS: VPUNPCKHDQ 50188 CPL: 3 50189 CATEGORY: AVX512 50190 EXTENSION: AVX512EVEX 50191 ISA_SET: AVX512F_128 50192 EXCEPTIONS: AVX512-E4NF 50193 REAL_OPCODE: Y 50194 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 50195 PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 50196 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 50197 IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 50198 } 50199 50200 50201 # EMITTING VPUNPCKHDQ (VPUNPCKHDQ-256-1) 50202 { 50203 ICLASS: VPUNPCKHDQ 50204 CPL: 3 50205 CATEGORY: AVX512 50206 EXTENSION: AVX512EVEX 50207 ISA_SET: AVX512F_256 50208 EXCEPTIONS: AVX512-E4NF 50209 REAL_OPCODE: Y 50210 ATTRIBUTES: MASKOP_EVEX 50211 PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 50212 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 50213 IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 50214 } 50215 50216 { 50217 ICLASS: VPUNPCKHDQ 50218 CPL: 3 50219 CATEGORY: AVX512 50220 EXTENSION: AVX512EVEX 50221 ISA_SET: AVX512F_256 50222 EXCEPTIONS: AVX512-E4NF 50223 REAL_OPCODE: Y 50224 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 50225 PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 50226 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 50227 IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 50228 } 50229 50230 50231 # EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-128-1) 50232 { 50233 ICLASS: VPUNPCKHQDQ 50234 CPL: 3 50235 CATEGORY: AVX512 50236 EXTENSION: AVX512EVEX 50237 ISA_SET: AVX512F_128 50238 EXCEPTIONS: AVX512-E4NF 50239 REAL_OPCODE: Y 50240 ATTRIBUTES: MASKOP_EVEX 50241 PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 50242 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 50243 IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 50244 } 50245 50246 { 50247 ICLASS: VPUNPCKHQDQ 50248 CPL: 3 50249 CATEGORY: AVX512 50250 EXTENSION: AVX512EVEX 50251 ISA_SET: AVX512F_128 50252 EXCEPTIONS: AVX512-E4NF 50253 REAL_OPCODE: Y 50254 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 50255 PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 50256 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 50257 IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 50258 } 50259 50260 50261 # EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-256-1) 50262 { 50263 ICLASS: VPUNPCKHQDQ 50264 CPL: 3 50265 CATEGORY: AVX512 50266 EXTENSION: AVX512EVEX 50267 ISA_SET: AVX512F_256 50268 EXCEPTIONS: AVX512-E4NF 50269 REAL_OPCODE: Y 50270 ATTRIBUTES: MASKOP_EVEX 50271 PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 50272 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 50273 IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 50274 } 50275 50276 { 50277 ICLASS: VPUNPCKHQDQ 50278 CPL: 3 50279 CATEGORY: AVX512 50280 EXTENSION: AVX512EVEX 50281 ISA_SET: AVX512F_256 50282 EXCEPTIONS: AVX512-E4NF 50283 REAL_OPCODE: Y 50284 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 50285 PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 50286 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 50287 IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 50288 } 50289 50290 50291 # EMITTING VPUNPCKHWD (VPUNPCKHWD-128-1) 50292 { 50293 ICLASS: VPUNPCKHWD 50294 CPL: 3 50295 CATEGORY: AVX512 50296 EXTENSION: AVX512EVEX 50297 ISA_SET: AVX512BW_128 50298 EXCEPTIONS: AVX512-E4NF 50299 REAL_OPCODE: Y 50300 ATTRIBUTES: MASKOP_EVEX 50301 PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 50302 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 50303 IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 50304 } 50305 50306 { 50307 ICLASS: VPUNPCKHWD 50308 CPL: 3 50309 CATEGORY: AVX512 50310 EXTENSION: AVX512EVEX 50311 ISA_SET: AVX512BW_128 50312 EXCEPTIONS: AVX512-E4NF 50313 REAL_OPCODE: Y 50314 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50315 PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 50316 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 50317 IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 50318 } 50319 50320 50321 # EMITTING VPUNPCKHWD (VPUNPCKHWD-256-1) 50322 { 50323 ICLASS: VPUNPCKHWD 50324 CPL: 3 50325 CATEGORY: AVX512 50326 EXTENSION: AVX512EVEX 50327 ISA_SET: AVX512BW_256 50328 EXCEPTIONS: AVX512-E4NF 50329 REAL_OPCODE: Y 50330 ATTRIBUTES: MASKOP_EVEX 50331 PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 50332 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 50333 IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 50334 } 50335 50336 { 50337 ICLASS: VPUNPCKHWD 50338 CPL: 3 50339 CATEGORY: AVX512 50340 EXTENSION: AVX512EVEX 50341 ISA_SET: AVX512BW_256 50342 EXCEPTIONS: AVX512-E4NF 50343 REAL_OPCODE: Y 50344 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50345 PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 50346 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 50347 IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 50348 } 50349 50350 50351 # EMITTING VPUNPCKHWD (VPUNPCKHWD-512-1) 50352 { 50353 ICLASS: VPUNPCKHWD 50354 CPL: 3 50355 CATEGORY: AVX512 50356 EXTENSION: AVX512EVEX 50357 ISA_SET: AVX512BW_512 50358 EXCEPTIONS: AVX512-E4NF 50359 REAL_OPCODE: Y 50360 ATTRIBUTES: MASKOP_EVEX 50361 PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 50362 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 50363 IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 50364 } 50365 50366 { 50367 ICLASS: VPUNPCKHWD 50368 CPL: 3 50369 CATEGORY: AVX512 50370 EXTENSION: AVX512EVEX 50371 ISA_SET: AVX512BW_512 50372 EXCEPTIONS: AVX512-E4NF 50373 REAL_OPCODE: Y 50374 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50375 PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 50376 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 50377 IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 50378 } 50379 50380 50381 # EMITTING VPUNPCKLBW (VPUNPCKLBW-128-1) 50382 { 50383 ICLASS: VPUNPCKLBW 50384 CPL: 3 50385 CATEGORY: AVX512 50386 EXTENSION: AVX512EVEX 50387 ISA_SET: AVX512BW_128 50388 EXCEPTIONS: AVX512-E4NF 50389 REAL_OPCODE: Y 50390 ATTRIBUTES: MASKOP_EVEX 50391 PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 50392 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 50393 IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 50394 } 50395 50396 { 50397 ICLASS: VPUNPCKLBW 50398 CPL: 3 50399 CATEGORY: AVX512 50400 EXTENSION: AVX512EVEX 50401 ISA_SET: AVX512BW_128 50402 EXCEPTIONS: AVX512-E4NF 50403 REAL_OPCODE: Y 50404 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50405 PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() 50406 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 50407 IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 50408 } 50409 50410 50411 # EMITTING VPUNPCKLBW (VPUNPCKLBW-256-1) 50412 { 50413 ICLASS: VPUNPCKLBW 50414 CPL: 3 50415 CATEGORY: AVX512 50416 EXTENSION: AVX512EVEX 50417 ISA_SET: AVX512BW_256 50418 EXCEPTIONS: AVX512-E4NF 50419 REAL_OPCODE: Y 50420 ATTRIBUTES: MASKOP_EVEX 50421 PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 50422 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 50423 IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 50424 } 50425 50426 { 50427 ICLASS: VPUNPCKLBW 50428 CPL: 3 50429 CATEGORY: AVX512 50430 EXTENSION: AVX512EVEX 50431 ISA_SET: AVX512BW_256 50432 EXCEPTIONS: AVX512-E4NF 50433 REAL_OPCODE: Y 50434 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50435 PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() 50436 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 50437 IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 50438 } 50439 50440 50441 # EMITTING VPUNPCKLBW (VPUNPCKLBW-512-1) 50442 { 50443 ICLASS: VPUNPCKLBW 50444 CPL: 3 50445 CATEGORY: AVX512 50446 EXTENSION: AVX512EVEX 50447 ISA_SET: AVX512BW_512 50448 EXCEPTIONS: AVX512-E4NF 50449 REAL_OPCODE: Y 50450 ATTRIBUTES: MASKOP_EVEX 50451 PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 50452 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 50453 IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 50454 } 50455 50456 { 50457 ICLASS: VPUNPCKLBW 50458 CPL: 3 50459 CATEGORY: AVX512 50460 EXTENSION: AVX512EVEX 50461 ISA_SET: AVX512BW_512 50462 EXCEPTIONS: AVX512-E4NF 50463 REAL_OPCODE: Y 50464 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50465 PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() 50466 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 50467 IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 50468 } 50469 50470 50471 # EMITTING VPUNPCKLDQ (VPUNPCKLDQ-128-1) 50472 { 50473 ICLASS: VPUNPCKLDQ 50474 CPL: 3 50475 CATEGORY: AVX512 50476 EXTENSION: AVX512EVEX 50477 ISA_SET: AVX512F_128 50478 EXCEPTIONS: AVX512-E4NF 50479 REAL_OPCODE: Y 50480 ATTRIBUTES: MASKOP_EVEX 50481 PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 50482 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 50483 IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 50484 } 50485 50486 { 50487 ICLASS: VPUNPCKLDQ 50488 CPL: 3 50489 CATEGORY: AVX512 50490 EXTENSION: AVX512EVEX 50491 ISA_SET: AVX512F_128 50492 EXCEPTIONS: AVX512-E4NF 50493 REAL_OPCODE: Y 50494 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 50495 PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 50496 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 50497 IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 50498 } 50499 50500 50501 # EMITTING VPUNPCKLDQ (VPUNPCKLDQ-256-1) 50502 { 50503 ICLASS: VPUNPCKLDQ 50504 CPL: 3 50505 CATEGORY: AVX512 50506 EXTENSION: AVX512EVEX 50507 ISA_SET: AVX512F_256 50508 EXCEPTIONS: AVX512-E4NF 50509 REAL_OPCODE: Y 50510 ATTRIBUTES: MASKOP_EVEX 50511 PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 50512 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 50513 IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 50514 } 50515 50516 { 50517 ICLASS: VPUNPCKLDQ 50518 CPL: 3 50519 CATEGORY: AVX512 50520 EXTENSION: AVX512EVEX 50521 ISA_SET: AVX512F_256 50522 EXCEPTIONS: AVX512-E4NF 50523 REAL_OPCODE: Y 50524 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 50525 PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 50526 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 50527 IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 50528 } 50529 50530 50531 # EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-128-1) 50532 { 50533 ICLASS: VPUNPCKLQDQ 50534 CPL: 3 50535 CATEGORY: AVX512 50536 EXTENSION: AVX512EVEX 50537 ISA_SET: AVX512F_128 50538 EXCEPTIONS: AVX512-E4NF 50539 REAL_OPCODE: Y 50540 ATTRIBUTES: MASKOP_EVEX 50541 PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 50542 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 50543 IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 50544 } 50545 50546 { 50547 ICLASS: VPUNPCKLQDQ 50548 CPL: 3 50549 CATEGORY: AVX512 50550 EXTENSION: AVX512EVEX 50551 ISA_SET: AVX512F_128 50552 EXCEPTIONS: AVX512-E4NF 50553 REAL_OPCODE: Y 50554 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 50555 PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 50556 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 50557 IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 50558 } 50559 50560 50561 # EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-256-1) 50562 { 50563 ICLASS: VPUNPCKLQDQ 50564 CPL: 3 50565 CATEGORY: AVX512 50566 EXTENSION: AVX512EVEX 50567 ISA_SET: AVX512F_256 50568 EXCEPTIONS: AVX512-E4NF 50569 REAL_OPCODE: Y 50570 ATTRIBUTES: MASKOP_EVEX 50571 PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 50572 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 50573 IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 50574 } 50575 50576 { 50577 ICLASS: VPUNPCKLQDQ 50578 CPL: 3 50579 CATEGORY: AVX512 50580 EXTENSION: AVX512EVEX 50581 ISA_SET: AVX512F_256 50582 EXCEPTIONS: AVX512-E4NF 50583 REAL_OPCODE: Y 50584 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 50585 PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 50586 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 50587 IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 50588 } 50589 50590 50591 # EMITTING VPUNPCKLWD (VPUNPCKLWD-128-1) 50592 { 50593 ICLASS: VPUNPCKLWD 50594 CPL: 3 50595 CATEGORY: AVX512 50596 EXTENSION: AVX512EVEX 50597 ISA_SET: AVX512BW_128 50598 EXCEPTIONS: AVX512-E4NF 50599 REAL_OPCODE: Y 50600 ATTRIBUTES: MASKOP_EVEX 50601 PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 50602 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 50603 IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 50604 } 50605 50606 { 50607 ICLASS: VPUNPCKLWD 50608 CPL: 3 50609 CATEGORY: AVX512 50610 EXTENSION: AVX512EVEX 50611 ISA_SET: AVX512BW_128 50612 EXCEPTIONS: AVX512-E4NF 50613 REAL_OPCODE: Y 50614 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50615 PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() 50616 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 50617 IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 50618 } 50619 50620 50621 # EMITTING VPUNPCKLWD (VPUNPCKLWD-256-1) 50622 { 50623 ICLASS: VPUNPCKLWD 50624 CPL: 3 50625 CATEGORY: AVX512 50626 EXTENSION: AVX512EVEX 50627 ISA_SET: AVX512BW_256 50628 EXCEPTIONS: AVX512-E4NF 50629 REAL_OPCODE: Y 50630 ATTRIBUTES: MASKOP_EVEX 50631 PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 50632 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 50633 IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 50634 } 50635 50636 { 50637 ICLASS: VPUNPCKLWD 50638 CPL: 3 50639 CATEGORY: AVX512 50640 EXTENSION: AVX512EVEX 50641 ISA_SET: AVX512BW_256 50642 EXCEPTIONS: AVX512-E4NF 50643 REAL_OPCODE: Y 50644 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50645 PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() 50646 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 50647 IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 50648 } 50649 50650 50651 # EMITTING VPUNPCKLWD (VPUNPCKLWD-512-1) 50652 { 50653 ICLASS: VPUNPCKLWD 50654 CPL: 3 50655 CATEGORY: AVX512 50656 EXTENSION: AVX512EVEX 50657 ISA_SET: AVX512BW_512 50658 EXCEPTIONS: AVX512-E4NF 50659 REAL_OPCODE: Y 50660 ATTRIBUTES: MASKOP_EVEX 50661 PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 50662 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 50663 IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 50664 } 50665 50666 { 50667 ICLASS: VPUNPCKLWD 50668 CPL: 3 50669 CATEGORY: AVX512 50670 EXTENSION: AVX512EVEX 50671 ISA_SET: AVX512BW_512 50672 EXCEPTIONS: AVX512-E4NF 50673 REAL_OPCODE: Y 50674 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 50675 PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() 50676 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 50677 IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 50678 } 50679 50680 50681 # EMITTING VPXORD (VPXORD-128-1) 50682 { 50683 ICLASS: VPXORD 50684 CPL: 3 50685 CATEGORY: LOGICAL 50686 EXTENSION: AVX512EVEX 50687 ISA_SET: AVX512F_128 50688 EXCEPTIONS: AVX512-E4 50689 REAL_OPCODE: Y 50690 ATTRIBUTES: MASKOP_EVEX 50691 PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 50692 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 50693 IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 50694 } 50695 50696 { 50697 ICLASS: VPXORD 50698 CPL: 3 50699 CATEGORY: LOGICAL 50700 EXTENSION: AVX512EVEX 50701 ISA_SET: AVX512F_128 50702 EXCEPTIONS: AVX512-E4 50703 REAL_OPCODE: Y 50704 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 50705 PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 50706 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 50707 IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 50708 } 50709 50710 50711 # EMITTING VPXORD (VPXORD-256-1) 50712 { 50713 ICLASS: VPXORD 50714 CPL: 3 50715 CATEGORY: LOGICAL 50716 EXTENSION: AVX512EVEX 50717 ISA_SET: AVX512F_256 50718 EXCEPTIONS: AVX512-E4 50719 REAL_OPCODE: Y 50720 ATTRIBUTES: MASKOP_EVEX 50721 PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 50722 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 50723 IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 50724 } 50725 50726 { 50727 ICLASS: VPXORD 50728 CPL: 3 50729 CATEGORY: LOGICAL 50730 EXTENSION: AVX512EVEX 50731 ISA_SET: AVX512F_256 50732 EXCEPTIONS: AVX512-E4 50733 REAL_OPCODE: Y 50734 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 50735 PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 50736 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 50737 IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 50738 } 50739 50740 50741 # EMITTING VPXORQ (VPXORQ-128-1) 50742 { 50743 ICLASS: VPXORQ 50744 CPL: 3 50745 CATEGORY: LOGICAL 50746 EXTENSION: AVX512EVEX 50747 ISA_SET: AVX512F_128 50748 EXCEPTIONS: AVX512-E4 50749 REAL_OPCODE: Y 50750 ATTRIBUTES: MASKOP_EVEX 50751 PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 50752 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 50753 IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 50754 } 50755 50756 { 50757 ICLASS: VPXORQ 50758 CPL: 3 50759 CATEGORY: LOGICAL 50760 EXTENSION: AVX512EVEX 50761 ISA_SET: AVX512F_128 50762 EXCEPTIONS: AVX512-E4 50763 REAL_OPCODE: Y 50764 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 50765 PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 50766 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 50767 IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 50768 } 50769 50770 50771 # EMITTING VPXORQ (VPXORQ-256-1) 50772 { 50773 ICLASS: VPXORQ 50774 CPL: 3 50775 CATEGORY: LOGICAL 50776 EXTENSION: AVX512EVEX 50777 ISA_SET: AVX512F_256 50778 EXCEPTIONS: AVX512-E4 50779 REAL_OPCODE: Y 50780 ATTRIBUTES: MASKOP_EVEX 50781 PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 50782 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 50783 IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 50784 } 50785 50786 { 50787 ICLASS: VPXORQ 50788 CPL: 3 50789 CATEGORY: LOGICAL 50790 EXTENSION: AVX512EVEX 50791 ISA_SET: AVX512F_256 50792 EXCEPTIONS: AVX512-E4 50793 REAL_OPCODE: Y 50794 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 50795 PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 50796 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 50797 IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 50798 } 50799 50800 50801 # EMITTING VRANGEPD (VRANGEPD-128-1) 50802 { 50803 ICLASS: VRANGEPD 50804 CPL: 3 50805 CATEGORY: AVX512 50806 EXTENSION: AVX512EVEX 50807 ISA_SET: AVX512DQ_128 50808 EXCEPTIONS: AVX512-E2 50809 REAL_OPCODE: Y 50810 ATTRIBUTES: MASKOP_EVEX MXCSR 50811 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 50812 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 50813 IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 50814 } 50815 50816 { 50817 ICLASS: VRANGEPD 50818 CPL: 3 50819 CATEGORY: AVX512 50820 EXTENSION: AVX512EVEX 50821 ISA_SET: AVX512DQ_128 50822 EXCEPTIONS: AVX512-E2 50823 REAL_OPCODE: Y 50824 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 50825 PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 50826 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 50827 IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 50828 } 50829 50830 50831 # EMITTING VRANGEPD (VRANGEPD-256-1) 50832 { 50833 ICLASS: VRANGEPD 50834 CPL: 3 50835 CATEGORY: AVX512 50836 EXTENSION: AVX512EVEX 50837 ISA_SET: AVX512DQ_256 50838 EXCEPTIONS: AVX512-E2 50839 REAL_OPCODE: Y 50840 ATTRIBUTES: MASKOP_EVEX MXCSR 50841 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 50842 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b 50843 IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 50844 } 50845 50846 { 50847 ICLASS: VRANGEPD 50848 CPL: 3 50849 CATEGORY: AVX512 50850 EXTENSION: AVX512EVEX 50851 ISA_SET: AVX512DQ_256 50852 EXCEPTIONS: AVX512-E2 50853 REAL_OPCODE: Y 50854 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 50855 PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 50856 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 50857 IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 50858 } 50859 50860 50861 # EMITTING VRANGEPD (VRANGEPD-512-1) 50862 { 50863 ICLASS: VRANGEPD 50864 CPL: 3 50865 CATEGORY: AVX512 50866 EXTENSION: AVX512EVEX 50867 ISA_SET: AVX512DQ_512 50868 EXCEPTIONS: AVX512-E2 50869 REAL_OPCODE: Y 50870 ATTRIBUTES: MASKOP_EVEX MXCSR 50871 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 50872 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 50873 IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 50874 } 50875 50876 { 50877 ICLASS: VRANGEPD 50878 CPL: 3 50879 CATEGORY: AVX512 50880 EXTENSION: AVX512EVEX 50881 ISA_SET: AVX512DQ_512 50882 EXCEPTIONS: AVX512-E2 50883 REAL_OPCODE: Y 50884 ATTRIBUTES: MASKOP_EVEX MXCSR 50885 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() 50886 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b 50887 IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 50888 } 50889 50890 { 50891 ICLASS: VRANGEPD 50892 CPL: 3 50893 CATEGORY: AVX512 50894 EXTENSION: AVX512EVEX 50895 ISA_SET: AVX512DQ_512 50896 EXCEPTIONS: AVX512-E2 50897 REAL_OPCODE: Y 50898 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 50899 PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 50900 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 50901 IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 50902 } 50903 50904 50905 # EMITTING VRANGEPS (VRANGEPS-128-1) 50906 { 50907 ICLASS: VRANGEPS 50908 CPL: 3 50909 CATEGORY: AVX512 50910 EXTENSION: AVX512EVEX 50911 ISA_SET: AVX512DQ_128 50912 EXCEPTIONS: AVX512-E2 50913 REAL_OPCODE: Y 50914 ATTRIBUTES: MASKOP_EVEX MXCSR 50915 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 50916 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 50917 IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 50918 } 50919 50920 { 50921 ICLASS: VRANGEPS 50922 CPL: 3 50923 CATEGORY: AVX512 50924 EXTENSION: AVX512EVEX 50925 ISA_SET: AVX512DQ_128 50926 EXCEPTIONS: AVX512-E2 50927 REAL_OPCODE: Y 50928 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 50929 PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 50930 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 50931 IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 50932 } 50933 50934 50935 # EMITTING VRANGEPS (VRANGEPS-256-1) 50936 { 50937 ICLASS: VRANGEPS 50938 CPL: 3 50939 CATEGORY: AVX512 50940 EXTENSION: AVX512EVEX 50941 ISA_SET: AVX512DQ_256 50942 EXCEPTIONS: AVX512-E2 50943 REAL_OPCODE: Y 50944 ATTRIBUTES: MASKOP_EVEX MXCSR 50945 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 50946 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b 50947 IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 50948 } 50949 50950 { 50951 ICLASS: VRANGEPS 50952 CPL: 3 50953 CATEGORY: AVX512 50954 EXTENSION: AVX512EVEX 50955 ISA_SET: AVX512DQ_256 50956 EXCEPTIONS: AVX512-E2 50957 REAL_OPCODE: Y 50958 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 50959 PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 50960 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 50961 IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 50962 } 50963 50964 50965 # EMITTING VRANGEPS (VRANGEPS-512-1) 50966 { 50967 ICLASS: VRANGEPS 50968 CPL: 3 50969 CATEGORY: AVX512 50970 EXTENSION: AVX512EVEX 50971 ISA_SET: AVX512DQ_512 50972 EXCEPTIONS: AVX512-E2 50973 REAL_OPCODE: Y 50974 ATTRIBUTES: MASKOP_EVEX MXCSR 50975 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 50976 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 50977 IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 50978 } 50979 50980 { 50981 ICLASS: VRANGEPS 50982 CPL: 3 50983 CATEGORY: AVX512 50984 EXTENSION: AVX512EVEX 50985 ISA_SET: AVX512DQ_512 50986 EXCEPTIONS: AVX512-E2 50987 REAL_OPCODE: Y 50988 ATTRIBUTES: MASKOP_EVEX MXCSR 50989 PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() 50990 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b 50991 IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 50992 } 50993 50994 { 50995 ICLASS: VRANGEPS 50996 CPL: 3 50997 CATEGORY: AVX512 50998 EXTENSION: AVX512EVEX 50999 ISA_SET: AVX512DQ_512 51000 EXCEPTIONS: AVX512-E2 51001 REAL_OPCODE: Y 51002 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51003 PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 51004 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 51005 IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 51006 } 51007 51008 51009 # EMITTING VRANGESD (VRANGESD-128-1) 51010 { 51011 ICLASS: VRANGESD 51012 CPL: 3 51013 CATEGORY: AVX512 51014 EXTENSION: AVX512EVEX 51015 ISA_SET: AVX512DQ_SCALAR 51016 EXCEPTIONS: AVX512-E3 51017 REAL_OPCODE: Y 51018 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 51019 PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() 51020 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 51021 IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 51022 } 51023 51024 { 51025 ICLASS: VRANGESD 51026 CPL: 3 51027 CATEGORY: AVX512 51028 EXTENSION: AVX512EVEX 51029 ISA_SET: AVX512DQ_SCALAR 51030 EXCEPTIONS: AVX512-E3 51031 REAL_OPCODE: Y 51032 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 51033 PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() 51034 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 51035 IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 51036 } 51037 51038 { 51039 ICLASS: VRANGESD 51040 CPL: 3 51041 CATEGORY: AVX512 51042 EXTENSION: AVX512EVEX 51043 ISA_SET: AVX512DQ_SCALAR 51044 EXCEPTIONS: AVX512-E3 51045 REAL_OPCODE: Y 51046 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 51047 PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 51048 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 51049 IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 51050 } 51051 51052 51053 # EMITTING VRANGESS (VRANGESS-128-1) 51054 { 51055 ICLASS: VRANGESS 51056 CPL: 3 51057 CATEGORY: AVX512 51058 EXTENSION: AVX512EVEX 51059 ISA_SET: AVX512DQ_SCALAR 51060 EXCEPTIONS: AVX512-E3 51061 REAL_OPCODE: Y 51062 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 51063 PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() 51064 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 51065 IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 51066 } 51067 51068 { 51069 ICLASS: VRANGESS 51070 CPL: 3 51071 CATEGORY: AVX512 51072 EXTENSION: AVX512EVEX 51073 ISA_SET: AVX512DQ_SCALAR 51074 EXCEPTIONS: AVX512-E3 51075 REAL_OPCODE: Y 51076 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 51077 PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() 51078 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 51079 IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 51080 } 51081 51082 { 51083 ICLASS: VRANGESS 51084 CPL: 3 51085 CATEGORY: AVX512 51086 EXTENSION: AVX512EVEX 51087 ISA_SET: AVX512DQ_SCALAR 51088 EXCEPTIONS: AVX512-E3 51089 REAL_OPCODE: Y 51090 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 51091 PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 51092 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 51093 IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 51094 } 51095 51096 51097 # EMITTING VRCP14PD (VRCP14PD-128-1) 51098 { 51099 ICLASS: VRCP14PD 51100 CPL: 3 51101 CATEGORY: AVX512 51102 EXTENSION: AVX512EVEX 51103 ISA_SET: AVX512F_128 51104 EXCEPTIONS: AVX512-E4 51105 REAL_OPCODE: Y 51106 ATTRIBUTES: MASKOP_EVEX MXCSR 51107 PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 51108 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 51109 IFORM: VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 51110 } 51111 51112 { 51113 ICLASS: VRCP14PD 51114 CPL: 3 51115 CATEGORY: AVX512 51116 EXTENSION: AVX512EVEX 51117 ISA_SET: AVX512F_128 51118 EXCEPTIONS: AVX512-E4 51119 REAL_OPCODE: Y 51120 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51121 PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 51122 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 51123 IFORM: VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 51124 } 51125 51126 51127 # EMITTING VRCP14PD (VRCP14PD-256-1) 51128 { 51129 ICLASS: VRCP14PD 51130 CPL: 3 51131 CATEGORY: AVX512 51132 EXTENSION: AVX512EVEX 51133 ISA_SET: AVX512F_256 51134 EXCEPTIONS: AVX512-E4 51135 REAL_OPCODE: Y 51136 ATTRIBUTES: MASKOP_EVEX MXCSR 51137 PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 51138 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 51139 IFORM: VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 51140 } 51141 51142 { 51143 ICLASS: VRCP14PD 51144 CPL: 3 51145 CATEGORY: AVX512 51146 EXTENSION: AVX512EVEX 51147 ISA_SET: AVX512F_256 51148 EXCEPTIONS: AVX512-E4 51149 REAL_OPCODE: Y 51150 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51151 PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 51152 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 51153 IFORM: VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 51154 } 51155 51156 51157 # EMITTING VRCP14PS (VRCP14PS-128-1) 51158 { 51159 ICLASS: VRCP14PS 51160 CPL: 3 51161 CATEGORY: AVX512 51162 EXTENSION: AVX512EVEX 51163 ISA_SET: AVX512F_128 51164 EXCEPTIONS: AVX512-E4 51165 REAL_OPCODE: Y 51166 ATTRIBUTES: MASKOP_EVEX MXCSR 51167 PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 51168 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 51169 IFORM: VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 51170 } 51171 51172 { 51173 ICLASS: VRCP14PS 51174 CPL: 3 51175 CATEGORY: AVX512 51176 EXTENSION: AVX512EVEX 51177 ISA_SET: AVX512F_128 51178 EXCEPTIONS: AVX512-E4 51179 REAL_OPCODE: Y 51180 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51181 PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 51182 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 51183 IFORM: VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 51184 } 51185 51186 51187 # EMITTING VRCP14PS (VRCP14PS-256-1) 51188 { 51189 ICLASS: VRCP14PS 51190 CPL: 3 51191 CATEGORY: AVX512 51192 EXTENSION: AVX512EVEX 51193 ISA_SET: AVX512F_256 51194 EXCEPTIONS: AVX512-E4 51195 REAL_OPCODE: Y 51196 ATTRIBUTES: MASKOP_EVEX MXCSR 51197 PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 51198 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 51199 IFORM: VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 51200 } 51201 51202 { 51203 ICLASS: VRCP14PS 51204 CPL: 3 51205 CATEGORY: AVX512 51206 EXTENSION: AVX512EVEX 51207 ISA_SET: AVX512F_256 51208 EXCEPTIONS: AVX512-E4 51209 REAL_OPCODE: Y 51210 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51211 PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 51212 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 51213 IFORM: VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 51214 } 51215 51216 51217 # EMITTING VREDUCEPD (VREDUCEPD-128-1) 51218 { 51219 ICLASS: VREDUCEPD 51220 CPL: 3 51221 CATEGORY: AVX512 51222 EXTENSION: AVX512EVEX 51223 ISA_SET: AVX512DQ_128 51224 EXCEPTIONS: AVX512-E2 51225 REAL_OPCODE: Y 51226 ATTRIBUTES: MASKOP_EVEX MXCSR 51227 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() 51228 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b 51229 IFORM: VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 51230 } 51231 51232 { 51233 ICLASS: VREDUCEPD 51234 CPL: 3 51235 CATEGORY: AVX512 51236 EXTENSION: AVX512EVEX 51237 ISA_SET: AVX512DQ_128 51238 EXCEPTIONS: AVX512-E2 51239 REAL_OPCODE: Y 51240 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51241 PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 51242 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 51243 IFORM: VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 51244 } 51245 51246 51247 # EMITTING VREDUCEPD (VREDUCEPD-256-1) 51248 { 51249 ICLASS: VREDUCEPD 51250 CPL: 3 51251 CATEGORY: AVX512 51252 EXTENSION: AVX512EVEX 51253 ISA_SET: AVX512DQ_256 51254 EXCEPTIONS: AVX512-E2 51255 REAL_OPCODE: Y 51256 ATTRIBUTES: MASKOP_EVEX MXCSR 51257 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 51258 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b 51259 IFORM: VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 51260 } 51261 51262 { 51263 ICLASS: VREDUCEPD 51264 CPL: 3 51265 CATEGORY: AVX512 51266 EXTENSION: AVX512EVEX 51267 ISA_SET: AVX512DQ_256 51268 EXCEPTIONS: AVX512-E2 51269 REAL_OPCODE: Y 51270 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51271 PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 51272 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 51273 IFORM: VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 51274 } 51275 51276 51277 # EMITTING VREDUCEPD (VREDUCEPD-512-1) 51278 { 51279 ICLASS: VREDUCEPD 51280 CPL: 3 51281 CATEGORY: AVX512 51282 EXTENSION: AVX512EVEX 51283 ISA_SET: AVX512DQ_512 51284 EXCEPTIONS: AVX512-E2 51285 REAL_OPCODE: Y 51286 ATTRIBUTES: MASKOP_EVEX MXCSR 51287 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() 51288 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 51289 IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 51290 } 51291 51292 { 51293 ICLASS: VREDUCEPD 51294 CPL: 3 51295 CATEGORY: AVX512 51296 EXTENSION: AVX512EVEX 51297 ISA_SET: AVX512DQ_512 51298 EXCEPTIONS: AVX512-E2 51299 REAL_OPCODE: Y 51300 ATTRIBUTES: MASKOP_EVEX MXCSR 51301 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() 51302 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b 51303 IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 51304 } 51305 51306 { 51307 ICLASS: VREDUCEPD 51308 CPL: 3 51309 CATEGORY: AVX512 51310 EXTENSION: AVX512EVEX 51311 ISA_SET: AVX512DQ_512 51312 EXCEPTIONS: AVX512-E2 51313 REAL_OPCODE: Y 51314 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51315 PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 51316 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 51317 IFORM: VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 51318 } 51319 51320 51321 # EMITTING VREDUCEPS (VREDUCEPS-128-1) 51322 { 51323 ICLASS: VREDUCEPS 51324 CPL: 3 51325 CATEGORY: AVX512 51326 EXTENSION: AVX512EVEX 51327 ISA_SET: AVX512DQ_128 51328 EXCEPTIONS: AVX512-E2 51329 REAL_OPCODE: Y 51330 ATTRIBUTES: MASKOP_EVEX MXCSR 51331 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() 51332 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b 51333 IFORM: VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 51334 } 51335 51336 { 51337 ICLASS: VREDUCEPS 51338 CPL: 3 51339 CATEGORY: AVX512 51340 EXTENSION: AVX512EVEX 51341 ISA_SET: AVX512DQ_128 51342 EXCEPTIONS: AVX512-E2 51343 REAL_OPCODE: Y 51344 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51345 PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 51346 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 51347 IFORM: VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 51348 } 51349 51350 51351 # EMITTING VREDUCEPS (VREDUCEPS-256-1) 51352 { 51353 ICLASS: VREDUCEPS 51354 CPL: 3 51355 CATEGORY: AVX512 51356 EXTENSION: AVX512EVEX 51357 ISA_SET: AVX512DQ_256 51358 EXCEPTIONS: AVX512-E2 51359 REAL_OPCODE: Y 51360 ATTRIBUTES: MASKOP_EVEX MXCSR 51361 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 51362 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b 51363 IFORM: VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 51364 } 51365 51366 { 51367 ICLASS: VREDUCEPS 51368 CPL: 3 51369 CATEGORY: AVX512 51370 EXTENSION: AVX512EVEX 51371 ISA_SET: AVX512DQ_256 51372 EXCEPTIONS: AVX512-E2 51373 REAL_OPCODE: Y 51374 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51375 PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 51376 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 51377 IFORM: VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 51378 } 51379 51380 51381 # EMITTING VREDUCEPS (VREDUCEPS-512-1) 51382 { 51383 ICLASS: VREDUCEPS 51384 CPL: 3 51385 CATEGORY: AVX512 51386 EXTENSION: AVX512EVEX 51387 ISA_SET: AVX512DQ_512 51388 EXCEPTIONS: AVX512-E2 51389 REAL_OPCODE: Y 51390 ATTRIBUTES: MASKOP_EVEX MXCSR 51391 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() 51392 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 51393 IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 51394 } 51395 51396 { 51397 ICLASS: VREDUCEPS 51398 CPL: 3 51399 CATEGORY: AVX512 51400 EXTENSION: AVX512EVEX 51401 ISA_SET: AVX512DQ_512 51402 EXCEPTIONS: AVX512-E2 51403 REAL_OPCODE: Y 51404 ATTRIBUTES: MASKOP_EVEX MXCSR 51405 PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() 51406 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b 51407 IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 51408 } 51409 51410 { 51411 ICLASS: VREDUCEPS 51412 CPL: 3 51413 CATEGORY: AVX512 51414 EXTENSION: AVX512EVEX 51415 ISA_SET: AVX512DQ_512 51416 EXCEPTIONS: AVX512-E2 51417 REAL_OPCODE: Y 51418 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51419 PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 51420 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 51421 IFORM: VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 51422 } 51423 51424 51425 # EMITTING VREDUCESD (VREDUCESD-128-1) 51426 { 51427 ICLASS: VREDUCESD 51428 CPL: 3 51429 CATEGORY: AVX512 51430 EXTENSION: AVX512EVEX 51431 ISA_SET: AVX512DQ_SCALAR 51432 EXCEPTIONS: AVX512-E3 51433 REAL_OPCODE: Y 51434 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 51435 PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() 51436 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 51437 IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 51438 } 51439 51440 { 51441 ICLASS: VREDUCESD 51442 CPL: 3 51443 CATEGORY: AVX512 51444 EXTENSION: AVX512EVEX 51445 ISA_SET: AVX512DQ_SCALAR 51446 EXCEPTIONS: AVX512-E3 51447 REAL_OPCODE: Y 51448 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 51449 PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() 51450 OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 51451 IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 51452 } 51453 51454 { 51455 ICLASS: VREDUCESD 51456 CPL: 3 51457 CATEGORY: AVX512 51458 EXTENSION: AVX512EVEX 51459 ISA_SET: AVX512DQ_SCALAR 51460 EXCEPTIONS: AVX512-E3 51461 REAL_OPCODE: Y 51462 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 51463 PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() 51464 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b 51465 IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 51466 } 51467 51468 51469 # EMITTING VREDUCESS (VREDUCESS-128-1) 51470 { 51471 ICLASS: VREDUCESS 51472 CPL: 3 51473 CATEGORY: AVX512 51474 EXTENSION: AVX512EVEX 51475 ISA_SET: AVX512DQ_SCALAR 51476 EXCEPTIONS: AVX512-E3 51477 REAL_OPCODE: Y 51478 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 51479 PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() 51480 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 51481 IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 51482 } 51483 51484 { 51485 ICLASS: VREDUCESS 51486 CPL: 3 51487 CATEGORY: AVX512 51488 EXTENSION: AVX512EVEX 51489 ISA_SET: AVX512DQ_SCALAR 51490 EXCEPTIONS: AVX512-E3 51491 REAL_OPCODE: Y 51492 ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR 51493 PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() 51494 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 51495 IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 51496 } 51497 51498 { 51499 ICLASS: VREDUCESS 51500 CPL: 3 51501 CATEGORY: AVX512 51502 EXTENSION: AVX512EVEX 51503 ISA_SET: AVX512DQ_SCALAR 51504 EXCEPTIONS: AVX512-E3 51505 REAL_OPCODE: Y 51506 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR 51507 PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() 51508 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b 51509 IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 51510 } 51511 51512 51513 # EMITTING VRNDSCALEPD (VRNDSCALEPD-128-1) 51514 { 51515 ICLASS: VRNDSCALEPD 51516 CPL: 3 51517 CATEGORY: AVX512 51518 EXTENSION: AVX512EVEX 51519 ISA_SET: AVX512F_128 51520 EXCEPTIONS: AVX512-E2 51521 REAL_OPCODE: Y 51522 ATTRIBUTES: MASKOP_EVEX MXCSR 51523 PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() 51524 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b 51525 IFORM: VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 51526 } 51527 51528 { 51529 ICLASS: VRNDSCALEPD 51530 CPL: 3 51531 CATEGORY: AVX512 51532 EXTENSION: AVX512EVEX 51533 ISA_SET: AVX512F_128 51534 EXCEPTIONS: AVX512-E2 51535 REAL_OPCODE: Y 51536 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51537 PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 51538 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 51539 IFORM: VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 51540 } 51541 51542 51543 # EMITTING VRNDSCALEPD (VRNDSCALEPD-256-1) 51544 { 51545 ICLASS: VRNDSCALEPD 51546 CPL: 3 51547 CATEGORY: AVX512 51548 EXTENSION: AVX512EVEX 51549 ISA_SET: AVX512F_256 51550 EXCEPTIONS: AVX512-E2 51551 REAL_OPCODE: Y 51552 ATTRIBUTES: MASKOP_EVEX MXCSR 51553 PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() 51554 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b 51555 IFORM: VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 51556 } 51557 51558 { 51559 ICLASS: VRNDSCALEPD 51560 CPL: 3 51561 CATEGORY: AVX512 51562 EXTENSION: AVX512EVEX 51563 ISA_SET: AVX512F_256 51564 EXCEPTIONS: AVX512-E2 51565 REAL_OPCODE: Y 51566 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51567 PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() 51568 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 51569 IFORM: VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 51570 } 51571 51572 51573 # EMITTING VRNDSCALEPS (VRNDSCALEPS-128-1) 51574 { 51575 ICLASS: VRNDSCALEPS 51576 CPL: 3 51577 CATEGORY: AVX512 51578 EXTENSION: AVX512EVEX 51579 ISA_SET: AVX512F_128 51580 EXCEPTIONS: AVX512-E2 51581 REAL_OPCODE: Y 51582 ATTRIBUTES: MASKOP_EVEX MXCSR 51583 PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() 51584 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b 51585 IFORM: VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 51586 } 51587 51588 { 51589 ICLASS: VRNDSCALEPS 51590 CPL: 3 51591 CATEGORY: AVX512 51592 EXTENSION: AVX512EVEX 51593 ISA_SET: AVX512F_128 51594 EXCEPTIONS: AVX512-E2 51595 REAL_OPCODE: Y 51596 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51597 PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 51598 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 51599 IFORM: VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 51600 } 51601 51602 51603 # EMITTING VRNDSCALEPS (VRNDSCALEPS-256-1) 51604 { 51605 ICLASS: VRNDSCALEPS 51606 CPL: 3 51607 CATEGORY: AVX512 51608 EXTENSION: AVX512EVEX 51609 ISA_SET: AVX512F_256 51610 EXCEPTIONS: AVX512-E2 51611 REAL_OPCODE: Y 51612 ATTRIBUTES: MASKOP_EVEX MXCSR 51613 PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() 51614 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b 51615 IFORM: VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 51616 } 51617 51618 { 51619 ICLASS: VRNDSCALEPS 51620 CPL: 3 51621 CATEGORY: AVX512 51622 EXTENSION: AVX512EVEX 51623 ISA_SET: AVX512F_256 51624 EXCEPTIONS: AVX512-E2 51625 REAL_OPCODE: Y 51626 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51627 PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() 51628 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 51629 IFORM: VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 51630 } 51631 51632 51633 # EMITTING VRSQRT14PD (VRSQRT14PD-128-1) 51634 { 51635 ICLASS: VRSQRT14PD 51636 CPL: 3 51637 CATEGORY: AVX512 51638 EXTENSION: AVX512EVEX 51639 ISA_SET: AVX512F_128 51640 EXCEPTIONS: AVX512-E4 51641 REAL_OPCODE: Y 51642 ATTRIBUTES: MASKOP_EVEX MXCSR 51643 PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 51644 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 51645 IFORM: VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 51646 } 51647 51648 { 51649 ICLASS: VRSQRT14PD 51650 CPL: 3 51651 CATEGORY: AVX512 51652 EXTENSION: AVX512EVEX 51653 ISA_SET: AVX512F_128 51654 EXCEPTIONS: AVX512-E4 51655 REAL_OPCODE: Y 51656 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51657 PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 51658 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 51659 IFORM: VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 51660 } 51661 51662 51663 # EMITTING VRSQRT14PD (VRSQRT14PD-256-1) 51664 { 51665 ICLASS: VRSQRT14PD 51666 CPL: 3 51667 CATEGORY: AVX512 51668 EXTENSION: AVX512EVEX 51669 ISA_SET: AVX512F_256 51670 EXCEPTIONS: AVX512-E4 51671 REAL_OPCODE: Y 51672 ATTRIBUTES: MASKOP_EVEX MXCSR 51673 PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 51674 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 51675 IFORM: VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 51676 } 51677 51678 { 51679 ICLASS: VRSQRT14PD 51680 CPL: 3 51681 CATEGORY: AVX512 51682 EXTENSION: AVX512EVEX 51683 ISA_SET: AVX512F_256 51684 EXCEPTIONS: AVX512-E4 51685 REAL_OPCODE: Y 51686 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51687 PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 51688 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 51689 IFORM: VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 51690 } 51691 51692 51693 # EMITTING VRSQRT14PS (VRSQRT14PS-128-1) 51694 { 51695 ICLASS: VRSQRT14PS 51696 CPL: 3 51697 CATEGORY: AVX512 51698 EXTENSION: AVX512EVEX 51699 ISA_SET: AVX512F_128 51700 EXCEPTIONS: AVX512-E4 51701 REAL_OPCODE: Y 51702 ATTRIBUTES: MASKOP_EVEX MXCSR 51703 PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 51704 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 51705 IFORM: VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 51706 } 51707 51708 { 51709 ICLASS: VRSQRT14PS 51710 CPL: 3 51711 CATEGORY: AVX512 51712 EXTENSION: AVX512EVEX 51713 ISA_SET: AVX512F_128 51714 EXCEPTIONS: AVX512-E4 51715 REAL_OPCODE: Y 51716 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51717 PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 51718 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 51719 IFORM: VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 51720 } 51721 51722 51723 # EMITTING VRSQRT14PS (VRSQRT14PS-256-1) 51724 { 51725 ICLASS: VRSQRT14PS 51726 CPL: 3 51727 CATEGORY: AVX512 51728 EXTENSION: AVX512EVEX 51729 ISA_SET: AVX512F_256 51730 EXCEPTIONS: AVX512-E4 51731 REAL_OPCODE: Y 51732 ATTRIBUTES: MASKOP_EVEX MXCSR 51733 PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 51734 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 51735 IFORM: VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 51736 } 51737 51738 { 51739 ICLASS: VRSQRT14PS 51740 CPL: 3 51741 CATEGORY: AVX512 51742 EXTENSION: AVX512EVEX 51743 ISA_SET: AVX512F_256 51744 EXCEPTIONS: AVX512-E4 51745 REAL_OPCODE: Y 51746 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51747 PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 51748 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 51749 IFORM: VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 51750 } 51751 51752 51753 # EMITTING VSCALEFPD (VSCALEFPD-128-1) 51754 { 51755 ICLASS: VSCALEFPD 51756 CPL: 3 51757 CATEGORY: AVX512 51758 EXTENSION: AVX512EVEX 51759 ISA_SET: AVX512F_128 51760 EXCEPTIONS: AVX512-E2 51761 REAL_OPCODE: Y 51762 ATTRIBUTES: MASKOP_EVEX MXCSR 51763 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 51764 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 51765 IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 51766 } 51767 51768 { 51769 ICLASS: VSCALEFPD 51770 CPL: 3 51771 CATEGORY: AVX512 51772 EXTENSION: AVX512EVEX 51773 ISA_SET: AVX512F_128 51774 EXCEPTIONS: AVX512-E2 51775 REAL_OPCODE: Y 51776 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51777 PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 51778 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 51779 IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 51780 } 51781 51782 51783 # EMITTING VSCALEFPD (VSCALEFPD-256-1) 51784 { 51785 ICLASS: VSCALEFPD 51786 CPL: 3 51787 CATEGORY: AVX512 51788 EXTENSION: AVX512EVEX 51789 ISA_SET: AVX512F_256 51790 EXCEPTIONS: AVX512-E2 51791 REAL_OPCODE: Y 51792 ATTRIBUTES: MASKOP_EVEX MXCSR 51793 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 51794 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 51795 IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 51796 } 51797 51798 { 51799 ICLASS: VSCALEFPD 51800 CPL: 3 51801 CATEGORY: AVX512 51802 EXTENSION: AVX512EVEX 51803 ISA_SET: AVX512F_256 51804 EXCEPTIONS: AVX512-E2 51805 REAL_OPCODE: Y 51806 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51807 PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 51808 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 51809 IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 51810 } 51811 51812 51813 # EMITTING VSCALEFPS (VSCALEFPS-128-1) 51814 { 51815 ICLASS: VSCALEFPS 51816 CPL: 3 51817 CATEGORY: AVX512 51818 EXTENSION: AVX512EVEX 51819 ISA_SET: AVX512F_128 51820 EXCEPTIONS: AVX512-E2 51821 REAL_OPCODE: Y 51822 ATTRIBUTES: MASKOP_EVEX MXCSR 51823 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 51824 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 51825 IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 51826 } 51827 51828 { 51829 ICLASS: VSCALEFPS 51830 CPL: 3 51831 CATEGORY: AVX512 51832 EXTENSION: AVX512EVEX 51833 ISA_SET: AVX512F_128 51834 EXCEPTIONS: AVX512-E2 51835 REAL_OPCODE: Y 51836 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51837 PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 51838 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 51839 IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 51840 } 51841 51842 51843 # EMITTING VSCALEFPS (VSCALEFPS-256-1) 51844 { 51845 ICLASS: VSCALEFPS 51846 CPL: 3 51847 CATEGORY: AVX512 51848 EXTENSION: AVX512EVEX 51849 ISA_SET: AVX512F_256 51850 EXCEPTIONS: AVX512-E2 51851 REAL_OPCODE: Y 51852 ATTRIBUTES: MASKOP_EVEX MXCSR 51853 PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 51854 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 51855 IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 51856 } 51857 51858 { 51859 ICLASS: VSCALEFPS 51860 CPL: 3 51861 CATEGORY: AVX512 51862 EXTENSION: AVX512EVEX 51863 ISA_SET: AVX512F_256 51864 EXCEPTIONS: AVX512-E2 51865 REAL_OPCODE: Y 51866 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 51867 PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 51868 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 51869 IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 51870 } 51871 51872 51873 # EMITTING VSCATTERDPD (VSCATTERDPD-128-1) 51874 { 51875 ICLASS: VSCATTERDPD 51876 CPL: 3 51877 CATEGORY: SCATTER 51878 EXTENSION: AVX512EVEX 51879 ISA_SET: AVX512F_128 51880 EXCEPTIONS: AVX512-E12 51881 REAL_OPCODE: Y 51882 ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 51883 PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 51884 OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 51885 IFORM: VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 51886 } 51887 51888 51889 # EMITTING VSCATTERDPD (VSCATTERDPD-256-1) 51890 { 51891 ICLASS: VSCATTERDPD 51892 CPL: 3 51893 CATEGORY: SCATTER 51894 EXTENSION: AVX512EVEX 51895 ISA_SET: AVX512F_256 51896 EXCEPTIONS: AVX512-E12 51897 REAL_OPCODE: Y 51898 ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 51899 PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 51900 OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 51901 IFORM: VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 51902 } 51903 51904 51905 # EMITTING VSCATTERDPS (VSCATTERDPS-128-1) 51906 { 51907 ICLASS: VSCATTERDPS 51908 CPL: 3 51909 CATEGORY: SCATTER 51910 EXTENSION: AVX512EVEX 51911 ISA_SET: AVX512F_128 51912 EXCEPTIONS: AVX512-E12 51913 REAL_OPCODE: Y 51914 ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 51915 PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 51916 OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 51917 IFORM: VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 51918 } 51919 51920 51921 # EMITTING VSCATTERDPS (VSCATTERDPS-256-1) 51922 { 51923 ICLASS: VSCATTERDPS 51924 CPL: 3 51925 CATEGORY: SCATTER 51926 EXTENSION: AVX512EVEX 51927 ISA_SET: AVX512F_256 51928 EXCEPTIONS: AVX512-E12 51929 REAL_OPCODE: Y 51930 ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 51931 PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 51932 OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 51933 IFORM: VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 51934 } 51935 51936 51937 # EMITTING VSCATTERQPD (VSCATTERQPD-128-1) 51938 { 51939 ICLASS: VSCATTERQPD 51940 CPL: 3 51941 CATEGORY: SCATTER 51942 EXTENSION: AVX512EVEX 51943 ISA_SET: AVX512F_128 51944 EXCEPTIONS: AVX512-E12 51945 REAL_OPCODE: Y 51946 ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 51947 PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 51948 OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 51949 IFORM: VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 51950 } 51951 51952 51953 # EMITTING VSCATTERQPD (VSCATTERQPD-256-1) 51954 { 51955 ICLASS: VSCATTERQPD 51956 CPL: 3 51957 CATEGORY: SCATTER 51958 EXTENSION: AVX512EVEX 51959 ISA_SET: AVX512F_256 51960 EXCEPTIONS: AVX512-E12 51961 REAL_OPCODE: Y 51962 ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 51963 PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() 51964 OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 51965 IFORM: VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 51966 } 51967 51968 51969 # EMITTING VSCATTERQPS (VSCATTERQPS-128-1) 51970 { 51971 ICLASS: VSCATTERQPS 51972 CPL: 3 51973 CATEGORY: SCATTER 51974 EXTENSION: AVX512EVEX 51975 ISA_SET: AVX512F_128 51976 EXCEPTIONS: AVX512-E12 51977 REAL_OPCODE: Y 51978 ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 51979 PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 51980 OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 51981 IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 51982 } 51983 51984 51985 # EMITTING VSCATTERQPS (VSCATTERQPS-256-1) 51986 { 51987 ICLASS: VSCATTERQPS 51988 CPL: 3 51989 CATEGORY: SCATTER 51990 EXTENSION: AVX512EVEX 51991 ISA_SET: AVX512F_256 51992 EXCEPTIONS: AVX512-E12 51993 REAL_OPCODE: Y 51994 ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER 51995 PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() 51996 OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 51997 IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 51998 } 51999 52000 52001 # EMITTING VSHUFF32X4 (VSHUFF32X4-256-1) 52002 { 52003 ICLASS: VSHUFF32X4 52004 CPL: 3 52005 CATEGORY: AVX512 52006 EXTENSION: AVX512EVEX 52007 ISA_SET: AVX512F_256 52008 EXCEPTIONS: AVX512-E4NF 52009 REAL_OPCODE: Y 52010 ATTRIBUTES: MASKOP_EVEX 52011 PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 52012 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b 52013 IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 52014 } 52015 52016 { 52017 ICLASS: VSHUFF32X4 52018 CPL: 3 52019 CATEGORY: AVX512 52020 EXTENSION: AVX512EVEX 52021 ISA_SET: AVX512F_256 52022 EXCEPTIONS: AVX512-E4NF 52023 REAL_OPCODE: Y 52024 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52025 PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 52026 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 52027 IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 52028 } 52029 52030 52031 # EMITTING VSHUFF64X2 (VSHUFF64X2-256-1) 52032 { 52033 ICLASS: VSHUFF64X2 52034 CPL: 3 52035 CATEGORY: AVX512 52036 EXTENSION: AVX512EVEX 52037 ISA_SET: AVX512F_256 52038 EXCEPTIONS: AVX512-E4NF 52039 REAL_OPCODE: Y 52040 ATTRIBUTES: MASKOP_EVEX 52041 PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 52042 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b 52043 IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 52044 } 52045 52046 { 52047 ICLASS: VSHUFF64X2 52048 CPL: 3 52049 CATEGORY: AVX512 52050 EXTENSION: AVX512EVEX 52051 ISA_SET: AVX512F_256 52052 EXCEPTIONS: AVX512-E4NF 52053 REAL_OPCODE: Y 52054 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52055 PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 52056 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 52057 IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 52058 } 52059 52060 52061 # EMITTING VSHUFI32X4 (VSHUFI32X4-256-1) 52062 { 52063 ICLASS: VSHUFI32X4 52064 CPL: 3 52065 CATEGORY: AVX512 52066 EXTENSION: AVX512EVEX 52067 ISA_SET: AVX512F_256 52068 EXCEPTIONS: AVX512-E4NF 52069 REAL_OPCODE: Y 52070 ATTRIBUTES: MASKOP_EVEX 52071 PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 52072 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b 52073 IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 52074 } 52075 52076 { 52077 ICLASS: VSHUFI32X4 52078 CPL: 3 52079 CATEGORY: AVX512 52080 EXTENSION: AVX512EVEX 52081 ISA_SET: AVX512F_256 52082 EXCEPTIONS: AVX512-E4NF 52083 REAL_OPCODE: Y 52084 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52085 PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 52086 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 52087 IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 52088 } 52089 52090 52091 # EMITTING VSHUFI64X2 (VSHUFI64X2-256-1) 52092 { 52093 ICLASS: VSHUFI64X2 52094 CPL: 3 52095 CATEGORY: AVX512 52096 EXTENSION: AVX512EVEX 52097 ISA_SET: AVX512F_256 52098 EXCEPTIONS: AVX512-E4NF 52099 REAL_OPCODE: Y 52100 ATTRIBUTES: MASKOP_EVEX 52101 PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 52102 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b 52103 IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 52104 } 52105 52106 { 52107 ICLASS: VSHUFI64X2 52108 CPL: 3 52109 CATEGORY: AVX512 52110 EXTENSION: AVX512EVEX 52111 ISA_SET: AVX512F_256 52112 EXCEPTIONS: AVX512-E4NF 52113 REAL_OPCODE: Y 52114 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52115 PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 52116 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 52117 IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 52118 } 52119 52120 52121 # EMITTING VSHUFPD (VSHUFPD-128-1) 52122 { 52123 ICLASS: VSHUFPD 52124 CPL: 3 52125 CATEGORY: AVX512 52126 EXTENSION: AVX512EVEX 52127 ISA_SET: AVX512F_128 52128 EXCEPTIONS: AVX512-E4NF 52129 REAL_OPCODE: Y 52130 ATTRIBUTES: MASKOP_EVEX 52131 PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 52132 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b 52133 IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 52134 } 52135 52136 { 52137 ICLASS: VSHUFPD 52138 CPL: 3 52139 CATEGORY: AVX512 52140 EXTENSION: AVX512EVEX 52141 ISA_SET: AVX512F_128 52142 EXCEPTIONS: AVX512-E4NF 52143 REAL_OPCODE: Y 52144 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52145 PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 52146 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 52147 IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 52148 } 52149 52150 52151 # EMITTING VSHUFPD (VSHUFPD-256-1) 52152 { 52153 ICLASS: VSHUFPD 52154 CPL: 3 52155 CATEGORY: AVX512 52156 EXTENSION: AVX512EVEX 52157 ISA_SET: AVX512F_256 52158 EXCEPTIONS: AVX512-E4NF 52159 REAL_OPCODE: Y 52160 ATTRIBUTES: MASKOP_EVEX 52161 PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 52162 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b 52163 IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 52164 } 52165 52166 { 52167 ICLASS: VSHUFPD 52168 CPL: 3 52169 CATEGORY: AVX512 52170 EXTENSION: AVX512EVEX 52171 ISA_SET: AVX512F_256 52172 EXCEPTIONS: AVX512-E4NF 52173 REAL_OPCODE: Y 52174 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52175 PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 52176 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b 52177 IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 52178 } 52179 52180 52181 # EMITTING VSHUFPS (VSHUFPS-128-1) 52182 { 52183 ICLASS: VSHUFPS 52184 CPL: 3 52185 CATEGORY: AVX512 52186 EXTENSION: AVX512EVEX 52187 ISA_SET: AVX512F_128 52188 EXCEPTIONS: AVX512-E4NF 52189 REAL_OPCODE: Y 52190 ATTRIBUTES: MASKOP_EVEX 52191 PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 52192 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b 52193 IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 52194 } 52195 52196 { 52197 ICLASS: VSHUFPS 52198 CPL: 3 52199 CATEGORY: AVX512 52200 EXTENSION: AVX512EVEX 52201 ISA_SET: AVX512F_128 52202 EXCEPTIONS: AVX512-E4NF 52203 REAL_OPCODE: Y 52204 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52205 PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 52206 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 52207 IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 52208 } 52209 52210 52211 # EMITTING VSHUFPS (VSHUFPS-256-1) 52212 { 52213 ICLASS: VSHUFPS 52214 CPL: 3 52215 CATEGORY: AVX512 52216 EXTENSION: AVX512EVEX 52217 ISA_SET: AVX512F_256 52218 EXCEPTIONS: AVX512-E4NF 52219 REAL_OPCODE: Y 52220 ATTRIBUTES: MASKOP_EVEX 52221 PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 52222 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b 52223 IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 52224 } 52225 52226 { 52227 ICLASS: VSHUFPS 52228 CPL: 3 52229 CATEGORY: AVX512 52230 EXTENSION: AVX512EVEX 52231 ISA_SET: AVX512F_256 52232 EXCEPTIONS: AVX512-E4NF 52233 REAL_OPCODE: Y 52234 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52235 PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 52236 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b 52237 IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 52238 } 52239 52240 52241 # EMITTING VSQRTPD (VSQRTPD-128-1) 52242 { 52243 ICLASS: VSQRTPD 52244 CPL: 3 52245 CATEGORY: AVX512 52246 EXTENSION: AVX512EVEX 52247 ISA_SET: AVX512F_128 52248 EXCEPTIONS: AVX512-E2 52249 REAL_OPCODE: Y 52250 ATTRIBUTES: MASKOP_EVEX MXCSR 52251 PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 52252 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 52253 IFORM: VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 52254 } 52255 52256 { 52257 ICLASS: VSQRTPD 52258 CPL: 3 52259 CATEGORY: AVX512 52260 EXTENSION: AVX512EVEX 52261 ISA_SET: AVX512F_128 52262 EXCEPTIONS: AVX512-E2 52263 REAL_OPCODE: Y 52264 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 52265 PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 52266 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 52267 IFORM: VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 52268 } 52269 52270 52271 # EMITTING VSQRTPD (VSQRTPD-256-1) 52272 { 52273 ICLASS: VSQRTPD 52274 CPL: 3 52275 CATEGORY: AVX512 52276 EXTENSION: AVX512EVEX 52277 ISA_SET: AVX512F_256 52278 EXCEPTIONS: AVX512-E2 52279 REAL_OPCODE: Y 52280 ATTRIBUTES: MASKOP_EVEX MXCSR 52281 PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 52282 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 52283 IFORM: VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 52284 } 52285 52286 { 52287 ICLASS: VSQRTPD 52288 CPL: 3 52289 CATEGORY: AVX512 52290 EXTENSION: AVX512EVEX 52291 ISA_SET: AVX512F_256 52292 EXCEPTIONS: AVX512-E2 52293 REAL_OPCODE: Y 52294 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 52295 PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 52296 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR 52297 IFORM: VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 52298 } 52299 52300 52301 # EMITTING VSQRTPS (VSQRTPS-128-1) 52302 { 52303 ICLASS: VSQRTPS 52304 CPL: 3 52305 CATEGORY: AVX512 52306 EXTENSION: AVX512EVEX 52307 ISA_SET: AVX512F_128 52308 EXCEPTIONS: AVX512-E2 52309 REAL_OPCODE: Y 52310 ATTRIBUTES: MASKOP_EVEX MXCSR 52311 PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 52312 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 52313 IFORM: VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 52314 } 52315 52316 { 52317 ICLASS: VSQRTPS 52318 CPL: 3 52319 CATEGORY: AVX512 52320 EXTENSION: AVX512EVEX 52321 ISA_SET: AVX512F_128 52322 EXCEPTIONS: AVX512-E2 52323 REAL_OPCODE: Y 52324 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 52325 PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 52326 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 52327 IFORM: VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 52328 } 52329 52330 52331 # EMITTING VSQRTPS (VSQRTPS-256-1) 52332 { 52333 ICLASS: VSQRTPS 52334 CPL: 3 52335 CATEGORY: AVX512 52336 EXTENSION: AVX512EVEX 52337 ISA_SET: AVX512F_256 52338 EXCEPTIONS: AVX512-E2 52339 REAL_OPCODE: Y 52340 ATTRIBUTES: MASKOP_EVEX MXCSR 52341 PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 52342 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 52343 IFORM: VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 52344 } 52345 52346 { 52347 ICLASS: VSQRTPS 52348 CPL: 3 52349 CATEGORY: AVX512 52350 EXTENSION: AVX512EVEX 52351 ISA_SET: AVX512F_256 52352 EXCEPTIONS: AVX512-E2 52353 REAL_OPCODE: Y 52354 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 52355 PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 52356 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR 52357 IFORM: VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 52358 } 52359 52360 52361 # EMITTING VSUBPD (VSUBPD-128-1) 52362 { 52363 ICLASS: VSUBPD 52364 CPL: 3 52365 CATEGORY: AVX512 52366 EXTENSION: AVX512EVEX 52367 ISA_SET: AVX512F_128 52368 EXCEPTIONS: AVX512-E2 52369 REAL_OPCODE: Y 52370 ATTRIBUTES: MASKOP_EVEX MXCSR 52371 PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 52372 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 52373 IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 52374 } 52375 52376 { 52377 ICLASS: VSUBPD 52378 CPL: 3 52379 CATEGORY: AVX512 52380 EXTENSION: AVX512EVEX 52381 ISA_SET: AVX512F_128 52382 EXCEPTIONS: AVX512-E2 52383 REAL_OPCODE: Y 52384 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 52385 PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 52386 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 52387 IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 52388 } 52389 52390 52391 # EMITTING VSUBPD (VSUBPD-256-1) 52392 { 52393 ICLASS: VSUBPD 52394 CPL: 3 52395 CATEGORY: AVX512 52396 EXTENSION: AVX512EVEX 52397 ISA_SET: AVX512F_256 52398 EXCEPTIONS: AVX512-E2 52399 REAL_OPCODE: Y 52400 ATTRIBUTES: MASKOP_EVEX MXCSR 52401 PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 52402 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 52403 IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 52404 } 52405 52406 { 52407 ICLASS: VSUBPD 52408 CPL: 3 52409 CATEGORY: AVX512 52410 EXTENSION: AVX512EVEX 52411 ISA_SET: AVX512F_256 52412 EXCEPTIONS: AVX512-E2 52413 REAL_OPCODE: Y 52414 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 52415 PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 52416 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 52417 IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 52418 } 52419 52420 52421 # EMITTING VSUBPS (VSUBPS-128-1) 52422 { 52423 ICLASS: VSUBPS 52424 CPL: 3 52425 CATEGORY: AVX512 52426 EXTENSION: AVX512EVEX 52427 ISA_SET: AVX512F_128 52428 EXCEPTIONS: AVX512-E2 52429 REAL_OPCODE: Y 52430 ATTRIBUTES: MASKOP_EVEX MXCSR 52431 PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 52432 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 52433 IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 52434 } 52435 52436 { 52437 ICLASS: VSUBPS 52438 CPL: 3 52439 CATEGORY: AVX512 52440 EXTENSION: AVX512EVEX 52441 ISA_SET: AVX512F_128 52442 EXCEPTIONS: AVX512-E2 52443 REAL_OPCODE: Y 52444 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 52445 PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 52446 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 52447 IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 52448 } 52449 52450 52451 # EMITTING VSUBPS (VSUBPS-256-1) 52452 { 52453 ICLASS: VSUBPS 52454 CPL: 3 52455 CATEGORY: AVX512 52456 EXTENSION: AVX512EVEX 52457 ISA_SET: AVX512F_256 52458 EXCEPTIONS: AVX512-E2 52459 REAL_OPCODE: Y 52460 ATTRIBUTES: MASKOP_EVEX MXCSR 52461 PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 52462 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 52463 IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 52464 } 52465 52466 { 52467 ICLASS: VSUBPS 52468 CPL: 3 52469 CATEGORY: AVX512 52470 EXTENSION: AVX512EVEX 52471 ISA_SET: AVX512F_256 52472 EXCEPTIONS: AVX512-E2 52473 REAL_OPCODE: Y 52474 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED 52475 PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 52476 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 52477 IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 52478 } 52479 52480 52481 # EMITTING VUNPCKHPD (VUNPCKHPD-128-1) 52482 { 52483 ICLASS: VUNPCKHPD 52484 CPL: 3 52485 CATEGORY: AVX512 52486 EXTENSION: AVX512EVEX 52487 ISA_SET: AVX512F_128 52488 EXCEPTIONS: AVX512-E4NF 52489 REAL_OPCODE: Y 52490 ATTRIBUTES: MASKOP_EVEX 52491 PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 52492 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 52493 IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 52494 } 52495 52496 { 52497 ICLASS: VUNPCKHPD 52498 CPL: 3 52499 CATEGORY: AVX512 52500 EXTENSION: AVX512EVEX 52501 ISA_SET: AVX512F_128 52502 EXCEPTIONS: AVX512-E4NF 52503 REAL_OPCODE: Y 52504 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52505 PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 52506 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 52507 IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 52508 } 52509 52510 52511 # EMITTING VUNPCKHPD (VUNPCKHPD-256-1) 52512 { 52513 ICLASS: VUNPCKHPD 52514 CPL: 3 52515 CATEGORY: AVX512 52516 EXTENSION: AVX512EVEX 52517 ISA_SET: AVX512F_256 52518 EXCEPTIONS: AVX512-E4NF 52519 REAL_OPCODE: Y 52520 ATTRIBUTES: MASKOP_EVEX 52521 PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 52522 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 52523 IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 52524 } 52525 52526 { 52527 ICLASS: VUNPCKHPD 52528 CPL: 3 52529 CATEGORY: AVX512 52530 EXTENSION: AVX512EVEX 52531 ISA_SET: AVX512F_256 52532 EXCEPTIONS: AVX512-E4NF 52533 REAL_OPCODE: Y 52534 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52535 PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 52536 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 52537 IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 52538 } 52539 52540 52541 # EMITTING VUNPCKHPS (VUNPCKHPS-128-1) 52542 { 52543 ICLASS: VUNPCKHPS 52544 CPL: 3 52545 CATEGORY: AVX512 52546 EXTENSION: AVX512EVEX 52547 ISA_SET: AVX512F_128 52548 EXCEPTIONS: AVX512-E4NF 52549 REAL_OPCODE: Y 52550 ATTRIBUTES: MASKOP_EVEX 52551 PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 52552 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 52553 IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 52554 } 52555 52556 { 52557 ICLASS: VUNPCKHPS 52558 CPL: 3 52559 CATEGORY: AVX512 52560 EXTENSION: AVX512EVEX 52561 ISA_SET: AVX512F_128 52562 EXCEPTIONS: AVX512-E4NF 52563 REAL_OPCODE: Y 52564 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52565 PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 52566 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 52567 IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 52568 } 52569 52570 52571 # EMITTING VUNPCKHPS (VUNPCKHPS-256-1) 52572 { 52573 ICLASS: VUNPCKHPS 52574 CPL: 3 52575 CATEGORY: AVX512 52576 EXTENSION: AVX512EVEX 52577 ISA_SET: AVX512F_256 52578 EXCEPTIONS: AVX512-E4NF 52579 REAL_OPCODE: Y 52580 ATTRIBUTES: MASKOP_EVEX 52581 PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 52582 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 52583 IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 52584 } 52585 52586 { 52587 ICLASS: VUNPCKHPS 52588 CPL: 3 52589 CATEGORY: AVX512 52590 EXTENSION: AVX512EVEX 52591 ISA_SET: AVX512F_256 52592 EXCEPTIONS: AVX512-E4NF 52593 REAL_OPCODE: Y 52594 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52595 PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 52596 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 52597 IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 52598 } 52599 52600 52601 # EMITTING VUNPCKLPD (VUNPCKLPD-128-1) 52602 { 52603 ICLASS: VUNPCKLPD 52604 CPL: 3 52605 CATEGORY: AVX512 52606 EXTENSION: AVX512EVEX 52607 ISA_SET: AVX512F_128 52608 EXCEPTIONS: AVX512-E4NF 52609 REAL_OPCODE: Y 52610 ATTRIBUTES: MASKOP_EVEX 52611 PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 52612 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 52613 IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 52614 } 52615 52616 { 52617 ICLASS: VUNPCKLPD 52618 CPL: 3 52619 CATEGORY: AVX512 52620 EXTENSION: AVX512EVEX 52621 ISA_SET: AVX512F_128 52622 EXCEPTIONS: AVX512-E4NF 52623 REAL_OPCODE: Y 52624 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52625 PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 52626 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 52627 IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 52628 } 52629 52630 52631 # EMITTING VUNPCKLPD (VUNPCKLPD-256-1) 52632 { 52633 ICLASS: VUNPCKLPD 52634 CPL: 3 52635 CATEGORY: AVX512 52636 EXTENSION: AVX512EVEX 52637 ISA_SET: AVX512F_256 52638 EXCEPTIONS: AVX512-E4NF 52639 REAL_OPCODE: Y 52640 ATTRIBUTES: MASKOP_EVEX 52641 PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 52642 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 52643 IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 52644 } 52645 52646 { 52647 ICLASS: VUNPCKLPD 52648 CPL: 3 52649 CATEGORY: AVX512 52650 EXTENSION: AVX512EVEX 52651 ISA_SET: AVX512F_256 52652 EXCEPTIONS: AVX512-E4NF 52653 REAL_OPCODE: Y 52654 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52655 PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 52656 OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR 52657 IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 52658 } 52659 52660 52661 # EMITTING VUNPCKLPS (VUNPCKLPS-128-1) 52662 { 52663 ICLASS: VUNPCKLPS 52664 CPL: 3 52665 CATEGORY: AVX512 52666 EXTENSION: AVX512EVEX 52667 ISA_SET: AVX512F_128 52668 EXCEPTIONS: AVX512-E4NF 52669 REAL_OPCODE: Y 52670 ATTRIBUTES: MASKOP_EVEX 52671 PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 52672 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 52673 IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 52674 } 52675 52676 { 52677 ICLASS: VUNPCKLPS 52678 CPL: 3 52679 CATEGORY: AVX512 52680 EXTENSION: AVX512EVEX 52681 ISA_SET: AVX512F_128 52682 EXCEPTIONS: AVX512-E4NF 52683 REAL_OPCODE: Y 52684 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52685 PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 52686 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 52687 IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 52688 } 52689 52690 52691 # EMITTING VUNPCKLPS (VUNPCKLPS-256-1) 52692 { 52693 ICLASS: VUNPCKLPS 52694 CPL: 3 52695 CATEGORY: AVX512 52696 EXTENSION: AVX512EVEX 52697 ISA_SET: AVX512F_256 52698 EXCEPTIONS: AVX512-E4NF 52699 REAL_OPCODE: Y 52700 ATTRIBUTES: MASKOP_EVEX 52701 PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 52702 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 52703 IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 52704 } 52705 52706 { 52707 ICLASS: VUNPCKLPS 52708 CPL: 3 52709 CATEGORY: AVX512 52710 EXTENSION: AVX512EVEX 52711 ISA_SET: AVX512F_256 52712 EXCEPTIONS: AVX512-E4NF 52713 REAL_OPCODE: Y 52714 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52715 PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 52716 OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR 52717 IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 52718 } 52719 52720 52721 # EMITTING VXORPD (VXORPD-128-1) 52722 { 52723 ICLASS: VXORPD 52724 CPL: 3 52725 CATEGORY: LOGICAL_FP 52726 EXTENSION: AVX512EVEX 52727 ISA_SET: AVX512DQ_128 52728 EXCEPTIONS: AVX512-E4 52729 REAL_OPCODE: Y 52730 ATTRIBUTES: MASKOP_EVEX 52731 PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 52732 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 52733 IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 52734 } 52735 52736 { 52737 ICLASS: VXORPD 52738 CPL: 3 52739 CATEGORY: LOGICAL_FP 52740 EXTENSION: AVX512EVEX 52741 ISA_SET: AVX512DQ_128 52742 EXCEPTIONS: AVX512-E4 52743 REAL_OPCODE: Y 52744 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52745 PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 52746 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 52747 IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 52748 } 52749 52750 52751 # EMITTING VXORPD (VXORPD-256-1) 52752 { 52753 ICLASS: VXORPD 52754 CPL: 3 52755 CATEGORY: LOGICAL_FP 52756 EXTENSION: AVX512EVEX 52757 ISA_SET: AVX512DQ_256 52758 EXCEPTIONS: AVX512-E4 52759 REAL_OPCODE: Y 52760 ATTRIBUTES: MASKOP_EVEX 52761 PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 52762 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 52763 IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 52764 } 52765 52766 { 52767 ICLASS: VXORPD 52768 CPL: 3 52769 CATEGORY: LOGICAL_FP 52770 EXTENSION: AVX512EVEX 52771 ISA_SET: AVX512DQ_256 52772 EXCEPTIONS: AVX512-E4 52773 REAL_OPCODE: Y 52774 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52775 PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 52776 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 52777 IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 52778 } 52779 52780 52781 # EMITTING VXORPD (VXORPD-512-1) 52782 { 52783 ICLASS: VXORPD 52784 CPL: 3 52785 CATEGORY: LOGICAL_FP 52786 EXTENSION: AVX512EVEX 52787 ISA_SET: AVX512DQ_512 52788 EXCEPTIONS: AVX512-E4 52789 REAL_OPCODE: Y 52790 ATTRIBUTES: MASKOP_EVEX 52791 PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 52792 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 52793 IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 52794 } 52795 52796 { 52797 ICLASS: VXORPD 52798 CPL: 3 52799 CATEGORY: LOGICAL_FP 52800 EXTENSION: AVX512EVEX 52801 ISA_SET: AVX512DQ_512 52802 EXCEPTIONS: AVX512-E4 52803 REAL_OPCODE: Y 52804 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52805 PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 52806 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 52807 IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 52808 } 52809 52810 52811 # EMITTING VXORPS (VXORPS-128-1) 52812 { 52813 ICLASS: VXORPS 52814 CPL: 3 52815 CATEGORY: LOGICAL_FP 52816 EXTENSION: AVX512EVEX 52817 ISA_SET: AVX512DQ_128 52818 EXCEPTIONS: AVX512-E4 52819 REAL_OPCODE: Y 52820 ATTRIBUTES: MASKOP_EVEX 52821 PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 52822 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 52823 IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 52824 } 52825 52826 { 52827 ICLASS: VXORPS 52828 CPL: 3 52829 CATEGORY: LOGICAL_FP 52830 EXTENSION: AVX512EVEX 52831 ISA_SET: AVX512DQ_128 52832 EXCEPTIONS: AVX512-E4 52833 REAL_OPCODE: Y 52834 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52835 PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 52836 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 52837 IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 52838 } 52839 52840 52841 # EMITTING VXORPS (VXORPS-256-1) 52842 { 52843 ICLASS: VXORPS 52844 CPL: 3 52845 CATEGORY: LOGICAL_FP 52846 EXTENSION: AVX512EVEX 52847 ISA_SET: AVX512DQ_256 52848 EXCEPTIONS: AVX512-E4 52849 REAL_OPCODE: Y 52850 ATTRIBUTES: MASKOP_EVEX 52851 PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 52852 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 52853 IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 52854 } 52855 52856 { 52857 ICLASS: VXORPS 52858 CPL: 3 52859 CATEGORY: LOGICAL_FP 52860 EXTENSION: AVX512EVEX 52861 ISA_SET: AVX512DQ_256 52862 EXCEPTIONS: AVX512-E4 52863 REAL_OPCODE: Y 52864 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52865 PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 52866 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 52867 IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 52868 } 52869 52870 52871 # EMITTING VXORPS (VXORPS-512-1) 52872 { 52873 ICLASS: VXORPS 52874 CPL: 3 52875 CATEGORY: LOGICAL_FP 52876 EXTENSION: AVX512EVEX 52877 ISA_SET: AVX512DQ_512 52878 EXCEPTIONS: AVX512-E4 52879 REAL_OPCODE: Y 52880 ATTRIBUTES: MASKOP_EVEX 52881 PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 52882 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 52883 IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 52884 } 52885 52886 { 52887 ICLASS: VXORPS 52888 CPL: 3 52889 CATEGORY: LOGICAL_FP 52890 EXTENSION: AVX512EVEX 52891 ISA_SET: AVX512DQ_512 52892 EXCEPTIONS: AVX512-E4 52893 REAL_OPCODE: Y 52894 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 52895 PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 52896 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 52897 IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 52898 } 52899 52900 52901 AVX_INSTRUCTIONS():: 52902 # EMITTING KADDB (KADDB-256-1) 52903 { 52904 ICLASS: KADDB 52905 CPL: 3 52906 CATEGORY: KMASK 52907 EXTENSION: AVX512VEX 52908 ISA_SET: AVX512DQ_KOP 52909 EXCEPTIONS: AVX512-K20 52910 REAL_OPCODE: Y 52911 ATTRIBUTES: KMASK 52912 PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 52913 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 52914 IFORM: KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 52915 } 52916 52917 52918 # EMITTING KADDD (KADDD-256-1) 52919 { 52920 ICLASS: KADDD 52921 CPL: 3 52922 CATEGORY: KMASK 52923 EXTENSION: AVX512VEX 52924 ISA_SET: AVX512BW_KOP 52925 EXCEPTIONS: AVX512-K20 52926 REAL_OPCODE: Y 52927 ATTRIBUTES: KMASK 52928 PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 52929 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 52930 IFORM: KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 52931 } 52932 52933 52934 # EMITTING KADDQ (KADDQ-256-1) 52935 { 52936 ICLASS: KADDQ 52937 CPL: 3 52938 CATEGORY: KMASK 52939 EXTENSION: AVX512VEX 52940 ISA_SET: AVX512BW_KOP 52941 EXCEPTIONS: AVX512-K20 52942 REAL_OPCODE: Y 52943 ATTRIBUTES: KMASK 52944 PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 52945 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 52946 IFORM: KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 52947 } 52948 52949 52950 # EMITTING KADDW (KADDW-256-1) 52951 { 52952 ICLASS: KADDW 52953 CPL: 3 52954 CATEGORY: KMASK 52955 EXTENSION: AVX512VEX 52956 ISA_SET: AVX512DQ_KOP 52957 EXCEPTIONS: AVX512-K20 52958 REAL_OPCODE: Y 52959 ATTRIBUTES: KMASK 52960 PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 52961 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 52962 IFORM: KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 52963 } 52964 52965 52966 # EMITTING KANDB (KANDB-256-1) 52967 { 52968 ICLASS: KANDB 52969 CPL: 3 52970 CATEGORY: KMASK 52971 EXTENSION: AVX512VEX 52972 ISA_SET: AVX512DQ_KOP 52973 EXCEPTIONS: AVX512-K20 52974 REAL_OPCODE: Y 52975 ATTRIBUTES: KMASK 52976 PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 52977 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 52978 IFORM: KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 52979 } 52980 52981 52982 # EMITTING KANDD (KANDD-256-1) 52983 { 52984 ICLASS: KANDD 52985 CPL: 3 52986 CATEGORY: KMASK 52987 EXTENSION: AVX512VEX 52988 ISA_SET: AVX512BW_KOP 52989 EXCEPTIONS: AVX512-K20 52990 REAL_OPCODE: Y 52991 ATTRIBUTES: KMASK 52992 PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 52993 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 52994 IFORM: KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 52995 } 52996 52997 52998 # EMITTING KANDNB (KANDNB-256-1) 52999 { 53000 ICLASS: KANDNB 53001 CPL: 3 53002 CATEGORY: KMASK 53003 EXTENSION: AVX512VEX 53004 ISA_SET: AVX512DQ_KOP 53005 EXCEPTIONS: AVX512-K20 53006 REAL_OPCODE: Y 53007 ATTRIBUTES: KMASK 53008 PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 53009 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53010 IFORM: KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 53011 } 53012 53013 53014 # EMITTING KANDND (KANDND-256-1) 53015 { 53016 ICLASS: KANDND 53017 CPL: 3 53018 CATEGORY: KMASK 53019 EXTENSION: AVX512VEX 53020 ISA_SET: AVX512BW_KOP 53021 EXCEPTIONS: AVX512-K20 53022 REAL_OPCODE: Y 53023 ATTRIBUTES: KMASK 53024 PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 53025 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53026 IFORM: KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 53027 } 53028 53029 53030 # EMITTING KANDNQ (KANDNQ-256-1) 53031 { 53032 ICLASS: KANDNQ 53033 CPL: 3 53034 CATEGORY: KMASK 53035 EXTENSION: AVX512VEX 53036 ISA_SET: AVX512BW_KOP 53037 EXCEPTIONS: AVX512-K20 53038 REAL_OPCODE: Y 53039 ATTRIBUTES: KMASK 53040 PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 53041 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53042 IFORM: KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 53043 } 53044 53045 53046 # EMITTING KANDQ (KANDQ-256-1) 53047 { 53048 ICLASS: KANDQ 53049 CPL: 3 53050 CATEGORY: KMASK 53051 EXTENSION: AVX512VEX 53052 ISA_SET: AVX512BW_KOP 53053 EXCEPTIONS: AVX512-K20 53054 REAL_OPCODE: Y 53055 ATTRIBUTES: KMASK 53056 PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 53057 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53058 IFORM: KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 53059 } 53060 53061 53062 # EMITTING KMOVB (KMOVB-128-1) 53063 { 53064 ICLASS: KMOVB 53065 CPL: 3 53066 CATEGORY: KMASK 53067 EXTENSION: AVX512VEX 53068 ISA_SET: AVX512DQ_KOP 53069 EXCEPTIONS: AVX512-K21 53070 REAL_OPCODE: Y 53071 ATTRIBUTES: KMASK 53072 PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 53073 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u8 53074 IFORM: KMOVB_MASKmskw_MASKu8_AVX512 53075 } 53076 53077 { 53078 ICLASS: KMOVB 53079 CPL: 3 53080 CATEGORY: KMASK 53081 EXTENSION: AVX512VEX 53082 ISA_SET: AVX512DQ_KOP 53083 EXCEPTIONS: AVX512-K21 53084 REAL_OPCODE: Y 53085 ATTRIBUTES: KMASK 53086 PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR 53087 OPERANDS: REG0=MASK_R():w:mskw MEM0:r:b:u8 53088 IFORM: KMOVB_MASKmskw_MEMu8_AVX512 53089 } 53090 53091 53092 # EMITTING KMOVB (KMOVB-128-2) 53093 { 53094 ICLASS: KMOVB 53095 CPL: 3 53096 CATEGORY: KMASK 53097 EXTENSION: AVX512VEX 53098 ISA_SET: AVX512DQ_KOP 53099 EXCEPTIONS: AVX512-K21 53100 REAL_OPCODE: Y 53101 ATTRIBUTES: KMASK 53102 PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W0 NOVSR 53103 OPERANDS: MEM0:w:b:u8 REG0=MASK_R():r:mskw 53104 IFORM: KMOVB_MEMu8_MASKmskw_AVX512 53105 } 53106 53107 53108 # EMITTING KMOVB (KMOVB-128-3) 53109 { 53110 ICLASS: KMOVB 53111 CPL: 3 53112 CATEGORY: KMASK 53113 EXTENSION: AVX512VEX 53114 ISA_SET: AVX512DQ_KOP 53115 EXCEPTIONS: AVX512-K20 53116 REAL_OPCODE: Y 53117 ATTRIBUTES: KMASK 53118 PATTERN: VV1 0x92 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 53119 OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 53120 IFORM: KMOVB_MASKmskw_GPR32u32_AVX512 53121 } 53122 53123 53124 # EMITTING KMOVB (KMOVB-128-4) 53125 { 53126 ICLASS: KMOVB 53127 CPL: 3 53128 CATEGORY: KMASK 53129 EXTENSION: AVX512VEX 53130 ISA_SET: AVX512DQ_KOP 53131 EXCEPTIONS: AVX512-K20 53132 REAL_OPCODE: Y 53133 ATTRIBUTES: KMASK 53134 PATTERN: VV1 0x93 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 53135 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw 53136 IFORM: KMOVB_GPR32u32_MASKmskw_AVX512 53137 } 53138 53139 53140 # EMITTING KMOVD (KMOVD-128-1) 53141 { 53142 ICLASS: KMOVD 53143 CPL: 3 53144 CATEGORY: KMASK 53145 EXTENSION: AVX512VEX 53146 ISA_SET: AVX512BW_KOP 53147 EXCEPTIONS: AVX512-K21 53148 REAL_OPCODE: Y 53149 ATTRIBUTES: KMASK 53150 PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 53151 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u32 53152 IFORM: KMOVD_MASKmskw_MASKu32_AVX512 53153 } 53154 53155 { 53156 ICLASS: KMOVD 53157 CPL: 3 53158 CATEGORY: KMASK 53159 EXTENSION: AVX512VEX 53160 ISA_SET: AVX512BW_KOP 53161 EXCEPTIONS: AVX512-K21 53162 REAL_OPCODE: Y 53163 ATTRIBUTES: KMASK 53164 PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR 53165 OPERANDS: REG0=MASK_R():w:mskw MEM0:r:d:u32 53166 IFORM: KMOVD_MASKmskw_MEMu32_AVX512 53167 } 53168 53169 53170 # EMITTING KMOVD (KMOVD-128-2) 53171 { 53172 ICLASS: KMOVD 53173 CPL: 3 53174 CATEGORY: KMASK 53175 EXTENSION: AVX512VEX 53176 ISA_SET: AVX512BW_KOP 53177 EXCEPTIONS: AVX512-K21 53178 REAL_OPCODE: Y 53179 ATTRIBUTES: KMASK 53180 PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR 53181 OPERANDS: MEM0:w:d:u32 REG0=MASK_R():r:mskw 53182 IFORM: KMOVD_MEMu32_MASKmskw_AVX512 53183 } 53184 53185 53186 # EMITTING KMOVD (KMOVD-128-3) 53187 { 53188 ICLASS: KMOVD 53189 CPL: 3 53190 CATEGORY: KMASK 53191 EXTENSION: AVX512VEX 53192 ISA_SET: AVX512BW_KOP 53193 EXCEPTIONS: AVX512-K20 53194 REAL_OPCODE: Y 53195 ATTRIBUTES: KMASK 53196 COMMENT: KMOVQ aliases to KMOVD in 32b mode due to W bit being ignored. 53197 PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 mode64 NOVSR 53198 OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 53199 IFORM: KMOVD_MASKmskw_GPR32u32_AVX512 53200 53201 PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 not64 NOVSR 53202 OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 53203 IFORM: KMOVD_MASKmskw_GPR32u32_AVX512 53204 } 53205 53206 53207 # EMITTING KMOVD (KMOVD-128-4) 53208 { 53209 ICLASS: KMOVD 53210 CPL: 3 53211 CATEGORY: KMASK 53212 EXTENSION: AVX512VEX 53213 ISA_SET: AVX512BW_KOP 53214 EXCEPTIONS: AVX512-K20 53215 REAL_OPCODE: Y 53216 ATTRIBUTES: KMASK 53217 COMMENT: KMOVQ aliases to KMOVD in 32b mode due to W bit being ignored. 53218 PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 mode64 NOVSR 53219 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw 53220 IFORM: KMOVD_GPR32u32_MASKmskw_AVX512 53221 53222 PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 not64 NOVSR 53223 OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw 53224 IFORM: KMOVD_GPR32u32_MASKmskw_AVX512 53225 } 53226 53227 53228 # EMITTING KMOVQ (KMOVQ-128-1) 53229 { 53230 ICLASS: KMOVQ 53231 CPL: 3 53232 CATEGORY: KMASK 53233 EXTENSION: AVX512VEX 53234 ISA_SET: AVX512BW_KOP 53235 EXCEPTIONS: AVX512-K21 53236 REAL_OPCODE: Y 53237 ATTRIBUTES: KMASK 53238 PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 53239 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u64 53240 IFORM: KMOVQ_MASKmskw_MASKu64_AVX512 53241 } 53242 53243 { 53244 ICLASS: KMOVQ 53245 CPL: 3 53246 CATEGORY: KMASK 53247 EXTENSION: AVX512VEX 53248 ISA_SET: AVX512BW_KOP 53249 EXCEPTIONS: AVX512-K21 53250 REAL_OPCODE: Y 53251 ATTRIBUTES: KMASK 53252 PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR 53253 OPERANDS: REG0=MASK_R():w:mskw MEM0:r:q:u64 53254 IFORM: KMOVQ_MASKmskw_MEMu64_AVX512 53255 } 53256 53257 53258 # EMITTING KMOVQ (KMOVQ-128-2) 53259 { 53260 ICLASS: KMOVQ 53261 CPL: 3 53262 CATEGORY: KMASK 53263 EXTENSION: AVX512VEX 53264 ISA_SET: AVX512BW_KOP 53265 EXCEPTIONS: AVX512-K21 53266 REAL_OPCODE: Y 53267 ATTRIBUTES: KMASK 53268 PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL=0 W1 NOVSR 53269 OPERANDS: MEM0:w:q:u64 REG0=MASK_R():r:mskw 53270 IFORM: KMOVQ_MEMu64_MASKmskw_AVX512 53271 } 53272 53273 53274 # EMITTING KMOVQ (KMOVQ-128-3) 53275 { 53276 ICLASS: KMOVQ 53277 CPL: 3 53278 CATEGORY: KMASK 53279 EXTENSION: AVX512VEX 53280 ISA_SET: AVX512BW_KOP 53281 EXCEPTIONS: AVX512-K20 53282 REAL_OPCODE: Y 53283 ATTRIBUTES: KMASK 53284 PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 mode64 NOVSR 53285 OPERANDS: REG0=MASK_R():w:mskw REG1=GPR64_B():r:q:u64 53286 IFORM: KMOVQ_MASKmskw_GPR64u64_AVX512 53287 } 53288 53289 53290 # EMITTING KMOVQ (KMOVQ-128-4) 53291 { 53292 ICLASS: KMOVQ 53293 CPL: 3 53294 CATEGORY: KMASK 53295 EXTENSION: AVX512VEX 53296 ISA_SET: AVX512BW_KOP 53297 EXCEPTIONS: AVX512-K20 53298 REAL_OPCODE: Y 53299 ATTRIBUTES: KMASK 53300 PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 mode64 NOVSR 53301 OPERANDS: REG0=GPR64_R():w:q:u64 REG1=MASK_B():r:mskw 53302 IFORM: KMOVQ_GPR64u64_MASKmskw_AVX512 53303 } 53304 53305 53306 # EMITTING KNOTB (KNOTB-128-1) 53307 { 53308 ICLASS: KNOTB 53309 CPL: 3 53310 CATEGORY: KMASK 53311 EXTENSION: AVX512VEX 53312 ISA_SET: AVX512DQ_KOP 53313 EXCEPTIONS: AVX512-K20 53314 REAL_OPCODE: Y 53315 ATTRIBUTES: KMASK 53316 PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 53317 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw 53318 IFORM: KNOTB_MASKmskw_MASKmskw_AVX512 53319 } 53320 53321 53322 # EMITTING KNOTD (KNOTD-128-1) 53323 { 53324 ICLASS: KNOTD 53325 CPL: 3 53326 CATEGORY: KMASK 53327 EXTENSION: AVX512VEX 53328 ISA_SET: AVX512BW_KOP 53329 EXCEPTIONS: AVX512-K20 53330 REAL_OPCODE: Y 53331 ATTRIBUTES: KMASK 53332 PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 53333 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw 53334 IFORM: KNOTD_MASKmskw_MASKmskw_AVX512 53335 } 53336 53337 53338 # EMITTING KNOTQ (KNOTQ-128-1) 53339 { 53340 ICLASS: KNOTQ 53341 CPL: 3 53342 CATEGORY: KMASK 53343 EXTENSION: AVX512VEX 53344 ISA_SET: AVX512BW_KOP 53345 EXCEPTIONS: AVX512-K20 53346 REAL_OPCODE: Y 53347 ATTRIBUTES: KMASK 53348 PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 53349 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw 53350 IFORM: KNOTQ_MASKmskw_MASKmskw_AVX512 53351 } 53352 53353 53354 # EMITTING KORB (KORB-256-1) 53355 { 53356 ICLASS: KORB 53357 CPL: 3 53358 CATEGORY: KMASK 53359 EXTENSION: AVX512VEX 53360 ISA_SET: AVX512DQ_KOP 53361 EXCEPTIONS: AVX512-K20 53362 REAL_OPCODE: Y 53363 ATTRIBUTES: KMASK 53364 PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 53365 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53366 IFORM: KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 53367 } 53368 53369 53370 # EMITTING KORD (KORD-256-1) 53371 { 53372 ICLASS: KORD 53373 CPL: 3 53374 CATEGORY: KMASK 53375 EXTENSION: AVX512VEX 53376 ISA_SET: AVX512BW_KOP 53377 EXCEPTIONS: AVX512-K20 53378 REAL_OPCODE: Y 53379 ATTRIBUTES: KMASK 53380 PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 53381 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53382 IFORM: KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 53383 } 53384 53385 53386 # EMITTING KORQ (KORQ-256-1) 53387 { 53388 ICLASS: KORQ 53389 CPL: 3 53390 CATEGORY: KMASK 53391 EXTENSION: AVX512VEX 53392 ISA_SET: AVX512BW_KOP 53393 EXCEPTIONS: AVX512-K20 53394 REAL_OPCODE: Y 53395 ATTRIBUTES: KMASK 53396 PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 53397 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53398 IFORM: KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 53399 } 53400 53401 53402 # EMITTING KORTESTB (KORTESTB-128-1) 53403 { 53404 ICLASS: KORTESTB 53405 CPL: 3 53406 CATEGORY: KMASK 53407 EXTENSION: AVX512VEX 53408 ISA_SET: AVX512DQ_KOP 53409 EXCEPTIONS: AVX512-K20 53410 REAL_OPCODE: Y 53411 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 53412 ATTRIBUTES: KMASK 53413 PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 53414 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 53415 IFORM: KORTESTB_MASKmskw_MASKmskw_AVX512 53416 } 53417 53418 53419 # EMITTING KORTESTD (KORTESTD-128-1) 53420 { 53421 ICLASS: KORTESTD 53422 CPL: 3 53423 CATEGORY: KMASK 53424 EXTENSION: AVX512VEX 53425 ISA_SET: AVX512BW_KOP 53426 EXCEPTIONS: AVX512-K20 53427 REAL_OPCODE: Y 53428 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 53429 ATTRIBUTES: KMASK 53430 PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 53431 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 53432 IFORM: KORTESTD_MASKmskw_MASKmskw_AVX512 53433 } 53434 53435 53436 # EMITTING KORTESTQ (KORTESTQ-128-1) 53437 { 53438 ICLASS: KORTESTQ 53439 CPL: 3 53440 CATEGORY: KMASK 53441 EXTENSION: AVX512VEX 53442 ISA_SET: AVX512BW_KOP 53443 EXCEPTIONS: AVX512-K20 53444 REAL_OPCODE: Y 53445 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 53446 ATTRIBUTES: KMASK 53447 PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 53448 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 53449 IFORM: KORTESTQ_MASKmskw_MASKmskw_AVX512 53450 } 53451 53452 53453 # EMITTING KSHIFTLB (KSHIFTLB-128-1) 53454 { 53455 ICLASS: KSHIFTLB 53456 CPL: 3 53457 CATEGORY: KMASK 53458 EXTENSION: AVX512VEX 53459 ISA_SET: AVX512DQ_KOP 53460 EXCEPTIONS: AVX512-K20 53461 REAL_OPCODE: Y 53462 ATTRIBUTES: KMASK 53463 PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() 53464 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 53465 IFORM: KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 53466 } 53467 53468 53469 # EMITTING KSHIFTLD (KSHIFTLD-128-1) 53470 { 53471 ICLASS: KSHIFTLD 53472 CPL: 3 53473 CATEGORY: KMASK 53474 EXTENSION: AVX512VEX 53475 ISA_SET: AVX512BW_KOP 53476 EXCEPTIONS: AVX512-K20 53477 REAL_OPCODE: Y 53478 ATTRIBUTES: KMASK 53479 PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() 53480 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 53481 IFORM: KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 53482 } 53483 53484 53485 # EMITTING KSHIFTLQ (KSHIFTLQ-128-1) 53486 { 53487 ICLASS: KSHIFTLQ 53488 CPL: 3 53489 CATEGORY: KMASK 53490 EXTENSION: AVX512VEX 53491 ISA_SET: AVX512BW_KOP 53492 EXCEPTIONS: AVX512-K20 53493 REAL_OPCODE: Y 53494 ATTRIBUTES: KMASK 53495 PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() 53496 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 53497 IFORM: KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 53498 } 53499 53500 53501 # EMITTING KSHIFTRB (KSHIFTRB-128-1) 53502 { 53503 ICLASS: KSHIFTRB 53504 CPL: 3 53505 CATEGORY: KMASK 53506 EXTENSION: AVX512VEX 53507 ISA_SET: AVX512DQ_KOP 53508 EXCEPTIONS: AVX512-K20 53509 REAL_OPCODE: Y 53510 ATTRIBUTES: KMASK 53511 PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() 53512 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 53513 IFORM: KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 53514 } 53515 53516 53517 # EMITTING KSHIFTRD (KSHIFTRD-128-1) 53518 { 53519 ICLASS: KSHIFTRD 53520 CPL: 3 53521 CATEGORY: KMASK 53522 EXTENSION: AVX512VEX 53523 ISA_SET: AVX512BW_KOP 53524 EXCEPTIONS: AVX512-K20 53525 REAL_OPCODE: Y 53526 ATTRIBUTES: KMASK 53527 PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR UIMM8() 53528 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 53529 IFORM: KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 53530 } 53531 53532 53533 # EMITTING KSHIFTRQ (KSHIFTRQ-128-1) 53534 { 53535 ICLASS: KSHIFTRQ 53536 CPL: 3 53537 CATEGORY: KMASK 53538 EXTENSION: AVX512VEX 53539 ISA_SET: AVX512BW_KOP 53540 EXCEPTIONS: AVX512-K20 53541 REAL_OPCODE: Y 53542 ATTRIBUTES: KMASK 53543 PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR UIMM8() 53544 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b 53545 IFORM: KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 53546 } 53547 53548 53549 # EMITTING KTESTB (KTESTB-128-1) 53550 { 53551 ICLASS: KTESTB 53552 CPL: 3 53553 CATEGORY: KMASK 53554 EXTENSION: AVX512VEX 53555 ISA_SET: AVX512DQ_KOP 53556 EXCEPTIONS: AVX512-K20 53557 REAL_OPCODE: Y 53558 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 53559 ATTRIBUTES: KMASK 53560 PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 53561 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 53562 IFORM: KTESTB_MASKmskw_MASKmskw_AVX512 53563 } 53564 53565 53566 # EMITTING KTESTD (KTESTD-128-1) 53567 { 53568 ICLASS: KTESTD 53569 CPL: 3 53570 CATEGORY: KMASK 53571 EXTENSION: AVX512VEX 53572 ISA_SET: AVX512BW_KOP 53573 EXCEPTIONS: AVX512-K20 53574 REAL_OPCODE: Y 53575 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 53576 ATTRIBUTES: KMASK 53577 PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 53578 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 53579 IFORM: KTESTD_MASKmskw_MASKmskw_AVX512 53580 } 53581 53582 53583 # EMITTING KTESTQ (KTESTQ-128-1) 53584 { 53585 ICLASS: KTESTQ 53586 CPL: 3 53587 CATEGORY: KMASK 53588 EXTENSION: AVX512VEX 53589 ISA_SET: AVX512BW_KOP 53590 EXCEPTIONS: AVX512-K20 53591 REAL_OPCODE: Y 53592 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 53593 ATTRIBUTES: KMASK 53594 PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W1 NOVSR 53595 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 53596 IFORM: KTESTQ_MASKmskw_MASKmskw_AVX512 53597 } 53598 53599 53600 # EMITTING KTESTW (KTESTW-128-1) 53601 { 53602 ICLASS: KTESTW 53603 CPL: 3 53604 CATEGORY: KMASK 53605 EXTENSION: AVX512VEX 53606 ISA_SET: AVX512DQ_KOP 53607 EXCEPTIONS: AVX512-K20 53608 REAL_OPCODE: Y 53609 FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] 53610 ATTRIBUTES: KMASK 53611 PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=0 W0 NOVSR 53612 OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw 53613 IFORM: KTESTW_MASKmskw_MASKmskw_AVX512 53614 } 53615 53616 53617 # EMITTING KUNPCKDQ (KUNPCKDQ-256-1) 53618 { 53619 ICLASS: KUNPCKDQ 53620 CPL: 3 53621 CATEGORY: KMASK 53622 EXTENSION: AVX512VEX 53623 ISA_SET: AVX512BW_KOP 53624 EXCEPTIONS: AVX512-K20 53625 REAL_OPCODE: Y 53626 ATTRIBUTES: KMASK 53627 PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 53628 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53629 IFORM: KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 53630 } 53631 53632 53633 # EMITTING KUNPCKWD (KUNPCKWD-256-1) 53634 { 53635 ICLASS: KUNPCKWD 53636 CPL: 3 53637 CATEGORY: KMASK 53638 EXTENSION: AVX512VEX 53639 ISA_SET: AVX512BW_KOP 53640 EXCEPTIONS: AVX512-K20 53641 REAL_OPCODE: Y 53642 ATTRIBUTES: KMASK 53643 PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 53644 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53645 IFORM: KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 53646 } 53647 53648 53649 # EMITTING KXNORB (KXNORB-256-1) 53650 { 53651 ICLASS: KXNORB 53652 CPL: 3 53653 CATEGORY: KMASK 53654 EXTENSION: AVX512VEX 53655 ISA_SET: AVX512DQ_KOP 53656 EXCEPTIONS: AVX512-K20 53657 REAL_OPCODE: Y 53658 ATTRIBUTES: KMASK 53659 PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 53660 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53661 IFORM: KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 53662 } 53663 53664 53665 # EMITTING KXNORD (KXNORD-256-1) 53666 { 53667 ICLASS: KXNORD 53668 CPL: 3 53669 CATEGORY: KMASK 53670 EXTENSION: AVX512VEX 53671 ISA_SET: AVX512BW_KOP 53672 EXCEPTIONS: AVX512-K20 53673 REAL_OPCODE: Y 53674 ATTRIBUTES: KMASK 53675 PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 53676 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53677 IFORM: KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 53678 } 53679 53680 53681 # EMITTING KXNORQ (KXNORQ-256-1) 53682 { 53683 ICLASS: KXNORQ 53684 CPL: 3 53685 CATEGORY: KMASK 53686 EXTENSION: AVX512VEX 53687 ISA_SET: AVX512BW_KOP 53688 EXCEPTIONS: AVX512-K20 53689 REAL_OPCODE: Y 53690 ATTRIBUTES: KMASK 53691 PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 53692 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53693 IFORM: KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 53694 } 53695 53696 53697 # EMITTING KXORB (KXORB-256-1) 53698 { 53699 ICLASS: KXORB 53700 CPL: 3 53701 CATEGORY: KMASK 53702 EXTENSION: AVX512VEX 53703 ISA_SET: AVX512DQ_KOP 53704 EXCEPTIONS: AVX512-K20 53705 REAL_OPCODE: Y 53706 ATTRIBUTES: KMASK 53707 PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W0 53708 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53709 IFORM: KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 53710 } 53711 53712 53713 # EMITTING KXORD (KXORD-256-1) 53714 { 53715 ICLASS: KXORD 53716 CPL: 3 53717 CATEGORY: KMASK 53718 EXTENSION: AVX512VEX 53719 ISA_SET: AVX512BW_KOP 53720 EXCEPTIONS: AVX512-K20 53721 REAL_OPCODE: Y 53722 ATTRIBUTES: KMASK 53723 PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 53724 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53725 IFORM: KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 53726 } 53727 53728 53729 # EMITTING KXORQ (KXORQ-256-1) 53730 { 53731 ICLASS: KXORQ 53732 CPL: 3 53733 CATEGORY: KMASK 53734 EXTENSION: AVX512VEX 53735 ISA_SET: AVX512BW_KOP 53736 EXCEPTIONS: AVX512-K20 53737 REAL_OPCODE: Y 53738 ATTRIBUTES: KMASK 53739 PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL=1 W1 53740 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw 53741 IFORM: KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 53742 } 53743 53744 53745 53746 ###FILE: ./datafiles/avx512ifma/ifma-isa.xed.txt 53747 53748 #BEGIN_LEGAL 53749 # 53750 #Copyright (c) 2016 Intel Corporation 53751 # 53752 # Licensed under the Apache License, Version 2.0 (the "License"); 53753 # you may not use this file except in compliance with the License. 53754 # You may obtain a copy of the License at 53755 # 53756 # http://www.apache.org/licenses/LICENSE-2.0 53757 # 53758 # Unless required by applicable law or agreed to in writing, software 53759 # distributed under the License is distributed on an "AS IS" BASIS, 53760 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 53761 # See the License for the specific language governing permissions and 53762 # limitations under the License. 53763 # 53764 #END_LEGAL 53765 # 53766 # 53767 # 53768 # ***** GENERATED FILE -- DO NOT EDIT! ***** 53769 # ***** GENERATED FILE -- DO NOT EDIT! ***** 53770 # ***** GENERATED FILE -- DO NOT EDIT! ***** 53771 # 53772 # 53773 # 53774 EVEX_INSTRUCTIONS():: 53775 # EMITTING VPMADD52HUQ (VPMADD52HUQ-128-1) 53776 { 53777 ICLASS: VPMADD52HUQ 53778 CPL: 3 53779 CATEGORY: IFMA 53780 EXTENSION: AVX512EVEX 53781 ISA_SET: AVX512_IFMA_128 53782 EXCEPTIONS: AVX512-E4 53783 REAL_OPCODE: Y 53784 ATTRIBUTES: MASKOP_EVEX 53785 PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 53786 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 53787 IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 53788 } 53789 53790 { 53791 ICLASS: VPMADD52HUQ 53792 CPL: 3 53793 CATEGORY: IFMA 53794 EXTENSION: AVX512EVEX 53795 ISA_SET: AVX512_IFMA_128 53796 EXCEPTIONS: AVX512-E4 53797 REAL_OPCODE: Y 53798 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 53799 PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 53800 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 53801 IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 53802 } 53803 53804 53805 # EMITTING VPMADD52HUQ (VPMADD52HUQ-256-1) 53806 { 53807 ICLASS: VPMADD52HUQ 53808 CPL: 3 53809 CATEGORY: IFMA 53810 EXTENSION: AVX512EVEX 53811 ISA_SET: AVX512_IFMA_256 53812 EXCEPTIONS: AVX512-E4 53813 REAL_OPCODE: Y 53814 ATTRIBUTES: MASKOP_EVEX 53815 PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 53816 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 53817 IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 53818 } 53819 53820 { 53821 ICLASS: VPMADD52HUQ 53822 CPL: 3 53823 CATEGORY: IFMA 53824 EXTENSION: AVX512EVEX 53825 ISA_SET: AVX512_IFMA_256 53826 EXCEPTIONS: AVX512-E4 53827 REAL_OPCODE: Y 53828 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 53829 PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 53830 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 53831 IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 53832 } 53833 53834 53835 # EMITTING VPMADD52HUQ (VPMADD52HUQ-512-1) 53836 { 53837 ICLASS: VPMADD52HUQ 53838 CPL: 3 53839 CATEGORY: IFMA 53840 EXTENSION: AVX512EVEX 53841 ISA_SET: AVX512_IFMA_512 53842 EXCEPTIONS: AVX512-E4 53843 REAL_OPCODE: Y 53844 ATTRIBUTES: MASKOP_EVEX 53845 PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 53846 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 53847 IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 53848 } 53849 53850 { 53851 ICLASS: VPMADD52HUQ 53852 CPL: 3 53853 CATEGORY: IFMA 53854 EXTENSION: AVX512EVEX 53855 ISA_SET: AVX512_IFMA_512 53856 EXCEPTIONS: AVX512-E4 53857 REAL_OPCODE: Y 53858 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 53859 PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 53860 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 53861 IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 53862 } 53863 53864 53865 # EMITTING VPMADD52LUQ (VPMADD52LUQ-128-1) 53866 { 53867 ICLASS: VPMADD52LUQ 53868 CPL: 3 53869 CATEGORY: IFMA 53870 EXTENSION: AVX512EVEX 53871 ISA_SET: AVX512_IFMA_128 53872 EXCEPTIONS: AVX512-E4 53873 REAL_OPCODE: Y 53874 ATTRIBUTES: MASKOP_EVEX 53875 PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 53876 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 53877 IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 53878 } 53879 53880 { 53881 ICLASS: VPMADD52LUQ 53882 CPL: 3 53883 CATEGORY: IFMA 53884 EXTENSION: AVX512EVEX 53885 ISA_SET: AVX512_IFMA_128 53886 EXCEPTIONS: AVX512-E4 53887 REAL_OPCODE: Y 53888 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 53889 PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 53890 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 53891 IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 53892 } 53893 53894 53895 # EMITTING VPMADD52LUQ (VPMADD52LUQ-256-1) 53896 { 53897 ICLASS: VPMADD52LUQ 53898 CPL: 3 53899 CATEGORY: IFMA 53900 EXTENSION: AVX512EVEX 53901 ISA_SET: AVX512_IFMA_256 53902 EXCEPTIONS: AVX512-E4 53903 REAL_OPCODE: Y 53904 ATTRIBUTES: MASKOP_EVEX 53905 PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 53906 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 53907 IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 53908 } 53909 53910 { 53911 ICLASS: VPMADD52LUQ 53912 CPL: 3 53913 CATEGORY: IFMA 53914 EXTENSION: AVX512EVEX 53915 ISA_SET: AVX512_IFMA_256 53916 EXCEPTIONS: AVX512-E4 53917 REAL_OPCODE: Y 53918 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 53919 PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 53920 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 53921 IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 53922 } 53923 53924 53925 # EMITTING VPMADD52LUQ (VPMADD52LUQ-512-1) 53926 { 53927 ICLASS: VPMADD52LUQ 53928 CPL: 3 53929 CATEGORY: IFMA 53930 EXTENSION: AVX512EVEX 53931 ISA_SET: AVX512_IFMA_512 53932 EXCEPTIONS: AVX512-E4 53933 REAL_OPCODE: Y 53934 ATTRIBUTES: MASKOP_EVEX 53935 PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 53936 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 53937 IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 53938 } 53939 53940 { 53941 ICLASS: VPMADD52LUQ 53942 CPL: 3 53943 CATEGORY: IFMA 53944 EXTENSION: AVX512EVEX 53945 ISA_SET: AVX512_IFMA_512 53946 EXCEPTIONS: AVX512-E4 53947 REAL_OPCODE: Y 53948 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 53949 PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 53950 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 53951 IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 53952 } 53953 53954 53955 53956 53957 ###FILE: ./datafiles/avx512vbmi/vbmi-isa.xed.txt 53958 53959 #BEGIN_LEGAL 53960 # 53961 #Copyright (c) 2016 Intel Corporation 53962 # 53963 # Licensed under the Apache License, Version 2.0 (the "License"); 53964 # you may not use this file except in compliance with the License. 53965 # You may obtain a copy of the License at 53966 # 53967 # http://www.apache.org/licenses/LICENSE-2.0 53968 # 53969 # Unless required by applicable law or agreed to in writing, software 53970 # distributed under the License is distributed on an "AS IS" BASIS, 53971 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 53972 # See the License for the specific language governing permissions and 53973 # limitations under the License. 53974 # 53975 #END_LEGAL 53976 # 53977 # 53978 # 53979 # ***** GENERATED FILE -- DO NOT EDIT! ***** 53980 # ***** GENERATED FILE -- DO NOT EDIT! ***** 53981 # ***** GENERATED FILE -- DO NOT EDIT! ***** 53982 # 53983 # 53984 # 53985 EVEX_INSTRUCTIONS():: 53986 # EMITTING VPERMB (VPERMB-128-1) 53987 { 53988 ICLASS: VPERMB 53989 CPL: 3 53990 CATEGORY: AVX512_VBMI 53991 EXTENSION: AVX512EVEX 53992 ISA_SET: AVX512_VBMI_128 53993 EXCEPTIONS: AVX512-E4NF 53994 REAL_OPCODE: Y 53995 ATTRIBUTES: MASKOP_EVEX 53996 PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 53997 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 53998 IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 53999 } 54000 54001 { 54002 ICLASS: VPERMB 54003 CPL: 3 54004 CATEGORY: AVX512_VBMI 54005 EXTENSION: AVX512EVEX 54006 ISA_SET: AVX512_VBMI_128 54007 EXCEPTIONS: AVX512-E4NF 54008 REAL_OPCODE: Y 54009 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 54010 PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() 54011 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 54012 IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 54013 } 54014 54015 54016 # EMITTING VPERMB (VPERMB-256-1) 54017 { 54018 ICLASS: VPERMB 54019 CPL: 3 54020 CATEGORY: AVX512_VBMI 54021 EXTENSION: AVX512EVEX 54022 ISA_SET: AVX512_VBMI_256 54023 EXCEPTIONS: AVX512-E4NF 54024 REAL_OPCODE: Y 54025 ATTRIBUTES: MASKOP_EVEX 54026 PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 54027 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 54028 IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 54029 } 54030 54031 { 54032 ICLASS: VPERMB 54033 CPL: 3 54034 CATEGORY: AVX512_VBMI 54035 EXTENSION: AVX512EVEX 54036 ISA_SET: AVX512_VBMI_256 54037 EXCEPTIONS: AVX512-E4NF 54038 REAL_OPCODE: Y 54039 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 54040 PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() 54041 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 54042 IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 54043 } 54044 54045 54046 # EMITTING VPERMB (VPERMB-512-1) 54047 { 54048 ICLASS: VPERMB 54049 CPL: 3 54050 CATEGORY: AVX512_VBMI 54051 EXTENSION: AVX512EVEX 54052 ISA_SET: AVX512_VBMI_512 54053 EXCEPTIONS: AVX512-E4NF 54054 REAL_OPCODE: Y 54055 ATTRIBUTES: MASKOP_EVEX 54056 PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 54057 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 54058 IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 54059 } 54060 54061 { 54062 ICLASS: VPERMB 54063 CPL: 3 54064 CATEGORY: AVX512_VBMI 54065 EXTENSION: AVX512EVEX 54066 ISA_SET: AVX512_VBMI_512 54067 EXCEPTIONS: AVX512-E4NF 54068 REAL_OPCODE: Y 54069 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 54070 PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() 54071 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 54072 IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 54073 } 54074 54075 54076 # EMITTING VPERMI2B (VPERMI2B-128-1) 54077 { 54078 ICLASS: VPERMI2B 54079 CPL: 3 54080 CATEGORY: AVX512_VBMI 54081 EXTENSION: AVX512EVEX 54082 ISA_SET: AVX512_VBMI_128 54083 EXCEPTIONS: AVX512-E4NF 54084 REAL_OPCODE: Y 54085 ATTRIBUTES: MASKOP_EVEX 54086 PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 54087 OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 54088 IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 54089 } 54090 54091 { 54092 ICLASS: VPERMI2B 54093 CPL: 3 54094 CATEGORY: AVX512_VBMI 54095 EXTENSION: AVX512EVEX 54096 ISA_SET: AVX512_VBMI_128 54097 EXCEPTIONS: AVX512-E4NF 54098 REAL_OPCODE: Y 54099 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 54100 PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() 54101 OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 54102 IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 54103 } 54104 54105 54106 # EMITTING VPERMI2B (VPERMI2B-256-1) 54107 { 54108 ICLASS: VPERMI2B 54109 CPL: 3 54110 CATEGORY: AVX512_VBMI 54111 EXTENSION: AVX512EVEX 54112 ISA_SET: AVX512_VBMI_256 54113 EXCEPTIONS: AVX512-E4NF 54114 REAL_OPCODE: Y 54115 ATTRIBUTES: MASKOP_EVEX 54116 PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 54117 OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 54118 IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 54119 } 54120 54121 { 54122 ICLASS: VPERMI2B 54123 CPL: 3 54124 CATEGORY: AVX512_VBMI 54125 EXTENSION: AVX512EVEX 54126 ISA_SET: AVX512_VBMI_256 54127 EXCEPTIONS: AVX512-E4NF 54128 REAL_OPCODE: Y 54129 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 54130 PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() 54131 OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 54132 IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 54133 } 54134 54135 54136 # EMITTING VPERMI2B (VPERMI2B-512-1) 54137 { 54138 ICLASS: VPERMI2B 54139 CPL: 3 54140 CATEGORY: AVX512_VBMI 54141 EXTENSION: AVX512EVEX 54142 ISA_SET: AVX512_VBMI_512 54143 EXCEPTIONS: AVX512-E4NF 54144 REAL_OPCODE: Y 54145 ATTRIBUTES: MASKOP_EVEX 54146 PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 54147 OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 54148 IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 54149 } 54150 54151 { 54152 ICLASS: VPERMI2B 54153 CPL: 3 54154 CATEGORY: AVX512_VBMI 54155 EXTENSION: AVX512EVEX 54156 ISA_SET: AVX512_VBMI_512 54157 EXCEPTIONS: AVX512-E4NF 54158 REAL_OPCODE: Y 54159 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 54160 PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() 54161 OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 54162 IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 54163 } 54164 54165 54166 # EMITTING VPERMT2B (VPERMT2B-128-1) 54167 { 54168 ICLASS: VPERMT2B 54169 CPL: 3 54170 CATEGORY: AVX512_VBMI 54171 EXTENSION: AVX512EVEX 54172 ISA_SET: AVX512_VBMI_128 54173 EXCEPTIONS: AVX512-E4NF 54174 REAL_OPCODE: Y 54175 ATTRIBUTES: MASKOP_EVEX 54176 PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 54177 OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 54178 IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 54179 } 54180 54181 { 54182 ICLASS: VPERMT2B 54183 CPL: 3 54184 CATEGORY: AVX512_VBMI 54185 EXTENSION: AVX512EVEX 54186 ISA_SET: AVX512_VBMI_128 54187 EXCEPTIONS: AVX512-E4NF 54188 REAL_OPCODE: Y 54189 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 54190 PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() 54191 OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 54192 IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 54193 } 54194 54195 54196 # EMITTING VPERMT2B (VPERMT2B-256-1) 54197 { 54198 ICLASS: VPERMT2B 54199 CPL: 3 54200 CATEGORY: AVX512_VBMI 54201 EXTENSION: AVX512EVEX 54202 ISA_SET: AVX512_VBMI_256 54203 EXCEPTIONS: AVX512-E4NF 54204 REAL_OPCODE: Y 54205 ATTRIBUTES: MASKOP_EVEX 54206 PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 54207 OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 54208 IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 54209 } 54210 54211 { 54212 ICLASS: VPERMT2B 54213 CPL: 3 54214 CATEGORY: AVX512_VBMI 54215 EXTENSION: AVX512EVEX 54216 ISA_SET: AVX512_VBMI_256 54217 EXCEPTIONS: AVX512-E4NF 54218 REAL_OPCODE: Y 54219 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 54220 PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() 54221 OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 54222 IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 54223 } 54224 54225 54226 # EMITTING VPERMT2B (VPERMT2B-512-1) 54227 { 54228 ICLASS: VPERMT2B 54229 CPL: 3 54230 CATEGORY: AVX512_VBMI 54231 EXTENSION: AVX512EVEX 54232 ISA_SET: AVX512_VBMI_512 54233 EXCEPTIONS: AVX512-E4NF 54234 REAL_OPCODE: Y 54235 ATTRIBUTES: MASKOP_EVEX 54236 PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 54237 OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 54238 IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 54239 } 54240 54241 { 54242 ICLASS: VPERMT2B 54243 CPL: 3 54244 CATEGORY: AVX512_VBMI 54245 EXTENSION: AVX512EVEX 54246 ISA_SET: AVX512_VBMI_512 54247 EXCEPTIONS: AVX512-E4NF 54248 REAL_OPCODE: Y 54249 ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM 54250 PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() 54251 OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 54252 IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 54253 } 54254 54255 54256 # EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-128-1) 54257 { 54258 ICLASS: VPMULTISHIFTQB 54259 CPL: 3 54260 CATEGORY: AVX512_VBMI 54261 EXTENSION: AVX512EVEX 54262 ISA_SET: AVX512_VBMI_128 54263 EXCEPTIONS: AVX512-E4NF 54264 REAL_OPCODE: Y 54265 ATTRIBUTES: MASKOP_EVEX 54266 PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 54267 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 54268 IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 54269 } 54270 54271 { 54272 ICLASS: VPMULTISHIFTQB 54273 CPL: 3 54274 CATEGORY: AVX512_VBMI 54275 EXTENSION: AVX512EVEX 54276 ISA_SET: AVX512_VBMI_128 54277 EXCEPTIONS: AVX512-E4NF 54278 REAL_OPCODE: Y 54279 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54280 PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 54281 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR 54282 IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 54283 } 54284 54285 54286 # EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-256-1) 54287 { 54288 ICLASS: VPMULTISHIFTQB 54289 CPL: 3 54290 CATEGORY: AVX512_VBMI 54291 EXTENSION: AVX512EVEX 54292 ISA_SET: AVX512_VBMI_256 54293 EXCEPTIONS: AVX512-E4NF 54294 REAL_OPCODE: Y 54295 ATTRIBUTES: MASKOP_EVEX 54296 PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 54297 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 54298 IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 54299 } 54300 54301 { 54302 ICLASS: VPMULTISHIFTQB 54303 CPL: 3 54304 CATEGORY: AVX512_VBMI 54305 EXTENSION: AVX512EVEX 54306 ISA_SET: AVX512_VBMI_256 54307 EXCEPTIONS: AVX512-E4NF 54308 REAL_OPCODE: Y 54309 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54310 PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 54311 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR 54312 IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 54313 } 54314 54315 54316 # EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-512-1) 54317 { 54318 ICLASS: VPMULTISHIFTQB 54319 CPL: 3 54320 CATEGORY: AVX512_VBMI 54321 EXTENSION: AVX512EVEX 54322 ISA_SET: AVX512_VBMI_512 54323 EXCEPTIONS: AVX512-E4NF 54324 REAL_OPCODE: Y 54325 ATTRIBUTES: MASKOP_EVEX 54326 PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 54327 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 54328 IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 54329 } 54330 54331 { 54332 ICLASS: VPMULTISHIFTQB 54333 CPL: 3 54334 CATEGORY: AVX512_VBMI 54335 EXTENSION: AVX512EVEX 54336 ISA_SET: AVX512_VBMI_512 54337 EXCEPTIONS: AVX512-E4NF 54338 REAL_OPCODE: Y 54339 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 54340 PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 54341 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR 54342 IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 54343 } 54344 54345 54346 54347 54348 ###FILE: ./datafiles/bitalg/bitalg-isa.xed.txt 54349 54350 #BEGIN_LEGAL 54351 # 54352 #Copyright (c) 2017 Intel Corporation 54353 # 54354 # Licensed under the Apache License, Version 2.0 (the "License"); 54355 # you may not use this file except in compliance with the License. 54356 # You may obtain a copy of the License at 54357 # 54358 # http://www.apache.org/licenses/LICENSE-2.0 54359 # 54360 # Unless required by applicable law or agreed to in writing, software 54361 # distributed under the License is distributed on an "AS IS" BASIS, 54362 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 54363 # See the License for the specific language governing permissions and 54364 # limitations under the License. 54365 # 54366 #END_LEGAL 54367 # 54368 # 54369 # 54370 # ***** GENERATED FILE -- DO NOT EDIT! ***** 54371 # ***** GENERATED FILE -- DO NOT EDIT! ***** 54372 # ***** GENERATED FILE -- DO NOT EDIT! ***** 54373 # 54374 # 54375 # 54376 EVEX_INSTRUCTIONS():: 54377 # EMITTING VPOPCNTB (VPOPCNTB-128-1) 54378 { 54379 ICLASS: VPOPCNTB 54380 CPL: 3 54381 CATEGORY: AVX512 54382 EXTENSION: AVX512EVEX 54383 ISA_SET: AVX512_BITALG_128 54384 EXCEPTIONS: AVX512-E4 54385 REAL_OPCODE: Y 54386 ATTRIBUTES: MASKOP_EVEX 54387 PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 54388 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 54389 IFORM: VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 54390 } 54391 54392 { 54393 ICLASS: VPOPCNTB 54394 CPL: 3 54395 CATEGORY: AVX512 54396 EXTENSION: AVX512EVEX 54397 ISA_SET: AVX512_BITALG_128 54398 EXCEPTIONS: AVX512-E4 54399 REAL_OPCODE: Y 54400 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54401 PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 54402 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 54403 IFORM: VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 54404 } 54405 54406 54407 # EMITTING VPOPCNTB (VPOPCNTB-256-1) 54408 { 54409 ICLASS: VPOPCNTB 54410 CPL: 3 54411 CATEGORY: AVX512 54412 EXTENSION: AVX512EVEX 54413 ISA_SET: AVX512_BITALG_256 54414 EXCEPTIONS: AVX512-E4 54415 REAL_OPCODE: Y 54416 ATTRIBUTES: MASKOP_EVEX 54417 PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 54418 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 54419 IFORM: VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 54420 } 54421 54422 { 54423 ICLASS: VPOPCNTB 54424 CPL: 3 54425 CATEGORY: AVX512 54426 EXTENSION: AVX512EVEX 54427 ISA_SET: AVX512_BITALG_256 54428 EXCEPTIONS: AVX512-E4 54429 REAL_OPCODE: Y 54430 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54431 PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 54432 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 54433 IFORM: VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 54434 } 54435 54436 54437 # EMITTING VPOPCNTB (VPOPCNTB-512-1) 54438 { 54439 ICLASS: VPOPCNTB 54440 CPL: 3 54441 CATEGORY: AVX512_BITALG 54442 EXTENSION: AVX512EVEX 54443 ISA_SET: AVX512_BITALG_512 54444 EXCEPTIONS: AVX512-E4 54445 REAL_OPCODE: Y 54446 ATTRIBUTES: MASKOP_EVEX 54447 PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 54448 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 54449 IFORM: VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 54450 } 54451 54452 { 54453 ICLASS: VPOPCNTB 54454 CPL: 3 54455 CATEGORY: AVX512_BITALG 54456 EXTENSION: AVX512EVEX 54457 ISA_SET: AVX512_BITALG_512 54458 EXCEPTIONS: AVX512-E4 54459 REAL_OPCODE: Y 54460 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54461 PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() 54462 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 54463 IFORM: VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 54464 } 54465 54466 54467 # EMITTING VPOPCNTW (VPOPCNTW-128-1) 54468 { 54469 ICLASS: VPOPCNTW 54470 CPL: 3 54471 CATEGORY: AVX512 54472 EXTENSION: AVX512EVEX 54473 ISA_SET: AVX512_BITALG_128 54474 EXCEPTIONS: AVX512-E4 54475 REAL_OPCODE: Y 54476 ATTRIBUTES: MASKOP_EVEX 54477 PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 54478 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 54479 IFORM: VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 54480 } 54481 54482 { 54483 ICLASS: VPOPCNTW 54484 CPL: 3 54485 CATEGORY: AVX512 54486 EXTENSION: AVX512EVEX 54487 ISA_SET: AVX512_BITALG_128 54488 EXCEPTIONS: AVX512-E4 54489 REAL_OPCODE: Y 54490 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54491 PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 54492 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 54493 IFORM: VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 54494 } 54495 54496 54497 # EMITTING VPOPCNTW (VPOPCNTW-256-1) 54498 { 54499 ICLASS: VPOPCNTW 54500 CPL: 3 54501 CATEGORY: AVX512 54502 EXTENSION: AVX512EVEX 54503 ISA_SET: AVX512_BITALG_256 54504 EXCEPTIONS: AVX512-E4 54505 REAL_OPCODE: Y 54506 ATTRIBUTES: MASKOP_EVEX 54507 PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 54508 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 54509 IFORM: VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 54510 } 54511 54512 { 54513 ICLASS: VPOPCNTW 54514 CPL: 3 54515 CATEGORY: AVX512 54516 EXTENSION: AVX512EVEX 54517 ISA_SET: AVX512_BITALG_256 54518 EXCEPTIONS: AVX512-E4 54519 REAL_OPCODE: Y 54520 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54521 PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 54522 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 54523 IFORM: VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 54524 } 54525 54526 54527 # EMITTING VPOPCNTW (VPOPCNTW-512-1) 54528 { 54529 ICLASS: VPOPCNTW 54530 CPL: 3 54531 CATEGORY: AVX512_BITALG 54532 EXTENSION: AVX512EVEX 54533 ISA_SET: AVX512_BITALG_512 54534 EXCEPTIONS: AVX512-E4 54535 REAL_OPCODE: Y 54536 ATTRIBUTES: MASKOP_EVEX 54537 PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 54538 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 54539 IFORM: VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 54540 } 54541 54542 { 54543 ICLASS: VPOPCNTW 54544 CPL: 3 54545 CATEGORY: AVX512_BITALG 54546 EXTENSION: AVX512EVEX 54547 ISA_SET: AVX512_BITALG_512 54548 EXCEPTIONS: AVX512-E4 54549 REAL_OPCODE: Y 54550 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54551 PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() 54552 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 54553 IFORM: VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 54554 } 54555 54556 54557 # EMITTING VPSHUFBITQMB (VPSHUFBITQMB-128-1) 54558 { 54559 ICLASS: VPSHUFBITQMB 54560 CPL: 3 54561 CATEGORY: AVX512 54562 EXTENSION: AVX512EVEX 54563 ISA_SET: AVX512_BITALG_128 54564 EXCEPTIONS: AVX512-E4 54565 REAL_OPCODE: Y 54566 ATTRIBUTES: MASKOP_EVEX 54567 PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 54568 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u8 54569 IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 54570 } 54571 54572 { 54573 ICLASS: VPSHUFBITQMB 54574 CPL: 3 54575 CATEGORY: AVX512 54576 EXTENSION: AVX512EVEX 54577 ISA_SET: AVX512_BITALG_128 54578 EXCEPTIONS: AVX512-E4 54579 REAL_OPCODE: Y 54580 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54581 PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 54582 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u8 54583 IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 54584 } 54585 54586 54587 # EMITTING VPSHUFBITQMB (VPSHUFBITQMB-256-1) 54588 { 54589 ICLASS: VPSHUFBITQMB 54590 CPL: 3 54591 CATEGORY: AVX512 54592 EXTENSION: AVX512EVEX 54593 ISA_SET: AVX512_BITALG_256 54594 EXCEPTIONS: AVX512-E4 54595 REAL_OPCODE: Y 54596 ATTRIBUTES: MASKOP_EVEX 54597 PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 54598 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u8 54599 IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 54600 } 54601 54602 { 54603 ICLASS: VPSHUFBITQMB 54604 CPL: 3 54605 CATEGORY: AVX512 54606 EXTENSION: AVX512EVEX 54607 ISA_SET: AVX512_BITALG_256 54608 EXCEPTIONS: AVX512-E4 54609 REAL_OPCODE: Y 54610 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54611 PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 54612 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:qq:u8 54613 IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 54614 } 54615 54616 54617 # EMITTING VPSHUFBITQMB (VPSHUFBITQMB-512-1) 54618 { 54619 ICLASS: VPSHUFBITQMB 54620 CPL: 3 54621 CATEGORY: AVX512_BITALG 54622 EXTENSION: AVX512EVEX 54623 ISA_SET: AVX512_BITALG_512 54624 EXCEPTIONS: AVX512-E4 54625 REAL_OPCODE: Y 54626 ATTRIBUTES: MASKOP_EVEX 54627 PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 54628 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu8 54629 IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 54630 } 54631 54632 { 54633 ICLASS: VPSHUFBITQMB 54634 CPL: 3 54635 CATEGORY: AVX512_BITALG 54636 EXTENSION: AVX512EVEX 54637 ISA_SET: AVX512_BITALG_512 54638 EXCEPTIONS: AVX512-E4 54639 REAL_OPCODE: Y 54640 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 54641 PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() 54642 OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:zd:u8 54643 IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 54644 } 54645 54646 54647 54648 54649 ###FILE: ./datafiles/vbmi2/vbmi2-isa.xed.txt 54650 54651 #BEGIN_LEGAL 54652 # 54653 #Copyright (c) 2017 Intel Corporation 54654 # 54655 # Licensed under the Apache License, Version 2.0 (the "License"); 54656 # you may not use this file except in compliance with the License. 54657 # You may obtain a copy of the License at 54658 # 54659 # http://www.apache.org/licenses/LICENSE-2.0 54660 # 54661 # Unless required by applicable law or agreed to in writing, software 54662 # distributed under the License is distributed on an "AS IS" BASIS, 54663 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 54664 # See the License for the specific language governing permissions and 54665 # limitations under the License. 54666 # 54667 #END_LEGAL 54668 # 54669 # 54670 # 54671 # ***** GENERATED FILE -- DO NOT EDIT! ***** 54672 # ***** GENERATED FILE -- DO NOT EDIT! ***** 54673 # ***** GENERATED FILE -- DO NOT EDIT! ***** 54674 # 54675 # 54676 # 54677 EVEX_INSTRUCTIONS():: 54678 # EMITTING VPCOMPRESSB (VPCOMPRESSB-128-1) 54679 { 54680 ICLASS: VPCOMPRESSB 54681 CPL: 3 54682 CATEGORY: COMPRESS 54683 EXTENSION: AVX512EVEX 54684 ISA_SET: AVX512_VBMI2_128 54685 EXCEPTIONS: AVX512-E4 54686 REAL_OPCODE: Y 54687 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 54688 PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() 54689 OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8 54690 IFORM: VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 54691 } 54692 54693 54694 # EMITTING VPCOMPRESSB (VPCOMPRESSB-128-2) 54695 { 54696 ICLASS: VPCOMPRESSB 54697 CPL: 3 54698 CATEGORY: COMPRESS 54699 EXTENSION: AVX512EVEX 54700 ISA_SET: AVX512_VBMI2_128 54701 EXCEPTIONS: AVX512-E4 54702 REAL_OPCODE: Y 54703 ATTRIBUTES: MASKOP_EVEX 54704 PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 54705 OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8 54706 IFORM: VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 54707 } 54708 54709 54710 # EMITTING VPCOMPRESSB (VPCOMPRESSB-256-1) 54711 { 54712 ICLASS: VPCOMPRESSB 54713 CPL: 3 54714 CATEGORY: COMPRESS 54715 EXTENSION: AVX512EVEX 54716 ISA_SET: AVX512_VBMI2_256 54717 EXCEPTIONS: AVX512-E4 54718 REAL_OPCODE: Y 54719 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 54720 PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() 54721 OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8 54722 IFORM: VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 54723 } 54724 54725 54726 # EMITTING VPCOMPRESSB (VPCOMPRESSB-256-2) 54727 { 54728 ICLASS: VPCOMPRESSB 54729 CPL: 3 54730 CATEGORY: COMPRESS 54731 EXTENSION: AVX512EVEX 54732 ISA_SET: AVX512_VBMI2_256 54733 EXCEPTIONS: AVX512-E4 54734 REAL_OPCODE: Y 54735 ATTRIBUTES: MASKOP_EVEX 54736 PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 54737 OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8 54738 IFORM: VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 54739 } 54740 54741 54742 # EMITTING VPCOMPRESSB (VPCOMPRESSB-512-1) 54743 { 54744 ICLASS: VPCOMPRESSB 54745 CPL: 3 54746 CATEGORY: COMPRESS 54747 EXTENSION: AVX512EVEX 54748 ISA_SET: AVX512_VBMI2_512 54749 EXCEPTIONS: AVX512-E4 54750 REAL_OPCODE: Y 54751 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 54752 PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() 54753 OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8 54754 IFORM: VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 54755 } 54756 54757 54758 # EMITTING VPCOMPRESSB (VPCOMPRESSB-512-2) 54759 { 54760 ICLASS: VPCOMPRESSB 54761 CPL: 3 54762 CATEGORY: COMPRESS 54763 EXTENSION: AVX512EVEX 54764 ISA_SET: AVX512_VBMI2_512 54765 EXCEPTIONS: AVX512-E4 54766 REAL_OPCODE: Y 54767 ATTRIBUTES: MASKOP_EVEX 54768 PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 54769 OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8 54770 IFORM: VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 54771 } 54772 54773 54774 # EMITTING VPCOMPRESSW (VPCOMPRESSW-128-1) 54775 { 54776 ICLASS: VPCOMPRESSW 54777 CPL: 3 54778 CATEGORY: COMPRESS 54779 EXTENSION: AVX512EVEX 54780 ISA_SET: AVX512_VBMI2_128 54781 EXCEPTIONS: AVX512-E4 54782 REAL_OPCODE: Y 54783 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 54784 PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() 54785 OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 54786 IFORM: VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 54787 } 54788 54789 54790 # EMITTING VPCOMPRESSW (VPCOMPRESSW-128-2) 54791 { 54792 ICLASS: VPCOMPRESSW 54793 CPL: 3 54794 CATEGORY: COMPRESS 54795 EXTENSION: AVX512EVEX 54796 ISA_SET: AVX512_VBMI2_128 54797 EXCEPTIONS: AVX512-E4 54798 REAL_OPCODE: Y 54799 ATTRIBUTES: MASKOP_EVEX 54800 PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 54801 OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 54802 IFORM: VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 54803 } 54804 54805 54806 # EMITTING VPCOMPRESSW (VPCOMPRESSW-256-1) 54807 { 54808 ICLASS: VPCOMPRESSW 54809 CPL: 3 54810 CATEGORY: COMPRESS 54811 EXTENSION: AVX512EVEX 54812 ISA_SET: AVX512_VBMI2_256 54813 EXCEPTIONS: AVX512-E4 54814 REAL_OPCODE: Y 54815 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 54816 PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() 54817 OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 54818 IFORM: VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 54819 } 54820 54821 54822 # EMITTING VPCOMPRESSW (VPCOMPRESSW-256-2) 54823 { 54824 ICLASS: VPCOMPRESSW 54825 CPL: 3 54826 CATEGORY: COMPRESS 54827 EXTENSION: AVX512EVEX 54828 ISA_SET: AVX512_VBMI2_256 54829 EXCEPTIONS: AVX512-E4 54830 REAL_OPCODE: Y 54831 ATTRIBUTES: MASKOP_EVEX 54832 PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 54833 OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 54834 IFORM: VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 54835 } 54836 54837 54838 # EMITTING VPCOMPRESSW (VPCOMPRESSW-512-1) 54839 { 54840 ICLASS: VPCOMPRESSW 54841 CPL: 3 54842 CATEGORY: COMPRESS 54843 EXTENSION: AVX512EVEX 54844 ISA_SET: AVX512_VBMI2_512 54845 EXCEPTIONS: AVX512-E4 54846 REAL_OPCODE: Y 54847 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 54848 PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() 54849 OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 54850 IFORM: VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 54851 } 54852 54853 54854 # EMITTING VPCOMPRESSW (VPCOMPRESSW-512-2) 54855 { 54856 ICLASS: VPCOMPRESSW 54857 CPL: 3 54858 CATEGORY: COMPRESS 54859 EXTENSION: AVX512EVEX 54860 ISA_SET: AVX512_VBMI2_512 54861 EXCEPTIONS: AVX512-E4 54862 REAL_OPCODE: Y 54863 ATTRIBUTES: MASKOP_EVEX 54864 PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 54865 OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 54866 IFORM: VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 54867 } 54868 54869 54870 # EMITTING VPEXPANDB (VPEXPANDB-128-1) 54871 { 54872 ICLASS: VPEXPANDB 54873 CPL: 3 54874 CATEGORY: EXPAND 54875 EXTENSION: AVX512EVEX 54876 ISA_SET: AVX512_VBMI2_128 54877 EXCEPTIONS: AVX512-E4 54878 REAL_OPCODE: Y 54879 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 54880 PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() 54881 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 54882 IFORM: VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 54883 } 54884 54885 54886 # EMITTING VPEXPANDB (VPEXPANDB-128-2) 54887 { 54888 ICLASS: VPEXPANDB 54889 CPL: 3 54890 CATEGORY: EXPAND 54891 EXTENSION: AVX512EVEX 54892 ISA_SET: AVX512_VBMI2_128 54893 EXCEPTIONS: AVX512-E4 54894 REAL_OPCODE: Y 54895 ATTRIBUTES: MASKOP_EVEX 54896 PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 54897 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 54898 IFORM: VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 54899 } 54900 54901 54902 # EMITTING VPEXPANDB (VPEXPANDB-256-1) 54903 { 54904 ICLASS: VPEXPANDB 54905 CPL: 3 54906 CATEGORY: EXPAND 54907 EXTENSION: AVX512EVEX 54908 ISA_SET: AVX512_VBMI2_256 54909 EXCEPTIONS: AVX512-E4 54910 REAL_OPCODE: Y 54911 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 54912 PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() 54913 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 54914 IFORM: VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 54915 } 54916 54917 54918 # EMITTING VPEXPANDB (VPEXPANDB-256-2) 54919 { 54920 ICLASS: VPEXPANDB 54921 CPL: 3 54922 CATEGORY: EXPAND 54923 EXTENSION: AVX512EVEX 54924 ISA_SET: AVX512_VBMI2_256 54925 EXCEPTIONS: AVX512-E4 54926 REAL_OPCODE: Y 54927 ATTRIBUTES: MASKOP_EVEX 54928 PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 54929 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 54930 IFORM: VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 54931 } 54932 54933 54934 # EMITTING VPEXPANDB (VPEXPANDB-512-1) 54935 { 54936 ICLASS: VPEXPANDB 54937 CPL: 3 54938 CATEGORY: EXPAND 54939 EXTENSION: AVX512EVEX 54940 ISA_SET: AVX512_VBMI2_512 54941 EXCEPTIONS: AVX512-E4 54942 REAL_OPCODE: Y 54943 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 54944 PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() 54945 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 54946 IFORM: VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 54947 } 54948 54949 54950 # EMITTING VPEXPANDB (VPEXPANDB-512-2) 54951 { 54952 ICLASS: VPEXPANDB 54953 CPL: 3 54954 CATEGORY: EXPAND 54955 EXTENSION: AVX512EVEX 54956 ISA_SET: AVX512_VBMI2_512 54957 EXCEPTIONS: AVX512-E4 54958 REAL_OPCODE: Y 54959 ATTRIBUTES: MASKOP_EVEX 54960 PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR 54961 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 54962 IFORM: VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 54963 } 54964 54965 54966 # EMITTING VPEXPANDW (VPEXPANDW-128-1) 54967 { 54968 ICLASS: VPEXPANDW 54969 CPL: 3 54970 CATEGORY: EXPAND 54971 EXTENSION: AVX512EVEX 54972 ISA_SET: AVX512_VBMI2_128 54973 EXCEPTIONS: AVX512-E4 54974 REAL_OPCODE: Y 54975 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 54976 PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() 54977 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 54978 IFORM: VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 54979 } 54980 54981 54982 # EMITTING VPEXPANDW (VPEXPANDW-128-2) 54983 { 54984 ICLASS: VPEXPANDW 54985 CPL: 3 54986 CATEGORY: EXPAND 54987 EXTENSION: AVX512EVEX 54988 ISA_SET: AVX512_VBMI2_128 54989 EXCEPTIONS: AVX512-E4 54990 REAL_OPCODE: Y 54991 ATTRIBUTES: MASKOP_EVEX 54992 PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 54993 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 54994 IFORM: VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 54995 } 54996 54997 54998 # EMITTING VPEXPANDW (VPEXPANDW-256-1) 54999 { 55000 ICLASS: VPEXPANDW 55001 CPL: 3 55002 CATEGORY: EXPAND 55003 EXTENSION: AVX512EVEX 55004 ISA_SET: AVX512_VBMI2_256 55005 EXCEPTIONS: AVX512-E4 55006 REAL_OPCODE: Y 55007 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 55008 PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() 55009 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 55010 IFORM: VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 55011 } 55012 55013 55014 # EMITTING VPEXPANDW (VPEXPANDW-256-2) 55015 { 55016 ICLASS: VPEXPANDW 55017 CPL: 3 55018 CATEGORY: EXPAND 55019 EXTENSION: AVX512EVEX 55020 ISA_SET: AVX512_VBMI2_256 55021 EXCEPTIONS: AVX512-E4 55022 REAL_OPCODE: Y 55023 ATTRIBUTES: MASKOP_EVEX 55024 PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 55025 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 55026 IFORM: VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 55027 } 55028 55029 55030 # EMITTING VPEXPANDW (VPEXPANDW-512-1) 55031 { 55032 ICLASS: VPEXPANDW 55033 CPL: 3 55034 CATEGORY: EXPAND 55035 EXTENSION: AVX512EVEX 55036 ISA_SET: AVX512_VBMI2_512 55037 EXCEPTIONS: AVX512-E4 55038 REAL_OPCODE: Y 55039 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 55040 PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() 55041 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 55042 IFORM: VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 55043 } 55044 55045 55046 # EMITTING VPEXPANDW (VPEXPANDW-512-2) 55047 { 55048 ICLASS: VPEXPANDW 55049 CPL: 3 55050 CATEGORY: EXPAND 55051 EXTENSION: AVX512EVEX 55052 ISA_SET: AVX512_VBMI2_512 55053 EXCEPTIONS: AVX512-E4 55054 REAL_OPCODE: Y 55055 ATTRIBUTES: MASKOP_EVEX 55056 PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR 55057 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 55058 IFORM: VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 55059 } 55060 55061 55062 # EMITTING VPSHLDD (VPSHLDD-128-1) 55063 { 55064 ICLASS: VPSHLDD 55065 CPL: 3 55066 CATEGORY: VBMI2 55067 EXTENSION: AVX512EVEX 55068 ISA_SET: AVX512_VBMI2_128 55069 EXCEPTIONS: AVX512-E4 55070 REAL_OPCODE: Y 55071 ATTRIBUTES: MASKOP_EVEX 55072 PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 55073 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b 55074 IFORM: VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 55075 } 55076 55077 { 55078 ICLASS: VPSHLDD 55079 CPL: 3 55080 CATEGORY: VBMI2 55081 EXTENSION: AVX512EVEX 55082 ISA_SET: AVX512_VBMI2_128 55083 EXCEPTIONS: AVX512-E4 55084 REAL_OPCODE: Y 55085 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55086 PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 55087 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 55088 IFORM: VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 55089 } 55090 55091 55092 # EMITTING VPSHLDD (VPSHLDD-256-1) 55093 { 55094 ICLASS: VPSHLDD 55095 CPL: 3 55096 CATEGORY: VBMI2 55097 EXTENSION: AVX512EVEX 55098 ISA_SET: AVX512_VBMI2_256 55099 EXCEPTIONS: AVX512-E4 55100 REAL_OPCODE: Y 55101 ATTRIBUTES: MASKOP_EVEX 55102 PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 55103 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b 55104 IFORM: VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 55105 } 55106 55107 { 55108 ICLASS: VPSHLDD 55109 CPL: 3 55110 CATEGORY: VBMI2 55111 EXTENSION: AVX512EVEX 55112 ISA_SET: AVX512_VBMI2_256 55113 EXCEPTIONS: AVX512-E4 55114 REAL_OPCODE: Y 55115 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55116 PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 55117 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 55118 IFORM: VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 55119 } 55120 55121 55122 # EMITTING VPSHLDD (VPSHLDD-512-1) 55123 { 55124 ICLASS: VPSHLDD 55125 CPL: 3 55126 CATEGORY: VBMI2 55127 EXTENSION: AVX512EVEX 55128 ISA_SET: AVX512_VBMI2_512 55129 EXCEPTIONS: AVX512-E4 55130 REAL_OPCODE: Y 55131 ATTRIBUTES: MASKOP_EVEX 55132 PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 55133 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b 55134 IFORM: VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 55135 } 55136 55137 { 55138 ICLASS: VPSHLDD 55139 CPL: 3 55140 CATEGORY: VBMI2 55141 EXTENSION: AVX512EVEX 55142 ISA_SET: AVX512_VBMI2_512 55143 EXCEPTIONS: AVX512-E4 55144 REAL_OPCODE: Y 55145 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55146 PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 55147 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 55148 IFORM: VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 55149 } 55150 55151 55152 # EMITTING VPSHLDQ (VPSHLDQ-128-1) 55153 { 55154 ICLASS: VPSHLDQ 55155 CPL: 3 55156 CATEGORY: VBMI2 55157 EXTENSION: AVX512EVEX 55158 ISA_SET: AVX512_VBMI2_128 55159 EXCEPTIONS: AVX512-E4 55160 REAL_OPCODE: Y 55161 ATTRIBUTES: MASKOP_EVEX 55162 PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 55163 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b 55164 IFORM: VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 55165 } 55166 55167 { 55168 ICLASS: VPSHLDQ 55169 CPL: 3 55170 CATEGORY: VBMI2 55171 EXTENSION: AVX512EVEX 55172 ISA_SET: AVX512_VBMI2_128 55173 EXCEPTIONS: AVX512-E4 55174 REAL_OPCODE: Y 55175 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55176 PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 55177 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 55178 IFORM: VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 55179 } 55180 55181 55182 # EMITTING VPSHLDQ (VPSHLDQ-256-1) 55183 { 55184 ICLASS: VPSHLDQ 55185 CPL: 3 55186 CATEGORY: VBMI2 55187 EXTENSION: AVX512EVEX 55188 ISA_SET: AVX512_VBMI2_256 55189 EXCEPTIONS: AVX512-E4 55190 REAL_OPCODE: Y 55191 ATTRIBUTES: MASKOP_EVEX 55192 PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 55193 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b 55194 IFORM: VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 55195 } 55196 55197 { 55198 ICLASS: VPSHLDQ 55199 CPL: 3 55200 CATEGORY: VBMI2 55201 EXTENSION: AVX512EVEX 55202 ISA_SET: AVX512_VBMI2_256 55203 EXCEPTIONS: AVX512-E4 55204 REAL_OPCODE: Y 55205 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55206 PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 55207 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 55208 IFORM: VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 55209 } 55210 55211 55212 # EMITTING VPSHLDQ (VPSHLDQ-512-1) 55213 { 55214 ICLASS: VPSHLDQ 55215 CPL: 3 55216 CATEGORY: VBMI2 55217 EXTENSION: AVX512EVEX 55218 ISA_SET: AVX512_VBMI2_512 55219 EXCEPTIONS: AVX512-E4 55220 REAL_OPCODE: Y 55221 ATTRIBUTES: MASKOP_EVEX 55222 PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 55223 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b 55224 IFORM: VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 55225 } 55226 55227 { 55228 ICLASS: VPSHLDQ 55229 CPL: 3 55230 CATEGORY: VBMI2 55231 EXTENSION: AVX512EVEX 55232 ISA_SET: AVX512_VBMI2_512 55233 EXCEPTIONS: AVX512-E4 55234 REAL_OPCODE: Y 55235 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55236 PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 55237 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 55238 IFORM: VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 55239 } 55240 55241 55242 # EMITTING VPSHLDVD (VPSHLDVD-128-1) 55243 { 55244 ICLASS: VPSHLDVD 55245 CPL: 3 55246 CATEGORY: VBMI2 55247 EXTENSION: AVX512EVEX 55248 ISA_SET: AVX512_VBMI2_128 55249 EXCEPTIONS: AVX512-E4 55250 REAL_OPCODE: Y 55251 ATTRIBUTES: MASKOP_EVEX 55252 PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 55253 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 55254 IFORM: VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 55255 } 55256 55257 { 55258 ICLASS: VPSHLDVD 55259 CPL: 3 55260 CATEGORY: VBMI2 55261 EXTENSION: AVX512EVEX 55262 ISA_SET: AVX512_VBMI2_128 55263 EXCEPTIONS: AVX512-E4 55264 REAL_OPCODE: Y 55265 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55266 PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 55267 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 55268 IFORM: VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 55269 } 55270 55271 55272 # EMITTING VPSHLDVD (VPSHLDVD-256-1) 55273 { 55274 ICLASS: VPSHLDVD 55275 CPL: 3 55276 CATEGORY: VBMI2 55277 EXTENSION: AVX512EVEX 55278 ISA_SET: AVX512_VBMI2_256 55279 EXCEPTIONS: AVX512-E4 55280 REAL_OPCODE: Y 55281 ATTRIBUTES: MASKOP_EVEX 55282 PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 55283 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 55284 IFORM: VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 55285 } 55286 55287 { 55288 ICLASS: VPSHLDVD 55289 CPL: 3 55290 CATEGORY: VBMI2 55291 EXTENSION: AVX512EVEX 55292 ISA_SET: AVX512_VBMI2_256 55293 EXCEPTIONS: AVX512-E4 55294 REAL_OPCODE: Y 55295 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55296 PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 55297 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 55298 IFORM: VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 55299 } 55300 55301 55302 # EMITTING VPSHLDVD (VPSHLDVD-512-1) 55303 { 55304 ICLASS: VPSHLDVD 55305 CPL: 3 55306 CATEGORY: VBMI2 55307 EXTENSION: AVX512EVEX 55308 ISA_SET: AVX512_VBMI2_512 55309 EXCEPTIONS: AVX512-E4 55310 REAL_OPCODE: Y 55311 ATTRIBUTES: MASKOP_EVEX 55312 PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 55313 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 55314 IFORM: VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 55315 } 55316 55317 { 55318 ICLASS: VPSHLDVD 55319 CPL: 3 55320 CATEGORY: VBMI2 55321 EXTENSION: AVX512EVEX 55322 ISA_SET: AVX512_VBMI2_512 55323 EXCEPTIONS: AVX512-E4 55324 REAL_OPCODE: Y 55325 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55326 PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 55327 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 55328 IFORM: VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 55329 } 55330 55331 55332 # EMITTING VPSHLDVQ (VPSHLDVQ-128-1) 55333 { 55334 ICLASS: VPSHLDVQ 55335 CPL: 3 55336 CATEGORY: VBMI2 55337 EXTENSION: AVX512EVEX 55338 ISA_SET: AVX512_VBMI2_128 55339 EXCEPTIONS: AVX512-E4 55340 REAL_OPCODE: Y 55341 ATTRIBUTES: MASKOP_EVEX 55342 PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 55343 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 55344 IFORM: VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 55345 } 55346 55347 { 55348 ICLASS: VPSHLDVQ 55349 CPL: 3 55350 CATEGORY: VBMI2 55351 EXTENSION: AVX512EVEX 55352 ISA_SET: AVX512_VBMI2_128 55353 EXCEPTIONS: AVX512-E4 55354 REAL_OPCODE: Y 55355 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55356 PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 55357 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 55358 IFORM: VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 55359 } 55360 55361 55362 # EMITTING VPSHLDVQ (VPSHLDVQ-256-1) 55363 { 55364 ICLASS: VPSHLDVQ 55365 CPL: 3 55366 CATEGORY: VBMI2 55367 EXTENSION: AVX512EVEX 55368 ISA_SET: AVX512_VBMI2_256 55369 EXCEPTIONS: AVX512-E4 55370 REAL_OPCODE: Y 55371 ATTRIBUTES: MASKOP_EVEX 55372 PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 55373 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 55374 IFORM: VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 55375 } 55376 55377 { 55378 ICLASS: VPSHLDVQ 55379 CPL: 3 55380 CATEGORY: VBMI2 55381 EXTENSION: AVX512EVEX 55382 ISA_SET: AVX512_VBMI2_256 55383 EXCEPTIONS: AVX512-E4 55384 REAL_OPCODE: Y 55385 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55386 PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 55387 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 55388 IFORM: VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 55389 } 55390 55391 55392 # EMITTING VPSHLDVQ (VPSHLDVQ-512-1) 55393 { 55394 ICLASS: VPSHLDVQ 55395 CPL: 3 55396 CATEGORY: VBMI2 55397 EXTENSION: AVX512EVEX 55398 ISA_SET: AVX512_VBMI2_512 55399 EXCEPTIONS: AVX512-E4 55400 REAL_OPCODE: Y 55401 ATTRIBUTES: MASKOP_EVEX 55402 PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 55403 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 55404 IFORM: VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 55405 } 55406 55407 { 55408 ICLASS: VPSHLDVQ 55409 CPL: 3 55410 CATEGORY: VBMI2 55411 EXTENSION: AVX512EVEX 55412 ISA_SET: AVX512_VBMI2_512 55413 EXCEPTIONS: AVX512-E4 55414 REAL_OPCODE: Y 55415 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55416 PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 55417 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 55418 IFORM: VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 55419 } 55420 55421 55422 # EMITTING VPSHLDVW (VPSHLDVW-128-1) 55423 { 55424 ICLASS: VPSHLDVW 55425 CPL: 3 55426 CATEGORY: VBMI2 55427 EXTENSION: AVX512EVEX 55428 ISA_SET: AVX512_VBMI2_128 55429 EXCEPTIONS: AVX512-E4 55430 REAL_OPCODE: Y 55431 ATTRIBUTES: MASKOP_EVEX 55432 PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 55433 OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 55434 IFORM: VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 55435 } 55436 55437 { 55438 ICLASS: VPSHLDVW 55439 CPL: 3 55440 CATEGORY: VBMI2 55441 EXTENSION: AVX512EVEX 55442 ISA_SET: AVX512_VBMI2_128 55443 EXCEPTIONS: AVX512-E4 55444 REAL_OPCODE: Y 55445 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55446 PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 55447 OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 55448 IFORM: VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 55449 } 55450 55451 55452 # EMITTING VPSHLDVW (VPSHLDVW-256-1) 55453 { 55454 ICLASS: VPSHLDVW 55455 CPL: 3 55456 CATEGORY: VBMI2 55457 EXTENSION: AVX512EVEX 55458 ISA_SET: AVX512_VBMI2_256 55459 EXCEPTIONS: AVX512-E4 55460 REAL_OPCODE: Y 55461 ATTRIBUTES: MASKOP_EVEX 55462 PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 55463 OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 55464 IFORM: VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 55465 } 55466 55467 { 55468 ICLASS: VPSHLDVW 55469 CPL: 3 55470 CATEGORY: VBMI2 55471 EXTENSION: AVX512EVEX 55472 ISA_SET: AVX512_VBMI2_256 55473 EXCEPTIONS: AVX512-E4 55474 REAL_OPCODE: Y 55475 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55476 PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 55477 OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 55478 IFORM: VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 55479 } 55480 55481 55482 # EMITTING VPSHLDVW (VPSHLDVW-512-1) 55483 { 55484 ICLASS: VPSHLDVW 55485 CPL: 3 55486 CATEGORY: VBMI2 55487 EXTENSION: AVX512EVEX 55488 ISA_SET: AVX512_VBMI2_512 55489 EXCEPTIONS: AVX512-E4 55490 REAL_OPCODE: Y 55491 ATTRIBUTES: MASKOP_EVEX 55492 PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 55493 OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 55494 IFORM: VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 55495 } 55496 55497 { 55498 ICLASS: VPSHLDVW 55499 CPL: 3 55500 CATEGORY: VBMI2 55501 EXTENSION: AVX512EVEX 55502 ISA_SET: AVX512_VBMI2_512 55503 EXCEPTIONS: AVX512-E4 55504 REAL_OPCODE: Y 55505 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55506 PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 55507 OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 55508 IFORM: VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 55509 } 55510 55511 55512 # EMITTING VPSHLDW (VPSHLDW-128-1) 55513 { 55514 ICLASS: VPSHLDW 55515 CPL: 3 55516 CATEGORY: VBMI2 55517 EXTENSION: AVX512EVEX 55518 ISA_SET: AVX512_VBMI2_128 55519 EXCEPTIONS: AVX512-E4 55520 REAL_OPCODE: Y 55521 ATTRIBUTES: MASKOP_EVEX 55522 PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 55523 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b 55524 IFORM: VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 55525 } 55526 55527 { 55528 ICLASS: VPSHLDW 55529 CPL: 3 55530 CATEGORY: VBMI2 55531 EXTENSION: AVX512EVEX 55532 ISA_SET: AVX512_VBMI2_128 55533 EXCEPTIONS: AVX512-E4 55534 REAL_OPCODE: Y 55535 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55536 PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 55537 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b 55538 IFORM: VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 55539 } 55540 55541 55542 # EMITTING VPSHLDW (VPSHLDW-256-1) 55543 { 55544 ICLASS: VPSHLDW 55545 CPL: 3 55546 CATEGORY: VBMI2 55547 EXTENSION: AVX512EVEX 55548 ISA_SET: AVX512_VBMI2_256 55549 EXCEPTIONS: AVX512-E4 55550 REAL_OPCODE: Y 55551 ATTRIBUTES: MASKOP_EVEX 55552 PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 55553 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b 55554 IFORM: VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 55555 } 55556 55557 { 55558 ICLASS: VPSHLDW 55559 CPL: 3 55560 CATEGORY: VBMI2 55561 EXTENSION: AVX512EVEX 55562 ISA_SET: AVX512_VBMI2_256 55563 EXCEPTIONS: AVX512-E4 55564 REAL_OPCODE: Y 55565 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55566 PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 55567 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b 55568 IFORM: VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 55569 } 55570 55571 55572 # EMITTING VPSHLDW (VPSHLDW-512-1) 55573 { 55574 ICLASS: VPSHLDW 55575 CPL: 3 55576 CATEGORY: VBMI2 55577 EXTENSION: AVX512EVEX 55578 ISA_SET: AVX512_VBMI2_512 55579 EXCEPTIONS: AVX512-E4 55580 REAL_OPCODE: Y 55581 ATTRIBUTES: MASKOP_EVEX 55582 PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 55583 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b 55584 IFORM: VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 55585 } 55586 55587 { 55588 ICLASS: VPSHLDW 55589 CPL: 3 55590 CATEGORY: VBMI2 55591 EXTENSION: AVX512EVEX 55592 ISA_SET: AVX512_VBMI2_512 55593 EXCEPTIONS: AVX512-E4 55594 REAL_OPCODE: Y 55595 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55596 PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 55597 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b 55598 IFORM: VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 55599 } 55600 55601 55602 # EMITTING VPSHRDD (VPSHRDD-128-1) 55603 { 55604 ICLASS: VPSHRDD 55605 CPL: 3 55606 CATEGORY: VBMI2 55607 EXTENSION: AVX512EVEX 55608 ISA_SET: AVX512_VBMI2_128 55609 EXCEPTIONS: AVX512-E4 55610 REAL_OPCODE: Y 55611 ATTRIBUTES: MASKOP_EVEX 55612 PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() 55613 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b 55614 IFORM: VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 55615 } 55616 55617 { 55618 ICLASS: VPSHRDD 55619 CPL: 3 55620 CATEGORY: VBMI2 55621 EXTENSION: AVX512EVEX 55622 ISA_SET: AVX512_VBMI2_128 55623 EXCEPTIONS: AVX512-E4 55624 REAL_OPCODE: Y 55625 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55626 PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 55627 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 55628 IFORM: VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 55629 } 55630 55631 55632 # EMITTING VPSHRDD (VPSHRDD-256-1) 55633 { 55634 ICLASS: VPSHRDD 55635 CPL: 3 55636 CATEGORY: VBMI2 55637 EXTENSION: AVX512EVEX 55638 ISA_SET: AVX512_VBMI2_256 55639 EXCEPTIONS: AVX512-E4 55640 REAL_OPCODE: Y 55641 ATTRIBUTES: MASKOP_EVEX 55642 PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() 55643 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b 55644 IFORM: VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 55645 } 55646 55647 { 55648 ICLASS: VPSHRDD 55649 CPL: 3 55650 CATEGORY: VBMI2 55651 EXTENSION: AVX512EVEX 55652 ISA_SET: AVX512_VBMI2_256 55653 EXCEPTIONS: AVX512-E4 55654 REAL_OPCODE: Y 55655 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55656 PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 55657 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 55658 IFORM: VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 55659 } 55660 55661 55662 # EMITTING VPSHRDD (VPSHRDD-512-1) 55663 { 55664 ICLASS: VPSHRDD 55665 CPL: 3 55666 CATEGORY: VBMI2 55667 EXTENSION: AVX512EVEX 55668 ISA_SET: AVX512_VBMI2_512 55669 EXCEPTIONS: AVX512-E4 55670 REAL_OPCODE: Y 55671 ATTRIBUTES: MASKOP_EVEX 55672 PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() 55673 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b 55674 IFORM: VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 55675 } 55676 55677 { 55678 ICLASS: VPSHRDD 55679 CPL: 3 55680 CATEGORY: VBMI2 55681 EXTENSION: AVX512EVEX 55682 ISA_SET: AVX512_VBMI2_512 55683 EXCEPTIONS: AVX512-E4 55684 REAL_OPCODE: Y 55685 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55686 PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() 55687 OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b 55688 IFORM: VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 55689 } 55690 55691 55692 # EMITTING VPSHRDQ (VPSHRDQ-128-1) 55693 { 55694 ICLASS: VPSHRDQ 55695 CPL: 3 55696 CATEGORY: VBMI2 55697 EXTENSION: AVX512EVEX 55698 ISA_SET: AVX512_VBMI2_128 55699 EXCEPTIONS: AVX512-E4 55700 REAL_OPCODE: Y 55701 ATTRIBUTES: MASKOP_EVEX 55702 PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 55703 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b 55704 IFORM: VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 55705 } 55706 55707 { 55708 ICLASS: VPSHRDQ 55709 CPL: 3 55710 CATEGORY: VBMI2 55711 EXTENSION: AVX512EVEX 55712 ISA_SET: AVX512_VBMI2_128 55713 EXCEPTIONS: AVX512-E4 55714 REAL_OPCODE: Y 55715 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55716 PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 55717 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 55718 IFORM: VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 55719 } 55720 55721 55722 # EMITTING VPSHRDQ (VPSHRDQ-256-1) 55723 { 55724 ICLASS: VPSHRDQ 55725 CPL: 3 55726 CATEGORY: VBMI2 55727 EXTENSION: AVX512EVEX 55728 ISA_SET: AVX512_VBMI2_256 55729 EXCEPTIONS: AVX512-E4 55730 REAL_OPCODE: Y 55731 ATTRIBUTES: MASKOP_EVEX 55732 PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 55733 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b 55734 IFORM: VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 55735 } 55736 55737 { 55738 ICLASS: VPSHRDQ 55739 CPL: 3 55740 CATEGORY: VBMI2 55741 EXTENSION: AVX512EVEX 55742 ISA_SET: AVX512_VBMI2_256 55743 EXCEPTIONS: AVX512-E4 55744 REAL_OPCODE: Y 55745 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55746 PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 55747 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 55748 IFORM: VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 55749 } 55750 55751 55752 # EMITTING VPSHRDQ (VPSHRDQ-512-1) 55753 { 55754 ICLASS: VPSHRDQ 55755 CPL: 3 55756 CATEGORY: VBMI2 55757 EXTENSION: AVX512EVEX 55758 ISA_SET: AVX512_VBMI2_512 55759 EXCEPTIONS: AVX512-E4 55760 REAL_OPCODE: Y 55761 ATTRIBUTES: MASKOP_EVEX 55762 PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 55763 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b 55764 IFORM: VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 55765 } 55766 55767 { 55768 ICLASS: VPSHRDQ 55769 CPL: 3 55770 CATEGORY: VBMI2 55771 EXTENSION: AVX512EVEX 55772 ISA_SET: AVX512_VBMI2_512 55773 EXCEPTIONS: AVX512-E4 55774 REAL_OPCODE: Y 55775 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55776 PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 55777 OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 55778 IFORM: VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 55779 } 55780 55781 55782 # EMITTING VPSHRDVD (VPSHRDVD-128-1) 55783 { 55784 ICLASS: VPSHRDVD 55785 CPL: 3 55786 CATEGORY: VBMI2 55787 EXTENSION: AVX512EVEX 55788 ISA_SET: AVX512_VBMI2_128 55789 EXCEPTIONS: AVX512-E4 55790 REAL_OPCODE: Y 55791 ATTRIBUTES: MASKOP_EVEX 55792 PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 55793 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 55794 IFORM: VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 55795 } 55796 55797 { 55798 ICLASS: VPSHRDVD 55799 CPL: 3 55800 CATEGORY: VBMI2 55801 EXTENSION: AVX512EVEX 55802 ISA_SET: AVX512_VBMI2_128 55803 EXCEPTIONS: AVX512-E4 55804 REAL_OPCODE: Y 55805 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55806 PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 55807 OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 55808 IFORM: VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 55809 } 55810 55811 55812 # EMITTING VPSHRDVD (VPSHRDVD-256-1) 55813 { 55814 ICLASS: VPSHRDVD 55815 CPL: 3 55816 CATEGORY: VBMI2 55817 EXTENSION: AVX512EVEX 55818 ISA_SET: AVX512_VBMI2_256 55819 EXCEPTIONS: AVX512-E4 55820 REAL_OPCODE: Y 55821 ATTRIBUTES: MASKOP_EVEX 55822 PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 55823 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 55824 IFORM: VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 55825 } 55826 55827 { 55828 ICLASS: VPSHRDVD 55829 CPL: 3 55830 CATEGORY: VBMI2 55831 EXTENSION: AVX512EVEX 55832 ISA_SET: AVX512_VBMI2_256 55833 EXCEPTIONS: AVX512-E4 55834 REAL_OPCODE: Y 55835 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55836 PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 55837 OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR 55838 IFORM: VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 55839 } 55840 55841 55842 # EMITTING VPSHRDVD (VPSHRDVD-512-1) 55843 { 55844 ICLASS: VPSHRDVD 55845 CPL: 3 55846 CATEGORY: VBMI2 55847 EXTENSION: AVX512EVEX 55848 ISA_SET: AVX512_VBMI2_512 55849 EXCEPTIONS: AVX512-E4 55850 REAL_OPCODE: Y 55851 ATTRIBUTES: MASKOP_EVEX 55852 PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 55853 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 55854 IFORM: VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 55855 } 55856 55857 { 55858 ICLASS: VPSHRDVD 55859 CPL: 3 55860 CATEGORY: VBMI2 55861 EXTENSION: AVX512EVEX 55862 ISA_SET: AVX512_VBMI2_512 55863 EXCEPTIONS: AVX512-E4 55864 REAL_OPCODE: Y 55865 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55866 PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 55867 OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR 55868 IFORM: VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 55869 } 55870 55871 55872 # EMITTING VPSHRDVQ (VPSHRDVQ-128-1) 55873 { 55874 ICLASS: VPSHRDVQ 55875 CPL: 3 55876 CATEGORY: VBMI2 55877 EXTENSION: AVX512EVEX 55878 ISA_SET: AVX512_VBMI2_128 55879 EXCEPTIONS: AVX512-E4 55880 REAL_OPCODE: Y 55881 ATTRIBUTES: MASKOP_EVEX 55882 PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 55883 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 55884 IFORM: VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 55885 } 55886 55887 { 55888 ICLASS: VPSHRDVQ 55889 CPL: 3 55890 CATEGORY: VBMI2 55891 EXTENSION: AVX512EVEX 55892 ISA_SET: AVX512_VBMI2_128 55893 EXCEPTIONS: AVX512-E4 55894 REAL_OPCODE: Y 55895 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55896 PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() 55897 OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 55898 IFORM: VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 55899 } 55900 55901 55902 # EMITTING VPSHRDVQ (VPSHRDVQ-256-1) 55903 { 55904 ICLASS: VPSHRDVQ 55905 CPL: 3 55906 CATEGORY: VBMI2 55907 EXTENSION: AVX512EVEX 55908 ISA_SET: AVX512_VBMI2_256 55909 EXCEPTIONS: AVX512-E4 55910 REAL_OPCODE: Y 55911 ATTRIBUTES: MASKOP_EVEX 55912 PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 55913 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 55914 IFORM: VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 55915 } 55916 55917 { 55918 ICLASS: VPSHRDVQ 55919 CPL: 3 55920 CATEGORY: VBMI2 55921 EXTENSION: AVX512EVEX 55922 ISA_SET: AVX512_VBMI2_256 55923 EXCEPTIONS: AVX512-E4 55924 REAL_OPCODE: Y 55925 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55926 PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() 55927 OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR 55928 IFORM: VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 55929 } 55930 55931 55932 # EMITTING VPSHRDVQ (VPSHRDVQ-512-1) 55933 { 55934 ICLASS: VPSHRDVQ 55935 CPL: 3 55936 CATEGORY: VBMI2 55937 EXTENSION: AVX512EVEX 55938 ISA_SET: AVX512_VBMI2_512 55939 EXCEPTIONS: AVX512-E4 55940 REAL_OPCODE: Y 55941 ATTRIBUTES: MASKOP_EVEX 55942 PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 55943 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 55944 IFORM: VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 55945 } 55946 55947 { 55948 ICLASS: VPSHRDVQ 55949 CPL: 3 55950 CATEGORY: VBMI2 55951 EXTENSION: AVX512EVEX 55952 ISA_SET: AVX512_VBMI2_512 55953 EXCEPTIONS: AVX512-E4 55954 REAL_OPCODE: Y 55955 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 55956 PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() 55957 OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR 55958 IFORM: VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 55959 } 55960 55961 55962 # EMITTING VPSHRDVW (VPSHRDVW-128-1) 55963 { 55964 ICLASS: VPSHRDVW 55965 CPL: 3 55966 CATEGORY: VBMI2 55967 EXTENSION: AVX512EVEX 55968 ISA_SET: AVX512_VBMI2_128 55969 EXCEPTIONS: AVX512-E4 55970 REAL_OPCODE: Y 55971 ATTRIBUTES: MASKOP_EVEX 55972 PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 55973 OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 55974 IFORM: VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 55975 } 55976 55977 { 55978 ICLASS: VPSHRDVW 55979 CPL: 3 55980 CATEGORY: VBMI2 55981 EXTENSION: AVX512EVEX 55982 ISA_SET: AVX512_VBMI2_128 55983 EXCEPTIONS: AVX512-E4 55984 REAL_OPCODE: Y 55985 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 55986 PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() 55987 OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 55988 IFORM: VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 55989 } 55990 55991 55992 # EMITTING VPSHRDVW (VPSHRDVW-256-1) 55993 { 55994 ICLASS: VPSHRDVW 55995 CPL: 3 55996 CATEGORY: VBMI2 55997 EXTENSION: AVX512EVEX 55998 ISA_SET: AVX512_VBMI2_256 55999 EXCEPTIONS: AVX512-E4 56000 REAL_OPCODE: Y 56001 ATTRIBUTES: MASKOP_EVEX 56002 PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 56003 OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 56004 IFORM: VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 56005 } 56006 56007 { 56008 ICLASS: VPSHRDVW 56009 CPL: 3 56010 CATEGORY: VBMI2 56011 EXTENSION: AVX512EVEX 56012 ISA_SET: AVX512_VBMI2_256 56013 EXCEPTIONS: AVX512-E4 56014 REAL_OPCODE: Y 56015 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 56016 PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() 56017 OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 56018 IFORM: VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 56019 } 56020 56021 56022 # EMITTING VPSHRDVW (VPSHRDVW-512-1) 56023 { 56024 ICLASS: VPSHRDVW 56025 CPL: 3 56026 CATEGORY: VBMI2 56027 EXTENSION: AVX512EVEX 56028 ISA_SET: AVX512_VBMI2_512 56029 EXCEPTIONS: AVX512-E4 56030 REAL_OPCODE: Y 56031 ATTRIBUTES: MASKOP_EVEX 56032 PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 56033 OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 56034 IFORM: VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 56035 } 56036 56037 { 56038 ICLASS: VPSHRDVW 56039 CPL: 3 56040 CATEGORY: VBMI2 56041 EXTENSION: AVX512EVEX 56042 ISA_SET: AVX512_VBMI2_512 56043 EXCEPTIONS: AVX512-E4 56044 REAL_OPCODE: Y 56045 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 56046 PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() 56047 OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 56048 IFORM: VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 56049 } 56050 56051 56052 # EMITTING VPSHRDW (VPSHRDW-128-1) 56053 { 56054 ICLASS: VPSHRDW 56055 CPL: 3 56056 CATEGORY: VBMI2 56057 EXTENSION: AVX512EVEX 56058 ISA_SET: AVX512_VBMI2_128 56059 EXCEPTIONS: AVX512-E4 56060 REAL_OPCODE: Y 56061 ATTRIBUTES: MASKOP_EVEX 56062 PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 56063 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b 56064 IFORM: VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 56065 } 56066 56067 { 56068 ICLASS: VPSHRDW 56069 CPL: 3 56070 CATEGORY: VBMI2 56071 EXTENSION: AVX512EVEX 56072 ISA_SET: AVX512_VBMI2_128 56073 EXCEPTIONS: AVX512-E4 56074 REAL_OPCODE: Y 56075 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 56076 PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 56077 OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b 56078 IFORM: VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 56079 } 56080 56081 56082 # EMITTING VPSHRDW (VPSHRDW-256-1) 56083 { 56084 ICLASS: VPSHRDW 56085 CPL: 3 56086 CATEGORY: VBMI2 56087 EXTENSION: AVX512EVEX 56088 ISA_SET: AVX512_VBMI2_256 56089 EXCEPTIONS: AVX512-E4 56090 REAL_OPCODE: Y 56091 ATTRIBUTES: MASKOP_EVEX 56092 PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 56093 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b 56094 IFORM: VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 56095 } 56096 56097 { 56098 ICLASS: VPSHRDW 56099 CPL: 3 56100 CATEGORY: VBMI2 56101 EXTENSION: AVX512EVEX 56102 ISA_SET: AVX512_VBMI2_256 56103 EXCEPTIONS: AVX512-E4 56104 REAL_OPCODE: Y 56105 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 56106 PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 56107 OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b 56108 IFORM: VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 56109 } 56110 56111 56112 # EMITTING VPSHRDW (VPSHRDW-512-1) 56113 { 56114 ICLASS: VPSHRDW 56115 CPL: 3 56116 CATEGORY: VBMI2 56117 EXTENSION: AVX512EVEX 56118 ISA_SET: AVX512_VBMI2_512 56119 EXCEPTIONS: AVX512-E4 56120 REAL_OPCODE: Y 56121 ATTRIBUTES: MASKOP_EVEX 56122 PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 56123 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b 56124 IFORM: VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 56125 } 56126 56127 { 56128 ICLASS: VPSHRDW 56129 CPL: 3 56130 CATEGORY: VBMI2 56131 EXTENSION: AVX512EVEX 56132 ISA_SET: AVX512_VBMI2_512 56133 EXCEPTIONS: AVX512-E4 56134 REAL_OPCODE: Y 56135 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 56136 PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() 56137 OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b 56138 IFORM: VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 56139 } 56140 56141 56142 56143 56144 ###FILE: ./datafiles/vnni/vnni-isa.xed.txt 56145 56146 #BEGIN_LEGAL 56147 # 56148 #Copyright (c) 2017 Intel Corporation 56149 # 56150 # Licensed under the Apache License, Version 2.0 (the "License"); 56151 # you may not use this file except in compliance with the License. 56152 # You may obtain a copy of the License at 56153 # 56154 # http://www.apache.org/licenses/LICENSE-2.0 56155 # 56156 # Unless required by applicable law or agreed to in writing, software 56157 # distributed under the License is distributed on an "AS IS" BASIS, 56158 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 56159 # See the License for the specific language governing permissions and 56160 # limitations under the License. 56161 # 56162 #END_LEGAL 56163 # 56164 # 56165 # 56166 # ***** GENERATED FILE -- DO NOT EDIT! ***** 56167 # ***** GENERATED FILE -- DO NOT EDIT! ***** 56168 # ***** GENERATED FILE -- DO NOT EDIT! ***** 56169 # 56170 # 56171 # 56172 EVEX_INSTRUCTIONS():: 56173 # EMITTING VPDPBUSD (VPDPBUSD-128-1) 56174 { 56175 ICLASS: VPDPBUSD 56176 CPL: 3 56177 CATEGORY: AVX512 56178 EXTENSION: AVX512EVEX 56179 ISA_SET: AVX512_VNNI_128 56180 EXCEPTIONS: AVX512-E4 56181 REAL_OPCODE: Y 56182 ATTRIBUTES: MASKOP_EVEX 56183 PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 56184 OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32 56185 IFORM: VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 56186 } 56187 56188 { 56189 ICLASS: VPDPBUSD 56190 CPL: 3 56191 CATEGORY: AVX512 56192 EXTENSION: AVX512EVEX 56193 ISA_SET: AVX512_VNNI_128 56194 EXCEPTIONS: AVX512-E4 56195 REAL_OPCODE: Y 56196 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56197 PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 56198 OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR 56199 IFORM: VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 56200 } 56201 56202 56203 # EMITTING VPDPBUSD (VPDPBUSD-256-1) 56204 { 56205 ICLASS: VPDPBUSD 56206 CPL: 3 56207 CATEGORY: AVX512 56208 EXTENSION: AVX512EVEX 56209 ISA_SET: AVX512_VNNI_256 56210 EXCEPTIONS: AVX512-E4 56211 REAL_OPCODE: Y 56212 ATTRIBUTES: MASKOP_EVEX 56213 PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 56214 OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32 56215 IFORM: VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 56216 } 56217 56218 { 56219 ICLASS: VPDPBUSD 56220 CPL: 3 56221 CATEGORY: AVX512 56222 EXTENSION: AVX512EVEX 56223 ISA_SET: AVX512_VNNI_256 56224 EXCEPTIONS: AVX512-E4 56225 REAL_OPCODE: Y 56226 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56227 PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 56228 OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR 56229 IFORM: VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 56230 } 56231 56232 56233 # EMITTING VPDPBUSD (VPDPBUSD-512-1) 56234 { 56235 ICLASS: VPDPBUSD 56236 CPL: 3 56237 CATEGORY: AVX512 56238 EXTENSION: AVX512EVEX 56239 ISA_SET: AVX512_VNNI_512 56240 EXCEPTIONS: AVX512-E4 56241 REAL_OPCODE: Y 56242 ATTRIBUTES: MASKOP_EVEX 56243 PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 56244 OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32 56245 IFORM: VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 56246 } 56247 56248 { 56249 ICLASS: VPDPBUSD 56250 CPL: 3 56251 CATEGORY: AVX512 56252 EXTENSION: AVX512EVEX 56253 ISA_SET: AVX512_VNNI_512 56254 EXCEPTIONS: AVX512-E4 56255 REAL_OPCODE: Y 56256 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56257 PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 56258 OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR 56259 IFORM: VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 56260 } 56261 56262 56263 # EMITTING VPDPBUSDS (VPDPBUSDS-128-1) 56264 { 56265 ICLASS: VPDPBUSDS 56266 CPL: 3 56267 CATEGORY: AVX512 56268 EXTENSION: AVX512EVEX 56269 ISA_SET: AVX512_VNNI_128 56270 EXCEPTIONS: AVX512-E4 56271 REAL_OPCODE: Y 56272 ATTRIBUTES: MASKOP_EVEX 56273 PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 56274 OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32 56275 IFORM: VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 56276 } 56277 56278 { 56279 ICLASS: VPDPBUSDS 56280 CPL: 3 56281 CATEGORY: AVX512 56282 EXTENSION: AVX512EVEX 56283 ISA_SET: AVX512_VNNI_128 56284 EXCEPTIONS: AVX512-E4 56285 REAL_OPCODE: Y 56286 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56287 PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 56288 OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR 56289 IFORM: VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 56290 } 56291 56292 56293 # EMITTING VPDPBUSDS (VPDPBUSDS-256-1) 56294 { 56295 ICLASS: VPDPBUSDS 56296 CPL: 3 56297 CATEGORY: AVX512 56298 EXTENSION: AVX512EVEX 56299 ISA_SET: AVX512_VNNI_256 56300 EXCEPTIONS: AVX512-E4 56301 REAL_OPCODE: Y 56302 ATTRIBUTES: MASKOP_EVEX 56303 PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 56304 OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32 56305 IFORM: VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 56306 } 56307 56308 { 56309 ICLASS: VPDPBUSDS 56310 CPL: 3 56311 CATEGORY: AVX512 56312 EXTENSION: AVX512EVEX 56313 ISA_SET: AVX512_VNNI_256 56314 EXCEPTIONS: AVX512-E4 56315 REAL_OPCODE: Y 56316 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56317 PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 56318 OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR 56319 IFORM: VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 56320 } 56321 56322 56323 # EMITTING VPDPBUSDS (VPDPBUSDS-512-1) 56324 { 56325 ICLASS: VPDPBUSDS 56326 CPL: 3 56327 CATEGORY: AVX512 56328 EXTENSION: AVX512EVEX 56329 ISA_SET: AVX512_VNNI_512 56330 EXCEPTIONS: AVX512-E4 56331 REAL_OPCODE: Y 56332 ATTRIBUTES: MASKOP_EVEX 56333 PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 56334 OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32 56335 IFORM: VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 56336 } 56337 56338 { 56339 ICLASS: VPDPBUSDS 56340 CPL: 3 56341 CATEGORY: AVX512 56342 EXTENSION: AVX512EVEX 56343 ISA_SET: AVX512_VNNI_512 56344 EXCEPTIONS: AVX512-E4 56345 REAL_OPCODE: Y 56346 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56347 PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 56348 OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR 56349 IFORM: VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 56350 } 56351 56352 56353 # EMITTING VPDPWSSD (VPDPWSSD-128-1) 56354 { 56355 ICLASS: VPDPWSSD 56356 CPL: 3 56357 CATEGORY: AVX512 56358 EXTENSION: AVX512EVEX 56359 ISA_SET: AVX512_VNNI_128 56360 EXCEPTIONS: AVX512-E4 56361 REAL_OPCODE: Y 56362 ATTRIBUTES: MASKOP_EVEX 56363 PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 56364 OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32 56365 IFORM: VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 56366 } 56367 56368 { 56369 ICLASS: VPDPWSSD 56370 CPL: 3 56371 CATEGORY: AVX512 56372 EXTENSION: AVX512EVEX 56373 ISA_SET: AVX512_VNNI_128 56374 EXCEPTIONS: AVX512-E4 56375 REAL_OPCODE: Y 56376 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56377 PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 56378 OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR 56379 IFORM: VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 56380 } 56381 56382 56383 # EMITTING VPDPWSSD (VPDPWSSD-256-1) 56384 { 56385 ICLASS: VPDPWSSD 56386 CPL: 3 56387 CATEGORY: AVX512 56388 EXTENSION: AVX512EVEX 56389 ISA_SET: AVX512_VNNI_256 56390 EXCEPTIONS: AVX512-E4 56391 REAL_OPCODE: Y 56392 ATTRIBUTES: MASKOP_EVEX 56393 PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 56394 OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32 56395 IFORM: VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 56396 } 56397 56398 { 56399 ICLASS: VPDPWSSD 56400 CPL: 3 56401 CATEGORY: AVX512 56402 EXTENSION: AVX512EVEX 56403 ISA_SET: AVX512_VNNI_256 56404 EXCEPTIONS: AVX512-E4 56405 REAL_OPCODE: Y 56406 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56407 PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 56408 OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR 56409 IFORM: VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 56410 } 56411 56412 56413 # EMITTING VPDPWSSD (VPDPWSSD-512-1) 56414 { 56415 ICLASS: VPDPWSSD 56416 CPL: 3 56417 CATEGORY: AVX512 56418 EXTENSION: AVX512EVEX 56419 ISA_SET: AVX512_VNNI_512 56420 EXCEPTIONS: AVX512-E4 56421 REAL_OPCODE: Y 56422 ATTRIBUTES: MASKOP_EVEX 56423 PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 56424 OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32 56425 IFORM: VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 56426 } 56427 56428 { 56429 ICLASS: VPDPWSSD 56430 CPL: 3 56431 CATEGORY: AVX512 56432 EXTENSION: AVX512EVEX 56433 ISA_SET: AVX512_VNNI_512 56434 EXCEPTIONS: AVX512-E4 56435 REAL_OPCODE: Y 56436 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56437 PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 56438 OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR 56439 IFORM: VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 56440 } 56441 56442 56443 # EMITTING VPDPWSSDS (VPDPWSSDS-128-1) 56444 { 56445 ICLASS: VPDPWSSDS 56446 CPL: 3 56447 CATEGORY: AVX512 56448 EXTENSION: AVX512EVEX 56449 ISA_SET: AVX512_VNNI_128 56450 EXCEPTIONS: AVX512-E4 56451 REAL_OPCODE: Y 56452 ATTRIBUTES: MASKOP_EVEX 56453 PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 56454 OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32 56455 IFORM: VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 56456 } 56457 56458 { 56459 ICLASS: VPDPWSSDS 56460 CPL: 3 56461 CATEGORY: AVX512 56462 EXTENSION: AVX512EVEX 56463 ISA_SET: AVX512_VNNI_128 56464 EXCEPTIONS: AVX512-E4 56465 REAL_OPCODE: Y 56466 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56467 PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() 56468 OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR 56469 IFORM: VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 56470 } 56471 56472 56473 # EMITTING VPDPWSSDS (VPDPWSSDS-256-1) 56474 { 56475 ICLASS: VPDPWSSDS 56476 CPL: 3 56477 CATEGORY: AVX512 56478 EXTENSION: AVX512EVEX 56479 ISA_SET: AVX512_VNNI_256 56480 EXCEPTIONS: AVX512-E4 56481 REAL_OPCODE: Y 56482 ATTRIBUTES: MASKOP_EVEX 56483 PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 56484 OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32 56485 IFORM: VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 56486 } 56487 56488 { 56489 ICLASS: VPDPWSSDS 56490 CPL: 3 56491 CATEGORY: AVX512 56492 EXTENSION: AVX512EVEX 56493 ISA_SET: AVX512_VNNI_256 56494 EXCEPTIONS: AVX512-E4 56495 REAL_OPCODE: Y 56496 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56497 PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() 56498 OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR 56499 IFORM: VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 56500 } 56501 56502 56503 # EMITTING VPDPWSSDS (VPDPWSSDS-512-1) 56504 { 56505 ICLASS: VPDPWSSDS 56506 CPL: 3 56507 CATEGORY: AVX512 56508 EXTENSION: AVX512EVEX 56509 ISA_SET: AVX512_VNNI_512 56510 EXCEPTIONS: AVX512-E4 56511 REAL_OPCODE: Y 56512 ATTRIBUTES: MASKOP_EVEX 56513 PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 56514 OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32 56515 IFORM: VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 56516 } 56517 56518 { 56519 ICLASS: VPDPWSSDS 56520 CPL: 3 56521 CATEGORY: AVX512 56522 EXTENSION: AVX512EVEX 56523 ISA_SET: AVX512_VNNI_512 56524 EXCEPTIONS: AVX512-E4 56525 REAL_OPCODE: Y 56526 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56527 PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() 56528 OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR 56529 IFORM: VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 56530 } 56531 56532 56533 56534 56535 ###FILE: ./datafiles/gfni-vaes-vpcl/gfni-sse-isa.xed.txt 56536 56537 #BEGIN_LEGAL 56538 # 56539 #Copyright (c) 2017 Intel Corporation 56540 # 56541 # Licensed under the Apache License, Version 2.0 (the "License"); 56542 # you may not use this file except in compliance with the License. 56543 # You may obtain a copy of the License at 56544 # 56545 # http://www.apache.org/licenses/LICENSE-2.0 56546 # 56547 # Unless required by applicable law or agreed to in writing, software 56548 # distributed under the License is distributed on an "AS IS" BASIS, 56549 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 56550 # See the License for the specific language governing permissions and 56551 # limitations under the License. 56552 # 56553 #END_LEGAL 56554 # 56555 # 56556 # 56557 # ***** GENERATED FILE -- DO NOT EDIT! ***** 56558 # ***** GENERATED FILE -- DO NOT EDIT! ***** 56559 # ***** GENERATED FILE -- DO NOT EDIT! ***** 56560 # 56561 # 56562 # 56563 INSTRUCTIONS():: 56564 # EMITTING GF2P8AFFINEINVQB (GF2P8AFFINEINVQB-N/A-1) 56565 { 56566 ICLASS: GF2P8AFFINEINVQB 56567 CPL: 3 56568 CATEGORY: GFNI 56569 EXTENSION: GFNI 56570 ISA_SET: GFNI 56571 EXCEPTIONS: E4 56572 REAL_OPCODE: Y 56573 PATTERN: 0x0F 0x3A 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8() 56574 OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u64 IMM0:r:b 56575 IFORM: GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 56576 } 56577 56578 { 56579 ICLASS: GF2P8AFFINEINVQB 56580 CPL: 3 56581 CATEGORY: GFNI 56582 EXTENSION: GFNI 56583 ISA_SET: GFNI 56584 EXCEPTIONS: E4 56585 REAL_OPCODE: Y 56586 PATTERN: 0x0F 0x3A 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8() 56587 OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u64 IMM0:r:b 56588 IFORM: GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 56589 } 56590 56591 56592 # EMITTING GF2P8AFFINEQB (GF2P8AFFINEQB-N/A-1) 56593 { 56594 ICLASS: GF2P8AFFINEQB 56595 CPL: 3 56596 CATEGORY: GFNI 56597 EXTENSION: GFNI 56598 ISA_SET: GFNI 56599 EXCEPTIONS: E4 56600 REAL_OPCODE: Y 56601 PATTERN: 0x0F 0x3A 0xCE MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8() 56602 OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u64 IMM0:r:b 56603 IFORM: GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 56604 } 56605 56606 { 56607 ICLASS: GF2P8AFFINEQB 56608 CPL: 3 56609 CATEGORY: GFNI 56610 EXTENSION: GFNI 56611 ISA_SET: GFNI 56612 EXCEPTIONS: E4 56613 REAL_OPCODE: Y 56614 PATTERN: 0x0F 0x3A 0xCE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8() 56615 OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u64 IMM0:r:b 56616 IFORM: GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 56617 } 56618 56619 56620 # EMITTING GF2P8MULB (GF2P8MULB-N/A-1) 56621 { 56622 ICLASS: GF2P8MULB 56623 CPL: 3 56624 CATEGORY: GFNI 56625 EXTENSION: GFNI 56626 ISA_SET: GFNI 56627 EXCEPTIONS: E4 56628 REAL_OPCODE: Y 56629 PATTERN: 0x0F 0x38 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix 56630 OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 56631 IFORM: GF2P8MULB_XMMu8_XMMu8 56632 } 56633 56634 { 56635 ICLASS: GF2P8MULB 56636 CPL: 3 56637 CATEGORY: GFNI 56638 EXTENSION: GFNI 56639 ISA_SET: GFNI 56640 EXCEPTIONS: E4 56641 REAL_OPCODE: Y 56642 PATTERN: 0x0F 0x38 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix 56643 OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 56644 IFORM: GF2P8MULB_XMMu8_MEMu8 56645 } 56646 56647 56648 56649 56650 ###FILE: ./datafiles/gfni-vaes-vpcl/gfni-evex-isa.xed.txt 56651 56652 #BEGIN_LEGAL 56653 # 56654 #Copyright (c) 2017 Intel Corporation 56655 # 56656 # Licensed under the Apache License, Version 2.0 (the "License"); 56657 # you may not use this file except in compliance with the License. 56658 # You may obtain a copy of the License at 56659 # 56660 # http://www.apache.org/licenses/LICENSE-2.0 56661 # 56662 # Unless required by applicable law or agreed to in writing, software 56663 # distributed under the License is distributed on an "AS IS" BASIS, 56664 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 56665 # See the License for the specific language governing permissions and 56666 # limitations under the License. 56667 # 56668 #END_LEGAL 56669 # 56670 # 56671 # 56672 # ***** GENERATED FILE -- DO NOT EDIT! ***** 56673 # ***** GENERATED FILE -- DO NOT EDIT! ***** 56674 # ***** GENERATED FILE -- DO NOT EDIT! ***** 56675 # 56676 # 56677 # 56678 EVEX_INSTRUCTIONS():: 56679 # EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-128-1) 56680 { 56681 ICLASS: VGF2P8AFFINEINVQB 56682 CPL: 3 56683 CATEGORY: GFNI 56684 EXTENSION: AVX512EVEX 56685 ISA_SET: AVX512_GFNI_128 56686 EXCEPTIONS: AVX512-E4 56687 REAL_OPCODE: Y 56688 ATTRIBUTES: MASKOP_EVEX 56689 PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 56690 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b 56691 IFORM: VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 56692 } 56693 56694 { 56695 ICLASS: VGF2P8AFFINEINVQB 56696 CPL: 3 56697 CATEGORY: GFNI 56698 EXTENSION: AVX512EVEX 56699 ISA_SET: AVX512_GFNI_128 56700 EXCEPTIONS: AVX512-E4 56701 REAL_OPCODE: Y 56702 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56703 PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 56704 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 56705 IFORM: VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 56706 } 56707 56708 56709 # EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-256-1) 56710 { 56711 ICLASS: VGF2P8AFFINEINVQB 56712 CPL: 3 56713 CATEGORY: GFNI 56714 EXTENSION: AVX512EVEX 56715 ISA_SET: AVX512_GFNI_256 56716 EXCEPTIONS: AVX512-E4 56717 REAL_OPCODE: Y 56718 ATTRIBUTES: MASKOP_EVEX 56719 PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 56720 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b 56721 IFORM: VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 56722 } 56723 56724 { 56725 ICLASS: VGF2P8AFFINEINVQB 56726 CPL: 3 56727 CATEGORY: GFNI 56728 EXTENSION: AVX512EVEX 56729 ISA_SET: AVX512_GFNI_256 56730 EXCEPTIONS: AVX512-E4 56731 REAL_OPCODE: Y 56732 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56733 PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 56734 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 56735 IFORM: VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 56736 } 56737 56738 56739 # EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-512-1) 56740 { 56741 ICLASS: VGF2P8AFFINEINVQB 56742 CPL: 3 56743 CATEGORY: GFNI 56744 EXTENSION: AVX512EVEX 56745 ISA_SET: AVX512_GFNI_512 56746 EXCEPTIONS: AVX512-E4 56747 REAL_OPCODE: Y 56748 ATTRIBUTES: MASKOP_EVEX 56749 PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 56750 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b 56751 IFORM: VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 56752 } 56753 56754 { 56755 ICLASS: VGF2P8AFFINEINVQB 56756 CPL: 3 56757 CATEGORY: GFNI 56758 EXTENSION: AVX512EVEX 56759 ISA_SET: AVX512_GFNI_512 56760 EXCEPTIONS: AVX512-E4 56761 REAL_OPCODE: Y 56762 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56763 PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 56764 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 56765 IFORM: VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 56766 } 56767 56768 56769 # EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-128-1) 56770 { 56771 ICLASS: VGF2P8AFFINEQB 56772 CPL: 3 56773 CATEGORY: GFNI 56774 EXTENSION: AVX512EVEX 56775 ISA_SET: AVX512_GFNI_128 56776 EXCEPTIONS: AVX512-E4 56777 REAL_OPCODE: Y 56778 ATTRIBUTES: MASKOP_EVEX 56779 PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() 56780 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b 56781 IFORM: VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 56782 } 56783 56784 { 56785 ICLASS: VGF2P8AFFINEQB 56786 CPL: 3 56787 CATEGORY: GFNI 56788 EXTENSION: AVX512EVEX 56789 ISA_SET: AVX512_GFNI_128 56790 EXCEPTIONS: AVX512-E4 56791 REAL_OPCODE: Y 56792 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56793 PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 56794 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 56795 IFORM: VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 56796 } 56797 56798 56799 # EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-256-1) 56800 { 56801 ICLASS: VGF2P8AFFINEQB 56802 CPL: 3 56803 CATEGORY: GFNI 56804 EXTENSION: AVX512EVEX 56805 ISA_SET: AVX512_GFNI_256 56806 EXCEPTIONS: AVX512-E4 56807 REAL_OPCODE: Y 56808 ATTRIBUTES: MASKOP_EVEX 56809 PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() 56810 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b 56811 IFORM: VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 56812 } 56813 56814 { 56815 ICLASS: VGF2P8AFFINEQB 56816 CPL: 3 56817 CATEGORY: GFNI 56818 EXTENSION: AVX512EVEX 56819 ISA_SET: AVX512_GFNI_256 56820 EXCEPTIONS: AVX512-E4 56821 REAL_OPCODE: Y 56822 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56823 PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 56824 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 56825 IFORM: VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 56826 } 56827 56828 56829 # EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-512-1) 56830 { 56831 ICLASS: VGF2P8AFFINEQB 56832 CPL: 3 56833 CATEGORY: GFNI 56834 EXTENSION: AVX512EVEX 56835 ISA_SET: AVX512_GFNI_512 56836 EXCEPTIONS: AVX512-E4 56837 REAL_OPCODE: Y 56838 ATTRIBUTES: MASKOP_EVEX 56839 PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() 56840 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b 56841 IFORM: VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 56842 } 56843 56844 { 56845 ICLASS: VGF2P8AFFINEQB 56846 CPL: 3 56847 CATEGORY: GFNI 56848 EXTENSION: AVX512EVEX 56849 ISA_SET: AVX512_GFNI_512 56850 EXCEPTIONS: AVX512-E4 56851 REAL_OPCODE: Y 56852 ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 56853 PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() 56854 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b 56855 IFORM: VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 56856 } 56857 56858 56859 # EMITTING VGF2P8MULB (VGF2P8MULB-128-1) 56860 { 56861 ICLASS: VGF2P8MULB 56862 CPL: 3 56863 CATEGORY: GFNI 56864 EXTENSION: AVX512EVEX 56865 ISA_SET: AVX512_GFNI_128 56866 EXCEPTIONS: AVX512-E4 56867 REAL_OPCODE: Y 56868 ATTRIBUTES: MASKOP_EVEX 56869 PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 56870 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 56871 IFORM: VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 56872 } 56873 56874 { 56875 ICLASS: VGF2P8MULB 56876 CPL: 3 56877 CATEGORY: GFNI 56878 EXTENSION: AVX512EVEX 56879 ISA_SET: AVX512_GFNI_128 56880 EXCEPTIONS: AVX512-E4 56881 REAL_OPCODE: Y 56882 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 56883 PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() 56884 OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 56885 IFORM: VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 56886 } 56887 56888 56889 # EMITTING VGF2P8MULB (VGF2P8MULB-256-1) 56890 { 56891 ICLASS: VGF2P8MULB 56892 CPL: 3 56893 CATEGORY: GFNI 56894 EXTENSION: AVX512EVEX 56895 ISA_SET: AVX512_GFNI_256 56896 EXCEPTIONS: AVX512-E4 56897 REAL_OPCODE: Y 56898 ATTRIBUTES: MASKOP_EVEX 56899 PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 56900 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 56901 IFORM: VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 56902 } 56903 56904 { 56905 ICLASS: VGF2P8MULB 56906 CPL: 3 56907 CATEGORY: GFNI 56908 EXTENSION: AVX512EVEX 56909 ISA_SET: AVX512_GFNI_256 56910 EXCEPTIONS: AVX512-E4 56911 REAL_OPCODE: Y 56912 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 56913 PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() 56914 OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 56915 IFORM: VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 56916 } 56917 56918 56919 # EMITTING VGF2P8MULB (VGF2P8MULB-512-1) 56920 { 56921 ICLASS: VGF2P8MULB 56922 CPL: 3 56923 CATEGORY: GFNI 56924 EXTENSION: AVX512EVEX 56925 ISA_SET: AVX512_GFNI_512 56926 EXCEPTIONS: AVX512-E4 56927 REAL_OPCODE: Y 56928 ATTRIBUTES: MASKOP_EVEX 56929 PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 56930 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 56931 IFORM: VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 56932 } 56933 56934 { 56935 ICLASS: VGF2P8MULB 56936 CPL: 3 56937 CATEGORY: GFNI 56938 EXTENSION: AVX512EVEX 56939 ISA_SET: AVX512_GFNI_512 56940 EXCEPTIONS: AVX512-E4 56941 REAL_OPCODE: Y 56942 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 56943 PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() 56944 OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 56945 IFORM: VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 56946 } 56947 56948 56949 56950 56951 ###FILE: ./datafiles/gfni-vaes-vpcl/gfni-vex-isa.xed.txt 56952 56953 #BEGIN_LEGAL 56954 # 56955 #Copyright (c) 2017 Intel Corporation 56956 # 56957 # Licensed under the Apache License, Version 2.0 (the "License"); 56958 # you may not use this file except in compliance with the License. 56959 # You may obtain a copy of the License at 56960 # 56961 # http://www.apache.org/licenses/LICENSE-2.0 56962 # 56963 # Unless required by applicable law or agreed to in writing, software 56964 # distributed under the License is distributed on an "AS IS" BASIS, 56965 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 56966 # See the License for the specific language governing permissions and 56967 # limitations under the License. 56968 # 56969 #END_LEGAL 56970 # 56971 # 56972 # 56973 # ***** GENERATED FILE -- DO NOT EDIT! ***** 56974 # ***** GENERATED FILE -- DO NOT EDIT! ***** 56975 # ***** GENERATED FILE -- DO NOT EDIT! ***** 56976 # 56977 # 56978 # 56979 AVX_INSTRUCTIONS():: 56980 # EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-128-2) 56981 { 56982 ICLASS: VGF2P8AFFINEINVQB 56983 CPL: 3 56984 CATEGORY: GFNI 56985 EXTENSION: GFNI 56986 ISA_SET: AVX_GFNI 56987 EXCEPTIONS: avx-type-4 56988 REAL_OPCODE: Y 56989 PATTERN: VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8() 56990 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u64 IMM0:r:b 56991 IFORM: VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 56992 } 56993 56994 { 56995 ICLASS: VGF2P8AFFINEINVQB 56996 CPL: 3 56997 CATEGORY: GFNI 56998 EXTENSION: GFNI 56999 ISA_SET: AVX_GFNI 57000 EXCEPTIONS: avx-type-4 57001 REAL_OPCODE: Y 57002 PATTERN: VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() 57003 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u64 IMM0:r:b 57004 IFORM: VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 57005 } 57006 57007 57008 # EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-256-2) 57009 { 57010 ICLASS: VGF2P8AFFINEINVQB 57011 CPL: 3 57012 CATEGORY: GFNI 57013 EXTENSION: GFNI 57014 ISA_SET: AVX_GFNI 57015 EXCEPTIONS: avx-type-4 57016 REAL_OPCODE: Y 57017 PATTERN: VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8() 57018 OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u64 IMM0:r:b 57019 IFORM: VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 57020 } 57021 57022 { 57023 ICLASS: VGF2P8AFFINEINVQB 57024 CPL: 3 57025 CATEGORY: GFNI 57026 EXTENSION: GFNI 57027 ISA_SET: AVX_GFNI 57028 EXCEPTIONS: avx-type-4 57029 REAL_OPCODE: Y 57030 PATTERN: VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() 57031 OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u64 IMM0:r:b 57032 IFORM: VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 57033 } 57034 57035 57036 # EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-128-2) 57037 { 57038 ICLASS: VGF2P8AFFINEQB 57039 CPL: 3 57040 CATEGORY: GFNI 57041 EXTENSION: GFNI 57042 ISA_SET: AVX_GFNI 57043 EXCEPTIONS: avx-type-4 57044 REAL_OPCODE: Y 57045 PATTERN: VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8() 57046 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u64 IMM0:r:b 57047 IFORM: VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 57048 } 57049 57050 { 57051 ICLASS: VGF2P8AFFINEQB 57052 CPL: 3 57053 CATEGORY: GFNI 57054 EXTENSION: GFNI 57055 ISA_SET: AVX_GFNI 57056 EXCEPTIONS: avx-type-4 57057 REAL_OPCODE: Y 57058 PATTERN: VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() 57059 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u64 IMM0:r:b 57060 IFORM: VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 57061 } 57062 57063 57064 # EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-256-2) 57065 { 57066 ICLASS: VGF2P8AFFINEQB 57067 CPL: 3 57068 CATEGORY: GFNI 57069 EXTENSION: GFNI 57070 ISA_SET: AVX_GFNI 57071 EXCEPTIONS: avx-type-4 57072 REAL_OPCODE: Y 57073 PATTERN: VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8() 57074 OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u64 IMM0:r:b 57075 IFORM: VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 57076 } 57077 57078 { 57079 ICLASS: VGF2P8AFFINEQB 57080 CPL: 3 57081 CATEGORY: GFNI 57082 EXTENSION: GFNI 57083 ISA_SET: AVX_GFNI 57084 EXCEPTIONS: avx-type-4 57085 REAL_OPCODE: Y 57086 PATTERN: VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() 57087 OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u64 IMM0:r:b 57088 IFORM: VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 57089 } 57090 57091 57092 # EMITTING VGF2P8MULB (VGF2P8MULB-128-2) 57093 { 57094 ICLASS: VGF2P8MULB 57095 CPL: 3 57096 CATEGORY: GFNI 57097 EXTENSION: GFNI 57098 ISA_SET: AVX_GFNI 57099 EXCEPTIONS: avx-type-4 57100 REAL_OPCODE: Y 57101 PATTERN: VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 57102 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 57103 IFORM: VGF2P8MULB_XMMu8_XMMu8_XMMu8 57104 } 57105 57106 { 57107 ICLASS: VGF2P8MULB 57108 CPL: 3 57109 CATEGORY: GFNI 57110 EXTENSION: GFNI 57111 ISA_SET: AVX_GFNI 57112 EXCEPTIONS: avx-type-4 57113 REAL_OPCODE: Y 57114 PATTERN: VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 57115 OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 57116 IFORM: VGF2P8MULB_XMMu8_XMMu8_MEMu8 57117 } 57118 57119 57120 # EMITTING VGF2P8MULB (VGF2P8MULB-256-2) 57121 { 57122 ICLASS: VGF2P8MULB 57123 CPL: 3 57124 CATEGORY: GFNI 57125 EXTENSION: GFNI 57126 ISA_SET: AVX_GFNI 57127 EXCEPTIONS: avx-type-4 57128 REAL_OPCODE: Y 57129 PATTERN: VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 57130 OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 57131 IFORM: VGF2P8MULB_YMMu8_YMMu8_YMMu8 57132 } 57133 57134 { 57135 ICLASS: VGF2P8MULB 57136 CPL: 3 57137 CATEGORY: GFNI 57138 EXTENSION: GFNI 57139 ISA_SET: AVX_GFNI 57140 EXCEPTIONS: avx-type-4 57141 REAL_OPCODE: Y 57142 PATTERN: VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 57143 OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 57144 IFORM: VGF2P8MULB_YMMu8_YMMu8_MEMu8 57145 } 57146 57147 57148 57149 57150 ###FILE: ./datafiles/gfni-vaes-vpcl/vaes-evex-isa.xed.txt 57151 57152 #BEGIN_LEGAL 57153 # 57154 #Copyright (c) 2017 Intel Corporation 57155 # 57156 # Licensed under the Apache License, Version 2.0 (the "License"); 57157 # you may not use this file except in compliance with the License. 57158 # You may obtain a copy of the License at 57159 # 57160 # http://www.apache.org/licenses/LICENSE-2.0 57161 # 57162 # Unless required by applicable law or agreed to in writing, software 57163 # distributed under the License is distributed on an "AS IS" BASIS, 57164 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 57165 # See the License for the specific language governing permissions and 57166 # limitations under the License. 57167 # 57168 #END_LEGAL 57169 # 57170 # 57171 # 57172 # ***** GENERATED FILE -- DO NOT EDIT! ***** 57173 # ***** GENERATED FILE -- DO NOT EDIT! ***** 57174 # ***** GENERATED FILE -- DO NOT EDIT! ***** 57175 # 57176 # 57177 # 57178 EVEX_INSTRUCTIONS():: 57179 # EMITTING VAESDEC (VAESDEC-128-1) 57180 { 57181 ICLASS: VAESDEC 57182 CPL: 3 57183 CATEGORY: VAES 57184 EXTENSION: AVX512EVEX 57185 ISA_SET: AVX512_VAES_128 57186 EXCEPTIONS: AVX512-E4 57187 REAL_OPCODE: Y 57188 PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 57189 OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 57190 IFORM: VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 57191 } 57192 57193 { 57194 ICLASS: VAESDEC 57195 CPL: 3 57196 CATEGORY: VAES 57197 EXTENSION: AVX512EVEX 57198 ISA_SET: AVX512_VAES_128 57199 EXCEPTIONS: AVX512-E4 57200 REAL_OPCODE: Y 57201 ATTRIBUTES: DISP8_FULLMEM 57202 PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() 57203 OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 57204 IFORM: VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 57205 } 57206 57207 57208 # EMITTING VAESDEC (VAESDEC-256-1) 57209 { 57210 ICLASS: VAESDEC 57211 CPL: 3 57212 CATEGORY: VAES 57213 EXTENSION: AVX512EVEX 57214 ISA_SET: AVX512_VAES_256 57215 EXCEPTIONS: AVX512-E4 57216 REAL_OPCODE: Y 57217 PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 57218 OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 57219 IFORM: VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 57220 } 57221 57222 { 57223 ICLASS: VAESDEC 57224 CPL: 3 57225 CATEGORY: VAES 57226 EXTENSION: AVX512EVEX 57227 ISA_SET: AVX512_VAES_256 57228 EXCEPTIONS: AVX512-E4 57229 REAL_OPCODE: Y 57230 ATTRIBUTES: DISP8_FULLMEM 57231 PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() 57232 OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 57233 IFORM: VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 57234 } 57235 57236 57237 # EMITTING VAESDEC (VAESDEC-512-1) 57238 { 57239 ICLASS: VAESDEC 57240 CPL: 3 57241 CATEGORY: VAES 57242 EXTENSION: AVX512EVEX 57243 ISA_SET: AVX512_VAES_512 57244 EXCEPTIONS: AVX512-E4 57245 REAL_OPCODE: Y 57246 PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 57247 OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 57248 IFORM: VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 57249 } 57250 57251 { 57252 ICLASS: VAESDEC 57253 CPL: 3 57254 CATEGORY: VAES 57255 EXTENSION: AVX512EVEX 57256 ISA_SET: AVX512_VAES_512 57257 EXCEPTIONS: AVX512-E4 57258 REAL_OPCODE: Y 57259 ATTRIBUTES: DISP8_FULLMEM 57260 PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() 57261 OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 57262 IFORM: VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 57263 } 57264 57265 57266 # EMITTING VAESDECLAST (VAESDECLAST-128-1) 57267 { 57268 ICLASS: VAESDECLAST 57269 CPL: 3 57270 CATEGORY: VAES 57271 EXTENSION: AVX512EVEX 57272 ISA_SET: AVX512_VAES_128 57273 EXCEPTIONS: AVX512-E4 57274 REAL_OPCODE: Y 57275 PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 57276 OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 57277 IFORM: VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 57278 } 57279 57280 { 57281 ICLASS: VAESDECLAST 57282 CPL: 3 57283 CATEGORY: VAES 57284 EXTENSION: AVX512EVEX 57285 ISA_SET: AVX512_VAES_128 57286 EXCEPTIONS: AVX512-E4 57287 REAL_OPCODE: Y 57288 ATTRIBUTES: DISP8_FULLMEM 57289 PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() 57290 OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 57291 IFORM: VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 57292 } 57293 57294 57295 # EMITTING VAESDECLAST (VAESDECLAST-256-1) 57296 { 57297 ICLASS: VAESDECLAST 57298 CPL: 3 57299 CATEGORY: VAES 57300 EXTENSION: AVX512EVEX 57301 ISA_SET: AVX512_VAES_256 57302 EXCEPTIONS: AVX512-E4 57303 REAL_OPCODE: Y 57304 PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 57305 OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 57306 IFORM: VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 57307 } 57308 57309 { 57310 ICLASS: VAESDECLAST 57311 CPL: 3 57312 CATEGORY: VAES 57313 EXTENSION: AVX512EVEX 57314 ISA_SET: AVX512_VAES_256 57315 EXCEPTIONS: AVX512-E4 57316 REAL_OPCODE: Y 57317 ATTRIBUTES: DISP8_FULLMEM 57318 PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() 57319 OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 57320 IFORM: VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 57321 } 57322 57323 57324 # EMITTING VAESDECLAST (VAESDECLAST-512-1) 57325 { 57326 ICLASS: VAESDECLAST 57327 CPL: 3 57328 CATEGORY: VAES 57329 EXTENSION: AVX512EVEX 57330 ISA_SET: AVX512_VAES_512 57331 EXCEPTIONS: AVX512-E4 57332 REAL_OPCODE: Y 57333 PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 57334 OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 57335 IFORM: VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 57336 } 57337 57338 { 57339 ICLASS: VAESDECLAST 57340 CPL: 3 57341 CATEGORY: VAES 57342 EXTENSION: AVX512EVEX 57343 ISA_SET: AVX512_VAES_512 57344 EXCEPTIONS: AVX512-E4 57345 REAL_OPCODE: Y 57346 ATTRIBUTES: DISP8_FULLMEM 57347 PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() 57348 OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 57349 IFORM: VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 57350 } 57351 57352 57353 # EMITTING VAESENC (VAESENC-128-1) 57354 { 57355 ICLASS: VAESENC 57356 CPL: 3 57357 CATEGORY: VAES 57358 EXTENSION: AVX512EVEX 57359 ISA_SET: AVX512_VAES_128 57360 EXCEPTIONS: AVX512-E4 57361 REAL_OPCODE: Y 57362 PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 57363 OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 57364 IFORM: VAESENC_XMMu128_XMMu128_XMMu128_AVX512 57365 } 57366 57367 { 57368 ICLASS: VAESENC 57369 CPL: 3 57370 CATEGORY: VAES 57371 EXTENSION: AVX512EVEX 57372 ISA_SET: AVX512_VAES_128 57373 EXCEPTIONS: AVX512-E4 57374 REAL_OPCODE: Y 57375 ATTRIBUTES: DISP8_FULLMEM 57376 PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() 57377 OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 57378 IFORM: VAESENC_XMMu128_XMMu128_MEMu128_AVX512 57379 } 57380 57381 57382 # EMITTING VAESENC (VAESENC-256-1) 57383 { 57384 ICLASS: VAESENC 57385 CPL: 3 57386 CATEGORY: VAES 57387 EXTENSION: AVX512EVEX 57388 ISA_SET: AVX512_VAES_256 57389 EXCEPTIONS: AVX512-E4 57390 REAL_OPCODE: Y 57391 PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 57392 OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 57393 IFORM: VAESENC_YMMu128_YMMu128_YMMu128_AVX512 57394 } 57395 57396 { 57397 ICLASS: VAESENC 57398 CPL: 3 57399 CATEGORY: VAES 57400 EXTENSION: AVX512EVEX 57401 ISA_SET: AVX512_VAES_256 57402 EXCEPTIONS: AVX512-E4 57403 REAL_OPCODE: Y 57404 ATTRIBUTES: DISP8_FULLMEM 57405 PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() 57406 OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 57407 IFORM: VAESENC_YMMu128_YMMu128_MEMu128_AVX512 57408 } 57409 57410 57411 # EMITTING VAESENC (VAESENC-512-1) 57412 { 57413 ICLASS: VAESENC 57414 CPL: 3 57415 CATEGORY: VAES 57416 EXTENSION: AVX512EVEX 57417 ISA_SET: AVX512_VAES_512 57418 EXCEPTIONS: AVX512-E4 57419 REAL_OPCODE: Y 57420 PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 57421 OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 57422 IFORM: VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 57423 } 57424 57425 { 57426 ICLASS: VAESENC 57427 CPL: 3 57428 CATEGORY: VAES 57429 EXTENSION: AVX512EVEX 57430 ISA_SET: AVX512_VAES_512 57431 EXCEPTIONS: AVX512-E4 57432 REAL_OPCODE: Y 57433 ATTRIBUTES: DISP8_FULLMEM 57434 PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() 57435 OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 57436 IFORM: VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 57437 } 57438 57439 57440 # EMITTING VAESENCLAST (VAESENCLAST-128-1) 57441 { 57442 ICLASS: VAESENCLAST 57443 CPL: 3 57444 CATEGORY: VAES 57445 EXTENSION: AVX512EVEX 57446 ISA_SET: AVX512_VAES_128 57447 EXCEPTIONS: AVX512-E4 57448 REAL_OPCODE: Y 57449 PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 57450 OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 57451 IFORM: VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 57452 } 57453 57454 { 57455 ICLASS: VAESENCLAST 57456 CPL: 3 57457 CATEGORY: VAES 57458 EXTENSION: AVX512EVEX 57459 ISA_SET: AVX512_VAES_128 57460 EXCEPTIONS: AVX512-E4 57461 REAL_OPCODE: Y 57462 ATTRIBUTES: DISP8_FULLMEM 57463 PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() 57464 OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 57465 IFORM: VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 57466 } 57467 57468 57469 # EMITTING VAESENCLAST (VAESENCLAST-256-1) 57470 { 57471 ICLASS: VAESENCLAST 57472 CPL: 3 57473 CATEGORY: VAES 57474 EXTENSION: AVX512EVEX 57475 ISA_SET: AVX512_VAES_256 57476 EXCEPTIONS: AVX512-E4 57477 REAL_OPCODE: Y 57478 PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 57479 OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 57480 IFORM: VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 57481 } 57482 57483 { 57484 ICLASS: VAESENCLAST 57485 CPL: 3 57486 CATEGORY: VAES 57487 EXTENSION: AVX512EVEX 57488 ISA_SET: AVX512_VAES_256 57489 EXCEPTIONS: AVX512-E4 57490 REAL_OPCODE: Y 57491 ATTRIBUTES: DISP8_FULLMEM 57492 PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() 57493 OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 57494 IFORM: VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 57495 } 57496 57497 57498 # EMITTING VAESENCLAST (VAESENCLAST-512-1) 57499 { 57500 ICLASS: VAESENCLAST 57501 CPL: 3 57502 CATEGORY: VAES 57503 EXTENSION: AVX512EVEX 57504 ISA_SET: AVX512_VAES_512 57505 EXCEPTIONS: AVX512-E4 57506 REAL_OPCODE: Y 57507 PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 57508 OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 57509 IFORM: VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 57510 } 57511 57512 { 57513 ICLASS: VAESENCLAST 57514 CPL: 3 57515 CATEGORY: VAES 57516 EXTENSION: AVX512EVEX 57517 ISA_SET: AVX512_VAES_512 57518 EXCEPTIONS: AVX512-E4 57519 REAL_OPCODE: Y 57520 ATTRIBUTES: DISP8_FULLMEM 57521 PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() 57522 OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 57523 IFORM: VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 57524 } 57525 57526 57527 # EMITTING VPCLMULQDQ (VPCLMULQDQ-128-1) 57528 { 57529 ICLASS: VPCLMULQDQ 57530 CPL: 3 57531 CATEGORY: VPCLMULQDQ 57532 EXTENSION: AVX512EVEX 57533 ISA_SET: AVX512_VPCLMULQDQ_128 57534 EXCEPTIONS: AVX512-E4 57535 REAL_OPCODE: Y 57536 PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() 57537 OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64 IMM0:r:b 57538 IFORM: VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 57539 } 57540 57541 { 57542 ICLASS: VPCLMULQDQ 57543 CPL: 3 57544 CATEGORY: VPCLMULQDQ 57545 EXTENSION: AVX512EVEX 57546 ISA_SET: AVX512_VPCLMULQDQ_128 57547 EXCEPTIONS: AVX512-E4 57548 REAL_OPCODE: Y 57549 ATTRIBUTES: DISP8_FULLMEM 57550 PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() 57551 OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b 57552 IFORM: VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 57553 } 57554 57555 57556 # EMITTING VPCLMULQDQ (VPCLMULQDQ-256-1) 57557 { 57558 ICLASS: VPCLMULQDQ 57559 CPL: 3 57560 CATEGORY: VPCLMULQDQ 57561 EXTENSION: AVX512EVEX 57562 ISA_SET: AVX512_VPCLMULQDQ_256 57563 EXCEPTIONS: AVX512-E4 57564 REAL_OPCODE: Y 57565 PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() 57566 OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 REG2=YMM_B3():r:qq:u64 IMM0:r:b 57567 IFORM: VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 57568 } 57569 57570 { 57571 ICLASS: VPCLMULQDQ 57572 CPL: 3 57573 CATEGORY: VPCLMULQDQ 57574 EXTENSION: AVX512EVEX 57575 ISA_SET: AVX512_VPCLMULQDQ_256 57576 EXCEPTIONS: AVX512-E4 57577 REAL_OPCODE: Y 57578 ATTRIBUTES: DISP8_FULLMEM 57579 PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() 57580 OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b 57581 IFORM: VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 57582 } 57583 57584 57585 # EMITTING VPCLMULQDQ (VPCLMULQDQ-512-1) 57586 { 57587 ICLASS: VPCLMULQDQ 57588 CPL: 3 57589 CATEGORY: VPCLMULQDQ 57590 EXTENSION: AVX512EVEX 57591 ISA_SET: AVX512_VPCLMULQDQ_512 57592 EXCEPTIONS: AVX512-E4 57593 REAL_OPCODE: Y 57594 PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() 57595 OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 REG2=ZMM_B3():r:zu64 IMM0:r:b 57596 IFORM: VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 57597 } 57598 57599 { 57600 ICLASS: VPCLMULQDQ 57601 CPL: 3 57602 CATEGORY: VPCLMULQDQ 57603 EXTENSION: AVX512EVEX 57604 ISA_SET: AVX512_VPCLMULQDQ_512 57605 EXCEPTIONS: AVX512-E4 57606 REAL_OPCODE: Y 57607 ATTRIBUTES: DISP8_FULLMEM 57608 PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() 57609 OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 MEM0:r:zd:u64 IMM0:r:b 57610 IFORM: VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 57611 } 57612 57613 57614 57615 57616 ###FILE: ./datafiles/gfni-vaes-vpcl/vaes-vex-isa.xed.txt 57617 57618 #BEGIN_LEGAL 57619 # 57620 #Copyright (c) 2017 Intel Corporation 57621 # 57622 # Licensed under the Apache License, Version 2.0 (the "License"); 57623 # you may not use this file except in compliance with the License. 57624 # You may obtain a copy of the License at 57625 # 57626 # http://www.apache.org/licenses/LICENSE-2.0 57627 # 57628 # Unless required by applicable law or agreed to in writing, software 57629 # distributed under the License is distributed on an "AS IS" BASIS, 57630 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 57631 # See the License for the specific language governing permissions and 57632 # limitations under the License. 57633 # 57634 #END_LEGAL 57635 # 57636 # 57637 # 57638 # ***** GENERATED FILE -- DO NOT EDIT! ***** 57639 # ***** GENERATED FILE -- DO NOT EDIT! ***** 57640 # ***** GENERATED FILE -- DO NOT EDIT! ***** 57641 # 57642 # 57643 # 57644 AVX_INSTRUCTIONS():: 57645 # EMITTING VAESDEC (VAESDEC-256-2) 57646 { 57647 ICLASS: VAESDEC 57648 CPL: 3 57649 CATEGORY: VAES 57650 EXTENSION: VAES 57651 ISA_SET: VAES 57652 EXCEPTIONS: avx-type-4 57653 REAL_OPCODE: Y 57654 PATTERN: VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 57655 OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 57656 IFORM: VAESDEC_YMMu128_YMMu128_YMMu128 57657 } 57658 57659 { 57660 ICLASS: VAESDEC 57661 CPL: 3 57662 CATEGORY: VAES 57663 EXTENSION: VAES 57664 ISA_SET: VAES 57665 EXCEPTIONS: avx-type-4 57666 REAL_OPCODE: Y 57667 PATTERN: VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 57668 OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 57669 IFORM: VAESDEC_YMMu128_YMMu128_MEMu128 57670 } 57671 57672 57673 # EMITTING VAESDECLAST (VAESDECLAST-256-2) 57674 { 57675 ICLASS: VAESDECLAST 57676 CPL: 3 57677 CATEGORY: VAES 57678 EXTENSION: VAES 57679 ISA_SET: VAES 57680 EXCEPTIONS: avx-type-4 57681 REAL_OPCODE: Y 57682 PATTERN: VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 57683 OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 57684 IFORM: VAESDECLAST_YMMu128_YMMu128_YMMu128 57685 } 57686 57687 { 57688 ICLASS: VAESDECLAST 57689 CPL: 3 57690 CATEGORY: VAES 57691 EXTENSION: VAES 57692 ISA_SET: VAES 57693 EXCEPTIONS: avx-type-4 57694 REAL_OPCODE: Y 57695 PATTERN: VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 57696 OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 57697 IFORM: VAESDECLAST_YMMu128_YMMu128_MEMu128 57698 } 57699 57700 57701 # EMITTING VAESENC (VAESENC-256-2) 57702 { 57703 ICLASS: VAESENC 57704 CPL: 3 57705 CATEGORY: VAES 57706 EXTENSION: VAES 57707 ISA_SET: VAES 57708 EXCEPTIONS: avx-type-4 57709 REAL_OPCODE: Y 57710 PATTERN: VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 57711 OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 57712 IFORM: VAESENC_YMMu128_YMMu128_YMMu128 57713 } 57714 57715 { 57716 ICLASS: VAESENC 57717 CPL: 3 57718 CATEGORY: VAES 57719 EXTENSION: VAES 57720 ISA_SET: VAES 57721 EXCEPTIONS: avx-type-4 57722 REAL_OPCODE: Y 57723 PATTERN: VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 57724 OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 57725 IFORM: VAESENC_YMMu128_YMMu128_MEMu128 57726 } 57727 57728 57729 # EMITTING VAESENCLAST (VAESENCLAST-256-2) 57730 { 57731 ICLASS: VAESENCLAST 57732 CPL: 3 57733 CATEGORY: VAES 57734 EXTENSION: VAES 57735 ISA_SET: VAES 57736 EXCEPTIONS: avx-type-4 57737 REAL_OPCODE: Y 57738 PATTERN: VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 57739 OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 57740 IFORM: VAESENCLAST_YMMu128_YMMu128_YMMu128 57741 } 57742 57743 { 57744 ICLASS: VAESENCLAST 57745 CPL: 3 57746 CATEGORY: VAES 57747 EXTENSION: VAES 57748 ISA_SET: VAES 57749 EXCEPTIONS: avx-type-4 57750 REAL_OPCODE: Y 57751 PATTERN: VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 57752 OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 57753 IFORM: VAESENCLAST_YMMu128_YMMu128_MEMu128 57754 } 57755 57756 57757 # EMITTING VPCLMULQDQ (VPCLMULQDQ-256-2) 57758 { 57759 ICLASS: VPCLMULQDQ 57760 CPL: 3 57761 CATEGORY: VPCLMULQDQ 57762 EXTENSION: VPCLMULQDQ 57763 ISA_SET: VPCLMULQDQ 57764 EXCEPTIONS: avx-type-4 57765 REAL_OPCODE: Y 57766 PATTERN: VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 UIMM8() 57767 OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 IMM0:r:b 57768 IFORM: VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 57769 } 57770 57771 { 57772 ICLASS: VPCLMULQDQ 57773 CPL: 3 57774 CATEGORY: VPCLMULQDQ 57775 EXTENSION: VPCLMULQDQ 57776 ISA_SET: VPCLMULQDQ 57777 EXCEPTIONS: avx-type-4 57778 REAL_OPCODE: Y 57779 PATTERN: VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 UIMM8() 57780 OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b 57781 IFORM: VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 57782 } 57783 57784 57785 57786 57787 ###FILE: ./datafiles/vpopcntdq-vl/vpopcntdq-vl-isa.xed.txt 57788 57789 #BEGIN_LEGAL 57790 # 57791 #Copyright (c) 2017 Intel Corporation 57792 # 57793 # Licensed under the Apache License, Version 2.0 (the "License"); 57794 # you may not use this file except in compliance with the License. 57795 # You may obtain a copy of the License at 57796 # 57797 # http://www.apache.org/licenses/LICENSE-2.0 57798 # 57799 # Unless required by applicable law or agreed to in writing, software 57800 # distributed under the License is distributed on an "AS IS" BASIS, 57801 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 57802 # See the License for the specific language governing permissions and 57803 # limitations under the License. 57804 # 57805 #END_LEGAL 57806 # 57807 # 57808 # 57809 # ***** GENERATED FILE -- DO NOT EDIT! ***** 57810 # ***** GENERATED FILE -- DO NOT EDIT! ***** 57811 # ***** GENERATED FILE -- DO NOT EDIT! ***** 57812 # 57813 # 57814 # 57815 EVEX_INSTRUCTIONS():: 57816 # EMITTING VPOPCNTD (VPOPCNTD-128-1) 57817 { 57818 ICLASS: VPOPCNTD 57819 CPL: 3 57820 CATEGORY: AVX512 57821 EXTENSION: AVX512EVEX 57822 ISA_SET: AVX512_VPOPCNTDQ_128 57823 EXCEPTIONS: AVX512-E4 57824 REAL_OPCODE: Y 57825 ATTRIBUTES: MASKOP_EVEX 57826 PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR 57827 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 57828 IFORM: VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 57829 } 57830 57831 { 57832 ICLASS: VPOPCNTD 57833 CPL: 3 57834 CATEGORY: AVX512 57835 EXTENSION: AVX512EVEX 57836 ISA_SET: AVX512_VPOPCNTDQ_128 57837 EXCEPTIONS: AVX512-E4 57838 REAL_OPCODE: Y 57839 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57840 PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 57841 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 57842 IFORM: VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 57843 } 57844 57845 57846 # EMITTING VPOPCNTD (VPOPCNTD-256-1) 57847 { 57848 ICLASS: VPOPCNTD 57849 CPL: 3 57850 CATEGORY: AVX512 57851 EXTENSION: AVX512EVEX 57852 ISA_SET: AVX512_VPOPCNTDQ_256 57853 EXCEPTIONS: AVX512-E4 57854 REAL_OPCODE: Y 57855 ATTRIBUTES: MASKOP_EVEX 57856 PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR 57857 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 57858 IFORM: VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 57859 } 57860 57861 { 57862 ICLASS: VPOPCNTD 57863 CPL: 3 57864 CATEGORY: AVX512 57865 EXTENSION: AVX512EVEX 57866 ISA_SET: AVX512_VPOPCNTDQ_256 57867 EXCEPTIONS: AVX512-E4 57868 REAL_OPCODE: Y 57869 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57870 PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() 57871 OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR 57872 IFORM: VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 57873 } 57874 57875 57876 # EMITTING VPOPCNTQ (VPOPCNTQ-128-1) 57877 { 57878 ICLASS: VPOPCNTQ 57879 CPL: 3 57880 CATEGORY: AVX512 57881 EXTENSION: AVX512EVEX 57882 ISA_SET: AVX512_VPOPCNTDQ_128 57883 EXCEPTIONS: AVX512-E4 57884 REAL_OPCODE: Y 57885 ATTRIBUTES: MASKOP_EVEX 57886 PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR 57887 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 57888 IFORM: VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 57889 } 57890 57891 { 57892 ICLASS: VPOPCNTQ 57893 CPL: 3 57894 CATEGORY: AVX512 57895 EXTENSION: AVX512EVEX 57896 ISA_SET: AVX512_VPOPCNTDQ_128 57897 EXCEPTIONS: AVX512-E4 57898 REAL_OPCODE: Y 57899 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57900 PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 57901 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 57902 IFORM: VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 57903 } 57904 57905 57906 # EMITTING VPOPCNTQ (VPOPCNTQ-256-1) 57907 { 57908 ICLASS: VPOPCNTQ 57909 CPL: 3 57910 CATEGORY: AVX512 57911 EXTENSION: AVX512EVEX 57912 ISA_SET: AVX512_VPOPCNTDQ_256 57913 EXCEPTIONS: AVX512-E4 57914 REAL_OPCODE: Y 57915 ATTRIBUTES: MASKOP_EVEX 57916 PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR 57917 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 57918 IFORM: VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 57919 } 57920 57921 { 57922 ICLASS: VPOPCNTQ 57923 CPL: 3 57924 CATEGORY: AVX512 57925 EXTENSION: AVX512EVEX 57926 ISA_SET: AVX512_VPOPCNTDQ_256 57927 EXCEPTIONS: AVX512-E4 57928 REAL_OPCODE: Y 57929 ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 57930 PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() 57931 OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR 57932 IFORM: VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 57933 } 57934 57935 57936 57937 57938 ###FILE: ./datafiles/rdpid/rdpid-isa.xed.txt 57939 57940 #BEGIN_LEGAL 57941 # 57942 #Copyright (c) 2017 Intel Corporation 57943 # 57944 # Licensed under the Apache License, Version 2.0 (the "License"); 57945 # you may not use this file except in compliance with the License. 57946 # You may obtain a copy of the License at 57947 # 57948 # http://www.apache.org/licenses/LICENSE-2.0 57949 # 57950 # Unless required by applicable law or agreed to in writing, software 57951 # distributed under the License is distributed on an "AS IS" BASIS, 57952 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 57953 # See the License for the specific language governing permissions and 57954 # limitations under the License. 57955 # 57956 #END_LEGAL 57957 # 57958 # 57959 # 57960 # ***** GENERATED FILE -- DO NOT EDIT! ***** 57961 # ***** GENERATED FILE -- DO NOT EDIT! ***** 57962 # ***** GENERATED FILE -- DO NOT EDIT! ***** 57963 # 57964 # 57965 # 57966 INSTRUCTIONS():: 57967 # EMITTING RDPID (RDPID-N/A-1-32) 57968 { 57969 ICLASS: RDPID 57970 CPL: 3 57971 CATEGORY: RDPID 57972 EXTENSION: RDPID 57973 ISA_SET: RDPID 57974 REAL_OPCODE: N 57975 PATTERN: 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64 57976 OPERANDS: REG0=GPR32_B():r:d:u32 REG1=XED_REG_TSCAUX:r:SUPP:d:u32 57977 IFORM: RDPID_GPR32u32 57978 } 57979 57980 57981 # EMITTING RDPID (RDPID-N/A-1-64) 57982 { 57983 ICLASS: RDPID 57984 CPL: 3 57985 CATEGORY: RDPID 57986 EXTENSION: RDPID 57987 ISA_SET: RDPID 57988 REAL_OPCODE: N 57989 PATTERN: 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64 57990 OPERANDS: REG0=GPR64_B():r:q:u64 REG1=XED_REG_TSCAUX:r:SUPP:d:u32 57991 IFORM: RDPID_GPR64u64 57992 } 57993 57994 57995 57996 57997 ###FILE: ./datafiles/pt/intelpt-isa.xed.txt 57998 57999 #BEGIN_LEGAL 58000 # 58001 #Copyright (c) 2016 Intel Corporation 58002 # 58003 # Licensed under the Apache License, Version 2.0 (the "License"); 58004 # you may not use this file except in compliance with the License. 58005 # You may obtain a copy of the License at 58006 # 58007 # http://www.apache.org/licenses/LICENSE-2.0 58008 # 58009 # Unless required by applicable law or agreed to in writing, software 58010 # distributed under the License is distributed on an "AS IS" BASIS, 58011 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 58012 # See the License for the specific language governing permissions and 58013 # limitations under the License. 58014 # 58015 #END_LEGAL 58016 58017 58018 INSTRUCTIONS():: 58019 { 58020 ICLASS : PTWRITE 58021 CPL : 3 58022 CATEGORY : PT 58023 EXTENSION : PT 58024 PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix 58025 OPERANDS : REG0=GPRy_B():r 58026 PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM() 58027 OPERANDS : MEM0:r:y 58028 58029 } 58030 58031 58032 58033 58034 ###FILE: ./datafiles/sha512/sha512-isa.xed.txt 58035 58036 #BEGIN_LEGAL 58037 # 58038 #Copyright (c) 2023 Intel Corporation 58039 # 58040 # Licensed under the Apache License, Version 2.0 (the "License"); 58041 # you may not use this file except in compliance with the License. 58042 # You may obtain a copy of the License at 58043 # 58044 # http://www.apache.org/licenses/LICENSE-2.0 58045 # 58046 # Unless required by applicable law or agreed to in writing, software 58047 # distributed under the License is distributed on an "AS IS" BASIS, 58048 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 58049 # See the License for the specific language governing permissions and 58050 # limitations under the License. 58051 # 58052 #END_LEGAL 58053 # 58054 # 58055 # 58056 # ***** GENERATED FILE -- DO NOT EDIT! ***** 58057 # ***** GENERATED FILE -- DO NOT EDIT! ***** 58058 # ***** GENERATED FILE -- DO NOT EDIT! ***** 58059 # 58060 # 58061 # 58062 AVX_INSTRUCTIONS():: 58063 # EMITTING VSHA512MSG1 (VSHA512MSG1-256-1) 58064 { 58065 ICLASS: VSHA512MSG1 58066 CPL: 3 58067 CATEGORY: SHA512 58068 EXTENSION: SHA512 58069 ISA_SET: SHA512 58070 EXCEPTIONS: avx-type-6 58071 REAL_OPCODE: Y 58072 PATTERN: VV1 0xCC VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 NOVSR 58073 OPERANDS: REG0=YMM_R():rw:qq:u64 REG1=XMM_B():r:dq:u64 58074 IFORM: VSHA512MSG1_YMMu64_XMMu64 58075 } 58076 58077 58078 # EMITTING VSHA512MSG2 (VSHA512MSG2-256-1) 58079 { 58080 ICLASS: VSHA512MSG2 58081 CPL: 3 58082 CATEGORY: SHA512 58083 EXTENSION: SHA512 58084 ISA_SET: SHA512 58085 EXCEPTIONS: avx-type-6 58086 REAL_OPCODE: Y 58087 PATTERN: VV1 0xCD VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 NOVSR 58088 OPERANDS: REG0=YMM_R():rw:qq:u64 REG1=YMM_B():r:qq:u64 58089 IFORM: VSHA512MSG2_YMMu64_YMMu64 58090 } 58091 58092 58093 # EMITTING VSHA512RNDS2 (VSHA512RNDS2-256-1) 58094 { 58095 ICLASS: VSHA512RNDS2 58096 CPL: 3 58097 CATEGORY: SHA512 58098 EXTENSION: SHA512 58099 ISA_SET: SHA512 58100 EXCEPTIONS: avx-type-6 58101 REAL_OPCODE: Y 58102 PATTERN: VV1 0xCB VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 58103 OPERANDS: REG0=YMM_R():rw:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:dq:u64 58104 IFORM: VSHA512RNDS2_YMMu64_YMMu64_XMMu64 58105 }