gvisor.dev/gvisor@v0.0.0-20240520182842-f9d4d51c7e0f/pkg/abi/nvgpu/ctrl.go (about) 1 // Copyright 2023 The gVisor Authors. 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 package nvgpu 16 17 // From src/nvidia/interface/deprecated/rmapi_deprecated.h: 18 const ( 19 RM_GSS_LEGACY_MASK = 0x00008000 20 ) 21 22 // From src/nvidia/inc/kernel/rmapi/param_copy.h: 23 const ( 24 // RMAPI_PARAM_COPY_MAX_PARAMS_SIZE is the size limit imposed while copying 25 // "embedded pointers" in rmapi parameter structs. 26 // See src/nvidia/src/kernel/rmapi/param_copy.c:rmapiParamsAcquire(). 27 RMAPI_PARAM_COPY_MAX_PARAMS_SIZE = 1 * 1024 * 1024 28 ) 29 30 // From src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h: 31 32 // +marshal 33 type NVXXXX_CTRL_XXX_INFO struct { 34 Index uint32 35 Data uint32 36 } 37 38 // From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h: 39 const ( 40 NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE = 0xd01 41 NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY = 0xd04 42 ) 43 44 // From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h: 45 const ( 46 NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS = 0x201 47 NV0000_CTRL_CMD_GPU_GET_ID_INFO = 0x202 48 NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 = 0x205 49 NV0000_CTRL_CMD_GPU_GET_PROBED_IDS = 0x214 50 NV0000_CTRL_CMD_GPU_ATTACH_IDS = 0x215 51 NV0000_CTRL_CMD_GPU_DETACH_IDS = 0x216 52 NV0000_CTRL_CMD_GPU_GET_PCI_INFO = 0x21b 53 NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE = 0x279 54 NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE = 0x27b 55 NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID = 0x289 56 NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID = 0x290 57 ) 58 59 // From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h: 60 const ( 61 NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO = 0xa04 62 ) 63 64 // From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h: 65 const ( 66 NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION = 0x101 67 NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS = 0x127 68 NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 = 0x12b 69 NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS = 0x136 70 NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX = 0x13a 71 NV0000_CTRL_CMD_SYSTEM_GET_FEATURES = 0x1f0 72 ) 73 74 // From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h: 75 const ( 76 NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD = 0x3d05 77 ) 78 79 // +marshal 80 type NV0000_CTRL_OS_UNIX_EXPORT_OBJECT struct { 81 Type uint32 // enum NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE 82 // These fields are inside union `data`, in struct `rmObject`. 83 HDevice Handle 84 HParent Handle 85 HObject Handle 86 } 87 88 // +marshal 89 type NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS struct { 90 Object NV0000_CTRL_OS_UNIX_EXPORT_OBJECT 91 FD int32 92 Flags uint32 93 } 94 95 // GetFrontendFD implements HasFrontendFD.GetFrontendFD. 96 func (p *NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS) GetFrontendFD() int32 { 97 return p.FD 98 } 99 100 // SetFrontendFD implements HasFrontendFD.SetFrontendFD. 101 func (p *NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS) SetFrontendFD(fd int32) { 102 p.FD = fd 103 } 104 105 // +marshal 106 type NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS struct { 107 SizeOfStrings uint32 108 Pad [4]byte 109 PDriverVersionBuffer P64 110 PVersionBuffer P64 111 PTitleBuffer P64 112 ChangelistNumber uint32 113 OfficialChangelistNumber uint32 114 } 115 116 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h: 117 const ( 118 NV0080_CTRL_CMD_FB_GET_CAPS_V2 = 0x801307 119 ) 120 121 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h: 122 const ( 123 NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST = 0x80170d 124 ) 125 126 // +marshal 127 type NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS struct { 128 NumChannels uint32 129 Pad [4]byte 130 PChannelHandleList P64 131 PChannelList P64 132 } 133 134 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h: 135 const ( 136 NV0080_CTRL_CMD_GPU_GET_CLASSLIST = 0x800201 137 NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES = 0x800280 138 NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE = 0x800288 139 NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE = 0x800289 140 NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 = 0x800292 141 ) 142 143 // +marshal 144 type NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS struct { 145 NumClasses uint32 146 Pad [4]byte 147 ClassList P64 148 } 149 150 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h: 151 152 // +marshal 153 type NV0080_CTRL_GR_ROUTE_INFO struct { 154 Flags uint32 155 Pad [4]byte 156 Route uint64 157 } 158 159 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h: 160 const ( 161 NV0080_CTRL_CMD_HOST_GET_CAPS_V2 = 0x801402 162 ) 163 164 // From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h: 165 const ( 166 NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL = 0x801909 167 ) 168 169 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h: 170 const ( 171 NV2080_CTRL_CMD_BUS_GET_PCI_INFO = 0x20801801 172 NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO = 0x20801803 173 NV2080_CTRL_CMD_BUS_GET_INFO_V2 = 0x20801823 174 NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS = 0x2080182a 175 NV2080_CTRL_CMD_BUS_GET_C2C_INFO = 0x2080182b 176 ) 177 178 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h: 179 const ( 180 NV2080_CTRL_CMD_CE_GET_ALL_CAPS = 0x20802a0a 181 ) 182 183 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h: 184 const ( 185 NV2080_CTRL_CMD_FB_GET_INFO_V2 = 0x20801303 186 ) 187 188 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h: 189 const ( 190 NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS = 0x2080110b 191 192 NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES = 64 193 ) 194 195 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h: 196 const ( 197 NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE = 0x20803125 198 ) 199 200 // +marshal 201 type NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS struct { 202 BDisable uint8 203 Pad1 [3]byte 204 NumChannels uint32 205 BOnlyDisableScheduling uint8 206 BRewindGpPut uint8 207 Pad2 [6]byte 208 PRunlistPreemptEvent P64 209 HClientList [NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]Handle 210 HChannelList [NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]Handle 211 } 212 213 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h: 214 const ( 215 NV2080_CTRL_CMD_GPU_GET_INFO_V2 = 0x20800102 216 NV2080_CTRL_CMD_GPU_GET_NAME_STRING = 0x20800110 217 NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING = 0x20800111 218 NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO = 0x20800119 219 NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS = 0x2080012f 220 NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES = 0x20800131 221 NV2080_CTRL_CMD_GPU_ACQUIRE_COMPUTE_MODE_RESERVATION = 0x20800145 // undocumented; paramSize == 0 222 NV2080_CTRL_CMD_GPU_RELEASE_COMPUTE_MODE_RESERVATION = 0x20800146 // undocumented; paramSize == 0 223 NV2080_CTRL_CMD_GPU_GET_GID_INFO = 0x2080014a 224 NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 = 0x20800170 225 NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS = 0x2080018b 226 NV2080_CTRL_CMD_GPU_GET_PIDS = 0x2080018d 227 NV2080_CTRL_CMD_GPU_GET_PID_INFO = 0x2080018e 228 NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG = 0x20800195 229 NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO = 0x208001a3 230 ) 231 232 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h: 233 const ( 234 NV2080_CTRL_CMD_GR_GET_INFO = 0x20801201 235 NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE = 0x20801210 236 NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE = 0x20801218 237 NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER = 0x2080121b 238 NV2080_CTRL_CMD_GR_GET_CAPS_V2 = 0x20801227 239 NV2080_CTRL_CMD_GR_GET_GPC_MASK = 0x2080122a 240 NV2080_CTRL_CMD_GR_GET_TPC_MASK = 0x2080122b 241 NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER = 0x20801230 242 ) 243 244 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h: 245 const ( 246 NV2080_CTRL_CMD_GSP_GET_FEATURES = 0x20803601 247 ) 248 249 // +marshal 250 type NV2080_CTRL_GR_GET_INFO_PARAMS struct { 251 GRInfoListSize uint32 // in elements 252 Pad [4]byte 253 GRInfoList P64 254 GRRouteInfo NV0080_CTRL_GR_ROUTE_INFO 255 } 256 257 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h: 258 const ( 259 NV2080_CTRL_CMD_MC_GET_ARCH_INFO = 0x20801701 260 NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS = 0x20801702 261 ) 262 263 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h: 264 const ( 265 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS = 0x20803001 266 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS = 0x20803002 267 ) 268 269 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h: 270 const ( 271 NV2080_CTRL_CMD_PERF_BOOST = 0x2080200a 272 ) 273 274 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h: 275 const ( 276 NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO = 0x20802209 277 NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS = 0x2080220c 278 NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG = 0x20802210 279 ) 280 281 // From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h: 282 const ( 283 NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO = 0x20800406 284 ) 285 286 // From src/common/sdk/nvidia/inc/ctrl/ctrl503c.h: 287 const ( 288 NV503C_CTRL_CMD_REGISTER_VA_SPACE = 0x503c0102 289 NV503C_CTRL_CMD_REGISTER_VIDMEM = 0x503c0104 290 NV503C_CTRL_CMD_UNREGISTER_VIDMEM = 0x503c0105 291 ) 292 293 // +marshal 294 type NV503C_CTRL_REGISTER_VA_SPACE_PARAMS struct { 295 HVASpace Handle 296 Pad [4]byte 297 VASpaceToken uint64 298 } 299 300 // From src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h: 301 const ( 302 NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK = 0x83de0309 303 NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES = 0x83de030c 304 NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES = 0x83de0310 305 ) 306 307 // From src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h: 308 const ( 309 NVC36F_CTRL_GET_CLASS_ENGINEID = 0xc36f0101 310 NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN = 0xc36f0108 311 ) 312 313 // From src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h: 314 const ( 315 NVC56F_CTRL_CMD_GET_KMB = 0xc56f010b 316 ) 317 318 // From src/common/sdk/nvidia/inc/ctrl/ctrl906f.h: 319 const ( 320 NV906F_CTRL_CMD_RESET_CHANNEL = 0x906f0102 321 ) 322 323 // From src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h: 324 const ( 325 NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK = 0x90e60102 326 ) 327 328 // From src/common/sdk/nvidia/inc/ctrl/ctrla06c.h: 329 const ( 330 NVA06C_CTRL_CMD_GPFIFO_SCHEDULE = 0xa06c0101 331 NVA06C_CTRL_CMD_SET_TIMESLICE = 0xa06c0103 332 NVA06C_CTRL_CMD_PREEMPT = 0xa06c0105 333 ) 334 335 // From src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h: 336 const ( 337 NVA06F_CTRL_CMD_GPFIFO_SCHEDULE = 0xa06f0103 338 ) 339 340 // From src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h: 341 const ( 342 NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = 0xcb330101 343 NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE = 0xcb330104 344 NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS = 0xcb33010b 345 )