gvisor.dev/gvisor@v0.0.0-20240520182842-f9d4d51c7e0f/pkg/abi/nvgpu/uvm.go (about) 1 // Copyright 2023 The gVisor Authors. 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 package nvgpu 16 17 // UVM ioctl commands. 18 const ( 19 // From kernel-open/nvidia-uvm/uvm_linux_ioctl.h: 20 UVM_INITIALIZE = 0x30000001 21 UVM_DEINITIALIZE = 0x30000002 22 23 // From kernel-open/nvidia-uvm/uvm_ioctl.h: 24 UVM_CREATE_RANGE_GROUP = 23 25 UVM_DESTROY_RANGE_GROUP = 24 26 UVM_REGISTER_GPU_VASPACE = 25 27 UVM_UNREGISTER_GPU_VASPACE = 26 28 UVM_REGISTER_CHANNEL = 27 29 UVM_UNREGISTER_CHANNEL = 28 30 UVM_MAP_EXTERNAL_ALLOCATION = 33 31 UVM_FREE = 34 32 UVM_REGISTER_GPU = 37 33 UVM_UNREGISTER_GPU = 38 34 UVM_PAGEABLE_MEM_ACCESS = 39 35 UVM_SET_PREFERRED_LOCATION = 42 36 UVM_DISABLE_READ_DUPLICATION = 45 37 UVM_TOOLS_READ_PROCESS_MEMORY = 62 38 UVM_TOOLS_WRITE_PROCESS_MEMORY = 63 39 UVM_MAP_DYNAMIC_PARALLELISM_REGION = 65 40 UVM_ALLOC_SEMAPHORE_POOL = 68 41 UVM_VALIDATE_VA_RANGE = 72 42 UVM_CREATE_EXTERNAL_RANGE = 73 43 UVM_MM_INITIALIZE = 75 44 ) 45 46 // +marshal 47 type UVM_INITIALIZE_PARAMS struct { 48 Flags uint64 49 RMStatus uint32 50 Pad0 [4]byte 51 } 52 53 // UVM_INITIALIZE_PARAMS flags, from kernel-open/nvidia-uvm/uvm_types.h. 54 const ( 55 UVM_INIT_FLAGS_MULTI_PROCESS_SHARING_MODE = 0x2 56 ) 57 58 // +marshal 59 type UVM_CREATE_RANGE_GROUP_PARAMS struct { 60 RangeGroupID uint64 61 RMStatus uint32 62 Pad0 [4]byte 63 } 64 65 // +marshal 66 type UVM_DESTROY_RANGE_GROUP_PARAMS struct { 67 RangeGroupID uint64 68 RMStatus uint32 69 Pad0 [4]byte 70 } 71 72 // +marshal 73 type UVM_REGISTER_GPU_VASPACE_PARAMS struct { 74 GPUUUID NvUUID 75 RMCtrlFD int32 76 HClient Handle 77 HVASpace Handle 78 RMStatus uint32 79 } 80 81 // GetFrontendFD implements HasFrontendFD.GetFrontendFD. 82 func (p *UVM_REGISTER_GPU_VASPACE_PARAMS) GetFrontendFD() int32 { 83 return p.RMCtrlFD 84 } 85 86 // SetFrontendFD implements HasFrontendFD.SetFrontendFD. 87 func (p *UVM_REGISTER_GPU_VASPACE_PARAMS) SetFrontendFD(fd int32) { 88 p.RMCtrlFD = fd 89 } 90 91 // +marshal 92 type UVM_UNREGISTER_GPU_VASPACE_PARAMS struct { 93 GPUUUID NvUUID 94 RMStatus uint32 95 } 96 97 // +marshal 98 type UVM_REGISTER_CHANNEL_PARAMS struct { 99 GPUUUID NvUUID 100 RMCtrlFD int32 101 HClient Handle 102 HChannel Handle 103 Pad [4]byte 104 Base uint64 105 Length uint64 106 RMStatus uint32 107 Pad0 [4]byte 108 } 109 110 // GetFrontendFD implements HasFrontendFD.GetFrontendFD. 111 func (p *UVM_REGISTER_CHANNEL_PARAMS) GetFrontendFD() int32 { 112 return p.RMCtrlFD 113 } 114 115 // SetFrontendFD implements HasFrontendFD.SetFrontendFD. 116 func (p *UVM_REGISTER_CHANNEL_PARAMS) SetFrontendFD(fd int32) { 117 p.RMCtrlFD = fd 118 } 119 120 // +marshal 121 type UVM_UNREGISTER_CHANNEL_PARAMS struct { 122 GPUUUID NvUUID 123 HClient Handle 124 HChannel Handle 125 RMStatus uint32 126 } 127 128 // +marshal 129 type UVM_MAP_EXTERNAL_ALLOCATION_PARAMS struct { 130 Base uint64 131 Length uint64 132 Offset uint64 133 PerGPUAttributes [UVM_MAX_GPUS]UvmGpuMappingAttributes 134 GPUAttributesCount uint64 135 RMCtrlFD int32 136 HClient Handle 137 HMemory Handle 138 RMStatus uint32 139 } 140 141 // GetFrontendFD implements HasFrontendFD.GetFrontendFD. 142 func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS) GetFrontendFD() int32 { 143 return p.RMCtrlFD 144 } 145 146 // SetFrontendFD implements HasFrontendFD.SetFrontendFD. 147 func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS) SetFrontendFD(fd int32) { 148 p.RMCtrlFD = fd 149 } 150 151 // +marshal 152 type UVM_MAP_EXTERNAL_ALLOCATION_PARAMS_V550 struct { 153 Base uint64 154 Length uint64 155 Offset uint64 156 PerGPUAttributes [UVM_MAX_GPUS_V2]UvmGpuMappingAttributes 157 GPUAttributesCount uint64 158 RMCtrlFD int32 159 HClient Handle 160 HMemory Handle 161 RMStatus uint32 162 } 163 164 // GetFrontendFD implements HasFrontendFD.GetFrontendFD. 165 func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS_V550) GetFrontendFD() int32 { 166 return p.RMCtrlFD 167 } 168 169 // SetFrontendFD implements HasFrontendFD.SetFrontendFD. 170 func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS_V550) SetFrontendFD(fd int32) { 171 p.RMCtrlFD = fd 172 } 173 174 // +marshal 175 type UVM_FREE_PARAMS struct { 176 Base uint64 177 Length uint64 178 RMStatus uint32 179 Pad0 [4]byte 180 } 181 182 // +marshal 183 type UVM_REGISTER_GPU_PARAMS struct { 184 GPUUUID NvUUID 185 NumaEnabled uint8 186 Pad [3]byte 187 NumaNodeID int32 188 RMCtrlFD int32 189 HClient Handle 190 HSMCPartRef Handle 191 RMStatus uint32 192 } 193 194 // GetFrontendFD implements HasFrontendFD.GetFrontendFD. 195 func (p *UVM_REGISTER_GPU_PARAMS) GetFrontendFD() int32 { 196 return p.RMCtrlFD 197 } 198 199 // SetFrontendFD implements HasFrontendFD.SetFrontendFD. 200 func (p *UVM_REGISTER_GPU_PARAMS) SetFrontendFD(fd int32) { 201 p.RMCtrlFD = fd 202 } 203 204 // +marshal 205 type UVM_UNREGISTER_GPU_PARAMS struct { 206 GPUUUID NvUUID 207 RMStatus uint32 208 } 209 210 // +marshal 211 type UVM_PAGEABLE_MEM_ACCESS_PARAMS struct { 212 PageableMemAccess uint8 213 Pad [3]byte 214 RMStatus uint32 215 } 216 217 // +marshal 218 type UVM_SET_PREFERRED_LOCATION_PARAMS struct { 219 RequestedBase uint64 220 Length uint64 221 PreferredLocation NvUUID 222 RMStatus uint32 223 Pad0 [4]byte 224 } 225 226 // +marshal 227 type UVM_SET_PREFERRED_LOCATION_PARAMS_V550 struct { 228 RequestedBase uint64 229 Length uint64 230 PreferredLocation NvUUID 231 PreferredCPUNumaNode int32 232 RMStatus uint32 233 } 234 235 // +marshal 236 type UVM_DISABLE_READ_DUPLICATION_PARAMS struct { 237 RequestedBase uint64 238 Length uint64 239 RMStatus uint32 240 Pad0 [4]byte 241 } 242 243 // +marshal 244 type UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS struct { 245 Buffer uint64 246 Size uint64 247 TargetVA uint64 248 BytesRead uint64 249 RMStatus uint32 250 Pad0 [4]byte 251 } 252 253 // +marshal 254 type UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS struct { 255 Buffer uint64 256 Size uint64 257 TargetVA uint64 258 BytesWritten uint64 259 RMStatus uint32 260 Pad0 [4]byte 261 } 262 263 // +marshal 264 type UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS struct { 265 Base uint64 266 Length uint64 267 GPUUUID NvUUID 268 RMStatus uint32 269 Pad0 [4]byte 270 } 271 272 // +marshal 273 type UVM_ALLOC_SEMAPHORE_POOL_PARAMS struct { 274 Base uint64 275 Length uint64 276 PerGPUAttributes [UVM_MAX_GPUS]UvmGpuMappingAttributes 277 GPUAttributesCount uint64 278 RMStatus uint32 279 Pad0 [4]byte 280 } 281 282 // +marshal 283 type UVM_ALLOC_SEMAPHORE_POOL_PARAMS_V550 struct { 284 Base uint64 285 Length uint64 286 PerGPUAttributes [UVM_MAX_GPUS_V2]UvmGpuMappingAttributes 287 GPUAttributesCount uint64 288 RMStatus uint32 289 Pad0 [4]byte 290 } 291 292 // +marshal 293 type UVM_VALIDATE_VA_RANGE_PARAMS struct { 294 Base uint64 295 Length uint64 296 RMStatus uint32 297 Pad0 [4]byte 298 } 299 300 // +marshal 301 type UVM_CREATE_EXTERNAL_RANGE_PARAMS struct { 302 Base uint64 303 Length uint64 304 RMStatus uint32 305 Pad0 [4]byte 306 } 307 308 // +marshal 309 type UVM_MM_INITIALIZE_PARAMS struct { 310 UvmFD int32 311 Status uint32 312 } 313 314 // From kernel-open/nvidia-uvm/uvm_types.h: 315 316 const ( 317 UVM_MAX_GPUS = NV_MAX_DEVICES 318 UVM_MAX_GPUS_V2 = NV_MAX_DEVICES * NV_MAX_SUBDEVICES 319 ) 320 321 // +marshal 322 type UvmGpuMappingAttributes struct { 323 GPUUUID NvUUID 324 GPUMappingType uint32 325 GPUCachingType uint32 326 GPUFormatType uint32 327 GPUElementBits uint32 328 GPUCompressionType uint32 329 }