rsc.io/go@v0.0.0-20150416155037-e040fd465409/src/cmd/old9a/lex.go (about)

     1  // cmd/9a/lex.c from Vita Nuova.
     2  //
     3  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     4  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     5  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     6  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     7  //	Portions Copyright © 2004,2006 Bruce Ellis
     8  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     9  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
    10  //	Portions Copyright © 2009 The Go Authors.  All rights reserved.
    11  //
    12  // Permission is hereby granted, free of charge, to any person obtaining a copy
    13  // of this software and associated documentation files (the "Software"), to deal
    14  // in the Software without restriction, including without limitation the rights
    15  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    16  // copies of the Software, and to permit persons to whom the Software is
    17  // furnished to do so, subject to the following conditions:
    18  //
    19  // The above copyright notice and this permission notice shall be included in
    20  // all copies or substantial portions of the Software.
    21  //
    22  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    23  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    24  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    25  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    26  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    27  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    28  // THE SOFTWARE.
    29  
    30  //go:generate go tool yacc a.y
    31  
    32  package main
    33  
    34  import (
    35  	"cmd/internal/asm"
    36  	"cmd/internal/obj"
    37  	"cmd/internal/obj/ppc64"
    38  )
    39  
    40  var (
    41  	yyerror  = asm.Yyerror
    42  	nullgen  obj.Addr
    43  	stmtline int32
    44  )
    45  
    46  func main() {
    47  	cinit()
    48  
    49  	asm.LSCONST = LSCONST
    50  	asm.LCONST = LCONST
    51  	asm.LFCONST = LFCONST
    52  	asm.LNAME = LNAME
    53  	asm.LVAR = LVAR
    54  	asm.LLAB = LLAB
    55  
    56  	asm.Lexinit = lexinit
    57  	asm.Cclean = cclean
    58  	asm.Yyparse = yyparse
    59  
    60  	asm.Thechar = '9'
    61  	asm.Thestring = "ppc64"
    62  	asm.Thelinkarch = &ppc64.Linkppc64
    63  	asm.Arches = map[string]*obj.LinkArch{
    64  		"ppc64le": &ppc64.Linkppc64le,
    65  	}
    66  
    67  	asm.Main()
    68  }
    69  
    70  type yy struct{}
    71  
    72  func (yy) Lex(v *yySymType) int {
    73  	var av asm.Yylval
    74  	tok := asm.Yylex(&av)
    75  	v.sym = av.Sym
    76  	v.lval = av.Lval
    77  	v.sval = av.Sval
    78  	v.dval = av.Dval
    79  	return tok
    80  }
    81  
    82  func (yy) Error(msg string) {
    83  	asm.Yyerror("%s", msg)
    84  }
    85  
    86  func yyparse() {
    87  	nosched = 0
    88  	yyParse(yy{})
    89  }
    90  
    91  var lexinit = []asm.Lextab{
    92  	{"SP", LSP, obj.NAME_AUTO},
    93  	{"SB", LSB, obj.NAME_EXTERN},
    94  	{"FP", LFP, obj.NAME_PARAM},
    95  	{"PC", LPC, obj.TYPE_BRANCH},
    96  	{"LR", LLR, ppc64.REG_LR},
    97  	{"CTR", LCTR, ppc64.REG_CTR},
    98  	{"XER", LSPREG, ppc64.REG_XER},
    99  	{"MSR", LMSR, ppc64.REG_MSR},
   100  	{"FPSCR", LFPSCR, ppc64.REG_FPSCR},
   101  	{"SPR", LSPR, ppc64.REG_SPR0},
   102  	{"DCR", LSPR, ppc64.REG_DCR0},
   103  	{"CR", LCR, ppc64.REG_CR},
   104  	{"CR0", LCREG, ppc64.REG_CR0},
   105  	{"CR1", LCREG, ppc64.REG_CR1},
   106  	{"CR2", LCREG, ppc64.REG_CR2},
   107  	{"CR3", LCREG, ppc64.REG_CR3},
   108  	{"CR4", LCREG, ppc64.REG_CR4},
   109  	{"CR5", LCREG, ppc64.REG_CR5},
   110  	{"CR6", LCREG, ppc64.REG_CR6},
   111  	{"CR7", LCREG, ppc64.REG_CR7},
   112  	{"R", LR, 0},
   113  	{"R0", LREG, ppc64.REG_R0},
   114  	{"R1", LREG, ppc64.REG_R1},
   115  	{"R2", LREG, ppc64.REG_R2},
   116  	{"R3", LREG, ppc64.REG_R3},
   117  	{"R4", LREG, ppc64.REG_R4},
   118  	{"R5", LREG, ppc64.REG_R5},
   119  	{"R6", LREG, ppc64.REG_R6},
   120  	{"R7", LREG, ppc64.REG_R7},
   121  	{"R8", LREG, ppc64.REG_R8},
   122  	{"R9", LREG, ppc64.REG_R9},
   123  	{"R10", LREG, ppc64.REG_R10},
   124  	{"R11", LREG, ppc64.REG_R11},
   125  	{"R12", LREG, ppc64.REG_R12},
   126  	{"R13", LREG, ppc64.REG_R13},
   127  	{"R14", LREG, ppc64.REG_R14},
   128  	{"R15", LREG, ppc64.REG_R15},
   129  	{"R16", LREG, ppc64.REG_R16},
   130  	{"R17", LREG, ppc64.REG_R17},
   131  	{"R18", LREG, ppc64.REG_R18},
   132  	{"R19", LREG, ppc64.REG_R19},
   133  	{"R20", LREG, ppc64.REG_R20},
   134  	{"R21", LREG, ppc64.REG_R21},
   135  	{"R22", LREG, ppc64.REG_R22},
   136  	{"R23", LREG, ppc64.REG_R23},
   137  	{"R24", LREG, ppc64.REG_R24},
   138  	{"R25", LREG, ppc64.REG_R25},
   139  	{"R26", LREG, ppc64.REG_R26},
   140  	{"R27", LREG, ppc64.REG_R27},
   141  	{"R28", LREG, ppc64.REG_R28},
   142  	{"R29", LREG, ppc64.REG_R29},
   143  	{"g", LREG, ppc64.REG_R30}, // avoid unintentionally clobbering g using R30
   144  	{"R31", LREG, ppc64.REG_R31},
   145  	{"F", LF, 0},
   146  	{"F0", LFREG, ppc64.REG_F0},
   147  	{"F1", LFREG, ppc64.REG_F1},
   148  	{"F2", LFREG, ppc64.REG_F2},
   149  	{"F3", LFREG, ppc64.REG_F3},
   150  	{"F4", LFREG, ppc64.REG_F4},
   151  	{"F5", LFREG, ppc64.REG_F5},
   152  	{"F6", LFREG, ppc64.REG_F6},
   153  	{"F7", LFREG, ppc64.REG_F7},
   154  	{"F8", LFREG, ppc64.REG_F8},
   155  	{"F9", LFREG, ppc64.REG_F9},
   156  	{"F10", LFREG, ppc64.REG_F10},
   157  	{"F11", LFREG, ppc64.REG_F11},
   158  	{"F12", LFREG, ppc64.REG_F12},
   159  	{"F13", LFREG, ppc64.REG_F13},
   160  	{"F14", LFREG, ppc64.REG_F14},
   161  	{"F15", LFREG, ppc64.REG_F15},
   162  	{"F16", LFREG, ppc64.REG_F16},
   163  	{"F17", LFREG, ppc64.REG_F17},
   164  	{"F18", LFREG, ppc64.REG_F18},
   165  	{"F19", LFREG, ppc64.REG_F19},
   166  	{"F20", LFREG, ppc64.REG_F20},
   167  	{"F21", LFREG, ppc64.REG_F21},
   168  	{"F22", LFREG, ppc64.REG_F22},
   169  	{"F23", LFREG, ppc64.REG_F23},
   170  	{"F24", LFREG, ppc64.REG_F24},
   171  	{"F25", LFREG, ppc64.REG_F25},
   172  	{"F26", LFREG, ppc64.REG_F26},
   173  	{"F27", LFREG, ppc64.REG_F27},
   174  	{"F28", LFREG, ppc64.REG_F28},
   175  	{"F29", LFREG, ppc64.REG_F29},
   176  	{"F30", LFREG, ppc64.REG_F30},
   177  	{"F31", LFREG, ppc64.REG_F31},
   178  	{"CREQV", LCROP, ppc64.ACREQV},
   179  	{"CRXOR", LCROP, ppc64.ACRXOR},
   180  	{"CRAND", LCROP, ppc64.ACRAND},
   181  	{"CROR", LCROP, ppc64.ACROR},
   182  	{"CRANDN", LCROP, ppc64.ACRANDN},
   183  	{"CRORN", LCROP, ppc64.ACRORN},
   184  	{"CRNAND", LCROP, ppc64.ACRNAND},
   185  	{"CRNOR", LCROP, ppc64.ACRNOR},
   186  	{"ADD", LADDW, ppc64.AADD},
   187  	{"ADDV", LADDW, ppc64.AADDV},
   188  	{"ADDCC", LADDW, ppc64.AADDCC},
   189  	{"ADDVCC", LADDW, ppc64.AADDVCC},
   190  	{"ADDC", LADDW, ppc64.AADDC},
   191  	{"ADDCV", LADDW, ppc64.AADDCV},
   192  	{"ADDCCC", LADDW, ppc64.AADDCCC},
   193  	{"ADDCVCC", LADDW, ppc64.AADDCVCC},
   194  	{"ADDE", LLOGW, ppc64.AADDE},
   195  	{"ADDEV", LLOGW, ppc64.AADDEV},
   196  	{"ADDECC", LLOGW, ppc64.AADDECC},
   197  	{"ADDEVCC", LLOGW, ppc64.AADDEVCC},
   198  	{"ADDME", LABS, ppc64.AADDME},
   199  	{"ADDMEV", LABS, ppc64.AADDMEV},
   200  	{"ADDMECC", LABS, ppc64.AADDMECC},
   201  	{"ADDMEVCC", LABS, ppc64.AADDMEVCC},
   202  	{"ADDZE", LABS, ppc64.AADDZE},
   203  	{"ADDZEV", LABS, ppc64.AADDZEV},
   204  	{"ADDZECC", LABS, ppc64.AADDZECC},
   205  	{"ADDZEVCC", LABS, ppc64.AADDZEVCC},
   206  	{"SUB", LADDW, ppc64.ASUB},
   207  	{"SUBV", LADDW, ppc64.ASUBV},
   208  	{"SUBCC", LADDW, ppc64.ASUBCC},
   209  	{"SUBVCC", LADDW, ppc64.ASUBVCC},
   210  	{"SUBE", LLOGW, ppc64.ASUBE},
   211  	{"SUBECC", LLOGW, ppc64.ASUBECC},
   212  	{"SUBEV", LLOGW, ppc64.ASUBEV},
   213  	{"SUBEVCC", LLOGW, ppc64.ASUBEVCC},
   214  	{"SUBC", LADDW, ppc64.ASUBC},
   215  	{"SUBCCC", LADDW, ppc64.ASUBCCC},
   216  	{"SUBCV", LADDW, ppc64.ASUBCV},
   217  	{"SUBCVCC", LADDW, ppc64.ASUBCVCC},
   218  	{"SUBME", LABS, ppc64.ASUBME},
   219  	{"SUBMEV", LABS, ppc64.ASUBMEV},
   220  	{"SUBMECC", LABS, ppc64.ASUBMECC},
   221  	{"SUBMEVCC", LABS, ppc64.ASUBMEVCC},
   222  	{"SUBZE", LABS, ppc64.ASUBZE},
   223  	{"SUBZEV", LABS, ppc64.ASUBZEV},
   224  	{"SUBZECC", LABS, ppc64.ASUBZECC},
   225  	{"SUBZEVCC", LABS, ppc64.ASUBZEVCC},
   226  	{"AND", LADDW, ppc64.AAND},
   227  	{"ANDCC", LADDW, ppc64.AANDCC}, /* includes andil & andiu */
   228  	{"ANDN", LLOGW, ppc64.AANDN},
   229  	{"ANDNCC", LLOGW, ppc64.AANDNCC},
   230  	{"EQV", LLOGW, ppc64.AEQV},
   231  	{"EQVCC", LLOGW, ppc64.AEQVCC},
   232  	{"NAND", LLOGW, ppc64.ANAND},
   233  	{"NANDCC", LLOGW, ppc64.ANANDCC},
   234  	{"NOR", LLOGW, ppc64.ANOR},
   235  	{"NORCC", LLOGW, ppc64.ANORCC},
   236  	{"OR", LADDW, ppc64.AOR}, /* includes oril & oriu */
   237  	{"ORCC", LADDW, ppc64.AORCC},
   238  	{"ORN", LLOGW, ppc64.AORN},
   239  	{"ORNCC", LLOGW, ppc64.AORNCC},
   240  	{"XOR", LADDW, ppc64.AXOR}, /* includes xoril & xoriu */
   241  	{"XORCC", LLOGW, ppc64.AXORCC},
   242  	{"EXTSB", LABS, ppc64.AEXTSB},
   243  	{"EXTSBCC", LABS, ppc64.AEXTSBCC},
   244  	{"EXTSH", LABS, ppc64.AEXTSH},
   245  	{"EXTSHCC", LABS, ppc64.AEXTSHCC},
   246  	{"CNTLZW", LABS, ppc64.ACNTLZW},
   247  	{"CNTLZWCC", LABS, ppc64.ACNTLZWCC},
   248  	{"RLWMI", LRLWM, ppc64.ARLWMI},
   249  	{"RLWMICC", LRLWM, ppc64.ARLWMICC},
   250  	{"RLWNM", LRLWM, ppc64.ARLWNM},
   251  	{"RLWNMCC", LRLWM, ppc64.ARLWNMCC},
   252  	{"SLW", LSHW, ppc64.ASLW},
   253  	{"SLWCC", LSHW, ppc64.ASLWCC},
   254  	{"SRW", LSHW, ppc64.ASRW},
   255  	{"SRWCC", LSHW, ppc64.ASRWCC},
   256  	{"SRAW", LSHW, ppc64.ASRAW},
   257  	{"SRAWCC", LSHW, ppc64.ASRAWCC},
   258  	{"BR", LBRA, ppc64.ABR},
   259  	{"BC", LBRA, ppc64.ABC},
   260  	{"BCL", LBRA, ppc64.ABC},
   261  	{"BL", LBRA, ppc64.ABL},
   262  	{"BEQ", LBRA, ppc64.ABEQ},
   263  	{"BNE", LBRA, ppc64.ABNE},
   264  	{"BGT", LBRA, ppc64.ABGT},
   265  	{"BGE", LBRA, ppc64.ABGE},
   266  	{"BLT", LBRA, ppc64.ABLT},
   267  	{"BLE", LBRA, ppc64.ABLE},
   268  	{"BVC", LBRA, ppc64.ABVC},
   269  	{"BVS", LBRA, ppc64.ABVS},
   270  	{"CMP", LCMP, ppc64.ACMP},
   271  	{"CMPU", LCMP, ppc64.ACMPU},
   272  	{"CMPW", LCMP, ppc64.ACMPW},
   273  	{"CMPWU", LCMP, ppc64.ACMPWU},
   274  	{"DIVW", LLOGW, ppc64.ADIVW},
   275  	{"DIVWV", LLOGW, ppc64.ADIVWV},
   276  	{"DIVWCC", LLOGW, ppc64.ADIVWCC},
   277  	{"DIVWVCC", LLOGW, ppc64.ADIVWVCC},
   278  	{"DIVWU", LLOGW, ppc64.ADIVWU},
   279  	{"DIVWUV", LLOGW, ppc64.ADIVWUV},
   280  	{"DIVWUCC", LLOGW, ppc64.ADIVWUCC},
   281  	{"DIVWUVCC", LLOGW, ppc64.ADIVWUVCC},
   282  	{"FABS", LFCONV, ppc64.AFABS},
   283  	{"FABSCC", LFCONV, ppc64.AFABSCC},
   284  	{"FNEG", LFCONV, ppc64.AFNEG},
   285  	{"FNEGCC", LFCONV, ppc64.AFNEGCC},
   286  	{"FNABS", LFCONV, ppc64.AFNABS},
   287  	{"FNABSCC", LFCONV, ppc64.AFNABSCC},
   288  	{"FADD", LFADD, ppc64.AFADD},
   289  	{"FADDCC", LFADD, ppc64.AFADDCC},
   290  	{"FSUB", LFADD, ppc64.AFSUB},
   291  	{"FSUBCC", LFADD, ppc64.AFSUBCC},
   292  	{"FMUL", LFADD, ppc64.AFMUL},
   293  	{"FMULCC", LFADD, ppc64.AFMULCC},
   294  	{"FDIV", LFADD, ppc64.AFDIV},
   295  	{"FDIVCC", LFADD, ppc64.AFDIVCC},
   296  	{"FRSP", LFCONV, ppc64.AFRSP},
   297  	{"FRSPCC", LFCONV, ppc64.AFRSPCC},
   298  	{"FCTIW", LFCONV, ppc64.AFCTIW},
   299  	{"FCTIWCC", LFCONV, ppc64.AFCTIWCC},
   300  	{"FCTIWZ", LFCONV, ppc64.AFCTIWZ},
   301  	{"FCTIWZCC", LFCONV, ppc64.AFCTIWZCC},
   302  	{"FMADD", LFMA, ppc64.AFMADD},
   303  	{"FMADDCC", LFMA, ppc64.AFMADDCC},
   304  	{"FMSUB", LFMA, ppc64.AFMSUB},
   305  	{"FMSUBCC", LFMA, ppc64.AFMSUBCC},
   306  	{"FNMADD", LFMA, ppc64.AFNMADD},
   307  	{"FNMADDCC", LFMA, ppc64.AFNMADDCC},
   308  	{"FNMSUB", LFMA, ppc64.AFNMSUB},
   309  	{"FNMSUBCC", LFMA, ppc64.AFNMSUBCC},
   310  	{"FMADDS", LFMA, ppc64.AFMADDS},
   311  	{"FMADDSCC", LFMA, ppc64.AFMADDSCC},
   312  	{"FMSUBS", LFMA, ppc64.AFMSUBS},
   313  	{"FMSUBSCC", LFMA, ppc64.AFMSUBSCC},
   314  	{"FNMADDS", LFMA, ppc64.AFNMADDS},
   315  	{"FNMADDSCC", LFMA, ppc64.AFNMADDSCC},
   316  	{"FNMSUBS", LFMA, ppc64.AFNMSUBS},
   317  	{"FNMSUBSCC", LFMA, ppc64.AFNMSUBSCC},
   318  	{"FCMPU", LFCMP, ppc64.AFCMPU},
   319  	{"FCMPO", LFCMP, ppc64.AFCMPO},
   320  	{"MTFSB0", LMTFSB, ppc64.AMTFSB0},
   321  	{"MTFSB1", LMTFSB, ppc64.AMTFSB1},
   322  	{"FMOVD", LFMOV, ppc64.AFMOVD},
   323  	{"FMOVS", LFMOV, ppc64.AFMOVS},
   324  	{"FMOVDCC", LFCONV, ppc64.AFMOVDCC}, /* fmr. */
   325  	{"GLOBL", LGLOBL, obj.AGLOBL},
   326  	{"MOVB", LMOVB, ppc64.AMOVB},
   327  	{"MOVBZ", LMOVB, ppc64.AMOVBZ},
   328  	{"MOVBU", LMOVB, ppc64.AMOVBU},
   329  	{"MOVBZU", LMOVB, ppc64.AMOVBZU},
   330  	{"MOVH", LMOVB, ppc64.AMOVH},
   331  	{"MOVHZ", LMOVB, ppc64.AMOVHZ},
   332  	{"MOVHU", LMOVB, ppc64.AMOVHU},
   333  	{"MOVHZU", LMOVB, ppc64.AMOVHZU},
   334  	{"MOVHBR", LXMV, ppc64.AMOVHBR},
   335  	{"MOVWBR", LXMV, ppc64.AMOVWBR},
   336  	{"MOVW", LMOVW, ppc64.AMOVW},
   337  	{"MOVWU", LMOVW, ppc64.AMOVWU},
   338  	{"MOVMW", LMOVMW, ppc64.AMOVMW},
   339  	{"MOVFL", LMOVW, ppc64.AMOVFL},
   340  	{"MULLW", LADDW, ppc64.AMULLW}, /* includes multiply immediate 10-139 */
   341  	{"MULLWV", LLOGW, ppc64.AMULLWV},
   342  	{"MULLWCC", LLOGW, ppc64.AMULLWCC},
   343  	{"MULLWVCC", LLOGW, ppc64.AMULLWVCC},
   344  	{"MULHW", LLOGW, ppc64.AMULHW},
   345  	{"MULHWCC", LLOGW, ppc64.AMULHWCC},
   346  	{"MULHWU", LLOGW, ppc64.AMULHWU},
   347  	{"MULHWUCC", LLOGW, ppc64.AMULHWUCC},
   348  	{"NEG", LABS, ppc64.ANEG},
   349  	{"NEGV", LABS, ppc64.ANEGV},
   350  	{"NEGCC", LABS, ppc64.ANEGCC},
   351  	{"NEGVCC", LABS, ppc64.ANEGVCC},
   352  	{"NOP", LNOP, obj.ANOP}, /* ori 0,0,0 */
   353  	{"SYSCALL", LNOP, ppc64.ASYSCALL},
   354  	{"UNDEF", LNOP, obj.AUNDEF},
   355  	{"RET", LRETRN, obj.ARET},
   356  	{"RETURN", LRETRN, obj.ARET},
   357  	{"RFI", LRETRN, ppc64.ARFI},
   358  	{"RFCI", LRETRN, ppc64.ARFCI},
   359  	{"DATA", LDATA, obj.ADATA},
   360  	{"END", LEND, obj.AEND},
   361  	{"TEXT", LTEXT, obj.ATEXT},
   362  
   363  	/* 64-bit instructions */
   364  	{"CNTLZD", LABS, ppc64.ACNTLZD},
   365  	{"CNTLZDCC", LABS, ppc64.ACNTLZDCC},
   366  	{"DIVD", LLOGW, ppc64.ADIVD},
   367  	{"DIVDCC", LLOGW, ppc64.ADIVDCC},
   368  	{"DIVDVCC", LLOGW, ppc64.ADIVDVCC},
   369  	{"DIVDV", LLOGW, ppc64.ADIVDV},
   370  	{"DIVDU", LLOGW, ppc64.ADIVDU},
   371  	{"DIVDUCC", LLOGW, ppc64.ADIVDUCC},
   372  	{"DIVDUVCC", LLOGW, ppc64.ADIVDUVCC},
   373  	{"DIVDUV", LLOGW, ppc64.ADIVDUV},
   374  	{"EXTSW", LABS, ppc64.AEXTSW},
   375  	{"EXTSWCC", LABS, ppc64.AEXTSWCC},
   376  	{"FCTID", LFCONV, ppc64.AFCTID},
   377  	{"FCTIDCC", LFCONV, ppc64.AFCTIDCC},
   378  	{"FCTIDZ", LFCONV, ppc64.AFCTIDZ},
   379  	{"FCTIDZCC", LFCONV, ppc64.AFCTIDZCC},
   380  	{"FCFID", LFCONV, ppc64.AFCFID},
   381  	{"FCFIDCC", LFCONV, ppc64.AFCFIDCC},
   382  	{"LDAR", LXLD, ppc64.ALDAR},
   383  	{"MOVD", LMOVW, ppc64.AMOVD},
   384  	{"MOVDU", LMOVW, ppc64.AMOVDU},
   385  	{"MOVWZ", LMOVW, ppc64.AMOVWZ},
   386  	{"MOVWZU", LMOVW, ppc64.AMOVWZU},
   387  	{"MULHD", LLOGW, ppc64.AMULHD},
   388  	{"MULHDCC", LLOGW, ppc64.AMULHDCC},
   389  	{"MULHDU", LLOGW, ppc64.AMULHDU},
   390  	{"MULHDUCC", LLOGW, ppc64.AMULHDUCC},
   391  	{"MULLD", LADDW, ppc64.AMULLD}, /* includes multiply immediate? */
   392  	{"MULLDCC", LLOGW, ppc64.AMULLDCC},
   393  	{"MULLDVCC", LLOGW, ppc64.AMULLDVCC},
   394  	{"MULLDV", LLOGW, ppc64.AMULLDV},
   395  	{"RFID", LRETRN, ppc64.ARFID},
   396  	{"HRFID", LRETRN, ppc64.AHRFID},
   397  	{"RLDMI", LRLWM, ppc64.ARLDMI},
   398  	{"RLDMICC", LRLWM, ppc64.ARLDMICC},
   399  	{"RLDC", LRLWM, ppc64.ARLDC},
   400  	{"RLDCCC", LRLWM, ppc64.ARLDCCC},
   401  	{"RLDCR", LRLWM, ppc64.ARLDCR},
   402  	{"RLDCRCC", LRLWM, ppc64.ARLDCRCC},
   403  	{"RLDCL", LRLWM, ppc64.ARLDCL},
   404  	{"RLDCLCC", LRLWM, ppc64.ARLDCLCC},
   405  	{"SLBIA", LNOP, ppc64.ASLBIA},
   406  	{"SLBIE", LNOP, ppc64.ASLBIE},
   407  	{"SLBMFEE", LABS, ppc64.ASLBMFEE},
   408  	{"SLBMFEV", LABS, ppc64.ASLBMFEV},
   409  	{"SLBMTE", LABS, ppc64.ASLBMTE},
   410  	{"SLD", LSHW, ppc64.ASLD},
   411  	{"SLDCC", LSHW, ppc64.ASLDCC},
   412  	{"SRD", LSHW, ppc64.ASRD},
   413  	{"SRAD", LSHW, ppc64.ASRAD},
   414  	{"SRADCC", LSHW, ppc64.ASRADCC},
   415  	{"SRDCC", LSHW, ppc64.ASRDCC},
   416  	{"STDCCC", LXST, ppc64.ASTDCCC},
   417  	{"TD", LADDW, ppc64.ATD},
   418  
   419  	/* pseudo instructions */
   420  	{"REM", LLOGW, ppc64.AREM},
   421  	{"REMCC", LLOGW, ppc64.AREMCC},
   422  	{"REMV", LLOGW, ppc64.AREMV},
   423  	{"REMVCC", LLOGW, ppc64.AREMVCC},
   424  	{"REMU", LLOGW, ppc64.AREMU},
   425  	{"REMUCC", LLOGW, ppc64.AREMUCC},
   426  	{"REMUV", LLOGW, ppc64.AREMUV},
   427  	{"REMUVCC", LLOGW, ppc64.AREMUVCC},
   428  	{"REMD", LLOGW, ppc64.AREMD},
   429  	{"REMDCC", LLOGW, ppc64.AREMDCC},
   430  	{"REMDV", LLOGW, ppc64.AREMDV},
   431  	{"REMDVCC", LLOGW, ppc64.AREMDVCC},
   432  	{"REMDU", LLOGW, ppc64.AREMDU},
   433  	{"REMDUCC", LLOGW, ppc64.AREMDUCC},
   434  	{"REMDUV", LLOGW, ppc64.AREMDUV},
   435  	{"REMDUVCC", LLOGW, ppc64.AREMDUVCC},
   436  
   437  	/* special instructions */
   438  	{"DCBF", LXOP, ppc64.ADCBF},
   439  	{"DCBI", LXOP, ppc64.ADCBI},
   440  	{"DCBST", LXOP, ppc64.ADCBST},
   441  	{"DCBT", LXOP, ppc64.ADCBT},
   442  	{"DCBTST", LXOP, ppc64.ADCBTST},
   443  	{"DCBZ", LXOP, ppc64.ADCBZ},
   444  	{"ICBI", LXOP, ppc64.AICBI},
   445  	{"ECIWX", LXLD, ppc64.AECIWX},
   446  	{"ECOWX", LXST, ppc64.AECOWX},
   447  	{"LWAR", LXLD, ppc64.ALWAR},
   448  	{"STWCCC", LXST, ppc64.ASTWCCC},
   449  	{"EIEIO", LRETRN, ppc64.AEIEIO},
   450  	{"TLBIE", LNOP, ppc64.ATLBIE},
   451  	{"TLBIEL", LNOP, ppc64.ATLBIEL},
   452  	{"LSW", LXLD, ppc64.ALSW},
   453  	{"STSW", LXST, ppc64.ASTSW},
   454  	{"ISYNC", LRETRN, ppc64.AISYNC},
   455  	{"SYNC", LRETRN, ppc64.ASYNC},
   456  	{"TLBSYNC", LRETRN, ppc64.ATLBSYNC},
   457  	{"PTESYNC", LRETRN, ppc64.APTESYNC},
   458  
   459  	/*	"TW",		LADDW,	ATW,*/
   460  	{"WORD", LWORD, ppc64.AWORD},
   461  	{"DWORD", LWORD, ppc64.ADWORD},
   462  	{"SCHED", LSCHED, 0},
   463  	{"NOSCHED", LSCHED, 0x80},
   464  	{"PCDATA", LPCDAT, obj.APCDATA},
   465  	{"FUNCDATA", LFUNCDAT, obj.AFUNCDATA},
   466  }
   467  
   468  func cinit() {
   469  }
   470  
   471  func cclean() {
   472  	outcode(obj.AEND, &nullgen, 0, &nullgen)
   473  }
   474  
   475  var lastpc *obj.Prog
   476  var nosched int
   477  
   478  func outcode(a int, g1 *obj.Addr, reg int, g2 *obj.Addr) {
   479  	var p *obj.Prog
   480  	var pl *obj.Plist
   481  
   482  	if asm.Pass == 1 {
   483  		goto out
   484  	}
   485  
   486  	if g1.Scale != 0 {
   487  		if reg != 0 || g2.Scale != 0 {
   488  			yyerror("bad addressing modes")
   489  		}
   490  		reg = int(g1.Scale)
   491  	} else if g2.Scale != 0 {
   492  		if reg != 0 {
   493  			yyerror("bad addressing modes")
   494  		}
   495  		reg = int(g2.Scale)
   496  	}
   497  
   498  	p = asm.Ctxt.NewProg()
   499  	p.As = int16(a)
   500  	p.Lineno = stmtline
   501  	if nosched != 0 {
   502  		p.Mark |= ppc64.NOSCHED
   503  	}
   504  	p.From = *g1
   505  	p.Reg = int16(reg)
   506  	p.To = *g2
   507  	p.Pc = int64(asm.PC)
   508  
   509  	if lastpc == nil {
   510  		pl = obj.Linknewplist(asm.Ctxt)
   511  		pl.Firstpc = p
   512  	} else {
   513  		lastpc.Link = p
   514  	}
   515  	lastpc = p
   516  
   517  out:
   518  	if a != obj.AGLOBL && a != obj.ADATA {
   519  		asm.PC++
   520  	}
   521  }
   522  
   523  func outgcode(a int, g1 *obj.Addr, reg int, g2, g3 *obj.Addr) {
   524  	var p *obj.Prog
   525  	var pl *obj.Plist
   526  
   527  	if asm.Pass == 1 {
   528  		goto out
   529  	}
   530  
   531  	p = asm.Ctxt.NewProg()
   532  	p.As = int16(a)
   533  	p.Lineno = stmtline
   534  	if nosched != 0 {
   535  		p.Mark |= ppc64.NOSCHED
   536  	}
   537  	p.From = *g1
   538  	p.Reg = int16(reg)
   539  	p.From3 = *g2
   540  	p.To = *g3
   541  	p.Pc = int64(asm.PC)
   542  
   543  	if lastpc == nil {
   544  		pl = obj.Linknewplist(asm.Ctxt)
   545  		pl.Firstpc = p
   546  	} else {
   547  		lastpc.Link = p
   548  	}
   549  	lastpc = p
   550  
   551  out:
   552  	if a != obj.AGLOBL && a != obj.ADATA {
   553  		asm.PC++
   554  	}
   555  }