wa-lang.org/wazero@v1.0.2/internal/asm/amd64/impl_1_test.go (about) 1 package amd64 2 3 import ( 4 "errors" 5 "strconv" 6 "testing" 7 8 "wa-lang.org/wazero/internal/asm" 9 "wa-lang.org/wazero/internal/testing/require" 10 ) 11 12 func TestNodeImpl_AssignJumpTarget(t *testing.T) { 13 n := &nodeImpl{} 14 target := &nodeImpl{} 15 n.AssignJumpTarget(target) 16 require.Equal(t, n.jumpTarget, target) 17 } 18 19 func TestNodeImpl_AssignDestinationConstant(t *testing.T) { 20 n := &nodeImpl{} 21 n.AssignDestinationConstant(12345) 22 require.Equal(t, int64(12345), n.dstConst) 23 } 24 25 func TestNodeImpl_AssignSourceConstant(t *testing.T) { 26 n := &nodeImpl{} 27 n.AssignSourceConstant(12345) 28 require.Equal(t, int64(12345), n.srcConst) 29 } 30 31 func TestAssemblerImpl_Assemble(t *testing.T) { 32 t.Run("callback", func(t *testing.T) { 33 t.Run("ok", func(t *testing.T) { 34 a := NewAssembler() 35 callbacked := false 36 a.AddOnGenerateCallBack(func(b []byte) error { callbacked = true; return nil }) 37 _, err := a.Assemble() 38 require.NoError(t, err) 39 require.True(t, callbacked) 40 }) 41 t.Run("error", func(t *testing.T) { 42 a := NewAssembler() 43 a.AddOnGenerateCallBack(func(b []byte) error { return errors.New("some error") }) 44 _, err := a.Assemble() 45 require.EqualError(t, err, "some error") 46 }) 47 }) 48 t.Run("no reassemble", func(t *testing.T) { 49 a := NewAssembler() 50 51 jmp := a.CompileJump(JCC) 52 const dummyInstruction = CDQ 53 a.CompileStandAlone(dummyInstruction) 54 a.CompileStandAlone(dummyInstruction) 55 a.CompileStandAlone(dummyInstruction) 56 jmp.AssignJumpTarget(a.CompileStandAlone(dummyInstruction)) 57 58 actual, err := a.Assemble() 59 require.NoError(t, err) 60 61 require.Equal(t, []byte{0x73, 0x3, 0x99, 0x99, 0x99, 0x99}, actual) 62 }) 63 t.Run("re-assemble", func(t *testing.T) { 64 a := NewAssembler() 65 jmp := a.CompileJump(JCC) 66 const dummyInstruction = CDQ 67 // Ensure that at least 128 bytes between JCC and the target which results in 68 // reassemble as we have to convert the forward jump as long variant. 69 for i := 0; i < 128; i++ { 70 a.CompileStandAlone(dummyInstruction) 71 } 72 jmp.AssignJumpTarget(a.CompileStandAlone(dummyInstruction)) 73 74 a.InitializeNodesForEncoding() 75 76 // For the first encoding, we must be forced to reassemble. 77 err := a.Encode() 78 require.NoError(t, err) 79 require.True(t, a.forceReAssemble) 80 }) 81 } 82 83 func TestNodeImpl_String(t *testing.T) { 84 tests := []struct { 85 in *nodeImpl 86 exp string 87 }{ 88 { 89 in: &nodeImpl{instruction: NOP}, 90 exp: "NOP", 91 }, 92 { 93 in: &nodeImpl{instruction: SETCC, types: operandTypesNoneToRegister, dstReg: RegAX}, 94 exp: "SETCC AX", 95 }, 96 { 97 in: &nodeImpl{instruction: JMP, types: operandTypesNoneToMemory, dstReg: RegAX, dstConst: 100}, 98 exp: "JMP [AX + 0x64]", 99 }, 100 { 101 in: &nodeImpl{instruction: JMP, types: operandTypesNoneToMemory, dstReg: RegAX, dstConst: 100, dstMemScale: 8, dstMemIndex: RegR11}, 102 exp: "JMP [AX + 0x64 + R11*0x8]", 103 }, 104 { 105 in: &nodeImpl{instruction: JMP, types: operandTypesNoneToBranch, jumpTarget: &nodeImpl{instruction: JMP, types: operandTypesNoneToMemory, dstReg: RegAX, dstConst: 100}}, 106 exp: "JMP {JMP [AX + 0x64]}", 107 }, 108 { 109 in: &nodeImpl{instruction: IDIVQ, types: operandTypesRegisterToNone, srcReg: RegDX}, 110 exp: "IDIVQ DX", 111 }, 112 { 113 in: &nodeImpl{instruction: ADDL, types: operandTypesRegisterToRegister, srcReg: RegDX, dstReg: RegR14}, 114 exp: "ADDL DX, R14", 115 }, 116 { 117 in: &nodeImpl{ 118 instruction: MOVQ, types: operandTypesRegisterToMemory, 119 srcReg: RegDX, dstReg: RegR14, dstConst: 100, 120 }, 121 exp: "MOVQ DX, [R14 + 0x64]", 122 }, 123 { 124 in: &nodeImpl{ 125 instruction: MOVQ, types: operandTypesRegisterToMemory, 126 srcReg: RegDX, dstReg: RegR14, dstConst: 100, dstMemIndex: RegCX, dstMemScale: 4, 127 }, 128 exp: "MOVQ DX, [R14 + 0x64 + CX*0x4]", 129 }, 130 { 131 in: &nodeImpl{ 132 instruction: CMPL, types: operandTypesRegisterToConst, 133 srcReg: RegDX, dstConst: 100, 134 }, 135 exp: "CMPL DX, 0x64", 136 }, 137 { 138 in: &nodeImpl{ 139 instruction: MOVL, types: operandTypesMemoryToRegister, 140 srcReg: RegDX, srcConst: 1, dstReg: RegAX, 141 }, 142 exp: "MOVL [DX + 0x1], AX", 143 }, 144 { 145 in: &nodeImpl{ 146 instruction: MOVL, types: operandTypesMemoryToRegister, 147 srcReg: RegDX, srcConst: 1, srcMemIndex: RegR12, srcMemScale: 2, 148 dstReg: RegAX, 149 }, 150 exp: "MOVL [DX + 0x1 + R12*0x2], AX", 151 }, 152 { 153 in: &nodeImpl{ 154 instruction: CMPQ, types: operandTypesMemoryToConst, 155 srcReg: RegDX, srcConst: 1, srcMemIndex: RegR12, srcMemScale: 2, 156 dstConst: 123, 157 }, 158 exp: "CMPQ [DX + 0x1 + R12*0x2], 0x7b", 159 }, 160 { 161 in: &nodeImpl{instruction: CMPQ, types: operandTypesMemoryToConst, srcReg: RegDX, srcConst: 1, dstConst: 123}, 162 exp: "CMPQ [DX + 0x1], 0x7b", 163 }, 164 { 165 in: &nodeImpl{instruction: MOVQ, types: operandTypesConstToMemory, srcConst: 123, dstReg: RegAX, dstConst: 100, dstMemScale: 8, dstMemIndex: RegR11}, 166 exp: "MOVQ 0x7b, [AX + 0x64 + R11*0x8]", 167 }, 168 { 169 in: &nodeImpl{instruction: MOVQ, types: operandTypesConstToMemory, srcConst: 123, dstReg: RegAX, dstConst: 100}, 170 exp: "MOVQ 0x7b, [AX + 0x64]", 171 }, 172 { 173 in: &nodeImpl{instruction: MOVQ, types: operandTypesConstToRegister, srcConst: 123, dstReg: RegAX}, 174 exp: "MOVQ 0x7b, AX", 175 }, 176 { 177 in: &nodeImpl{instruction: LEAQ, types: operandTypesStaticConstToRegister, staticConst: &asm.StaticConst{Raw: []byte{0xff, 0x01, 0x2, 0xff}}, dstReg: RegAX}, 178 exp: "LEAQ $0xff0102ff, AX", 179 }, 180 { 181 in: &nodeImpl{instruction: CMPQ, types: operandTypesRegisterToStaticConst, staticConst: &asm.StaticConst{Raw: []byte{0xff, 0x01, 0x2, 0xff}}, srcReg: RegAX}, 182 exp: "CMPQ AX, $0xff0102ff", 183 }, 184 } 185 186 for _, tt := range tests { 187 tc := tt 188 require.Equal(t, tc.exp, tc.in.String()) 189 } 190 } 191 192 func TestAssemblerImpl_addNode(t *testing.T) { 193 a := NewAssembler() 194 195 root := &nodeImpl{} 196 a.addNode(root) 197 require.Equal(t, a.root, root) 198 require.Equal(t, a.current, root) 199 require.Nil(t, root.next) 200 201 next := &nodeImpl{} 202 a.addNode(next) 203 require.Equal(t, a.root, root) 204 require.Equal(t, a.current, next) 205 require.Equal(t, next, root.next) 206 require.Nil(t, next.next) 207 } 208 209 func TestAssemblerImpl_newNode(t *testing.T) { 210 a := NewAssembler() 211 actual := a.newNode(ADDL, operandTypesConstToMemory) 212 require.Equal(t, ADDL, actual.instruction) 213 require.Equal(t, operandTypeConst, actual.types.src) 214 require.Equal(t, operandTypeMemory, actual.types.dst) 215 require.Equal(t, actual, a.root) 216 require.Equal(t, actual, a.current) 217 } 218 219 func TestAssemblerImpl_encodeNode(t *testing.T) { 220 a := NewAssembler() 221 err := a.EncodeNode(&nodeImpl{ 222 instruction: ADDPD, 223 types: operandTypesRegisterToMemory, 224 }) 225 require.EqualError(t, err, "ADDPD is unsupported for from:register,to:memory type: ADDPD nil, [nil + 0x0]") 226 } 227 228 func TestAssemblerImpl_padNOP(t *testing.T) { 229 tests := []struct { 230 num int 231 expected []byte 232 }{ 233 {num: 1, expected: nopOpcodes[0][:1]}, 234 {num: 2, expected: nopOpcodes[1][:2]}, 235 {num: 3, expected: nopOpcodes[2][:3]}, 236 {num: 4, expected: nopOpcodes[3][:4]}, 237 {num: 5, expected: nopOpcodes[4][:5]}, 238 {num: 6, expected: nopOpcodes[5][:6]}, 239 {num: 7, expected: nopOpcodes[6][:7]}, 240 {num: 8, expected: nopOpcodes[7][:8]}, 241 {num: 9, expected: nopOpcodes[8][:9]}, 242 {num: 10, expected: nopOpcodes[9][:10]}, 243 {num: 11, expected: nopOpcodes[10][:11]}, 244 {num: 12, expected: append(nopOpcodes[10][:11], nopOpcodes[0][:1]...)}, 245 {num: 13, expected: append(nopOpcodes[10][:11], nopOpcodes[1][:2]...)}, 246 {num: 14, expected: append(nopOpcodes[10][:11], nopOpcodes[2][:3]...)}, 247 {num: 15, expected: append(nopOpcodes[10][:11], nopOpcodes[3][:4]...)}, 248 {num: 16, expected: append(nopOpcodes[10][:11], nopOpcodes[4][:5]...)}, 249 {num: 17, expected: append(nopOpcodes[10][:11], nopOpcodes[5][:6]...)}, 250 {num: 18, expected: append(nopOpcodes[10][:11], nopOpcodes[6][:7]...)}, 251 {num: 19, expected: append(nopOpcodes[10][:11], nopOpcodes[7][:8]...)}, 252 {num: 20, expected: append(nopOpcodes[10][:11], nopOpcodes[8][:9]...)}, 253 } 254 255 for _, tt := range tests { 256 tc := tt 257 t.Run(strconv.Itoa(tc.num), func(t *testing.T) { 258 a := NewAssembler() 259 a.padNOP(tc.num) 260 actual := a.buf.Bytes() 261 require.Equal(t, tc.expected, actual) 262 }) 263 } 264 } 265 266 func TestAssemblerImpl_CompileStandAlone(t *testing.T) { 267 a := NewAssembler() 268 a.CompileStandAlone(RET) 269 actualNode := a.current 270 require.Equal(t, RET, actualNode.instruction) 271 require.Equal(t, operandTypeNone, actualNode.types.src) 272 require.Equal(t, operandTypeNone, actualNode.types.dst) 273 } 274 275 func TestAssemblerImpl_CompileConstToRegister(t *testing.T) { 276 a := NewAssembler() 277 a.CompileConstToRegister(MOVQ, 1000, RegAX) 278 actualNode := a.current 279 require.Equal(t, MOVQ, actualNode.instruction) 280 require.Equal(t, int64(1000), actualNode.srcConst) 281 require.Equal(t, RegAX, actualNode.dstReg) 282 require.Equal(t, operandTypeConst, actualNode.types.src) 283 require.Equal(t, operandTypeRegister, actualNode.types.dst) 284 } 285 286 func TestAssemblerImpl_CompileRegisterToRegister(t *testing.T) { 287 a := NewAssembler() 288 a.CompileRegisterToRegister(MOVQ, RegBX, RegAX) 289 actualNode := a.current 290 require.Equal(t, MOVQ, actualNode.instruction) 291 require.Equal(t, RegBX, actualNode.srcReg) 292 require.Equal(t, RegAX, actualNode.dstReg) 293 require.Equal(t, operandTypeRegister, actualNode.types.src) 294 require.Equal(t, operandTypeRegister, actualNode.types.dst) 295 } 296 297 func TestAssemblerImpl_CompileMemoryToRegister(t *testing.T) { 298 a := NewAssembler() 299 a.CompileMemoryToRegister(MOVQ, RegBX, 100, RegAX) 300 actualNode := a.current 301 require.Equal(t, MOVQ, actualNode.instruction) 302 require.Equal(t, RegBX, actualNode.srcReg) 303 require.Equal(t, int64(100), actualNode.srcConst) 304 require.Equal(t, RegAX, actualNode.dstReg) 305 require.Equal(t, operandTypeMemory, actualNode.types.src) 306 require.Equal(t, operandTypeRegister, actualNode.types.dst) 307 } 308 309 func TestAssemblerImpl_CompileRegisterToMemory(t *testing.T) { 310 a := NewAssembler() 311 a.CompileRegisterToMemory(MOVQ, RegBX, RegAX, 100) 312 actualNode := a.current 313 require.Equal(t, MOVQ, actualNode.instruction) 314 require.Equal(t, RegBX, actualNode.srcReg) 315 require.Equal(t, RegAX, actualNode.dstReg) 316 require.Equal(t, int64(100), actualNode.dstConst) 317 require.Equal(t, operandTypeRegister, actualNode.types.src) 318 require.Equal(t, operandTypeMemory, actualNode.types.dst) 319 } 320 321 func TestAssemblerImpl_CompileJump(t *testing.T) { 322 a := NewAssembler() 323 a.CompileJump(JMP) 324 actualNode := a.current 325 require.Equal(t, JMP, actualNode.instruction) 326 require.Equal(t, operandTypeNone, actualNode.types.src) 327 require.Equal(t, operandTypeBranch, actualNode.types.dst) 328 } 329 330 func TestAssemblerImpl_CompileJumpToRegister(t *testing.T) { 331 a := NewAssembler() 332 a.CompileJumpToRegister(JNE, RegAX) 333 actualNode := a.current 334 require.Equal(t, JNE, actualNode.instruction) 335 require.Equal(t, RegAX, actualNode.dstReg) 336 require.Equal(t, operandTypeNone, actualNode.types.src) 337 require.Equal(t, operandTypeRegister, actualNode.types.dst) 338 } 339 340 func TestAssemblerImpl_CompileJumpToMemory(t *testing.T) { 341 a := NewAssembler() 342 a.CompileJumpToMemory(JNE, RegAX, 100) 343 actualNode := a.current 344 require.Equal(t, JNE, actualNode.instruction) 345 require.Equal(t, RegAX, actualNode.dstReg) 346 require.Equal(t, int64(100), actualNode.dstConst) 347 require.Equal(t, operandTypeNone, actualNode.types.src) 348 require.Equal(t, operandTypeMemory, actualNode.types.dst) 349 } 350 351 func TestAssemblerImpl_CompileReadInstructionAddress(t *testing.T) { 352 a := NewAssembler() 353 a.CompileReadInstructionAddress(RegR10, RET) 354 actualNode := a.current 355 require.Equal(t, LEAQ, actualNode.instruction) 356 require.Equal(t, RegR10, actualNode.dstReg) 357 require.Equal(t, operandTypeMemory, actualNode.types.src) 358 require.Equal(t, operandTypeRegister, actualNode.types.dst) 359 require.Equal(t, RET, actualNode.readInstructionAddressBeforeTargetInstruction) 360 } 361 362 func TestAssemblerImpl_CompileRegisterToRegisterWithArg(t *testing.T) { 363 a := NewAssembler() 364 a.CompileRegisterToRegisterWithArg(MOVQ, RegBX, RegAX, 123) 365 actualNode := a.current 366 require.Equal(t, MOVQ, actualNode.instruction) 367 require.Equal(t, RegBX, actualNode.srcReg) 368 require.Equal(t, RegAX, actualNode.dstReg) 369 require.Equal(t, byte(123), actualNode.arg) 370 require.Equal(t, operandTypeRegister, actualNode.types.src) 371 require.Equal(t, operandTypeRegister, actualNode.types.dst) 372 } 373 374 func TestAssemblerImpl_CompileMemoryWithIndexToRegister(t *testing.T) { 375 a := NewAssembler() 376 a.CompileMemoryWithIndexToRegister(MOVQ, RegBX, 100, RegR10, 8, RegAX) 377 actualNode := a.current 378 require.Equal(t, MOVQ, actualNode.instruction) 379 require.Equal(t, RegBX, actualNode.srcReg) 380 require.Equal(t, int64(100), actualNode.srcConst) 381 require.Equal(t, RegR10, actualNode.srcMemIndex) 382 require.Equal(t, byte(8), actualNode.srcMemScale) 383 require.Equal(t, RegAX, actualNode.dstReg) 384 require.Equal(t, operandTypeMemory, actualNode.types.src) 385 require.Equal(t, operandTypeRegister, actualNode.types.dst) 386 } 387 388 func TestAssemblerImpl_CompileRegisterToConst(t *testing.T) { 389 a := NewAssembler() 390 a.CompileRegisterToConst(MOVQ, RegBX, 123) 391 actualNode := a.current 392 require.Equal(t, RegBX, actualNode.srcReg) 393 require.Equal(t, int64(123), actualNode.dstConst) 394 require.Equal(t, operandTypeRegister, actualNode.types.src) 395 require.Equal(t, operandTypeConst, actualNode.types.dst) 396 } 397 398 func TestAssemblerImpl_CompileRegisterToNone(t *testing.T) { 399 a := NewAssembler() 400 a.CompileRegisterToNone(MOVQ, RegBX) 401 actualNode := a.current 402 require.Equal(t, RegBX, actualNode.srcReg) 403 require.Equal(t, operandTypeRegister, actualNode.types.src) 404 require.Equal(t, operandTypeNone, actualNode.types.dst) 405 } 406 407 func TestAssemblerImpl_CompileNoneToRegister(t *testing.T) { 408 a := NewAssembler() 409 a.CompileNoneToRegister(MOVQ, RegBX) 410 actualNode := a.current 411 require.Equal(t, RegBX, actualNode.dstReg) 412 require.Equal(t, operandTypeNone, actualNode.types.src) 413 require.Equal(t, operandTypeRegister, actualNode.types.dst) 414 } 415 416 func TestAssemblerImpl_CompileNoneToMemory(t *testing.T) { 417 a := NewAssembler() 418 a.CompileNoneToMemory(MOVQ, RegBX, 1234) 419 actualNode := a.current 420 require.Equal(t, RegBX, actualNode.dstReg) 421 require.Equal(t, int64(1234), actualNode.dstConst) 422 require.Equal(t, operandTypeNone, actualNode.types.src) 423 require.Equal(t, operandTypeMemory, actualNode.types.dst) 424 } 425 426 func TestAssemblerImpl_CompileConstToMemory(t *testing.T) { 427 a := NewAssembler() 428 a.CompileConstToMemory(MOVQ, -9999, RegBX, 1234) 429 actualNode := a.current 430 require.Equal(t, RegBX, actualNode.dstReg) 431 require.Equal(t, int64(-9999), actualNode.srcConst) 432 require.Equal(t, int64(1234), actualNode.dstConst) 433 require.Equal(t, operandTypeConst, actualNode.types.src) 434 require.Equal(t, operandTypeMemory, actualNode.types.dst) 435 } 436 437 func TestAssemblerImpl_CompileMemoryToConst(t *testing.T) { 438 a := NewAssembler() 439 a.CompileMemoryToConst(MOVQ, RegBX, 1234, -9999) 440 actualNode := a.current 441 require.Equal(t, RegBX, actualNode.srcReg) 442 require.Equal(t, int64(1234), actualNode.srcConst) 443 require.Equal(t, int64(-9999), actualNode.dstConst) 444 require.Equal(t, operandTypeMemory, actualNode.types.src) 445 require.Equal(t, operandTypeConst, actualNode.types.dst) 446 } 447 448 func TestAssemblerImpl_encodeNoneToNone(t *testing.T) { 449 tests := []struct { 450 inst asm.Instruction 451 exp []byte 452 expErr bool 453 }{ 454 {inst: ADDL, expErr: true}, 455 {inst: CDQ, exp: []byte{0x99}}, 456 {inst: CQO, exp: []byte{0x48, 0x99}}, 457 {inst: NOP, exp: nil}, 458 {inst: RET, exp: []byte{0xc3}}, 459 {inst: REPMOVSQ, exp: []byte{0xf3, RexPrefixW, 0xa5}}, 460 {inst: REPSTOSQ, exp: []byte{0xf3, RexPrefixW, 0xab}}, 461 {inst: STD, exp: []byte{0xfd}}, 462 {inst: CLD, exp: []byte{0xfc}}, 463 } 464 465 for _, tt := range tests { 466 tc := tt 467 t.Run(InstructionName(tc.inst), func(t *testing.T) { 468 a := NewAssembler() 469 err := a.encodeNoneToNone(&nodeImpl{instruction: tc.inst, types: operandTypesNoneToNone}) 470 if tc.expErr { 471 require.Error(t, err) 472 } else { 473 require.NoError(t, err) 474 require.Equal(t, tc.exp, a.buf.Bytes()) 475 } 476 }) 477 } 478 } 479 480 func TestAssemblerImpl_EncodeMemoryToRegister(t *testing.T) { 481 tests := []struct { 482 name string 483 n *nodeImpl 484 exp []byte 485 }{ 486 {name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegAX, dstReg: RegX3, srcConst: 10}, exp: []byte{0xf3, 0xf, 0x6f, 0x58, 0xa}}, 487 {name: "MOVDQU/2", n: &nodeImpl{instruction: MOVDQU, srcReg: RegR13, dstReg: RegX3, srcConst: 10}, exp: []byte{0xf3, 0x41, 0xf, 0x6f, 0x5d, 0xa}}, 488 {name: "PINSRB/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0x20, 0x0}}, 489 {name: "PINSRB/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0x20, 0x1}}, 490 {name: "PINSRB/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0x20, 0x1, 0x0}}, 491 {name: "PINSRB/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0x20, 0x1, 0x1}}, 492 {name: "PINSRB/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 493 {name: "PINSRB/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 494 {name: "PINSRB/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x0, 0x0}}, 495 {name: "PINSRB/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x0, 0x1}}, 496 {name: "PINSRB/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x0, 0x1, 0x0}}, 497 {name: "PINSRB/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x0, 0x1, 0x1}}, 498 {name: "PINSRB/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 499 {name: "PINSRB/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 500 {name: "PINSRB/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x28, 0x0}}, 501 {name: "PINSRB/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x28, 0x1}}, 502 {name: "PINSRB/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x28, 0x1, 0x0}}, 503 {name: "PINSRB/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x28, 0x1, 0x1}}, 504 {name: "PINSRB/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 505 {name: "PINSRB/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 506 {name: "PINSRB/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x30, 0x0}}, 507 {name: "PINSRB/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x30, 0x1}}, 508 {name: "PINSRB/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x30, 0x1, 0x0}}, 509 {name: "PINSRB/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x30, 0x1, 0x1}}, 510 {name: "PINSRB/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 511 {name: "PINSRB/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 512 {name: "PINSRB/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0x20, 0x0}}, 513 {name: "PINSRB/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0x20, 0x1}}, 514 {name: "PINSRB/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0x20, 0x1, 0x0}}, 515 {name: "PINSRB/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0x20, 0x1, 0x1}}, 516 {name: "PINSRB/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 517 {name: "PINSRB/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 518 {name: "PINSRB/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x0, 0x0}}, 519 {name: "PINSRB/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x0, 0x1}}, 520 {name: "PINSRB/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x0, 0x1, 0x0}}, 521 {name: "PINSRB/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x0, 0x1, 0x1}}, 522 {name: "PINSRB/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 523 {name: "PINSRB/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 524 {name: "PINSRB/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x28, 0x0}}, 525 {name: "PINSRB/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x28, 0x1}}, 526 {name: "PINSRB/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x28, 0x1, 0x0}}, 527 {name: "PINSRB/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x28, 0x1, 0x1}}, 528 {name: "PINSRB/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 529 {name: "PINSRB/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 530 {name: "PINSRB/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x30, 0x0}}, 531 {name: "PINSRB/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x30, 0x1}}, 532 {name: "PINSRB/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x30, 0x1, 0x0}}, 533 {name: "PINSRB/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x30, 0x1, 0x1}}, 534 {name: "PINSRB/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 535 {name: "PINSRB/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 536 {name: "PINSRB/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0x60, 0x0}}, 537 {name: "PINSRB/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0x60, 0x1}}, 538 {name: "PINSRB/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0x60, 0x1, 0x0}}, 539 {name: "PINSRB/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0x60, 0x1, 0x1}}, 540 {name: "PINSRB/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 541 {name: "PINSRB/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 542 {name: "PINSRB/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x40, 0x0}}, 543 {name: "PINSRB/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x40, 0x1}}, 544 {name: "PINSRB/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x40, 0x1, 0x0}}, 545 {name: "PINSRB/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x40, 0x1, 0x1}}, 546 {name: "PINSRB/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 547 {name: "PINSRB/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 548 {name: "PINSRB/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x68, 0x0}}, 549 {name: "PINSRB/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x68, 0x1}}, 550 {name: "PINSRB/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x68, 0x1, 0x0}}, 551 {name: "PINSRB/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x68, 0x1, 0x1}}, 552 {name: "PINSRB/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 553 {name: "PINSRB/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 554 {name: "PINSRB/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x70, 0x0}}, 555 {name: "PINSRB/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x70, 0x1}}, 556 {name: "PINSRB/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x70, 0x1, 0x0}}, 557 {name: "PINSRB/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x70, 0x1, 0x1}}, 558 {name: "PINSRB/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 559 {name: "PINSRB/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 560 {name: "PINSRB/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0x60, 0x0}}, 561 {name: "PINSRB/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0x60, 0x1}}, 562 {name: "PINSRB/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0x60, 0x1, 0x0}}, 563 {name: "PINSRB/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0x60, 0x1, 0x1}}, 564 {name: "PINSRB/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 565 {name: "PINSRB/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 566 {name: "PINSRB/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x40, 0x0}}, 567 {name: "PINSRB/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x40, 0x1}}, 568 {name: "PINSRB/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x40, 0x1, 0x0}}, 569 {name: "PINSRB/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x40, 0x1, 0x1}}, 570 {name: "PINSRB/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 571 {name: "PINSRB/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 572 {name: "PINSRB/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x68, 0x0}}, 573 {name: "PINSRB/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x68, 0x1}}, 574 {name: "PINSRB/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x68, 0x1, 0x0}}, 575 {name: "PINSRB/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x68, 0x1, 0x1}}, 576 {name: "PINSRB/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 577 {name: "PINSRB/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 578 {name: "PINSRB/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x70, 0x0}}, 579 {name: "PINSRB/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x70, 0x1}}, 580 {name: "PINSRB/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x70, 0x1, 0x0}}, 581 {name: "PINSRB/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x70, 0x1, 0x1}}, 582 {name: "PINSRB/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 583 {name: "PINSRB/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 584 {name: "PINSRB/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0xa0, 0x0}}, 585 {name: "PINSRB/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0xa0, 0x1}}, 586 {name: "PINSRB/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0xa0, 0x1, 0x0}}, 587 {name: "PINSRB/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0xa0, 0x1, 0x1}}, 588 {name: "PINSRB/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 589 {name: "PINSRB/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 590 {name: "PINSRB/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x80, 0x0}}, 591 {name: "PINSRB/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x80, 0x1}}, 592 {name: "PINSRB/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x80, 0x1, 0x0}}, 593 {name: "PINSRB/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x80, 0x1, 0x1}}, 594 {name: "PINSRB/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 595 {name: "PINSRB/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 596 {name: "PINSRB/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xa8, 0x0}}, 597 {name: "PINSRB/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xa8, 0x1}}, 598 {name: "PINSRB/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xa8, 0x1, 0x0}}, 599 {name: "PINSRB/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xa8, 0x1, 0x1}}, 600 {name: "PINSRB/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 601 {name: "PINSRB/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 602 {name: "PINSRB/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xb0, 0x0}}, 603 {name: "PINSRB/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xb0, 0x1}}, 604 {name: "PINSRB/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xb0, 0x1, 0x0}}, 605 {name: "PINSRB/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xb0, 0x1, 0x1}}, 606 {name: "PINSRB/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 607 {name: "PINSRB/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 608 {name: "PINSRB/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0xa0, 0x0}}, 609 {name: "PINSRB/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0xa0, 0x1}}, 610 {name: "PINSRB/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0xa0, 0x1, 0x0}}, 611 {name: "PINSRB/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0xa0, 0x1, 0x1}}, 612 {name: "PINSRB/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 613 {name: "PINSRB/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 614 {name: "PINSRB/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x80, 0x0}}, 615 {name: "PINSRB/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x80, 0x1}}, 616 {name: "PINSRB/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x80, 0x1, 0x0}}, 617 {name: "PINSRB/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x80, 0x1, 0x1}}, 618 {name: "PINSRB/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 619 {name: "PINSRB/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 620 {name: "PINSRB/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xa8, 0x0}}, 621 {name: "PINSRB/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xa8, 0x1}}, 622 {name: "PINSRB/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xa8, 0x1, 0x0}}, 623 {name: "PINSRB/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xa8, 0x1, 0x1}}, 624 {name: "PINSRB/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 625 {name: "PINSRB/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 626 {name: "PINSRB/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xb0, 0x0}}, 627 {name: "PINSRB/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xb0, 0x1}}, 628 {name: "PINSRB/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xb0, 0x1, 0x0}}, 629 {name: "PINSRB/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xb0, 0x1, 0x1}}, 630 {name: "PINSRB/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 631 {name: "PINSRB/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 632 {name: "PINSRB/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0xe0, 0x0}}, 633 {name: "PINSRB/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0xe0, 0x1}}, 634 {name: "PINSRB/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0xe0, 0x1, 0x0}}, 635 {name: "PINSRB/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0xe0, 0x1, 0x1}}, 636 {name: "PINSRB/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 637 {name: "PINSRB/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 638 {name: "PINSRB/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xc0, 0x0}}, 639 {name: "PINSRB/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xc0, 0x1}}, 640 {name: "PINSRB/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xc0, 0x1, 0x0}}, 641 {name: "PINSRB/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xc0, 0x1, 0x1}}, 642 {name: "PINSRB/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 643 {name: "PINSRB/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 644 {name: "PINSRB/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xe8, 0x0}}, 645 {name: "PINSRB/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xe8, 0x1}}, 646 {name: "PINSRB/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xe8, 0x1, 0x0}}, 647 {name: "PINSRB/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xe8, 0x1, 0x1}}, 648 {name: "PINSRB/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 649 {name: "PINSRB/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 650 {name: "PINSRB/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xf0, 0x0}}, 651 {name: "PINSRB/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xf0, 0x1}}, 652 {name: "PINSRB/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xf0, 0x1, 0x0}}, 653 {name: "PINSRB/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xf0, 0x1, 0x1}}, 654 {name: "PINSRB/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 655 {name: "PINSRB/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 656 {name: "PINSRB/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0xe0, 0x0}}, 657 {name: "PINSRB/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0xe0, 0x1}}, 658 {name: "PINSRB/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0xe0, 0x1, 0x0}}, 659 {name: "PINSRB/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0xe0, 0x1, 0x1}}, 660 {name: "PINSRB/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 661 {name: "PINSRB/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 662 {name: "PINSRB/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xc0, 0x0}}, 663 {name: "PINSRB/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xc0, 0x1}}, 664 {name: "PINSRB/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xc0, 0x1, 0x0}}, 665 {name: "PINSRB/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xc0, 0x1, 0x1}}, 666 {name: "PINSRB/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 667 {name: "PINSRB/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 668 {name: "PINSRB/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xe8, 0x0}}, 669 {name: "PINSRB/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xe8, 0x1}}, 670 {name: "PINSRB/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xe8, 0x1, 0x0}}, 671 {name: "PINSRB/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xe8, 0x1, 0x1}}, 672 {name: "PINSRB/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 673 {name: "PINSRB/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 674 {name: "PINSRB/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xf0, 0x0}}, 675 {name: "PINSRB/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xf0, 0x1}}, 676 {name: "PINSRB/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xf0, 0x1, 0x0}}, 677 {name: "PINSRB/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xf0, 0x1, 0x1}}, 678 {name: "PINSRB/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 679 {name: "PINSRB/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 680 {name: "PINSRW/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0x20, 0x0}}, 681 {name: "PINSRW/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0x20, 0x1}}, 682 {name: "PINSRW/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0x20, 0x1, 0x0}}, 683 {name: "PINSRW/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0x20, 0x1, 0x1}}, 684 {name: "PINSRW/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 685 {name: "PINSRW/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 686 {name: "PINSRW/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x0, 0x0}}, 687 {name: "PINSRW/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x0, 0x1}}, 688 {name: "PINSRW/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x0, 0x1, 0x0}}, 689 {name: "PINSRW/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x0, 0x1, 0x1}}, 690 {name: "PINSRW/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 691 {name: "PINSRW/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 692 {name: "PINSRW/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x28, 0x0}}, 693 {name: "PINSRW/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x28, 0x1}}, 694 {name: "PINSRW/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x28, 0x1, 0x0}}, 695 {name: "PINSRW/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x28, 0x1, 0x1}}, 696 {name: "PINSRW/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 697 {name: "PINSRW/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 698 {name: "PINSRW/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x30, 0x0}}, 699 {name: "PINSRW/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x30, 0x1}}, 700 {name: "PINSRW/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x30, 0x1, 0x0}}, 701 {name: "PINSRW/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x30, 0x1, 0x1}}, 702 {name: "PINSRW/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 703 {name: "PINSRW/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 704 {name: "PINSRW/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0x20, 0x0}}, 705 {name: "PINSRW/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0x20, 0x1}}, 706 {name: "PINSRW/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0x20, 0x1, 0x0}}, 707 {name: "PINSRW/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0x20, 0x1, 0x1}}, 708 {name: "PINSRW/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 709 {name: "PINSRW/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 710 {name: "PINSRW/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x0, 0x0}}, 711 {name: "PINSRW/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x0, 0x1}}, 712 {name: "PINSRW/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x0, 0x1, 0x0}}, 713 {name: "PINSRW/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x0, 0x1, 0x1}}, 714 {name: "PINSRW/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 715 {name: "PINSRW/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 716 {name: "PINSRW/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x28, 0x0}}, 717 {name: "PINSRW/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x28, 0x1}}, 718 {name: "PINSRW/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x28, 0x1, 0x0}}, 719 {name: "PINSRW/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x28, 0x1, 0x1}}, 720 {name: "PINSRW/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 721 {name: "PINSRW/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 722 {name: "PINSRW/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x30, 0x0}}, 723 {name: "PINSRW/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x30, 0x1}}, 724 {name: "PINSRW/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x30, 0x1, 0x0}}, 725 {name: "PINSRW/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x30, 0x1, 0x1}}, 726 {name: "PINSRW/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 727 {name: "PINSRW/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 728 {name: "PINSRW/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0x60, 0x0}}, 729 {name: "PINSRW/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0x60, 0x1}}, 730 {name: "PINSRW/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0x60, 0x1, 0x0}}, 731 {name: "PINSRW/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0x60, 0x1, 0x1}}, 732 {name: "PINSRW/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 733 {name: "PINSRW/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 734 {name: "PINSRW/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x40, 0x0}}, 735 {name: "PINSRW/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x40, 0x1}}, 736 {name: "PINSRW/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x40, 0x1, 0x0}}, 737 {name: "PINSRW/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x40, 0x1, 0x1}}, 738 {name: "PINSRW/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 739 {name: "PINSRW/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 740 {name: "PINSRW/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x68, 0x0}}, 741 {name: "PINSRW/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x68, 0x1}}, 742 {name: "PINSRW/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x68, 0x1, 0x0}}, 743 {name: "PINSRW/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x68, 0x1, 0x1}}, 744 {name: "PINSRW/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 745 {name: "PINSRW/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 746 {name: "PINSRW/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x70, 0x0}}, 747 {name: "PINSRW/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x70, 0x1}}, 748 {name: "PINSRW/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x70, 0x1, 0x0}}, 749 {name: "PINSRW/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x70, 0x1, 0x1}}, 750 {name: "PINSRW/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 751 {name: "PINSRW/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 752 {name: "PINSRW/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0x60, 0x0}}, 753 {name: "PINSRW/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0x60, 0x1}}, 754 {name: "PINSRW/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0x60, 0x1, 0x0}}, 755 {name: "PINSRW/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0x60, 0x1, 0x1}}, 756 {name: "PINSRW/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 757 {name: "PINSRW/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 758 {name: "PINSRW/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x40, 0x0}}, 759 {name: "PINSRW/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x40, 0x1}}, 760 {name: "PINSRW/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x40, 0x1, 0x0}}, 761 {name: "PINSRW/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x40, 0x1, 0x1}}, 762 {name: "PINSRW/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 763 {name: "PINSRW/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 764 {name: "PINSRW/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x68, 0x0}}, 765 {name: "PINSRW/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x68, 0x1}}, 766 {name: "PINSRW/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x68, 0x1, 0x0}}, 767 {name: "PINSRW/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x68, 0x1, 0x1}}, 768 {name: "PINSRW/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 769 {name: "PINSRW/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 770 {name: "PINSRW/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x70, 0x0}}, 771 {name: "PINSRW/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x70, 0x1}}, 772 {name: "PINSRW/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x70, 0x1, 0x0}}, 773 {name: "PINSRW/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x70, 0x1, 0x1}}, 774 {name: "PINSRW/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 775 {name: "PINSRW/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 776 {name: "PINSRW/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0xa0, 0x0}}, 777 {name: "PINSRW/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0xa0, 0x1}}, 778 {name: "PINSRW/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0xa0, 0x1, 0x0}}, 779 {name: "PINSRW/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0xa0, 0x1, 0x1}}, 780 {name: "PINSRW/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 781 {name: "PINSRW/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 782 {name: "PINSRW/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x80, 0x0}}, 783 {name: "PINSRW/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x80, 0x1}}, 784 {name: "PINSRW/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x80, 0x1, 0x0}}, 785 {name: "PINSRW/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x80, 0x1, 0x1}}, 786 {name: "PINSRW/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 787 {name: "PINSRW/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 788 {name: "PINSRW/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xa8, 0x0}}, 789 {name: "PINSRW/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xa8, 0x1}}, 790 {name: "PINSRW/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xa8, 0x1, 0x0}}, 791 {name: "PINSRW/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xa8, 0x1, 0x1}}, 792 {name: "PINSRW/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 793 {name: "PINSRW/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 794 {name: "PINSRW/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xb0, 0x0}}, 795 {name: "PINSRW/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xb0, 0x1}}, 796 {name: "PINSRW/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xb0, 0x1, 0x0}}, 797 {name: "PINSRW/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xb0, 0x1, 0x1}}, 798 {name: "PINSRW/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 799 {name: "PINSRW/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 800 {name: "PINSRW/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0xa0, 0x0}}, 801 {name: "PINSRW/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0xa0, 0x1}}, 802 {name: "PINSRW/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0xa0, 0x1, 0x0}}, 803 {name: "PINSRW/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0xa0, 0x1, 0x1}}, 804 {name: "PINSRW/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 805 {name: "PINSRW/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 806 {name: "PINSRW/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x80, 0x0}}, 807 {name: "PINSRW/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x80, 0x1}}, 808 {name: "PINSRW/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x80, 0x1, 0x0}}, 809 {name: "PINSRW/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x80, 0x1, 0x1}}, 810 {name: "PINSRW/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 811 {name: "PINSRW/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 812 {name: "PINSRW/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xa8, 0x0}}, 813 {name: "PINSRW/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xa8, 0x1}}, 814 {name: "PINSRW/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xa8, 0x1, 0x0}}, 815 {name: "PINSRW/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xa8, 0x1, 0x1}}, 816 {name: "PINSRW/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 817 {name: "PINSRW/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 818 {name: "PINSRW/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xb0, 0x0}}, 819 {name: "PINSRW/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xb0, 0x1}}, 820 {name: "PINSRW/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xb0, 0x1, 0x0}}, 821 {name: "PINSRW/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xb0, 0x1, 0x1}}, 822 {name: "PINSRW/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 823 {name: "PINSRW/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 824 {name: "PINSRW/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0xe0, 0x0}}, 825 {name: "PINSRW/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0xe0, 0x1}}, 826 {name: "PINSRW/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0xe0, 0x1, 0x0}}, 827 {name: "PINSRW/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0xe0, 0x1, 0x1}}, 828 {name: "PINSRW/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 829 {name: "PINSRW/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 830 {name: "PINSRW/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xc0, 0x0}}, 831 {name: "PINSRW/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xc0, 0x1}}, 832 {name: "PINSRW/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xc0, 0x1, 0x0}}, 833 {name: "PINSRW/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xc0, 0x1, 0x1}}, 834 {name: "PINSRW/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 835 {name: "PINSRW/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 836 {name: "PINSRW/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xe8, 0x0}}, 837 {name: "PINSRW/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xe8, 0x1}}, 838 {name: "PINSRW/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xe8, 0x1, 0x0}}, 839 {name: "PINSRW/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xe8, 0x1, 0x1}}, 840 {name: "PINSRW/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 841 {name: "PINSRW/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 842 {name: "PINSRW/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xf0, 0x0}}, 843 {name: "PINSRW/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xf0, 0x1}}, 844 {name: "PINSRW/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xf0, 0x1, 0x0}}, 845 {name: "PINSRW/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xf0, 0x1, 0x1}}, 846 {name: "PINSRW/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 847 {name: "PINSRW/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 848 {name: "PINSRW/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0xe0, 0x0}}, 849 {name: "PINSRW/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0xe0, 0x1}}, 850 {name: "PINSRW/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0xe0, 0x1, 0x0}}, 851 {name: "PINSRW/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0xe0, 0x1, 0x1}}, 852 {name: "PINSRW/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 853 {name: "PINSRW/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 854 {name: "PINSRW/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xc0, 0x0}}, 855 {name: "PINSRW/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xc0, 0x1}}, 856 {name: "PINSRW/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xc0, 0x1, 0x0}}, 857 {name: "PINSRW/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xc0, 0x1, 0x1}}, 858 {name: "PINSRW/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 859 {name: "PINSRW/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 860 {name: "PINSRW/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xe8, 0x0}}, 861 {name: "PINSRW/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xe8, 0x1}}, 862 {name: "PINSRW/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xe8, 0x1, 0x0}}, 863 {name: "PINSRW/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xe8, 0x1, 0x1}}, 864 {name: "PINSRW/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 865 {name: "PINSRW/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 866 {name: "PINSRW/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xf0, 0x0}}, 867 {name: "PINSRW/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xf0, 0x1}}, 868 {name: "PINSRW/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xf0, 0x1, 0x0}}, 869 {name: "PINSRW/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xf0, 0x1, 0x1}}, 870 {name: "PINSRW/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 871 {name: "PINSRW/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 872 {name: "PINSRD/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0x20, 0x0}}, 873 {name: "PINSRD/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0x20, 0x1}}, 874 {name: "PINSRD/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0x20, 0x1, 0x0}}, 875 {name: "PINSRD/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0x20, 0x1, 0x1}}, 876 {name: "PINSRD/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 877 {name: "PINSRD/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 878 {name: "PINSRD/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x0, 0x0}}, 879 {name: "PINSRD/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x0, 0x1}}, 880 {name: "PINSRD/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x0, 0x1, 0x0}}, 881 {name: "PINSRD/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x0, 0x1, 0x1}}, 882 {name: "PINSRD/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 883 {name: "PINSRD/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 884 {name: "PINSRD/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x28, 0x0}}, 885 {name: "PINSRD/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x28, 0x1}}, 886 {name: "PINSRD/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x28, 0x1, 0x0}}, 887 {name: "PINSRD/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x28, 0x1, 0x1}}, 888 {name: "PINSRD/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 889 {name: "PINSRD/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 890 {name: "PINSRD/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x30, 0x0}}, 891 {name: "PINSRD/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x30, 0x1}}, 892 {name: "PINSRD/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x30, 0x1, 0x0}}, 893 {name: "PINSRD/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x30, 0x1, 0x1}}, 894 {name: "PINSRD/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 895 {name: "PINSRD/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 896 {name: "PINSRD/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0x20, 0x0}}, 897 {name: "PINSRD/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0x20, 0x1}}, 898 {name: "PINSRD/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0x20, 0x1, 0x0}}, 899 {name: "PINSRD/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0x20, 0x1, 0x1}}, 900 {name: "PINSRD/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 901 {name: "PINSRD/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 902 {name: "PINSRD/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x0, 0x0}}, 903 {name: "PINSRD/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x0, 0x1}}, 904 {name: "PINSRD/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x0, 0x1, 0x0}}, 905 {name: "PINSRD/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x0, 0x1, 0x1}}, 906 {name: "PINSRD/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 907 {name: "PINSRD/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 908 {name: "PINSRD/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x28, 0x0}}, 909 {name: "PINSRD/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x28, 0x1}}, 910 {name: "PINSRD/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x28, 0x1, 0x0}}, 911 {name: "PINSRD/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x28, 0x1, 0x1}}, 912 {name: "PINSRD/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 913 {name: "PINSRD/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 914 {name: "PINSRD/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x30, 0x0}}, 915 {name: "PINSRD/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x30, 0x1}}, 916 {name: "PINSRD/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x30, 0x1, 0x0}}, 917 {name: "PINSRD/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x30, 0x1, 0x1}}, 918 {name: "PINSRD/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 919 {name: "PINSRD/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 920 {name: "PINSRD/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0x60, 0x0}}, 921 {name: "PINSRD/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0x60, 0x1}}, 922 {name: "PINSRD/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0x60, 0x1, 0x0}}, 923 {name: "PINSRD/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0x60, 0x1, 0x1}}, 924 {name: "PINSRD/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 925 {name: "PINSRD/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 926 {name: "PINSRD/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x40, 0x0}}, 927 {name: "PINSRD/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x40, 0x1}}, 928 {name: "PINSRD/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x40, 0x1, 0x0}}, 929 {name: "PINSRD/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x40, 0x1, 0x1}}, 930 {name: "PINSRD/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 931 {name: "PINSRD/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 932 {name: "PINSRD/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x68, 0x0}}, 933 {name: "PINSRD/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x68, 0x1}}, 934 {name: "PINSRD/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x68, 0x1, 0x0}}, 935 {name: "PINSRD/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x68, 0x1, 0x1}}, 936 {name: "PINSRD/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 937 {name: "PINSRD/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 938 {name: "PINSRD/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x70, 0x0}}, 939 {name: "PINSRD/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x70, 0x1}}, 940 {name: "PINSRD/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x70, 0x1, 0x0}}, 941 {name: "PINSRD/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x70, 0x1, 0x1}}, 942 {name: "PINSRD/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 943 {name: "PINSRD/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 944 {name: "PINSRD/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0x60, 0x0}}, 945 {name: "PINSRD/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0x60, 0x1}}, 946 {name: "PINSRD/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0x60, 0x1, 0x0}}, 947 {name: "PINSRD/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0x60, 0x1, 0x1}}, 948 {name: "PINSRD/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 949 {name: "PINSRD/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 950 {name: "PINSRD/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x40, 0x0}}, 951 {name: "PINSRD/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x40, 0x1}}, 952 {name: "PINSRD/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x40, 0x1, 0x0}}, 953 {name: "PINSRD/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x40, 0x1, 0x1}}, 954 {name: "PINSRD/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 955 {name: "PINSRD/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 956 {name: "PINSRD/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x68, 0x0}}, 957 {name: "PINSRD/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x68, 0x1}}, 958 {name: "PINSRD/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x68, 0x1, 0x0}}, 959 {name: "PINSRD/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x68, 0x1, 0x1}}, 960 {name: "PINSRD/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 961 {name: "PINSRD/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 962 {name: "PINSRD/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x70, 0x0}}, 963 {name: "PINSRD/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x70, 0x1}}, 964 {name: "PINSRD/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x70, 0x1, 0x0}}, 965 {name: "PINSRD/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x70, 0x1, 0x1}}, 966 {name: "PINSRD/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 967 {name: "PINSRD/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 968 {name: "PINSRD/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0xa0, 0x0}}, 969 {name: "PINSRD/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0xa0, 0x1}}, 970 {name: "PINSRD/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0xa0, 0x1, 0x0}}, 971 {name: "PINSRD/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0xa0, 0x1, 0x1}}, 972 {name: "PINSRD/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 973 {name: "PINSRD/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 974 {name: "PINSRD/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x80, 0x0}}, 975 {name: "PINSRD/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x80, 0x1}}, 976 {name: "PINSRD/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x80, 0x1, 0x0}}, 977 {name: "PINSRD/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x80, 0x1, 0x1}}, 978 {name: "PINSRD/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 979 {name: "PINSRD/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 980 {name: "PINSRD/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xa8, 0x0}}, 981 {name: "PINSRD/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xa8, 0x1}}, 982 {name: "PINSRD/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xa8, 0x1, 0x0}}, 983 {name: "PINSRD/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xa8, 0x1, 0x1}}, 984 {name: "PINSRD/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 985 {name: "PINSRD/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 986 {name: "PINSRD/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xb0, 0x0}}, 987 {name: "PINSRD/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xb0, 0x1}}, 988 {name: "PINSRD/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xb0, 0x1, 0x0}}, 989 {name: "PINSRD/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xb0, 0x1, 0x1}}, 990 {name: "PINSRD/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 991 {name: "PINSRD/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 992 {name: "PINSRD/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0xa0, 0x0}}, 993 {name: "PINSRD/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0xa0, 0x1}}, 994 {name: "PINSRD/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0xa0, 0x1, 0x0}}, 995 {name: "PINSRD/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0xa0, 0x1, 0x1}}, 996 {name: "PINSRD/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 997 {name: "PINSRD/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 998 {name: "PINSRD/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x80, 0x0}}, 999 {name: "PINSRD/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x80, 0x1}}, 1000 {name: "PINSRD/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x80, 0x1, 0x0}}, 1001 {name: "PINSRD/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x80, 0x1, 0x1}}, 1002 {name: "PINSRD/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1003 {name: "PINSRD/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1004 {name: "PINSRD/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xa8, 0x0}}, 1005 {name: "PINSRD/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xa8, 0x1}}, 1006 {name: "PINSRD/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xa8, 0x1, 0x0}}, 1007 {name: "PINSRD/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xa8, 0x1, 0x1}}, 1008 {name: "PINSRD/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1009 {name: "PINSRD/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1010 {name: "PINSRD/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xb0, 0x0}}, 1011 {name: "PINSRD/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xb0, 0x1}}, 1012 {name: "PINSRD/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xb0, 0x1, 0x0}}, 1013 {name: "PINSRD/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xb0, 0x1, 0x1}}, 1014 {name: "PINSRD/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1015 {name: "PINSRD/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1016 {name: "PINSRD/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0xe0, 0x0}}, 1017 {name: "PINSRD/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0xe0, 0x1}}, 1018 {name: "PINSRD/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0xe0, 0x1, 0x0}}, 1019 {name: "PINSRD/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0xe0, 0x1, 0x1}}, 1020 {name: "PINSRD/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1021 {name: "PINSRD/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1022 {name: "PINSRD/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xc0, 0x0}}, 1023 {name: "PINSRD/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xc0, 0x1}}, 1024 {name: "PINSRD/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xc0, 0x1, 0x0}}, 1025 {name: "PINSRD/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xc0, 0x1, 0x1}}, 1026 {name: "PINSRD/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1027 {name: "PINSRD/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1028 {name: "PINSRD/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xe8, 0x0}}, 1029 {name: "PINSRD/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xe8, 0x1}}, 1030 {name: "PINSRD/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xe8, 0x1, 0x0}}, 1031 {name: "PINSRD/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xe8, 0x1, 0x1}}, 1032 {name: "PINSRD/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1033 {name: "PINSRD/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1034 {name: "PINSRD/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xf0, 0x0}}, 1035 {name: "PINSRD/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xf0, 0x1}}, 1036 {name: "PINSRD/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xf0, 0x1, 0x0}}, 1037 {name: "PINSRD/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xf0, 0x1, 0x1}}, 1038 {name: "PINSRD/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1039 {name: "PINSRD/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1040 {name: "PINSRD/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0xe0, 0x0}}, 1041 {name: "PINSRD/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0xe0, 0x1}}, 1042 {name: "PINSRD/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0xe0, 0x1, 0x0}}, 1043 {name: "PINSRD/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0xe0, 0x1, 0x1}}, 1044 {name: "PINSRD/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1045 {name: "PINSRD/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1046 {name: "PINSRD/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xc0, 0x0}}, 1047 {name: "PINSRD/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xc0, 0x1}}, 1048 {name: "PINSRD/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xc0, 0x1, 0x0}}, 1049 {name: "PINSRD/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xc0, 0x1, 0x1}}, 1050 {name: "PINSRD/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1051 {name: "PINSRD/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1052 {name: "PINSRD/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xe8, 0x0}}, 1053 {name: "PINSRD/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xe8, 0x1}}, 1054 {name: "PINSRD/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xe8, 0x1, 0x0}}, 1055 {name: "PINSRD/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xe8, 0x1, 0x1}}, 1056 {name: "PINSRD/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1057 {name: "PINSRD/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1058 {name: "PINSRD/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xf0, 0x0}}, 1059 {name: "PINSRD/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xf0, 0x1}}, 1060 {name: "PINSRD/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xf0, 0x1, 0x0}}, 1061 {name: "PINSRD/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xf0, 0x1, 0x1}}, 1062 {name: "PINSRD/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1063 {name: "PINSRD/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1064 {name: "PINSRQ/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0x20, 0x0}}, 1065 {name: "PINSRQ/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0x20, 0x1}}, 1066 {name: "PINSRQ/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0x20, 0x1, 0x0}}, 1067 {name: "PINSRQ/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0x20, 0x1, 0x1}}, 1068 {name: "PINSRQ/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1069 {name: "PINSRQ/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1070 {name: "PINSRQ/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x0, 0x0}}, 1071 {name: "PINSRQ/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x0, 0x1}}, 1072 {name: "PINSRQ/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x0, 0x1, 0x0}}, 1073 {name: "PINSRQ/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x0, 0x1, 0x1}}, 1074 {name: "PINSRQ/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1075 {name: "PINSRQ/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1076 {name: "PINSRQ/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x28, 0x0}}, 1077 {name: "PINSRQ/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x28, 0x1}}, 1078 {name: "PINSRQ/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x28, 0x1, 0x0}}, 1079 {name: "PINSRQ/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x28, 0x1, 0x1}}, 1080 {name: "PINSRQ/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1081 {name: "PINSRQ/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1082 {name: "PINSRQ/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x30, 0x0}}, 1083 {name: "PINSRQ/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x30, 0x1}}, 1084 {name: "PINSRQ/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x30, 0x1, 0x0}}, 1085 {name: "PINSRQ/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x30, 0x1, 0x1}}, 1086 {name: "PINSRQ/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1087 {name: "PINSRQ/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1088 {name: "PINSRQ/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0x20, 0x0}}, 1089 {name: "PINSRQ/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0x20, 0x1}}, 1090 {name: "PINSRQ/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0x20, 0x1, 0x0}}, 1091 {name: "PINSRQ/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0x20, 0x1, 0x1}}, 1092 {name: "PINSRQ/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1093 {name: "PINSRQ/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1094 {name: "PINSRQ/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x0, 0x0}}, 1095 {name: "PINSRQ/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x0, 0x1}}, 1096 {name: "PINSRQ/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x0, 0x1, 0x0}}, 1097 {name: "PINSRQ/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x0, 0x1, 0x1}}, 1098 {name: "PINSRQ/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1099 {name: "PINSRQ/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1100 {name: "PINSRQ/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x28, 0x0}}, 1101 {name: "PINSRQ/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x28, 0x1}}, 1102 {name: "PINSRQ/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x28, 0x1, 0x0}}, 1103 {name: "PINSRQ/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x28, 0x1, 0x1}}, 1104 {name: "PINSRQ/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1105 {name: "PINSRQ/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1106 {name: "PINSRQ/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x30, 0x0}}, 1107 {name: "PINSRQ/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x30, 0x1}}, 1108 {name: "PINSRQ/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x30, 0x1, 0x0}}, 1109 {name: "PINSRQ/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x30, 0x1, 0x1}}, 1110 {name: "PINSRQ/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1111 {name: "PINSRQ/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1112 {name: "PINSRQ/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0x60, 0x0}}, 1113 {name: "PINSRQ/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0x60, 0x1}}, 1114 {name: "PINSRQ/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0x60, 0x1, 0x0}}, 1115 {name: "PINSRQ/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0x60, 0x1, 0x1}}, 1116 {name: "PINSRQ/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1117 {name: "PINSRQ/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1118 {name: "PINSRQ/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x40, 0x0}}, 1119 {name: "PINSRQ/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x40, 0x1}}, 1120 {name: "PINSRQ/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x40, 0x1, 0x0}}, 1121 {name: "PINSRQ/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x40, 0x1, 0x1}}, 1122 {name: "PINSRQ/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1123 {name: "PINSRQ/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1124 {name: "PINSRQ/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x68, 0x0}}, 1125 {name: "PINSRQ/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x68, 0x1}}, 1126 {name: "PINSRQ/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x68, 0x1, 0x0}}, 1127 {name: "PINSRQ/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x68, 0x1, 0x1}}, 1128 {name: "PINSRQ/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1129 {name: "PINSRQ/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1130 {name: "PINSRQ/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x70, 0x0}}, 1131 {name: "PINSRQ/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x70, 0x1}}, 1132 {name: "PINSRQ/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x70, 0x1, 0x0}}, 1133 {name: "PINSRQ/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x70, 0x1, 0x1}}, 1134 {name: "PINSRQ/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1135 {name: "PINSRQ/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1136 {name: "PINSRQ/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0x60, 0x0}}, 1137 {name: "PINSRQ/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0x60, 0x1}}, 1138 {name: "PINSRQ/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0x60, 0x1, 0x0}}, 1139 {name: "PINSRQ/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0x60, 0x1, 0x1}}, 1140 {name: "PINSRQ/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1141 {name: "PINSRQ/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1142 {name: "PINSRQ/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x40, 0x0}}, 1143 {name: "PINSRQ/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x40, 0x1}}, 1144 {name: "PINSRQ/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x40, 0x1, 0x0}}, 1145 {name: "PINSRQ/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x40, 0x1, 0x1}}, 1146 {name: "PINSRQ/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1147 {name: "PINSRQ/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1148 {name: "PINSRQ/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x68, 0x0}}, 1149 {name: "PINSRQ/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x68, 0x1}}, 1150 {name: "PINSRQ/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x68, 0x1, 0x0}}, 1151 {name: "PINSRQ/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x68, 0x1, 0x1}}, 1152 {name: "PINSRQ/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1153 {name: "PINSRQ/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1154 {name: "PINSRQ/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x70, 0x0}}, 1155 {name: "PINSRQ/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x70, 0x1}}, 1156 {name: "PINSRQ/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x70, 0x1, 0x0}}, 1157 {name: "PINSRQ/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x70, 0x1, 0x1}}, 1158 {name: "PINSRQ/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1159 {name: "PINSRQ/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1160 {name: "PINSRQ/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0xa0, 0x0}}, 1161 {name: "PINSRQ/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0xa0, 0x1}}, 1162 {name: "PINSRQ/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0xa0, 0x1, 0x0}}, 1163 {name: "PINSRQ/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0xa0, 0x1, 0x1}}, 1164 {name: "PINSRQ/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1165 {name: "PINSRQ/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1166 {name: "PINSRQ/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x80, 0x0}}, 1167 {name: "PINSRQ/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x80, 0x1}}, 1168 {name: "PINSRQ/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x80, 0x1, 0x0}}, 1169 {name: "PINSRQ/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x80, 0x1, 0x1}}, 1170 {name: "PINSRQ/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1171 {name: "PINSRQ/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1172 {name: "PINSRQ/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xa8, 0x0}}, 1173 {name: "PINSRQ/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xa8, 0x1}}, 1174 {name: "PINSRQ/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xa8, 0x1, 0x0}}, 1175 {name: "PINSRQ/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xa8, 0x1, 0x1}}, 1176 {name: "PINSRQ/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1177 {name: "PINSRQ/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1178 {name: "PINSRQ/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xb0, 0x0}}, 1179 {name: "PINSRQ/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xb0, 0x1}}, 1180 {name: "PINSRQ/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xb0, 0x1, 0x0}}, 1181 {name: "PINSRQ/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xb0, 0x1, 0x1}}, 1182 {name: "PINSRQ/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1183 {name: "PINSRQ/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1184 {name: "PINSRQ/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0xa0, 0x0}}, 1185 {name: "PINSRQ/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0xa0, 0x1}}, 1186 {name: "PINSRQ/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0xa0, 0x1, 0x0}}, 1187 {name: "PINSRQ/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0xa0, 0x1, 0x1}}, 1188 {name: "PINSRQ/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1189 {name: "PINSRQ/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1190 {name: "PINSRQ/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x80, 0x0}}, 1191 {name: "PINSRQ/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x80, 0x1}}, 1192 {name: "PINSRQ/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x80, 0x1, 0x0}}, 1193 {name: "PINSRQ/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x80, 0x1, 0x1}}, 1194 {name: "PINSRQ/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1195 {name: "PINSRQ/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1196 {name: "PINSRQ/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xa8, 0x0}}, 1197 {name: "PINSRQ/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xa8, 0x1}}, 1198 {name: "PINSRQ/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xa8, 0x1, 0x0}}, 1199 {name: "PINSRQ/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xa8, 0x1, 0x1}}, 1200 {name: "PINSRQ/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1201 {name: "PINSRQ/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1202 {name: "PINSRQ/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xb0, 0x0}}, 1203 {name: "PINSRQ/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xb0, 0x1}}, 1204 {name: "PINSRQ/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xb0, 0x1, 0x0}}, 1205 {name: "PINSRQ/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xb0, 0x1, 0x1}}, 1206 {name: "PINSRQ/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1207 {name: "PINSRQ/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1208 {name: "PINSRQ/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0xe0, 0x0}}, 1209 {name: "PINSRQ/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0xe0, 0x1}}, 1210 {name: "PINSRQ/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0xe0, 0x1, 0x0}}, 1211 {name: "PINSRQ/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0xe0, 0x1, 0x1}}, 1212 {name: "PINSRQ/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1213 {name: "PINSRQ/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1214 {name: "PINSRQ/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xc0, 0x0}}, 1215 {name: "PINSRQ/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xc0, 0x1}}, 1216 {name: "PINSRQ/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xc0, 0x1, 0x0}}, 1217 {name: "PINSRQ/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xc0, 0x1, 0x1}}, 1218 {name: "PINSRQ/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1219 {name: "PINSRQ/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1220 {name: "PINSRQ/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xe8, 0x0}}, 1221 {name: "PINSRQ/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xe8, 0x1}}, 1222 {name: "PINSRQ/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xe8, 0x1, 0x0}}, 1223 {name: "PINSRQ/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xe8, 0x1, 0x1}}, 1224 {name: "PINSRQ/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1225 {name: "PINSRQ/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1226 {name: "PINSRQ/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xf0, 0x0}}, 1227 {name: "PINSRQ/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xf0, 0x1}}, 1228 {name: "PINSRQ/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xf0, 0x1, 0x0}}, 1229 {name: "PINSRQ/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xf0, 0x1, 0x1}}, 1230 {name: "PINSRQ/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1231 {name: "PINSRQ/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1232 {name: "PINSRQ/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0xe0, 0x0}}, 1233 {name: "PINSRQ/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0xe0, 0x1}}, 1234 {name: "PINSRQ/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0xe0, 0x1, 0x0}}, 1235 {name: "PINSRQ/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0xe0, 0x1, 0x1}}, 1236 {name: "PINSRQ/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1237 {name: "PINSRQ/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1238 {name: "PINSRQ/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xc0, 0x0}}, 1239 {name: "PINSRQ/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xc0, 0x1}}, 1240 {name: "PINSRQ/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xc0, 0x1, 0x0}}, 1241 {name: "PINSRQ/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xc0, 0x1, 0x1}}, 1242 {name: "PINSRQ/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1243 {name: "PINSRQ/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1244 {name: "PINSRQ/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xe8, 0x0}}, 1245 {name: "PINSRQ/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xe8, 0x1}}, 1246 {name: "PINSRQ/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xe8, 0x1, 0x0}}, 1247 {name: "PINSRQ/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xe8, 0x1, 0x1}}, 1248 {name: "PINSRQ/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1249 {name: "PINSRQ/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1250 {name: "PINSRQ/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xf0, 0x0}}, 1251 {name: "PINSRQ/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xf0, 0x1}}, 1252 {name: "PINSRQ/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xf0, 0x1, 0x0}}, 1253 {name: "PINSRQ/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xf0, 0x1, 0x1}}, 1254 {name: "PINSRQ/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, 1255 {name: "PINSRQ/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, 1256 {name: "ADDL/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x3, 0x8}}, 1257 {name: "ADDL/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x3, 0xc, 0xb0}}, 1258 {name: "ADDL/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x3, 0x48, 0x1}}, 1259 {name: "ADDL/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x3, 0x4c, 0xb0, 0x1}}, 1260 {name: "ADDL/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x3, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1261 {name: "ADDL/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x3, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1262 {name: "ADDL/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0x3, 0xa}}, 1263 {name: "ADDL/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x3, 0xc, 0xb2}}, 1264 {name: "ADDL/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0x3, 0x4a, 0x1}}, 1265 {name: "ADDL/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x3, 0x4c, 0xb2, 0x1}}, 1266 {name: "ADDL/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0x3, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1267 {name: "ADDL/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x3, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1268 {name: "ADDQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x3, 0x8}}, 1269 {name: "ADDQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x3, 0xc, 0xb0}}, 1270 {name: "ADDQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x3, 0x48, 0x1}}, 1271 {name: "ADDQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x3, 0x4c, 0xb0, 0x1}}, 1272 {name: "ADDQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x3, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1273 {name: "ADDQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x3, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1274 {name: "ADDQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x3, 0xa}}, 1275 {name: "ADDQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x3, 0xc, 0xb2}}, 1276 {name: "ADDQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x3, 0x4a, 0x1}}, 1277 {name: "ADDQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x3, 0x4c, 0xb2, 0x1}}, 1278 {name: "ADDQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x3, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1279 {name: "ADDQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x3, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1280 {name: "CMPL/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x39, 0x8}}, 1281 {name: "CMPL/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x39, 0xc, 0xb0}}, 1282 {name: "CMPL/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x39, 0x48, 0x1}}, 1283 {name: "CMPL/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x39, 0x4c, 0xb0, 0x1}}, 1284 {name: "CMPL/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x39, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1285 {name: "CMPL/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x39, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1286 {name: "CMPL/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0x39, 0xa}}, 1287 {name: "CMPL/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x39, 0xc, 0xb2}}, 1288 {name: "CMPL/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0x39, 0x4a, 0x1}}, 1289 {name: "CMPL/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x39, 0x4c, 0xb2, 0x1}}, 1290 {name: "CMPL/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0x39, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1291 {name: "CMPL/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x39, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1292 {name: "CMPQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x39, 0x8}}, 1293 {name: "CMPQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x39, 0xc, 0xb0}}, 1294 {name: "CMPQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x39, 0x48, 0x1}}, 1295 {name: "CMPQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x39, 0x4c, 0xb0, 0x1}}, 1296 {name: "CMPQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x39, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1297 {name: "CMPQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x39, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1298 {name: "CMPQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x39, 0xa}}, 1299 {name: "CMPQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x39, 0xc, 0xb2}}, 1300 {name: "CMPQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x39, 0x4a, 0x1}}, 1301 {name: "CMPQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x39, 0x4c, 0xb2, 0x1}}, 1302 {name: "CMPQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x39, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1303 {name: "CMPQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x39, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1304 {name: "LEAQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x8d, 0x8}}, 1305 {name: "LEAQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8d, 0xc, 0xb0}}, 1306 {name: "LEAQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x8d, 0x48, 0x1}}, 1307 {name: "LEAQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8d, 0x4c, 0xb0, 0x1}}, 1308 {name: "LEAQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x8d, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1309 {name: "LEAQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8d, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1310 {name: "LEAQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x8d, 0xa}}, 1311 {name: "LEAQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8d, 0xc, 0xb2}}, 1312 {name: "LEAQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x8d, 0x4a, 0x1}}, 1313 {name: "LEAQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8d, 0x4c, 0xb2, 0x1}}, 1314 {name: "LEAQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x8d, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1315 {name: "LEAQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8d, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1316 {name: "MOVBLSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0xf, 0xbe, 0x8}}, 1317 {name: "MOVBLSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbe, 0xc, 0xb0}}, 1318 {name: "MOVBLSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0xf, 0xbe, 0x48, 0x1}}, 1319 {name: "MOVBLSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbe, 0x4c, 0xb0, 0x1}}, 1320 {name: "MOVBLSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0xf, 0xbe, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1321 {name: "MOVBLSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbe, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1322 {name: "MOVBLSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbe, 0xa}}, 1323 {name: "MOVBLSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbe, 0xc, 0xb2}}, 1324 {name: "MOVBLSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbe, 0x4a, 0x1}}, 1325 {name: "MOVBLSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbe, 0x4c, 0xb2, 0x1}}, 1326 {name: "MOVBLSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbe, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1327 {name: "MOVBLSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbe, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1328 {name: "MOVBLZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0xf, 0xb6, 0x8}}, 1329 {name: "MOVBLZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb6, 0xc, 0xb0}}, 1330 {name: "MOVBLZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0xf, 0xb6, 0x48, 0x1}}, 1331 {name: "MOVBLZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb6, 0x4c, 0xb0, 0x1}}, 1332 {name: "MOVBLZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0xf, 0xb6, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1333 {name: "MOVBLZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb6, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1334 {name: "MOVBLZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb6, 0xa}}, 1335 {name: "MOVBLZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb6, 0xc, 0xb2}}, 1336 {name: "MOVBLZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb6, 0x4a, 0x1}}, 1337 {name: "MOVBLZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb6, 0x4c, 0xb2, 0x1}}, 1338 {name: "MOVBLZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb6, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1339 {name: "MOVBLZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb6, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1340 {name: "MOVBQSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbe, 0x8}}, 1341 {name: "MOVBQSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbe, 0xc, 0xb0}}, 1342 {name: "MOVBQSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbe, 0x48, 0x1}}, 1343 {name: "MOVBQSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbe, 0x4c, 0xb0, 0x1}}, 1344 {name: "MOVBQSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbe, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1345 {name: "MOVBQSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbe, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1346 {name: "MOVBQSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbe, 0xa}}, 1347 {name: "MOVBQSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbe, 0xc, 0xb2}}, 1348 {name: "MOVBQSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbe, 0x4a, 0x1}}, 1349 {name: "MOVBQSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbe, 0x4c, 0xb2, 0x1}}, 1350 {name: "MOVBQSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbe, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1351 {name: "MOVBQSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbe, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1352 {name: "MOVBQZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb6, 0x8}}, 1353 {name: "MOVBQZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb6, 0xc, 0xb0}}, 1354 {name: "MOVBQZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb6, 0x48, 0x1}}, 1355 {name: "MOVBQZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb6, 0x4c, 0xb0, 0x1}}, 1356 {name: "MOVBQZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb6, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1357 {name: "MOVBQZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb6, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1358 {name: "MOVBQZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb6, 0xa}}, 1359 {name: "MOVBQZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb6, 0xc, 0xb2}}, 1360 {name: "MOVBQZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb6, 0x4a, 0x1}}, 1361 {name: "MOVBQZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb6, 0x4c, 0xb2, 0x1}}, 1362 {name: "MOVBQZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb6, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1363 {name: "MOVBQZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb6, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1364 {name: "MOVLQSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x63, 0x8}}, 1365 {name: "MOVLQSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x63, 0xc, 0xb0}}, 1366 {name: "MOVLQSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x63, 0x48, 0x1}}, 1367 {name: "MOVLQSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x63, 0x4c, 0xb0, 0x1}}, 1368 {name: "MOVLQSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x63, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1369 {name: "MOVLQSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x63, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1370 {name: "MOVLQSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x63, 0xa}}, 1371 {name: "MOVLQSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x63, 0xc, 0xb2}}, 1372 {name: "MOVLQSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x63, 0x4a, 0x1}}, 1373 {name: "MOVLQSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x63, 0x4c, 0xb2, 0x1}}, 1374 {name: "MOVLQSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x63, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1375 {name: "MOVLQSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x63, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1376 {name: "MOVLQZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x8b, 0x8}}, 1377 {name: "MOVLQZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0xc, 0xb0}}, 1378 {name: "MOVLQZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x8b, 0x48, 0x1}}, 1379 {name: "MOVLQZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0x4c, 0xb0, 0x1}}, 1380 {name: "MOVLQZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x8b, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1381 {name: "MOVLQZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1382 {name: "MOVLQZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0xa}}, 1383 {name: "MOVLQZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0xc, 0xb2}}, 1384 {name: "MOVLQZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0x4a, 0x1}}, 1385 {name: "MOVLQZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0x4c, 0xb2, 0x1}}, 1386 {name: "MOVLQZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1387 {name: "MOVLQZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1388 {name: "MOVL/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x8b, 0x8}}, 1389 {name: "MOVL/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0xc, 0xb0}}, 1390 {name: "MOVL/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x8b, 0x48, 0x1}}, 1391 {name: "MOVL/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0x4c, 0xb0, 0x1}}, 1392 {name: "MOVL/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x8b, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1393 {name: "MOVL/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1394 {name: "MOVL/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x6e, 0x18}}, 1395 {name: "MOVL/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x6e, 0x1c, 0xb0}}, 1396 {name: "MOVL/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x6e, 0x58, 0x1}}, 1397 {name: "MOVL/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x6e, 0x5c, 0xb0, 0x1}}, 1398 {name: "MOVL/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x6e, 0x98, 0xff, 0xff, 0xff, 0x7f}}, 1399 {name: "MOVL/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x6e, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1400 {name: "MOVL/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0xa}}, 1401 {name: "MOVL/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0xc, 0xb2}}, 1402 {name: "MOVL/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0x4a, 0x1}}, 1403 {name: "MOVL/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0x4c, 0xb2, 0x1}}, 1404 {name: "MOVL/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1405 {name: "MOVL/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1406 {name: "MOVL/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x6e, 0x1a}}, 1407 {name: "MOVL/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x6e, 0x1c, 0xb2}}, 1408 {name: "MOVL/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x6e, 0x5a, 0x1}}, 1409 {name: "MOVL/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x6e, 0x5c, 0xb2, 0x1}}, 1410 {name: "MOVL/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x6e, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, 1411 {name: "MOVL/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x6e, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1412 {name: "MOVQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x8b, 0x8}}, 1413 {name: "MOVQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8b, 0xc, 0xb0}}, 1414 {name: "MOVQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x8b, 0x48, 0x1}}, 1415 {name: "MOVQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8b, 0x4c, 0xb0, 0x1}}, 1416 {name: "MOVQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x8b, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1417 {name: "MOVQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8b, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1418 {name: "MOVQ/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x7e, 0x18}}, 1419 {name: "MOVQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x7e, 0x1c, 0xb0}}, 1420 {name: "MOVQ/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x7e, 0x58, 0x1}}, 1421 {name: "MOVQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x7e, 0x5c, 0xb0, 0x1}}, 1422 {name: "MOVQ/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x7e, 0x98, 0xff, 0xff, 0xff, 0x7f}}, 1423 {name: "MOVQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x7e, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1424 {name: "MOVQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x8b, 0xa}}, 1425 {name: "MOVQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8b, 0xc, 0xb2}}, 1426 {name: "MOVQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x8b, 0x4a, 0x1}}, 1427 {name: "MOVQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8b, 0x4c, 0xb2, 0x1}}, 1428 {name: "MOVQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x8b, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1429 {name: "MOVQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8b, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1430 {name: "MOVQ/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x7e, 0x1a}}, 1431 {name: "MOVQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x7e, 0x1c, 0xb2}}, 1432 {name: "MOVQ/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x7e, 0x5a, 0x1}}, 1433 {name: "MOVQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x7e, 0x5c, 0xb2, 0x1}}, 1434 {name: "MOVQ/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x7e, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, 1435 {name: "MOVQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x7e, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1436 {name: "MOVWLSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0xf, 0xbf, 0x8}}, 1437 {name: "MOVWLSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbf, 0xc, 0xb0}}, 1438 {name: "MOVWLSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0xf, 0xbf, 0x48, 0x1}}, 1439 {name: "MOVWLSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbf, 0x4c, 0xb0, 0x1}}, 1440 {name: "MOVWLSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0xf, 0xbf, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1441 {name: "MOVWLSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbf, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1442 {name: "MOVWLSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbf, 0xa}}, 1443 {name: "MOVWLSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbf, 0xc, 0xb2}}, 1444 {name: "MOVWLSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbf, 0x4a, 0x1}}, 1445 {name: "MOVWLSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbf, 0x4c, 0xb2, 0x1}}, 1446 {name: "MOVWLSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbf, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1447 {name: "MOVWLSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbf, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1448 {name: "MOVWLZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0xf, 0xb7, 0x8}}, 1449 {name: "MOVWLZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb7, 0xc, 0xb0}}, 1450 {name: "MOVWLZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0xf, 0xb7, 0x48, 0x1}}, 1451 {name: "MOVWLZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb7, 0x4c, 0xb0, 0x1}}, 1452 {name: "MOVWLZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0xf, 0xb7, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1453 {name: "MOVWLZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb7, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1454 {name: "MOVWLZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb7, 0xa}}, 1455 {name: "MOVWLZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb7, 0xc, 0xb2}}, 1456 {name: "MOVWLZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb7, 0x4a, 0x1}}, 1457 {name: "MOVWLZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb7, 0x4c, 0xb2, 0x1}}, 1458 {name: "MOVWLZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb7, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1459 {name: "MOVWLZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb7, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1460 {name: "MOVWQSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbf, 0x8}}, 1461 {name: "MOVWQSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbf, 0xc, 0xb0}}, 1462 {name: "MOVWQSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbf, 0x48, 0x1}}, 1463 {name: "MOVWQSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbf, 0x4c, 0xb0, 0x1}}, 1464 {name: "MOVWQSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbf, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1465 {name: "MOVWQSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbf, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1466 {name: "MOVWQSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbf, 0xa}}, 1467 {name: "MOVWQSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbf, 0xc, 0xb2}}, 1468 {name: "MOVWQSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbf, 0x4a, 0x1}}, 1469 {name: "MOVWQSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbf, 0x4c, 0xb2, 0x1}}, 1470 {name: "MOVWQSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbf, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1471 {name: "MOVWQSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbf, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1472 {name: "MOVWQZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb7, 0x8}}, 1473 {name: "MOVWQZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb7, 0xc, 0xb0}}, 1474 {name: "MOVWQZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb7, 0x48, 0x1}}, 1475 {name: "MOVWQZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb7, 0x4c, 0xb0, 0x1}}, 1476 {name: "MOVWQZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb7, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1477 {name: "MOVWQZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb7, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1478 {name: "MOVWQZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb7, 0xa}}, 1479 {name: "MOVWQZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb7, 0xc, 0xb2}}, 1480 {name: "MOVWQZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb7, 0x4a, 0x1}}, 1481 {name: "MOVWQZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb7, 0x4c, 0xb2, 0x1}}, 1482 {name: "MOVWQZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb7, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1483 {name: "MOVWQZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb7, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1484 {name: "SUBQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x2b, 0x8}}, 1485 {name: "SUBQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x2b, 0xc, 0xb0}}, 1486 {name: "SUBQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x2b, 0x48, 0x1}}, 1487 {name: "SUBQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x2b, 0x4c, 0xb0, 0x1}}, 1488 {name: "SUBQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x2b, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 1489 {name: "SUBQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x2b, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1490 {name: "SUBQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x2b, 0xa}}, 1491 {name: "SUBQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x2b, 0xc, 0xb2}}, 1492 {name: "SUBQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x2b, 0x4a, 0x1}}, 1493 {name: "SUBQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x2b, 0x4c, 0xb2, 0x1}}, 1494 {name: "SUBQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x2b, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, 1495 {name: "SUBQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x2b, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1496 {name: "SUBSD/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf2, 0xf, 0x5c, 0x18}}, 1497 {name: "SUBSD/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x42, 0xf, 0x5c, 0x1c, 0xb0}}, 1498 {name: "SUBSD/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf2, 0xf, 0x5c, 0x58, 0x1}}, 1499 {name: "SUBSD/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x42, 0xf, 0x5c, 0x5c, 0xb0, 0x1}}, 1500 {name: "SUBSD/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf2, 0xf, 0x5c, 0x98, 0xff, 0xff, 0xff, 0x7f}}, 1501 {name: "SUBSD/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x42, 0xf, 0x5c, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1502 {name: "SUBSD/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf2, 0x41, 0xf, 0x5c, 0x1a}}, 1503 {name: "SUBSD/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x43, 0xf, 0x5c, 0x1c, 0xb2}}, 1504 {name: "SUBSD/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf2, 0x41, 0xf, 0x5c, 0x5a, 0x1}}, 1505 {name: "SUBSD/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x43, 0xf, 0x5c, 0x5c, 0xb2, 0x1}}, 1506 {name: "SUBSD/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf2, 0x41, 0xf, 0x5c, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, 1507 {name: "SUBSD/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x43, 0xf, 0x5c, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1508 {name: "SUBSS/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x5c, 0x18}}, 1509 {name: "SUBSS/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x5c, 0x1c, 0xb0}}, 1510 {name: "SUBSS/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x5c, 0x58, 0x1}}, 1511 {name: "SUBSS/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x5c, 0x5c, 0xb0, 0x1}}, 1512 {name: "SUBSS/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x5c, 0x98, 0xff, 0xff, 0xff, 0x7f}}, 1513 {name: "SUBSS/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x5c, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1514 {name: "SUBSS/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x5c, 0x1a}}, 1515 {name: "SUBSS/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x5c, 0x1c, 0xb2}}, 1516 {name: "SUBSS/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x5c, 0x5a, 0x1}}, 1517 {name: "SUBSS/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x5c, 0x5c, 0xb2, 0x1}}, 1518 {name: "SUBSS/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x5c, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, 1519 {name: "SUBSS/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x5c, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1520 {name: "UCOMISD/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x2e, 0x18}}, 1521 {name: "UCOMISD/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x2e, 0x1c, 0xb0}}, 1522 {name: "UCOMISD/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x2e, 0x58, 0x1}}, 1523 {name: "UCOMISD/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x2e, 0x5c, 0xb0, 0x1}}, 1524 {name: "UCOMISD/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x2e, 0x98, 0xff, 0xff, 0xff, 0x7f}}, 1525 {name: "UCOMISD/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x2e, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1526 {name: "UCOMISD/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x2e, 0x1a}}, 1527 {name: "UCOMISD/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x2e, 0x1c, 0xb2}}, 1528 {name: "UCOMISD/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x2e, 0x5a, 0x1}}, 1529 {name: "UCOMISD/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x2e, 0x5c, 0xb2, 0x1}}, 1530 {name: "UCOMISD/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x2e, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, 1531 {name: "UCOMISD/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x2e, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1532 {name: "UCOMISS/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf, 0x2e, 0x18}}, 1533 {name: "UCOMISS/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x42, 0xf, 0x2e, 0x1c, 0xb0}}, 1534 {name: "UCOMISS/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf, 0x2e, 0x58, 0x1}}, 1535 {name: "UCOMISS/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x42, 0xf, 0x2e, 0x5c, 0xb0, 0x1}}, 1536 {name: "UCOMISS/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf, 0x2e, 0x98, 0xff, 0xff, 0xff, 0x7f}}, 1537 {name: "UCOMISS/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x42, 0xf, 0x2e, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1538 {name: "UCOMISS/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x41, 0xf, 0x2e, 0x1a}}, 1539 {name: "UCOMISS/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x43, 0xf, 0x2e, 0x1c, 0xb2}}, 1540 {name: "UCOMISS/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x41, 0xf, 0x2e, 0x5a, 0x1}}, 1541 {name: "UCOMISS/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x43, 0xf, 0x2e, 0x5c, 0xb2, 0x1}}, 1542 {name: "UCOMISS/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x41, 0xf, 0x2e, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, 1543 {name: "UCOMISS/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x43, 0xf, 0x2e, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1544 {name: "PMOVSXBW/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x20, 0x18}}, 1545 {name: "PMOVSXBW/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x20, 0x1c, 0xb0}}, 1546 {name: "PMOVSXBW/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x20, 0x58, 0x1}}, 1547 {name: "PMOVSXBW/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x20, 0x5c, 0xb0, 0x1}}, 1548 {name: "PMOVSXBW/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x20, 0x98, 0xff, 0xff, 0xff, 0x7f}}, 1549 {name: "PMOVSXBW/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x20, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1550 {name: "PMOVSXBW/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x20, 0x1a}}, 1551 {name: "PMOVSXBW/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x20, 0x1c, 0xb2}}, 1552 {name: "PMOVSXBW/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x20, 0x5a, 0x1}}, 1553 {name: "PMOVSXBW/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x20, 0x5c, 0xb2, 0x1}}, 1554 {name: "PMOVSXBW/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x20, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, 1555 {name: "PMOVSXBW/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x20, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1556 {name: "PMOVSXWD/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x23, 0x18}}, 1557 {name: "PMOVSXWD/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x23, 0x1c, 0xb0}}, 1558 {name: "PMOVSXWD/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x23, 0x58, 0x1}}, 1559 {name: "PMOVSXWD/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x23, 0x5c, 0xb0, 0x1}}, 1560 {name: "PMOVSXWD/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x23, 0x98, 0xff, 0xff, 0xff, 0x7f}}, 1561 {name: "PMOVSXWD/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x23, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1562 {name: "PMOVSXWD/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x23, 0x1a}}, 1563 {name: "PMOVSXWD/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x23, 0x1c, 0xb2}}, 1564 {name: "PMOVSXWD/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x23, 0x5a, 0x1}}, 1565 {name: "PMOVSXWD/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x23, 0x5c, 0xb2, 0x1}}, 1566 {name: "PMOVSXWD/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x23, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, 1567 {name: "PMOVSXWD/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x23, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1568 {name: "PMOVSXDQ/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x25, 0x18}}, 1569 {name: "PMOVSXDQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x25, 0x1c, 0xb0}}, 1570 {name: "PMOVSXDQ/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x25, 0x58, 0x1}}, 1571 {name: "PMOVSXDQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x25, 0x5c, 0xb0, 0x1}}, 1572 {name: "PMOVSXDQ/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x25, 0x98, 0xff, 0xff, 0xff, 0x7f}}, 1573 {name: "PMOVSXDQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x25, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1574 {name: "PMOVSXDQ/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x25, 0x1a}}, 1575 {name: "PMOVSXDQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x25, 0x1c, 0xb2}}, 1576 {name: "PMOVSXDQ/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x25, 0x5a, 0x1}}, 1577 {name: "PMOVSXDQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x25, 0x5c, 0xb2, 0x1}}, 1578 {name: "PMOVSXDQ/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x25, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, 1579 {name: "PMOVSXDQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x25, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1580 {name: "PMOVZXBW/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x30, 0x18}}, 1581 {name: "PMOVZXBW/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x30, 0x1c, 0xb0}}, 1582 {name: "PMOVZXBW/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x30, 0x58, 0x1}}, 1583 {name: "PMOVZXBW/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x30, 0x5c, 0xb0, 0x1}}, 1584 {name: "PMOVZXBW/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x30, 0x98, 0xff, 0xff, 0xff, 0x7f}}, 1585 {name: "PMOVZXBW/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x30, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1586 {name: "PMOVZXBW/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x30, 0x1a}}, 1587 {name: "PMOVZXBW/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x30, 0x1c, 0xb2}}, 1588 {name: "PMOVZXBW/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x30, 0x5a, 0x1}}, 1589 {name: "PMOVZXBW/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x30, 0x5c, 0xb2, 0x1}}, 1590 {name: "PMOVZXBW/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x30, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, 1591 {name: "PMOVZXBW/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x30, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1592 {name: "PMOVZXWD/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x33, 0x18}}, 1593 {name: "PMOVZXWD/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x33, 0x1c, 0xb0}}, 1594 {name: "PMOVZXWD/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x33, 0x58, 0x1}}, 1595 {name: "PMOVZXWD/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x33, 0x5c, 0xb0, 0x1}}, 1596 {name: "PMOVZXWD/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x33, 0x98, 0xff, 0xff, 0xff, 0x7f}}, 1597 {name: "PMOVZXWD/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x33, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1598 {name: "PMOVZXWD/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x33, 0x1a}}, 1599 {name: "PMOVZXWD/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x33, 0x1c, 0xb2}}, 1600 {name: "PMOVZXWD/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x33, 0x5a, 0x1}}, 1601 {name: "PMOVZXWD/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x33, 0x5c, 0xb2, 0x1}}, 1602 {name: "PMOVZXWD/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x33, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, 1603 {name: "PMOVZXWD/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x33, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1604 {name: "PMOVZXDQ/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x35, 0x18}}, 1605 {name: "PMOVZXDQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x35, 0x1c, 0xb0}}, 1606 {name: "PMOVZXDQ/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x35, 0x58, 0x1}}, 1607 {name: "PMOVZXDQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x35, 0x5c, 0xb0, 0x1}}, 1608 {name: "PMOVZXDQ/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x35, 0x98, 0xff, 0xff, 0xff, 0x7f}}, 1609 {name: "PMOVZXDQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x35, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, 1610 {name: "PMOVZXDQ/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x35, 0x1a}}, 1611 {name: "PMOVZXDQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x35, 0x1c, 0xb2}}, 1612 {name: "PMOVZXDQ/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x35, 0x5a, 0x1}}, 1613 {name: "PMOVZXDQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x35, 0x5c, 0xb2, 0x1}}, 1614 {name: "PMOVZXDQ/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x35, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, 1615 {name: "PMOVZXDQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x35, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, 1616 } 1617 1618 for _, tc := range tests { 1619 tc.n.types = operandTypesMemoryToRegister 1620 a := NewAssembler() 1621 err := a.encodeMemoryToRegister(tc.n) 1622 require.NoError(t, err, tc.name) 1623 1624 actual, err := a.Assemble() 1625 require.NoError(t, err, tc.name) 1626 require.Equal(t, tc.exp, actual, tc.name) 1627 } 1628 } 1629 1630 func TestAssemblerImpl_EncodeConstToRegister(t *testing.T) { 1631 tests := []struct { 1632 name string 1633 n *nodeImpl 1634 exp []byte 1635 }{ 1636 { 1637 name: "psraw xmm10, 1", 1638 n: &nodeImpl{instruction: PSRAW, types: operandTypesRegisterToRegister, srcConst: 1, dstReg: RegX10}, 1639 exp: []byte{0x66, 0x41, 0xf, 0x71, 0xe2, 0x1}, 1640 }, 1641 { 1642 name: "psraw xmm10, 8", 1643 n: &nodeImpl{instruction: PSRAW, types: operandTypesRegisterToRegister, srcConst: 8, dstReg: RegX10}, 1644 exp: []byte{0x66, 0x41, 0xf, 0x71, 0xe2, 0x8}, 1645 }, 1646 { 1647 name: "psrlw xmm10, 1", 1648 n: &nodeImpl{instruction: PSRLW, types: operandTypesRegisterToRegister, srcConst: 1, dstReg: RegX10}, 1649 exp: []byte{0x66, 0x41, 0xf, 0x71, 0xd2, 0x1}, 1650 }, 1651 { 1652 name: "psrlw xmm10, 8", 1653 n: &nodeImpl{instruction: PSRLW, types: operandTypesRegisterToRegister, srcConst: 8, dstReg: RegX10}, 1654 exp: []byte{0x66, 0x41, 0xf, 0x71, 0xd2, 0x8}, 1655 }, 1656 { 1657 name: "psllw xmm10, 1", 1658 n: &nodeImpl{instruction: PSLLW, types: operandTypesRegisterToRegister, srcConst: 1, dstReg: RegX10}, 1659 exp: []byte{0x66, 0x41, 0xf, 0x71, 0xf2, 0x1}, 1660 }, 1661 { 1662 name: "psllw xmm10, 8", 1663 n: &nodeImpl{instruction: PSLLW, types: operandTypesRegisterToRegister, srcConst: 8, dstReg: RegX10}, 1664 exp: []byte{0x66, 0x41, 0xf, 0x71, 0xf2, 0x8}, 1665 }, 1666 { 1667 name: "psrad xmm10, 0x1f", 1668 n: &nodeImpl{instruction: PSRAD, types: operandTypesRegisterToRegister, srcConst: 0x1f, dstReg: RegX10}, 1669 exp: []byte{0x66, 0x41, 0xf, 0x72, 0xe2, 0x1f}, 1670 }, 1671 } 1672 1673 for _, tt := range tests { 1674 tc := tt 1675 a := NewAssembler() 1676 err := a.encodeConstToRegister(tc.n) 1677 require.NoError(t, err, tc.name) 1678 1679 actual, err := a.Assemble() 1680 require.NoError(t, err, tc.name) 1681 require.Equal(t, tc.exp, actual, tc.name) 1682 } 1683 }