wa-lang.org/wazero@v1.0.2/internal/asm/amd64/impl_2_test.go (about) 1 package amd64 2 3 import ( 4 "testing" 5 6 "wa-lang.org/wazero/internal/asm" 7 "wa-lang.org/wazero/internal/testing/require" 8 ) 9 10 /* 11 12 var cs []string 13 cs = append(cs, fmt.Sprintf( 14 `{name: "%s", inst: %s, dst: Reg%s, exp: %#v}`, 15 fmt.Sprintf("inst=%s/reg=%s", InstructionName(inst), RegisterName(reg)), 16 InstructionName(inst), RegisterName(reg), 17 a.buf.Bytes(), 18 )) 19 fmt.Println(strings.Join(cs, ",\n")) 20 */ 21 22 func TestAssemblerImpl_EncodeNoneToRegister(t *testing.T) { 23 t.Run("error", func(t *testing.T) { 24 a := NewAssembler() 25 err := a.encodeNoneToRegister(&nodeImpl{ 26 instruction: ADDL, 27 types: operandTypesNoneToRegister, dstReg: RegAX, 28 }) 29 require.Error(t, err) 30 31 t.Run("error", func(t *testing.T) { 32 tests := []struct { 33 n *nodeImpl 34 expErr string 35 }{ 36 { 37 n: &nodeImpl{instruction: ADDL, types: operandTypesNoneToRegister, dstReg: RegAX}, 38 expErr: "ADDL is unsupported for from:none,to:register type", 39 }, 40 { 41 n: &nodeImpl{instruction: JMP, types: operandTypesNoneToRegister}, 42 expErr: "invalid register [nil]", 43 }, 44 } 45 46 for _, tt := range tests { 47 a := NewAssembler() 48 err := a.encodeNoneToRegister(tt.n) 49 require.EqualError(t, err, tt.expErr, tt.expErr) 50 } 51 }) 52 }) 53 54 tests := []struct { 55 name string 56 inst asm.Instruction 57 dst asm.Register 58 exp []byte 59 }{ 60 {name: "inst=JMP/reg=AX", inst: JMP, dst: RegAX, exp: []byte{0xff, 0xe0}}, 61 {name: "inst=JMP/reg=BX", inst: JMP, dst: RegBX, exp: []byte{0xff, 0xe3}}, 62 {name: "inst=JMP/reg=SP", inst: JMP, dst: RegSP, exp: []byte{0xff, 0xe4}}, 63 {name: "inst=JMP/reg=BP", inst: JMP, dst: RegBP, exp: []byte{0xff, 0xe5}}, 64 {name: "inst=JMP/reg=SI", inst: JMP, dst: RegSI, exp: []byte{0xff, 0xe6}}, 65 {name: "inst=JMP/reg=DI", inst: JMP, dst: RegDI, exp: []byte{0xff, 0xe7}}, 66 {name: "inst=JMP/reg=R8", inst: JMP, dst: RegR8, exp: []byte{0x41, 0xff, 0xe0}}, 67 {name: "inst=JMP/reg=R9", inst: JMP, dst: RegR9, exp: []byte{0x41, 0xff, 0xe1}}, 68 {name: "inst=JMP/reg=R13", inst: JMP, dst: RegR13, exp: []byte{0x41, 0xff, 0xe5}}, 69 {name: "inst=JMP/reg=R14", inst: JMP, dst: RegR14, exp: []byte{0x41, 0xff, 0xe6}}, 70 {name: "inst=JMP/reg=R15", inst: JMP, dst: RegR15, exp: []byte{0x41, 0xff, 0xe7}}, 71 {name: "inst=SETCC/reg=AX", inst: SETCC, dst: RegAX, exp: []byte{0xf, 0x93, 0xc0}}, 72 {name: "inst=SETCC/reg=BX", inst: SETCC, dst: RegBX, exp: []byte{0xf, 0x93, 0xc3}}, 73 {name: "inst=SETCC/reg=SP", inst: SETCC, dst: RegSP, exp: []byte{0x40, 0xf, 0x93, 0xc4}}, 74 {name: "inst=SETCC/reg=BP", inst: SETCC, dst: RegBP, exp: []byte{0x40, 0xf, 0x93, 0xc5}}, 75 {name: "inst=SETCC/reg=SI", inst: SETCC, dst: RegSI, exp: []byte{0x40, 0xf, 0x93, 0xc6}}, 76 {name: "inst=SETCC/reg=DI", inst: SETCC, dst: RegDI, exp: []byte{0x40, 0xf, 0x93, 0xc7}}, 77 {name: "inst=SETCC/reg=R8", inst: SETCC, dst: RegR8, exp: []byte{0x41, 0xf, 0x93, 0xc0}}, 78 {name: "inst=SETCC/reg=R9", inst: SETCC, dst: RegR9, exp: []byte{0x41, 0xf, 0x93, 0xc1}}, 79 {name: "inst=SETCC/reg=R13", inst: SETCC, dst: RegR13, exp: []byte{0x41, 0xf, 0x93, 0xc5}}, 80 {name: "inst=SETCC/reg=R14", inst: SETCC, dst: RegR14, exp: []byte{0x41, 0xf, 0x93, 0xc6}}, 81 {name: "inst=SETCC/reg=R15", inst: SETCC, dst: RegR15, exp: []byte{0x41, 0xf, 0x93, 0xc7}}, 82 {name: "inst=SETCS/reg=AX", inst: SETCS, dst: RegAX, exp: []byte{0xf, 0x92, 0xc0}}, 83 {name: "inst=SETCS/reg=BX", inst: SETCS, dst: RegBX, exp: []byte{0xf, 0x92, 0xc3}}, 84 {name: "inst=SETCS/reg=SP", inst: SETCS, dst: RegSP, exp: []byte{0x40, 0xf, 0x92, 0xc4}}, 85 {name: "inst=SETCS/reg=BP", inst: SETCS, dst: RegBP, exp: []byte{0x40, 0xf, 0x92, 0xc5}}, 86 {name: "inst=SETCS/reg=SI", inst: SETCS, dst: RegSI, exp: []byte{0x40, 0xf, 0x92, 0xc6}}, 87 {name: "inst=SETCS/reg=DI", inst: SETCS, dst: RegDI, exp: []byte{0x40, 0xf, 0x92, 0xc7}}, 88 {name: "inst=SETCS/reg=R8", inst: SETCS, dst: RegR8, exp: []byte{0x41, 0xf, 0x92, 0xc0}}, 89 {name: "inst=SETCS/reg=R9", inst: SETCS, dst: RegR9, exp: []byte{0x41, 0xf, 0x92, 0xc1}}, 90 {name: "inst=SETCS/reg=R13", inst: SETCS, dst: RegR13, exp: []byte{0x41, 0xf, 0x92, 0xc5}}, 91 {name: "inst=SETCS/reg=R14", inst: SETCS, dst: RegR14, exp: []byte{0x41, 0xf, 0x92, 0xc6}}, 92 {name: "inst=SETCS/reg=R15", inst: SETCS, dst: RegR15, exp: []byte{0x41, 0xf, 0x92, 0xc7}}, 93 {name: "inst=SETEQ/reg=AX", inst: SETEQ, dst: RegAX, exp: []byte{0xf, 0x94, 0xc0}}, 94 {name: "inst=SETEQ/reg=BX", inst: SETEQ, dst: RegBX, exp: []byte{0xf, 0x94, 0xc3}}, 95 {name: "inst=SETEQ/reg=SP", inst: SETEQ, dst: RegSP, exp: []byte{0x40, 0xf, 0x94, 0xc4}}, 96 {name: "inst=SETEQ/reg=BP", inst: SETEQ, dst: RegBP, exp: []byte{0x40, 0xf, 0x94, 0xc5}}, 97 {name: "inst=SETEQ/reg=SI", inst: SETEQ, dst: RegSI, exp: []byte{0x40, 0xf, 0x94, 0xc6}}, 98 {name: "inst=SETEQ/reg=DI", inst: SETEQ, dst: RegDI, exp: []byte{0x40, 0xf, 0x94, 0xc7}}, 99 {name: "inst=SETEQ/reg=R8", inst: SETEQ, dst: RegR8, exp: []byte{0x41, 0xf, 0x94, 0xc0}}, 100 {name: "inst=SETEQ/reg=R9", inst: SETEQ, dst: RegR9, exp: []byte{0x41, 0xf, 0x94, 0xc1}}, 101 {name: "inst=SETEQ/reg=R13", inst: SETEQ, dst: RegR13, exp: []byte{0x41, 0xf, 0x94, 0xc5}}, 102 {name: "inst=SETEQ/reg=R14", inst: SETEQ, dst: RegR14, exp: []byte{0x41, 0xf, 0x94, 0xc6}}, 103 {name: "inst=SETEQ/reg=R15", inst: SETEQ, dst: RegR15, exp: []byte{0x41, 0xf, 0x94, 0xc7}}, 104 {name: "inst=SETGE/reg=AX", inst: SETGE, dst: RegAX, exp: []byte{0xf, 0x9d, 0xc0}}, 105 {name: "inst=SETGE/reg=BX", inst: SETGE, dst: RegBX, exp: []byte{0xf, 0x9d, 0xc3}}, 106 {name: "inst=SETGE/reg=SP", inst: SETGE, dst: RegSP, exp: []byte{0x40, 0xf, 0x9d, 0xc4}}, 107 {name: "inst=SETGE/reg=BP", inst: SETGE, dst: RegBP, exp: []byte{0x40, 0xf, 0x9d, 0xc5}}, 108 {name: "inst=SETGE/reg=SI", inst: SETGE, dst: RegSI, exp: []byte{0x40, 0xf, 0x9d, 0xc6}}, 109 {name: "inst=SETGE/reg=DI", inst: SETGE, dst: RegDI, exp: []byte{0x40, 0xf, 0x9d, 0xc7}}, 110 {name: "inst=SETGE/reg=R8", inst: SETGE, dst: RegR8, exp: []byte{0x41, 0xf, 0x9d, 0xc0}}, 111 {name: "inst=SETGE/reg=R9", inst: SETGE, dst: RegR9, exp: []byte{0x41, 0xf, 0x9d, 0xc1}}, 112 {name: "inst=SETGE/reg=R13", inst: SETGE, dst: RegR13, exp: []byte{0x41, 0xf, 0x9d, 0xc5}}, 113 {name: "inst=SETGE/reg=R14", inst: SETGE, dst: RegR14, exp: []byte{0x41, 0xf, 0x9d, 0xc6}}, 114 {name: "inst=SETGE/reg=R15", inst: SETGE, dst: RegR15, exp: []byte{0x41, 0xf, 0x9d, 0xc7}}, 115 {name: "inst=SETGT/reg=AX", inst: SETGT, dst: RegAX, exp: []byte{0xf, 0x9f, 0xc0}}, 116 {name: "inst=SETGT/reg=BX", inst: SETGT, dst: RegBX, exp: []byte{0xf, 0x9f, 0xc3}}, 117 {name: "inst=SETGT/reg=SP", inst: SETGT, dst: RegSP, exp: []byte{0x40, 0xf, 0x9f, 0xc4}}, 118 {name: "inst=SETGT/reg=BP", inst: SETGT, dst: RegBP, exp: []byte{0x40, 0xf, 0x9f, 0xc5}}, 119 {name: "inst=SETGT/reg=SI", inst: SETGT, dst: RegSI, exp: []byte{0x40, 0xf, 0x9f, 0xc6}}, 120 {name: "inst=SETGT/reg=DI", inst: SETGT, dst: RegDI, exp: []byte{0x40, 0xf, 0x9f, 0xc7}}, 121 {name: "inst=SETGT/reg=R8", inst: SETGT, dst: RegR8, exp: []byte{0x41, 0xf, 0x9f, 0xc0}}, 122 {name: "inst=SETGT/reg=R9", inst: SETGT, dst: RegR9, exp: []byte{0x41, 0xf, 0x9f, 0xc1}}, 123 {name: "inst=SETGT/reg=R13", inst: SETGT, dst: RegR13, exp: []byte{0x41, 0xf, 0x9f, 0xc5}}, 124 {name: "inst=SETGT/reg=R14", inst: SETGT, dst: RegR14, exp: []byte{0x41, 0xf, 0x9f, 0xc6}}, 125 {name: "inst=SETGT/reg=R15", inst: SETGT, dst: RegR15, exp: []byte{0x41, 0xf, 0x9f, 0xc7}}, 126 {name: "inst=SETHI/reg=AX", inst: SETHI, dst: RegAX, exp: []byte{0xf, 0x97, 0xc0}}, 127 {name: "inst=SETHI/reg=BX", inst: SETHI, dst: RegBX, exp: []byte{0xf, 0x97, 0xc3}}, 128 {name: "inst=SETHI/reg=SP", inst: SETHI, dst: RegSP, exp: []byte{0x40, 0xf, 0x97, 0xc4}}, 129 {name: "inst=SETHI/reg=BP", inst: SETHI, dst: RegBP, exp: []byte{0x40, 0xf, 0x97, 0xc5}}, 130 {name: "inst=SETHI/reg=SI", inst: SETHI, dst: RegSI, exp: []byte{0x40, 0xf, 0x97, 0xc6}}, 131 {name: "inst=SETHI/reg=DI", inst: SETHI, dst: RegDI, exp: []byte{0x40, 0xf, 0x97, 0xc7}}, 132 {name: "inst=SETHI/reg=R8", inst: SETHI, dst: RegR8, exp: []byte{0x41, 0xf, 0x97, 0xc0}}, 133 {name: "inst=SETHI/reg=R9", inst: SETHI, dst: RegR9, exp: []byte{0x41, 0xf, 0x97, 0xc1}}, 134 {name: "inst=SETHI/reg=R13", inst: SETHI, dst: RegR13, exp: []byte{0x41, 0xf, 0x97, 0xc5}}, 135 {name: "inst=SETHI/reg=R14", inst: SETHI, dst: RegR14, exp: []byte{0x41, 0xf, 0x97, 0xc6}}, 136 {name: "inst=SETHI/reg=R15", inst: SETHI, dst: RegR15, exp: []byte{0x41, 0xf, 0x97, 0xc7}}, 137 {name: "inst=SETLE/reg=AX", inst: SETLE, dst: RegAX, exp: []byte{0xf, 0x9e, 0xc0}}, 138 {name: "inst=SETLE/reg=BX", inst: SETLE, dst: RegBX, exp: []byte{0xf, 0x9e, 0xc3}}, 139 {name: "inst=SETLE/reg=SP", inst: SETLE, dst: RegSP, exp: []byte{0x40, 0xf, 0x9e, 0xc4}}, 140 {name: "inst=SETLE/reg=BP", inst: SETLE, dst: RegBP, exp: []byte{0x40, 0xf, 0x9e, 0xc5}}, 141 {name: "inst=SETLE/reg=SI", inst: SETLE, dst: RegSI, exp: []byte{0x40, 0xf, 0x9e, 0xc6}}, 142 {name: "inst=SETLE/reg=DI", inst: SETLE, dst: RegDI, exp: []byte{0x40, 0xf, 0x9e, 0xc7}}, 143 {name: "inst=SETLE/reg=R8", inst: SETLE, dst: RegR8, exp: []byte{0x41, 0xf, 0x9e, 0xc0}}, 144 {name: "inst=SETLE/reg=R9", inst: SETLE, dst: RegR9, exp: []byte{0x41, 0xf, 0x9e, 0xc1}}, 145 {name: "inst=SETLE/reg=R13", inst: SETLE, dst: RegR13, exp: []byte{0x41, 0xf, 0x9e, 0xc5}}, 146 {name: "inst=SETLE/reg=R14", inst: SETLE, dst: RegR14, exp: []byte{0x41, 0xf, 0x9e, 0xc6}}, 147 {name: "inst=SETLE/reg=R15", inst: SETLE, dst: RegR15, exp: []byte{0x41, 0xf, 0x9e, 0xc7}}, 148 {name: "inst=SETLS/reg=AX", inst: SETLS, dst: RegAX, exp: []byte{0xf, 0x96, 0xc0}}, 149 {name: "inst=SETLS/reg=BX", inst: SETLS, dst: RegBX, exp: []byte{0xf, 0x96, 0xc3}}, 150 {name: "inst=SETLS/reg=SP", inst: SETLS, dst: RegSP, exp: []byte{0x40, 0xf, 0x96, 0xc4}}, 151 {name: "inst=SETLS/reg=BP", inst: SETLS, dst: RegBP, exp: []byte{0x40, 0xf, 0x96, 0xc5}}, 152 {name: "inst=SETLS/reg=SI", inst: SETLS, dst: RegSI, exp: []byte{0x40, 0xf, 0x96, 0xc6}}, 153 {name: "inst=SETLS/reg=DI", inst: SETLS, dst: RegDI, exp: []byte{0x40, 0xf, 0x96, 0xc7}}, 154 {name: "inst=SETLS/reg=R8", inst: SETLS, dst: RegR8, exp: []byte{0x41, 0xf, 0x96, 0xc0}}, 155 {name: "inst=SETLS/reg=R9", inst: SETLS, dst: RegR9, exp: []byte{0x41, 0xf, 0x96, 0xc1}}, 156 {name: "inst=SETLS/reg=R13", inst: SETLS, dst: RegR13, exp: []byte{0x41, 0xf, 0x96, 0xc5}}, 157 {name: "inst=SETLS/reg=R14", inst: SETLS, dst: RegR14, exp: []byte{0x41, 0xf, 0x96, 0xc6}}, 158 {name: "inst=SETLS/reg=R15", inst: SETLS, dst: RegR15, exp: []byte{0x41, 0xf, 0x96, 0xc7}}, 159 {name: "inst=SETLT/reg=AX", inst: SETLT, dst: RegAX, exp: []byte{0xf, 0x9c, 0xc0}}, 160 {name: "inst=SETLT/reg=BX", inst: SETLT, dst: RegBX, exp: []byte{0xf, 0x9c, 0xc3}}, 161 {name: "inst=SETLT/reg=SP", inst: SETLT, dst: RegSP, exp: []byte{0x40, 0xf, 0x9c, 0xc4}}, 162 {name: "inst=SETLT/reg=BP", inst: SETLT, dst: RegBP, exp: []byte{0x40, 0xf, 0x9c, 0xc5}}, 163 {name: "inst=SETLT/reg=SI", inst: SETLT, dst: RegSI, exp: []byte{0x40, 0xf, 0x9c, 0xc6}}, 164 {name: "inst=SETLT/reg=DI", inst: SETLT, dst: RegDI, exp: []byte{0x40, 0xf, 0x9c, 0xc7}}, 165 {name: "inst=SETLT/reg=R8", inst: SETLT, dst: RegR8, exp: []byte{0x41, 0xf, 0x9c, 0xc0}}, 166 {name: "inst=SETLT/reg=R9", inst: SETLT, dst: RegR9, exp: []byte{0x41, 0xf, 0x9c, 0xc1}}, 167 {name: "inst=SETLT/reg=R13", inst: SETLT, dst: RegR13, exp: []byte{0x41, 0xf, 0x9c, 0xc5}}, 168 {name: "inst=SETLT/reg=R14", inst: SETLT, dst: RegR14, exp: []byte{0x41, 0xf, 0x9c, 0xc6}}, 169 {name: "inst=SETLT/reg=R15", inst: SETLT, dst: RegR15, exp: []byte{0x41, 0xf, 0x9c, 0xc7}}, 170 {name: "inst=SETNE/reg=AX", inst: SETNE, dst: RegAX, exp: []byte{0xf, 0x95, 0xc0}}, 171 {name: "inst=SETNE/reg=BX", inst: SETNE, dst: RegBX, exp: []byte{0xf, 0x95, 0xc3}}, 172 {name: "inst=SETNE/reg=SP", inst: SETNE, dst: RegSP, exp: []byte{0x40, 0xf, 0x95, 0xc4}}, 173 {name: "inst=SETNE/reg=BP", inst: SETNE, dst: RegBP, exp: []byte{0x40, 0xf, 0x95, 0xc5}}, 174 {name: "inst=SETNE/reg=SI", inst: SETNE, dst: RegSI, exp: []byte{0x40, 0xf, 0x95, 0xc6}}, 175 {name: "inst=SETNE/reg=DI", inst: SETNE, dst: RegDI, exp: []byte{0x40, 0xf, 0x95, 0xc7}}, 176 {name: "inst=SETNE/reg=R8", inst: SETNE, dst: RegR8, exp: []byte{0x41, 0xf, 0x95, 0xc0}}, 177 {name: "inst=SETNE/reg=R9", inst: SETNE, dst: RegR9, exp: []byte{0x41, 0xf, 0x95, 0xc1}}, 178 {name: "inst=SETNE/reg=R13", inst: SETNE, dst: RegR13, exp: []byte{0x41, 0xf, 0x95, 0xc5}}, 179 {name: "inst=SETNE/reg=R14", inst: SETNE, dst: RegR14, exp: []byte{0x41, 0xf, 0x95, 0xc6}}, 180 {name: "inst=SETNE/reg=R15", inst: SETNE, dst: RegR15, exp: []byte{0x41, 0xf, 0x95, 0xc7}}, 181 {name: "inst=SETPC/reg=AX", inst: SETPC, dst: RegAX, exp: []byte{0xf, 0x9b, 0xc0}}, 182 {name: "inst=SETPC/reg=BX", inst: SETPC, dst: RegBX, exp: []byte{0xf, 0x9b, 0xc3}}, 183 {name: "inst=SETPC/reg=SP", inst: SETPC, dst: RegSP, exp: []byte{0x40, 0xf, 0x9b, 0xc4}}, 184 {name: "inst=SETPC/reg=BP", inst: SETPC, dst: RegBP, exp: []byte{0x40, 0xf, 0x9b, 0xc5}}, 185 {name: "inst=SETPC/reg=SI", inst: SETPC, dst: RegSI, exp: []byte{0x40, 0xf, 0x9b, 0xc6}}, 186 {name: "inst=SETPC/reg=DI", inst: SETPC, dst: RegDI, exp: []byte{0x40, 0xf, 0x9b, 0xc7}}, 187 {name: "inst=SETPC/reg=R8", inst: SETPC, dst: RegR8, exp: []byte{0x41, 0xf, 0x9b, 0xc0}}, 188 {name: "inst=SETPC/reg=R9", inst: SETPC, dst: RegR9, exp: []byte{0x41, 0xf, 0x9b, 0xc1}}, 189 {name: "inst=SETPC/reg=R13", inst: SETPC, dst: RegR13, exp: []byte{0x41, 0xf, 0x9b, 0xc5}}, 190 {name: "inst=SETPC/reg=R14", inst: SETPC, dst: RegR14, exp: []byte{0x41, 0xf, 0x9b, 0xc6}}, 191 {name: "inst=SETPC/reg=R15", inst: SETPC, dst: RegR15, exp: []byte{0x41, 0xf, 0x9b, 0xc7}}, 192 {name: "inst=SETPS/reg=AX", inst: SETPS, dst: RegAX, exp: []byte{0xf, 0x9a, 0xc0}}, 193 {name: "inst=SETPS/reg=BX", inst: SETPS, dst: RegBX, exp: []byte{0xf, 0x9a, 0xc3}}, 194 {name: "inst=SETPS/reg=SP", inst: SETPS, dst: RegSP, exp: []byte{0x40, 0xf, 0x9a, 0xc4}}, 195 {name: "inst=SETPS/reg=BP", inst: SETPS, dst: RegBP, exp: []byte{0x40, 0xf, 0x9a, 0xc5}}, 196 {name: "inst=SETPS/reg=SI", inst: SETPS, dst: RegSI, exp: []byte{0x40, 0xf, 0x9a, 0xc6}}, 197 {name: "inst=SETPS/reg=DI", inst: SETPS, dst: RegDI, exp: []byte{0x40, 0xf, 0x9a, 0xc7}}, 198 {name: "inst=SETPS/reg=R8", inst: SETPS, dst: RegR8, exp: []byte{0x41, 0xf, 0x9a, 0xc0}}, 199 {name: "inst=SETPS/reg=R9", inst: SETPS, dst: RegR9, exp: []byte{0x41, 0xf, 0x9a, 0xc1}}, 200 {name: "inst=SETPS/reg=R13", inst: SETPS, dst: RegR13, exp: []byte{0x41, 0xf, 0x9a, 0xc5}}, 201 {name: "inst=SETPS/reg=R14", inst: SETPS, dst: RegR14, exp: []byte{0x41, 0xf, 0x9a, 0xc6}}, 202 {name: "inst=SETPS/reg=R15", inst: SETPS, dst: RegR15, exp: []byte{0x41, 0xf, 0x9a, 0xc7}}, 203 {name: "inst=NEGQ/reg=AX", inst: NEGQ, dst: RegAX, exp: []byte{0x48, 0xf7, 0xd8}}, 204 {name: "inst=NEGQ/reg=BX", inst: NEGQ, dst: RegBX, exp: []byte{0x48, 0xf7, 0xdb}}, 205 {name: "inst=NEGQ/reg=SP", inst: NEGQ, dst: RegSP, exp: []byte{0x48, 0xf7, 0xdc}}, 206 {name: "inst=NEGQ/reg=BP", inst: NEGQ, dst: RegBP, exp: []byte{0x48, 0xf7, 0xdd}}, 207 {name: "inst=NEGQ/reg=SI", inst: NEGQ, dst: RegSI, exp: []byte{0x48, 0xf7, 0xde}}, 208 {name: "inst=NEGQ/reg=DI", inst: NEGQ, dst: RegDI, exp: []byte{0x48, 0xf7, 0xdf}}, 209 {name: "inst=NEGQ/reg=R8", inst: NEGQ, dst: RegR8, exp: []byte{0x49, 0xf7, 0xd8}}, 210 {name: "inst=NEGQ/reg=R9", inst: NEGQ, dst: RegR9, exp: []byte{0x49, 0xf7, 0xd9}}, 211 {name: "inst=NEGQ/reg=R13", inst: NEGQ, dst: RegR13, exp: []byte{0x49, 0xf7, 0xdd}}, 212 {name: "inst=NEGQ/reg=R14", inst: NEGQ, dst: RegR14, exp: []byte{0x49, 0xf7, 0xde}}, 213 {name: "inst=NEGQ/reg=R15", inst: NEGQ, dst: RegR15, exp: []byte{0x49, 0xf7, 0xdf}}, 214 {name: "inst=INCQ/reg=AX", inst: INCQ, dst: RegAX, exp: []byte{0x48, 0xff, 0xc0}}, 215 {name: "inst=INCQ/reg=BX", inst: INCQ, dst: RegBX, exp: []byte{0x48, 0xff, 0xc3}}, 216 {name: "inst=INCQ/reg=SP", inst: INCQ, dst: RegSP, exp: []byte{0x48, 0xff, 0xc4}}, 217 {name: "inst=INCQ/reg=BP", inst: INCQ, dst: RegBP, exp: []byte{0x48, 0xff, 0xc5}}, 218 {name: "inst=INCQ/reg=SI", inst: INCQ, dst: RegSI, exp: []byte{0x48, 0xff, 0xc6}}, 219 {name: "inst=INCQ/reg=DI", inst: INCQ, dst: RegDI, exp: []byte{0x48, 0xff, 0xc7}}, 220 {name: "inst=INCQ/reg=R8", inst: INCQ, dst: RegR8, exp: []byte{0x49, 0xff, 0xc0}}, 221 {name: "inst=INCQ/reg=R9", inst: INCQ, dst: RegR9, exp: []byte{0x49, 0xff, 0xc1}}, 222 {name: "inst=INCQ/reg=R13", inst: INCQ, dst: RegR13, exp: []byte{0x49, 0xff, 0xc5}}, 223 {name: "inst=INCQ/reg=R14", inst: INCQ, dst: RegR14, exp: []byte{0x49, 0xff, 0xc6}}, 224 {name: "inst=INCQ/reg=R15", inst: INCQ, dst: RegR15, exp: []byte{0x49, 0xff, 0xc7}}, 225 {name: "inst=DECQ/reg=AX", inst: DECQ, dst: RegAX, exp: []byte{0x48, 0xff, 0xc8}}, 226 {name: "inst=DECQ/reg=BX", inst: DECQ, dst: RegBX, exp: []byte{0x48, 0xff, 0xcb}}, 227 {name: "inst=DECQ/reg=SP", inst: DECQ, dst: RegSP, exp: []byte{0x48, 0xff, 0xcc}}, 228 {name: "inst=DECQ/reg=BP", inst: DECQ, dst: RegBP, exp: []byte{0x48, 0xff, 0xcd}}, 229 {name: "inst=DECQ/reg=SI", inst: DECQ, dst: RegSI, exp: []byte{0x48, 0xff, 0xce}}, 230 {name: "inst=DECQ/reg=DI", inst: DECQ, dst: RegDI, exp: []byte{0x48, 0xff, 0xcf}}, 231 {name: "inst=DECQ/reg=R8", inst: DECQ, dst: RegR8, exp: []byte{0x49, 0xff, 0xc8}}, 232 {name: "inst=DECQ/reg=R9", inst: DECQ, dst: RegR9, exp: []byte{0x49, 0xff, 0xc9}}, 233 {name: "inst=DECQ/reg=R13", inst: DECQ, dst: RegR13, exp: []byte{0x49, 0xff, 0xcd}}, 234 {name: "inst=DECQ/reg=R14", inst: DECQ, dst: RegR14, exp: []byte{0x49, 0xff, 0xce}}, 235 {name: "inst=DECQ/reg=R15", inst: DECQ, dst: RegR15, exp: []byte{0x49, 0xff, 0xcf}}, 236 } 237 238 for _, tc := range tests { 239 tc := tc 240 a := NewAssembler() 241 err := a.encodeNoneToRegister(&nodeImpl{instruction: tc.inst, dstReg: tc.dst}) 242 require.NoError(t, err, tc.name) 243 require.Equal(t, tc.exp, a.buf.Bytes(), tc.name) 244 } 245 } 246 247 func TestAssemblerImpl_EncodeNoneToMemory(t *testing.T) { 248 t.Run("error", func(t *testing.T) { 249 tests := []struct { 250 n *nodeImpl 251 expErr string 252 }{ 253 { 254 n: &nodeImpl{instruction: ADDL, types: operandTypesNoneToMemory, dstReg: RegAX}, 255 expErr: "ADDL is unsupported for from:none,to:memory type", 256 }, 257 } 258 259 for _, tt := range tests { 260 tc := tt 261 t.Run(tc.expErr, func(t *testing.T) { 262 tc := tc 263 a := NewAssembler() 264 err := a.encodeNoneToMemory(tc.n) 265 require.EqualError(t, err, tc.expErr) 266 }) 267 } 268 }) 269 270 tests := []struct { 271 name string 272 inst asm.Instruction 273 dst asm.Register 274 dstOffset int64 275 exp []byte 276 }{ 277 {name: "inst=DECQ/reg=AX/offset=0", inst: DECQ, dst: RegAX, dstOffset: 0, exp: []byte{0x48, 0xff, 0x8}}, 278 {name: "inst=DECQ/reg=AX/offset=1", inst: DECQ, dst: RegAX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x48, 0x1}}, 279 {name: "inst=DECQ/reg=AX/offset=-1", inst: DECQ, dst: RegAX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x48, 0xff}}, 280 {name: "inst=DECQ/reg=AX/offset=1243", inst: DECQ, dst: RegAX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x88, 0xdb, 0x4, 0x0, 0x0}}, 281 {name: "inst=DECQ/reg=AX/offset=2147483647", inst: DECQ, dst: RegAX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 282 {name: "inst=DECQ/reg=AX/offset=-32768", inst: DECQ, dst: RegAX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x88, 0x0, 0x80, 0xff, 0xff}}, 283 {name: "inst=DECQ/reg=BX/offset=0", inst: DECQ, dst: RegBX, dstOffset: 0, exp: []byte{0x48, 0xff, 0xb}}, 284 {name: "inst=DECQ/reg=BX/offset=1", inst: DECQ, dst: RegBX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4b, 0x1}}, 285 {name: "inst=DECQ/reg=BX/offset=-1", inst: DECQ, dst: RegBX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4b, 0xff}}, 286 {name: "inst=DECQ/reg=BX/offset=1243", inst: DECQ, dst: RegBX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8b, 0xdb, 0x4, 0x0, 0x0}}, 287 {name: "inst=DECQ/reg=BX/offset=2147483647", inst: DECQ, dst: RegBX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8b, 0xff, 0xff, 0xff, 0x7f}}, 288 {name: "inst=DECQ/reg=BX/offset=-32768", inst: DECQ, dst: RegBX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8b, 0x0, 0x80, 0xff, 0xff}}, 289 {name: "inst=DECQ/reg=SP/offset=0", inst: DECQ, dst: RegSP, dstOffset: 0, exp: []byte{0x48, 0xff, 0xc, 0x24}}, 290 {name: "inst=DECQ/reg=SP/offset=1", inst: DECQ, dst: RegSP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4c, 0x24, 0x1}}, 291 {name: "inst=DECQ/reg=SP/offset=-1", inst: DECQ, dst: RegSP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4c, 0x24, 0xff}}, 292 {name: "inst=DECQ/reg=SP/offset=1243", inst: DECQ, dst: RegSP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8c, 0x24, 0xdb, 0x4, 0x0, 0x0}}, 293 {name: "inst=DECQ/reg=SP/offset=2147483647", inst: DECQ, dst: RegSP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8c, 0x24, 0xff, 0xff, 0xff, 0x7f}}, 294 {name: "inst=DECQ/reg=SP/offset=-32768", inst: DECQ, dst: RegSP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8c, 0x24, 0x0, 0x80, 0xff, 0xff}}, 295 {name: "inst=DECQ/reg=BP/offset=0", inst: DECQ, dst: RegBP, dstOffset: 0, exp: []byte{0x48, 0xff, 0x4d, 0x0}}, 296 {name: "inst=DECQ/reg=BP/offset=1", inst: DECQ, dst: RegBP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4d, 0x1}}, 297 {name: "inst=DECQ/reg=BP/offset=-1", inst: DECQ, dst: RegBP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4d, 0xff}}, 298 {name: "inst=DECQ/reg=BP/offset=1243", inst: DECQ, dst: RegBP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8d, 0xdb, 0x4, 0x0, 0x0}}, 299 {name: "inst=DECQ/reg=BP/offset=2147483647", inst: DECQ, dst: RegBP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8d, 0xff, 0xff, 0xff, 0x7f}}, 300 {name: "inst=DECQ/reg=BP/offset=-32768", inst: DECQ, dst: RegBP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8d, 0x0, 0x80, 0xff, 0xff}}, 301 {name: "inst=DECQ/reg=SI/offset=0", inst: DECQ, dst: RegSI, dstOffset: 0, exp: []byte{0x48, 0xff, 0xe}}, 302 {name: "inst=DECQ/reg=SI/offset=1", inst: DECQ, dst: RegSI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4e, 0x1}}, 303 {name: "inst=DECQ/reg=SI/offset=-1", inst: DECQ, dst: RegSI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4e, 0xff}}, 304 {name: "inst=DECQ/reg=SI/offset=1243", inst: DECQ, dst: RegSI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8e, 0xdb, 0x4, 0x0, 0x0}}, 305 {name: "inst=DECQ/reg=SI/offset=2147483647", inst: DECQ, dst: RegSI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8e, 0xff, 0xff, 0xff, 0x7f}}, 306 {name: "inst=DECQ/reg=SI/offset=-32768", inst: DECQ, dst: RegSI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8e, 0x0, 0x80, 0xff, 0xff}}, 307 {name: "inst=DECQ/reg=DI/offset=0", inst: DECQ, dst: RegDI, dstOffset: 0, exp: []byte{0x48, 0xff, 0xf}}, 308 {name: "inst=DECQ/reg=DI/offset=1", inst: DECQ, dst: RegDI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4f, 0x1}}, 309 {name: "inst=DECQ/reg=DI/offset=-1", inst: DECQ, dst: RegDI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4f, 0xff}}, 310 {name: "inst=DECQ/reg=DI/offset=1243", inst: DECQ, dst: RegDI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8f, 0xdb, 0x4, 0x0, 0x0}}, 311 {name: "inst=DECQ/reg=DI/offset=2147483647", inst: DECQ, dst: RegDI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8f, 0xff, 0xff, 0xff, 0x7f}}, 312 {name: "inst=DECQ/reg=DI/offset=-32768", inst: DECQ, dst: RegDI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8f, 0x0, 0x80, 0xff, 0xff}}, 313 {name: "inst=DECQ/reg=R8/offset=0", inst: DECQ, dst: RegR8, dstOffset: 0, exp: []byte{0x49, 0xff, 0x8}}, 314 {name: "inst=DECQ/reg=R8/offset=1", inst: DECQ, dst: RegR8, dstOffset: 1, exp: []byte{0x49, 0xff, 0x48, 0x1}}, 315 {name: "inst=DECQ/reg=R8/offset=-1", inst: DECQ, dst: RegR8, dstOffset: -1, exp: []byte{0x49, 0xff, 0x48, 0xff}}, 316 {name: "inst=DECQ/reg=R8/offset=1243", inst: DECQ, dst: RegR8, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x88, 0xdb, 0x4, 0x0, 0x0}}, 317 {name: "inst=DECQ/reg=R8/offset=2147483647", inst: DECQ, dst: RegR8, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x88, 0xff, 0xff, 0xff, 0x7f}}, 318 {name: "inst=DECQ/reg=R8/offset=-32768", inst: DECQ, dst: RegR8, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x88, 0x0, 0x80, 0xff, 0xff}}, 319 {name: "inst=DECQ/reg=R9/offset=0", inst: DECQ, dst: RegR9, dstOffset: 0, exp: []byte{0x49, 0xff, 0x9}}, 320 {name: "inst=DECQ/reg=R9/offset=1", inst: DECQ, dst: RegR9, dstOffset: 1, exp: []byte{0x49, 0xff, 0x49, 0x1}}, 321 {name: "inst=DECQ/reg=R9/offset=-1", inst: DECQ, dst: RegR9, dstOffset: -1, exp: []byte{0x49, 0xff, 0x49, 0xff}}, 322 {name: "inst=DECQ/reg=R9/offset=1243", inst: DECQ, dst: RegR9, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x89, 0xdb, 0x4, 0x0, 0x0}}, 323 {name: "inst=DECQ/reg=R9/offset=2147483647", inst: DECQ, dst: RegR9, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x89, 0xff, 0xff, 0xff, 0x7f}}, 324 {name: "inst=DECQ/reg=R9/offset=-32768", inst: DECQ, dst: RegR9, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x89, 0x0, 0x80, 0xff, 0xff}}, 325 {name: "inst=DECQ/reg=R13/offset=0", inst: DECQ, dst: RegR13, dstOffset: 0, exp: []byte{0x49, 0xff, 0x4d, 0x0}}, 326 {name: "inst=DECQ/reg=R13/offset=1", inst: DECQ, dst: RegR13, dstOffset: 1, exp: []byte{0x49, 0xff, 0x4d, 0x1}}, 327 {name: "inst=DECQ/reg=R13/offset=-1", inst: DECQ, dst: RegR13, dstOffset: -1, exp: []byte{0x49, 0xff, 0x4d, 0xff}}, 328 {name: "inst=DECQ/reg=R13/offset=1243", inst: DECQ, dst: RegR13, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x8d, 0xdb, 0x4, 0x0, 0x0}}, 329 {name: "inst=DECQ/reg=R13/offset=2147483647", inst: DECQ, dst: RegR13, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x8d, 0xff, 0xff, 0xff, 0x7f}}, 330 {name: "inst=DECQ/reg=R13/offset=-32768", inst: DECQ, dst: RegR13, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x8d, 0x0, 0x80, 0xff, 0xff}}, 331 {name: "inst=DECQ/reg=R14/offset=0", inst: DECQ, dst: RegR14, dstOffset: 0, exp: []byte{0x49, 0xff, 0xe}}, 332 {name: "inst=DECQ/reg=R14/offset=1", inst: DECQ, dst: RegR14, dstOffset: 1, exp: []byte{0x49, 0xff, 0x4e, 0x1}}, 333 {name: "inst=DECQ/reg=R14/offset=-1", inst: DECQ, dst: RegR14, dstOffset: -1, exp: []byte{0x49, 0xff, 0x4e, 0xff}}, 334 {name: "inst=DECQ/reg=R14/offset=1243", inst: DECQ, dst: RegR14, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x8e, 0xdb, 0x4, 0x0, 0x0}}, 335 {name: "inst=DECQ/reg=R14/offset=2147483647", inst: DECQ, dst: RegR14, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x8e, 0xff, 0xff, 0xff, 0x7f}}, 336 {name: "inst=DECQ/reg=R14/offset=-32768", inst: DECQ, dst: RegR14, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x8e, 0x0, 0x80, 0xff, 0xff}}, 337 {name: "inst=DECQ/reg=R15/offset=0", inst: DECQ, dst: RegR15, dstOffset: 0, exp: []byte{0x49, 0xff, 0xf}}, 338 {name: "inst=DECQ/reg=R15/offset=1", inst: DECQ, dst: RegR15, dstOffset: 1, exp: []byte{0x49, 0xff, 0x4f, 0x1}}, 339 {name: "inst=DECQ/reg=R15/offset=-1", inst: DECQ, dst: RegR15, dstOffset: -1, exp: []byte{0x49, 0xff, 0x4f, 0xff}}, 340 {name: "inst=DECQ/reg=R15/offset=1243", inst: DECQ, dst: RegR15, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x8f, 0xdb, 0x4, 0x0, 0x0}}, 341 {name: "inst=DECQ/reg=R15/offset=2147483647", inst: DECQ, dst: RegR15, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x8f, 0xff, 0xff, 0xff, 0x7f}}, 342 {name: "inst=DECQ/reg=R15/offset=-32768", inst: DECQ, dst: RegR15, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x8f, 0x0, 0x80, 0xff, 0xff}}, 343 {name: "inst=INCQ/reg=AX/offset=0", inst: INCQ, dst: RegAX, dstOffset: 0, exp: []byte{0x48, 0xff, 0x0}}, 344 {name: "inst=INCQ/reg=AX/offset=1", inst: INCQ, dst: RegAX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x40, 0x1}}, 345 {name: "inst=INCQ/reg=AX/offset=-1", inst: INCQ, dst: RegAX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x40, 0xff}}, 346 {name: "inst=INCQ/reg=AX/offset=1243", inst: INCQ, dst: RegAX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x80, 0xdb, 0x4, 0x0, 0x0}}, 347 {name: "inst=INCQ/reg=AX/offset=2147483647", inst: INCQ, dst: RegAX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x80, 0xff, 0xff, 0xff, 0x7f}}, 348 {name: "inst=INCQ/reg=AX/offset=-32768", inst: INCQ, dst: RegAX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x80, 0x0, 0x80, 0xff, 0xff}}, 349 {name: "inst=INCQ/reg=BX/offset=0", inst: INCQ, dst: RegBX, dstOffset: 0, exp: []byte{0x48, 0xff, 0x3}}, 350 {name: "inst=INCQ/reg=BX/offset=1", inst: INCQ, dst: RegBX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x43, 0x1}}, 351 {name: "inst=INCQ/reg=BX/offset=-1", inst: INCQ, dst: RegBX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x43, 0xff}}, 352 {name: "inst=INCQ/reg=BX/offset=1243", inst: INCQ, dst: RegBX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x83, 0xdb, 0x4, 0x0, 0x0}}, 353 {name: "inst=INCQ/reg=BX/offset=2147483647", inst: INCQ, dst: RegBX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x83, 0xff, 0xff, 0xff, 0x7f}}, 354 {name: "inst=INCQ/reg=BX/offset=-32768", inst: INCQ, dst: RegBX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x83, 0x0, 0x80, 0xff, 0xff}}, 355 {name: "inst=INCQ/reg=SP/offset=0", inst: INCQ, dst: RegSP, dstOffset: 0, exp: []byte{0x48, 0xff, 0x4, 0x24}}, 356 {name: "inst=INCQ/reg=SP/offset=1", inst: INCQ, dst: RegSP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x44, 0x24, 0x1}}, 357 {name: "inst=INCQ/reg=SP/offset=-1", inst: INCQ, dst: RegSP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x44, 0x24, 0xff}}, 358 {name: "inst=INCQ/reg=SP/offset=1243", inst: INCQ, dst: RegSP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x84, 0x24, 0xdb, 0x4, 0x0, 0x0}}, 359 {name: "inst=INCQ/reg=SP/offset=2147483647", inst: INCQ, dst: RegSP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x84, 0x24, 0xff, 0xff, 0xff, 0x7f}}, 360 {name: "inst=INCQ/reg=SP/offset=-32768", inst: INCQ, dst: RegSP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x84, 0x24, 0x0, 0x80, 0xff, 0xff}}, 361 {name: "inst=INCQ/reg=BP/offset=0", inst: INCQ, dst: RegBP, dstOffset: 0, exp: []byte{0x48, 0xff, 0x45, 0x0}}, 362 {name: "inst=INCQ/reg=BP/offset=1", inst: INCQ, dst: RegBP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x45, 0x1}}, 363 {name: "inst=INCQ/reg=BP/offset=-1", inst: INCQ, dst: RegBP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x45, 0xff}}, 364 {name: "inst=INCQ/reg=BP/offset=1243", inst: INCQ, dst: RegBP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x85, 0xdb, 0x4, 0x0, 0x0}}, 365 {name: "inst=INCQ/reg=BP/offset=2147483647", inst: INCQ, dst: RegBP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x85, 0xff, 0xff, 0xff, 0x7f}}, 366 {name: "inst=INCQ/reg=BP/offset=-32768", inst: INCQ, dst: RegBP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x85, 0x0, 0x80, 0xff, 0xff}}, 367 {name: "inst=INCQ/reg=SI/offset=0", inst: INCQ, dst: RegSI, dstOffset: 0, exp: []byte{0x48, 0xff, 0x6}}, 368 {name: "inst=INCQ/reg=SI/offset=1", inst: INCQ, dst: RegSI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x46, 0x1}}, 369 {name: "inst=INCQ/reg=SI/offset=-1", inst: INCQ, dst: RegSI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x46, 0xff}}, 370 {name: "inst=INCQ/reg=SI/offset=1243", inst: INCQ, dst: RegSI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x86, 0xdb, 0x4, 0x0, 0x0}}, 371 {name: "inst=INCQ/reg=SI/offset=2147483647", inst: INCQ, dst: RegSI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x86, 0xff, 0xff, 0xff, 0x7f}}, 372 {name: "inst=INCQ/reg=SI/offset=-32768", inst: INCQ, dst: RegSI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x86, 0x0, 0x80, 0xff, 0xff}}, 373 {name: "inst=INCQ/reg=DI/offset=0", inst: INCQ, dst: RegDI, dstOffset: 0, exp: []byte{0x48, 0xff, 0x7}}, 374 {name: "inst=INCQ/reg=DI/offset=1", inst: INCQ, dst: RegDI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x47, 0x1}}, 375 {name: "inst=INCQ/reg=DI/offset=-1", inst: INCQ, dst: RegDI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x47, 0xff}}, 376 {name: "inst=INCQ/reg=DI/offset=1243", inst: INCQ, dst: RegDI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x87, 0xdb, 0x4, 0x0, 0x0}}, 377 {name: "inst=INCQ/reg=DI/offset=2147483647", inst: INCQ, dst: RegDI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x87, 0xff, 0xff, 0xff, 0x7f}}, 378 {name: "inst=INCQ/reg=DI/offset=-32768", inst: INCQ, dst: RegDI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x87, 0x0, 0x80, 0xff, 0xff}}, 379 {name: "inst=INCQ/reg=R8/offset=0", inst: INCQ, dst: RegR8, dstOffset: 0, exp: []byte{0x49, 0xff, 0x0}}, 380 {name: "inst=INCQ/reg=R8/offset=1", inst: INCQ, dst: RegR8, dstOffset: 1, exp: []byte{0x49, 0xff, 0x40, 0x1}}, 381 {name: "inst=INCQ/reg=R8/offset=-1", inst: INCQ, dst: RegR8, dstOffset: -1, exp: []byte{0x49, 0xff, 0x40, 0xff}}, 382 {name: "inst=INCQ/reg=R8/offset=1243", inst: INCQ, dst: RegR8, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x80, 0xdb, 0x4, 0x0, 0x0}}, 383 {name: "inst=INCQ/reg=R8/offset=2147483647", inst: INCQ, dst: RegR8, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x80, 0xff, 0xff, 0xff, 0x7f}}, 384 {name: "inst=INCQ/reg=R8/offset=-32768", inst: INCQ, dst: RegR8, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x80, 0x0, 0x80, 0xff, 0xff}}, 385 {name: "inst=INCQ/reg=R9/offset=0", inst: INCQ, dst: RegR9, dstOffset: 0, exp: []byte{0x49, 0xff, 0x1}}, 386 {name: "inst=INCQ/reg=R9/offset=1", inst: INCQ, dst: RegR9, dstOffset: 1, exp: []byte{0x49, 0xff, 0x41, 0x1}}, 387 {name: "inst=INCQ/reg=R9/offset=-1", inst: INCQ, dst: RegR9, dstOffset: -1, exp: []byte{0x49, 0xff, 0x41, 0xff}}, 388 {name: "inst=INCQ/reg=R9/offset=1243", inst: INCQ, dst: RegR9, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x81, 0xdb, 0x4, 0x0, 0x0}}, 389 {name: "inst=INCQ/reg=R9/offset=2147483647", inst: INCQ, dst: RegR9, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x81, 0xff, 0xff, 0xff, 0x7f}}, 390 {name: "inst=INCQ/reg=R9/offset=-32768", inst: INCQ, dst: RegR9, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x81, 0x0, 0x80, 0xff, 0xff}}, 391 {name: "inst=INCQ/reg=R13/offset=0", inst: INCQ, dst: RegR13, dstOffset: 0, exp: []byte{0x49, 0xff, 0x45, 0x0}}, 392 {name: "inst=INCQ/reg=R13/offset=1", inst: INCQ, dst: RegR13, dstOffset: 1, exp: []byte{0x49, 0xff, 0x45, 0x1}}, 393 {name: "inst=INCQ/reg=R13/offset=-1", inst: INCQ, dst: RegR13, dstOffset: -1, exp: []byte{0x49, 0xff, 0x45, 0xff}}, 394 {name: "inst=INCQ/reg=R13/offset=1243", inst: INCQ, dst: RegR13, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x85, 0xdb, 0x4, 0x0, 0x0}}, 395 {name: "inst=INCQ/reg=R13/offset=2147483647", inst: INCQ, dst: RegR13, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x85, 0xff, 0xff, 0xff, 0x7f}}, 396 {name: "inst=INCQ/reg=R13/offset=-32768", inst: INCQ, dst: RegR13, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x85, 0x0, 0x80, 0xff, 0xff}}, 397 {name: "inst=INCQ/reg=R14/offset=0", inst: INCQ, dst: RegR14, dstOffset: 0, exp: []byte{0x49, 0xff, 0x6}}, 398 {name: "inst=INCQ/reg=R14/offset=1", inst: INCQ, dst: RegR14, dstOffset: 1, exp: []byte{0x49, 0xff, 0x46, 0x1}}, 399 {name: "inst=INCQ/reg=R14/offset=-1", inst: INCQ, dst: RegR14, dstOffset: -1, exp: []byte{0x49, 0xff, 0x46, 0xff}}, 400 {name: "inst=INCQ/reg=R14/offset=1243", inst: INCQ, dst: RegR14, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x86, 0xdb, 0x4, 0x0, 0x0}}, 401 {name: "inst=INCQ/reg=R14/offset=2147483647", inst: INCQ, dst: RegR14, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x86, 0xff, 0xff, 0xff, 0x7f}}, 402 {name: "inst=INCQ/reg=R14/offset=-32768", inst: INCQ, dst: RegR14, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x86, 0x0, 0x80, 0xff, 0xff}}, 403 {name: "inst=INCQ/reg=R15/offset=0", inst: INCQ, dst: RegR15, dstOffset: 0, exp: []byte{0x49, 0xff, 0x7}}, 404 {name: "inst=INCQ/reg=R15/offset=1", inst: INCQ, dst: RegR15, dstOffset: 1, exp: []byte{0x49, 0xff, 0x47, 0x1}}, 405 {name: "inst=INCQ/reg=R15/offset=-1", inst: INCQ, dst: RegR15, dstOffset: -1, exp: []byte{0x49, 0xff, 0x47, 0xff}}, 406 {name: "inst=INCQ/reg=R15/offset=1243", inst: INCQ, dst: RegR15, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x87, 0xdb, 0x4, 0x0, 0x0}}, 407 {name: "inst=INCQ/reg=R15/offset=2147483647", inst: INCQ, dst: RegR15, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x87, 0xff, 0xff, 0xff, 0x7f}}, 408 {name: "inst=INCQ/reg=R15/offset=-32768", inst: INCQ, dst: RegR15, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x87, 0x0, 0x80, 0xff, 0xff}}, 409 {name: "inst=JMP/reg=AX/offset=0", inst: JMP, dst: RegAX, dstOffset: 0, exp: []byte{0xff, 0x20}}, 410 {name: "inst=JMP/reg=AX/offset=1", inst: JMP, dst: RegAX, dstOffset: 1, exp: []byte{0xff, 0x60, 0x1}}, 411 {name: "inst=JMP/reg=AX/offset=-1", inst: JMP, dst: RegAX, dstOffset: -1, exp: []byte{0xff, 0x60, 0xff}}, 412 {name: "inst=JMP/reg=AX/offset=1243", inst: JMP, dst: RegAX, dstOffset: 1243, exp: []byte{0xff, 0xa0, 0xdb, 0x4, 0x0, 0x0}}, 413 {name: "inst=JMP/reg=AX/offset=2147483647", inst: JMP, dst: RegAX, dstOffset: 2147483647, exp: []byte{0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, 414 {name: "inst=JMP/reg=AX/offset=-32768", inst: JMP, dst: RegAX, dstOffset: -32768, exp: []byte{0xff, 0xa0, 0x0, 0x80, 0xff, 0xff}}, 415 {name: "inst=JMP/reg=BX/offset=0", inst: JMP, dst: RegBX, dstOffset: 0, exp: []byte{0xff, 0x23}}, 416 {name: "inst=JMP/reg=BX/offset=1", inst: JMP, dst: RegBX, dstOffset: 1, exp: []byte{0xff, 0x63, 0x1}}, 417 {name: "inst=JMP/reg=BX/offset=-1", inst: JMP, dst: RegBX, dstOffset: -1, exp: []byte{0xff, 0x63, 0xff}}, 418 {name: "inst=JMP/reg=BX/offset=1243", inst: JMP, dst: RegBX, dstOffset: 1243, exp: []byte{0xff, 0xa3, 0xdb, 0x4, 0x0, 0x0}}, 419 {name: "inst=JMP/reg=BX/offset=2147483647", inst: JMP, dst: RegBX, dstOffset: 2147483647, exp: []byte{0xff, 0xa3, 0xff, 0xff, 0xff, 0x7f}}, 420 {name: "inst=JMP/reg=BX/offset=-32768", inst: JMP, dst: RegBX, dstOffset: -32768, exp: []byte{0xff, 0xa3, 0x0, 0x80, 0xff, 0xff}}, 421 {name: "inst=JMP/reg=SP/offset=0", inst: JMP, dst: RegSP, dstOffset: 0, exp: []byte{0xff, 0x24, 0x24}}, 422 {name: "inst=JMP/reg=SP/offset=1", inst: JMP, dst: RegSP, dstOffset: 1, exp: []byte{0xff, 0x64, 0x24, 0x1}}, 423 {name: "inst=JMP/reg=SP/offset=-1", inst: JMP, dst: RegSP, dstOffset: -1, exp: []byte{0xff, 0x64, 0x24, 0xff}}, 424 {name: "inst=JMP/reg=SP/offset=1243", inst: JMP, dst: RegSP, dstOffset: 1243, exp: []byte{0xff, 0xa4, 0x24, 0xdb, 0x4, 0x0, 0x0}}, 425 {name: "inst=JMP/reg=SP/offset=2147483647", inst: JMP, dst: RegSP, dstOffset: 2147483647, exp: []byte{0xff, 0xa4, 0x24, 0xff, 0xff, 0xff, 0x7f}}, 426 {name: "inst=JMP/reg=SP/offset=-32768", inst: JMP, dst: RegSP, dstOffset: -32768, exp: []byte{0xff, 0xa4, 0x24, 0x0, 0x80, 0xff, 0xff}}, 427 {name: "inst=JMP/reg=BP/offset=0", inst: JMP, dst: RegBP, dstOffset: 0, exp: []byte{0xff, 0x65, 0x0}}, 428 {name: "inst=JMP/reg=BP/offset=1", inst: JMP, dst: RegBP, dstOffset: 1, exp: []byte{0xff, 0x65, 0x1}}, 429 {name: "inst=JMP/reg=BP/offset=-1", inst: JMP, dst: RegBP, dstOffset: -1, exp: []byte{0xff, 0x65, 0xff}}, 430 {name: "inst=JMP/reg=BP/offset=1243", inst: JMP, dst: RegBP, dstOffset: 1243, exp: []byte{0xff, 0xa5, 0xdb, 0x4, 0x0, 0x0}}, 431 {name: "inst=JMP/reg=BP/offset=2147483647", inst: JMP, dst: RegBP, dstOffset: 2147483647, exp: []byte{0xff, 0xa5, 0xff, 0xff, 0xff, 0x7f}}, 432 {name: "inst=JMP/reg=BP/offset=-32768", inst: JMP, dst: RegBP, dstOffset: -32768, exp: []byte{0xff, 0xa5, 0x0, 0x80, 0xff, 0xff}}, 433 {name: "inst=JMP/reg=SI/offset=0", inst: JMP, dst: RegSI, dstOffset: 0, exp: []byte{0xff, 0x26}}, 434 {name: "inst=JMP/reg=SI/offset=1", inst: JMP, dst: RegSI, dstOffset: 1, exp: []byte{0xff, 0x66, 0x1}}, 435 {name: "inst=JMP/reg=SI/offset=-1", inst: JMP, dst: RegSI, dstOffset: -1, exp: []byte{0xff, 0x66, 0xff}}, 436 {name: "inst=JMP/reg=SI/offset=1243", inst: JMP, dst: RegSI, dstOffset: 1243, exp: []byte{0xff, 0xa6, 0xdb, 0x4, 0x0, 0x0}}, 437 {name: "inst=JMP/reg=SI/offset=2147483647", inst: JMP, dst: RegSI, dstOffset: 2147483647, exp: []byte{0xff, 0xa6, 0xff, 0xff, 0xff, 0x7f}}, 438 {name: "inst=JMP/reg=SI/offset=-32768", inst: JMP, dst: RegSI, dstOffset: -32768, exp: []byte{0xff, 0xa6, 0x0, 0x80, 0xff, 0xff}}, 439 {name: "inst=JMP/reg=DI/offset=0", inst: JMP, dst: RegDI, dstOffset: 0, exp: []byte{0xff, 0x27}}, 440 {name: "inst=JMP/reg=DI/offset=1", inst: JMP, dst: RegDI, dstOffset: 1, exp: []byte{0xff, 0x67, 0x1}}, 441 {name: "inst=JMP/reg=DI/offset=-1", inst: JMP, dst: RegDI, dstOffset: -1, exp: []byte{0xff, 0x67, 0xff}}, 442 {name: "inst=JMP/reg=DI/offset=1243", inst: JMP, dst: RegDI, dstOffset: 1243, exp: []byte{0xff, 0xa7, 0xdb, 0x4, 0x0, 0x0}}, 443 {name: "inst=JMP/reg=DI/offset=2147483647", inst: JMP, dst: RegDI, dstOffset: 2147483647, exp: []byte{0xff, 0xa7, 0xff, 0xff, 0xff, 0x7f}}, 444 {name: "inst=JMP/reg=DI/offset=-32768", inst: JMP, dst: RegDI, dstOffset: -32768, exp: []byte{0xff, 0xa7, 0x0, 0x80, 0xff, 0xff}}, 445 {name: "inst=JMP/reg=R8/offset=0", inst: JMP, dst: RegR8, dstOffset: 0, exp: []byte{0x41, 0xff, 0x20}}, 446 {name: "inst=JMP/reg=R8/offset=1", inst: JMP, dst: RegR8, dstOffset: 1, exp: []byte{0x41, 0xff, 0x60, 0x1}}, 447 {name: "inst=JMP/reg=R8/offset=-1", inst: JMP, dst: RegR8, dstOffset: -1, exp: []byte{0x41, 0xff, 0x60, 0xff}}, 448 {name: "inst=JMP/reg=R8/offset=1243", inst: JMP, dst: RegR8, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa0, 0xdb, 0x4, 0x0, 0x0}}, 449 {name: "inst=JMP/reg=R8/offset=2147483647", inst: JMP, dst: RegR8, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, 450 {name: "inst=JMP/reg=R8/offset=-32768", inst: JMP, dst: RegR8, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa0, 0x0, 0x80, 0xff, 0xff}}, 451 {name: "inst=JMP/reg=R9/offset=0", inst: JMP, dst: RegR9, dstOffset: 0, exp: []byte{0x41, 0xff, 0x21}}, 452 {name: "inst=JMP/reg=R9/offset=1", inst: JMP, dst: RegR9, dstOffset: 1, exp: []byte{0x41, 0xff, 0x61, 0x1}}, 453 {name: "inst=JMP/reg=R9/offset=-1", inst: JMP, dst: RegR9, dstOffset: -1, exp: []byte{0x41, 0xff, 0x61, 0xff}}, 454 {name: "inst=JMP/reg=R9/offset=1243", inst: JMP, dst: RegR9, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa1, 0xdb, 0x4, 0x0, 0x0}}, 455 {name: "inst=JMP/reg=R9/offset=2147483647", inst: JMP, dst: RegR9, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa1, 0xff, 0xff, 0xff, 0x7f}}, 456 {name: "inst=JMP/reg=R9/offset=-32768", inst: JMP, dst: RegR9, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa1, 0x0, 0x80, 0xff, 0xff}}, 457 {name: "inst=JMP/reg=R13/offset=0", inst: JMP, dst: RegR13, dstOffset: 0, exp: []byte{0x41, 0xff, 0x65, 0x0}}, 458 {name: "inst=JMP/reg=R13/offset=1", inst: JMP, dst: RegR13, dstOffset: 1, exp: []byte{0x41, 0xff, 0x65, 0x1}}, 459 {name: "inst=JMP/reg=R13/offset=-1", inst: JMP, dst: RegR13, dstOffset: -1, exp: []byte{0x41, 0xff, 0x65, 0xff}}, 460 {name: "inst=JMP/reg=R13/offset=1243", inst: JMP, dst: RegR13, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa5, 0xdb, 0x4, 0x0, 0x0}}, 461 {name: "inst=JMP/reg=R13/offset=2147483647", inst: JMP, dst: RegR13, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa5, 0xff, 0xff, 0xff, 0x7f}}, 462 {name: "inst=JMP/reg=R13/offset=-32768", inst: JMP, dst: RegR13, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa5, 0x0, 0x80, 0xff, 0xff}}, 463 {name: "inst=JMP/reg=R14/offset=0", inst: JMP, dst: RegR14, dstOffset: 0, exp: []byte{0x41, 0xff, 0x26}}, 464 {name: "inst=JMP/reg=R14/offset=1", inst: JMP, dst: RegR14, dstOffset: 1, exp: []byte{0x41, 0xff, 0x66, 0x1}}, 465 {name: "inst=JMP/reg=R14/offset=-1", inst: JMP, dst: RegR14, dstOffset: -1, exp: []byte{0x41, 0xff, 0x66, 0xff}}, 466 {name: "inst=JMP/reg=R14/offset=1243", inst: JMP, dst: RegR14, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa6, 0xdb, 0x4, 0x0, 0x0}}, 467 {name: "inst=JMP/reg=R14/offset=2147483647", inst: JMP, dst: RegR14, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa6, 0xff, 0xff, 0xff, 0x7f}}, 468 {name: "inst=JMP/reg=R14/offset=-32768", inst: JMP, dst: RegR14, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa6, 0x0, 0x80, 0xff, 0xff}}, 469 {name: "inst=JMP/reg=R15/offset=0", inst: JMP, dst: RegR15, dstOffset: 0, exp: []byte{0x41, 0xff, 0x27}}, 470 {name: "inst=JMP/reg=R15/offset=1", inst: JMP, dst: RegR15, dstOffset: 1, exp: []byte{0x41, 0xff, 0x67, 0x1}}, 471 {name: "inst=JMP/reg=R15/offset=-1", inst: JMP, dst: RegR15, dstOffset: -1, exp: []byte{0x41, 0xff, 0x67, 0xff}}, 472 {name: "inst=JMP/reg=R15/offset=1243", inst: JMP, dst: RegR15, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa7, 0xdb, 0x4, 0x0, 0x0}}, 473 {name: "inst=JMP/reg=R15/offset=2147483647", inst: JMP, dst: RegR15, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa7, 0xff, 0xff, 0xff, 0x7f}}, 474 {name: "inst=JMP/reg=R15/offset=-32768", inst: JMP, dst: RegR15, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa7, 0x0, 0x80, 0xff, 0xff}}, 475 } 476 477 for _, tc := range tests { 478 tc := tc 479 a := NewAssembler() 480 err := a.encodeNoneToMemory(&nodeImpl{ 481 types: operandTypesNoneToMemory, 482 instruction: tc.inst, dstReg: tc.dst, dstConst: tc.dstOffset, 483 }) 484 require.NoError(t, err, tc.name) 485 require.Equal(t, tc.exp, a.buf.Bytes(), tc.name) 486 } 487 } 488 489 func TestAssemblerImpl_EncodeRegisterToNone(t *testing.T) { 490 t.Run("error", func(t *testing.T) { 491 tests := []struct { 492 n *nodeImpl 493 expErr string 494 }{ 495 { 496 n: &nodeImpl{instruction: ADDL, types: operandTypesRegisterToNone, srcReg: RegAX}, 497 expErr: "ADDL is unsupported for from:register,to:none type", 498 }, 499 { 500 n: &nodeImpl{instruction: DIVQ, types: operandTypesRegisterToNone}, 501 expErr: "invalid register [nil]", 502 }, 503 } 504 505 for _, tc := range tests { 506 a := NewAssembler() 507 err := a.encodeRegisterToNone(tc.n) 508 require.EqualError(t, err, tc.expErr, tc, tc.expErr) 509 } 510 }) 511 512 tests := []struct { 513 name string 514 inst asm.Instruction 515 reg asm.Register 516 exp []byte 517 }{ 518 {name: "DIVL/reg=AX/", reg: RegAX, inst: DIVL, exp: []byte{0xf7, 0xf0}}, 519 {name: "DIVL/reg=BX/", reg: RegBX, inst: DIVL, exp: []byte{0xf7, 0xf3}}, 520 {name: "DIVL/reg=SP/", reg: RegSP, inst: DIVL, exp: []byte{0xf7, 0xf4}}, 521 {name: "DIVL/reg=BP/", reg: RegBP, inst: DIVL, exp: []byte{0xf7, 0xf5}}, 522 {name: "DIVL/reg=SI/", reg: RegSI, inst: DIVL, exp: []byte{0xf7, 0xf6}}, 523 {name: "DIVL/reg=DI/", reg: RegDI, inst: DIVL, exp: []byte{0xf7, 0xf7}}, 524 {name: "DIVL/reg=R8/", reg: RegR8, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf0}}, 525 {name: "DIVL/reg=R9/", reg: RegR9, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf1}}, 526 {name: "DIVL/reg=R13/", reg: RegR13, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf5}}, 527 {name: "DIVL/reg=R14/", reg: RegR14, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf6}}, 528 {name: "DIVL/reg=R15/", reg: RegR15, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf7}}, 529 {name: "DIVQ/reg=AX/", reg: RegAX, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf0}}, 530 {name: "DIVQ/reg=BX/", reg: RegBX, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf3}}, 531 {name: "DIVQ/reg=SP/", reg: RegSP, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf4}}, 532 {name: "DIVQ/reg=BP/", reg: RegBP, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf5}}, 533 {name: "DIVQ/reg=SI/", reg: RegSI, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf6}}, 534 {name: "DIVQ/reg=DI/", reg: RegDI, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf7}}, 535 {name: "DIVQ/reg=R8/", reg: RegR8, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf0}}, 536 {name: "DIVQ/reg=R9/", reg: RegR9, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf1}}, 537 {name: "DIVQ/reg=R13/", reg: RegR13, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf5}}, 538 {name: "DIVQ/reg=R14/", reg: RegR14, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf6}}, 539 {name: "DIVQ/reg=R15/", reg: RegR15, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf7}}, 540 {name: "IDIVL/reg=AX/", reg: RegAX, inst: IDIVL, exp: []byte{0xf7, 0xf8}}, 541 {name: "IDIVL/reg=BX/", reg: RegBX, inst: IDIVL, exp: []byte{0xf7, 0xfb}}, 542 {name: "IDIVL/reg=SP/", reg: RegSP, inst: IDIVL, exp: []byte{0xf7, 0xfc}}, 543 {name: "IDIVL/reg=BP/", reg: RegBP, inst: IDIVL, exp: []byte{0xf7, 0xfd}}, 544 {name: "IDIVL/reg=SI/", reg: RegSI, inst: IDIVL, exp: []byte{0xf7, 0xfe}}, 545 {name: "IDIVL/reg=DI/", reg: RegDI, inst: IDIVL, exp: []byte{0xf7, 0xff}}, 546 {name: "IDIVL/reg=R8/", reg: RegR8, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xf8}}, 547 {name: "IDIVL/reg=R9/", reg: RegR9, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xf9}}, 548 {name: "IDIVL/reg=R13/", reg: RegR13, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xfd}}, 549 {name: "IDIVL/reg=R14/", reg: RegR14, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xfe}}, 550 {name: "IDIVL/reg=R15/", reg: RegR15, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xff}}, 551 {name: "IDIVQ/reg=AX/", reg: RegAX, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xf8}}, 552 {name: "IDIVQ/reg=BX/", reg: RegBX, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfb}}, 553 {name: "IDIVQ/reg=SP/", reg: RegSP, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfc}}, 554 {name: "IDIVQ/reg=BP/", reg: RegBP, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfd}}, 555 {name: "IDIVQ/reg=SI/", reg: RegSI, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfe}}, 556 {name: "IDIVQ/reg=DI/", reg: RegDI, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xff}}, 557 {name: "IDIVQ/reg=R8/", reg: RegR8, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xf8}}, 558 {name: "IDIVQ/reg=R9/", reg: RegR9, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xf9}}, 559 {name: "IDIVQ/reg=R13/", reg: RegR13, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xfd}}, 560 {name: "IDIVQ/reg=R14/", reg: RegR14, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xfe}}, 561 {name: "IDIVQ/reg=R15/", reg: RegR15, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xff}}, 562 {name: "MULL/reg=AX/", reg: RegAX, inst: MULL, exp: []byte{0xf7, 0xe0}}, 563 {name: "MULL/reg=BX/", reg: RegBX, inst: MULL, exp: []byte{0xf7, 0xe3}}, 564 {name: "MULL/reg=SP/", reg: RegSP, inst: MULL, exp: []byte{0xf7, 0xe4}}, 565 {name: "MULL/reg=BP/", reg: RegBP, inst: MULL, exp: []byte{0xf7, 0xe5}}, 566 {name: "MULL/reg=SI/", reg: RegSI, inst: MULL, exp: []byte{0xf7, 0xe6}}, 567 {name: "MULL/reg=DI/", reg: RegDI, inst: MULL, exp: []byte{0xf7, 0xe7}}, 568 {name: "MULL/reg=R8/", reg: RegR8, inst: MULL, exp: []byte{0x41, 0xf7, 0xe0}}, 569 {name: "MULL/reg=R9/", reg: RegR9, inst: MULL, exp: []byte{0x41, 0xf7, 0xe1}}, 570 {name: "MULL/reg=R13/", reg: RegR13, inst: MULL, exp: []byte{0x41, 0xf7, 0xe5}}, 571 {name: "MULL/reg=R14/", reg: RegR14, inst: MULL, exp: []byte{0x41, 0xf7, 0xe6}}, 572 {name: "MULL/reg=R15/", reg: RegR15, inst: MULL, exp: []byte{0x41, 0xf7, 0xe7}}, 573 {name: "MULQ/reg=AX/", reg: RegAX, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe0}}, 574 {name: "MULQ/reg=BX/", reg: RegBX, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe3}}, 575 {name: "MULQ/reg=SP/", reg: RegSP, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe4}}, 576 {name: "MULQ/reg=BP/", reg: RegBP, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe5}}, 577 {name: "MULQ/reg=SI/", reg: RegSI, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe6}}, 578 {name: "MULQ/reg=DI/", reg: RegDI, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe7}}, 579 {name: "MULQ/reg=R8/", reg: RegR8, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe0}}, 580 {name: "MULQ/reg=R9/", reg: RegR9, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe1}}, 581 {name: "MULQ/reg=R13/", reg: RegR13, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe5}}, 582 {name: "MULQ/reg=R14/", reg: RegR14, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe6}}, 583 {name: "MULQ/reg=R15/", reg: RegR15, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe7}}, 584 } 585 586 for _, tc := range tests { 587 a := NewAssembler() 588 err := a.encodeRegisterToNone(&nodeImpl{ 589 instruction: tc.inst, 590 types: operandTypesRegisterToNone, srcReg: tc.reg, 591 }) 592 require.NoError(t, err, tc.name) 593 require.Equal(t, tc.exp, a.buf.Bytes(), tc.name) 594 } 595 } 596 597 func TestAssemblerImpl_EncodeRegisterToRegister(t *testing.T) { 598 t.Run("error", func(t *testing.T) { 599 tests := []struct { 600 n *nodeImpl 601 expErr string 602 }{ 603 { 604 n: &nodeImpl{instruction: JMP, types: operandTypesRegisterToRegister, srcReg: RegAX, dstReg: RegAX}, 605 expErr: "JMP is unsupported for from:register,to:register type", 606 }, 607 { 608 n: &nodeImpl{instruction: ADDL, types: operandTypesRegisterToRegister, dstReg: RegAX}, 609 expErr: "invalid register [nil]", 610 }, 611 { 612 n: &nodeImpl{instruction: ADDL, types: operandTypesRegisterToRegister, srcReg: RegAX}, 613 expErr: "invalid register [nil]", 614 }, 615 { 616 n: &nodeImpl{instruction: MOVL, types: operandTypesRegisterToRegister, srcReg: RegX0, dstReg: RegX1}, 617 expErr: "MOVL for float to float is undefined", 618 }, 619 } 620 621 for _, tc := range tests { 622 a := NewAssembler() 623 err := a.encodeRegisterToRegister(tc.n) 624 require.EqualError(t, err, tc.expErr) 625 } 626 }) 627 628 tests := []struct { 629 name string 630 n *nodeImpl 631 exp []byte 632 }{ 633 {name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0xf3, 0x44, 0xf, 0x6f, 0xd3}}, 634 {name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX10, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x6f, 0xda}}, 635 {name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX10, dstReg: RegX15}, exp: []byte{0xf3, 0x45, 0xf, 0x6f, 0xfa}}, 636 {name: "MOVDQA", n: &nodeImpl{instruction: MOVDQA, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x6f, 0xd3}}, 637 {name: "MOVDQA", n: &nodeImpl{instruction: MOVDQA, srcReg: RegX10, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x6f, 0xda}}, 638 {name: "MOVDQA", n: &nodeImpl{instruction: MOVDQA, srcReg: RegX10, dstReg: RegX15}, exp: []byte{0x66, 0x45, 0xf, 0x6f, 0xfa}}, 639 {name: "PACKSSWB", n: &nodeImpl{instruction: PACKSSWB, srcReg: RegX10, dstReg: RegX15}, exp: []byte{0x66, 0x45, 0xf, 0x63, 0xfa}}, 640 {name: "pmovmskb r15d, xmm10", n: &nodeImpl{instruction: PMOVMSKB, srcReg: RegX10, dstReg: RegR15}, exp: []byte{0x66, 0x45, 0xf, 0xd7, 0xfa}}, 641 {name: "movmskps eax, xmm10", n: &nodeImpl{instruction: MOVMSKPS, srcReg: RegX10, dstReg: RegAX}, exp: []byte{0x41, 0xf, 0x50, 0xc2}}, 642 {name: "movmskps r13d, xmm1", n: &nodeImpl{instruction: MOVMSKPS, srcReg: RegX1, dstReg: RegR13}, exp: []byte{0x44, 0xf, 0x50, 0xe9}}, 643 {name: "movmskpd eax, xmm10", n: &nodeImpl{instruction: MOVMSKPD, srcReg: RegX10, dstReg: RegAX}, exp: []byte{0x66, 0x41, 0xf, 0x50, 0xc2}}, 644 {name: "movmskpd r15d, xmm1", n: &nodeImpl{instruction: MOVMSKPD, srcReg: RegX1, dstReg: RegR15}, exp: []byte{0x66, 0x44, 0xf, 0x50, 0xf9}}, 645 {name: "pand xmm15, xmm1", n: &nodeImpl{instruction: PAND, srcReg: RegX1, dstReg: RegX15}, exp: []byte{0x66, 0x44, 0xf, 0xdb, 0xf9}}, 646 {name: "por xmm1, xmm15", n: &nodeImpl{instruction: POR, srcReg: RegX15, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xeb, 0xcf}}, 647 {name: "pandn xmm13, xmm15", n: &nodeImpl{instruction: PANDN, srcReg: RegX15, dstReg: RegX13}, exp: []byte{0x66, 0x45, 0xf, 0xdf, 0xef}}, 648 {name: "psrad xmm13, xmm15", n: &nodeImpl{instruction: PSRAD, srcReg: RegX15, dstReg: RegX13}, exp: []byte{0x66, 0x45, 0xf, 0xe2, 0xef}}, 649 {name: "psraw xmm1, xmm1", n: &nodeImpl{instruction: PSRAW, srcReg: RegX1, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0xe1, 0xc9}}, 650 {name: "psrlq xmm14, xmm14", n: &nodeImpl{instruction: PSRLQ, srcReg: RegX14, dstReg: RegX14}, exp: []byte{0x66, 0x45, 0xf, 0xd3, 0xf6}}, 651 {name: "psrld xmm3, xmm3", n: &nodeImpl{instruction: PSRLD, srcReg: RegX3, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0xd2, 0xdb}}, 652 {name: "psrlw xmm15, xmm1", n: &nodeImpl{instruction: PSRLW, srcReg: RegX1, dstReg: RegX15}, exp: []byte{0x66, 0x44, 0xf, 0xd1, 0xf9}}, 653 {name: "psllw xmm1, xmm15", n: &nodeImpl{instruction: PSLLW, srcReg: RegX15, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xf1, 0xcf}}, 654 {name: "punpcklbw xmm1, xmm15", n: &nodeImpl{instruction: PUNPCKLBW, srcReg: RegX15, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x60, 0xcf}}, 655 {name: "punpckhbw xmm11, xmm1", n: &nodeImpl{instruction: PUNPCKHBW, srcReg: RegX1, dstReg: RegX11}, exp: []byte{0x66, 0x44, 0xf, 0x68, 0xd9}}, 656 {name: "pslld xmm11, xmm1", n: &nodeImpl{instruction: PSLLD, srcReg: RegX1, dstReg: RegX11}, exp: []byte{0x66, 0x44, 0xf, 0xf2, 0xd9}}, 657 {name: "psllq xmm11, xmm15", n: &nodeImpl{instruction: PSLLQ, srcReg: RegX15, dstReg: RegX11}, exp: []byte{0x66, 0x45, 0xf, 0xf3, 0xdf}}, 658 { 659 name: "cmpeqps xmm11, xmm15", n: &nodeImpl{instruction: CMPPS, srcReg: RegX15, dstReg: RegX11, arg: 0}, // CMPPS with arg=0 == Pseudo-Op CMPEQPS. 660 exp: []byte{0x45, 0xf, 0xc2, 0xdf, 0x0}, 661 }, 662 { 663 name: "cmpordps xmm1, xmm5", n: &nodeImpl{instruction: CMPPS, srcReg: RegX5, dstReg: RegX1, arg: 7}, // CMPPS with arg=7 == Pseudo-Op CMPORDPS. 664 exp: []byte{0xf, 0xc2, 0xcd, 0x7}, 665 }, 666 {name: "cmplepd xmm11, xmm15", n: &nodeImpl{instruction: CMPPD, srcReg: RegX15, dstReg: RegX11, arg: 2}, // CMPPD with arg=2 == Pseudo-Op CMPLEPD. 667 exp: []byte{0x66, 0x45, 0xf, 0xc2, 0xdf, 0x2}}, 668 { 669 name: "cmpneqpd xmm1, xmm5", n: &nodeImpl{instruction: CMPPD, srcReg: RegX5, dstReg: RegX1, arg: 4}, // CMPPD with arg=4 == Pseudo-Op CMPNEQPD. 670 exp: []byte{0x66, 0xf, 0xc2, 0xcd, 0x4}, 671 }, 672 {name: "pcmpgtq xmm10, xmm3", n: &nodeImpl{instruction: PCMPGTQ, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x37, 0xd3}}, 673 {name: "pcmpgtd xmm10, xmm3", n: &nodeImpl{instruction: PCMPGTD, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x66, 0xd3}}, 674 {name: "pminsd xmm10, xmm3", n: &nodeImpl{instruction: PMINSD, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x39, 0xd3}}, 675 {name: "pmaxsd xmm1, xmm12", n: &nodeImpl{instruction: PMAXSD, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x3d, 0xcc}}, 676 {name: "pmaxsw xmm1, xmm12", n: &nodeImpl{instruction: PMAXSW, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xee, 0xcc}}, 677 {name: "pminsw xmm1, xmm12", n: &nodeImpl{instruction: PMINSW, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xea, 0xcc}}, 678 {name: "pcmpgtb xmm1, xmm12", n: &nodeImpl{instruction: PCMPGTB, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x64, 0xcc}}, 679 {name: "pminsb xmm1, xmm12", n: &nodeImpl{instruction: PMINSB, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x38, 0xcc}}, 680 {name: "pmaxsb xmm1, xmm2", n: &nodeImpl{instruction: PMAXSB, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3c, 0xca}}, 681 {name: "pminud xmm1, xmm2", n: &nodeImpl{instruction: PMINUD, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3b, 0xca}}, 682 {name: "pminuw xmm1, xmm2", n: &nodeImpl{instruction: PMINUW, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3a, 0xca}}, 683 {name: "pminub xmm1, xmm2", n: &nodeImpl{instruction: PMINUB, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0xda, 0xca}}, 684 {name: "pmaxud xmm1, xmm2", n: &nodeImpl{instruction: PMAXUD, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3f, 0xca}}, 685 {name: "pmaxuw xmm1, xmm2", n: &nodeImpl{instruction: PMAXUW, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3e, 0xca}}, 686 {name: "pmaxub xmm1, xmm2", n: &nodeImpl{instruction: PMAXUB, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0xde, 0xca}}, 687 {name: "pcmpgtw xmm1, xmm2", n: &nodeImpl{instruction: PCMPGTW, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x65, 0xca}}, 688 {name: "pmullw xmm13, xmm1", n: &nodeImpl{instruction: PMULLW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xd5, 0xe9}}, 689 {name: "pmulld xmm1, xmm11", n: &nodeImpl{instruction: PMULLD, srcReg: RegX11, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x40, 0xcb}}, 690 {name: "pmuludq xmm13, xmm1", n: &nodeImpl{instruction: PMULUDQ, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xf4, 0xe9}}, 691 {name: "psubsb xmm13, xmm1", n: &nodeImpl{instruction: PSUBSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe8, 0xe9}}, 692 {name: "psubsw xmm13, xmm1", n: &nodeImpl{instruction: PSUBSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe9, 0xe9}}, 693 {name: "psubusb xmm13, xmm1", n: &nodeImpl{instruction: PSUBUSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xd8, 0xe9}}, 694 {name: "psubusw xmm13, xmm1", n: &nodeImpl{instruction: PSUBUSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xd9, 0xe9}}, 695 {name: "paddsw xmm13, xmm1", n: &nodeImpl{instruction: PADDSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xed, 0xe9}}, 696 {name: "paddsb xmm13, xmm1", n: &nodeImpl{instruction: PADDSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xec, 0xe9}}, 697 {name: "paddusw xmm13, xmm1", n: &nodeImpl{instruction: PADDUSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xdd, 0xe9}}, 698 {name: "pavgb xmm13, xmm1", n: &nodeImpl{instruction: PAVGB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe0, 0xe9}}, 699 {name: "pavgw xmm13, xmm1", n: &nodeImpl{instruction: PAVGW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe3, 0xe9}}, 700 {name: "pabsb xmm13, xmm1", n: &nodeImpl{instruction: PABSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x1c, 0xe9}}, 701 {name: "pabsw xmm13, xmm1", n: &nodeImpl{instruction: PABSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x1d, 0xe9}}, 702 {name: "pabsd xmm13, xmm1", n: &nodeImpl{instruction: PABSD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x1e, 0xe9}}, 703 {name: "blendvpd xmm13, xmm1", n: &nodeImpl{instruction: BLENDVPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x15, 0xe9}}, 704 {name: "maxpd xmm13, xmm1", n: &nodeImpl{instruction: MAXPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x5f, 0xe9}}, 705 {name: "maxps xmm13, xmm1", n: &nodeImpl{instruction: MAXPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x5f, 0xe9}}, 706 {name: "minpd xmm13, xmm1", n: &nodeImpl{instruction: MINPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x5d, 0xe9}}, 707 {name: "minps xmm13, xmm1", n: &nodeImpl{instruction: MINPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x5d, 0xe9}}, 708 {name: "andnpd xmm13, xmm1", n: &nodeImpl{instruction: ANDNPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x55, 0xe9}}, 709 {name: "andnps xmm13, xmm1", n: &nodeImpl{instruction: ANDNPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x55, 0xe9}}, 710 {name: "mulps xmm13, xmm1", n: &nodeImpl{instruction: MULPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x59, 0xe9}}, 711 {name: "mulpd xmm13, xmm1", n: &nodeImpl{instruction: MULPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x59, 0xe9}}, 712 {name: "divps xmm13, xmm1", n: &nodeImpl{instruction: DIVPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x5e, 0xe9}}, 713 {name: "divpd xmm13, xmm1", n: &nodeImpl{instruction: DIVPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x5e, 0xe9}}, 714 {name: "sqrtps xmm13, xmm1", n: &nodeImpl{instruction: SQRTPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x51, 0xe9}}, 715 {name: "sqrtpd xmm13, xmm1", n: &nodeImpl{instruction: SQRTPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x51, 0xe9}}, 716 {name: "roundps xmm13, xmm1, 0", n: &nodeImpl{instruction: ROUNDPS, srcReg: RegX1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x8, 0xe9, 0x0}}, 717 {name: "roundps xmm13, xmm1, 1", n: &nodeImpl{instruction: ROUNDPS, srcReg: RegX1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x8, 0xe9, 0x1}}, 718 {name: "roundps xmm13, xmm1, 3", n: &nodeImpl{instruction: ROUNDPS, srcReg: RegX1, dstReg: RegX13, arg: 3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x8, 0xe9, 0x3}}, 719 {name: "roundpd xmm13, xmm1, 0", n: &nodeImpl{instruction: ROUNDPD, srcReg: RegX1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x9, 0xe9, 0x0}}, 720 {name: "roundpd xmm13, xmm1, 1", n: &nodeImpl{instruction: ROUNDPD, srcReg: RegX1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x9, 0xe9, 0x1}}, 721 {name: "roundpd xmm13, xmm1, 3", n: &nodeImpl{instruction: ROUNDPD, srcReg: RegX1, dstReg: RegX13, arg: 3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x9, 0xe9, 0x3}}, 722 {name: "palignr xmm13, xmm1, 3", n: &nodeImpl{instruction: PALIGNR, srcReg: RegX1, dstReg: RegX13, arg: 3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xf, 0xe9, 0x3}}, 723 {name: "punpcklwd xmm13, xmm1", n: &nodeImpl{instruction: PUNPCKLWD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x61, 0xe9}}, 724 {name: "punpckhwd xmm13, xmm1", n: &nodeImpl{instruction: PUNPCKHWD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x69, 0xe9}}, 725 {name: "pmulhuw xmm13, xmm1", n: &nodeImpl{instruction: PMULHUW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe4, 0xe9}}, 726 {name: "pmuldq xmm13, xmm1", n: &nodeImpl{instruction: PMULDQ, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x28, 0xe9}}, 727 {name: "pmulhrsw xmm13, xmm1", n: &nodeImpl{instruction: PMULHRSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0xb, 0xe9}}, 728 {name: "pmovsxbw xmm5, xmm10", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x20, 0xea}}, 729 {name: "pmovsxwd xmm5, xmm10", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x23, 0xea}}, 730 {name: "pmovsxdq xmm5, xmm10", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x25, 0xea}}, 731 {name: "pmovzxbw xmm5, xmm10", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x30, 0xea}}, 732 {name: "pmovzxwd xmm5, xmm10", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x33, 0xea}}, 733 {name: "pmovzxdq xmm5, xmm10", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x35, 0xea}}, 734 {name: "pmulhw xmm2, xmm1", n: &nodeImpl{instruction: PMULHW, srcReg: RegX1, dstReg: RegX2}, exp: []byte{0x66, 0xf, 0xe5, 0xd1}}, 735 {name: "cmpltps xmm1, xmm14", n: &nodeImpl{instruction: CMPEQPS, srcReg: RegX14, dstReg: RegX1, arg: 1}, exp: []byte{0x41, 0xf, 0xc2, 0xce, 0x1}}, 736 {name: "cmpunordpd xmm1, xmm14", n: &nodeImpl{instruction: CMPEQPD, srcReg: RegX14, dstReg: RegX1, arg: 3}, exp: []byte{0x66, 0x41, 0xf, 0xc2, 0xce, 0x3}}, 737 {name: "cvttps2dq xmm1, xmm14", n: &nodeImpl{instruction: CVTTPS2DQ, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0xf3, 0x41, 0xf, 0x5b, 0xce}}, 738 {name: "cvtdq2ps xmm1, xmm14", n: &nodeImpl{instruction: CVTDQ2PS, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x41, 0xf, 0x5b, 0xce}}, 739 {name: "movupd xmm1, xmm14", n: &nodeImpl{instruction: MOVUPD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x10, 0xce}}, 740 {name: "shufps xmm1, xmm14, 5", n: &nodeImpl{instruction: SHUFPS, srcReg: RegX14, dstReg: RegX1, arg: 5}, exp: []byte{0x41, 0xf, 0xc6, 0xce, 0x5}}, 741 {name: "pmaddwd xmm1, xmm14", n: &nodeImpl{instruction: PMADDWD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xf5, 0xce}}, 742 {name: "cvtdq2pd xmm1, xmm14", n: &nodeImpl{instruction: CVTDQ2PD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0xf3, 0x41, 0xf, 0xe6, 0xce}}, 743 {name: "unpcklps xmm1, xmm14", n: &nodeImpl{instruction: UNPCKLPS, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x41, 0xf, 0x14, 0xce}}, 744 {name: "packuswb xmm1, xmm14", n: &nodeImpl{instruction: PACKUSWB, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x67, 0xce}}, 745 {name: "packssdw xmm1, xmm14", n: &nodeImpl{instruction: PACKSSDW, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x6b, 0xce}}, 746 {name: "packusdw xmm1, xmm14", n: &nodeImpl{instruction: PACKUSDW, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x2b, 0xce}}, 747 {name: "cvtps2pd xmm1, xmm14", n: &nodeImpl{instruction: CVTPS2PD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x41, 0xf, 0x5a, 0xce}}, 748 {name: "cvtpd2ps xmm1, xmm14", n: &nodeImpl{instruction: CVTPD2PS, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x5a, 0xce}}, 749 {name: "pmaddubsw xmm1, xmm14", n: &nodeImpl{instruction: PMADDUBSW, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x4, 0xce}}, 750 {name: "cvttpd2dq xmm1, xmm14", n: &nodeImpl{instruction: CVTTPD2DQ, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xe6, 0xce}}, 751 {name: "PADDB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfc, 0xc0}}, 752 {name: "PADDB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfc, 0xc0}}, 753 {name: "PADDB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfc, 0xc0}}, 754 {name: "PADDB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfc, 0xc0}}, 755 {name: "PADDW/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfd, 0xc0}}, 756 {name: "PADDW/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfd, 0xc0}}, 757 {name: "PADDW/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfd, 0xc0}}, 758 {name: "PADDW/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfd, 0xc0}}, 759 {name: "PADDD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfe, 0xc0}}, 760 {name: "PADDD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfe, 0xc0}}, 761 {name: "PADDD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfe, 0xc0}}, 762 {name: "PADDD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfe, 0xc0}}, 763 {name: "PADDQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xd4, 0xc0}}, 764 {name: "PADDQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xd4, 0xc0}}, 765 {name: "PADDQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xd4, 0xc0}}, 766 {name: "PADDQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xd4, 0xc0}}, 767 {name: "ADDPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x58, 0xc0}}, 768 {name: "ADDPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x58, 0xc0}}, 769 {name: "ADDPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x58, 0xc0}}, 770 {name: "ADDPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x58, 0xc0}}, 771 {name: "ADDPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x58, 0xc0}}, 772 {name: "ADDPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x58, 0xc0}}, 773 {name: "ADDPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x58, 0xc0}}, 774 {name: "ADDPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x58, 0xc0}}, 775 {name: "PSUBB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xf8, 0xc0}}, 776 {name: "PSUBB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xf8, 0xc0}}, 777 {name: "PSUBB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xf8, 0xc0}}, 778 {name: "PSUBB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xf8, 0xc0}}, 779 {name: "PSUBW/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xf9, 0xc0}}, 780 {name: "PSUBW/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xf9, 0xc0}}, 781 {name: "PSUBW/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xf9, 0xc0}}, 782 {name: "PSUBW/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xf9, 0xc0}}, 783 {name: "PSUBL/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfa, 0xc0}}, 784 {name: "PSUBL/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfa, 0xc0}}, 785 {name: "PSUBL/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfa, 0xc0}}, 786 {name: "PSUBL/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfa, 0xc0}}, 787 {name: "PSUBQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfb, 0xc0}}, 788 {name: "PSUBQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfb, 0xc0}}, 789 {name: "PSUBQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfb, 0xc0}}, 790 {name: "PSUBQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfb, 0xc0}}, 791 {name: "SUBPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x5c, 0xc0}}, 792 {name: "SUBPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x5c, 0xc0}}, 793 {name: "SUBPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x5c, 0xc0}}, 794 {name: "SUBPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x5c, 0xc0}}, 795 {name: "SUBPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x5c, 0xc0}}, 796 {name: "SUBPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x5c, 0xc0}}, 797 {name: "SUBPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x5c, 0xc0}}, 798 {name: "SUBPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x5c, 0xc0}}, 799 {name: "PINSRQ/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, 800 {name: "PINSRQ/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, 801 {name: "PINSRQ/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x49, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, 802 {name: "PINSRQ/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x4d, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, 803 {name: "PINSRQ/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, 804 {name: "PINSRQ/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, 805 {name: "PINSRQ/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x49, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, 806 {name: "PINSRQ/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4d, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, 807 {name: "PINSRD/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, 808 {name: "PINSRD/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, 809 {name: "PINSRD/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, 810 {name: "PINSRD/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, 811 {name: "PINSRD/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, 812 {name: "PINSRD/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, 813 {name: "PINSRD/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, 814 {name: "PINSRD/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, 815 {name: "PINSRW/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0xc4, 0xc0, 0x1}}, 816 {name: "PINSRW/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xc0, 0x1}}, 817 {name: "PINSRW/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0xc4, 0xc0, 0x1}}, 818 {name: "PINSRW/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0xc4, 0xc0, 0x1}}, 819 {name: "PINSRW/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xc4, 0xc0, 0x0}}, 820 {name: "PINSRW/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xc0, 0x0}}, 821 {name: "PINSRW/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xc4, 0xc0, 0x0}}, 822 {name: "PINSRW/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xc4, 0xc0, 0x0}}, 823 {name: "PINSRB/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0xc0, 0x1}}, 824 {name: "PINSRB/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xc0, 0x1}}, 825 {name: "PINSRB/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x20, 0xc0, 0x1}}, 826 {name: "PINSRB/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x20, 0xc0, 0x1}}, 827 {name: "PINSRB/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0xc0, 0x0}}, 828 {name: "PINSRB/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xc0, 0x0}}, 829 {name: "PINSRB/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x20, 0xc0, 0x0}}, 830 {name: "PINSRB/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x20, 0xc0, 0x0}}, 831 {name: "ADDL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x1, 0xc0}}, 832 {name: "ADDL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x1, 0xc0}}, 833 {name: "ADDL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x1, 0xc0}}, 834 {name: "ADDL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x1, 0xc0}}, 835 {name: "ADDQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x1, 0xc0}}, 836 {name: "ADDQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x1, 0xc0}}, 837 {name: "ADDQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x1, 0xc0}}, 838 {name: "ADDQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x1, 0xc0}}, 839 {name: "ADDSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x58, 0xc0}}, 840 {name: "ADDSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x58, 0xc0}}, 841 {name: "ADDSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x58, 0xc0}}, 842 {name: "ADDSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x58, 0xc0}}, 843 {name: "ADDSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x58, 0xc0}}, 844 {name: "ADDSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x58, 0xc0}}, 845 {name: "ADDSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x58, 0xc0}}, 846 {name: "ADDSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x58, 0xc0}}, 847 {name: "ANDL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x21, 0xc0}}, 848 {name: "ANDL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x21, 0xc0}}, 849 {name: "ANDL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x21, 0xc0}}, 850 {name: "ANDL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x21, 0xc0}}, 851 {name: "ANDPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x54, 0xc0}}, 852 {name: "ANDPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x54, 0xc0}}, 853 {name: "ANDPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x54, 0xc0}}, 854 {name: "ANDPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x54, 0xc0}}, 855 {name: "ANDPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x54, 0xc0}}, 856 {name: "ANDPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x54, 0xc0}}, 857 {name: "ANDPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x54, 0xc0}}, 858 {name: "ANDPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x54, 0xc0}}, 859 {name: "ANDQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x21, 0xc0}}, 860 {name: "ANDQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x21, 0xc0}}, 861 {name: "ANDQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x21, 0xc0}}, 862 {name: "ANDQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x21, 0xc0}}, 863 {name: "BSRL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xbd, 0xc0}}, 864 {name: "BSRL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xbd, 0xc0}}, 865 {name: "BSRL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xbd, 0xc0}}, 866 {name: "BSRL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xbd, 0xc0}}, 867 {name: "BSRQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xbd, 0xc0}}, 868 {name: "BSRQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0xbd, 0xc0}}, 869 {name: "BSRQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xbd, 0xc0}}, 870 {name: "BSRQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xbd, 0xc0}}, 871 {name: "CMOVQCS/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0x42, 0xc0}}, 872 {name: "CMOVQCS/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0x42, 0xc0}}, 873 {name: "CMOVQCS/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0x42, 0xc0}}, 874 {name: "CMOVQCS/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0x42, 0xc0}}, 875 {name: "CMPL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x39, 0xc0}}, 876 {name: "CMPL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0x39, 0xc0}}, 877 {name: "CMPL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0x39, 0xc0}}, 878 {name: "CMPL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x39, 0xc0}}, 879 {name: "CMPQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x39, 0xc0}}, 880 {name: "CMPQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0x39, 0xc0}}, 881 {name: "CMPQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0x39, 0xc0}}, 882 {name: "CMPQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x39, 0xc0}}, 883 {name: "COMISD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x2f, 0xc0}}, 884 {name: "COMISD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x2f, 0xc0}}, 885 {name: "COMISD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x2f, 0xc0}}, 886 {name: "COMISD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x2f, 0xc0}}, 887 {name: "COMISS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x2f, 0xc0}}, 888 {name: "COMISS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x2f, 0xc0}}, 889 {name: "COMISS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x2f, 0xc0}}, 890 {name: "COMISS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x2f, 0xc0}}, 891 {name: "CVTSD2SS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5a, 0xc0}}, 892 {name: "CVTSD2SS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5a, 0xc0}}, 893 {name: "CVTSD2SS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5a, 0xc0}}, 894 {name: "CVTSD2SS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5a, 0xc0}}, 895 {name: "CVTSL2SD/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x2a, 0xc0}}, 896 {name: "CVTSL2SD/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x2a, 0xc0}}, 897 {name: "CVTSL2SD/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x2a, 0xc0}}, 898 {name: "CVTSL2SD/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x2a, 0xc0}}, 899 {name: "CVTSL2SS/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x2a, 0xc0}}, 900 {name: "CVTSL2SS/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x2a, 0xc0}}, 901 {name: "CVTSL2SS/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x2a, 0xc0}}, 902 {name: "CVTSL2SS/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x2a, 0xc0}}, 903 {name: "CVTSQ2SD/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x48, 0xf, 0x2a, 0xc0}}, 904 {name: "CVTSQ2SD/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x4c, 0xf, 0x2a, 0xc0}}, 905 {name: "CVTSQ2SD/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x49, 0xf, 0x2a, 0xc0}}, 906 {name: "CVTSQ2SD/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x4d, 0xf, 0x2a, 0xc0}}, 907 {name: "CVTSQ2SS/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0x2a, 0xc0}}, 908 {name: "CVTSQ2SS/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0x2a, 0xc0}}, 909 {name: "CVTSQ2SS/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0x2a, 0xc0}}, 910 {name: "CVTSQ2SS/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0x2a, 0xc0}}, 911 {name: "CVTSS2SD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5a, 0xc0}}, 912 {name: "CVTSS2SD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5a, 0xc0}}, 913 {name: "CVTSS2SD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5a, 0xc0}}, 914 {name: "CVTSS2SD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5a, 0xc0}}, 915 {name: "CVTTSD2SL/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x2c, 0xc0}}, 916 {name: "CVTTSD2SL/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x2c, 0xc0}}, 917 {name: "CVTTSD2SL/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x2c, 0xc0}}, 918 {name: "CVTTSD2SL/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x2c, 0xc0}}, 919 {name: "CVTTSD2SQ/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0x48, 0xf, 0x2c, 0xc0}}, 920 {name: "CVTTSD2SQ/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x4c, 0xf, 0x2c, 0xc0}}, 921 {name: "CVTTSD2SQ/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0x49, 0xf, 0x2c, 0xc0}}, 922 {name: "CVTTSD2SQ/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x4d, 0xf, 0x2c, 0xc0}}, 923 {name: "CVTTSS2SL/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x2c, 0xc0}}, 924 {name: "CVTTSS2SL/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x2c, 0xc0}}, 925 {name: "CVTTSS2SL/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x2c, 0xc0}}, 926 {name: "CVTTSS2SL/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x2c, 0xc0}}, 927 {name: "CVTTSS2SQ/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0x2c, 0xc0}}, 928 {name: "CVTTSS2SQ/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0x2c, 0xc0}}, 929 {name: "CVTTSS2SQ/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0x2c, 0xc0}}, 930 {name: "CVTTSS2SQ/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0x2c, 0xc0}}, 931 {name: "DIVSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5e, 0xc0}}, 932 {name: "DIVSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5e, 0xc0}}, 933 {name: "DIVSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5e, 0xc0}}, 934 {name: "DIVSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5e, 0xc0}}, 935 {name: "DIVSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5e, 0xc0}}, 936 {name: "DIVSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5e, 0xc0}}, 937 {name: "DIVSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5e, 0xc0}}, 938 {name: "DIVSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5e, 0xc0}}, 939 {name: "LZCNTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0xbd, 0xc0}}, 940 {name: "LZCNTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0xbd, 0xc0}}, 941 {name: "LZCNTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0xbd, 0xc0}}, 942 {name: "LZCNTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0xbd, 0xc0}}, 943 {name: "LZCNTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0xbd, 0xc0}}, 944 {name: "LZCNTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0xbd, 0xc0}}, 945 {name: "LZCNTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0xbd, 0xc0}}, 946 {name: "LZCNTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0xbd, 0xc0}}, 947 {name: "MAXSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5f, 0xc0}}, 948 {name: "MAXSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5f, 0xc0}}, 949 {name: "MAXSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5f, 0xc0}}, 950 {name: "MAXSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5f, 0xc0}}, 951 {name: "MINSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5d, 0xc0}}, 952 {name: "MINSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5d, 0xc0}}, 953 {name: "MINSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5d, 0xc0}}, 954 {name: "MINSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5d, 0xc0}}, 955 {name: "MAXSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5f, 0xc0}}, 956 {name: "MAXSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5f, 0xc0}}, 957 {name: "MAXSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5f, 0xc0}}, 958 {name: "MAXSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5f, 0xc0}}, 959 {name: "MINSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5d, 0xc0}}, 960 {name: "MINSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5d, 0xc0}}, 961 {name: "MINSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5d, 0xc0}}, 962 {name: "MINSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5d, 0xc0}}, 963 {name: "MOVBLSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xbe, 0xc0}}, 964 {name: "MOVBLSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xbe, 0xc0}}, 965 {name: "MOVBLSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xbe, 0xc0}}, 966 {name: "MOVBLSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xbe, 0xc0}}, 967 {name: "MOVWLZX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xb7, 0xc0}}, 968 {name: "MOVWLZX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xb7, 0xc0}}, 969 {name: "MOVWLZX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xb7, 0xc0}}, 970 {name: "MOVWLZX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xb7, 0xc0}}, 971 {name: "MOVBLZX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xb6, 0xc0}}, 972 {name: "MOVBLZX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xb6, 0xc0}}, 973 {name: "MOVBLZX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xb6, 0xc0}}, 974 {name: "MOVBLZX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xb6, 0xc0}}, 975 {name: "MOVBQSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xbe, 0xc0}}, 976 {name: "MOVBQSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0xbe, 0xc0}}, 977 {name: "MOVBQSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xbe, 0xc0}}, 978 {name: "MOVBQSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xbe, 0xc0}}, 979 {name: "MOVLQSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x63, 0xc0}}, 980 {name: "MOVLQSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0x63, 0xc0}}, 981 {name: "MOVLQSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0x63, 0xc0}}, 982 {name: "MOVLQSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x63, 0xc0}}, 983 {name: "MOVL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x89, 0xc0}}, 984 {name: "MOVL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x89, 0xc0}}, 985 {name: "MOVL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x89, 0xc0}}, 986 {name: "MOVL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x89, 0xc0}}, 987 {name: "MOVL/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x6e, 0xc0}}, 988 {name: "MOVL/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x6e, 0xc0}}, 989 {name: "MOVL/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x6e, 0xc0}}, 990 {name: "MOVL/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x6e, 0xc0}}, 991 {name: "MOVL/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0xf, 0x7e, 0xc0}}, 992 {name: "MOVL/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x7e, 0xc0}}, 993 {name: "MOVL/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x7e, 0xc0}}, 994 {name: "MOVL/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x7e, 0xc0}}, 995 {name: "MOVQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x89, 0xc0}}, 996 {name: "MOVQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x89, 0xc0}}, 997 {name: "MOVQ/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x48, 0xf, 0x6e, 0xc0}}, 998 {name: "MOVQ/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4c, 0xf, 0x6e, 0xc0}}, 999 {name: "MOVQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x89, 0xc0}}, 1000 {name: "MOVQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x89, 0xc0}}, 1001 {name: "MOVQ/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x49, 0xf, 0x6e, 0xc0}}, 1002 {name: "MOVQ/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4d, 0xf, 0x6e, 0xc0}}, 1003 {name: "MOVQ/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x48, 0xf, 0x7e, 0xc0}}, 1004 {name: "MOVQ/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x49, 0xf, 0x7e, 0xc0}}, 1005 {name: "MOVQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x7e, 0xc0}}, 1006 {name: "MOVQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x7e, 0xc0}}, 1007 {name: "MOVQ/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x4c, 0xf, 0x7e, 0xc0}}, 1008 {name: "MOVQ/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x4d, 0xf, 0x7e, 0xc0}}, 1009 {name: "MOVQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x7e, 0xc0}}, 1010 {name: "MOVQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x7e, 0xc0}}, 1011 {name: "MOVWLSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xbf, 0xc0}}, 1012 {name: "MOVWLSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xbf, 0xc0}}, 1013 {name: "MOVWLSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xbf, 0xc0}}, 1014 {name: "MOVWLSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xbf, 0xc0}}, 1015 {name: "MOVWQSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xbf, 0xc0}}, 1016 {name: "MOVWQSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0xbf, 0xc0}}, 1017 {name: "MOVWQSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xbf, 0xc0}}, 1018 {name: "MOVWQSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xbf, 0xc0}}, 1019 {name: "MULSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x59, 0xc0}}, 1020 {name: "MULSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x59, 0xc0}}, 1021 {name: "MULSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x59, 0xc0}}, 1022 {name: "MULSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x59, 0xc0}}, 1023 {name: "MULSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x59, 0xc0}}, 1024 {name: "MULSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x59, 0xc0}}, 1025 {name: "MULSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x59, 0xc0}}, 1026 {name: "MULSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x59, 0xc0}}, 1027 {name: "IMULQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xaf, 0xc0}}, 1028 {name: "IMULQ/src=DX/dst=AX/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegDX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xaf, 0xc2}}, 1029 {name: "IMULQ/src=R10/dst=CX/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegR10, dstReg: RegCX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xaf, 0xca}}, 1030 {name: "IMULQ/src=CX/dst=DI/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegCX, dstReg: RegDI, arg: 0x0}, exp: []byte{0x48, 0xf, 0xaf, 0xf9}}, 1031 {name: "ORL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x9, 0xc0}}, 1032 {name: "ORL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x9, 0xc0}}, 1033 {name: "ORL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x9, 0xc0}}, 1034 {name: "ORL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x9, 0xc0}}, 1035 {name: "ORPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x56, 0xc0}}, 1036 {name: "ORPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x56, 0xc0}}, 1037 {name: "ORPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x56, 0xc0}}, 1038 {name: "ORPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x56, 0xc0}}, 1039 {name: "ORPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x56, 0xc0}}, 1040 {name: "ORPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x56, 0xc0}}, 1041 {name: "ORPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x56, 0xc0}}, 1042 {name: "ORPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x56, 0xc0}}, 1043 {name: "ORQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x9, 0xc0}}, 1044 {name: "ORQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x9, 0xc0}}, 1045 {name: "ORQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x9, 0xc0}}, 1046 {name: "ORQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x9, 0xc0}}, 1047 {name: "POPCNTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0xb8, 0xc0}}, 1048 {name: "POPCNTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0xb8, 0xc0}}, 1049 {name: "POPCNTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0xb8, 0xc0}}, 1050 {name: "POPCNTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0xb8, 0xc0}}, 1051 {name: "POPCNTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0xb8, 0xc0}}, 1052 {name: "POPCNTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0xb8, 0xc0}}, 1053 {name: "POPCNTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0xb8, 0xc0}}, 1054 {name: "POPCNTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0xb8, 0xc0}}, 1055 {name: "ROLL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xc0}}, 1056 {name: "ROLL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xc0}}, 1057 {name: "ROLQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xc0}}, 1058 {name: "ROLQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xc0}}, 1059 {name: "RORL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xc8}}, 1060 {name: "RORL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xc8}}, 1061 {name: "RORQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xc8}}, 1062 {name: "RORQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xc8}}, 1063 {name: "ROUNDSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x0}}, 1064 {name: "ROUNDSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x0}}, 1065 {name: "ROUNDSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x0}}, 1066 {name: "ROUNDSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x0}}, 1067 {name: "ROUNDSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x0}}, 1068 {name: "ROUNDSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x0}}, 1069 {name: "ROUNDSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x0}}, 1070 {name: "ROUNDSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x0}}, 1071 {name: "ROUNDSD/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x1}}, 1072 {name: "ROUNDSD/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x1}}, 1073 {name: "ROUNDSD/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x1}}, 1074 {name: "ROUNDSD/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x1}}, 1075 {name: "ROUNDSS/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x1}}, 1076 {name: "ROUNDSS/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x1}}, 1077 {name: "ROUNDSS/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x1}}, 1078 {name: "ROUNDSS/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x1}}, 1079 {name: "ROUNDSD/src=X0/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x2}}, 1080 {name: "ROUNDSD/src=X0/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x2}}, 1081 {name: "ROUNDSD/src=X8/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x2}}, 1082 {name: "ROUNDSD/src=X8/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x2}}, 1083 {name: "ROUNDSS/src=X0/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x2}}, 1084 {name: "ROUNDSS/src=X0/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x2}}, 1085 {name: "ROUNDSS/src=X8/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x2}}, 1086 {name: "ROUNDSS/src=X8/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x2}}, 1087 {name: "ROUNDSD/src=X0/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x3}}, 1088 {name: "ROUNDSD/src=X0/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x3}}, 1089 {name: "ROUNDSD/src=X8/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x3}}, 1090 {name: "ROUNDSD/src=X8/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x3}}, 1091 {name: "ROUNDSS/src=X0/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x3}}, 1092 {name: "ROUNDSS/src=X0/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x3}}, 1093 {name: "ROUNDSS/src=X8/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x3}}, 1094 {name: "ROUNDSS/src=X8/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x3}}, 1095 {name: "ROUNDSD/src=X0/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x4}}, 1096 {name: "ROUNDSD/src=X0/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x4}}, 1097 {name: "ROUNDSD/src=X8/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x4}}, 1098 {name: "ROUNDSD/src=X8/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x4}}, 1099 {name: "ROUNDSS/src=X0/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x4}}, 1100 {name: "ROUNDSS/src=X0/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x4}}, 1101 {name: "ROUNDSS/src=X8/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x4}}, 1102 {name: "ROUNDSS/src=X8/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x4}}, 1103 {name: "SARL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xf8}}, 1104 {name: "SARL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xf8}}, 1105 {name: "SARQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xf8}}, 1106 {name: "SARQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xf8}}, 1107 {name: "SHLL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xe0}}, 1108 {name: "SHLL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xe0}}, 1109 {name: "SHLQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xe0}}, 1110 {name: "SHLQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xe0}}, 1111 {name: "SHRL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xe8}}, 1112 {name: "SHRL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xe8}}, 1113 {name: "SHRQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xe8}}, 1114 {name: "SHRQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xe8}}, 1115 {name: "SQRTSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x51, 0xc0}}, 1116 {name: "SQRTSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x51, 0xc0}}, 1117 {name: "SQRTSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x51, 0xc0}}, 1118 {name: "SQRTSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x51, 0xc0}}, 1119 {name: "SQRTSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x51, 0xc0}}, 1120 {name: "SQRTSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x51, 0xc0}}, 1121 {name: "SQRTSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x51, 0xc0}}, 1122 {name: "SQRTSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x51, 0xc0}}, 1123 {name: "SUBL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x29, 0xc0}}, 1124 {name: "SUBL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x29, 0xc0}}, 1125 {name: "SUBL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x29, 0xc0}}, 1126 {name: "SUBL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x29, 0xc0}}, 1127 {name: "SUBQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x29, 0xc0}}, 1128 {name: "SUBQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x29, 0xc0}}, 1129 {name: "SUBQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x29, 0xc0}}, 1130 {name: "SUBQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x29, 0xc0}}, 1131 {name: "SUBSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5c, 0xc0}}, 1132 {name: "SUBSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5c, 0xc0}}, 1133 {name: "SUBSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5c, 0xc0}}, 1134 {name: "SUBSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5c, 0xc0}}, 1135 {name: "SUBSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5c, 0xc0}}, 1136 {name: "SUBSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5c, 0xc0}}, 1137 {name: "SUBSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5c, 0xc0}}, 1138 {name: "SUBSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5c, 0xc0}}, 1139 {name: "TESTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x85, 0xc0}}, 1140 {name: "TESTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x85, 0xc0}}, 1141 {name: "TESTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x85, 0xc0}}, 1142 {name: "TESTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x85, 0xc0}}, 1143 {name: "TESTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x85, 0xc0}}, 1144 {name: "TESTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x85, 0xc0}}, 1145 {name: "TESTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x85, 0xc0}}, 1146 {name: "TESTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x85, 0xc0}}, 1147 {name: "TZCNTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0xbc, 0xc0}}, 1148 {name: "TZCNTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0xbc, 0xc0}}, 1149 {name: "TZCNTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0xbc, 0xc0}}, 1150 {name: "TZCNTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0xbc, 0xc0}}, 1151 {name: "TZCNTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0xbc, 0xc0}}, 1152 {name: "TZCNTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0xbc, 0xc0}}, 1153 {name: "TZCNTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0xbc, 0xc0}}, 1154 {name: "TZCNTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0xbc, 0xc0}}, 1155 {name: "UCOMISD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x2e, 0xc0}}, 1156 {name: "UCOMISD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x2e, 0xc0}}, 1157 {name: "UCOMISD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x2e, 0xc0}}, 1158 {name: "UCOMISD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x2e, 0xc0}}, 1159 {name: "UCOMISS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x2e, 0xc0}}, 1160 {name: "UCOMISS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x2e, 0xc0}}, 1161 {name: "UCOMISS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x2e, 0xc0}}, 1162 {name: "UCOMISS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x2e, 0xc0}}, 1163 {name: "XORL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x31, 0xc0}}, 1164 {name: "XORL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x31, 0xc0}}, 1165 {name: "XORL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x31, 0xc0}}, 1166 {name: "XORL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x31, 0xc0}}, 1167 {name: "XORPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x57, 0xc0}}, 1168 {name: "XORPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x57, 0xc0}}, 1169 {name: "XORPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x57, 0xc0}}, 1170 {name: "XORPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x57, 0xc0}}, 1171 {name: "XORPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x57, 0xc0}}, 1172 {name: "XORPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x57, 0xc0}}, 1173 {name: "XORPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x57, 0xc0}}, 1174 {name: "XORPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x57, 0xc0}}, 1175 {name: "XORQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x31, 0xc0}}, 1176 {name: "XORQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x31, 0xc0}}, 1177 {name: "XORQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x31, 0xc0}}, 1178 {name: "XORQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x31, 0xc0}}, 1179 {name: "XCHGQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x87, 0xc0}}, 1180 {name: "XCHGQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: XCHGQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x87, 0xc0}}, 1181 {name: "XCHGQ/src=R8/dst=R9/arg=0", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR9, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x87, 0xc8}}, 1182 {name: "PXOR/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PXOR, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xef, 0xc0}}, 1183 {name: "PXOR/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PXOR, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xef, 0xc0}}, 1184 {name: "PXOR/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PXOR, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xef, 0xc0}}, 1185 {name: "PSHUFB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x38, 0x0, 0xc0}}, 1186 {name: "PSHUFB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x0, 0xc0}}, 1187 {name: "PSHUFB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x0, 0xc0}}, 1188 {name: "PSHUFB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x38, 0x0, 0xc0}}, 1189 {name: "PSHUFD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x70, 0xc0, 0x0}}, 1190 {name: "PSHUFD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x70, 0xc0, 0x0}}, 1191 {name: "PSHUFD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x70, 0xc0, 0x0}}, 1192 {name: "PSHUFD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x70, 0xc0, 0x0}}, 1193 {name: "PSHUFD/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x70, 0xc0, 0x1}}, 1194 {name: "PSHUFD/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x70, 0xc0, 0x1}}, 1195 {name: "PSHUFD/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x70, 0xc0, 0x1}}, 1196 {name: "PSHUFD/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x70, 0xc0, 0x1}}, 1197 {name: "PEXTRB/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0xc0, 0x0}}, 1198 {name: "PEXTRB/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x14, 0xc0, 0x0}}, 1199 {name: "PEXTRB/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xc0, 0x0}}, 1200 {name: "PEXTRB/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x14, 0xc0, 0x0}}, 1201 {name: "PEXTRW/src=X0/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0xf, 0xc5, 0xc0, 0x1}}, 1202 {name: "PEXTRW/src=X0/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0xc5, 0xc0, 0x1}}, 1203 {name: "PEXTRW/src=X8/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX8, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0xc5, 0xc0, 0x1}}, 1204 {name: "PEXTRW/src=X8/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX8, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0xc5, 0xc0, 0x1}}, 1205 {name: "PEXTRD/src=X0/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, 1206 {name: "PEXTRD/src=X0/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, 1207 {name: "PEXTRD/src=X8/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX8, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, 1208 {name: "PEXTRD/src=X8/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX8, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, 1209 {name: "PEXTRQ/src=X0/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, 1210 {name: "PEXTRQ/src=X0/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x49, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, 1211 {name: "PEXTRQ/src=X8/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX8, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, 1212 {name: "PEXTRQ/src=X8/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX8, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x4d, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, 1213 {name: "MOVLHPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x16, 0xc0}}, 1214 {name: "MOVLHPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x16, 0xc0}}, 1215 {name: "MOVLHPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x16, 0xc0}}, 1216 {name: "MOVLHPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x16, 0xc0}}, 1217 {name: "INSERTPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x21, 0xc0, 0x0}}, 1218 {name: "INSERTPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x21, 0xc0, 0x0}}, 1219 {name: "INSERTPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x21, 0xc0, 0x0}}, 1220 {name: "INSERTPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x21, 0xc0, 0x0}}, 1221 {name: "INSERTPS/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x21, 0xc0, 0x1}}, 1222 {name: "INSERTPS/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x21, 0xc0, 0x1}}, 1223 {name: "INSERTPS/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x21, 0xc0, 0x1}}, 1224 {name: "INSERTPS/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x21, 0xc0, 0x1}}, 1225 {name: "PTEST/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x38, 0x17, 0xc0}}, 1226 {name: "PTEST/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x17, 0xc0}}, 1227 {name: "PTEST/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x17, 0xc0}}, 1228 {name: "PTEST/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x38, 0x17, 0xc0}}, 1229 {name: "PCMPEQB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x74, 0xc0}}, 1230 {name: "PCMPEQB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x74, 0xc0}}, 1231 {name: "PCMPEQB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x74, 0xc0}}, 1232 {name: "PCMPEQB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x74, 0xc0}}, 1233 {name: "PCMPEQW/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x75, 0xc0}}, 1234 {name: "PCMPEQW/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x75, 0xc0}}, 1235 {name: "PCMPEQW/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x75, 0xc0}}, 1236 {name: "PCMPEQW/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x75, 0xc0}}, 1237 {name: "PCMPEQD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x76, 0xc0}}, 1238 {name: "PCMPEQD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x76, 0xc0}}, 1239 {name: "PCMPEQD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x76, 0xc0}}, 1240 {name: "PCMPEQD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x76, 0xc0}}, 1241 {name: "PCMPEQQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x38, 0x29, 0xc0}}, 1242 {name: "PCMPEQQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x29, 0xc0}}, 1243 {name: "PCMPEQQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x29, 0xc0}}, 1244 {name: "PCMPEQQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x38, 0x29, 0xc0}}, 1245 {name: "PADDUSB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xdc, 0xc0}}, 1246 {name: "PADDUSB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xdc, 0xc0}}, 1247 {name: "PADDUSB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xdc, 0xc0}}, 1248 {name: "PADDUSB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xdc, 0xc0}}, 1249 {name: "MOVSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x10, 0xc0}}, 1250 {name: "MOVSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x10, 0xc0}}, 1251 {name: "MOVSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x10, 0xc0}}, 1252 {name: "MOVSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x10, 0xc0}}, 1253 } 1254 1255 for _, tt := range tests { 1256 tc := tt 1257 a := NewAssembler() 1258 err := a.encodeRegisterToRegister(tc.n) 1259 require.NoError(t, err, tc.name) 1260 1261 actual, err := a.Assemble() 1262 require.NoError(t, err, tc.name) 1263 require.Equal(t, tc.exp, actual, tc.name) 1264 } 1265 }