wa-lang.org/wazero@v1.0.2/internal/asm/arm64/consts.go (about) 1 package arm64 2 3 import ( 4 "fmt" 5 6 "wa-lang.org/wazero/internal/asm" 7 ) 8 9 // Arm64-specific register states. 10 // 11 // Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm 12 // See https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/condition-codes-1-condition-flags-and-codes 13 const ( 14 // CondEQ is the eq (equal) condition code 15 CondEQ = asm.ConditionalRegisterStateUnset + 1 + iota 16 // CondNE is the ne (not equal) condition code 17 CondNE 18 // CondHS is the hs (unsigned higher or same) condition code 19 CondHS 20 // CondLO is the lo (unsigned lower) condition code 21 CondLO 22 // CondMI is the mi (negative) condition code 23 CondMI 24 // CondPL is the pl (positive or zero) condition code 25 CondPL 26 // CondVS is the vs (signed overflow) condition code 27 CondVS 28 // CondVC is the vc (no signed overflow) condition code 29 CondVC 30 // CondHI is the hi (unsigned higher) condition code 31 CondHI 32 // CondLS is the ls (unsigned lower or same) condition code 33 CondLS 34 // CondGE is the ge (signed greater than or equal) condition code 35 CondGE 36 // CondLT is the lt (signed less than) condition code 37 CondLT 38 // CondGT is the gt (signed greater than) condition code 39 CondGT 40 // CondLE is the le (signed less than or equal) condition code 41 CondLE 42 // CondAL is the al (always executed) condition code 43 CondAL 44 // CondNV has the same meaning as CondAL 45 CondNV 46 ) 47 48 // Arm64-specific registers. 49 // 50 // Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm 51 // See https://developer.arm.com/documentation/dui0801/a/Overview-of-AArch64-state/Predeclared-core-register-names-in-AArch64-state 52 const ( 53 // Integer registers. 54 55 // RegR0 is the R0 register 56 RegR0 asm.Register = asm.NilRegister + 1 + iota 57 // RegR1 is the R1 register 58 RegR1 59 // RegR2 is the R2 register 60 RegR2 61 // RegR3 is the R3 register 62 RegR3 63 // RegR4 is the R4 register 64 RegR4 65 // RegR5 is the R5 register 66 RegR5 67 // RegR6 is the R6 register 68 RegR6 69 // RegR7 is the R7 register 70 RegR7 71 // RegR8 is the R8 register 72 RegR8 73 // RegR9 is the R9 register 74 RegR9 75 // RegR10 is the R10 register 76 RegR10 77 // RegR11 is the R11 register 78 RegR11 79 // RegR12 is the R12 register 80 RegR12 81 // RegR13 is the R13 register 82 RegR13 83 // RegR14 is the R14 register 84 RegR14 85 // RegR15 is the R15 register 86 RegR15 87 // RegR16 is the R16 register 88 RegR16 89 // RegR17 is the R17 register 90 RegR17 91 // RegR18 is the R18 register 92 RegR18 93 // RegR19 is the R19 register 94 RegR19 95 // RegR20 is the R20 register 96 RegR20 97 // RegR21 is the R21 register 98 RegR21 99 // RegR22 is the R22 register 100 RegR22 101 // RegR23 is the R23 register 102 RegR23 103 // RegR24 is the R24 register 104 RegR24 105 // RegR25 is the R25 register 106 RegR25 107 // RegR26 is the R26 register 108 RegR26 109 // RegR27 is the R27 register 110 RegR27 111 // RegR28 is the R28 register 112 RegR28 113 // RegR29 is the R29 register 114 RegR29 115 // RegR30 is the R30 register 116 RegR30 117 // RegRZR is the RZR register (read-only, always returning zero) 118 RegRZR 119 120 // Scalar floating point registers. 121 122 // RegV0 is the V0 register 123 RegV0 124 // RegV1 is the V1 register 125 RegV1 126 // RegV2 is the V2 register 127 RegV2 128 // RegV3 is the V3 register 129 RegV3 130 // RegV4 is the V4 register 131 RegV4 132 // RegV5 is the V5 register 133 RegV5 134 // RegV6 is the V6 register 135 RegV6 136 // RegV7 is the V7 register 137 RegV7 138 // RegV8 is the V8 register 139 RegV8 140 // RegV9 is the V9 register 141 RegV9 142 // RegV10 is the V10 register 143 RegV10 144 // RegV11 is the V11 register 145 RegV11 146 // RegV12 is the V12 register 147 RegV12 148 // RegV13 is the V13 register 149 RegV13 150 // RegV14 is the V14 register 151 RegV14 152 // RegV15 is the V15 register 153 RegV15 154 // RegV16 is the V16 register 155 RegV16 156 // RegV17 is the V17 register 157 RegV17 158 // RegV18 is the V18 register 159 RegV18 160 // RegV19 is the V19 register 161 RegV19 162 // RegV20 is the V20 register 163 RegV20 164 // RegV21 is the V21 register 165 RegV21 166 // RegV22 is the V22 register 167 RegV22 168 // RegV23 is the V23 register 169 RegV23 170 // RegV24 is the V24 register 171 RegV24 172 // RegV25 is the V25 register 173 RegV25 174 // RegV26 is the V26 register 175 RegV26 176 // RegV27 is the V27 register 177 RegV27 178 // RegV28 is the V28 register 179 RegV28 180 // RegV29 is the V29 register 181 RegV29 182 // RegV30 is the V30 register 183 RegV30 184 // RegV31 is the V31 register 185 RegV31 186 187 // Floating point status register. 188 189 // RegFPSR is the FPSR register 190 RegFPSR 191 192 // Assign each conditional register state to the unique register ID. 193 // This is to reduce the size of nodeImpl struct without having dedicated field 194 // for conditional register state which would not be used by most nodes. 195 // This is taking advantage of the fact that conditional operations are always 196 // on a single register and condition code, and never two registers. 197 198 // RegCondEQ encodes CondEQ into a field that would otherwise store a register 199 RegCondEQ 200 // RegCondNE encodes CondNE into a field that would otherwise store a register 201 RegCondNE 202 // RegCondHS encodes CondHS into a field that would otherwise store a register 203 RegCondHS 204 // RegCondLO encodes CondLO into a field that would otherwise store a register 205 RegCondLO 206 // RegCondMI encodes CondMI into a field that would otherwise store a register 207 RegCondMI 208 // RegCondPL encodes CondPL into a field that would otherwise store a register 209 RegCondPL 210 // RegCondVS encodes CondVS into a field that would otherwise store a register 211 RegCondVS 212 // RegCondVC encodes CondVC into a field that would otherwise store a register 213 RegCondVC 214 // RegCondHI encodes CondHI into a field that would otherwise store a register 215 RegCondHI 216 // RegCondLS encodes CondLS into a field that would otherwise store a register 217 RegCondLS 218 // RegCondGE encodes CondGE into a field that would otherwise store a register 219 RegCondGE 220 // RegCondLT encodes CondLT into a field that would otherwise store a register 221 RegCondLT 222 // RegCondGT encodes CondGT into a field that would otherwise store a register 223 RegCondGT 224 // RegCondLE encodes CondLE into a field that would otherwise store a register 225 RegCondLE 226 // RegCondAL encodes CondAL into a field that would otherwise store a register 227 RegCondAL 228 // RegCondNV encodes CondNV into a field that would otherwise store a register 229 RegCondNV 230 ) 231 232 // conditionalRegisterStateToRegister cast a conditional register to its unique register ID. 233 // See the comment on RegCondEQ above. 234 func conditionalRegisterStateToRegister(c asm.ConditionalRegisterState) asm.Register { 235 switch c { 236 case CondEQ: 237 return RegCondEQ 238 case CondNE: 239 return RegCondNE 240 case CondHS: 241 return RegCondHS 242 case CondLO: 243 return RegCondLO 244 case CondMI: 245 return RegCondMI 246 case CondPL: 247 return RegCondPL 248 case CondVS: 249 return RegCondVS 250 case CondVC: 251 return RegCondVC 252 case CondHI: 253 return RegCondHI 254 case CondLS: 255 return RegCondLS 256 case CondGE: 257 return RegCondGE 258 case CondLT: 259 return RegCondLT 260 case CondGT: 261 return RegCondGT 262 case CondLE: 263 return RegCondLE 264 case CondAL: 265 return RegCondAL 266 case CondNV: 267 return RegCondNV 268 } 269 return asm.NilRegister 270 } 271 272 // RegisterName returns the name of a given register 273 func RegisterName(r asm.Register) string { 274 switch r { 275 case asm.NilRegister: 276 return "nil" 277 case RegR0: 278 return "R0" 279 case RegR1: 280 return "R1" 281 case RegR2: 282 return "R2" 283 case RegR3: 284 return "R3" 285 case RegR4: 286 return "R4" 287 case RegR5: 288 return "R5" 289 case RegR6: 290 return "R6" 291 case RegR7: 292 return "R7" 293 case RegR8: 294 return "R8" 295 case RegR9: 296 return "R9" 297 case RegR10: 298 return "R10" 299 case RegR11: 300 return "R11" 301 case RegR12: 302 return "R12" 303 case RegR13: 304 return "R13" 305 case RegR14: 306 return "R14" 307 case RegR15: 308 return "R15" 309 case RegR16: 310 return "R16" 311 case RegR17: 312 return "R17" 313 case RegR18: 314 return "R18" 315 case RegR19: 316 return "R19" 317 case RegR20: 318 return "R20" 319 case RegR21: 320 return "R21" 321 case RegR22: 322 return "R22" 323 case RegR23: 324 return "R23" 325 case RegR24: 326 return "R24" 327 case RegR25: 328 return "R25" 329 case RegR26: 330 return "R26" 331 case RegR27: 332 return "R27" 333 case RegR28: 334 return "R28" 335 case RegR29: 336 return "R29" 337 case RegR30: 338 return "R30" 339 case RegRZR: 340 return "RZR" 341 case RegV0: 342 return "V0" 343 case RegV1: 344 return "V1" 345 case RegV2: 346 return "V2" 347 case RegV3: 348 return "V3" 349 case RegV4: 350 return "V4" 351 case RegV5: 352 return "V5" 353 case RegV6: 354 return "V6" 355 case RegV7: 356 return "V7" 357 case RegV8: 358 return "V8" 359 case RegV9: 360 return "V9" 361 case RegV10: 362 return "V10" 363 case RegV11: 364 return "V11" 365 case RegV12: 366 return "V12" 367 case RegV13: 368 return "V13" 369 case RegV14: 370 return "V14" 371 case RegV15: 372 return "V15" 373 case RegV16: 374 return "V16" 375 case RegV17: 376 return "V17" 377 case RegV18: 378 return "V18" 379 case RegV19: 380 return "V19" 381 case RegV20: 382 return "V20" 383 case RegV21: 384 return "V21" 385 case RegV22: 386 return "V22" 387 case RegV23: 388 return "V23" 389 case RegV24: 390 return "V24" 391 case RegV25: 392 return "V25" 393 case RegV26: 394 return "V26" 395 case RegV27: 396 return "V27" 397 case RegV28: 398 return "V28" 399 case RegV29: 400 return "V29" 401 case RegV30: 402 return "V30" 403 case RegV31: 404 return "V31" 405 case RegFPSR: 406 return "FPSR" 407 case RegCondEQ: 408 return "COND_EQ" 409 case RegCondNE: 410 return "COND_NE" 411 case RegCondHS: 412 return "COND_HS" 413 case RegCondLO: 414 return "COND_LO" 415 case RegCondMI: 416 return "COND_MI" 417 case RegCondPL: 418 return "COND_PL" 419 case RegCondVS: 420 return "COND_VS" 421 case RegCondVC: 422 return "COND_VC" 423 case RegCondHI: 424 return "COND_HI" 425 case RegCondLS: 426 return "COND_LS" 427 case RegCondGE: 428 return "COND_GE" 429 case RegCondLT: 430 return "COND_LT" 431 case RegCondGT: 432 return "COND_GT" 433 case RegCondLE: 434 return "COND_LE" 435 case RegCondAL: 436 return "COND_AL" 437 case RegCondNV: 438 return "COND_NV" 439 } 440 return "UNKNOWN" 441 } 442 443 // Arm64-specific instructions. 444 // 445 // Note: This only defines arm64 instructions used by wazero's compiler. 446 // Note: Naming conventions partially match the Go assembler: https://go.dev/doc/asm 447 const ( 448 // NOP is the NOP instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NOP 449 NOP asm.Instruction = iota 450 // RET is the RET instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RET 451 RET 452 // ADD is the ADD instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADD--shifted-register- 453 ADD 454 // ADDS is the ADDS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADDS--shifted-register- 455 ADDS 456 // ADDW is the ADD instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADD--shifted-register- 457 ADDW 458 // ADR is the ADR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADR 459 ADR 460 // AND is the AND instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/AND--shifted-register- 461 AND 462 // ANDIMM32 is the AND(immediate) instruction in 32-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/AND--immediate---Bitwise-AND--immediate--?lang=en 463 ANDIMM32 464 // ANDIMM64 is the AND(immediate) instruction in 64-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/AND--immediate---Bitwise-AND--immediate--?lang=en 465 ANDIMM64 466 // ANDW is the AND instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/AND--register- 467 ANDW 468 // ASR is the ASR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ASR--register- 469 ASR 470 // ASRW is the ASR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ASR--register- 471 ASRW 472 // B is the B instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B 473 B 474 475 // Below are B.cond instructions. 476 // * https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond 477 // * https://developer.arm.com/documentation/dui0802/a/A32-and-T32-Instructions/Condition-codes 478 479 // BCONDEQ is the B.cond instruction with CondEQ. 480 BCONDEQ 481 // BCONDGE is the B.cond instruction with CondGE. 482 BCONDGE 483 // BCONDGT is the B.cond instruction with CondGT. 484 BCONDGT 485 // BCONDHI is the B.cond instruction with CondHI. 486 BCONDHI 487 // BCONDHS is the B.cond instruction with CondHS. 488 BCONDHS 489 // BCONDLE is the B.cond instruction with CondLE. 490 BCONDLE 491 // BCONDLO is the B.cond instruction with CondLO. 492 BCONDLO 493 // BCONDLS is the B.cond instruction with CondLS. 494 BCONDLS 495 // BCONDLT is the B.cond instruction with CondLT. 496 BCONDLT 497 // BCONDMI is the B.cond instruction with CondMI. 498 BCONDMI 499 // BCONDPL is the B.cond instruction with CondPL. 500 BCONDPL 501 // BCONDNE is the B.cond instruction with CondNE. 502 BCONDNE 503 // BCONDVS is the B.cond instruction with CondVS. 504 BCONDVS 505 506 // CLZ is the CLZ instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CLZ 507 CLZ 508 // CLZW is the CLZ instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CLZ 509 CLZW 510 // CMP is the CMP instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CMP--shifted-register- 511 CMP 512 // CMPW is the CMP instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CMP--shifted-register- 513 CMPW 514 // CSET is the CSET instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CSET 515 CSET 516 // EOR is the EOR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/EOR--shifted-register- 517 EOR 518 // EORW is the EOR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/EOR--shifted-register- 519 EORW 520 // FABSD is the FABS instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FABS--scalar- 521 FABSD 522 // FABSS is the FABS instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FABS--scalar- 523 FABSS 524 // FADDD is the FADD instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FADD--scalar- 525 FADDD 526 // FADDS is the FADD instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FADD--scalar- 527 FADDS 528 // FCMPD is the FCMP instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCMP 529 FCMPD 530 // FCMPS is the FCMP instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCMP 531 FCMPS 532 // FCVTDS is the FCVT instruction, for single to double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVT 533 FCVTDS 534 // FCVTSD is the FCVT instruction, for double to single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVT 535 FCVTSD 536 // FCVTZSD is the FCVTZS instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- 537 FCVTZSD 538 // FCVTZSDW is the FCVTZS instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- 539 FCVTZSDW 540 // FCVTZSS is the FCVTZS instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- 541 FCVTZSS 542 // FCVTZSSW is the FCVTZS instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- 543 FCVTZSSW 544 // FCVTZUD is the FCVTZU instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- 545 FCVTZUD 546 // FCVTZUDW is the FCVTZU instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- 547 FCVTZUDW 548 // FCVTZUS is the FCVTZU instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- 549 FCVTZUS 550 // FCVTZUSW is the FCVTZU instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- 551 FCVTZUSW 552 // FDIVD is the FDIV instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FDIV--scalar- 553 FDIVD 554 // FDIVS is the FDIV instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FDIV--scalar- 555 FDIVS 556 // FMAXD is the FMAX instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMAX--scalar- 557 FMAXD 558 // FMAXS is the FMAX instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMAX--scalar- 559 FMAXS 560 // FMIND is the FMIN instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMIN--scalar- 561 FMIND 562 // FMINS is the FMIN instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMIN--scalar- 563 FMINS 564 // FMOVD is the FMOV instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMOV--register- 565 FMOVD 566 // FMOVS is the FMOV instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMOV--register- 567 FMOVS 568 // FMULD is the FMUL instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMUL--scalar- 569 FMULD 570 // FMULS is the FMUL instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMUL--scalar- 571 FMULS 572 // FNEGD is the FNEG instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FNEG--scalar- 573 FNEGD 574 // FNEGS is the FNEG instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FNEG--scalar- 575 FNEGS 576 // FRINTMD is the FRINTM instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTM--scalar- 577 FRINTMD 578 // FRINTMS is the FRINTM instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTM--scalar- 579 FRINTMS 580 // FRINTND is the FRINTN instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTN--scalar- 581 FRINTND 582 // FRINTNS is the FRINTN instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTN--scalar- 583 FRINTNS 584 // FRINTPD is the FRINTP instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTP--scalar- 585 FRINTPD 586 // FRINTPS is the FRINTP instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTP--scalar- 587 FRINTPS 588 // FRINTZD is the FRINTZ instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTZ--scalar- 589 FRINTZD 590 // FRINTZS is the FRINTZ instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTZ--scalar- 591 FRINTZS 592 // FSQRTD is the FSQRT instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSQRT--scalar- 593 FSQRTD 594 // FSQRTS is the FSQRT instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSQRT--scalar- 595 FSQRTS 596 // FSUBD is the FSUB instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSUB--scalar- 597 FSUBD 598 // FSUBS is the FSUB instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSUB--scalar- 599 FSUBS 600 // LSL is the LSL instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSL--register- 601 LSL 602 // LSLW is the LSL instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSL--register- 603 LSLW 604 // LSR is the LSR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSR--register- 605 LSR 606 // LSRW is the LSR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSR--register- 607 LSRW 608 // FLDRD is the LDR (SIMD&FP) instruction for double precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LDR--register--SIMD-FP---Load-SIMD-FP-Register--register-offset--?lang=en 609 FLDRD 610 // FLDRS is the LDR (SIMD&FP) instruction for single precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LDR--register--SIMD-FP---Load-SIMD-FP-Register--register-offset--?lang=en 611 FLDRS 612 // LDRD is the LDR instruction in 64-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en 613 LDRD 614 // LDRW is the LDR instruction in 32-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en 615 LDRW 616 // LDRSBD is the LDRSB instruction in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSB--register- 617 LDRSBD 618 // LDRSBW is the LDRSB instruction in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSB--register- 619 LDRSBW 620 // LDRB is the LDRB instruction. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRB--register- 621 LDRB 622 // LDRSHD is the LDRSHW instruction in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSH--register- 623 LDRSHD 624 // LDRSHW is the LDRSHW instruction in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSH--register- 625 LDRSHW 626 // LDRH is the LDRH instruction. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRH--register- 627 LDRH 628 // LDRSW is the LDRSW instruction https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSW--register- 629 LDRSW 630 // FSTRD is the STR (SIMD&FP) instruction for double precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset--?lang=en 631 FSTRD 632 // FSTRS is the STR (SIMD&FP) instruction for single precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset--?lang=en 633 FSTRS 634 // STRD is the STR instruction in 64-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STR--register---Store-Register--register--?lang=en 635 STRD 636 // STRW is the STR instruction in 32-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STR--register---Store-Register--register--?lang=en 637 STRW 638 // STRH is the STRH instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STRH--register---Store-Register-Halfword--register--?lang=en 639 STRH 640 // STRB is the STRB instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STRB--register---Store-Register-Byte--register--?lang=en 641 STRB 642 // MOVD moves a double word from register to register, or const to register. 643 MOVD 644 // MOVW moves a word from register to register, or const to register. 645 MOVW 646 // MRS is the MRS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MRS 647 MRS 648 // MSR is the MSR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSR--register- 649 MSR 650 // MSUB is the MSUB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSUB 651 MSUB 652 // MSUBW is the MSUB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSUB 653 MSUBW 654 // MUL is the MUL instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MUL 655 MUL 656 // MULW is the MUL instruction, in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MUL 657 MULW 658 // NEG is the NEG instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NEG 659 NEG 660 // NEGW is the NEG instruction, in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NEG 661 NEGW 662 // ORR is the ORR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ORR--shifted-register- 663 ORR 664 // ORRW is the ORR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ORR--shifted-register- 665 ORRW 666 // RBIT is the RBIT instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RBIT 667 RBIT 668 // RBITW is the RBIT instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RBIT 669 RBITW 670 // ROR is the ROR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ROR--register- 671 ROR 672 // RORW is the RORW instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ROR--register- 673 RORW 674 // SCVTFD is the SCVTF instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- 675 SCVTFD 676 // SCVTFS is the SCVTF instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- 677 SCVTFS 678 // SCVTFWD is the SCVTF instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- 679 SCVTFWD 680 // SCVTFWS is the SCVTF instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- 681 SCVTFWS 682 // SDIV is the SDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SDIV 683 SDIV 684 // SDIVW is the SDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SDIV 685 SDIVW 686 // SUB is the SUB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUB--shifted-register- 687 SUB 688 // SUBS is the SUBS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUBS--shifted-register- 689 SUBS 690 // SUBW is the SUB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUB--shifted-register- 691 SUBW 692 // SXTB is the SXTB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTB 693 SXTB 694 // SXTBW is the SXTB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTB 695 SXTBW 696 // SXTH is the SXTH instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTH 697 SXTH 698 // SXTHW is the SXTH instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTH 699 SXTHW 700 // SXTW is the SXTW instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTW 701 SXTW 702 // UCVTFD is the UCVTF instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- 703 UCVTFD 704 // UCVTFS is the UCVTF instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- 705 UCVTFS 706 // UCVTFWD is the UCVTF instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- 707 UCVTFWD 708 // UCVTFWS is the UCVTF instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- 709 UCVTFWS 710 // UDIV is the UDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV 711 UDIV 712 // UDIVW is the UDIV instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV 713 UDIVW 714 // VBIT is the BIT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/BIT--vector- 715 VBIT 716 // VCNT is the CNT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/CNT--vector- 717 VCNT 718 // VMOV has different semantics depending on the types of operands: 719 // - LDR(SIMD&FP) if the src is memory and dst is a vector: https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/LDR--immediate--SIMD-FP---Load-SIMD-FP-Register--immediate-offset-- 720 // - LDR(literal, SIMD&FP) if the src is static const and dst is a vector: https://developer.arm.com/documentation/dui0801/h/A64-Floating-point-Instructions/LDR--literal--SIMD-and-FP- 721 // - STR(SIMD&FP) if the dst is memory and src is a vector: https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset-- 722 VMOV 723 // UMOV is the UMOV instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMOV--Unsigned-Move-vector-element-to-general-purpose-register-?lang=en 724 UMOV 725 // INSGEN is the INS(general) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/INS--general---Insert-vector-element-from-general-purpose-register-?lang=en 726 INSGEN 727 // INSELEM is the INS(element) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/INS--element---Insert-vector-element-from-another-vector-element-?lang=en 728 INSELEM 729 // UADDLV is the UADDLV(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/UADDLV--vector- 730 UADDLV 731 // VADD is the ADD(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/ADD--vector- 732 VADD 733 // VFADDS is the FADD(vector) instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FADD--vector- 734 VFADDS 735 // VFADDD is the FADD(vector) instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FADD--vector- 736 VFADDD 737 // VSUB is the SUB(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/SUB--vector- 738 VSUB 739 // VFSUBS is the FSUB(vector) instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FSUB--vector- 740 VFSUBS 741 // VFSUBD is the FSUB(vector) instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FSUB--vector- 742 VFSUBD 743 // SSHL is the SSHL(vector,register) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHL--Signed-Shift-Left--register--?lang=en 744 SSHL 745 // SSHLL is the SSHLL(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- 746 SSHLL 747 // USHL is the USHL(vector,register) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHL--Signed-Shift-Left--register--?lang=en 748 USHL 749 // USHLL is the USHLL(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- 750 USHLL 751 // LD1R is the LD1R instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LD1R--Load-one-single-element-structure-and-Replicate-to-all-lanes--of-one-register-- 752 LD1R 753 // SMOV32 is the 32-bit variant of SMOV(vector) instruction. https://developer.arm.com/documentation/100069/0610/A64-SIMD-Vector-Instructions/SMOV--vector- 754 SMOV32 755 // DUPGEN is the DUP(general) instruction. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/DUP--general---Duplicate-general-purpose-register-to-vector- 756 DUPGEN 757 // DUPELEM is the DUP(element) instruction. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/DUP--element---Duplicate-vector-element-to-vector-or-scalar- 758 DUPELEM 759 // UMAXP is the UMAXP(vector) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/UMAXP--vector- 760 UMAXP 761 // UMINV is the UMINV(vector) instruction. https://developer.arm.com/documentation/100069/0610/A64-SIMD-Vector-Instructions/UMINV--vector- 762 UMINV 763 // CMEQ is the CMEQ(vector, register) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/CMEQ--vector--register- 764 CMEQ 765 // CMEQZERO is the CMEP(zero) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMEQ--zero---Compare-bitwise-Equal-to-zero--vector--?lang=en 766 CMEQZERO 767 // ADDP is the ADDP(scalar) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ADDP--scalar---Add-Pair-of-elements--scalar--?lang=en 768 ADDP 769 // VADDP is the ADDP(vector) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/ADDP--vector- 770 // Note: prefixed by V to distinguish from the non-vector variant of ADDP(scalar). 771 VADDP 772 // TBL1 is the TBL instruction whose source is one vector. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup- 773 TBL1 774 // TBL2 is the TBL instruction whose source is two vectors. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup- 775 TBL2 776 // NOT is the NOT(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/NOT--Bitwise-NOT--vector--?lang=en 777 NOT 778 // VAND is the AND(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/AND--vector---Bitwise-AND--vector-- 779 // Note: prefixed by V to distinguish from the non-vector variant of AND. 780 VAND 781 // VORR is the ORR(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/ORR--vector--register---Bitwise-inclusive-OR--vector--register-- 782 // Note: prefixed by V to distinguish from the non-vector variant of ORR. 783 VORR 784 // BSL https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/BSL--Bitwise-Select- 785 BSL 786 // BIC is the BIC(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/BIC--vector--register---Bitwise-bit-Clear--vector--register-- 787 BIC 788 // VFNEG is the FNEG(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/FNEG--vector---Floating-point-Negate--vector-- 789 // Note: prefixed by V to distinguish from the non-vector variant of FNEG. 790 VFNEG 791 // ADDV is the ADDV instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/ADDV--Add-across-Vector- 792 ADDV 793 // ZIP1 is the ZIP1 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ZIP1--Zip-vectors--primary--?lang=en 794 ZIP1 795 // SSHR is the SSHR(immediate,vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHR--Signed-Shift-Right--immediate--?lang=en 796 SSHR 797 // EXT is the EXT instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/EXT--Extract-vector-from-pair-of-vectors-?lang=en 798 EXT 799 // CMGT is the CMGT(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMGT--register---Compare-signed-Greater-than--vector--?lang=en 800 CMGT 801 // CMHI is the CMHI(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMHI--register---Compare-unsigned-Higher--vector--?lang=en 802 CMHI 803 // CMGE is the CMGE(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMGE--register---Compare-signed-Greater-than-or-Equal--vector--?lang=en 804 CMGE 805 // CMHS is the CMHS(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMHS--register---Compare-unsigned-Higher-or-Same--vector--?lang=en 806 CMHS 807 // FCMEQ is the FCMEQ(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMEQ--register---Floating-point-Compare-Equal--vector--?lang=en 808 FCMEQ 809 // FCMGT is the FCMGT(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMGT--register---Floating-point-Compare-Greater-than--vector--?lang=en 810 FCMGT 811 // FCMGE is the FCMGE(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMGE--register---Floating-point-Compare-Greater-than-or-Equal--vector--?lang=en 812 FCMGE 813 // VFMUL is the FMUL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMUL--vector---Floating-point-Multiply--vector--?lang=en 814 // Note: prefixed by V to distinguish from the non-vector variant. 815 VFMUL 816 // VFDIV is the FDIV(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FDIV--vector---Floating-point-Divide--vector--?lang=en 817 // Note: prefixed by V to distinguish from the non-vector variant. 818 VFDIV 819 // VFSQRT is the FSQRT(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FSQRT--vector---Floating-point-Square-Root--vector--?lang=en 820 // Note: prefixed by V to distinguish from the non-vector variant. 821 VFSQRT 822 // VFMIN is the FMIN(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMIN--vector---Floating-point-minimum--vector--?lang=en 823 // Note: prefixed by V to distinguish from the non-vector variant. 824 VFMIN 825 // VFMAX is the FMAX(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMAX--vector---Floating-point-Maximum--vector--?lang=en 826 // Note: prefixed by V to distinguish from the non-vector variant. 827 VFMAX 828 // VFABS is the FABS(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FABS--vector---Floating-point-Absolute-value--vector--?lang=en 829 // Note: prefixed by V to distinguish from the non-vector variant. 830 VFABS 831 // VFRINTP is the FRINTP(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTP--vector---Floating-point-Round-to-Integral--toward-Plus-infinity--vector--?lang=en 832 // Note: prefixed by V to distinguish from the non-vector variant. 833 VFRINTP 834 // VFRINTM is the FRINTM(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTM--vector---Floating-point-Round-to-Integral--toward-Minus-infinity--vector--?lang=en 835 // Note: prefixed by V to distinguish from the non-vector variant. 836 VFRINTM 837 // VFRINTZ is the FRINTZ(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTZ--vector---Floating-point-Round-to-Integral--toward-Zero--vector--?lang=en 838 // Note: prefixed by V to distinguish from the non-vector variant. 839 VFRINTZ 840 // VFRINTN is the FRINTN(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTN--vector---Floating-point-Round-to-Integral--to-nearest-with-ties-to-even--vector--?lang=en 841 // Note: prefixed by V to distinguish from the non-vector variant. 842 VFRINTN 843 // VMUL is the MUL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/MUL--vector---Multiply--vector--?lang=en 844 // Note: prefixed by V to distinguish from the non-vector variant. 845 VMUL 846 // VNEG is the NEG(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/NEG--vector---Negate--vector--?lang=en 847 // Note: prefixed by V to distinguish from the non-vector variant. 848 VNEG 849 // VABS is the ABS(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ABS--Absolute-value--vector--?lang=en 850 // Note: prefixed by V to distinguish from the non-vector variant. 851 VABS 852 // VSQADD is the SQADD(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQADD--Signed-saturating-Add-?lang=en 853 // Note: prefixed by V to distinguish from the non-vector variant. 854 VSQADD 855 // VUQADD is the UQADD(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQADD--Unsigned-saturating-Add-?lang=en 856 // Note: prefixed by V to distinguish from the non-vector variant. 857 VUQADD 858 // VSQSUB is the SQSUB(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQSUB--Signed-saturating-Subtract-?lang=en 859 // Note: prefixed by V to distinguish from the non-vector variant. 860 VSQSUB 861 // VUQSUB is the UQSUB(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQSUB--Unsigned-saturating-Subtract-?lang=en 862 // Note: prefixed by V to distinguish from the non-vector variant. 863 VUQSUB 864 // SMIN is the SMIN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMIN--Signed-Minimum--vector--?lang=en 865 SMIN 866 // SMAX is the SMAX instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMAX--Signed-Maximum--vector--?lang=en 867 SMAX 868 // UMIN is the UMIN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMIN--Unsigned-Minimum--vector--?lang=en 869 UMIN 870 // UMAX is the UMAX instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMAX--Unsigned-Maximum--vector--?lang=en 871 UMAX 872 // URHADD is the URHADD instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/URHADD--Unsigned-Rounding-Halving-Add-?lang=en 873 URHADD 874 // REV64 is the REV64 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/REV64--Reverse-elements-in-64-bit-doublewords--vector--?lang=en 875 REV64 876 // XTN is the XTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/XTN--XTN2--Extract-Narrow-?lang=en 877 XTN 878 // VUMLAL is the UMLAL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMLAL--UMLAL2--vector---Unsigned-Multiply-Add-Long--vector--?lang=en 879 // Note: prefixed by V to distinguish from the non-vector variant. 880 VUMLAL 881 // SHLL is the SHLL instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SHLL--SHLL2--Shift-Left-Long--by-element-size--?lang=en 882 SHLL 883 // SADDLP is the SADDLP instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SADDLP--Signed-Add-Long-Pairwise-?lang=en 884 SADDLP 885 // UADDLP is the UADDLP instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UADDLP--Unsigned-Add-Long-Pairwise-?lang=en 886 UADDLP 887 // SSHLL2 is the SSHLL2(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- 888 SSHLL2 889 // USHLL2 is the USHLL2(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- 890 USHLL2 891 // SQRDMULH is the SQRDMULH(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQRDMULH--vector---Signed-saturating-Rounding-Doubling-Multiply-returning-High-half-?lang=en 892 SQRDMULH 893 // SMULL is the SMULL(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMULL--SMULL2--vector---Signed-Multiply-Long--vector--?lang=en 894 SMULL 895 // SMULL2 is the SMULL2(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMULL--SMULL2--vector---Signed-Multiply-Long--vector--?lang=en 896 SMULL2 897 // UMULL is the UMULL instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en 898 UMULL 899 // UMULL2 is the UMULL2 instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en 900 UMULL2 901 // VFCVTZS is the FCVTZS(vector,integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTZS--vector--integer---Floating-point-Convert-to-Signed-integer--rounding-toward-Zero--vector--?lang=en 902 // Note: prefixed by V to distinguish from the non-vector variant. 903 VFCVTZS 904 // VFCVTZU is the FCVTZU(vector,integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTZU--vector--integer---Floating-point-Convert-to-Unsigned-integer--rounding-toward-Zero--vector--?lang=en 905 // Note: prefixed by V to distinguish from the non-vector variant. 906 VFCVTZU 907 // SQXTN is the SQXTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTN--SQXTN2--Signed-saturating-extract-Narrow-?lang=en 908 SQXTN 909 // UQXTN is the UQXTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQXTN--UQXTN2--Unsigned-saturating-extract-Narrow-?lang=en 910 UQXTN 911 // SQXTN2 is the SQXTN2 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTN--SQXTN2--Signed-saturating-extract-Narrow-?lang=en 912 SQXTN2 913 // SQXTUN is the SQXTUN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTUN--SQXTUN2--Signed-saturating-extract-Unsigned-Narrow-?lang=en 914 SQXTUN 915 // SQXTUN2 is the SQXTUN2 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTUN--SQXTUN2--Signed-saturating-extract-Unsigned-Narrow-?lang=en 916 SQXTUN2 917 // VSCVTF is the SCVTF(vector, integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SCVTF--vector--integer---Signed-integer-Convert-to-Floating-point--vector--?lang=en 918 // Note: prefixed by V to distinguish from the non-vector variant. 919 VSCVTF 920 // VUCVTF is the UCVTF(vector, integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UCVTF--vector--integer---Unsigned-integer-Convert-to-Floating-point--vector--?lang=en 921 // Note: prefixed by V to distinguish from the non-vector variant. 922 VUCVTF 923 // FCVTL is the FCVTL instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTL--FCVTL2--Floating-point-Convert-to-higher-precision-Long--vector--?lang=en 924 FCVTL 925 // FCVTN is the FCVTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTN--FCVTN2--Floating-point-Convert-to-lower-precision-Narrow--vector--?lang=en 926 FCVTN 927 928 // instructionEnd is always placed at the bottom of this iota definition to be used in the test. 929 instructionEnd 930 ) 931 932 // VectorArrangement is the arrangement of data within a vector register. 933 type VectorArrangement byte 934 935 const ( 936 // VectorArrangementNone is an arrangement indicating no data is stored. 937 VectorArrangementNone VectorArrangement = iota 938 // VectorArrangement8B is an arrangement of 8 bytes (64-bit vector) 939 VectorArrangement8B 940 // VectorArrangement16B is an arrangement of 16 bytes (128-bit vector) 941 VectorArrangement16B 942 // VectorArrangement4H is an arrangement of 4 half precisions (64-bit vector) 943 VectorArrangement4H 944 // VectorArrangement8H is an arrangement of 8 half precisions (128-bit vector) 945 VectorArrangement8H 946 // VectorArrangement2S is an arrangement of 2 single precisions (64-bit vector) 947 VectorArrangement2S 948 // VectorArrangement4S is an arrangement of 4 single precisions (128-bit vector) 949 VectorArrangement4S 950 // VectorArrangement1D is an arrangement of 1 double precision (64-bit vector) 951 VectorArrangement1D 952 // VectorArrangement2D is an arrangement of 2 double precisions (128-bit vector) 953 VectorArrangement2D 954 955 // Assign each vector size specifier to a vector arrangement ID. 956 // Instructions can only have an arrangement or a size specifier, but not both, so it 957 // simplifies the internal representation of vector instructions by being able to 958 // store either into the same field. 959 960 // VectorArrangementB is a size specifier of byte 961 VectorArrangementB 962 // VectorArrangementH is a size specifier of word (16-bit) 963 VectorArrangementH 964 // VectorArrangementS is a size specifier of double word (32-bit) 965 VectorArrangementS 966 // VectorArrangementD is a size specifier of quad word (64-bit) 967 VectorArrangementD 968 // VectorArrangementQ is a size specifier of the entire vector (128-bit) 969 VectorArrangementQ 970 ) 971 972 func (v VectorArrangement) String() (ret string) { 973 switch v { 974 case VectorArrangement8B: 975 ret = "8B" 976 case VectorArrangement16B: 977 ret = "16B" 978 case VectorArrangement4H: 979 ret = "4H" 980 case VectorArrangement8H: 981 ret = "8H" 982 case VectorArrangement2S: 983 ret = "2S" 984 case VectorArrangement4S: 985 ret = "4S" 986 case VectorArrangement1D: 987 ret = "1D" 988 case VectorArrangement2D: 989 ret = "2D" 990 case VectorArrangementB: 991 ret = "B" 992 case VectorArrangementH: 993 ret = "H" 994 case VectorArrangementS: 995 ret = "S" 996 case VectorArrangementD: 997 ret = "D" 998 case VectorArrangementQ: 999 ret = "Q" 1000 case VectorArrangementNone: 1001 ret = "none" 1002 default: 1003 panic(v) 1004 } 1005 return 1006 } 1007 1008 // VectorIndex is the index of an element of a vector register 1009 type VectorIndex byte 1010 1011 // VectorIndexNone indicates no vector index specified. 1012 const VectorIndexNone = ^VectorIndex(0) 1013 1014 // InstructionName returns the name of the given instruction 1015 func InstructionName(i asm.Instruction) string { 1016 switch i { 1017 case NOP: 1018 return "NOP" 1019 case RET: 1020 return "RET" 1021 case ADD: 1022 return "ADD" 1023 case ADDS: 1024 return "ADDS" 1025 case ADDW: 1026 return "ADDW" 1027 case ADR: 1028 return "ADR" 1029 case AND: 1030 return "AND" 1031 case ANDIMM32: 1032 return "ANDIMM32" 1033 case ANDIMM64: 1034 return "ANDIMM64" 1035 case ANDW: 1036 return "ANDW" 1037 case ASR: 1038 return "ASR" 1039 case ASRW: 1040 return "ASRW" 1041 case B: 1042 return "B" 1043 case BCONDEQ: 1044 return "BCONDEQ" 1045 case BCONDGE: 1046 return "BCONDGE" 1047 case BCONDGT: 1048 return "BCONDGT" 1049 case BCONDHI: 1050 return "BCONDHI" 1051 case BCONDHS: 1052 return "BCONDHS" 1053 case BCONDLE: 1054 return "BCONDLE" 1055 case BCONDLO: 1056 return "BCONDLO" 1057 case BCONDLS: 1058 return "BCONDLS" 1059 case BCONDLT: 1060 return "BCONDLT" 1061 case BCONDMI: 1062 return "BCONDMI" 1063 case BCONDPL: 1064 return "BCONDPL" 1065 case BCONDNE: 1066 return "BCONDNE" 1067 case BCONDVS: 1068 return "BCONDVS" 1069 case CLZ: 1070 return "CLZ" 1071 case CLZW: 1072 return "CLZW" 1073 case CMP: 1074 return "CMP" 1075 case CMPW: 1076 return "CMPW" 1077 case CSET: 1078 return "CSET" 1079 case EOR: 1080 return "EOR" 1081 case EORW: 1082 return "EORW" 1083 case FABSD: 1084 return "FABSD" 1085 case FABSS: 1086 return "FABSS" 1087 case FADDD: 1088 return "FADDD" 1089 case FADDS: 1090 return "FADDS" 1091 case FCMPD: 1092 return "FCMPD" 1093 case FCMPS: 1094 return "FCMPS" 1095 case FCVTDS: 1096 return "FCVTDS" 1097 case FCVTSD: 1098 return "FCVTSD" 1099 case FCVTZSD: 1100 return "FCVTZSD" 1101 case FCVTZSDW: 1102 return "FCVTZSDW" 1103 case FCVTZSS: 1104 return "FCVTZSS" 1105 case FCVTZSSW: 1106 return "FCVTZSSW" 1107 case FCVTZUD: 1108 return "FCVTZUD" 1109 case FCVTZUDW: 1110 return "FCVTZUDW" 1111 case FCVTZUS: 1112 return "FCVTZUS" 1113 case FCVTZUSW: 1114 return "FCVTZUSW" 1115 case FDIVD: 1116 return "FDIVD" 1117 case FDIVS: 1118 return "FDIVS" 1119 case FMAXD: 1120 return "FMAXD" 1121 case FMAXS: 1122 return "FMAXS" 1123 case FMIND: 1124 return "FMIND" 1125 case FMINS: 1126 return "FMINS" 1127 case FMOVD: 1128 return "FMOVD" 1129 case FMOVS: 1130 return "FMOVS" 1131 case FMULD: 1132 return "FMULD" 1133 case FMULS: 1134 return "FMULS" 1135 case FNEGD: 1136 return "FNEGD" 1137 case FNEGS: 1138 return "FNEGS" 1139 case FRINTMD: 1140 return "FRINTMD" 1141 case FRINTMS: 1142 return "FRINTMS" 1143 case FRINTND: 1144 return "FRINTND" 1145 case FRINTNS: 1146 return "FRINTNS" 1147 case FRINTPD: 1148 return "FRINTPD" 1149 case FRINTPS: 1150 return "FRINTPS" 1151 case FRINTZD: 1152 return "FRINTZD" 1153 case FRINTZS: 1154 return "FRINTZS" 1155 case FSQRTD: 1156 return "FSQRTD" 1157 case FSQRTS: 1158 return "FSQRTS" 1159 case FSUBD: 1160 return "FSUBD" 1161 case FSUBS: 1162 return "FSUBS" 1163 case LSL: 1164 return "LSL" 1165 case LSLW: 1166 return "LSLW" 1167 case LSR: 1168 return "LSR" 1169 case LSRW: 1170 return "LSRW" 1171 case LDRSBD: 1172 return "LDRSBD" 1173 case LDRSBW: 1174 return "LDRSBW" 1175 case LDRB: 1176 return "LDRB" 1177 case MOVD: 1178 return "MOVD" 1179 case LDRSHD: 1180 return "LDRSHD" 1181 case LDRSHW: 1182 return "LDRSHW" 1183 case LDRH: 1184 return "LDRH" 1185 case LDRSW: 1186 return "LDRSW" 1187 case STRD: 1188 return "STRD" 1189 case STRW: 1190 return "STRW" 1191 case STRH: 1192 return "STRH" 1193 case STRB: 1194 return "STRB" 1195 case MOVW: 1196 return "MOVW" 1197 case MRS: 1198 return "MRS" 1199 case MSR: 1200 return "MSR" 1201 case MSUB: 1202 return "MSUB" 1203 case MSUBW: 1204 return "MSUBW" 1205 case MUL: 1206 return "MUL" 1207 case MULW: 1208 return "MULW" 1209 case NEG: 1210 return "NEG" 1211 case NEGW: 1212 return "NEGW" 1213 case ORR: 1214 return "ORR" 1215 case ORRW: 1216 return "ORRW" 1217 case RBIT: 1218 return "RBIT" 1219 case RBITW: 1220 return "RBITW" 1221 case ROR: 1222 return "ROR" 1223 case RORW: 1224 return "RORW" 1225 case SCVTFD: 1226 return "SCVTFD" 1227 case SCVTFS: 1228 return "SCVTFS" 1229 case SCVTFWD: 1230 return "SCVTFWD" 1231 case SCVTFWS: 1232 return "SCVTFWS" 1233 case SDIV: 1234 return "SDIV" 1235 case SDIVW: 1236 return "SDIVW" 1237 case SUB: 1238 return "SUB" 1239 case SUBS: 1240 return "SUBS" 1241 case SUBW: 1242 return "SUBW" 1243 case SXTB: 1244 return "SXTB" 1245 case SXTBW: 1246 return "SXTBW" 1247 case SXTH: 1248 return "SXTH" 1249 case SXTHW: 1250 return "SXTHW" 1251 case SXTW: 1252 return "SXTW" 1253 case UCVTFD: 1254 return "UCVTFD" 1255 case UCVTFS: 1256 return "UCVTFS" 1257 case UCVTFWD: 1258 return "UCVTFWD" 1259 case UCVTFWS: 1260 return "UCVTFWS" 1261 case UDIV: 1262 return "UDIV" 1263 case UDIVW: 1264 return "UDIVW" 1265 case VBIT: 1266 return "VBIT" 1267 case VCNT: 1268 return "VCNT" 1269 case UADDLV: 1270 return "UADDLV" 1271 case VMOV: 1272 return "VMOV" 1273 case INSELEM: 1274 return "INSELEM" 1275 case UMOV: 1276 return "UMOV" 1277 case INSGEN: 1278 return "INSGEN" 1279 case VADD: 1280 return "VADD" 1281 case VFADDS: 1282 return "VFADDS" 1283 case VFADDD: 1284 return "VFADDD" 1285 case VSUB: 1286 return "VSUB" 1287 case VFSUBS: 1288 return "VFSUBS" 1289 case VFSUBD: 1290 return "VFSUBD" 1291 case SSHL: 1292 return "SSHL" 1293 case USHL: 1294 return "USHL" 1295 case SSHLL: 1296 return "SSHLL" 1297 case USHLL: 1298 return "USHLL" 1299 case LD1R: 1300 return "LD1R" 1301 case SMOV32: 1302 return "SMOV32" 1303 case DUPGEN: 1304 return "DUPGEN" 1305 case DUPELEM: 1306 return "DUPELEM" 1307 case UMAXP: 1308 return "UMAXP" 1309 case UMINV: 1310 return "UMINV" 1311 case CMEQ: 1312 return "CMEQ" 1313 case ADDP: 1314 return "ADDP" 1315 case VADDP: 1316 return "VADDP" 1317 case TBL1: 1318 return "TBL1" 1319 case TBL2: 1320 return "TBL2" 1321 case NOT: 1322 return "NOT" 1323 case VAND: 1324 return "VAND" 1325 case VORR: 1326 return "VORR" 1327 case BSL: 1328 return "BSL" 1329 case BIC: 1330 return "BIC" 1331 case VFNEG: 1332 return "VFNEG" 1333 case ADDV: 1334 return "ADDV" 1335 case CMEQZERO: 1336 return "CMEQZERO" 1337 case ZIP1: 1338 return "ZIP1" 1339 case SSHR: 1340 return "SSHR" 1341 case EXT: 1342 return "EXT" 1343 case CMGT: 1344 return "CMGT" 1345 case CMHI: 1346 return "CMHI" 1347 case CMGE: 1348 return "CMGE" 1349 case CMHS: 1350 return "CMHS" 1351 case FCMEQ: 1352 return "FCMEQ" 1353 case FCMGT: 1354 return "FCMGT" 1355 case FCMGE: 1356 return "FCMGE" 1357 case VFMUL: 1358 return "VFMUL" 1359 case VFDIV: 1360 return "VFDIV" 1361 case VFSQRT: 1362 return "VFSQRT" 1363 case VFMIN: 1364 return "VFMIN" 1365 case VFMAX: 1366 return "VFMAX" 1367 case VFABS: 1368 return "VFABS" 1369 case VFRINTP: 1370 return "VFRINTP" 1371 case VFRINTM: 1372 return "VFRINTM" 1373 case VFRINTZ: 1374 return "VFRINTZ" 1375 case VFRINTN: 1376 return "VFRINTN" 1377 case VMUL: 1378 return "VMUL" 1379 case VNEG: 1380 return "VNEG" 1381 case VABS: 1382 return "VABS" 1383 case VSQADD: 1384 return "VSQADD" 1385 case VUQADD: 1386 return "VUQADD" 1387 case SMIN: 1388 return "SMIN" 1389 case SMAX: 1390 return "SMAX" 1391 case UMIN: 1392 return "UMIN" 1393 case UMAX: 1394 return "UMAX" 1395 case URHADD: 1396 return "URHADD" 1397 case VSQSUB: 1398 return "VSQSUB" 1399 case VUQSUB: 1400 return "VUQSUB" 1401 case REV64: 1402 return "REV64" 1403 case XTN: 1404 return "XTN" 1405 case VUMLAL: 1406 return "VUMLAL" 1407 case SHLL: 1408 return "SHLL" 1409 case SSHLL2: 1410 return "SSHLL2" 1411 case USHLL2: 1412 return "USHLL2" 1413 case SQRDMULH: 1414 return "SQRDMULH" 1415 case SADDLP: 1416 return "SADDLP" 1417 case UADDLP: 1418 return "UADDLP" 1419 case SMULL: 1420 return "SMULL" 1421 case SMULL2: 1422 return "SMULL2" 1423 case UMULL: 1424 return "UMULL" 1425 case UMULL2: 1426 return "UMULL2" 1427 case VFCVTZS: 1428 return "VFCVTZS" 1429 case VFCVTZU: 1430 return "VFCVTZU" 1431 case SQXTN: 1432 return "SQXTN" 1433 case UQXTN: 1434 return "UQXTN" 1435 case SQXTN2: 1436 return "SQXTN2" 1437 case SQXTUN: 1438 return "SQXTUN" 1439 case SQXTUN2: 1440 return "SQXTUN2" 1441 case VSCVTF: 1442 return "VSCVTF" 1443 case VUCVTF: 1444 return "VUCVTF" 1445 case FCVTL: 1446 return "FCVTL" 1447 case FCVTN: 1448 return "FCVTN" 1449 case FSTRD: 1450 return "FSTRD" 1451 case FSTRS: 1452 return "FSTRS" 1453 case LDRD: 1454 return "LDRD" 1455 case LDRW: 1456 return "LDRW" 1457 case FLDRD: 1458 return "FLDRD" 1459 case FLDRS: 1460 return "FLDRS" 1461 } 1462 panic(fmt.Errorf("unknown instruction %d", i)) 1463 }