wa-lang.org/wazero@v1.0.2/internal/asm/arm64/impl_4_test.go (about) 1 package arm64 2 3 import ( 4 "encoding/hex" 5 "fmt" 6 "math" 7 "testing" 8 9 "wa-lang.org/wazero/internal/asm" 10 "wa-lang.org/wazero/internal/testing/require" 11 ) 12 13 func TestAssemblerImpl_encodeJumpToRegister(t *testing.T) { 14 t.Run("error", func(t *testing.T) { 15 tests := []struct { 16 n *nodeImpl 17 expErr string 18 }{ 19 { 20 n: &nodeImpl{instruction: ADD, types: operandTypesNoneToRegister}, 21 expErr: "ADD is unsupported for from:none,to:register type", 22 }, 23 { 24 n: &nodeImpl{instruction: RET, dstReg: asm.NilRegister}, 25 expErr: "invalid destination register: nil is not integer", 26 }, 27 { 28 n: &nodeImpl{instruction: RET, dstReg: RegV0}, 29 expErr: "invalid destination register: V0 is not integer", 30 }, 31 } 32 33 for _, tt := range tests { 34 tc := tt 35 a := NewAssembler(asm.NilRegister) 36 err := a.encodeJumpToRegister(tc.n) 37 require.EqualError(t, err, tc.expErr) 38 } 39 }) 40 41 tests := []struct { 42 name string 43 inst asm.Instruction 44 reg asm.Register 45 expHex string 46 }{ 47 { 48 name: "B", 49 inst: B, 50 reg: RegR0, 51 expHex: "00001fd6000000000000000000000000", 52 }, 53 { 54 name: "B", 55 inst: B, 56 reg: RegR5, 57 expHex: "a0001fd6000000000000000000000000", 58 }, 59 { 60 name: "B", 61 inst: B, 62 reg: RegR30, 63 expHex: "c0031fd6000000000000000000000000", 64 }, 65 { 66 name: "RET", 67 inst: RET, 68 reg: RegR0, 69 expHex: "00005fd6000000000000000000000000", 70 }, 71 { 72 name: "RET", 73 inst: RET, 74 reg: RegR5, 75 expHex: "a0005fd6000000000000000000000000", 76 }, 77 { 78 name: "RET", 79 inst: RET, 80 reg: RegR30, 81 expHex: "c0035fd6000000000000000000000000", 82 }, 83 } 84 85 for _, tc := range tests { 86 tc := tc 87 t.Run(tc.name, func(t *testing.T) { 88 a := NewAssembler(asm.NilRegister) 89 err := a.encodeJumpToRegister(&nodeImpl{instruction: tc.inst, dstReg: tc.reg}) 90 require.NoError(t, err) 91 92 actual := a.bytes() 93 require.Equal(t, tc.expHex, hex.EncodeToString(actual)) 94 }) 95 } 96 } 97 98 func TestAssemblerImpl_EncodeMemoryToRegister(t *testing.T) { 99 t.Run("error", func(t *testing.T) { 100 tests := []struct { 101 n *nodeImpl 102 expErr string 103 }{ 104 { 105 n: &nodeImpl{instruction: SUB, types: operandTypesMemoryToRegister}, 106 expErr: "SUB is unsupported for from:memory,to:register type", 107 }, 108 } 109 110 for _, tt := range tests { 111 tc := tt 112 a := NewAssembler(asm.NilRegister) 113 err := a.encodeMemoryToRegister(tc.n) 114 require.EqualError(t, err, tc.expErr) 115 } 116 }) 117 118 tests := []struct { 119 name string 120 n *nodeImpl 121 exp []byte 122 }{ 123 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x5f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 124 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x40, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 125 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x40, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 126 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x20, 0x40, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 127 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: -2, dstReg: RegR11}, exp: []byte{0xab, 0xe0, 0x5f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 128 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x40, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 129 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: -15, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x5f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 130 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x10", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 16, dstReg: RegR11}, exp: []byte{0xab, 0x8, 0x40, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 131 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x40, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 132 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x11", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 17, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x41, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 133 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x58, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 134 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: -256, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x50, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 135 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x50", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 80, dstReg: RegR11}, exp: []byte{0xab, 0x28, 0x40, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 136 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x58, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 137 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xff", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 255, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x4f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 138 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x1000", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x48, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 139 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x2000", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x50, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 140 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xab, 0xfc, 0x7f, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 141 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xfff0", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xbb, 0x20, 0x40, 0x91, 0x6b, 0xfb, 0x7f, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 142 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffe8", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xbb, 0x20, 0x40, 0x91, 0x6b, 0xf7, 0x7f, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 143 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffe0", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xbb, 0x20, 0x40, 0x91, 0x6b, 0xf3, 0x7f, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 144 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x8000000", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 145 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x40000000", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 146 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x40000008", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 147 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 148 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x40000010", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 149 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 150 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 151 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x10000004", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 152 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x100008", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x6b, 0x7, 0x40, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 153 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xbb, 0xe0, 0x43, 0x91, 0x6b, 0xff, 0x7f, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 154 {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=RegR8", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0x68, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 155 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: -1, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x5f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 156 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x0", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 0, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x40, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 157 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x1", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x40, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 158 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x2", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 2, dstReg: RegR11}, exp: []byte{0xcb, 0x23, 0x40, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 159 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: -2, dstReg: RegR11}, exp: []byte{0xcb, 0xe3, 0x5f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 160 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x40, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 161 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: -15, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x5f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 162 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x10", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 16, dstReg: RegR11}, exp: []byte{0xcb, 0xb, 0x40, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 163 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x40, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 164 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x11", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 17, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x41, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 165 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x58, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 166 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: -256, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x50, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 167 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x50", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 80, dstReg: RegR11}, exp: []byte{0xcb, 0x2b, 0x40, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 168 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x58, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 169 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xff", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 255, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x4f, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 170 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x1000", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x48, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 171 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x2000", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x50, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 172 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xcb, 0xff, 0x7f, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 173 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xfff0", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x6b, 0xfb, 0x7f, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 174 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffe8", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x6b, 0xf7, 0x7f, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 175 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffe0", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x6b, 0xf3, 0x7f, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 176 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x8000000", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 177 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x40000000", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 178 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x40000008", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 179 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 180 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x40000010", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 181 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 182 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 183 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x10000004", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 184 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x100008", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x6b, 0x7, 0x40, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 185 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xdb, 0xe3, 0x43, 0x91, 0x6b, 0xff, 0x7f, 0xf9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 186 {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=RegR8", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xcb, 0x6b, 0x68, 0xf8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 187 {name: "LDRW/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRW, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x5f, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 188 {name: "LDRW/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRW, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x40, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 189 {name: "LDRW/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRW, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x40, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 190 {name: "LDRW/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRW, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x20, 0x40, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 191 {name: "LDRW/RegisterOffset/dst=R11,base=R5,offsetReg=R12", n: &nodeImpl{instruction: LDRW, srcReg: RegR5, srcReg2: RegR12, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0x6c, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 192 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x9f, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 193 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x80, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 194 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x80, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 195 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x20, 0x80, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 196 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: -2, dstReg: RegR11}, exp: []byte{0xab, 0xe0, 0x9f, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 197 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x80, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 198 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: -15, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x9f, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 199 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x10", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 16, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x80, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 200 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x80, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 201 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x11", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 17, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x81, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 202 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x98, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 203 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: -256, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x90, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 204 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x50", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 80, dstReg: RegR11}, exp: []byte{0xab, 0x50, 0x80, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 205 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x98, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 206 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xff", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 255, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x8f, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 207 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x1000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x90, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 208 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x2000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0xa0, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 209 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xbb, 0x10, 0x40, 0x91, 0x6b, 0xfb, 0xbf, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 210 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xfff0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xbb, 0x30, 0x40, 0x91, 0x6b, 0xf3, 0xbf, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 211 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffe8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xbb, 0x30, 0x40, 0x91, 0x6b, 0xeb, 0xbf, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 212 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffe0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xbb, 0x30, 0x40, 0x91, 0x6b, 0xe3, 0xbf, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 213 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x8000000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 214 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x40000000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 215 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x40000008", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 216 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 217 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x40000010", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 218 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 219 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 220 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x10000004", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 221 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x100008", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x6b, 0xb, 0x80, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 222 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xbb, 0xf0, 0x43, 0x91, 0x6b, 0xfb, 0xbf, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 223 {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=RegR8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0xa8, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 224 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: -1, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x9f, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 225 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 0, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x80, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 226 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x1", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x80, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 227 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x2", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 2, dstReg: RegR11}, exp: []byte{0xcb, 0x23, 0x80, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 228 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: -2, dstReg: RegR11}, exp: []byte{0xcb, 0xe3, 0x9f, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 229 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x80, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 230 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: -15, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x9f, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 231 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x10", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 16, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x80, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 232 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x80, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 233 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x11", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 17, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x81, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 234 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x98, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 235 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: -256, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x90, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 236 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x50", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 80, dstReg: RegR11}, exp: []byte{0xcb, 0x53, 0x80, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 237 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x98, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 238 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xff", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 255, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x8f, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 239 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x1000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x90, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 240 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x2000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0xa0, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 241 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x6b, 0xfb, 0xbf, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 242 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xfff0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x6b, 0xf3, 0xbf, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 243 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffe8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x6b, 0xeb, 0xbf, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 244 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffe0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x6b, 0xe3, 0xbf, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 245 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x8000000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 246 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x40000000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 247 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x40000008", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 248 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 249 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x40000010", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 250 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 251 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 252 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x10000004", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 253 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x100008", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x6b, 0xb, 0x80, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 254 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xdb, 0xf3, 0x43, 0x91, 0x6b, 0xfb, 0xbf, 0xb9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 255 {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=RegR8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xcb, 0x6b, 0xa8, 0xb8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 256 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x9f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 257 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x80, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 258 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x80, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 259 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x4, 0x80, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 260 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: -2, dstReg: RegR11}, exp: []byte{0xab, 0xe0, 0x9f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 261 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x80, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 262 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: -15, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x9f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 263 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x10", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 16, dstReg: RegR11}, exp: []byte{0xab, 0x20, 0x80, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 264 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x80, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 265 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x11", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 17, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x81, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 266 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x98, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 267 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: -256, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x90, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 268 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x50", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 80, dstReg: RegR11}, exp: []byte{0xab, 0xa0, 0x80, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 269 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x98, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 270 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xff", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 255, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x8f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 271 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x1000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0xa0, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 272 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x2000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xbb, 0x8, 0x40, 0x91, 0x6b, 0x3, 0x80, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 273 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xbb, 0x18, 0x40, 0x91, 0x6b, 0xf3, 0xbf, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 274 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xfff0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xbb, 0x38, 0x40, 0x91, 0x6b, 0xe3, 0xbf, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 275 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffe8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xbb, 0x38, 0x40, 0x91, 0x6b, 0xd3, 0xbf, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 276 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffe0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xbb, 0x38, 0x40, 0x91, 0x6b, 0xc3, 0xbf, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 277 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x8000000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 278 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x40000000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 279 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x40000008", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 280 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 281 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x40000010", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 282 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 283 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 284 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x10000004", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 285 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x100008", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x6b, 0x13, 0x80, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 286 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xbb, 0xf8, 0x43, 0x91, 0x6b, 0xf3, 0xbf, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 287 {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=RegR8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0xa8, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 288 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: -1, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x9f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 289 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 0, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x80, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 290 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x1", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x80, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 291 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x2", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 2, dstReg: RegR11}, exp: []byte{0xcb, 0x7, 0x80, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 292 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: -2, dstReg: RegR11}, exp: []byte{0xcb, 0xe3, 0x9f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 293 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x80, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 294 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: -15, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x9f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 295 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x10", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 16, dstReg: RegR11}, exp: []byte{0xcb, 0x23, 0x80, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 296 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x80, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 297 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x11", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 17, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x81, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 298 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x98, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 299 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: -256, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x90, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 300 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x50", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 80, dstReg: RegR11}, exp: []byte{0xcb, 0xa3, 0x80, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 301 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x98, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 302 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xff", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 255, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x8f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 303 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x1000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0xa0, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 304 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x2000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x6b, 0x3, 0x80, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 305 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xdb, 0x1b, 0x40, 0x91, 0x6b, 0xf3, 0xbf, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 306 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xfff0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x6b, 0xe3, 0xbf, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 307 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffe8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x6b, 0xd3, 0xbf, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 308 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffe0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x6b, 0xc3, 0xbf, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 309 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x8000000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 310 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x40000000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 311 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x40000008", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 312 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 313 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x40000010", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 314 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 315 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 316 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x10000004", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 317 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x100008", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x6b, 0x13, 0x80, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 318 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xdb, 0xfb, 0x43, 0x91, 0x6b, 0xf3, 0xbf, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 319 {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=RegR8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xcb, 0x6b, 0xa8, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 320 {name: "LDRSHW/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSHW, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0xdf, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 321 {name: "LDRSHW/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRSHW, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0xc0, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 322 {name: "LDRSHW/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRSHW, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0xc0, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 323 {name: "LDRSHW/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRSHW, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x4, 0xc0, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 324 {name: "LDRSHW/RegisterOffset/dst=R11,base=R5,offsetReg=R12", n: &nodeImpl{instruction: LDRSHW, srcReg: RegR5, srcReg2: RegR12, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0xec, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 325 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x5f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 326 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x40, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 327 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x40, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 328 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x4, 0x40, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 329 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: -2, dstReg: RegR11}, exp: []byte{0xab, 0xe0, 0x5f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 330 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x40, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 331 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: -15, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x5f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 332 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x10", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 16, dstReg: RegR11}, exp: []byte{0xab, 0x20, 0x40, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 333 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x40, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 334 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x11", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 17, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x41, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 335 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x58, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 336 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: -256, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x50, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 337 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x50", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 80, dstReg: RegR11}, exp: []byte{0xab, 0xa0, 0x40, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 338 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x58, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 339 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xff", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 255, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x4f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 340 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x1000", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x60, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 341 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x2000", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xbb, 0x8, 0x40, 0x91, 0x6b, 0x3, 0x40, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 342 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xbb, 0x18, 0x40, 0x91, 0x6b, 0xf3, 0x7f, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 343 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xfff0", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xbb, 0x38, 0x40, 0x91, 0x6b, 0xe3, 0x7f, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 344 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffe8", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xbb, 0x38, 0x40, 0x91, 0x6b, 0xd3, 0x7f, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 345 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffe0", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xbb, 0x38, 0x40, 0x91, 0x6b, 0xc3, 0x7f, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 346 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x8000000", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 347 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x40000000", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 348 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x40000008", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 349 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 350 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x40000010", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 351 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 352 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 353 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x10000004", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 354 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x100008", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x6b, 0x13, 0x40, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 355 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xbb, 0xf8, 0x43, 0x91, 0x6b, 0xf3, 0x7f, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 356 {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=RegR8", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0x68, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 357 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: -1, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x5f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 358 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x0", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 0, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x40, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 359 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x1", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x40, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 360 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x2", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 2, dstReg: RegR11}, exp: []byte{0xcb, 0x7, 0x40, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 361 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: -2, dstReg: RegR11}, exp: []byte{0xcb, 0xe3, 0x5f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 362 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x40, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 363 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: -15, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x5f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 364 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x10", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 16, dstReg: RegR11}, exp: []byte{0xcb, 0x23, 0x40, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 365 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x40, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 366 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x11", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 17, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x41, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 367 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x58, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 368 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: -256, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x50, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 369 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x50", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 80, dstReg: RegR11}, exp: []byte{0xcb, 0xa3, 0x40, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 370 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x58, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 371 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xff", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 255, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x4f, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 372 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x1000", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x60, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 373 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x2000", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x6b, 0x3, 0x40, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 374 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xdb, 0x1b, 0x40, 0x91, 0x6b, 0xf3, 0x7f, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 375 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xfff0", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x6b, 0xe3, 0x7f, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 376 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffe8", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x6b, 0xd3, 0x7f, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 377 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffe0", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x6b, 0xc3, 0x7f, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 378 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x8000000", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 379 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x40000000", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 380 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x40000008", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 381 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 382 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x40000010", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 383 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 384 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 385 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x10000004", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 386 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x100008", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x6b, 0x13, 0x40, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 387 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xdb, 0xfb, 0x43, 0x91, 0x6b, 0xf3, 0x7f, 0x79, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 388 {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=RegR8", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xcb, 0x6b, 0x68, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 389 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x9f, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 390 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 391 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x4, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 392 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x8, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 393 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: -2, dstReg: RegR11}, exp: []byte{0xab, 0xe0, 0x9f, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 394 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0x3c, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 395 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: -15, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x9f, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 396 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x10", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 16, dstReg: RegR11}, exp: []byte{0xab, 0x40, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 397 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0x3c, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 398 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x11", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 17, dstReg: RegR11}, exp: []byte{0xab, 0x44, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 399 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x98, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 400 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: -256, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x90, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 401 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x50", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 80, dstReg: RegR11}, exp: []byte{0xab, 0x40, 0x81, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 402 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x98, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 403 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xff", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 255, dstReg: RegR11}, exp: []byte{0xab, 0xfc, 0x83, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 404 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x1000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xbb, 0x4, 0x40, 0x91, 0x6b, 0x3, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 405 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x2000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xbb, 0x8, 0x40, 0x91, 0x6b, 0x3, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 406 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xbb, 0x1c, 0x40, 0x91, 0x6b, 0xe3, 0xbf, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 407 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xfff0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xbb, 0x3c, 0x40, 0x91, 0x6b, 0xc3, 0xbf, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 408 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffe8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xbb, 0x3c, 0x40, 0x91, 0x6b, 0xa3, 0xbf, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 409 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffe0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xbb, 0x3c, 0x40, 0x91, 0x6b, 0x83, 0xbf, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 410 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x8000000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 411 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x40000000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 412 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x40000008", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 413 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 414 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x40000010", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 415 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 416 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 417 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x10000004", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 418 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x100008", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x6b, 0x23, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 419 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xbb, 0xfc, 0x43, 0x91, 0x6b, 0xe3, 0xbf, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 420 {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=RegR8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0xa8, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 421 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: -1, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x9f, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 422 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 0, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 423 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x1", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1, dstReg: RegR11}, exp: []byte{0xcb, 0x7, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 424 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x2", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 2, dstReg: RegR11}, exp: []byte{0xcb, 0xb, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 425 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: -2, dstReg: RegR11}, exp: []byte{0xcb, 0xe3, 0x9f, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 426 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0x3f, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 427 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: -15, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x9f, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 428 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x10", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 16, dstReg: RegR11}, exp: []byte{0xcb, 0x43, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 429 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0x3f, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 430 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x11", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 17, dstReg: RegR11}, exp: []byte{0xcb, 0x47, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 431 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x98, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 432 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: -256, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x90, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 433 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x50", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 80, dstReg: RegR11}, exp: []byte{0xcb, 0x43, 0x81, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 434 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x98, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 435 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xff", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 255, dstReg: RegR11}, exp: []byte{0xcb, 0xff, 0x83, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 436 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x1000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xdb, 0x7, 0x40, 0x91, 0x6b, 0x3, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 437 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x2000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x6b, 0x3, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 438 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xdb, 0x1f, 0x40, 0x91, 0x6b, 0xe3, 0xbf, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 439 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xfff0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x6b, 0xc3, 0xbf, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 440 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffe8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x6b, 0xa3, 0xbf, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 441 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffe0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x6b, 0x83, 0xbf, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 442 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x8000000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 443 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x40000000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 444 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x40000008", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 445 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 446 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x40000010", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 447 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 448 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 449 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x10000004", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 450 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x100008", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x6b, 0x23, 0x80, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 451 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xdb, 0xff, 0x43, 0x91, 0x6b, 0xe3, 0xbf, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 452 {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=RegR8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xcb, 0x6b, 0xa8, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 453 {name: "LDRSBW/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRSBW, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0xc0, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 454 {name: "LDRSBW/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRSBW, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x4, 0xc0, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 455 {name: "LDRSBW/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRSBW, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x8, 0xc0, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 456 {name: "LDRSBW/RegisterOffset/dst=R11,base=R5,offsetReg=R12", n: &nodeImpl{instruction: LDRSBW, srcReg: RegR5, srcReg2: RegR12, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0xec, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 457 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x5f, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 458 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 459 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x4, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 460 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x8, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 461 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: -2, dstReg: RegR11}, exp: []byte{0xab, 0xe0, 0x5f, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 462 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0x3c, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 463 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: -15, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x5f, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 464 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x10", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 16, dstReg: RegR11}, exp: []byte{0xab, 0x40, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 465 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0x3c, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 466 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x11", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 17, dstReg: RegR11}, exp: []byte{0xab, 0x44, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 467 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x58, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 468 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: -256, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x50, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 469 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x50", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 80, dstReg: RegR11}, exp: []byte{0xab, 0x40, 0x41, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 470 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x58, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 471 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xff", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 255, dstReg: RegR11}, exp: []byte{0xab, 0xfc, 0x43, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 472 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x1000", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xbb, 0x4, 0x40, 0x91, 0x6b, 0x3, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 473 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x2000", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xbb, 0x8, 0x40, 0x91, 0x6b, 0x3, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 474 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xbb, 0x1c, 0x40, 0x91, 0x6b, 0xe3, 0x7f, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 475 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xfff0", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xbb, 0x3c, 0x40, 0x91, 0x6b, 0xc3, 0x7f, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 476 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffe8", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xbb, 0x3c, 0x40, 0x91, 0x6b, 0xa3, 0x7f, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 477 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffe0", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xbb, 0x3c, 0x40, 0x91, 0x6b, 0x83, 0x7f, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 478 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x8000000", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 479 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x40000000", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 480 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x40000008", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 481 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 482 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x40000010", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 483 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 484 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 485 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x10000004", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 486 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x100008", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x6b, 0x23, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 487 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xbb, 0xfc, 0x43, 0x91, 0x6b, 0xe3, 0x7f, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 488 {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=RegR8", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0x68, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 489 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: -1, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x5f, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 490 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x0", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 0, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 491 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x1", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1, dstReg: RegR11}, exp: []byte{0xcb, 0x7, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 492 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x2", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 2, dstReg: RegR11}, exp: []byte{0xcb, 0xb, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 493 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: -2, dstReg: RegR11}, exp: []byte{0xcb, 0xe3, 0x5f, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 494 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0x3f, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 495 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: -15, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x5f, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 496 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x10", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 16, dstReg: RegR11}, exp: []byte{0xcb, 0x43, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 497 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0x3f, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 498 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x11", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 17, dstReg: RegR11}, exp: []byte{0xcb, 0x47, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 499 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x58, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 500 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: -256, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x50, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 501 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x50", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 80, dstReg: RegR11}, exp: []byte{0xcb, 0x43, 0x41, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 502 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x58, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 503 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xff", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 255, dstReg: RegR11}, exp: []byte{0xcb, 0xff, 0x43, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 504 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x1000", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xdb, 0x7, 0x40, 0x91, 0x6b, 0x3, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 505 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x2000", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x6b, 0x3, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 506 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xdb, 0x1f, 0x40, 0x91, 0x6b, 0xe3, 0x7f, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 507 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xfff0", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x6b, 0xc3, 0x7f, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 508 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffe8", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x6b, 0xa3, 0x7f, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 509 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffe0", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x6b, 0x83, 0x7f, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 510 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x8000000", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 511 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x40000000", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 512 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x40000008", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 513 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 514 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x40000010", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 515 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 516 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 517 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x10000004", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 518 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x100008", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x6b, 0x23, 0x40, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 519 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xdb, 0xff, 0x43, 0x91, 0x6b, 0xe3, 0x7f, 0x39, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 520 {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=RegR8", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xcb, 0x6b, 0x68, 0x38, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 521 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: -1, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x5f, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 522 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 0, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x40, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 523 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x1", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x40, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 524 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x2", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 2, dstReg: RegV30}, exp: []byte{0xbe, 0x20, 0x40, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 525 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: -2, dstReg: RegV30}, exp: []byte{0xbe, 0xe0, 0x5f, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 526 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xf", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 15, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x40, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 527 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: -15, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x5f, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 528 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x10", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 16, dstReg: RegV30}, exp: []byte{0xbe, 0x8, 0x40, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 529 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xf", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 15, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x40, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 530 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x11", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 17, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x41, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 531 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: -128, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x58, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 532 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: -256, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x50, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 533 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x50", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 80, dstReg: RegV30}, exp: []byte{0xbe, 0x28, 0x40, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 534 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: -128, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x58, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 535 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xff", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 255, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x4f, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 536 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x1000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 4096, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x48, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 537 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x2000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 8192, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x50, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 538 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 32760, dstReg: RegV30}, exp: []byte{0xbe, 0xfc, 0x7f, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 539 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xfff0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 65520, dstReg: RegV30}, exp: []byte{0xbb, 0x20, 0x40, 0x91, 0x7e, 0xfb, 0x7f, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 540 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffe8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 65512, dstReg: RegV30}, exp: []byte{0xbb, 0x20, 0x40, 0x91, 0x7e, 0xf7, 0x7f, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 541 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffe0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 65504, dstReg: RegV30}, exp: []byte{0xbb, 0x20, 0x40, 0x91, 0x7e, 0xf3, 0x7f, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 542 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x8000000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 134217728, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 543 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x40000000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1073741824, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 544 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x40000008", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1073741832, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 545 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1073741816, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 546 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x40000010", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1073741840, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 547 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1073741808, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 548 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 2147483640, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 549 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x10000004", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 268435460, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 550 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x100008", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1048584, dstReg: RegV30}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x7e, 0x7, 0x40, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 551 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1048568, dstReg: RegV30}, exp: []byte{0xbb, 0xe0, 0x43, 0x91, 0x7e, 0xff, 0x7f, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 552 {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=RegR8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcReg2: RegR8, dstReg: RegV30}, exp: []byte{0xbe, 0x68, 0x68, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 553 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: -1, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x5f, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 554 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 0, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x40, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 555 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x1", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x40, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 556 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x2", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 2, dstReg: RegV30}, exp: []byte{0xde, 0x23, 0x40, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 557 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: -2, dstReg: RegV30}, exp: []byte{0xde, 0xe3, 0x5f, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 558 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 15, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x40, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 559 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: -15, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x5f, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 560 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x10", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 16, dstReg: RegV30}, exp: []byte{0xde, 0xb, 0x40, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 561 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 15, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x40, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 562 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x11", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 17, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x41, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 563 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: -128, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x58, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 564 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: -256, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x50, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 565 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x50", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 80, dstReg: RegV30}, exp: []byte{0xde, 0x2b, 0x40, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 566 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: -128, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x58, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 567 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xff", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 255, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x4f, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 568 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x1000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 4096, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x48, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 569 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x2000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 8192, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x50, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 570 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 32760, dstReg: RegV30}, exp: []byte{0xde, 0xff, 0x7f, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 571 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 65520, dstReg: RegV30}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xfb, 0x7f, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 572 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 65512, dstReg: RegV30}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf7, 0x7f, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 573 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 65504, dstReg: RegV30}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf3, 0x7f, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 574 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 134217728, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 575 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1073741824, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 576 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1073741832, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 577 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1073741816, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 578 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1073741840, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 579 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1073741808, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 580 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 2147483640, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 581 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 268435460, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 582 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x100008", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1048584, dstReg: RegV30}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x7e, 0x7, 0x40, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 583 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1048568, dstReg: RegV30}, exp: []byte{0xdb, 0xe3, 0x43, 0x91, 0x7e, 0xff, 0x7f, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 584 {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=RegR8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcReg2: RegR8, dstReg: RegV30}, exp: []byte{0xde, 0x6b, 0x68, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 585 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: -1, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x5f, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 586 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 0, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x40, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 587 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x1", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x40, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 588 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x2", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 2, dstReg: RegV30}, exp: []byte{0xbe, 0x20, 0x40, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 589 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: -2, dstReg: RegV30}, exp: []byte{0xbe, 0xe0, 0x5f, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 590 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xf", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 15, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x40, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 591 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: -15, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x5f, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 592 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x10", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 16, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x40, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 593 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xf", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 15, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x40, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 594 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x11", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 17, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x41, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 595 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: -128, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x58, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 596 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: -256, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x50, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 597 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x50", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 80, dstReg: RegV30}, exp: []byte{0xbe, 0x50, 0x40, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 598 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: -128, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x58, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 599 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xff", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 255, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x4f, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 600 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x1000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 4096, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x50, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 601 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x2000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 8192, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x60, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 602 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 32760, dstReg: RegV30}, exp: []byte{0xbb, 0x10, 0x40, 0x91, 0x7e, 0xfb, 0x7f, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 603 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xfff0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 65520, dstReg: RegV30}, exp: []byte{0xbb, 0x30, 0x40, 0x91, 0x7e, 0xf3, 0x7f, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 604 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffe8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 65512, dstReg: RegV30}, exp: []byte{0xbb, 0x30, 0x40, 0x91, 0x7e, 0xeb, 0x7f, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 605 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffe0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 65504, dstReg: RegV30}, exp: []byte{0xbb, 0x30, 0x40, 0x91, 0x7e, 0xe3, 0x7f, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 606 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x8000000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 134217728, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 607 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x40000000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1073741824, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 608 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x40000008", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1073741832, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 609 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1073741816, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 610 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x40000010", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1073741840, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 611 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1073741808, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 612 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 2147483640, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 613 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x10000004", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 268435460, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 614 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x100008", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1048584, dstReg: RegV30}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x7e, 0xb, 0x40, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 615 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1048568, dstReg: RegV30}, exp: []byte{0xbb, 0xf0, 0x43, 0x91, 0x7e, 0xfb, 0x7f, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 616 {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=RegR8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcReg2: RegR8, dstReg: RegV30}, exp: []byte{0xbe, 0x68, 0x68, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 617 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: -1, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x5f, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 618 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 0, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x40, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 619 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x1", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x40, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 620 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x2", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 2, dstReg: RegV30}, exp: []byte{0xde, 0x23, 0x40, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 621 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: -2, dstReg: RegV30}, exp: []byte{0xde, 0xe3, 0x5f, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 622 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 15, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x40, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 623 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: -15, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x5f, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 624 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x10", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 16, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x40, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 625 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 15, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x40, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 626 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x11", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 17, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x41, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 627 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: -128, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x58, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 628 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: -256, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x50, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 629 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x50", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 80, dstReg: RegV30}, exp: []byte{0xde, 0x53, 0x40, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 630 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: -128, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x58, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 631 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xff", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 255, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x4f, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 632 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x1000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 4096, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x50, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 633 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x2000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 8192, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x60, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 634 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 32760, dstReg: RegV30}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x7e, 0xfb, 0x7f, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 635 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 65520, dstReg: RegV30}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xf3, 0x7f, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 636 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 65512, dstReg: RegV30}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xeb, 0x7f, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 637 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 65504, dstReg: RegV30}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xe3, 0x7f, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 638 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 134217728, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 639 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1073741824, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 640 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1073741832, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 641 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1073741816, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 642 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1073741840, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 643 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1073741808, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 644 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 2147483640, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 645 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 268435460, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 646 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x100008", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1048584, dstReg: RegV30}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x7e, 0xb, 0x40, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 647 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1048568, dstReg: RegV30}, exp: []byte{0xdb, 0xf3, 0x43, 0x91, 0x7e, 0xfb, 0x7f, 0xbd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 648 {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=RegR8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcReg2: RegR8, dstReg: RegV30}, exp: []byte{0xde, 0x6b, 0x68, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 649 } 650 651 for _, tc := range tests { 652 t.Run(tc.name, func(t *testing.T) { 653 a := NewAssembler(RegR27) 654 err := a.encodeMemoryToRegister(tc.n) 655 require.NoError(t, err) 656 657 actual, err := a.Assemble() 658 require.NoError(t, err) 659 require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) 660 }) 661 } 662 } 663 664 func TestAssemblerImpl_encodeReadInstructionAddress(t *testing.T) { 665 t.Run("ok", func(t *testing.T) { 666 tests := []struct { 667 name string 668 numDummyInstructions int 669 expADRInstructionBytes []byte 670 }{ 671 { 672 name: "< 8-bit offset", 673 numDummyInstructions: 1, 674 expADRInstructionBytes: []byte{0x77, 0x0, 0x0, 0x10}, 675 }, 676 { 677 name: "> 8-bit offset", 678 numDummyInstructions: 5000, 679 expADRInstructionBytes: []byte{0x57, 0x71, 0x2, 0x10}, 680 }, 681 } 682 683 for _, tc := range tests { 684 tc := tc 685 t.Run(tc.name, func(t *testing.T) { 686 const targetBeforeInstruction, dstReg = RET, RegR23 687 a := NewAssembler(asm.NilRegister) 688 689 a.CompileReadInstructionAddress(dstReg, targetBeforeInstruction) 690 adrInst := a.Current 691 for i := 0; i < tc.numDummyInstructions; i++ { 692 a.CompileJumpToRegister(B, RegR5) 693 } 694 a.CompileJumpToRegister(targetBeforeInstruction, RegR25) 695 a.CompileConstToRegister(MOVD, 0x3e8, RegR10) // Target. 696 target := a.Current 697 698 actual, err := a.Assemble() 699 require.NoError(t, err) 700 // The binary should start with ADR instruction. 701 require.Equal(t, tc.expADRInstructionBytes, actual[:4], hex.EncodeToString(actual)) 702 // Then, follow the dummy B instructions. 703 pos := 4 704 for i := 0; i < tc.numDummyInstructions; i++ { 705 require.Equal(t, 706 // A0 00 1F D6 br x5 707 []byte{0xa0, 0x0, 0x1f, 0xd6}, 708 actual[pos:pos+4], hex.EncodeToString(actual)) 709 pos += 4 710 } 711 // And targetBeforeInstruction follows: "20 03 5F D6 ret x25" 712 require.Equal(t, []byte{0x20, 0x03, 0x5F, 0xd6}, 713 actual[pos:pos+4], hex.EncodeToString(actual)) 714 715 // After that, we end with the target instruction "movz x10, #0x3e8" 716 pos += 4 717 require.Equal(t, []byte{0xa, 0x7d, 0x80, 0xd2}, 718 actual[pos:pos+4], hex.EncodeToString(actual)) 719 fmt.Println(hex.EncodeToString(actual)) 720 721 require.Equal(t, uint64(4+tc.numDummyInstructions*4+4), 722 target.offsetInBinaryField-adrInst.offsetInBinaryField) 723 }) 724 } 725 }) 726 727 t.Run("not found", func(t *testing.T) { 728 a := NewAssembler(asm.NilRegister) 729 a.CompileReadInstructionAddress(RegR27, NOP) 730 a.CompileConstToRegister(MOVD, 1000, RegR10) 731 _, err := a.Assemble() 732 require.EqualError(t, err, "BUG: target instruction NOP not found for ADR") 733 }) 734 t.Run("offset too large", func(t *testing.T) { 735 for _, offset := range []int64{ 736 1 << 20, 737 -(1 << 20) - 1, 738 math.MaxInt64, math.MinInt64, 739 } { 740 u64 := uint64(offset) 741 t.Run(fmt.Sprintf("offset=%#b", u64), func(t *testing.T) { 742 a := NewAssembler(asm.NilRegister) 743 a.CompileReadInstructionAddress(RegR27, RET) 744 a.CompileJumpToRegister(RET, RegR25) 745 a.CompileConstToRegister(MOVD, 1000, RegR10) 746 747 for n := a.Root; n != nil; n = n.next { 748 n.offsetInBinaryField = uint64(a.Buf.Len()) 749 750 err := a.encodeNode(n) 751 require.NoError(t, err) 752 } 753 754 require.Equal(t, 1, len(a.OnGenerateCallbacks)) 755 cb := a.OnGenerateCallbacks[0] 756 757 targetNode := a.Current 758 targetNode.offsetInBinaryField = u64 759 760 err := cb(nil) 761 require.EqualError(t, err, fmt.Sprintf("BUG: too large offset for ADR: %#x", u64)) 762 }) 763 } 764 }) 765 }